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1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
33#include "debug.h"
34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
97 int retries = 10000;
98 u32 reg;
99
100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
131 /* wait for a change in DSTS */
132 retries = 10000;
133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
139 udelay(5);
140 }
141
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
144
145 return -ETIMEDOUT;
146}
147
148/**
149 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
150 * @dwc: pointer to our context structure
151 *
152 * This function will a best effort FIFO allocation in order
153 * to improve FIFO usage and throughput, while still allowing
154 * us to enable as many endpoints as possible.
155 *
156 * Keep in mind that this operation will be highly dependent
157 * on the configured size for RAM1 - which contains TxFifo -,
158 * the amount of endpoints enabled on coreConsultant tool, and
159 * the width of the Master Bus.
160 *
161 * In the ideal world, we would always be able to satisfy the
162 * following equation:
163 *
164 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
165 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
166 *
167 * Unfortunately, due to many variables that's not always the case.
168 */
169int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
170{
171 int last_fifo_depth = 0;
172 int ram1_depth;
173 int fifo_size;
174 int mdwidth;
175 int num;
176
177 if (!dwc->needs_fifo_resize)
178 return 0;
179
180 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
181 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
182
183 /* MDWIDTH is represented in bits, we need it in bytes */
184 mdwidth >>= 3;
185
186 /*
187 * FIXME For now we will only allocate 1 wMaxPacketSize space
188 * for each enabled endpoint, later patches will come to
189 * improve this algorithm so that we better use the internal
190 * FIFO space
191 */
192 for (num = 0; num < dwc->num_in_eps; num++) {
193 /* bit0 indicates direction; 1 means IN ep */
194 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
195 int mult = 1;
196 int tmp;
197
198 if (!(dep->flags & DWC3_EP_ENABLED))
199 continue;
200
201 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
202 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
203 mult = 3;
204
205 /*
206 * REVISIT: the following assumes we will always have enough
207 * space available on the FIFO RAM for all possible use cases.
208 * Make sure that's true somehow and change FIFO allocation
209 * accordingly.
210 *
211 * If we have Bulk or Isochronous endpoints, we want
212 * them to be able to be very, very fast. So we're giving
213 * those endpoints a fifo_size which is enough for 3 full
214 * packets
215 */
216 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
217 tmp += mdwidth;
218
219 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
220
221 fifo_size |= (last_fifo_depth << 16);
222
223 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
224 dep->name, last_fifo_depth, fifo_size & 0xffff);
225
226 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
227
228 last_fifo_depth += (fifo_size & 0xffff);
229 }
230
231 return 0;
232}
233
234void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
235 int status)
236{
237 struct dwc3 *dwc = dep->dwc;
238 int i;
239
240 if (req->queued) {
241 i = 0;
242 do {
243 dep->busy_slot++;
244 /*
245 * Skip LINK TRB. We can't use req->trb and check for
246 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
247 * just completed (not the LINK TRB).
248 */
249 if (((dep->busy_slot & DWC3_TRB_MASK) ==
250 DWC3_TRB_NUM- 1) &&
251 usb_endpoint_xfer_isoc(dep->endpoint.desc))
252 dep->busy_slot++;
253 } while(++i < req->request.num_mapped_sgs);
254 req->queued = false;
255 }
256 list_del(&req->list);
257 req->trb = NULL;
258
259 if (req->request.status == -EINPROGRESS)
260 req->request.status = status;
261
262 if (dwc->ep0_bounced && dep->number == 0)
263 dwc->ep0_bounced = false;
264 else
265 usb_gadget_unmap_request(&dwc->gadget, &req->request,
266 req->direction);
267
268 trace_dwc3_gadget_giveback(req);
269
270 spin_unlock(&dwc->lock);
271 usb_gadget_giveback_request(&dep->endpoint, &req->request);
272 spin_lock(&dwc->lock);
273}
274
275int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
276{
277 u32 timeout = 500;
278 u32 reg;
279
280 trace_dwc3_gadget_generic_cmd(cmd, param);
281
282 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
283 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
284
285 do {
286 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
287 if (!(reg & DWC3_DGCMD_CMDACT)) {
288 dwc3_trace(trace_dwc3_gadget,
289 "Command Complete --> %d",
290 DWC3_DGCMD_STATUS(reg));
291 if (DWC3_DGCMD_STATUS(reg))
292 return -EINVAL;
293 return 0;
294 }
295
296 /*
297 * We can't sleep here, because it's also called from
298 * interrupt context.
299 */
300 timeout--;
301 if (!timeout) {
302 dwc3_trace(trace_dwc3_gadget,
303 "Command Timed Out");
304 return -ETIMEDOUT;
305 }
306 udelay(1);
307 } while (1);
308}
309
310int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
311 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
312{
313 struct dwc3_ep *dep = dwc->eps[ep];
314 u32 timeout = 500;
315 u32 reg;
316
317 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
318
319 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
320 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
321 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
322
323 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
324 do {
325 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
326 if (!(reg & DWC3_DEPCMD_CMDACT)) {
327 dwc3_trace(trace_dwc3_gadget,
328 "Command Complete --> %d",
329 DWC3_DEPCMD_STATUS(reg));
330 if (DWC3_DEPCMD_STATUS(reg))
331 return -EINVAL;
332 return 0;
333 }
334
335 /*
336 * We can't sleep here, because it is also called from
337 * interrupt context.
338 */
339 timeout--;
340 if (!timeout) {
341 dwc3_trace(trace_dwc3_gadget,
342 "Command Timed Out");
343 return -ETIMEDOUT;
344 }
345
346 udelay(1);
347 } while (1);
348}
349
350static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
351 struct dwc3_trb *trb)
352{
353 u32 offset = (char *) trb - (char *) dep->trb_pool;
354
355 return dep->trb_pool_dma + offset;
356}
357
358static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
359{
360 struct dwc3 *dwc = dep->dwc;
361
362 if (dep->trb_pool)
363 return 0;
364
365 dep->trb_pool = dma_alloc_coherent(dwc->dev,
366 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
367 &dep->trb_pool_dma, GFP_KERNEL);
368 if (!dep->trb_pool) {
369 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
370 dep->name);
371 return -ENOMEM;
372 }
373
374 return 0;
375}
376
377static void dwc3_free_trb_pool(struct dwc3_ep *dep)
378{
379 struct dwc3 *dwc = dep->dwc;
380
381 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
382 dep->trb_pool, dep->trb_pool_dma);
383
384 dep->trb_pool = NULL;
385 dep->trb_pool_dma = 0;
386}
387
388static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
389
390/**
391 * dwc3_gadget_start_config - Configure EP resources
392 * @dwc: pointer to our controller context structure
393 * @dep: endpoint that is being enabled
394 *
395 * The assignment of transfer resources cannot perfectly follow the
396 * data book due to the fact that the controller driver does not have
397 * all knowledge of the configuration in advance. It is given this
398 * information piecemeal by the composite gadget framework after every
399 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
400 * programming model in this scenario can cause errors. For two
401 * reasons:
402 *
403 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
404 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
405 * multiple interfaces.
406 *
407 * 2) The databook does not mention doing more DEPXFERCFG for new
408 * endpoint on alt setting (8.1.6).
409 *
410 * The following simplified method is used instead:
411 *
412 * All hardware endpoints can be assigned a transfer resource and this
413 * setting will stay persistent until either a core reset or
414 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
415 * do DEPXFERCFG for every hardware endpoint as well. We are
416 * guaranteed that there are as many transfer resources as endpoints.
417 *
418 * This function is called for each endpoint when it is being enabled
419 * but is triggered only when called for EP0-out, which always happens
420 * first, and which should only happen in one of the above conditions.
421 */
422static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
423{
424 struct dwc3_gadget_ep_cmd_params params;
425 u32 cmd;
426 int i;
427 int ret;
428
429 if (dep->number)
430 return 0;
431
432 memset(¶ms, 0x00, sizeof(params));
433 cmd = DWC3_DEPCMD_DEPSTARTCFG;
434
435 ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
436 if (ret)
437 return ret;
438
439 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
440 struct dwc3_ep *dep = dwc->eps[i];
441
442 if (!dep)
443 continue;
444
445 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
446 if (ret)
447 return ret;
448 }
449
450 return 0;
451}
452
453static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
454 const struct usb_endpoint_descriptor *desc,
455 const struct usb_ss_ep_comp_descriptor *comp_desc,
456 bool ignore, bool restore)
457{
458 struct dwc3_gadget_ep_cmd_params params;
459
460 memset(¶ms, 0x00, sizeof(params));
461
462 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
463 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
464
465 /* Burst size is only needed in SuperSpeed mode */
466 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
467 u32 burst = dep->endpoint.maxburst - 1;
468
469 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
470 }
471
472 if (ignore)
473 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
474
475 if (restore) {
476 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
477 params.param2 |= dep->saved_state;
478 }
479
480 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
481 | DWC3_DEPCFG_XFER_NOT_READY_EN;
482
483 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
484 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
485 | DWC3_DEPCFG_STREAM_EVENT_EN;
486 dep->stream_capable = true;
487 }
488
489 if (!usb_endpoint_xfer_control(desc))
490 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
491
492 /*
493 * We are doing 1:1 mapping for endpoints, meaning
494 * Physical Endpoints 2 maps to Logical Endpoint 2 and
495 * so on. We consider the direction bit as part of the physical
496 * endpoint number. So USB endpoint 0x81 is 0x03.
497 */
498 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
499
500 /*
501 * We must use the lower 16 TX FIFOs even though
502 * HW might have more
503 */
504 if (dep->direction)
505 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
506
507 if (desc->bInterval) {
508 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
509 dep->interval = 1 << (desc->bInterval - 1);
510 }
511
512 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
513 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
514}
515
516static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
517{
518 struct dwc3_gadget_ep_cmd_params params;
519
520 memset(¶ms, 0x00, sizeof(params));
521
522 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
523
524 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
525 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
526}
527
528/**
529 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
530 * @dep: endpoint to be initialized
531 * @desc: USB Endpoint Descriptor
532 *
533 * Caller should take care of locking
534 */
535static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
536 const struct usb_endpoint_descriptor *desc,
537 const struct usb_ss_ep_comp_descriptor *comp_desc,
538 bool ignore, bool restore)
539{
540 struct dwc3 *dwc = dep->dwc;
541 u32 reg;
542 int ret;
543
544 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
545
546 if (!(dep->flags & DWC3_EP_ENABLED)) {
547 ret = dwc3_gadget_start_config(dwc, dep);
548 if (ret)
549 return ret;
550 }
551
552 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
553 restore);
554 if (ret)
555 return ret;
556
557 if (!(dep->flags & DWC3_EP_ENABLED)) {
558 struct dwc3_trb *trb_st_hw;
559 struct dwc3_trb *trb_link;
560
561 dep->endpoint.desc = desc;
562 dep->comp_desc = comp_desc;
563 dep->type = usb_endpoint_type(desc);
564 dep->flags |= DWC3_EP_ENABLED;
565
566 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
567 reg |= DWC3_DALEPENA_EP(dep->number);
568 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
569
570 if (!usb_endpoint_xfer_isoc(desc))
571 goto out;
572
573 /* Link TRB for ISOC. The HWO bit is never reset */
574 trb_st_hw = &dep->trb_pool[0];
575
576 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
577 memset(trb_link, 0, sizeof(*trb_link));
578
579 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
580 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
581 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
582 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
583 }
584
585out:
586 switch (usb_endpoint_type(desc)) {
587 case USB_ENDPOINT_XFER_CONTROL:
588 /* don't change name */
589 break;
590 case USB_ENDPOINT_XFER_ISOC:
591 strlcat(dep->name, "-isoc", sizeof(dep->name));
592 break;
593 case USB_ENDPOINT_XFER_BULK:
594 strlcat(dep->name, "-bulk", sizeof(dep->name));
595 break;
596 case USB_ENDPOINT_XFER_INT:
597 strlcat(dep->name, "-int", sizeof(dep->name));
598 break;
599 default:
600 dev_err(dwc->dev, "invalid endpoint transfer type\n");
601 }
602
603 return 0;
604}
605
606static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
607static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
608{
609 struct dwc3_request *req;
610
611 if (!list_empty(&dep->req_queued)) {
612 dwc3_stop_active_transfer(dwc, dep->number, true);
613
614 /* - giveback all requests to gadget driver */
615 while (!list_empty(&dep->req_queued)) {
616 req = next_request(&dep->req_queued);
617
618 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
619 }
620 }
621
622 while (!list_empty(&dep->request_list)) {
623 req = next_request(&dep->request_list);
624
625 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
626 }
627}
628
629/**
630 * __dwc3_gadget_ep_disable - Disables a HW endpoint
631 * @dep: the endpoint to disable
632 *
633 * This function also removes requests which are currently processed ny the
634 * hardware and those which are not yet scheduled.
635 * Caller should take care of locking.
636 */
637static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
638{
639 struct dwc3 *dwc = dep->dwc;
640 u32 reg;
641
642 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
643
644 dwc3_remove_requests(dwc, dep);
645
646 /* make sure HW endpoint isn't stalled */
647 if (dep->flags & DWC3_EP_STALL)
648 __dwc3_gadget_ep_set_halt(dep, 0, false);
649
650 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
651 reg &= ~DWC3_DALEPENA_EP(dep->number);
652 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
653
654 dep->stream_capable = false;
655 dep->endpoint.desc = NULL;
656 dep->comp_desc = NULL;
657 dep->type = 0;
658 dep->flags = 0;
659
660 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
661 dep->number >> 1,
662 (dep->number & 1) ? "in" : "out");
663
664 return 0;
665}
666
667/* -------------------------------------------------------------------------- */
668
669static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
670 const struct usb_endpoint_descriptor *desc)
671{
672 return -EINVAL;
673}
674
675static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
676{
677 return -EINVAL;
678}
679
680/* -------------------------------------------------------------------------- */
681
682static int dwc3_gadget_ep_enable(struct usb_ep *ep,
683 const struct usb_endpoint_descriptor *desc)
684{
685 struct dwc3_ep *dep;
686 struct dwc3 *dwc;
687 unsigned long flags;
688 int ret;
689
690 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
691 pr_debug("dwc3: invalid parameters\n");
692 return -EINVAL;
693 }
694
695 if (!desc->wMaxPacketSize) {
696 pr_debug("dwc3: missing wMaxPacketSize\n");
697 return -EINVAL;
698 }
699
700 dep = to_dwc3_ep(ep);
701 dwc = dep->dwc;
702
703 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
704 "%s is already enabled\n",
705 dep->name))
706 return 0;
707
708 spin_lock_irqsave(&dwc->lock, flags);
709 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
710 spin_unlock_irqrestore(&dwc->lock, flags);
711
712 return ret;
713}
714
715static int dwc3_gadget_ep_disable(struct usb_ep *ep)
716{
717 struct dwc3_ep *dep;
718 struct dwc3 *dwc;
719 unsigned long flags;
720 int ret;
721
722 if (!ep) {
723 pr_debug("dwc3: invalid parameters\n");
724 return -EINVAL;
725 }
726
727 dep = to_dwc3_ep(ep);
728 dwc = dep->dwc;
729
730 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
731 "%s is already disabled\n",
732 dep->name))
733 return 0;
734
735 spin_lock_irqsave(&dwc->lock, flags);
736 ret = __dwc3_gadget_ep_disable(dep);
737 spin_unlock_irqrestore(&dwc->lock, flags);
738
739 return ret;
740}
741
742static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
743 gfp_t gfp_flags)
744{
745 struct dwc3_request *req;
746 struct dwc3_ep *dep = to_dwc3_ep(ep);
747
748 req = kzalloc(sizeof(*req), gfp_flags);
749 if (!req)
750 return NULL;
751
752 req->epnum = dep->number;
753 req->dep = dep;
754
755 trace_dwc3_alloc_request(req);
756
757 return &req->request;
758}
759
760static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
761 struct usb_request *request)
762{
763 struct dwc3_request *req = to_dwc3_request(request);
764
765 trace_dwc3_free_request(req);
766 kfree(req);
767}
768
769/**
770 * dwc3_prepare_one_trb - setup one TRB from one request
771 * @dep: endpoint for which this request is prepared
772 * @req: dwc3_request pointer
773 */
774static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
775 struct dwc3_request *req, dma_addr_t dma,
776 unsigned length, unsigned last, unsigned chain, unsigned node)
777{
778 struct dwc3_trb *trb;
779
780 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
781 dep->name, req, (unsigned long long) dma,
782 length, last ? " last" : "",
783 chain ? " chain" : "");
784
785
786 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
787
788 if (!req->trb) {
789 dwc3_gadget_move_request_queued(req);
790 req->trb = trb;
791 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
792 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
793 }
794
795 dep->free_slot++;
796 /* Skip the LINK-TRB on ISOC */
797 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
798 usb_endpoint_xfer_isoc(dep->endpoint.desc))
799 dep->free_slot++;
800
801 trb->size = DWC3_TRB_SIZE_LENGTH(length);
802 trb->bpl = lower_32_bits(dma);
803 trb->bph = upper_32_bits(dma);
804
805 switch (usb_endpoint_type(dep->endpoint.desc)) {
806 case USB_ENDPOINT_XFER_CONTROL:
807 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
808 break;
809
810 case USB_ENDPOINT_XFER_ISOC:
811 if (!node)
812 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
813 else
814 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
815 break;
816
817 case USB_ENDPOINT_XFER_BULK:
818 case USB_ENDPOINT_XFER_INT:
819 trb->ctrl = DWC3_TRBCTL_NORMAL;
820 break;
821 default:
822 /*
823 * This is only possible with faulty memory because we
824 * checked it already :)
825 */
826 BUG();
827 }
828
829 if (!req->request.no_interrupt && !chain)
830 trb->ctrl |= DWC3_TRB_CTRL_IOC;
831
832 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
833 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
834 trb->ctrl |= DWC3_TRB_CTRL_CSP;
835 } else if (last) {
836 trb->ctrl |= DWC3_TRB_CTRL_LST;
837 }
838
839 if (chain)
840 trb->ctrl |= DWC3_TRB_CTRL_CHN;
841
842 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
843 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
844
845 trb->ctrl |= DWC3_TRB_CTRL_HWO;
846
847 trace_dwc3_prepare_trb(dep, trb);
848}
849
850/*
851 * dwc3_prepare_trbs - setup TRBs from requests
852 * @dep: endpoint for which requests are being prepared
853 * @starting: true if the endpoint is idle and no requests are queued.
854 *
855 * The function goes through the requests list and sets up TRBs for the
856 * transfers. The function returns once there are no more TRBs available or
857 * it runs out of requests.
858 */
859static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
860{
861 struct dwc3_request *req, *n;
862 u32 trbs_left;
863 u32 max;
864 unsigned int last_one = 0;
865
866 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
867
868 /* the first request must not be queued */
869 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
870
871 /* Can't wrap around on a non-isoc EP since there's no link TRB */
872 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
873 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
874 if (trbs_left > max)
875 trbs_left = max;
876 }
877
878 /*
879 * If busy & slot are equal than it is either full or empty. If we are
880 * starting to process requests then we are empty. Otherwise we are
881 * full and don't do anything
882 */
883 if (!trbs_left) {
884 if (!starting)
885 return;
886 trbs_left = DWC3_TRB_NUM;
887 /*
888 * In case we start from scratch, we queue the ISOC requests
889 * starting from slot 1. This is done because we use ring
890 * buffer and have no LST bit to stop us. Instead, we place
891 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
892 * after the first request so we start at slot 1 and have
893 * 7 requests proceed before we hit the first IOC.
894 * Other transfer types don't use the ring buffer and are
895 * processed from the first TRB until the last one. Since we
896 * don't wrap around we have to start at the beginning.
897 */
898 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
899 dep->busy_slot = 1;
900 dep->free_slot = 1;
901 } else {
902 dep->busy_slot = 0;
903 dep->free_slot = 0;
904 }
905 }
906
907 /* The last TRB is a link TRB, not used for xfer */
908 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
909 return;
910
911 list_for_each_entry_safe(req, n, &dep->request_list, list) {
912 unsigned length;
913 dma_addr_t dma;
914 last_one = false;
915
916 if (req->request.num_mapped_sgs > 0) {
917 struct usb_request *request = &req->request;
918 struct scatterlist *sg = request->sg;
919 struct scatterlist *s;
920 int i;
921
922 for_each_sg(sg, s, request->num_mapped_sgs, i) {
923 unsigned chain = true;
924
925 length = sg_dma_len(s);
926 dma = sg_dma_address(s);
927
928 if (i == (request->num_mapped_sgs - 1) ||
929 sg_is_last(s)) {
930 if (list_empty(&dep->request_list))
931 last_one = true;
932 chain = false;
933 }
934
935 trbs_left--;
936 if (!trbs_left)
937 last_one = true;
938
939 if (last_one)
940 chain = false;
941
942 dwc3_prepare_one_trb(dep, req, dma, length,
943 last_one, chain, i);
944
945 if (last_one)
946 break;
947 }
948
949 if (last_one)
950 break;
951 } else {
952 dma = req->request.dma;
953 length = req->request.length;
954 trbs_left--;
955
956 if (!trbs_left)
957 last_one = 1;
958
959 /* Is this the last request? */
960 if (list_is_last(&req->list, &dep->request_list))
961 last_one = 1;
962
963 dwc3_prepare_one_trb(dep, req, dma, length,
964 last_one, false, 0);
965
966 if (last_one)
967 break;
968 }
969 }
970}
971
972static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
973 int start_new)
974{
975 struct dwc3_gadget_ep_cmd_params params;
976 struct dwc3_request *req;
977 struct dwc3 *dwc = dep->dwc;
978 int ret;
979 u32 cmd;
980
981 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
982 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
983 return -EBUSY;
984 }
985
986 /*
987 * If we are getting here after a short-out-packet we don't enqueue any
988 * new requests as we try to set the IOC bit only on the last request.
989 */
990 if (start_new) {
991 if (list_empty(&dep->req_queued))
992 dwc3_prepare_trbs(dep, start_new);
993
994 /* req points to the first request which will be sent */
995 req = next_request(&dep->req_queued);
996 } else {
997 dwc3_prepare_trbs(dep, start_new);
998
999 /*
1000 * req points to the first request where HWO changed from 0 to 1
1001 */
1002 req = next_request(&dep->req_queued);
1003 }
1004 if (!req) {
1005 dep->flags |= DWC3_EP_PENDING_REQUEST;
1006 return 0;
1007 }
1008
1009 memset(¶ms, 0, sizeof(params));
1010
1011 if (start_new) {
1012 params.param0 = upper_32_bits(req->trb_dma);
1013 params.param1 = lower_32_bits(req->trb_dma);
1014 cmd = DWC3_DEPCMD_STARTTRANSFER;
1015 } else {
1016 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1017 }
1018
1019 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1020 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1021 if (ret < 0) {
1022 /*
1023 * FIXME we need to iterate over the list of requests
1024 * here and stop, unmap, free and del each of the linked
1025 * requests instead of what we do now.
1026 */
1027 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1028 req->direction);
1029 list_del(&req->list);
1030 return ret;
1031 }
1032
1033 dep->flags |= DWC3_EP_BUSY;
1034
1035 if (start_new) {
1036 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1037 dep->number);
1038 WARN_ON_ONCE(!dep->resource_index);
1039 }
1040
1041 return 0;
1042}
1043
1044static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1045 struct dwc3_ep *dep, u32 cur_uf)
1046{
1047 u32 uf;
1048
1049 if (list_empty(&dep->request_list)) {
1050 dwc3_trace(trace_dwc3_gadget,
1051 "ISOC ep %s run out for requests",
1052 dep->name);
1053 dep->flags |= DWC3_EP_PENDING_REQUEST;
1054 return;
1055 }
1056
1057 /* 4 micro frames in the future */
1058 uf = cur_uf + dep->interval * 4;
1059
1060 __dwc3_gadget_kick_transfer(dep, uf, 1);
1061}
1062
1063static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1064 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1065{
1066 u32 cur_uf, mask;
1067
1068 mask = ~(dep->interval - 1);
1069 cur_uf = event->parameters & mask;
1070
1071 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1072}
1073
1074static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1075{
1076 struct dwc3 *dwc = dep->dwc;
1077 int ret;
1078
1079 if (!dep->endpoint.desc) {
1080 dwc3_trace(trace_dwc3_gadget,
1081 "trying to queue request %p to disabled %s\n",
1082 &req->request, dep->endpoint.name);
1083 return -ESHUTDOWN;
1084 }
1085
1086 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1087 &req->request, req->dep->name)) {
1088 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1089 &req->request, req->dep->name);
1090 return -EINVAL;
1091 }
1092
1093 req->request.actual = 0;
1094 req->request.status = -EINPROGRESS;
1095 req->direction = dep->direction;
1096 req->epnum = dep->number;
1097
1098 trace_dwc3_ep_queue(req);
1099
1100 /*
1101 * We only add to our list of requests now and
1102 * start consuming the list once we get XferNotReady
1103 * IRQ.
1104 *
1105 * That way, we avoid doing anything that we don't need
1106 * to do now and defer it until the point we receive a
1107 * particular token from the Host side.
1108 *
1109 * This will also avoid Host cancelling URBs due to too
1110 * many NAKs.
1111 */
1112 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1113 dep->direction);
1114 if (ret)
1115 return ret;
1116
1117 list_add_tail(&req->list, &dep->request_list);
1118
1119 /*
1120 * If there are no pending requests and the endpoint isn't already
1121 * busy, we will just start the request straight away.
1122 *
1123 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1124 * little bit faster.
1125 */
1126 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1127 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1128 !(dep->flags & DWC3_EP_BUSY)) {
1129 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1130 goto out;
1131 }
1132
1133 /*
1134 * There are a few special cases:
1135 *
1136 * 1. XferNotReady with empty list of requests. We need to kick the
1137 * transfer here in that situation, otherwise we will be NAKing
1138 * forever. If we get XferNotReady before gadget driver has a
1139 * chance to queue a request, we will ACK the IRQ but won't be
1140 * able to receive the data until the next request is queued.
1141 * The following code is handling exactly that.
1142 *
1143 */
1144 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1145 /*
1146 * If xfernotready is already elapsed and it is a case
1147 * of isoc transfer, then issue END TRANSFER, so that
1148 * you can receive xfernotready again and can have
1149 * notion of current microframe.
1150 */
1151 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1152 if (list_empty(&dep->req_queued)) {
1153 dwc3_stop_active_transfer(dwc, dep->number, true);
1154 dep->flags = DWC3_EP_ENABLED;
1155 }
1156 return 0;
1157 }
1158
1159 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1160 if (!ret)
1161 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1162
1163 goto out;
1164 }
1165
1166 /*
1167 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1168 * kick the transfer here after queuing a request, otherwise the
1169 * core may not see the modified TRB(s).
1170 */
1171 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1172 (dep->flags & DWC3_EP_BUSY) &&
1173 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1174 WARN_ON_ONCE(!dep->resource_index);
1175 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1176 false);
1177 goto out;
1178 }
1179
1180 /*
1181 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1182 * right away, otherwise host will not know we have streams to be
1183 * handled.
1184 */
1185 if (dep->stream_capable)
1186 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1187
1188out:
1189 if (ret && ret != -EBUSY)
1190 dwc3_trace(trace_dwc3_gadget,
1191 "%s: failed to kick transfers\n",
1192 dep->name);
1193 if (ret == -EBUSY)
1194 ret = 0;
1195
1196 return ret;
1197}
1198
1199static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1200 struct usb_request *request)
1201{
1202 dwc3_gadget_ep_free_request(ep, request);
1203}
1204
1205static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1206{
1207 struct dwc3_request *req;
1208 struct usb_request *request;
1209 struct usb_ep *ep = &dep->endpoint;
1210
1211 dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1212 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1213 if (!request)
1214 return -ENOMEM;
1215
1216 request->length = 0;
1217 request->buf = dwc->zlp_buf;
1218 request->complete = __dwc3_gadget_ep_zlp_complete;
1219
1220 req = to_dwc3_request(request);
1221
1222 return __dwc3_gadget_ep_queue(dep, req);
1223}
1224
1225static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1226 gfp_t gfp_flags)
1227{
1228 struct dwc3_request *req = to_dwc3_request(request);
1229 struct dwc3_ep *dep = to_dwc3_ep(ep);
1230 struct dwc3 *dwc = dep->dwc;
1231
1232 unsigned long flags;
1233
1234 int ret;
1235
1236 spin_lock_irqsave(&dwc->lock, flags);
1237 ret = __dwc3_gadget_ep_queue(dep, req);
1238
1239 /*
1240 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1241 * setting request->zero, instead of doing magic, we will just queue an
1242 * extra usb_request ourselves so that it gets handled the same way as
1243 * any other request.
1244 */
1245 if (ret == 0 && request->zero && request->length &&
1246 (request->length % ep->maxpacket == 0))
1247 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1248
1249 spin_unlock_irqrestore(&dwc->lock, flags);
1250
1251 return ret;
1252}
1253
1254static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1255 struct usb_request *request)
1256{
1257 struct dwc3_request *req = to_dwc3_request(request);
1258 struct dwc3_request *r = NULL;
1259
1260 struct dwc3_ep *dep = to_dwc3_ep(ep);
1261 struct dwc3 *dwc = dep->dwc;
1262
1263 unsigned long flags;
1264 int ret = 0;
1265
1266 trace_dwc3_ep_dequeue(req);
1267
1268 spin_lock_irqsave(&dwc->lock, flags);
1269
1270 list_for_each_entry(r, &dep->request_list, list) {
1271 if (r == req)
1272 break;
1273 }
1274
1275 if (r != req) {
1276 list_for_each_entry(r, &dep->req_queued, list) {
1277 if (r == req)
1278 break;
1279 }
1280 if (r == req) {
1281 /* wait until it is processed */
1282 dwc3_stop_active_transfer(dwc, dep->number, true);
1283 goto out1;
1284 }
1285 dev_err(dwc->dev, "request %p was not queued to %s\n",
1286 request, ep->name);
1287 ret = -EINVAL;
1288 goto out0;
1289 }
1290
1291out1:
1292 /* giveback the request */
1293 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1294
1295out0:
1296 spin_unlock_irqrestore(&dwc->lock, flags);
1297
1298 return ret;
1299}
1300
1301int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1302{
1303 struct dwc3_gadget_ep_cmd_params params;
1304 struct dwc3 *dwc = dep->dwc;
1305 int ret;
1306
1307 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1308 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1309 return -EINVAL;
1310 }
1311
1312 memset(¶ms, 0x00, sizeof(params));
1313
1314 if (value) {
1315 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1316 (!list_empty(&dep->req_queued) ||
1317 !list_empty(&dep->request_list)))) {
1318 dwc3_trace(trace_dwc3_gadget,
1319 "%s: pending request, cannot halt\n",
1320 dep->name);
1321 return -EAGAIN;
1322 }
1323
1324 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1325 DWC3_DEPCMD_SETSTALL, ¶ms);
1326 if (ret)
1327 dev_err(dwc->dev, "failed to set STALL on %s\n",
1328 dep->name);
1329 else
1330 dep->flags |= DWC3_EP_STALL;
1331 } else {
1332 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1333 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1334 if (ret)
1335 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1336 dep->name);
1337 else
1338 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1339 }
1340
1341 return ret;
1342}
1343
1344static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1345{
1346 struct dwc3_ep *dep = to_dwc3_ep(ep);
1347 struct dwc3 *dwc = dep->dwc;
1348
1349 unsigned long flags;
1350
1351 int ret;
1352
1353 spin_lock_irqsave(&dwc->lock, flags);
1354 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1355 spin_unlock_irqrestore(&dwc->lock, flags);
1356
1357 return ret;
1358}
1359
1360static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1361{
1362 struct dwc3_ep *dep = to_dwc3_ep(ep);
1363 struct dwc3 *dwc = dep->dwc;
1364 unsigned long flags;
1365 int ret;
1366
1367 spin_lock_irqsave(&dwc->lock, flags);
1368 dep->flags |= DWC3_EP_WEDGE;
1369
1370 if (dep->number == 0 || dep->number == 1)
1371 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1372 else
1373 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1374 spin_unlock_irqrestore(&dwc->lock, flags);
1375
1376 return ret;
1377}
1378
1379/* -------------------------------------------------------------------------- */
1380
1381static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1382 .bLength = USB_DT_ENDPOINT_SIZE,
1383 .bDescriptorType = USB_DT_ENDPOINT,
1384 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1385};
1386
1387static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1388 .enable = dwc3_gadget_ep0_enable,
1389 .disable = dwc3_gadget_ep0_disable,
1390 .alloc_request = dwc3_gadget_ep_alloc_request,
1391 .free_request = dwc3_gadget_ep_free_request,
1392 .queue = dwc3_gadget_ep0_queue,
1393 .dequeue = dwc3_gadget_ep_dequeue,
1394 .set_halt = dwc3_gadget_ep0_set_halt,
1395 .set_wedge = dwc3_gadget_ep_set_wedge,
1396};
1397
1398static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1399 .enable = dwc3_gadget_ep_enable,
1400 .disable = dwc3_gadget_ep_disable,
1401 .alloc_request = dwc3_gadget_ep_alloc_request,
1402 .free_request = dwc3_gadget_ep_free_request,
1403 .queue = dwc3_gadget_ep_queue,
1404 .dequeue = dwc3_gadget_ep_dequeue,
1405 .set_halt = dwc3_gadget_ep_set_halt,
1406 .set_wedge = dwc3_gadget_ep_set_wedge,
1407};
1408
1409/* -------------------------------------------------------------------------- */
1410
1411static int dwc3_gadget_get_frame(struct usb_gadget *g)
1412{
1413 struct dwc3 *dwc = gadget_to_dwc(g);
1414 u32 reg;
1415
1416 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1417 return DWC3_DSTS_SOFFN(reg);
1418}
1419
1420static int dwc3_gadget_wakeup(struct usb_gadget *g)
1421{
1422 struct dwc3 *dwc = gadget_to_dwc(g);
1423
1424 unsigned long timeout;
1425 unsigned long flags;
1426
1427 u32 reg;
1428
1429 int ret = 0;
1430
1431 u8 link_state;
1432 u8 speed;
1433
1434 spin_lock_irqsave(&dwc->lock, flags);
1435
1436 /*
1437 * According to the Databook Remote wakeup request should
1438 * be issued only when the device is in early suspend state.
1439 *
1440 * We can check that via USB Link State bits in DSTS register.
1441 */
1442 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1443
1444 speed = reg & DWC3_DSTS_CONNECTSPD;
1445 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1446 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1447 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1448 ret = -EINVAL;
1449 goto out;
1450 }
1451
1452 link_state = DWC3_DSTS_USBLNKST(reg);
1453
1454 switch (link_state) {
1455 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1456 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1457 break;
1458 default:
1459 dwc3_trace(trace_dwc3_gadget,
1460 "can't wakeup from '%s'\n",
1461 dwc3_gadget_link_string(link_state));
1462 ret = -EINVAL;
1463 goto out;
1464 }
1465
1466 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1467 if (ret < 0) {
1468 dev_err(dwc->dev, "failed to put link in Recovery\n");
1469 goto out;
1470 }
1471
1472 /* Recent versions do this automatically */
1473 if (dwc->revision < DWC3_REVISION_194A) {
1474 /* write zeroes to Link Change Request */
1475 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1476 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1477 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1478 }
1479
1480 /* poll until Link State changes to ON */
1481 timeout = jiffies + msecs_to_jiffies(100);
1482
1483 while (!time_after(jiffies, timeout)) {
1484 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1485
1486 /* in HS, means ON */
1487 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1488 break;
1489 }
1490
1491 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1492 dev_err(dwc->dev, "failed to send remote wakeup\n");
1493 ret = -EINVAL;
1494 }
1495
1496out:
1497 spin_unlock_irqrestore(&dwc->lock, flags);
1498
1499 return ret;
1500}
1501
1502static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1503 int is_selfpowered)
1504{
1505 struct dwc3 *dwc = gadget_to_dwc(g);
1506 unsigned long flags;
1507
1508 spin_lock_irqsave(&dwc->lock, flags);
1509 g->is_selfpowered = !!is_selfpowered;
1510 spin_unlock_irqrestore(&dwc->lock, flags);
1511
1512 return 0;
1513}
1514
1515static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1516{
1517 u32 reg;
1518 u32 timeout = 500;
1519
1520 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1521 if (is_on) {
1522 if (dwc->revision <= DWC3_REVISION_187A) {
1523 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1524 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1525 }
1526
1527 if (dwc->revision >= DWC3_REVISION_194A)
1528 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1529 reg |= DWC3_DCTL_RUN_STOP;
1530
1531 if (dwc->has_hibernation)
1532 reg |= DWC3_DCTL_KEEP_CONNECT;
1533
1534 dwc->pullups_connected = true;
1535 } else {
1536 reg &= ~DWC3_DCTL_RUN_STOP;
1537
1538 if (dwc->has_hibernation && !suspend)
1539 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1540
1541 dwc->pullups_connected = false;
1542 }
1543
1544 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1545
1546 do {
1547 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1548 if (is_on) {
1549 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1550 break;
1551 } else {
1552 if (reg & DWC3_DSTS_DEVCTRLHLT)
1553 break;
1554 }
1555 timeout--;
1556 if (!timeout)
1557 return -ETIMEDOUT;
1558 udelay(1);
1559 } while (1);
1560
1561 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1562 dwc->gadget_driver
1563 ? dwc->gadget_driver->function : "no-function",
1564 is_on ? "connect" : "disconnect");
1565
1566 return 0;
1567}
1568
1569static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1570{
1571 struct dwc3 *dwc = gadget_to_dwc(g);
1572 unsigned long flags;
1573 int ret;
1574
1575 is_on = !!is_on;
1576
1577 spin_lock_irqsave(&dwc->lock, flags);
1578 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1579 spin_unlock_irqrestore(&dwc->lock, flags);
1580
1581 return ret;
1582}
1583
1584static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1585{
1586 u32 reg;
1587
1588 /* Enable all but Start and End of Frame IRQs */
1589 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1590 DWC3_DEVTEN_EVNTOVERFLOWEN |
1591 DWC3_DEVTEN_CMDCMPLTEN |
1592 DWC3_DEVTEN_ERRTICERREN |
1593 DWC3_DEVTEN_WKUPEVTEN |
1594 DWC3_DEVTEN_ULSTCNGEN |
1595 DWC3_DEVTEN_CONNECTDONEEN |
1596 DWC3_DEVTEN_USBRSTEN |
1597 DWC3_DEVTEN_DISCONNEVTEN);
1598
1599 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1600}
1601
1602static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1603{
1604 /* mask all interrupts */
1605 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1606}
1607
1608static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1609static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1610
1611static int dwc3_gadget_start(struct usb_gadget *g,
1612 struct usb_gadget_driver *driver)
1613{
1614 struct dwc3 *dwc = gadget_to_dwc(g);
1615 struct dwc3_ep *dep;
1616 unsigned long flags;
1617 int ret = 0;
1618 int irq;
1619 u32 reg;
1620
1621 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1622 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1623 IRQF_SHARED, "dwc3", dwc);
1624 if (ret) {
1625 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1626 irq, ret);
1627 goto err0;
1628 }
1629
1630 spin_lock_irqsave(&dwc->lock, flags);
1631
1632 if (dwc->gadget_driver) {
1633 dev_err(dwc->dev, "%s is already bound to %s\n",
1634 dwc->gadget.name,
1635 dwc->gadget_driver->driver.name);
1636 ret = -EBUSY;
1637 goto err1;
1638 }
1639
1640 dwc->gadget_driver = driver;
1641
1642 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1643 reg &= ~(DWC3_DCFG_SPEED_MASK);
1644
1645 /**
1646 * WORKAROUND: DWC3 revision < 2.20a have an issue
1647 * which would cause metastability state on Run/Stop
1648 * bit if we try to force the IP to USB2-only mode.
1649 *
1650 * Because of that, we cannot configure the IP to any
1651 * speed other than the SuperSpeed
1652 *
1653 * Refers to:
1654 *
1655 * STAR#9000525659: Clock Domain Crossing on DCTL in
1656 * USB 2.0 Mode
1657 */
1658 if (dwc->revision < DWC3_REVISION_220A) {
1659 reg |= DWC3_DCFG_SUPERSPEED;
1660 } else {
1661 switch (dwc->maximum_speed) {
1662 case USB_SPEED_LOW:
1663 reg |= DWC3_DSTS_LOWSPEED;
1664 break;
1665 case USB_SPEED_FULL:
1666 reg |= DWC3_DSTS_FULLSPEED1;
1667 break;
1668 case USB_SPEED_HIGH:
1669 reg |= DWC3_DSTS_HIGHSPEED;
1670 break;
1671 case USB_SPEED_SUPER_PLUS:
1672 reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1673 break;
1674 default:
1675 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1676 dwc->maximum_speed);
1677 /* fall through */
1678 case USB_SPEED_SUPER:
1679 reg |= DWC3_DCFG_SUPERSPEED;
1680 break;
1681 }
1682 }
1683 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1684
1685 /* Start with SuperSpeed Default */
1686 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1687
1688 dep = dwc->eps[0];
1689 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1690 false);
1691 if (ret) {
1692 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1693 goto err2;
1694 }
1695
1696 dep = dwc->eps[1];
1697 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1698 false);
1699 if (ret) {
1700 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1701 goto err3;
1702 }
1703
1704 /* begin to receive SETUP packets */
1705 dwc->ep0state = EP0_SETUP_PHASE;
1706 dwc3_ep0_out_start(dwc);
1707
1708 dwc3_gadget_enable_irq(dwc);
1709
1710 spin_unlock_irqrestore(&dwc->lock, flags);
1711
1712 return 0;
1713
1714err3:
1715 __dwc3_gadget_ep_disable(dwc->eps[0]);
1716
1717err2:
1718 dwc->gadget_driver = NULL;
1719
1720err1:
1721 spin_unlock_irqrestore(&dwc->lock, flags);
1722
1723 free_irq(irq, dwc);
1724
1725err0:
1726 return ret;
1727}
1728
1729static int dwc3_gadget_stop(struct usb_gadget *g)
1730{
1731 struct dwc3 *dwc = gadget_to_dwc(g);
1732 unsigned long flags;
1733 int irq;
1734
1735 spin_lock_irqsave(&dwc->lock, flags);
1736
1737 dwc3_gadget_disable_irq(dwc);
1738 __dwc3_gadget_ep_disable(dwc->eps[0]);
1739 __dwc3_gadget_ep_disable(dwc->eps[1]);
1740
1741 dwc->gadget_driver = NULL;
1742
1743 spin_unlock_irqrestore(&dwc->lock, flags);
1744
1745 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1746 free_irq(irq, dwc);
1747
1748 return 0;
1749}
1750
1751static const struct usb_gadget_ops dwc3_gadget_ops = {
1752 .get_frame = dwc3_gadget_get_frame,
1753 .wakeup = dwc3_gadget_wakeup,
1754 .set_selfpowered = dwc3_gadget_set_selfpowered,
1755 .pullup = dwc3_gadget_pullup,
1756 .udc_start = dwc3_gadget_start,
1757 .udc_stop = dwc3_gadget_stop,
1758};
1759
1760/* -------------------------------------------------------------------------- */
1761
1762static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1763 u8 num, u32 direction)
1764{
1765 struct dwc3_ep *dep;
1766 u8 i;
1767
1768 for (i = 0; i < num; i++) {
1769 u8 epnum = (i << 1) | (!!direction);
1770
1771 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1772 if (!dep)
1773 return -ENOMEM;
1774
1775 dep->dwc = dwc;
1776 dep->number = epnum;
1777 dep->direction = !!direction;
1778 dwc->eps[epnum] = dep;
1779
1780 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1781 (epnum & 1) ? "in" : "out");
1782
1783 dep->endpoint.name = dep->name;
1784
1785 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1786
1787 if (epnum == 0 || epnum == 1) {
1788 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1789 dep->endpoint.maxburst = 1;
1790 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1791 if (!epnum)
1792 dwc->gadget.ep0 = &dep->endpoint;
1793 } else {
1794 int ret;
1795
1796 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1797 dep->endpoint.max_streams = 15;
1798 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1799 list_add_tail(&dep->endpoint.ep_list,
1800 &dwc->gadget.ep_list);
1801
1802 ret = dwc3_alloc_trb_pool(dep);
1803 if (ret)
1804 return ret;
1805 }
1806
1807 if (epnum == 0 || epnum == 1) {
1808 dep->endpoint.caps.type_control = true;
1809 } else {
1810 dep->endpoint.caps.type_iso = true;
1811 dep->endpoint.caps.type_bulk = true;
1812 dep->endpoint.caps.type_int = true;
1813 }
1814
1815 dep->endpoint.caps.dir_in = !!direction;
1816 dep->endpoint.caps.dir_out = !direction;
1817
1818 INIT_LIST_HEAD(&dep->request_list);
1819 INIT_LIST_HEAD(&dep->req_queued);
1820 }
1821
1822 return 0;
1823}
1824
1825static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1826{
1827 int ret;
1828
1829 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1830
1831 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1832 if (ret < 0) {
1833 dwc3_trace(trace_dwc3_gadget,
1834 "failed to allocate OUT endpoints");
1835 return ret;
1836 }
1837
1838 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1839 if (ret < 0) {
1840 dwc3_trace(trace_dwc3_gadget,
1841 "failed to allocate IN endpoints");
1842 return ret;
1843 }
1844
1845 return 0;
1846}
1847
1848static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1849{
1850 struct dwc3_ep *dep;
1851 u8 epnum;
1852
1853 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1854 dep = dwc->eps[epnum];
1855 if (!dep)
1856 continue;
1857 /*
1858 * Physical endpoints 0 and 1 are special; they form the
1859 * bi-directional USB endpoint 0.
1860 *
1861 * For those two physical endpoints, we don't allocate a TRB
1862 * pool nor do we add them the endpoints list. Due to that, we
1863 * shouldn't do these two operations otherwise we would end up
1864 * with all sorts of bugs when removing dwc3.ko.
1865 */
1866 if (epnum != 0 && epnum != 1) {
1867 dwc3_free_trb_pool(dep);
1868 list_del(&dep->endpoint.ep_list);
1869 }
1870
1871 kfree(dep);
1872 }
1873}
1874
1875/* -------------------------------------------------------------------------- */
1876
1877static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1878 struct dwc3_request *req, struct dwc3_trb *trb,
1879 const struct dwc3_event_depevt *event, int status)
1880{
1881 unsigned int count;
1882 unsigned int s_pkt = 0;
1883 unsigned int trb_status;
1884
1885 trace_dwc3_complete_trb(dep, trb);
1886
1887 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1888 /*
1889 * We continue despite the error. There is not much we
1890 * can do. If we don't clean it up we loop forever. If
1891 * we skip the TRB then it gets overwritten after a
1892 * while since we use them in a ring buffer. A BUG()
1893 * would help. Lets hope that if this occurs, someone
1894 * fixes the root cause instead of looking away :)
1895 */
1896 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1897 dep->name, trb);
1898 count = trb->size & DWC3_TRB_SIZE_MASK;
1899
1900 if (dep->direction) {
1901 if (count) {
1902 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1903 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1904 dwc3_trace(trace_dwc3_gadget,
1905 "%s: incomplete IN transfer\n",
1906 dep->name);
1907 /*
1908 * If missed isoc occurred and there is
1909 * no request queued then issue END
1910 * TRANSFER, so that core generates
1911 * next xfernotready and we will issue
1912 * a fresh START TRANSFER.
1913 * If there are still queued request
1914 * then wait, do not issue either END
1915 * or UPDATE TRANSFER, just attach next
1916 * request in request_list during
1917 * giveback.If any future queued request
1918 * is successfully transferred then we
1919 * will issue UPDATE TRANSFER for all
1920 * request in the request_list.
1921 */
1922 dep->flags |= DWC3_EP_MISSED_ISOC;
1923 } else {
1924 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1925 dep->name);
1926 status = -ECONNRESET;
1927 }
1928 } else {
1929 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1930 }
1931 } else {
1932 if (count && (event->status & DEPEVT_STATUS_SHORT))
1933 s_pkt = 1;
1934 }
1935
1936 /*
1937 * We assume here we will always receive the entire data block
1938 * which we should receive. Meaning, if we program RX to
1939 * receive 4K but we receive only 2K, we assume that's all we
1940 * should receive and we simply bounce the request back to the
1941 * gadget driver for further processing.
1942 */
1943 req->request.actual += req->request.length - count;
1944 if (s_pkt)
1945 return 1;
1946 if ((event->status & DEPEVT_STATUS_LST) &&
1947 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1948 DWC3_TRB_CTRL_HWO)))
1949 return 1;
1950 if ((event->status & DEPEVT_STATUS_IOC) &&
1951 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1952 return 1;
1953 return 0;
1954}
1955
1956static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1957 const struct dwc3_event_depevt *event, int status)
1958{
1959 struct dwc3_request *req;
1960 struct dwc3_trb *trb;
1961 unsigned int slot;
1962 unsigned int i;
1963 int ret;
1964
1965 do {
1966 req = next_request(&dep->req_queued);
1967 if (WARN_ON_ONCE(!req))
1968 return 1;
1969
1970 i = 0;
1971 do {
1972 slot = req->start_slot + i;
1973 if ((slot == DWC3_TRB_NUM - 1) &&
1974 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1975 slot++;
1976 slot %= DWC3_TRB_NUM;
1977 trb = &dep->trb_pool[slot];
1978
1979 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1980 event, status);
1981 if (ret)
1982 break;
1983 } while (++i < req->request.num_mapped_sgs);
1984
1985 dwc3_gadget_giveback(dep, req, status);
1986
1987 if (ret)
1988 break;
1989 } while (1);
1990
1991 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1992 list_empty(&dep->req_queued)) {
1993 if (list_empty(&dep->request_list)) {
1994 /*
1995 * If there is no entry in request list then do
1996 * not issue END TRANSFER now. Just set PENDING
1997 * flag, so that END TRANSFER is issued when an
1998 * entry is added into request list.
1999 */
2000 dep->flags = DWC3_EP_PENDING_REQUEST;
2001 } else {
2002 dwc3_stop_active_transfer(dwc, dep->number, true);
2003 dep->flags = DWC3_EP_ENABLED;
2004 }
2005 return 1;
2006 }
2007
2008 return 1;
2009}
2010
2011static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2012 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2013{
2014 unsigned status = 0;
2015 int clean_busy;
2016 u32 is_xfer_complete;
2017
2018 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2019
2020 if (event->status & DEPEVT_STATUS_BUSERR)
2021 status = -ECONNRESET;
2022
2023 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2024 if (clean_busy && (is_xfer_complete ||
2025 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2026 dep->flags &= ~DWC3_EP_BUSY;
2027
2028 /*
2029 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2030 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2031 */
2032 if (dwc->revision < DWC3_REVISION_183A) {
2033 u32 reg;
2034 int i;
2035
2036 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2037 dep = dwc->eps[i];
2038
2039 if (!(dep->flags & DWC3_EP_ENABLED))
2040 continue;
2041
2042 if (!list_empty(&dep->req_queued))
2043 return;
2044 }
2045
2046 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2047 reg |= dwc->u1u2;
2048 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2049
2050 dwc->u1u2 = 0;
2051 }
2052
2053 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2054 int ret;
2055
2056 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2057 if (!ret || ret == -EBUSY)
2058 return;
2059 }
2060}
2061
2062static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2063 const struct dwc3_event_depevt *event)
2064{
2065 struct dwc3_ep *dep;
2066 u8 epnum = event->endpoint_number;
2067
2068 dep = dwc->eps[epnum];
2069
2070 if (!(dep->flags & DWC3_EP_ENABLED))
2071 return;
2072
2073 if (epnum == 0 || epnum == 1) {
2074 dwc3_ep0_interrupt(dwc, event);
2075 return;
2076 }
2077
2078 switch (event->endpoint_event) {
2079 case DWC3_DEPEVT_XFERCOMPLETE:
2080 dep->resource_index = 0;
2081
2082 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2083 dwc3_trace(trace_dwc3_gadget,
2084 "%s is an Isochronous endpoint\n",
2085 dep->name);
2086 return;
2087 }
2088
2089 dwc3_endpoint_transfer_complete(dwc, dep, event);
2090 break;
2091 case DWC3_DEPEVT_XFERINPROGRESS:
2092 dwc3_endpoint_transfer_complete(dwc, dep, event);
2093 break;
2094 case DWC3_DEPEVT_XFERNOTREADY:
2095 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2096 dwc3_gadget_start_isoc(dwc, dep, event);
2097 } else {
2098 int active;
2099 int ret;
2100
2101 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2102
2103 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2104 dep->name, active ? "Transfer Active"
2105 : "Transfer Not Active");
2106
2107 ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2108 if (!ret || ret == -EBUSY)
2109 return;
2110
2111 dwc3_trace(trace_dwc3_gadget,
2112 "%s: failed to kick transfers\n",
2113 dep->name);
2114 }
2115
2116 break;
2117 case DWC3_DEPEVT_STREAMEVT:
2118 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2119 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2120 dep->name);
2121 return;
2122 }
2123
2124 switch (event->status) {
2125 case DEPEVT_STREAMEVT_FOUND:
2126 dwc3_trace(trace_dwc3_gadget,
2127 "Stream %d found and started",
2128 event->parameters);
2129
2130 break;
2131 case DEPEVT_STREAMEVT_NOTFOUND:
2132 /* FALLTHROUGH */
2133 default:
2134 dwc3_trace(trace_dwc3_gadget,
2135 "unable to find suitable stream\n");
2136 }
2137 break;
2138 case DWC3_DEPEVT_RXTXFIFOEVT:
2139 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2140 break;
2141 case DWC3_DEPEVT_EPCMDCMPLT:
2142 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2143 break;
2144 }
2145}
2146
2147static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2148{
2149 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2150 spin_unlock(&dwc->lock);
2151 dwc->gadget_driver->disconnect(&dwc->gadget);
2152 spin_lock(&dwc->lock);
2153 }
2154}
2155
2156static void dwc3_suspend_gadget(struct dwc3 *dwc)
2157{
2158 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2159 spin_unlock(&dwc->lock);
2160 dwc->gadget_driver->suspend(&dwc->gadget);
2161 spin_lock(&dwc->lock);
2162 }
2163}
2164
2165static void dwc3_resume_gadget(struct dwc3 *dwc)
2166{
2167 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2168 spin_unlock(&dwc->lock);
2169 dwc->gadget_driver->resume(&dwc->gadget);
2170 spin_lock(&dwc->lock);
2171 }
2172}
2173
2174static void dwc3_reset_gadget(struct dwc3 *dwc)
2175{
2176 if (!dwc->gadget_driver)
2177 return;
2178
2179 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2180 spin_unlock(&dwc->lock);
2181 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2182 spin_lock(&dwc->lock);
2183 }
2184}
2185
2186static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2187{
2188 struct dwc3_ep *dep;
2189 struct dwc3_gadget_ep_cmd_params params;
2190 u32 cmd;
2191 int ret;
2192
2193 dep = dwc->eps[epnum];
2194
2195 if (!dep->resource_index)
2196 return;
2197
2198 /*
2199 * NOTICE: We are violating what the Databook says about the
2200 * EndTransfer command. Ideally we would _always_ wait for the
2201 * EndTransfer Command Completion IRQ, but that's causing too
2202 * much trouble synchronizing between us and gadget driver.
2203 *
2204 * We have discussed this with the IP Provider and it was
2205 * suggested to giveback all requests here, but give HW some
2206 * extra time to synchronize with the interconnect. We're using
2207 * an arbitrary 100us delay for that.
2208 *
2209 * Note also that a similar handling was tested by Synopsys
2210 * (thanks a lot Paul) and nothing bad has come out of it.
2211 * In short, what we're doing is:
2212 *
2213 * - Issue EndTransfer WITH CMDIOC bit set
2214 * - Wait 100us
2215 */
2216
2217 cmd = DWC3_DEPCMD_ENDTRANSFER;
2218 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2219 cmd |= DWC3_DEPCMD_CMDIOC;
2220 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2221 memset(¶ms, 0, sizeof(params));
2222 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2223 WARN_ON_ONCE(ret);
2224 dep->resource_index = 0;
2225 dep->flags &= ~DWC3_EP_BUSY;
2226 udelay(100);
2227}
2228
2229static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2230{
2231 u32 epnum;
2232
2233 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2234 struct dwc3_ep *dep;
2235
2236 dep = dwc->eps[epnum];
2237 if (!dep)
2238 continue;
2239
2240 if (!(dep->flags & DWC3_EP_ENABLED))
2241 continue;
2242
2243 dwc3_remove_requests(dwc, dep);
2244 }
2245}
2246
2247static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2248{
2249 u32 epnum;
2250
2251 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2252 struct dwc3_ep *dep;
2253 struct dwc3_gadget_ep_cmd_params params;
2254 int ret;
2255
2256 dep = dwc->eps[epnum];
2257 if (!dep)
2258 continue;
2259
2260 if (!(dep->flags & DWC3_EP_STALL))
2261 continue;
2262
2263 dep->flags &= ~DWC3_EP_STALL;
2264
2265 memset(¶ms, 0, sizeof(params));
2266 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2267 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2268 WARN_ON_ONCE(ret);
2269 }
2270}
2271
2272static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2273{
2274 int reg;
2275
2276 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2277 reg &= ~DWC3_DCTL_INITU1ENA;
2278 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2279
2280 reg &= ~DWC3_DCTL_INITU2ENA;
2281 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2282
2283 dwc3_disconnect_gadget(dwc);
2284
2285 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2286 dwc->setup_packet_pending = false;
2287 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2288}
2289
2290static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2291{
2292 u32 reg;
2293
2294 /*
2295 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2296 * would cause a missing Disconnect Event if there's a
2297 * pending Setup Packet in the FIFO.
2298 *
2299 * There's no suggested workaround on the official Bug
2300 * report, which states that "unless the driver/application
2301 * is doing any special handling of a disconnect event,
2302 * there is no functional issue".
2303 *
2304 * Unfortunately, it turns out that we _do_ some special
2305 * handling of a disconnect event, namely complete all
2306 * pending transfers, notify gadget driver of the
2307 * disconnection, and so on.
2308 *
2309 * Our suggested workaround is to follow the Disconnect
2310 * Event steps here, instead, based on a setup_packet_pending
2311 * flag. Such flag gets set whenever we have a SETUP_PENDING
2312 * status for EP0 TRBs and gets cleared on XferComplete for the
2313 * same endpoint.
2314 *
2315 * Refers to:
2316 *
2317 * STAR#9000466709: RTL: Device : Disconnect event not
2318 * generated if setup packet pending in FIFO
2319 */
2320 if (dwc->revision < DWC3_REVISION_188A) {
2321 if (dwc->setup_packet_pending)
2322 dwc3_gadget_disconnect_interrupt(dwc);
2323 }
2324
2325 dwc3_reset_gadget(dwc);
2326
2327 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2328 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2329 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2330 dwc->test_mode = false;
2331
2332 dwc3_stop_active_transfers(dwc);
2333 dwc3_clear_stall_all_ep(dwc);
2334
2335 /* Reset device address to zero */
2336 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2337 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2338 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2339}
2340
2341static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2342{
2343 u32 reg;
2344 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2345
2346 /*
2347 * We change the clock only at SS but I dunno why I would want to do
2348 * this. Maybe it becomes part of the power saving plan.
2349 */
2350
2351 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2352 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2353 return;
2354
2355 /*
2356 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2357 * each time on Connect Done.
2358 */
2359 if (!usb30_clock)
2360 return;
2361
2362 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2363 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2364 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2365}
2366
2367static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2368{
2369 struct dwc3_ep *dep;
2370 int ret;
2371 u32 reg;
2372 u8 speed;
2373
2374 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2375 speed = reg & DWC3_DSTS_CONNECTSPD;
2376 dwc->speed = speed;
2377
2378 dwc3_update_ram_clk_sel(dwc, speed);
2379
2380 switch (speed) {
2381 case DWC3_DCFG_SUPERSPEED_PLUS:
2382 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2383 dwc->gadget.ep0->maxpacket = 512;
2384 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2385 break;
2386 case DWC3_DCFG_SUPERSPEED:
2387 /*
2388 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2389 * would cause a missing USB3 Reset event.
2390 *
2391 * In such situations, we should force a USB3 Reset
2392 * event by calling our dwc3_gadget_reset_interrupt()
2393 * routine.
2394 *
2395 * Refers to:
2396 *
2397 * STAR#9000483510: RTL: SS : USB3 reset event may
2398 * not be generated always when the link enters poll
2399 */
2400 if (dwc->revision < DWC3_REVISION_190A)
2401 dwc3_gadget_reset_interrupt(dwc);
2402
2403 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2404 dwc->gadget.ep0->maxpacket = 512;
2405 dwc->gadget.speed = USB_SPEED_SUPER;
2406 break;
2407 case DWC3_DCFG_HIGHSPEED:
2408 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2409 dwc->gadget.ep0->maxpacket = 64;
2410 dwc->gadget.speed = USB_SPEED_HIGH;
2411 break;
2412 case DWC3_DCFG_FULLSPEED2:
2413 case DWC3_DCFG_FULLSPEED1:
2414 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2415 dwc->gadget.ep0->maxpacket = 64;
2416 dwc->gadget.speed = USB_SPEED_FULL;
2417 break;
2418 case DWC3_DCFG_LOWSPEED:
2419 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2420 dwc->gadget.ep0->maxpacket = 8;
2421 dwc->gadget.speed = USB_SPEED_LOW;
2422 break;
2423 }
2424
2425 /* Enable USB2 LPM Capability */
2426
2427 if ((dwc->revision > DWC3_REVISION_194A) &&
2428 (speed != DWC3_DCFG_SUPERSPEED) &&
2429 (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2430 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2431 reg |= DWC3_DCFG_LPM_CAP;
2432 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2433
2434 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2435 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2436
2437 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2438
2439 /*
2440 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2441 * DCFG.LPMCap is set, core responses with an ACK and the
2442 * BESL value in the LPM token is less than or equal to LPM
2443 * NYET threshold.
2444 */
2445 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2446 && dwc->has_lpm_erratum,
2447 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2448
2449 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2450 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2451
2452 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2453 } else {
2454 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2455 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2456 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2457 }
2458
2459 dep = dwc->eps[0];
2460 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2461 false);
2462 if (ret) {
2463 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2464 return;
2465 }
2466
2467 dep = dwc->eps[1];
2468 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2469 false);
2470 if (ret) {
2471 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2472 return;
2473 }
2474
2475 /*
2476 * Configure PHY via GUSB3PIPECTLn if required.
2477 *
2478 * Update GTXFIFOSIZn
2479 *
2480 * In both cases reset values should be sufficient.
2481 */
2482}
2483
2484static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2485{
2486 /*
2487 * TODO take core out of low power mode when that's
2488 * implemented.
2489 */
2490
2491 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2492 spin_unlock(&dwc->lock);
2493 dwc->gadget_driver->resume(&dwc->gadget);
2494 spin_lock(&dwc->lock);
2495 }
2496}
2497
2498static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2499 unsigned int evtinfo)
2500{
2501 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2502 unsigned int pwropt;
2503
2504 /*
2505 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2506 * Hibernation mode enabled which would show up when device detects
2507 * host-initiated U3 exit.
2508 *
2509 * In that case, device will generate a Link State Change Interrupt
2510 * from U3 to RESUME which is only necessary if Hibernation is
2511 * configured in.
2512 *
2513 * There are no functional changes due to such spurious event and we
2514 * just need to ignore it.
2515 *
2516 * Refers to:
2517 *
2518 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2519 * operational mode
2520 */
2521 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2522 if ((dwc->revision < DWC3_REVISION_250A) &&
2523 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2524 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2525 (next == DWC3_LINK_STATE_RESUME)) {
2526 dwc3_trace(trace_dwc3_gadget,
2527 "ignoring transition U3 -> Resume");
2528 return;
2529 }
2530 }
2531
2532 /*
2533 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2534 * on the link partner, the USB session might do multiple entry/exit
2535 * of low power states before a transfer takes place.
2536 *
2537 * Due to this problem, we might experience lower throughput. The
2538 * suggested workaround is to disable DCTL[12:9] bits if we're
2539 * transitioning from U1/U2 to U0 and enable those bits again
2540 * after a transfer completes and there are no pending transfers
2541 * on any of the enabled endpoints.
2542 *
2543 * This is the first half of that workaround.
2544 *
2545 * Refers to:
2546 *
2547 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2548 * core send LGO_Ux entering U0
2549 */
2550 if (dwc->revision < DWC3_REVISION_183A) {
2551 if (next == DWC3_LINK_STATE_U0) {
2552 u32 u1u2;
2553 u32 reg;
2554
2555 switch (dwc->link_state) {
2556 case DWC3_LINK_STATE_U1:
2557 case DWC3_LINK_STATE_U2:
2558 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2559 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2560 | DWC3_DCTL_ACCEPTU2ENA
2561 | DWC3_DCTL_INITU1ENA
2562 | DWC3_DCTL_ACCEPTU1ENA);
2563
2564 if (!dwc->u1u2)
2565 dwc->u1u2 = reg & u1u2;
2566
2567 reg &= ~u1u2;
2568
2569 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2570 break;
2571 default:
2572 /* do nothing */
2573 break;
2574 }
2575 }
2576 }
2577
2578 switch (next) {
2579 case DWC3_LINK_STATE_U1:
2580 if (dwc->speed == USB_SPEED_SUPER)
2581 dwc3_suspend_gadget(dwc);
2582 break;
2583 case DWC3_LINK_STATE_U2:
2584 case DWC3_LINK_STATE_U3:
2585 dwc3_suspend_gadget(dwc);
2586 break;
2587 case DWC3_LINK_STATE_RESUME:
2588 dwc3_resume_gadget(dwc);
2589 break;
2590 default:
2591 /* do nothing */
2592 break;
2593 }
2594
2595 dwc->link_state = next;
2596}
2597
2598static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2599 unsigned int evtinfo)
2600{
2601 unsigned int is_ss = evtinfo & BIT(4);
2602
2603 /**
2604 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2605 * have a known issue which can cause USB CV TD.9.23 to fail
2606 * randomly.
2607 *
2608 * Because of this issue, core could generate bogus hibernation
2609 * events which SW needs to ignore.
2610 *
2611 * Refers to:
2612 *
2613 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2614 * Device Fallback from SuperSpeed
2615 */
2616 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2617 return;
2618
2619 /* enter hibernation here */
2620}
2621
2622static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2623 const struct dwc3_event_devt *event)
2624{
2625 switch (event->type) {
2626 case DWC3_DEVICE_EVENT_DISCONNECT:
2627 dwc3_gadget_disconnect_interrupt(dwc);
2628 break;
2629 case DWC3_DEVICE_EVENT_RESET:
2630 dwc3_gadget_reset_interrupt(dwc);
2631 break;
2632 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2633 dwc3_gadget_conndone_interrupt(dwc);
2634 break;
2635 case DWC3_DEVICE_EVENT_WAKEUP:
2636 dwc3_gadget_wakeup_interrupt(dwc);
2637 break;
2638 case DWC3_DEVICE_EVENT_HIBER_REQ:
2639 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2640 "unexpected hibernation event\n"))
2641 break;
2642
2643 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2644 break;
2645 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2646 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2647 break;
2648 case DWC3_DEVICE_EVENT_EOPF:
2649 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2650 break;
2651 case DWC3_DEVICE_EVENT_SOF:
2652 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2653 break;
2654 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2655 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2656 break;
2657 case DWC3_DEVICE_EVENT_CMD_CMPL:
2658 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2659 break;
2660 case DWC3_DEVICE_EVENT_OVERFLOW:
2661 dwc3_trace(trace_dwc3_gadget, "Overflow");
2662 break;
2663 default:
2664 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2665 }
2666}
2667
2668static void dwc3_process_event_entry(struct dwc3 *dwc,
2669 const union dwc3_event *event)
2670{
2671 trace_dwc3_event(event->raw);
2672
2673 /* Endpoint IRQ, handle it and return early */
2674 if (event->type.is_devspec == 0) {
2675 /* depevt */
2676 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2677 }
2678
2679 switch (event->type.type) {
2680 case DWC3_EVENT_TYPE_DEV:
2681 dwc3_gadget_interrupt(dwc, &event->devt);
2682 break;
2683 /* REVISIT what to do with Carkit and I2C events ? */
2684 default:
2685 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2686 }
2687}
2688
2689static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2690{
2691 struct dwc3_event_buffer *evt;
2692 irqreturn_t ret = IRQ_NONE;
2693 int left;
2694 u32 reg;
2695
2696 evt = dwc->ev_buffs[buf];
2697 left = evt->count;
2698
2699 if (!(evt->flags & DWC3_EVENT_PENDING))
2700 return IRQ_NONE;
2701
2702 while (left > 0) {
2703 union dwc3_event event;
2704
2705 event.raw = *(u32 *) (evt->buf + evt->lpos);
2706
2707 dwc3_process_event_entry(dwc, &event);
2708
2709 /*
2710 * FIXME we wrap around correctly to the next entry as
2711 * almost all entries are 4 bytes in size. There is one
2712 * entry which has 12 bytes which is a regular entry
2713 * followed by 8 bytes data. ATM I don't know how
2714 * things are organized if we get next to the a
2715 * boundary so I worry about that once we try to handle
2716 * that.
2717 */
2718 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2719 left -= 4;
2720
2721 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2722 }
2723
2724 evt->count = 0;
2725 evt->flags &= ~DWC3_EVENT_PENDING;
2726 ret = IRQ_HANDLED;
2727
2728 /* Unmask interrupt */
2729 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2730 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2731 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2732
2733 return ret;
2734}
2735
2736static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2737{
2738 struct dwc3 *dwc = _dwc;
2739 unsigned long flags;
2740 irqreturn_t ret = IRQ_NONE;
2741 int i;
2742
2743 spin_lock_irqsave(&dwc->lock, flags);
2744
2745 for (i = 0; i < dwc->num_event_buffers; i++)
2746 ret |= dwc3_process_event_buf(dwc, i);
2747
2748 spin_unlock_irqrestore(&dwc->lock, flags);
2749
2750 return ret;
2751}
2752
2753static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2754{
2755 struct dwc3_event_buffer *evt;
2756 u32 count;
2757 u32 reg;
2758
2759 evt = dwc->ev_buffs[buf];
2760
2761 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2762 count &= DWC3_GEVNTCOUNT_MASK;
2763 if (!count)
2764 return IRQ_NONE;
2765
2766 evt->count = count;
2767 evt->flags |= DWC3_EVENT_PENDING;
2768
2769 /* Mask interrupt */
2770 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2771 reg |= DWC3_GEVNTSIZ_INTMASK;
2772 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2773
2774 return IRQ_WAKE_THREAD;
2775}
2776
2777static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2778{
2779 struct dwc3 *dwc = _dwc;
2780 int i;
2781 irqreturn_t ret = IRQ_NONE;
2782
2783 for (i = 0; i < dwc->num_event_buffers; i++) {
2784 irqreturn_t status;
2785
2786 status = dwc3_check_event_buf(dwc, i);
2787 if (status == IRQ_WAKE_THREAD)
2788 ret = status;
2789 }
2790
2791 return ret;
2792}
2793
2794/**
2795 * dwc3_gadget_init - Initializes gadget related registers
2796 * @dwc: pointer to our controller context structure
2797 *
2798 * Returns 0 on success otherwise negative errno.
2799 */
2800int dwc3_gadget_init(struct dwc3 *dwc)
2801{
2802 int ret;
2803
2804 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2805 &dwc->ctrl_req_addr, GFP_KERNEL);
2806 if (!dwc->ctrl_req) {
2807 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2808 ret = -ENOMEM;
2809 goto err0;
2810 }
2811
2812 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2813 &dwc->ep0_trb_addr, GFP_KERNEL);
2814 if (!dwc->ep0_trb) {
2815 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2816 ret = -ENOMEM;
2817 goto err1;
2818 }
2819
2820 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2821 if (!dwc->setup_buf) {
2822 ret = -ENOMEM;
2823 goto err2;
2824 }
2825
2826 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2827 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2828 GFP_KERNEL);
2829 if (!dwc->ep0_bounce) {
2830 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2831 ret = -ENOMEM;
2832 goto err3;
2833 }
2834
2835 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2836 if (!dwc->zlp_buf) {
2837 ret = -ENOMEM;
2838 goto err4;
2839 }
2840
2841 dwc->gadget.ops = &dwc3_gadget_ops;
2842 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2843 dwc->gadget.sg_supported = true;
2844 dwc->gadget.name = "dwc3-gadget";
2845 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
2846
2847 /*
2848 * FIXME We might be setting max_speed to <SUPER, however versions
2849 * <2.20a of dwc3 have an issue with metastability (documented
2850 * elsewhere in this driver) which tells us we can't set max speed to
2851 * anything lower than SUPER.
2852 *
2853 * Because gadget.max_speed is only used by composite.c and function
2854 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2855 * to happen so we avoid sending SuperSpeed Capability descriptor
2856 * together with our BOS descriptor as that could confuse host into
2857 * thinking we can handle super speed.
2858 *
2859 * Note that, in fact, we won't even support GetBOS requests when speed
2860 * is less than super speed because we don't have means, yet, to tell
2861 * composite.c that we are USB 2.0 + LPM ECN.
2862 */
2863 if (dwc->revision < DWC3_REVISION_220A)
2864 dwc3_trace(trace_dwc3_gadget,
2865 "Changing max_speed on rev %08x\n",
2866 dwc->revision);
2867
2868 dwc->gadget.max_speed = dwc->maximum_speed;
2869
2870 /*
2871 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2872 * on ep out.
2873 */
2874 dwc->gadget.quirk_ep_out_aligned_size = true;
2875
2876 /*
2877 * REVISIT: Here we should clear all pending IRQs to be
2878 * sure we're starting from a well known location.
2879 */
2880
2881 ret = dwc3_gadget_init_endpoints(dwc);
2882 if (ret)
2883 goto err5;
2884
2885 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2886 if (ret) {
2887 dev_err(dwc->dev, "failed to register udc\n");
2888 goto err5;
2889 }
2890
2891 return 0;
2892
2893err5:
2894 kfree(dwc->zlp_buf);
2895
2896err4:
2897 dwc3_gadget_free_endpoints(dwc);
2898 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2899 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2900
2901err3:
2902 kfree(dwc->setup_buf);
2903
2904err2:
2905 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2906 dwc->ep0_trb, dwc->ep0_trb_addr);
2907
2908err1:
2909 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2910 dwc->ctrl_req, dwc->ctrl_req_addr);
2911
2912err0:
2913 return ret;
2914}
2915
2916/* -------------------------------------------------------------------------- */
2917
2918void dwc3_gadget_exit(struct dwc3 *dwc)
2919{
2920 usb_del_gadget_udc(&dwc->gadget);
2921
2922 dwc3_gadget_free_endpoints(dwc);
2923
2924 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2925 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2926
2927 kfree(dwc->setup_buf);
2928 kfree(dwc->zlp_buf);
2929
2930 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2931 dwc->ep0_trb, dwc->ep0_trb_addr);
2932
2933 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2934 dwc->ctrl_req, dwc->ctrl_req_addr);
2935}
2936
2937int dwc3_gadget_suspend(struct dwc3 *dwc)
2938{
2939 if (!dwc->gadget_driver)
2940 return 0;
2941
2942 if (dwc->pullups_connected) {
2943 dwc3_gadget_disable_irq(dwc);
2944 dwc3_gadget_run_stop(dwc, true, true);
2945 }
2946
2947 __dwc3_gadget_ep_disable(dwc->eps[0]);
2948 __dwc3_gadget_ep_disable(dwc->eps[1]);
2949
2950 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2951
2952 return 0;
2953}
2954
2955int dwc3_gadget_resume(struct dwc3 *dwc)
2956{
2957 struct dwc3_ep *dep;
2958 int ret;
2959
2960 if (!dwc->gadget_driver)
2961 return 0;
2962
2963 /* Start with SuperSpeed Default */
2964 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2965
2966 dep = dwc->eps[0];
2967 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2968 false);
2969 if (ret)
2970 goto err0;
2971
2972 dep = dwc->eps[1];
2973 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2974 false);
2975 if (ret)
2976 goto err1;
2977
2978 /* begin to receive SETUP packets */
2979 dwc->ep0state = EP0_SETUP_PHASE;
2980 dwc3_ep0_out_start(dwc);
2981
2982 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2983
2984 if (dwc->pullups_connected) {
2985 dwc3_gadget_enable_irq(dwc);
2986 dwc3_gadget_run_stop(dwc, true, false);
2987 }
2988
2989 return 0;
2990
2991err1:
2992 __dwc3_gadget_ep_disable(dwc->eps[0]);
2993
2994err0:
2995 return ret;
2996}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30#define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
32
33/**
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37 *
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
40 */
41int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42{
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48 switch (mode) {
49 case USB_TEST_J:
50 case USB_TEST_K:
51 case USB_TEST_SE0_NAK:
52 case USB_TEST_PACKET:
53 case USB_TEST_FORCE_ENABLE:
54 reg |= mode << 1;
55 break;
56 default:
57 return -EINVAL;
58 }
59
60 dwc3_gadget_dctl_write_safe(dwc, reg);
61
62 return 0;
63}
64
65/**
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
68 *
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
71 */
72int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73{
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78 return DWC3_DSTS_USBLNKST(reg);
79}
80
81/**
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
85 *
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
88 */
89int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90{
91 int retries = 10000;
92 u32 reg;
93
94 /*
95 * Wait until device controller is ready. Only applies to 1.94a and
96 * later RTL.
97 */
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
99 while (--retries) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
102 udelay(5);
103 else
104 break;
105 }
106
107 if (retries <= 0)
108 return -ETIMEDOUT;
109 }
110
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
116
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
120
121 /*
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
124 */
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
126 return 0;
127
128 /* wait for a change in DSTS */
129 retries = 10000;
130 while (--retries) {
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
132
133 if (DWC3_DSTS_USBLNKST(reg) == state)
134 return 0;
135
136 udelay(5);
137 }
138
139 return -ETIMEDOUT;
140}
141
142/**
143 * dwc3_ep_inc_trb - increment a trb index.
144 * @index: Pointer to the TRB index to increment.
145 *
146 * The index should never point to the link TRB. After incrementing,
147 * if it is point to the link TRB, wrap around to the beginning. The
148 * link TRB is always at the last TRB entry.
149 */
150static void dwc3_ep_inc_trb(u8 *index)
151{
152 (*index)++;
153 if (*index == (DWC3_TRB_NUM - 1))
154 *index = 0;
155}
156
157/**
158 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159 * @dep: The endpoint whose enqueue pointer we're incrementing
160 */
161static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
162{
163 dwc3_ep_inc_trb(&dep->trb_enqueue);
164}
165
166/**
167 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168 * @dep: The endpoint whose enqueue pointer we're incrementing
169 */
170static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
171{
172 dwc3_ep_inc_trb(&dep->trb_dequeue);
173}
174
175static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
176 struct dwc3_request *req, int status)
177{
178 struct dwc3 *dwc = dep->dwc;
179
180 list_del(&req->list);
181 req->remaining = 0;
182 req->needs_extra_trb = false;
183
184 if (req->request.status == -EINPROGRESS)
185 req->request.status = status;
186
187 if (req->trb)
188 usb_gadget_unmap_request_by_dev(dwc->sysdev,
189 &req->request, req->direction);
190
191 req->trb = NULL;
192 trace_dwc3_gadget_giveback(req);
193
194 if (dep->number > 1)
195 pm_runtime_put(dwc->dev);
196}
197
198/**
199 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200 * @dep: The endpoint to whom the request belongs to
201 * @req: The request we're giving back
202 * @status: completion code for the request
203 *
204 * Must be called with controller's lock held and interrupts disabled. This
205 * function will unmap @req and call its ->complete() callback to notify upper
206 * layers that it has completed.
207 */
208void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
209 int status)
210{
211 struct dwc3 *dwc = dep->dwc;
212
213 dwc3_gadget_del_and_unmap_request(dep, req, status);
214 req->status = DWC3_REQUEST_STATUS_COMPLETED;
215
216 spin_unlock(&dwc->lock);
217 usb_gadget_giveback_request(&dep->endpoint, &req->request);
218 spin_lock(&dwc->lock);
219}
220
221/**
222 * dwc3_send_gadget_generic_command - issue a generic command for the controller
223 * @dwc: pointer to the controller context
224 * @cmd: the command to be issued
225 * @param: command parameter
226 *
227 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228 * and wait for its completion.
229 */
230int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
231 u32 param)
232{
233 u32 timeout = 500;
234 int status = 0;
235 int ret = 0;
236 u32 reg;
237
238 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
239 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
240
241 do {
242 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
243 if (!(reg & DWC3_DGCMD_CMDACT)) {
244 status = DWC3_DGCMD_STATUS(reg);
245 if (status)
246 ret = -EINVAL;
247 break;
248 }
249 } while (--timeout);
250
251 if (!timeout) {
252 ret = -ETIMEDOUT;
253 status = -ETIMEDOUT;
254 }
255
256 trace_dwc3_gadget_generic_cmd(cmd, param, status);
257
258 return ret;
259}
260
261static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
262
263/**
264 * dwc3_send_gadget_ep_cmd - issue an endpoint command
265 * @dep: the endpoint to which the command is going to be issued
266 * @cmd: the command to be issued
267 * @params: parameters to the command
268 *
269 * Caller should handle locking. This function will issue @cmd with given
270 * @params to @dep and wait for its completion.
271 */
272int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
273 struct dwc3_gadget_ep_cmd_params *params)
274{
275 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
276 struct dwc3 *dwc = dep->dwc;
277 u32 timeout = 5000;
278 u32 saved_config = 0;
279 u32 reg;
280
281 int cmd_status = 0;
282 int ret = -EINVAL;
283
284 /*
285 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
286 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
287 * endpoint command.
288 *
289 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
290 * settings. Restore them after the command is completed.
291 *
292 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
293 */
294 if (dwc->gadget->speed <= USB_SPEED_HIGH) {
295 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
296 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
297 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
298 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
299 }
300
301 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
302 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
303 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
304 }
305
306 if (saved_config)
307 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
308 }
309
310 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
311 int link_state;
312
313 link_state = dwc3_gadget_get_link_state(dwc);
314 if (link_state == DWC3_LINK_STATE_U1 ||
315 link_state == DWC3_LINK_STATE_U2 ||
316 link_state == DWC3_LINK_STATE_U3) {
317 ret = __dwc3_gadget_wakeup(dwc);
318 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
319 ret);
320 }
321 }
322
323 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
324 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
325 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
326
327 /*
328 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
329 * not relying on XferNotReady, we can make use of a special "No
330 * Response Update Transfer" command where we should clear both CmdAct
331 * and CmdIOC bits.
332 *
333 * With this, we don't need to wait for command completion and can
334 * straight away issue further commands to the endpoint.
335 *
336 * NOTICE: We're making an assumption that control endpoints will never
337 * make use of Update Transfer command. This is a safe assumption
338 * because we can never have more than one request at a time with
339 * Control Endpoints. If anybody changes that assumption, this chunk
340 * needs to be updated accordingly.
341 */
342 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
343 !usb_endpoint_xfer_isoc(desc))
344 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
345 else
346 cmd |= DWC3_DEPCMD_CMDACT;
347
348 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
349 do {
350 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
351 if (!(reg & DWC3_DEPCMD_CMDACT)) {
352 cmd_status = DWC3_DEPCMD_STATUS(reg);
353
354 switch (cmd_status) {
355 case 0:
356 ret = 0;
357 break;
358 case DEPEVT_TRANSFER_NO_RESOURCE:
359 dev_WARN(dwc->dev, "No resource for %s\n",
360 dep->name);
361 ret = -EINVAL;
362 break;
363 case DEPEVT_TRANSFER_BUS_EXPIRY:
364 /*
365 * SW issues START TRANSFER command to
366 * isochronous ep with future frame interval. If
367 * future interval time has already passed when
368 * core receives the command, it will respond
369 * with an error status of 'Bus Expiry'.
370 *
371 * Instead of always returning -EINVAL, let's
372 * give a hint to the gadget driver that this is
373 * the case by returning -EAGAIN.
374 */
375 ret = -EAGAIN;
376 break;
377 default:
378 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
379 }
380
381 break;
382 }
383 } while (--timeout);
384
385 if (timeout == 0) {
386 ret = -ETIMEDOUT;
387 cmd_status = -ETIMEDOUT;
388 }
389
390 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
391
392 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
393 if (ret == 0)
394 dep->flags |= DWC3_EP_TRANSFER_STARTED;
395
396 if (ret != -ETIMEDOUT)
397 dwc3_gadget_ep_get_transfer_index(dep);
398 }
399
400 if (saved_config) {
401 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
402 reg |= saved_config;
403 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
404 }
405
406 return ret;
407}
408
409static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
410{
411 struct dwc3 *dwc = dep->dwc;
412 struct dwc3_gadget_ep_cmd_params params;
413 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
414
415 /*
416 * As of core revision 2.60a the recommended programming model
417 * is to set the ClearPendIN bit when issuing a Clear Stall EP
418 * command for IN endpoints. This is to prevent an issue where
419 * some (non-compliant) hosts may not send ACK TPs for pending
420 * IN transfers due to a mishandled error condition. Synopsys
421 * STAR 9000614252.
422 */
423 if (dep->direction &&
424 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
425 (dwc->gadget->speed >= USB_SPEED_SUPER))
426 cmd |= DWC3_DEPCMD_CLEARPENDIN;
427
428 memset(¶ms, 0, sizeof(params));
429
430 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
431}
432
433static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
434 struct dwc3_trb *trb)
435{
436 u32 offset = (char *) trb - (char *) dep->trb_pool;
437
438 return dep->trb_pool_dma + offset;
439}
440
441static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
442{
443 struct dwc3 *dwc = dep->dwc;
444
445 if (dep->trb_pool)
446 return 0;
447
448 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
449 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
450 &dep->trb_pool_dma, GFP_KERNEL);
451 if (!dep->trb_pool) {
452 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
453 dep->name);
454 return -ENOMEM;
455 }
456
457 return 0;
458}
459
460static void dwc3_free_trb_pool(struct dwc3_ep *dep)
461{
462 struct dwc3 *dwc = dep->dwc;
463
464 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
465 dep->trb_pool, dep->trb_pool_dma);
466
467 dep->trb_pool = NULL;
468 dep->trb_pool_dma = 0;
469}
470
471static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
472{
473 struct dwc3_gadget_ep_cmd_params params;
474
475 memset(¶ms, 0x00, sizeof(params));
476
477 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
478
479 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
480 ¶ms);
481}
482
483/**
484 * dwc3_gadget_start_config - configure ep resources
485 * @dep: endpoint that is being enabled
486 *
487 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
488 * completion, it will set Transfer Resource for all available endpoints.
489 *
490 * The assignment of transfer resources cannot perfectly follow the data book
491 * due to the fact that the controller driver does not have all knowledge of the
492 * configuration in advance. It is given this information piecemeal by the
493 * composite gadget framework after every SET_CONFIGURATION and
494 * SET_INTERFACE. Trying to follow the databook programming model in this
495 * scenario can cause errors. For two reasons:
496 *
497 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
498 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
499 * incorrect in the scenario of multiple interfaces.
500 *
501 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
502 * endpoint on alt setting (8.1.6).
503 *
504 * The following simplified method is used instead:
505 *
506 * All hardware endpoints can be assigned a transfer resource and this setting
507 * will stay persistent until either a core reset or hibernation. So whenever we
508 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
509 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
510 * guaranteed that there are as many transfer resources as endpoints.
511 *
512 * This function is called for each endpoint when it is being enabled but is
513 * triggered only when called for EP0-out, which always happens first, and which
514 * should only happen in one of the above conditions.
515 */
516static int dwc3_gadget_start_config(struct dwc3_ep *dep)
517{
518 struct dwc3_gadget_ep_cmd_params params;
519 struct dwc3 *dwc;
520 u32 cmd;
521 int i;
522 int ret;
523
524 if (dep->number)
525 return 0;
526
527 memset(¶ms, 0x00, sizeof(params));
528 cmd = DWC3_DEPCMD_DEPSTARTCFG;
529 dwc = dep->dwc;
530
531 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
532 if (ret)
533 return ret;
534
535 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
536 struct dwc3_ep *dep = dwc->eps[i];
537
538 if (!dep)
539 continue;
540
541 ret = dwc3_gadget_set_xfer_resource(dep);
542 if (ret)
543 return ret;
544 }
545
546 return 0;
547}
548
549static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
550{
551 const struct usb_ss_ep_comp_descriptor *comp_desc;
552 const struct usb_endpoint_descriptor *desc;
553 struct dwc3_gadget_ep_cmd_params params;
554 struct dwc3 *dwc = dep->dwc;
555
556 comp_desc = dep->endpoint.comp_desc;
557 desc = dep->endpoint.desc;
558
559 memset(¶ms, 0x00, sizeof(params));
560
561 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
562 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
563
564 /* Burst size is only needed in SuperSpeed mode */
565 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
566 u32 burst = dep->endpoint.maxburst;
567
568 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
569 }
570
571 params.param0 |= action;
572 if (action == DWC3_DEPCFG_ACTION_RESTORE)
573 params.param2 |= dep->saved_state;
574
575 if (usb_endpoint_xfer_control(desc))
576 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
577
578 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
579 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
580
581 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
582 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
583 | DWC3_DEPCFG_XFER_COMPLETE_EN
584 | DWC3_DEPCFG_STREAM_EVENT_EN;
585 dep->stream_capable = true;
586 }
587
588 if (!usb_endpoint_xfer_control(desc))
589 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
590
591 /*
592 * We are doing 1:1 mapping for endpoints, meaning
593 * Physical Endpoints 2 maps to Logical Endpoint 2 and
594 * so on. We consider the direction bit as part of the physical
595 * endpoint number. So USB endpoint 0x81 is 0x03.
596 */
597 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
598
599 /*
600 * We must use the lower 16 TX FIFOs even though
601 * HW might have more
602 */
603 if (dep->direction)
604 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
605
606 if (desc->bInterval) {
607 u8 bInterval_m1;
608
609 /*
610 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
611 *
612 * NOTE: The programming guide incorrectly stated bInterval_m1
613 * must be set to 0 when operating in fullspeed. Internally the
614 * controller does not have this limitation. See DWC_usb3x
615 * programming guide section 3.2.2.1.
616 */
617 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
618
619 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
620 dwc->gadget->speed == USB_SPEED_FULL)
621 dep->interval = desc->bInterval;
622 else
623 dep->interval = 1 << (desc->bInterval - 1);
624
625 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
626 }
627
628 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
629}
630
631static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
632 bool interrupt);
633
634/**
635 * __dwc3_gadget_ep_enable - initializes a hw endpoint
636 * @dep: endpoint to be initialized
637 * @action: one of INIT, MODIFY or RESTORE
638 *
639 * Caller should take care of locking. Execute all necessary commands to
640 * initialize a HW endpoint so it can be used by a gadget driver.
641 */
642static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
643{
644 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
645 struct dwc3 *dwc = dep->dwc;
646
647 u32 reg;
648 int ret;
649
650 if (!(dep->flags & DWC3_EP_ENABLED)) {
651 ret = dwc3_gadget_start_config(dep);
652 if (ret)
653 return ret;
654 }
655
656 ret = dwc3_gadget_set_ep_config(dep, action);
657 if (ret)
658 return ret;
659
660 if (!(dep->flags & DWC3_EP_ENABLED)) {
661 struct dwc3_trb *trb_st_hw;
662 struct dwc3_trb *trb_link;
663
664 dep->type = usb_endpoint_type(desc);
665 dep->flags |= DWC3_EP_ENABLED;
666
667 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
668 reg |= DWC3_DALEPENA_EP(dep->number);
669 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
670
671 if (usb_endpoint_xfer_control(desc))
672 goto out;
673
674 /* Initialize the TRB ring */
675 dep->trb_dequeue = 0;
676 dep->trb_enqueue = 0;
677 memset(dep->trb_pool, 0,
678 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
679
680 /* Link TRB. The HWO bit is never reset */
681 trb_st_hw = &dep->trb_pool[0];
682
683 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
684 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
685 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
686 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
687 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
688 }
689
690 /*
691 * Issue StartTransfer here with no-op TRB so we can always rely on No
692 * Response Update Transfer command.
693 */
694 if (usb_endpoint_xfer_bulk(desc) ||
695 usb_endpoint_xfer_int(desc)) {
696 struct dwc3_gadget_ep_cmd_params params;
697 struct dwc3_trb *trb;
698 dma_addr_t trb_dma;
699 u32 cmd;
700
701 memset(¶ms, 0, sizeof(params));
702 trb = &dep->trb_pool[0];
703 trb_dma = dwc3_trb_dma_offset(dep, trb);
704
705 params.param0 = upper_32_bits(trb_dma);
706 params.param1 = lower_32_bits(trb_dma);
707
708 cmd = DWC3_DEPCMD_STARTTRANSFER;
709
710 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
711 if (ret < 0)
712 return ret;
713
714 if (dep->stream_capable) {
715 /*
716 * For streams, at start, there maybe a race where the
717 * host primes the endpoint before the function driver
718 * queues a request to initiate a stream. In that case,
719 * the controller will not see the prime to generate the
720 * ERDY and start stream. To workaround this, issue a
721 * no-op TRB as normal, but end it immediately. As a
722 * result, when the function driver queues the request,
723 * the next START_TRANSFER command will cause the
724 * controller to generate an ERDY to initiate the
725 * stream.
726 */
727 dwc3_stop_active_transfer(dep, true, true);
728
729 /*
730 * All stream eps will reinitiate stream on NoStream
731 * rejection until we can determine that the host can
732 * prime after the first transfer.
733 *
734 * However, if the controller is capable of
735 * TXF_FLUSH_BYPASS, then IN direction endpoints will
736 * automatically restart the stream without the driver
737 * initiation.
738 */
739 if (!dep->direction ||
740 !(dwc->hwparams.hwparams9 &
741 DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
742 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
743 }
744 }
745
746out:
747 trace_dwc3_gadget_ep_enable(dep);
748
749 return 0;
750}
751
752static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
753{
754 struct dwc3_request *req;
755
756 dwc3_stop_active_transfer(dep, true, false);
757
758 /* - giveback all requests to gadget driver */
759 while (!list_empty(&dep->started_list)) {
760 req = next_request(&dep->started_list);
761
762 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
763 }
764
765 while (!list_empty(&dep->pending_list)) {
766 req = next_request(&dep->pending_list);
767
768 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
769 }
770
771 while (!list_empty(&dep->cancelled_list)) {
772 req = next_request(&dep->cancelled_list);
773
774 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
775 }
776}
777
778/**
779 * __dwc3_gadget_ep_disable - disables a hw endpoint
780 * @dep: the endpoint to disable
781 *
782 * This function undoes what __dwc3_gadget_ep_enable did and also removes
783 * requests which are currently being processed by the hardware and those which
784 * are not yet scheduled.
785 *
786 * Caller should take care of locking.
787 */
788static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
789{
790 struct dwc3 *dwc = dep->dwc;
791 u32 reg;
792
793 trace_dwc3_gadget_ep_disable(dep);
794
795 /* make sure HW endpoint isn't stalled */
796 if (dep->flags & DWC3_EP_STALL)
797 __dwc3_gadget_ep_set_halt(dep, 0, false);
798
799 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
800 reg &= ~DWC3_DALEPENA_EP(dep->number);
801 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
802
803 /* Clear out the ep descriptors for non-ep0 */
804 if (dep->number > 1) {
805 dep->endpoint.comp_desc = NULL;
806 dep->endpoint.desc = NULL;
807 }
808
809 dwc3_remove_requests(dwc, dep);
810
811 dep->stream_capable = false;
812 dep->type = 0;
813 dep->flags = 0;
814
815 return 0;
816}
817
818/* -------------------------------------------------------------------------- */
819
820static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
821 const struct usb_endpoint_descriptor *desc)
822{
823 return -EINVAL;
824}
825
826static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
827{
828 return -EINVAL;
829}
830
831/* -------------------------------------------------------------------------- */
832
833static int dwc3_gadget_ep_enable(struct usb_ep *ep,
834 const struct usb_endpoint_descriptor *desc)
835{
836 struct dwc3_ep *dep;
837 struct dwc3 *dwc;
838 unsigned long flags;
839 int ret;
840
841 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
842 pr_debug("dwc3: invalid parameters\n");
843 return -EINVAL;
844 }
845
846 if (!desc->wMaxPacketSize) {
847 pr_debug("dwc3: missing wMaxPacketSize\n");
848 return -EINVAL;
849 }
850
851 dep = to_dwc3_ep(ep);
852 dwc = dep->dwc;
853
854 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
855 "%s is already enabled\n",
856 dep->name))
857 return 0;
858
859 spin_lock_irqsave(&dwc->lock, flags);
860 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
861 spin_unlock_irqrestore(&dwc->lock, flags);
862
863 return ret;
864}
865
866static int dwc3_gadget_ep_disable(struct usb_ep *ep)
867{
868 struct dwc3_ep *dep;
869 struct dwc3 *dwc;
870 unsigned long flags;
871 int ret;
872
873 if (!ep) {
874 pr_debug("dwc3: invalid parameters\n");
875 return -EINVAL;
876 }
877
878 dep = to_dwc3_ep(ep);
879 dwc = dep->dwc;
880
881 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
882 "%s is already disabled\n",
883 dep->name))
884 return 0;
885
886 spin_lock_irqsave(&dwc->lock, flags);
887 ret = __dwc3_gadget_ep_disable(dep);
888 spin_unlock_irqrestore(&dwc->lock, flags);
889
890 return ret;
891}
892
893static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
894 gfp_t gfp_flags)
895{
896 struct dwc3_request *req;
897 struct dwc3_ep *dep = to_dwc3_ep(ep);
898
899 req = kzalloc(sizeof(*req), gfp_flags);
900 if (!req)
901 return NULL;
902
903 req->direction = dep->direction;
904 req->epnum = dep->number;
905 req->dep = dep;
906 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
907
908 trace_dwc3_alloc_request(req);
909
910 return &req->request;
911}
912
913static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
914 struct usb_request *request)
915{
916 struct dwc3_request *req = to_dwc3_request(request);
917
918 trace_dwc3_free_request(req);
919 kfree(req);
920}
921
922/**
923 * dwc3_ep_prev_trb - returns the previous TRB in the ring
924 * @dep: The endpoint with the TRB ring
925 * @index: The index of the current TRB in the ring
926 *
927 * Returns the TRB prior to the one pointed to by the index. If the
928 * index is 0, we will wrap backwards, skip the link TRB, and return
929 * the one just before that.
930 */
931static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
932{
933 u8 tmp = index;
934
935 if (!tmp)
936 tmp = DWC3_TRB_NUM - 1;
937
938 return &dep->trb_pool[tmp - 1];
939}
940
941static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
942{
943 u8 trbs_left;
944
945 /*
946 * If the enqueue & dequeue are equal then the TRB ring is either full
947 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
948 * pending to be processed by the driver.
949 */
950 if (dep->trb_enqueue == dep->trb_dequeue) {
951 /*
952 * If there is any request remained in the started_list at
953 * this point, that means there is no TRB available.
954 */
955 if (!list_empty(&dep->started_list))
956 return 0;
957
958 return DWC3_TRB_NUM - 1;
959 }
960
961 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
962 trbs_left &= (DWC3_TRB_NUM - 1);
963
964 if (dep->trb_dequeue < dep->trb_enqueue)
965 trbs_left--;
966
967 return trbs_left;
968}
969
970static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
971 dma_addr_t dma, unsigned int length, unsigned int chain,
972 unsigned int node, unsigned int stream_id,
973 unsigned int short_not_ok, unsigned int no_interrupt,
974 unsigned int is_last, bool must_interrupt)
975{
976 struct dwc3 *dwc = dep->dwc;
977 struct usb_gadget *gadget = dwc->gadget;
978 enum usb_device_speed speed = gadget->speed;
979
980 trb->size = DWC3_TRB_SIZE_LENGTH(length);
981 trb->bpl = lower_32_bits(dma);
982 trb->bph = upper_32_bits(dma);
983
984 switch (usb_endpoint_type(dep->endpoint.desc)) {
985 case USB_ENDPOINT_XFER_CONTROL:
986 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
987 break;
988
989 case USB_ENDPOINT_XFER_ISOC:
990 if (!node) {
991 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
992
993 /*
994 * USB Specification 2.0 Section 5.9.2 states that: "If
995 * there is only a single transaction in the microframe,
996 * only a DATA0 data packet PID is used. If there are
997 * two transactions per microframe, DATA1 is used for
998 * the first transaction data packet and DATA0 is used
999 * for the second transaction data packet. If there are
1000 * three transactions per microframe, DATA2 is used for
1001 * the first transaction data packet, DATA1 is used for
1002 * the second, and DATA0 is used for the third."
1003 *
1004 * IOW, we should satisfy the following cases:
1005 *
1006 * 1) length <= maxpacket
1007 * - DATA0
1008 *
1009 * 2) maxpacket < length <= (2 * maxpacket)
1010 * - DATA1, DATA0
1011 *
1012 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1013 * - DATA2, DATA1, DATA0
1014 */
1015 if (speed == USB_SPEED_HIGH) {
1016 struct usb_ep *ep = &dep->endpoint;
1017 unsigned int mult = 2;
1018 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1019
1020 if (length <= (2 * maxp))
1021 mult--;
1022
1023 if (length <= maxp)
1024 mult--;
1025
1026 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1027 }
1028 } else {
1029 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1030 }
1031
1032 /* always enable Interrupt on Missed ISOC */
1033 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1034 break;
1035
1036 case USB_ENDPOINT_XFER_BULK:
1037 case USB_ENDPOINT_XFER_INT:
1038 trb->ctrl = DWC3_TRBCTL_NORMAL;
1039 break;
1040 default:
1041 /*
1042 * This is only possible with faulty memory because we
1043 * checked it already :)
1044 */
1045 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1046 usb_endpoint_type(dep->endpoint.desc));
1047 }
1048
1049 /*
1050 * Enable Continue on Short Packet
1051 * when endpoint is not a stream capable
1052 */
1053 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1054 if (!dep->stream_capable)
1055 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1056
1057 if (short_not_ok)
1058 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1059 }
1060
1061 if ((!no_interrupt && !chain) || must_interrupt)
1062 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1063
1064 if (chain)
1065 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1066 else if (dep->stream_capable && is_last)
1067 trb->ctrl |= DWC3_TRB_CTRL_LST;
1068
1069 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1070 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1071
1072 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1073
1074 dwc3_ep_inc_enq(dep);
1075
1076 trace_dwc3_prepare_trb(dep, trb);
1077}
1078
1079/**
1080 * dwc3_prepare_one_trb - setup one TRB from one request
1081 * @dep: endpoint for which this request is prepared
1082 * @req: dwc3_request pointer
1083 * @trb_length: buffer size of the TRB
1084 * @chain: should this TRB be chained to the next?
1085 * @node: only for isochronous endpoints. First TRB needs different type.
1086 * @use_bounce_buffer: set to use bounce buffer
1087 * @must_interrupt: set to interrupt on TRB completion
1088 */
1089static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1090 struct dwc3_request *req, unsigned int trb_length,
1091 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1092 bool must_interrupt)
1093{
1094 struct dwc3_trb *trb;
1095 dma_addr_t dma;
1096 unsigned int stream_id = req->request.stream_id;
1097 unsigned int short_not_ok = req->request.short_not_ok;
1098 unsigned int no_interrupt = req->request.no_interrupt;
1099 unsigned int is_last = req->request.is_last;
1100
1101 if (use_bounce_buffer)
1102 dma = dep->dwc->bounce_addr;
1103 else if (req->request.num_sgs > 0)
1104 dma = sg_dma_address(req->start_sg);
1105 else
1106 dma = req->request.dma;
1107
1108 trb = &dep->trb_pool[dep->trb_enqueue];
1109
1110 if (!req->trb) {
1111 dwc3_gadget_move_started_request(req);
1112 req->trb = trb;
1113 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1114 }
1115
1116 req->num_trbs++;
1117
1118 __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1119 stream_id, short_not_ok, no_interrupt, is_last,
1120 must_interrupt);
1121}
1122
1123static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1124{
1125 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1126 unsigned int rem = req->request.length % maxp;
1127
1128 if ((req->request.length && req->request.zero && !rem &&
1129 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1130 (!req->direction && rem))
1131 return true;
1132
1133 return false;
1134}
1135
1136/**
1137 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1138 * @dep: The endpoint that the request belongs to
1139 * @req: The request to prepare
1140 * @entry_length: The last SG entry size
1141 * @node: Indicates whether this is not the first entry (for isoc only)
1142 *
1143 * Return the number of TRBs prepared.
1144 */
1145static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1146 struct dwc3_request *req, unsigned int entry_length,
1147 unsigned int node)
1148{
1149 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1150 unsigned int rem = req->request.length % maxp;
1151 unsigned int num_trbs = 1;
1152
1153 if (dwc3_needs_extra_trb(dep, req))
1154 num_trbs++;
1155
1156 if (dwc3_calc_trbs_left(dep) < num_trbs)
1157 return 0;
1158
1159 req->needs_extra_trb = num_trbs > 1;
1160
1161 /* Prepare a normal TRB */
1162 if (req->direction || req->request.length)
1163 dwc3_prepare_one_trb(dep, req, entry_length,
1164 req->needs_extra_trb, node, false, false);
1165
1166 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1167 if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1168 dwc3_prepare_one_trb(dep, req,
1169 req->direction ? 0 : maxp - rem,
1170 false, 1, true, false);
1171
1172 return num_trbs;
1173}
1174
1175static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1176 struct dwc3_request *req)
1177{
1178 struct scatterlist *sg = req->start_sg;
1179 struct scatterlist *s;
1180 int i;
1181 unsigned int length = req->request.length;
1182 unsigned int remaining = req->request.num_mapped_sgs
1183 - req->num_queued_sgs;
1184 unsigned int num_trbs = req->num_trbs;
1185 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1186
1187 /*
1188 * If we resume preparing the request, then get the remaining length of
1189 * the request and resume where we left off.
1190 */
1191 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1192 length -= sg_dma_len(s);
1193
1194 for_each_sg(sg, s, remaining, i) {
1195 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1196 unsigned int trb_length;
1197 bool must_interrupt = false;
1198 bool last_sg = false;
1199
1200 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1201
1202 length -= trb_length;
1203
1204 /*
1205 * IOMMU driver is coalescing the list of sgs which shares a
1206 * page boundary into one and giving it to USB driver. With
1207 * this the number of sgs mapped is not equal to the number of
1208 * sgs passed. So mark the chain bit to false if it isthe last
1209 * mapped sg.
1210 */
1211 if ((i == remaining - 1) || !length)
1212 last_sg = true;
1213
1214 if (!num_trbs_left)
1215 break;
1216
1217 if (last_sg) {
1218 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1219 break;
1220 } else {
1221 /*
1222 * Look ahead to check if we have enough TRBs for the
1223 * next SG entry. If not, set interrupt on this TRB to
1224 * resume preparing the next SG entry when more TRBs are
1225 * free.
1226 */
1227 if (num_trbs_left == 1 || (needs_extra_trb &&
1228 num_trbs_left <= 2 &&
1229 sg_dma_len(sg_next(s)) >= length))
1230 must_interrupt = true;
1231
1232 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1233 must_interrupt);
1234 }
1235
1236 /*
1237 * There can be a situation where all sgs in sglist are not
1238 * queued because of insufficient trb number. To handle this
1239 * case, update start_sg to next sg to be queued, so that
1240 * we have free trbs we can continue queuing from where we
1241 * previously stopped
1242 */
1243 if (!last_sg)
1244 req->start_sg = sg_next(s);
1245
1246 req->num_queued_sgs++;
1247 req->num_pending_sgs--;
1248
1249 /*
1250 * The number of pending SG entries may not correspond to the
1251 * number of mapped SG entries. If all the data are queued, then
1252 * don't include unused SG entries.
1253 */
1254 if (length == 0) {
1255 req->num_pending_sgs = 0;
1256 break;
1257 }
1258
1259 if (must_interrupt)
1260 break;
1261 }
1262
1263 return req->num_trbs - num_trbs;
1264}
1265
1266static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1267 struct dwc3_request *req)
1268{
1269 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1270}
1271
1272/*
1273 * dwc3_prepare_trbs - setup TRBs from requests
1274 * @dep: endpoint for which requests are being prepared
1275 *
1276 * The function goes through the requests list and sets up TRBs for the
1277 * transfers. The function returns once there are no more TRBs available or
1278 * it runs out of requests.
1279 *
1280 * Returns the number of TRBs prepared or negative errno.
1281 */
1282static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1283{
1284 struct dwc3_request *req, *n;
1285 int ret = 0;
1286
1287 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1288
1289 /*
1290 * We can get in a situation where there's a request in the started list
1291 * but there weren't enough TRBs to fully kick it in the first time
1292 * around, so it has been waiting for more TRBs to be freed up.
1293 *
1294 * In that case, we should check if we have a request with pending_sgs
1295 * in the started list and prepare TRBs for that request first,
1296 * otherwise we will prepare TRBs completely out of order and that will
1297 * break things.
1298 */
1299 list_for_each_entry(req, &dep->started_list, list) {
1300 if (req->num_pending_sgs > 0) {
1301 ret = dwc3_prepare_trbs_sg(dep, req);
1302 if (!ret || req->num_pending_sgs)
1303 return ret;
1304 }
1305
1306 if (!dwc3_calc_trbs_left(dep))
1307 return ret;
1308
1309 /*
1310 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1311 * burst capability may try to read and use TRBs beyond the
1312 * active transfer instead of stopping.
1313 */
1314 if (dep->stream_capable && req->request.is_last)
1315 return ret;
1316 }
1317
1318 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1319 struct dwc3 *dwc = dep->dwc;
1320
1321 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1322 dep->direction);
1323 if (ret)
1324 return ret;
1325
1326 req->sg = req->request.sg;
1327 req->start_sg = req->sg;
1328 req->num_queued_sgs = 0;
1329 req->num_pending_sgs = req->request.num_mapped_sgs;
1330
1331 if (req->num_pending_sgs > 0) {
1332 ret = dwc3_prepare_trbs_sg(dep, req);
1333 if (req->num_pending_sgs)
1334 return ret;
1335 } else {
1336 ret = dwc3_prepare_trbs_linear(dep, req);
1337 }
1338
1339 if (!ret || !dwc3_calc_trbs_left(dep))
1340 return ret;
1341
1342 /*
1343 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1344 * burst capability may try to read and use TRBs beyond the
1345 * active transfer instead of stopping.
1346 */
1347 if (dep->stream_capable && req->request.is_last)
1348 return ret;
1349 }
1350
1351 return ret;
1352}
1353
1354static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1355
1356static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1357{
1358 struct dwc3_gadget_ep_cmd_params params;
1359 struct dwc3_request *req;
1360 int starting;
1361 int ret;
1362 u32 cmd;
1363
1364 /*
1365 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1366 * This happens when we need to stop and restart a transfer such as in
1367 * the case of reinitiating a stream or retrying an isoc transfer.
1368 */
1369 ret = dwc3_prepare_trbs(dep);
1370 if (ret < 0)
1371 return ret;
1372
1373 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1374
1375 /*
1376 * If there's no new TRB prepared and we don't need to restart a
1377 * transfer, there's no need to update the transfer.
1378 */
1379 if (!ret && !starting)
1380 return ret;
1381
1382 req = next_request(&dep->started_list);
1383 if (!req) {
1384 dep->flags |= DWC3_EP_PENDING_REQUEST;
1385 return 0;
1386 }
1387
1388 memset(¶ms, 0, sizeof(params));
1389
1390 if (starting) {
1391 params.param0 = upper_32_bits(req->trb_dma);
1392 params.param1 = lower_32_bits(req->trb_dma);
1393 cmd = DWC3_DEPCMD_STARTTRANSFER;
1394
1395 if (dep->stream_capable)
1396 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1397
1398 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1399 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1400 } else {
1401 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1402 DWC3_DEPCMD_PARAM(dep->resource_index);
1403 }
1404
1405 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1406 if (ret < 0) {
1407 struct dwc3_request *tmp;
1408
1409 if (ret == -EAGAIN)
1410 return ret;
1411
1412 dwc3_stop_active_transfer(dep, true, true);
1413
1414 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1415 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1416
1417 /* If ep isn't started, then there's no end transfer pending */
1418 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1419 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1420
1421 return ret;
1422 }
1423
1424 if (dep->stream_capable && req->request.is_last)
1425 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1426
1427 return 0;
1428}
1429
1430static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1431{
1432 u32 reg;
1433
1434 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1435 return DWC3_DSTS_SOFFN(reg);
1436}
1437
1438/**
1439 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1440 * @dep: isoc endpoint
1441 *
1442 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1443 * microframe number reported by the XferNotReady event for the future frame
1444 * number to start the isoc transfer.
1445 *
1446 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1447 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1448 * XferNotReady event are invalid. The driver uses this number to schedule the
1449 * isochronous transfer and passes it to the START TRANSFER command. Because
1450 * this number is invalid, the command may fail. If BIT[15:14] matches the
1451 * internal 16-bit microframe, the START TRANSFER command will pass and the
1452 * transfer will start at the scheduled time, if it is off by 1, the command
1453 * will still pass, but the transfer will start 2 seconds in the future. For all
1454 * other conditions, the START TRANSFER command will fail with bus-expiry.
1455 *
1456 * In order to workaround this issue, we can test for the correct combination of
1457 * BIT[15:14] by sending START TRANSFER commands with different values of
1458 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1459 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1460 * As the result, within the 4 possible combinations for BIT[15:14], there will
1461 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1462 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1463 * value is the correct combination.
1464 *
1465 * Since there are only 4 outcomes and the results are ordered, we can simply
1466 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1467 * deduce the smaller successful combination.
1468 *
1469 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1470 * of BIT[15:14]. The correct combination is as follow:
1471 *
1472 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1473 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1474 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1475 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1476 *
1477 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1478 * endpoints.
1479 */
1480static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1481{
1482 int cmd_status = 0;
1483 bool test0;
1484 bool test1;
1485
1486 while (dep->combo_num < 2) {
1487 struct dwc3_gadget_ep_cmd_params params;
1488 u32 test_frame_number;
1489 u32 cmd;
1490
1491 /*
1492 * Check if we can start isoc transfer on the next interval or
1493 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1494 */
1495 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1496 test_frame_number |= dep->combo_num << 14;
1497 test_frame_number += max_t(u32, 4, dep->interval);
1498
1499 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1500 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1501
1502 cmd = DWC3_DEPCMD_STARTTRANSFER;
1503 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1504 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1505
1506 /* Redo if some other failure beside bus-expiry is received */
1507 if (cmd_status && cmd_status != -EAGAIN) {
1508 dep->start_cmd_status = 0;
1509 dep->combo_num = 0;
1510 return 0;
1511 }
1512
1513 /* Store the first test status */
1514 if (dep->combo_num == 0)
1515 dep->start_cmd_status = cmd_status;
1516
1517 dep->combo_num++;
1518
1519 /*
1520 * End the transfer if the START_TRANSFER command is successful
1521 * to wait for the next XferNotReady to test the command again
1522 */
1523 if (cmd_status == 0) {
1524 dwc3_stop_active_transfer(dep, true, true);
1525 return 0;
1526 }
1527 }
1528
1529 /* test0 and test1 are both completed at this point */
1530 test0 = (dep->start_cmd_status == 0);
1531 test1 = (cmd_status == 0);
1532
1533 if (!test0 && test1)
1534 dep->combo_num = 1;
1535 else if (!test0 && !test1)
1536 dep->combo_num = 2;
1537 else if (test0 && !test1)
1538 dep->combo_num = 3;
1539 else if (test0 && test1)
1540 dep->combo_num = 0;
1541
1542 dep->frame_number &= DWC3_FRNUMBER_MASK;
1543 dep->frame_number |= dep->combo_num << 14;
1544 dep->frame_number += max_t(u32, 4, dep->interval);
1545
1546 /* Reinitialize test variables */
1547 dep->start_cmd_status = 0;
1548 dep->combo_num = 0;
1549
1550 return __dwc3_gadget_kick_transfer(dep);
1551}
1552
1553static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1554{
1555 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1556 struct dwc3 *dwc = dep->dwc;
1557 int ret;
1558 int i;
1559
1560 if (list_empty(&dep->pending_list) &&
1561 list_empty(&dep->started_list)) {
1562 dep->flags |= DWC3_EP_PENDING_REQUEST;
1563 return -EAGAIN;
1564 }
1565
1566 if (!dwc->dis_start_transfer_quirk &&
1567 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1568 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1569 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1570 return dwc3_gadget_start_isoc_quirk(dep);
1571 }
1572
1573 if (desc->bInterval <= 14 &&
1574 dwc->gadget->speed >= USB_SPEED_HIGH) {
1575 u32 frame = __dwc3_gadget_get_frame(dwc);
1576 bool rollover = frame <
1577 (dep->frame_number & DWC3_FRNUMBER_MASK);
1578
1579 /*
1580 * frame_number is set from XferNotReady and may be already
1581 * out of date. DSTS only provides the lower 14 bit of the
1582 * current frame number. So add the upper two bits of
1583 * frame_number and handle a possible rollover.
1584 * This will provide the correct frame_number unless more than
1585 * rollover has happened since XferNotReady.
1586 */
1587
1588 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1589 frame;
1590 if (rollover)
1591 dep->frame_number += BIT(14);
1592 }
1593
1594 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1595 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1596
1597 ret = __dwc3_gadget_kick_transfer(dep);
1598 if (ret != -EAGAIN)
1599 break;
1600 }
1601
1602 /*
1603 * After a number of unsuccessful start attempts due to bus-expiry
1604 * status, issue END_TRANSFER command and retry on the next XferNotReady
1605 * event.
1606 */
1607 if (ret == -EAGAIN) {
1608 struct dwc3_gadget_ep_cmd_params params;
1609 u32 cmd;
1610
1611 cmd = DWC3_DEPCMD_ENDTRANSFER |
1612 DWC3_DEPCMD_CMDIOC |
1613 DWC3_DEPCMD_PARAM(dep->resource_index);
1614
1615 dep->resource_index = 0;
1616 memset(¶ms, 0, sizeof(params));
1617
1618 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1619 if (!ret)
1620 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1621 }
1622
1623 return ret;
1624}
1625
1626static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1627{
1628 struct dwc3 *dwc = dep->dwc;
1629
1630 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1631 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1632 dep->name);
1633 return -ESHUTDOWN;
1634 }
1635
1636 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1637 &req->request, req->dep->name))
1638 return -EINVAL;
1639
1640 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1641 "%s: request %pK already in flight\n",
1642 dep->name, &req->request))
1643 return -EINVAL;
1644
1645 pm_runtime_get(dwc->dev);
1646
1647 req->request.actual = 0;
1648 req->request.status = -EINPROGRESS;
1649
1650 trace_dwc3_ep_queue(req);
1651
1652 list_add_tail(&req->list, &dep->pending_list);
1653 req->status = DWC3_REQUEST_STATUS_QUEUED;
1654
1655 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1656 return 0;
1657
1658 /*
1659 * Start the transfer only after the END_TRANSFER is completed
1660 * and endpoint STALL is cleared.
1661 */
1662 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1663 (dep->flags & DWC3_EP_WEDGE) ||
1664 (dep->flags & DWC3_EP_STALL)) {
1665 dep->flags |= DWC3_EP_DELAY_START;
1666 return 0;
1667 }
1668
1669 /*
1670 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1671 * wait for a XferNotReady event so we will know what's the current
1672 * (micro-)frame number.
1673 *
1674 * Without this trick, we are very, very likely gonna get Bus Expiry
1675 * errors which will force us issue EndTransfer command.
1676 */
1677 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1678 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1679 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1680 return 0;
1681
1682 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1683 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1684 return __dwc3_gadget_start_isoc(dep);
1685 }
1686 }
1687
1688 __dwc3_gadget_kick_transfer(dep);
1689
1690 return 0;
1691}
1692
1693static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1694 gfp_t gfp_flags)
1695{
1696 struct dwc3_request *req = to_dwc3_request(request);
1697 struct dwc3_ep *dep = to_dwc3_ep(ep);
1698 struct dwc3 *dwc = dep->dwc;
1699
1700 unsigned long flags;
1701
1702 int ret;
1703
1704 spin_lock_irqsave(&dwc->lock, flags);
1705 ret = __dwc3_gadget_ep_queue(dep, req);
1706 spin_unlock_irqrestore(&dwc->lock, flags);
1707
1708 return ret;
1709}
1710
1711static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1712{
1713 int i;
1714
1715 /* If req->trb is not set, then the request has not started */
1716 if (!req->trb)
1717 return;
1718
1719 /*
1720 * If request was already started, this means we had to
1721 * stop the transfer. With that we also need to ignore
1722 * all TRBs used by the request, however TRBs can only
1723 * be modified after completion of END_TRANSFER
1724 * command. So what we do here is that we wait for
1725 * END_TRANSFER completion and only after that, we jump
1726 * over TRBs by clearing HWO and incrementing dequeue
1727 * pointer.
1728 */
1729 for (i = 0; i < req->num_trbs; i++) {
1730 struct dwc3_trb *trb;
1731
1732 trb = &dep->trb_pool[dep->trb_dequeue];
1733 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1734 dwc3_ep_inc_deq(dep);
1735 }
1736
1737 req->num_trbs = 0;
1738}
1739
1740static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1741{
1742 struct dwc3_request *req;
1743 struct dwc3_request *tmp;
1744 struct dwc3 *dwc = dep->dwc;
1745
1746 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1747 dwc3_gadget_ep_skip_trbs(dep, req);
1748 switch (req->status) {
1749 case DWC3_REQUEST_STATUS_DISCONNECTED:
1750 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
1751 break;
1752 case DWC3_REQUEST_STATUS_DEQUEUED:
1753 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1754 break;
1755 case DWC3_REQUEST_STATUS_STALLED:
1756 dwc3_gadget_giveback(dep, req, -EPIPE);
1757 break;
1758 default:
1759 dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
1760 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1761 break;
1762 }
1763 }
1764}
1765
1766static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1767 struct usb_request *request)
1768{
1769 struct dwc3_request *req = to_dwc3_request(request);
1770 struct dwc3_request *r = NULL;
1771
1772 struct dwc3_ep *dep = to_dwc3_ep(ep);
1773 struct dwc3 *dwc = dep->dwc;
1774
1775 unsigned long flags;
1776 int ret = 0;
1777
1778 trace_dwc3_ep_dequeue(req);
1779
1780 spin_lock_irqsave(&dwc->lock, flags);
1781
1782 list_for_each_entry(r, &dep->cancelled_list, list) {
1783 if (r == req)
1784 goto out;
1785 }
1786
1787 list_for_each_entry(r, &dep->pending_list, list) {
1788 if (r == req) {
1789 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1790 goto out;
1791 }
1792 }
1793
1794 list_for_each_entry(r, &dep->started_list, list) {
1795 if (r == req) {
1796 struct dwc3_request *t;
1797
1798 /* wait until it is processed */
1799 dwc3_stop_active_transfer(dep, true, true);
1800
1801 /*
1802 * Remove any started request if the transfer is
1803 * cancelled.
1804 */
1805 list_for_each_entry_safe(r, t, &dep->started_list, list)
1806 dwc3_gadget_move_cancelled_request(r,
1807 DWC3_REQUEST_STATUS_DEQUEUED);
1808
1809 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
1810
1811 goto out;
1812 }
1813 }
1814
1815 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1816 request, ep->name);
1817 ret = -EINVAL;
1818out:
1819 spin_unlock_irqrestore(&dwc->lock, flags);
1820
1821 return ret;
1822}
1823
1824int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1825{
1826 struct dwc3_gadget_ep_cmd_params params;
1827 struct dwc3 *dwc = dep->dwc;
1828 struct dwc3_request *req;
1829 struct dwc3_request *tmp;
1830 int ret;
1831
1832 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1833 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1834 return -EINVAL;
1835 }
1836
1837 memset(¶ms, 0x00, sizeof(params));
1838
1839 if (value) {
1840 struct dwc3_trb *trb;
1841
1842 unsigned int transfer_in_flight;
1843 unsigned int started;
1844
1845 if (dep->number > 1)
1846 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1847 else
1848 trb = &dwc->ep0_trb[dep->trb_enqueue];
1849
1850 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1851 started = !list_empty(&dep->started_list);
1852
1853 if (!protocol && ((dep->direction && transfer_in_flight) ||
1854 (!dep->direction && started))) {
1855 return -EAGAIN;
1856 }
1857
1858 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1859 ¶ms);
1860 if (ret)
1861 dev_err(dwc->dev, "failed to set STALL on %s\n",
1862 dep->name);
1863 else
1864 dep->flags |= DWC3_EP_STALL;
1865 } else {
1866 /*
1867 * Don't issue CLEAR_STALL command to control endpoints. The
1868 * controller automatically clears the STALL when it receives
1869 * the SETUP token.
1870 */
1871 if (dep->number <= 1) {
1872 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1873 return 0;
1874 }
1875
1876 dwc3_stop_active_transfer(dep, true, true);
1877
1878 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1879 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
1880
1881 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
1882 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
1883 return 0;
1884 }
1885
1886 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1887
1888 ret = dwc3_send_clear_stall_ep_cmd(dep);
1889 if (ret) {
1890 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1891 dep->name);
1892 return ret;
1893 }
1894
1895 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1896
1897 if ((dep->flags & DWC3_EP_DELAY_START) &&
1898 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
1899 __dwc3_gadget_kick_transfer(dep);
1900
1901 dep->flags &= ~DWC3_EP_DELAY_START;
1902 }
1903
1904 return ret;
1905}
1906
1907static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1908{
1909 struct dwc3_ep *dep = to_dwc3_ep(ep);
1910 struct dwc3 *dwc = dep->dwc;
1911
1912 unsigned long flags;
1913
1914 int ret;
1915
1916 spin_lock_irqsave(&dwc->lock, flags);
1917 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1918 spin_unlock_irqrestore(&dwc->lock, flags);
1919
1920 return ret;
1921}
1922
1923static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1924{
1925 struct dwc3_ep *dep = to_dwc3_ep(ep);
1926 struct dwc3 *dwc = dep->dwc;
1927 unsigned long flags;
1928 int ret;
1929
1930 spin_lock_irqsave(&dwc->lock, flags);
1931 dep->flags |= DWC3_EP_WEDGE;
1932
1933 if (dep->number == 0 || dep->number == 1)
1934 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1935 else
1936 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1937 spin_unlock_irqrestore(&dwc->lock, flags);
1938
1939 return ret;
1940}
1941
1942/* -------------------------------------------------------------------------- */
1943
1944static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1945 .bLength = USB_DT_ENDPOINT_SIZE,
1946 .bDescriptorType = USB_DT_ENDPOINT,
1947 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1948};
1949
1950static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1951 .enable = dwc3_gadget_ep0_enable,
1952 .disable = dwc3_gadget_ep0_disable,
1953 .alloc_request = dwc3_gadget_ep_alloc_request,
1954 .free_request = dwc3_gadget_ep_free_request,
1955 .queue = dwc3_gadget_ep0_queue,
1956 .dequeue = dwc3_gadget_ep_dequeue,
1957 .set_halt = dwc3_gadget_ep0_set_halt,
1958 .set_wedge = dwc3_gadget_ep_set_wedge,
1959};
1960
1961static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1962 .enable = dwc3_gadget_ep_enable,
1963 .disable = dwc3_gadget_ep_disable,
1964 .alloc_request = dwc3_gadget_ep_alloc_request,
1965 .free_request = dwc3_gadget_ep_free_request,
1966 .queue = dwc3_gadget_ep_queue,
1967 .dequeue = dwc3_gadget_ep_dequeue,
1968 .set_halt = dwc3_gadget_ep_set_halt,
1969 .set_wedge = dwc3_gadget_ep_set_wedge,
1970};
1971
1972/* -------------------------------------------------------------------------- */
1973
1974static int dwc3_gadget_get_frame(struct usb_gadget *g)
1975{
1976 struct dwc3 *dwc = gadget_to_dwc(g);
1977
1978 return __dwc3_gadget_get_frame(dwc);
1979}
1980
1981static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1982{
1983 int retries;
1984
1985 int ret;
1986 u32 reg;
1987
1988 u8 link_state;
1989
1990 /*
1991 * According to the Databook Remote wakeup request should
1992 * be issued only when the device is in early suspend state.
1993 *
1994 * We can check that via USB Link State bits in DSTS register.
1995 */
1996 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1997
1998 link_state = DWC3_DSTS_USBLNKST(reg);
1999
2000 switch (link_state) {
2001 case DWC3_LINK_STATE_RESET:
2002 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2003 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2004 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2005 case DWC3_LINK_STATE_U1:
2006 case DWC3_LINK_STATE_RESUME:
2007 break;
2008 default:
2009 return -EINVAL;
2010 }
2011
2012 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2013 if (ret < 0) {
2014 dev_err(dwc->dev, "failed to put link in Recovery\n");
2015 return ret;
2016 }
2017
2018 /* Recent versions do this automatically */
2019 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2020 /* write zeroes to Link Change Request */
2021 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2022 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2023 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2024 }
2025
2026 /* poll until Link State changes to ON */
2027 retries = 20000;
2028
2029 while (retries--) {
2030 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2031
2032 /* in HS, means ON */
2033 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2034 break;
2035 }
2036
2037 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2038 dev_err(dwc->dev, "failed to send remote wakeup\n");
2039 return -EINVAL;
2040 }
2041
2042 return 0;
2043}
2044
2045static int dwc3_gadget_wakeup(struct usb_gadget *g)
2046{
2047 struct dwc3 *dwc = gadget_to_dwc(g);
2048 unsigned long flags;
2049 int ret;
2050
2051 spin_lock_irqsave(&dwc->lock, flags);
2052 ret = __dwc3_gadget_wakeup(dwc);
2053 spin_unlock_irqrestore(&dwc->lock, flags);
2054
2055 return ret;
2056}
2057
2058static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2059 int is_selfpowered)
2060{
2061 struct dwc3 *dwc = gadget_to_dwc(g);
2062 unsigned long flags;
2063
2064 spin_lock_irqsave(&dwc->lock, flags);
2065 g->is_selfpowered = !!is_selfpowered;
2066 spin_unlock_irqrestore(&dwc->lock, flags);
2067
2068 return 0;
2069}
2070
2071static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2072{
2073 u32 epnum;
2074
2075 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2076 struct dwc3_ep *dep;
2077
2078 dep = dwc->eps[epnum];
2079 if (!dep)
2080 continue;
2081
2082 dwc3_remove_requests(dwc, dep);
2083 }
2084}
2085
2086static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2087{
2088 enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
2089 u32 reg;
2090
2091 if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2092 ssp_rate = dwc->max_ssp_rate;
2093
2094 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2095 reg &= ~DWC3_DCFG_SPEED_MASK;
2096 reg &= ~DWC3_DCFG_NUMLANES(~0);
2097
2098 if (ssp_rate == USB_SSP_GEN_1x2)
2099 reg |= DWC3_DCFG_SUPERSPEED;
2100 else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2101 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2102
2103 if (ssp_rate != USB_SSP_GEN_2x1 &&
2104 dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2105 reg |= DWC3_DCFG_NUMLANES(1);
2106
2107 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2108}
2109
2110static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2111{
2112 enum usb_device_speed speed;
2113 u32 reg;
2114
2115 speed = dwc->gadget_max_speed;
2116 if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2117 speed = dwc->maximum_speed;
2118
2119 if (speed == USB_SPEED_SUPER_PLUS &&
2120 DWC3_IP_IS(DWC32)) {
2121 __dwc3_gadget_set_ssp_rate(dwc);
2122 return;
2123 }
2124
2125 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2126 reg &= ~(DWC3_DCFG_SPEED_MASK);
2127
2128 /*
2129 * WORKAROUND: DWC3 revision < 2.20a have an issue
2130 * which would cause metastability state on Run/Stop
2131 * bit if we try to force the IP to USB2-only mode.
2132 *
2133 * Because of that, we cannot configure the IP to any
2134 * speed other than the SuperSpeed
2135 *
2136 * Refers to:
2137 *
2138 * STAR#9000525659: Clock Domain Crossing on DCTL in
2139 * USB 2.0 Mode
2140 */
2141 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2142 !dwc->dis_metastability_quirk) {
2143 reg |= DWC3_DCFG_SUPERSPEED;
2144 } else {
2145 switch (speed) {
2146 case USB_SPEED_FULL:
2147 reg |= DWC3_DCFG_FULLSPEED;
2148 break;
2149 case USB_SPEED_HIGH:
2150 reg |= DWC3_DCFG_HIGHSPEED;
2151 break;
2152 case USB_SPEED_SUPER:
2153 reg |= DWC3_DCFG_SUPERSPEED;
2154 break;
2155 case USB_SPEED_SUPER_PLUS:
2156 if (DWC3_IP_IS(DWC3))
2157 reg |= DWC3_DCFG_SUPERSPEED;
2158 else
2159 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2160 break;
2161 default:
2162 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2163
2164 if (DWC3_IP_IS(DWC3))
2165 reg |= DWC3_DCFG_SUPERSPEED;
2166 else
2167 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2168 }
2169 }
2170
2171 if (DWC3_IP_IS(DWC32) &&
2172 speed > USB_SPEED_UNKNOWN &&
2173 speed < USB_SPEED_SUPER_PLUS)
2174 reg &= ~DWC3_DCFG_NUMLANES(~0);
2175
2176 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2177}
2178
2179static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2180{
2181 u32 reg;
2182 u32 timeout = 500;
2183
2184 if (pm_runtime_suspended(dwc->dev))
2185 return 0;
2186
2187 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2188 if (is_on) {
2189 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2190 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2191 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2192 }
2193
2194 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2195 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2196 reg |= DWC3_DCTL_RUN_STOP;
2197
2198 if (dwc->has_hibernation)
2199 reg |= DWC3_DCTL_KEEP_CONNECT;
2200
2201 __dwc3_gadget_set_speed(dwc);
2202 dwc->pullups_connected = true;
2203 } else {
2204 reg &= ~DWC3_DCTL_RUN_STOP;
2205
2206 if (dwc->has_hibernation && !suspend)
2207 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2208
2209 dwc->pullups_connected = false;
2210 }
2211
2212 dwc3_gadget_dctl_write_safe(dwc, reg);
2213
2214 do {
2215 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2216 reg &= DWC3_DSTS_DEVCTRLHLT;
2217 } while (--timeout && !(!is_on ^ !reg));
2218
2219 if (!timeout)
2220 return -ETIMEDOUT;
2221
2222 return 0;
2223}
2224
2225static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2226static void __dwc3_gadget_stop(struct dwc3 *dwc);
2227static int __dwc3_gadget_start(struct dwc3 *dwc);
2228
2229static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2230{
2231 struct dwc3 *dwc = gadget_to_dwc(g);
2232 unsigned long flags;
2233 int ret;
2234
2235 is_on = !!is_on;
2236
2237 /*
2238 * Per databook, when we want to stop the gadget, if a control transfer
2239 * is still in process, complete it and get the core into setup phase.
2240 */
2241 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2242 reinit_completion(&dwc->ep0_in_setup);
2243
2244 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2245 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2246 if (ret == 0)
2247 dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
2248 }
2249
2250 /*
2251 * Avoid issuing a runtime resume if the device is already in the
2252 * suspended state during gadget disconnect. DWC3 gadget was already
2253 * halted/stopped during runtime suspend.
2254 */
2255 if (!is_on) {
2256 pm_runtime_barrier(dwc->dev);
2257 if (pm_runtime_suspended(dwc->dev))
2258 return 0;
2259 }
2260
2261 /*
2262 * Check the return value for successful resume, or error. For a
2263 * successful resume, the DWC3 runtime PM resume routine will handle
2264 * the run stop sequence, so avoid duplicate operations here.
2265 */
2266 ret = pm_runtime_get_sync(dwc->dev);
2267 if (!ret || ret < 0) {
2268 pm_runtime_put(dwc->dev);
2269 return 0;
2270 }
2271
2272 /*
2273 * Synchronize and disable any further event handling while controller
2274 * is being enabled/disabled.
2275 */
2276 disable_irq(dwc->irq_gadget);
2277
2278 spin_lock_irqsave(&dwc->lock, flags);
2279
2280 if (!is_on) {
2281 u32 count;
2282
2283 dwc->connected = false;
2284 /*
2285 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2286 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2287 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2288 * command for any active transfers" before clearing the RunStop
2289 * bit.
2290 */
2291 dwc3_stop_active_transfers(dwc);
2292 __dwc3_gadget_stop(dwc);
2293
2294 /*
2295 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2296 * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the
2297 * "software needs to acknowledge the events that are generated
2298 * (by writing to GEVNTCOUNTn) while it is waiting for this bit
2299 * to be set to '1'."
2300 */
2301 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2302 count &= DWC3_GEVNTCOUNT_MASK;
2303 if (count > 0) {
2304 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2305 dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) %
2306 dwc->ev_buf->length;
2307 }
2308 } else {
2309 __dwc3_gadget_start(dwc);
2310 }
2311
2312 ret = dwc3_gadget_run_stop(dwc, is_on, false);
2313 spin_unlock_irqrestore(&dwc->lock, flags);
2314 enable_irq(dwc->irq_gadget);
2315
2316 pm_runtime_put(dwc->dev);
2317
2318 return ret;
2319}
2320
2321static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2322{
2323 u32 reg;
2324
2325 /* Enable all but Start and End of Frame IRQs */
2326 reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2327 DWC3_DEVTEN_CMDCMPLTEN |
2328 DWC3_DEVTEN_ERRTICERREN |
2329 DWC3_DEVTEN_WKUPEVTEN |
2330 DWC3_DEVTEN_CONNECTDONEEN |
2331 DWC3_DEVTEN_USBRSTEN |
2332 DWC3_DEVTEN_DISCONNEVTEN);
2333
2334 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2335 reg |= DWC3_DEVTEN_ULSTCNGEN;
2336
2337 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2338 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2339 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2340
2341 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2342}
2343
2344static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2345{
2346 /* mask all interrupts */
2347 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2348}
2349
2350static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2351static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2352
2353/**
2354 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2355 * @dwc: pointer to our context structure
2356 *
2357 * The following looks like complex but it's actually very simple. In order to
2358 * calculate the number of packets we can burst at once on OUT transfers, we're
2359 * gonna use RxFIFO size.
2360 *
2361 * To calculate RxFIFO size we need two numbers:
2362 * MDWIDTH = size, in bits, of the internal memory bus
2363 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2364 *
2365 * Given these two numbers, the formula is simple:
2366 *
2367 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2368 *
2369 * 24 bytes is for 3x SETUP packets
2370 * 16 bytes is a clock domain crossing tolerance
2371 *
2372 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2373 */
2374static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2375{
2376 u32 ram2_depth;
2377 u32 mdwidth;
2378 u32 nump;
2379 u32 reg;
2380
2381 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2382 mdwidth = dwc3_mdwidth(dwc);
2383
2384 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2385 nump = min_t(u32, nump, 16);
2386
2387 /* update NumP */
2388 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2389 reg &= ~DWC3_DCFG_NUMP_MASK;
2390 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2391 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2392}
2393
2394static int __dwc3_gadget_start(struct dwc3 *dwc)
2395{
2396 struct dwc3_ep *dep;
2397 int ret = 0;
2398 u32 reg;
2399
2400 /*
2401 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2402 * the core supports IMOD, disable it.
2403 */
2404 if (dwc->imod_interval) {
2405 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2406 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2407 } else if (dwc3_has_imod(dwc)) {
2408 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2409 }
2410
2411 /*
2412 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2413 * field instead of letting dwc3 itself calculate that automatically.
2414 *
2415 * This way, we maximize the chances that we'll be able to get several
2416 * bursts of data without going through any sort of endpoint throttling.
2417 */
2418 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2419 if (DWC3_IP_IS(DWC3))
2420 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2421 else
2422 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2423
2424 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2425
2426 dwc3_gadget_setup_nump(dwc);
2427
2428 /*
2429 * Currently the controller handles single stream only. So, Ignore
2430 * Packet Pending bit for stream selection and don't search for another
2431 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2432 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2433 * the stream performance.
2434 */
2435 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2436 reg |= DWC3_DCFG_IGNSTRMPP;
2437 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2438
2439 /* Start with SuperSpeed Default */
2440 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2441
2442 dep = dwc->eps[0];
2443 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2444 if (ret) {
2445 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2446 goto err0;
2447 }
2448
2449 dep = dwc->eps[1];
2450 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2451 if (ret) {
2452 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2453 goto err1;
2454 }
2455
2456 /* begin to receive SETUP packets */
2457 dwc->ep0state = EP0_SETUP_PHASE;
2458 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2459 dwc->delayed_status = false;
2460 dwc3_ep0_out_start(dwc);
2461
2462 dwc3_gadget_enable_irq(dwc);
2463
2464 return 0;
2465
2466err1:
2467 __dwc3_gadget_ep_disable(dwc->eps[0]);
2468
2469err0:
2470 return ret;
2471}
2472
2473static int dwc3_gadget_start(struct usb_gadget *g,
2474 struct usb_gadget_driver *driver)
2475{
2476 struct dwc3 *dwc = gadget_to_dwc(g);
2477 unsigned long flags;
2478 int ret;
2479 int irq;
2480
2481 irq = dwc->irq_gadget;
2482 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2483 IRQF_SHARED, "dwc3", dwc->ev_buf);
2484 if (ret) {
2485 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2486 irq, ret);
2487 return ret;
2488 }
2489
2490 spin_lock_irqsave(&dwc->lock, flags);
2491 dwc->gadget_driver = driver;
2492 spin_unlock_irqrestore(&dwc->lock, flags);
2493
2494 return 0;
2495}
2496
2497static void __dwc3_gadget_stop(struct dwc3 *dwc)
2498{
2499 dwc3_gadget_disable_irq(dwc);
2500 __dwc3_gadget_ep_disable(dwc->eps[0]);
2501 __dwc3_gadget_ep_disable(dwc->eps[1]);
2502}
2503
2504static int dwc3_gadget_stop(struct usb_gadget *g)
2505{
2506 struct dwc3 *dwc = gadget_to_dwc(g);
2507 unsigned long flags;
2508
2509 spin_lock_irqsave(&dwc->lock, flags);
2510 dwc->gadget_driver = NULL;
2511 spin_unlock_irqrestore(&dwc->lock, flags);
2512
2513 free_irq(dwc->irq_gadget, dwc->ev_buf);
2514
2515 return 0;
2516}
2517
2518static void dwc3_gadget_config_params(struct usb_gadget *g,
2519 struct usb_dcd_config_params *params)
2520{
2521 struct dwc3 *dwc = gadget_to_dwc(g);
2522
2523 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2524 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2525
2526 /* Recommended BESL */
2527 if (!dwc->dis_enblslpm_quirk) {
2528 /*
2529 * If the recommended BESL baseline is 0 or if the BESL deep is
2530 * less than 2, Microsoft's Windows 10 host usb stack will issue
2531 * a usb reset immediately after it receives the extended BOS
2532 * descriptor and the enumeration will fail. To maintain
2533 * compatibility with the Windows' usb stack, let's set the
2534 * recommended BESL baseline to 1 and clamp the BESL deep to be
2535 * within 2 to 15.
2536 */
2537 params->besl_baseline = 1;
2538 if (dwc->is_utmi_l1_suspend)
2539 params->besl_deep =
2540 clamp_t(u8, dwc->hird_threshold, 2, 15);
2541 }
2542
2543 /* U1 Device exit Latency */
2544 if (dwc->dis_u1_entry_quirk)
2545 params->bU1devExitLat = 0;
2546 else
2547 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2548
2549 /* U2 Device exit Latency */
2550 if (dwc->dis_u2_entry_quirk)
2551 params->bU2DevExitLat = 0;
2552 else
2553 params->bU2DevExitLat =
2554 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2555}
2556
2557static void dwc3_gadget_set_speed(struct usb_gadget *g,
2558 enum usb_device_speed speed)
2559{
2560 struct dwc3 *dwc = gadget_to_dwc(g);
2561 unsigned long flags;
2562
2563 spin_lock_irqsave(&dwc->lock, flags);
2564 dwc->gadget_max_speed = speed;
2565 spin_unlock_irqrestore(&dwc->lock, flags);
2566}
2567
2568static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
2569 enum usb_ssp_rate rate)
2570{
2571 struct dwc3 *dwc = gadget_to_dwc(g);
2572 unsigned long flags;
2573
2574 spin_lock_irqsave(&dwc->lock, flags);
2575 dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
2576 dwc->gadget_ssp_rate = rate;
2577 spin_unlock_irqrestore(&dwc->lock, flags);
2578}
2579
2580static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
2581{
2582 struct dwc3 *dwc = gadget_to_dwc(g);
2583 union power_supply_propval val = {0};
2584 int ret;
2585
2586 if (dwc->usb2_phy)
2587 return usb_phy_set_power(dwc->usb2_phy, mA);
2588
2589 if (!dwc->usb_psy)
2590 return -EOPNOTSUPP;
2591
2592 val.intval = 1000 * mA;
2593 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2594
2595 return ret;
2596}
2597
2598static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
2599{
2600 struct dwc3 *dwc = gadget_to_dwc(g);
2601 unsigned long flags;
2602
2603 spin_lock_irqsave(&dwc->lock, flags);
2604 dwc->async_callbacks = enable;
2605 spin_unlock_irqrestore(&dwc->lock, flags);
2606}
2607
2608static const struct usb_gadget_ops dwc3_gadget_ops = {
2609 .get_frame = dwc3_gadget_get_frame,
2610 .wakeup = dwc3_gadget_wakeup,
2611 .set_selfpowered = dwc3_gadget_set_selfpowered,
2612 .pullup = dwc3_gadget_pullup,
2613 .udc_start = dwc3_gadget_start,
2614 .udc_stop = dwc3_gadget_stop,
2615 .udc_set_speed = dwc3_gadget_set_speed,
2616 .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
2617 .get_config_params = dwc3_gadget_config_params,
2618 .vbus_draw = dwc3_gadget_vbus_draw,
2619 .udc_async_callbacks = dwc3_gadget_async_callbacks,
2620};
2621
2622/* -------------------------------------------------------------------------- */
2623
2624static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2625{
2626 struct dwc3 *dwc = dep->dwc;
2627
2628 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2629 dep->endpoint.maxburst = 1;
2630 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2631 if (!dep->direction)
2632 dwc->gadget->ep0 = &dep->endpoint;
2633
2634 dep->endpoint.caps.type_control = true;
2635
2636 return 0;
2637}
2638
2639static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2640{
2641 struct dwc3 *dwc = dep->dwc;
2642 u32 mdwidth;
2643 int size;
2644
2645 mdwidth = dwc3_mdwidth(dwc);
2646
2647 /* MDWIDTH is represented in bits, we need it in bytes */
2648 mdwidth /= 8;
2649
2650 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2651 if (DWC3_IP_IS(DWC3))
2652 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2653 else
2654 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2655
2656 /* FIFO Depth is in MDWDITH bytes. Multiply */
2657 size *= mdwidth;
2658
2659 /*
2660 * To meet performance requirement, a minimum TxFIFO size of 3x
2661 * MaxPacketSize is recommended for endpoints that support burst and a
2662 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2663 * support burst. Use those numbers and we can calculate the max packet
2664 * limit as below.
2665 */
2666 if (dwc->maximum_speed >= USB_SPEED_SUPER)
2667 size /= 3;
2668 else
2669 size /= 2;
2670
2671 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2672
2673 dep->endpoint.max_streams = 16;
2674 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2675 list_add_tail(&dep->endpoint.ep_list,
2676 &dwc->gadget->ep_list);
2677 dep->endpoint.caps.type_iso = true;
2678 dep->endpoint.caps.type_bulk = true;
2679 dep->endpoint.caps.type_int = true;
2680
2681 return dwc3_alloc_trb_pool(dep);
2682}
2683
2684static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2685{
2686 struct dwc3 *dwc = dep->dwc;
2687 u32 mdwidth;
2688 int size;
2689
2690 mdwidth = dwc3_mdwidth(dwc);
2691
2692 /* MDWIDTH is represented in bits, convert to bytes */
2693 mdwidth /= 8;
2694
2695 /* All OUT endpoints share a single RxFIFO space */
2696 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2697 if (DWC3_IP_IS(DWC3))
2698 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2699 else
2700 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2701
2702 /* FIFO depth is in MDWDITH bytes */
2703 size *= mdwidth;
2704
2705 /*
2706 * To meet performance requirement, a minimum recommended RxFIFO size
2707 * is defined as follow:
2708 * RxFIFO size >= (3 x MaxPacketSize) +
2709 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2710 *
2711 * Then calculate the max packet limit as below.
2712 */
2713 size -= (3 * 8) + 16;
2714 if (size < 0)
2715 size = 0;
2716 else
2717 size /= 3;
2718
2719 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2720 dep->endpoint.max_streams = 16;
2721 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2722 list_add_tail(&dep->endpoint.ep_list,
2723 &dwc->gadget->ep_list);
2724 dep->endpoint.caps.type_iso = true;
2725 dep->endpoint.caps.type_bulk = true;
2726 dep->endpoint.caps.type_int = true;
2727
2728 return dwc3_alloc_trb_pool(dep);
2729}
2730
2731static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2732{
2733 struct dwc3_ep *dep;
2734 bool direction = epnum & 1;
2735 int ret;
2736 u8 num = epnum >> 1;
2737
2738 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2739 if (!dep)
2740 return -ENOMEM;
2741
2742 dep->dwc = dwc;
2743 dep->number = epnum;
2744 dep->direction = direction;
2745 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2746 dwc->eps[epnum] = dep;
2747 dep->combo_num = 0;
2748 dep->start_cmd_status = 0;
2749
2750 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2751 direction ? "in" : "out");
2752
2753 dep->endpoint.name = dep->name;
2754
2755 if (!(dep->number > 1)) {
2756 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2757 dep->endpoint.comp_desc = NULL;
2758 }
2759
2760 if (num == 0)
2761 ret = dwc3_gadget_init_control_endpoint(dep);
2762 else if (direction)
2763 ret = dwc3_gadget_init_in_endpoint(dep);
2764 else
2765 ret = dwc3_gadget_init_out_endpoint(dep);
2766
2767 if (ret)
2768 return ret;
2769
2770 dep->endpoint.caps.dir_in = direction;
2771 dep->endpoint.caps.dir_out = !direction;
2772
2773 INIT_LIST_HEAD(&dep->pending_list);
2774 INIT_LIST_HEAD(&dep->started_list);
2775 INIT_LIST_HEAD(&dep->cancelled_list);
2776
2777 dwc3_debugfs_create_endpoint_dir(dep);
2778
2779 return 0;
2780}
2781
2782static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2783{
2784 u8 epnum;
2785
2786 INIT_LIST_HEAD(&dwc->gadget->ep_list);
2787
2788 for (epnum = 0; epnum < total; epnum++) {
2789 int ret;
2790
2791 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2792 if (ret)
2793 return ret;
2794 }
2795
2796 return 0;
2797}
2798
2799static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2800{
2801 struct dwc3_ep *dep;
2802 u8 epnum;
2803
2804 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2805 dep = dwc->eps[epnum];
2806 if (!dep)
2807 continue;
2808 /*
2809 * Physical endpoints 0 and 1 are special; they form the
2810 * bi-directional USB endpoint 0.
2811 *
2812 * For those two physical endpoints, we don't allocate a TRB
2813 * pool nor do we add them the endpoints list. Due to that, we
2814 * shouldn't do these two operations otherwise we would end up
2815 * with all sorts of bugs when removing dwc3.ko.
2816 */
2817 if (epnum != 0 && epnum != 1) {
2818 dwc3_free_trb_pool(dep);
2819 list_del(&dep->endpoint.ep_list);
2820 }
2821
2822 debugfs_remove_recursive(debugfs_lookup(dep->name,
2823 debugfs_lookup(dev_name(dep->dwc->dev),
2824 usb_debug_root)));
2825 kfree(dep);
2826 }
2827}
2828
2829/* -------------------------------------------------------------------------- */
2830
2831static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2832 struct dwc3_request *req, struct dwc3_trb *trb,
2833 const struct dwc3_event_depevt *event, int status, int chain)
2834{
2835 unsigned int count;
2836
2837 dwc3_ep_inc_deq(dep);
2838
2839 trace_dwc3_complete_trb(dep, trb);
2840 req->num_trbs--;
2841
2842 /*
2843 * If we're in the middle of series of chained TRBs and we
2844 * receive a short transfer along the way, DWC3 will skip
2845 * through all TRBs including the last TRB in the chain (the
2846 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2847 * bit and SW has to do it manually.
2848 *
2849 * We're going to do that here to avoid problems of HW trying
2850 * to use bogus TRBs for transfers.
2851 */
2852 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2853 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2854
2855 /*
2856 * For isochronous transfers, the first TRB in a service interval must
2857 * have the Isoc-First type. Track and report its interval frame number.
2858 */
2859 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2860 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2861 unsigned int frame_number;
2862
2863 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2864 frame_number &= ~(dep->interval - 1);
2865 req->request.frame_number = frame_number;
2866 }
2867
2868 /*
2869 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
2870 * this TRB points to the bounce buffer address, it's a MPS alignment
2871 * TRB. Don't add it to req->remaining calculation.
2872 */
2873 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
2874 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
2875 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2876 return 1;
2877 }
2878
2879 count = trb->size & DWC3_TRB_SIZE_MASK;
2880 req->remaining += count;
2881
2882 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2883 return 1;
2884
2885 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2886 return 1;
2887
2888 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
2889 (trb->ctrl & DWC3_TRB_CTRL_LST))
2890 return 1;
2891
2892 return 0;
2893}
2894
2895static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2896 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2897 int status)
2898{
2899 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2900 struct scatterlist *sg = req->sg;
2901 struct scatterlist *s;
2902 unsigned int num_queued = req->num_queued_sgs;
2903 unsigned int i;
2904 int ret = 0;
2905
2906 for_each_sg(sg, s, num_queued, i) {
2907 trb = &dep->trb_pool[dep->trb_dequeue];
2908
2909 req->sg = sg_next(s);
2910 req->num_queued_sgs--;
2911
2912 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2913 trb, event, status, true);
2914 if (ret)
2915 break;
2916 }
2917
2918 return ret;
2919}
2920
2921static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2922 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2923 int status)
2924{
2925 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2926
2927 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2928 event, status, false);
2929}
2930
2931static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2932{
2933 return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
2934}
2935
2936static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2937 const struct dwc3_event_depevt *event,
2938 struct dwc3_request *req, int status)
2939{
2940 int ret;
2941
2942 if (req->request.num_mapped_sgs)
2943 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2944 status);
2945 else
2946 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2947 status);
2948
2949 req->request.actual = req->request.length - req->remaining;
2950
2951 if (!dwc3_gadget_ep_request_completed(req))
2952 goto out;
2953
2954 if (req->needs_extra_trb) {
2955 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2956 status);
2957 req->needs_extra_trb = false;
2958 }
2959
2960 dwc3_gadget_giveback(dep, req, status);
2961
2962out:
2963 return ret;
2964}
2965
2966static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2967 const struct dwc3_event_depevt *event, int status)
2968{
2969 struct dwc3_request *req;
2970 struct dwc3_request *tmp;
2971
2972 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2973 int ret;
2974
2975 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2976 req, status);
2977 if (ret)
2978 break;
2979 }
2980}
2981
2982static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
2983{
2984 struct dwc3_request *req;
2985 struct dwc3 *dwc = dep->dwc;
2986
2987 if (!dep->endpoint.desc || !dwc->pullups_connected ||
2988 !dwc->connected)
2989 return false;
2990
2991 if (!list_empty(&dep->pending_list))
2992 return true;
2993
2994 /*
2995 * We only need to check the first entry of the started list. We can
2996 * assume the completed requests are removed from the started list.
2997 */
2998 req = next_request(&dep->started_list);
2999 if (!req)
3000 return false;
3001
3002 return !dwc3_gadget_ep_request_completed(req);
3003}
3004
3005static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3006 const struct dwc3_event_depevt *event)
3007{
3008 dep->frame_number = event->parameters;
3009}
3010
3011static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3012 const struct dwc3_event_depevt *event, int status)
3013{
3014 struct dwc3 *dwc = dep->dwc;
3015 bool no_started_trb = true;
3016
3017 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3018
3019 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3020 goto out;
3021
3022 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3023 list_empty(&dep->started_list) &&
3024 (list_empty(&dep->pending_list) || status == -EXDEV))
3025 dwc3_stop_active_transfer(dep, true, true);
3026 else if (dwc3_gadget_ep_should_continue(dep))
3027 if (__dwc3_gadget_kick_transfer(dep) == 0)
3028 no_started_trb = false;
3029
3030out:
3031 /*
3032 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3033 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3034 */
3035 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3036 u32 reg;
3037 int i;
3038
3039 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3040 dep = dwc->eps[i];
3041
3042 if (!(dep->flags & DWC3_EP_ENABLED))
3043 continue;
3044
3045 if (!list_empty(&dep->started_list))
3046 return no_started_trb;
3047 }
3048
3049 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3050 reg |= dwc->u1u2;
3051 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3052
3053 dwc->u1u2 = 0;
3054 }
3055
3056 return no_started_trb;
3057}
3058
3059static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3060 const struct dwc3_event_depevt *event)
3061{
3062 int status = 0;
3063
3064 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3065 dwc3_gadget_endpoint_frame_from_event(dep, event);
3066
3067 if (event->status & DEPEVT_STATUS_BUSERR)
3068 status = -ECONNRESET;
3069
3070 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3071 status = -EXDEV;
3072
3073 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3074}
3075
3076static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3077 const struct dwc3_event_depevt *event)
3078{
3079 int status = 0;
3080
3081 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3082
3083 if (event->status & DEPEVT_STATUS_BUSERR)
3084 status = -ECONNRESET;
3085
3086 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3087 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3088}
3089
3090static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3091 const struct dwc3_event_depevt *event)
3092{
3093 dwc3_gadget_endpoint_frame_from_event(dep, event);
3094
3095 /*
3096 * The XferNotReady event is generated only once before the endpoint
3097 * starts. It will be generated again when END_TRANSFER command is
3098 * issued. For some controller versions, the XferNotReady event may be
3099 * generated while the END_TRANSFER command is still in process. Ignore
3100 * it and wait for the next XferNotReady event after the command is
3101 * completed.
3102 */
3103 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3104 return;
3105
3106 (void) __dwc3_gadget_start_isoc(dep);
3107}
3108
3109static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3110 const struct dwc3_event_depevt *event)
3111{
3112 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3113
3114 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3115 return;
3116
3117 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3118 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3119 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3120
3121 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3122 struct dwc3 *dwc = dep->dwc;
3123
3124 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3125 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3126 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3127
3128 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3129 if (dwc->delayed_status)
3130 __dwc3_gadget_ep0_set_halt(ep0, 1);
3131 return;
3132 }
3133
3134 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3135 if (dwc->delayed_status)
3136 dwc3_ep0_send_delayed_status(dwc);
3137 }
3138
3139 if ((dep->flags & DWC3_EP_DELAY_START) &&
3140 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3141 __dwc3_gadget_kick_transfer(dep);
3142
3143 dep->flags &= ~DWC3_EP_DELAY_START;
3144}
3145
3146static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3147 const struct dwc3_event_depevt *event)
3148{
3149 struct dwc3 *dwc = dep->dwc;
3150
3151 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3152 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3153 goto out;
3154 }
3155
3156 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3157 switch (event->parameters) {
3158 case DEPEVT_STREAM_PRIME:
3159 /*
3160 * If the host can properly transition the endpoint state from
3161 * idle to prime after a NoStream rejection, there's no need to
3162 * force restarting the endpoint to reinitiate the stream. To
3163 * simplify the check, assume the host follows the USB spec if
3164 * it primed the endpoint more than once.
3165 */
3166 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3167 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3168 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3169 else
3170 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3171 }
3172
3173 break;
3174 case DEPEVT_STREAM_NOSTREAM:
3175 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3176 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3177 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
3178 break;
3179
3180 /*
3181 * If the host rejects a stream due to no active stream, by the
3182 * USB and xHCI spec, the endpoint will be put back to idle
3183 * state. When the host is ready (buffer added/updated), it will
3184 * prime the endpoint to inform the usb device controller. This
3185 * triggers the device controller to issue ERDY to restart the
3186 * stream. However, some hosts don't follow this and keep the
3187 * endpoint in the idle state. No prime will come despite host
3188 * streams are updated, and the device controller will not be
3189 * triggered to generate ERDY to move the next stream data. To
3190 * workaround this and maintain compatibility with various
3191 * hosts, force to reinitate the stream until the host is ready
3192 * instead of waiting for the host to prime the endpoint.
3193 */
3194 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3195 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3196
3197 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3198 } else {
3199 dep->flags |= DWC3_EP_DELAY_START;
3200 dwc3_stop_active_transfer(dep, true, true);
3201 return;
3202 }
3203 break;
3204 }
3205
3206out:
3207 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3208}
3209
3210static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3211 const struct dwc3_event_depevt *event)
3212{
3213 struct dwc3_ep *dep;
3214 u8 epnum = event->endpoint_number;
3215
3216 dep = dwc->eps[epnum];
3217
3218 if (!(dep->flags & DWC3_EP_ENABLED)) {
3219 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3220 return;
3221
3222 /* Handle only EPCMDCMPLT when EP disabled */
3223 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3224 return;
3225 }
3226
3227 if (epnum == 0 || epnum == 1) {
3228 dwc3_ep0_interrupt(dwc, event);
3229 return;
3230 }
3231
3232 switch (event->endpoint_event) {
3233 case DWC3_DEPEVT_XFERINPROGRESS:
3234 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3235 break;
3236 case DWC3_DEPEVT_XFERNOTREADY:
3237 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3238 break;
3239 case DWC3_DEPEVT_EPCMDCMPLT:
3240 dwc3_gadget_endpoint_command_complete(dep, event);
3241 break;
3242 case DWC3_DEPEVT_XFERCOMPLETE:
3243 dwc3_gadget_endpoint_transfer_complete(dep, event);
3244 break;
3245 case DWC3_DEPEVT_STREAMEVT:
3246 dwc3_gadget_endpoint_stream_event(dep, event);
3247 break;
3248 case DWC3_DEPEVT_RXTXFIFOEVT:
3249 break;
3250 }
3251}
3252
3253static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3254{
3255 if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3256 spin_unlock(&dwc->lock);
3257 dwc->gadget_driver->disconnect(dwc->gadget);
3258 spin_lock(&dwc->lock);
3259 }
3260}
3261
3262static void dwc3_suspend_gadget(struct dwc3 *dwc)
3263{
3264 if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3265 spin_unlock(&dwc->lock);
3266 dwc->gadget_driver->suspend(dwc->gadget);
3267 spin_lock(&dwc->lock);
3268 }
3269}
3270
3271static void dwc3_resume_gadget(struct dwc3 *dwc)
3272{
3273 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3274 spin_unlock(&dwc->lock);
3275 dwc->gadget_driver->resume(dwc->gadget);
3276 spin_lock(&dwc->lock);
3277 }
3278}
3279
3280static void dwc3_reset_gadget(struct dwc3 *dwc)
3281{
3282 if (!dwc->gadget_driver)
3283 return;
3284
3285 if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3286 spin_unlock(&dwc->lock);
3287 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3288 spin_lock(&dwc->lock);
3289 }
3290}
3291
3292static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3293 bool interrupt)
3294{
3295 struct dwc3_gadget_ep_cmd_params params;
3296 u32 cmd;
3297 int ret;
3298
3299 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3300 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3301 return;
3302
3303 /*
3304 * NOTICE: We are violating what the Databook says about the
3305 * EndTransfer command. Ideally we would _always_ wait for the
3306 * EndTransfer Command Completion IRQ, but that's causing too
3307 * much trouble synchronizing between us and gadget driver.
3308 *
3309 * We have discussed this with the IP Provider and it was
3310 * suggested to giveback all requests here.
3311 *
3312 * Note also that a similar handling was tested by Synopsys
3313 * (thanks a lot Paul) and nothing bad has come out of it.
3314 * In short, what we're doing is issuing EndTransfer with
3315 * CMDIOC bit set and delay kicking transfer until the
3316 * EndTransfer command had completed.
3317 *
3318 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3319 * supports a mode to work around the above limitation. The
3320 * software can poll the CMDACT bit in the DEPCMD register
3321 * after issuing a EndTransfer command. This mode is enabled
3322 * by writing GUCTL2[14]. This polling is already done in the
3323 * dwc3_send_gadget_ep_cmd() function so if the mode is
3324 * enabled, the EndTransfer command will have completed upon
3325 * returning from this function.
3326 *
3327 * This mode is NOT available on the DWC_usb31 IP.
3328 */
3329
3330 cmd = DWC3_DEPCMD_ENDTRANSFER;
3331 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
3332 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
3333 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3334 memset(¶ms, 0, sizeof(params));
3335 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
3336 WARN_ON_ONCE(ret);
3337 dep->resource_index = 0;
3338
3339 /*
3340 * The END_TRANSFER command will cause the controller to generate a
3341 * NoStream Event, and it's not due to the host DP NoStream rejection.
3342 * Ignore the next NoStream event.
3343 */
3344 if (dep->stream_capable)
3345 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3346
3347 if (!interrupt)
3348 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3349 else
3350 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
3351}
3352
3353static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3354{
3355 u32 epnum;
3356
3357 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3358 struct dwc3_ep *dep;
3359 int ret;
3360
3361 dep = dwc->eps[epnum];
3362 if (!dep)
3363 continue;
3364
3365 if (!(dep->flags & DWC3_EP_STALL))
3366 continue;
3367
3368 dep->flags &= ~DWC3_EP_STALL;
3369
3370 ret = dwc3_send_clear_stall_ep_cmd(dep);
3371 WARN_ON_ONCE(ret);
3372 }
3373}
3374
3375static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3376{
3377 int reg;
3378
3379 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3380
3381 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3382 reg &= ~DWC3_DCTL_INITU1ENA;
3383 reg &= ~DWC3_DCTL_INITU2ENA;
3384 dwc3_gadget_dctl_write_safe(dwc, reg);
3385
3386 dwc3_disconnect_gadget(dwc);
3387
3388 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3389 dwc->setup_packet_pending = false;
3390 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3391
3392 dwc->connected = false;
3393}
3394
3395static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3396{
3397 u32 reg;
3398
3399 /*
3400 * Ideally, dwc3_reset_gadget() would trigger the function
3401 * drivers to stop any active transfers through ep disable.
3402 * However, for functions which defer ep disable, such as mass
3403 * storage, we will need to rely on the call to stop active
3404 * transfers here, and avoid allowing of request queuing.
3405 */
3406 dwc->connected = false;
3407
3408 /*
3409 * WORKAROUND: DWC3 revisions <1.88a have an issue which
3410 * would cause a missing Disconnect Event if there's a
3411 * pending Setup Packet in the FIFO.
3412 *
3413 * There's no suggested workaround on the official Bug
3414 * report, which states that "unless the driver/application
3415 * is doing any special handling of a disconnect event,
3416 * there is no functional issue".
3417 *
3418 * Unfortunately, it turns out that we _do_ some special
3419 * handling of a disconnect event, namely complete all
3420 * pending transfers, notify gadget driver of the
3421 * disconnection, and so on.
3422 *
3423 * Our suggested workaround is to follow the Disconnect
3424 * Event steps here, instead, based on a setup_packet_pending
3425 * flag. Such flag gets set whenever we have a SETUP_PENDING
3426 * status for EP0 TRBs and gets cleared on XferComplete for the
3427 * same endpoint.
3428 *
3429 * Refers to:
3430 *
3431 * STAR#9000466709: RTL: Device : Disconnect event not
3432 * generated if setup packet pending in FIFO
3433 */
3434 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3435 if (dwc->setup_packet_pending)
3436 dwc3_gadget_disconnect_interrupt(dwc);
3437 }
3438
3439 dwc3_reset_gadget(dwc);
3440 /*
3441 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3442 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3443 * needs to ensure that it sends "a DEPENDXFER command for any active
3444 * transfers."
3445 */
3446 dwc3_stop_active_transfers(dwc);
3447 dwc->connected = true;
3448
3449 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3450 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3451 dwc3_gadget_dctl_write_safe(dwc, reg);
3452 dwc->test_mode = false;
3453 dwc3_clear_stall_all_ep(dwc);
3454
3455 /* Reset device address to zero */
3456 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3457 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3458 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3459}
3460
3461static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3462{
3463 struct dwc3_ep *dep;
3464 int ret;
3465 u32 reg;
3466 u8 lanes = 1;
3467 u8 speed;
3468
3469 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3470 speed = reg & DWC3_DSTS_CONNECTSPD;
3471 dwc->speed = speed;
3472
3473 if (DWC3_IP_IS(DWC32))
3474 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
3475
3476 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3477
3478 /*
3479 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3480 * each time on Connect Done.
3481 *
3482 * Currently we always use the reset value. If any platform
3483 * wants to set this to a different value, we need to add a
3484 * setting and update GCTL.RAMCLKSEL here.
3485 */
3486
3487 switch (speed) {
3488 case DWC3_DSTS_SUPERSPEED_PLUS:
3489 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3490 dwc->gadget->ep0->maxpacket = 512;
3491 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3492
3493 if (lanes > 1)
3494 dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
3495 else
3496 dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
3497 break;
3498 case DWC3_DSTS_SUPERSPEED:
3499 /*
3500 * WORKAROUND: DWC3 revisions <1.90a have an issue which
3501 * would cause a missing USB3 Reset event.
3502 *
3503 * In such situations, we should force a USB3 Reset
3504 * event by calling our dwc3_gadget_reset_interrupt()
3505 * routine.
3506 *
3507 * Refers to:
3508 *
3509 * STAR#9000483510: RTL: SS : USB3 reset event may
3510 * not be generated always when the link enters poll
3511 */
3512 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3513 dwc3_gadget_reset_interrupt(dwc);
3514
3515 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3516 dwc->gadget->ep0->maxpacket = 512;
3517 dwc->gadget->speed = USB_SPEED_SUPER;
3518
3519 if (lanes > 1) {
3520 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3521 dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
3522 }
3523 break;
3524 case DWC3_DSTS_HIGHSPEED:
3525 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3526 dwc->gadget->ep0->maxpacket = 64;
3527 dwc->gadget->speed = USB_SPEED_HIGH;
3528 break;
3529 case DWC3_DSTS_FULLSPEED:
3530 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3531 dwc->gadget->ep0->maxpacket = 64;
3532 dwc->gadget->speed = USB_SPEED_FULL;
3533 break;
3534 }
3535
3536 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3537
3538 /* Enable USB2 LPM Capability */
3539
3540 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3541 !dwc->usb2_gadget_lpm_disable &&
3542 (speed != DWC3_DSTS_SUPERSPEED) &&
3543 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3544 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3545 reg |= DWC3_DCFG_LPM_CAP;
3546 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3547
3548 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3549 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3550
3551 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3552 (dwc->is_utmi_l1_suspend << 4));
3553
3554 /*
3555 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3556 * DCFG.LPMCap is set, core responses with an ACK and the
3557 * BESL value in the LPM token is less than or equal to LPM
3558 * NYET threshold.
3559 */
3560 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3561 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3562
3563 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3564 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3565
3566 dwc3_gadget_dctl_write_safe(dwc, reg);
3567 } else {
3568 if (dwc->usb2_gadget_lpm_disable) {
3569 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3570 reg &= ~DWC3_DCFG_LPM_CAP;
3571 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3572 }
3573
3574 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3575 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3576 dwc3_gadget_dctl_write_safe(dwc, reg);
3577 }
3578
3579 dep = dwc->eps[0];
3580 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3581 if (ret) {
3582 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3583 return;
3584 }
3585
3586 dep = dwc->eps[1];
3587 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3588 if (ret) {
3589 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3590 return;
3591 }
3592
3593 /*
3594 * Configure PHY via GUSB3PIPECTLn if required.
3595 *
3596 * Update GTXFIFOSIZn
3597 *
3598 * In both cases reset values should be sufficient.
3599 */
3600}
3601
3602static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3603{
3604 /*
3605 * TODO take core out of low power mode when that's
3606 * implemented.
3607 */
3608
3609 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3610 spin_unlock(&dwc->lock);
3611 dwc->gadget_driver->resume(dwc->gadget);
3612 spin_lock(&dwc->lock);
3613 }
3614}
3615
3616static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3617 unsigned int evtinfo)
3618{
3619 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3620 unsigned int pwropt;
3621
3622 /*
3623 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3624 * Hibernation mode enabled which would show up when device detects
3625 * host-initiated U3 exit.
3626 *
3627 * In that case, device will generate a Link State Change Interrupt
3628 * from U3 to RESUME which is only necessary if Hibernation is
3629 * configured in.
3630 *
3631 * There are no functional changes due to such spurious event and we
3632 * just need to ignore it.
3633 *
3634 * Refers to:
3635 *
3636 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3637 * operational mode
3638 */
3639 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3640 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3641 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3642 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3643 (next == DWC3_LINK_STATE_RESUME)) {
3644 return;
3645 }
3646 }
3647
3648 /*
3649 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3650 * on the link partner, the USB session might do multiple entry/exit
3651 * of low power states before a transfer takes place.
3652 *
3653 * Due to this problem, we might experience lower throughput. The
3654 * suggested workaround is to disable DCTL[12:9] bits if we're
3655 * transitioning from U1/U2 to U0 and enable those bits again
3656 * after a transfer completes and there are no pending transfers
3657 * on any of the enabled endpoints.
3658 *
3659 * This is the first half of that workaround.
3660 *
3661 * Refers to:
3662 *
3663 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3664 * core send LGO_Ux entering U0
3665 */
3666 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3667 if (next == DWC3_LINK_STATE_U0) {
3668 u32 u1u2;
3669 u32 reg;
3670
3671 switch (dwc->link_state) {
3672 case DWC3_LINK_STATE_U1:
3673 case DWC3_LINK_STATE_U2:
3674 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3675 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3676 | DWC3_DCTL_ACCEPTU2ENA
3677 | DWC3_DCTL_INITU1ENA
3678 | DWC3_DCTL_ACCEPTU1ENA);
3679
3680 if (!dwc->u1u2)
3681 dwc->u1u2 = reg & u1u2;
3682
3683 reg &= ~u1u2;
3684
3685 dwc3_gadget_dctl_write_safe(dwc, reg);
3686 break;
3687 default:
3688 /* do nothing */
3689 break;
3690 }
3691 }
3692 }
3693
3694 switch (next) {
3695 case DWC3_LINK_STATE_U1:
3696 if (dwc->speed == USB_SPEED_SUPER)
3697 dwc3_suspend_gadget(dwc);
3698 break;
3699 case DWC3_LINK_STATE_U2:
3700 case DWC3_LINK_STATE_U3:
3701 dwc3_suspend_gadget(dwc);
3702 break;
3703 case DWC3_LINK_STATE_RESUME:
3704 dwc3_resume_gadget(dwc);
3705 break;
3706 default:
3707 /* do nothing */
3708 break;
3709 }
3710
3711 dwc->link_state = next;
3712}
3713
3714static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3715 unsigned int evtinfo)
3716{
3717 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3718
3719 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3720 dwc3_suspend_gadget(dwc);
3721
3722 dwc->link_state = next;
3723}
3724
3725static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3726 unsigned int evtinfo)
3727{
3728 unsigned int is_ss = evtinfo & BIT(4);
3729
3730 /*
3731 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3732 * have a known issue which can cause USB CV TD.9.23 to fail
3733 * randomly.
3734 *
3735 * Because of this issue, core could generate bogus hibernation
3736 * events which SW needs to ignore.
3737 *
3738 * Refers to:
3739 *
3740 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3741 * Device Fallback from SuperSpeed
3742 */
3743 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3744 return;
3745
3746 /* enter hibernation here */
3747}
3748
3749static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3750 const struct dwc3_event_devt *event)
3751{
3752 switch (event->type) {
3753 case DWC3_DEVICE_EVENT_DISCONNECT:
3754 dwc3_gadget_disconnect_interrupt(dwc);
3755 break;
3756 case DWC3_DEVICE_EVENT_RESET:
3757 dwc3_gadget_reset_interrupt(dwc);
3758 break;
3759 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3760 dwc3_gadget_conndone_interrupt(dwc);
3761 break;
3762 case DWC3_DEVICE_EVENT_WAKEUP:
3763 dwc3_gadget_wakeup_interrupt(dwc);
3764 break;
3765 case DWC3_DEVICE_EVENT_HIBER_REQ:
3766 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3767 "unexpected hibernation event\n"))
3768 break;
3769
3770 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3771 break;
3772 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3773 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3774 break;
3775 case DWC3_DEVICE_EVENT_SUSPEND:
3776 /* It changed to be suspend event for version 2.30a and above */
3777 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
3778 /*
3779 * Ignore suspend event until the gadget enters into
3780 * USB_STATE_CONFIGURED state.
3781 */
3782 if (dwc->gadget->state >= USB_STATE_CONFIGURED)
3783 dwc3_gadget_suspend_interrupt(dwc,
3784 event->event_info);
3785 }
3786 break;
3787 case DWC3_DEVICE_EVENT_SOF:
3788 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3789 case DWC3_DEVICE_EVENT_CMD_CMPL:
3790 case DWC3_DEVICE_EVENT_OVERFLOW:
3791 break;
3792 default:
3793 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3794 }
3795}
3796
3797static void dwc3_process_event_entry(struct dwc3 *dwc,
3798 const union dwc3_event *event)
3799{
3800 trace_dwc3_event(event->raw, dwc);
3801
3802 if (!event->type.is_devspec)
3803 dwc3_endpoint_interrupt(dwc, &event->depevt);
3804 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3805 dwc3_gadget_interrupt(dwc, &event->devt);
3806 else
3807 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3808}
3809
3810static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3811{
3812 struct dwc3 *dwc = evt->dwc;
3813 irqreturn_t ret = IRQ_NONE;
3814 int left;
3815 u32 reg;
3816
3817 left = evt->count;
3818
3819 if (!(evt->flags & DWC3_EVENT_PENDING))
3820 return IRQ_NONE;
3821
3822 while (left > 0) {
3823 union dwc3_event event;
3824
3825 event.raw = *(u32 *) (evt->cache + evt->lpos);
3826
3827 dwc3_process_event_entry(dwc, &event);
3828
3829 /*
3830 * FIXME we wrap around correctly to the next entry as
3831 * almost all entries are 4 bytes in size. There is one
3832 * entry which has 12 bytes which is a regular entry
3833 * followed by 8 bytes data. ATM I don't know how
3834 * things are organized if we get next to the a
3835 * boundary so I worry about that once we try to handle
3836 * that.
3837 */
3838 evt->lpos = (evt->lpos + 4) % evt->length;
3839 left -= 4;
3840 }
3841
3842 evt->count = 0;
3843 evt->flags &= ~DWC3_EVENT_PENDING;
3844 ret = IRQ_HANDLED;
3845
3846 /* Unmask interrupt */
3847 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3848 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3849 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3850
3851 if (dwc->imod_interval) {
3852 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3853 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3854 }
3855
3856 return ret;
3857}
3858
3859static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3860{
3861 struct dwc3_event_buffer *evt = _evt;
3862 struct dwc3 *dwc = evt->dwc;
3863 unsigned long flags;
3864 irqreturn_t ret = IRQ_NONE;
3865
3866 spin_lock_irqsave(&dwc->lock, flags);
3867 ret = dwc3_process_event_buf(evt);
3868 spin_unlock_irqrestore(&dwc->lock, flags);
3869
3870 return ret;
3871}
3872
3873static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3874{
3875 struct dwc3 *dwc = evt->dwc;
3876 u32 amount;
3877 u32 count;
3878 u32 reg;
3879
3880 if (pm_runtime_suspended(dwc->dev)) {
3881 pm_runtime_get(dwc->dev);
3882 disable_irq_nosync(dwc->irq_gadget);
3883 dwc->pending_events = true;
3884 return IRQ_HANDLED;
3885 }
3886
3887 /*
3888 * With PCIe legacy interrupt, test shows that top-half irq handler can
3889 * be called again after HW interrupt deassertion. Check if bottom-half
3890 * irq event handler completes before caching new event to prevent
3891 * losing events.
3892 */
3893 if (evt->flags & DWC3_EVENT_PENDING)
3894 return IRQ_HANDLED;
3895
3896 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3897 count &= DWC3_GEVNTCOUNT_MASK;
3898 if (!count)
3899 return IRQ_NONE;
3900
3901 evt->count = count;
3902 evt->flags |= DWC3_EVENT_PENDING;
3903
3904 /* Mask interrupt */
3905 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3906 reg |= DWC3_GEVNTSIZ_INTMASK;
3907 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3908
3909 amount = min(count, evt->length - evt->lpos);
3910 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3911
3912 if (amount < count)
3913 memcpy(evt->cache, evt->buf, count - amount);
3914
3915 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3916
3917 return IRQ_WAKE_THREAD;
3918}
3919
3920static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3921{
3922 struct dwc3_event_buffer *evt = _evt;
3923
3924 return dwc3_check_event_buf(evt);
3925}
3926
3927static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3928{
3929 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3930 int irq;
3931
3932 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3933 if (irq > 0)
3934 goto out;
3935
3936 if (irq == -EPROBE_DEFER)
3937 goto out;
3938
3939 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3940 if (irq > 0)
3941 goto out;
3942
3943 if (irq == -EPROBE_DEFER)
3944 goto out;
3945
3946 irq = platform_get_irq(dwc3_pdev, 0);
3947 if (irq > 0)
3948 goto out;
3949
3950 if (!irq)
3951 irq = -EINVAL;
3952
3953out:
3954 return irq;
3955}
3956
3957static void dwc_gadget_release(struct device *dev)
3958{
3959 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
3960
3961 kfree(gadget);
3962}
3963
3964/**
3965 * dwc3_gadget_init - initializes gadget related registers
3966 * @dwc: pointer to our controller context structure
3967 *
3968 * Returns 0 on success otherwise negative errno.
3969 */
3970int dwc3_gadget_init(struct dwc3 *dwc)
3971{
3972 int ret;
3973 int irq;
3974 struct device *dev;
3975
3976 irq = dwc3_gadget_get_irq(dwc);
3977 if (irq < 0) {
3978 ret = irq;
3979 goto err0;
3980 }
3981
3982 dwc->irq_gadget = irq;
3983
3984 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3985 sizeof(*dwc->ep0_trb) * 2,
3986 &dwc->ep0_trb_addr, GFP_KERNEL);
3987 if (!dwc->ep0_trb) {
3988 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3989 ret = -ENOMEM;
3990 goto err0;
3991 }
3992
3993 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3994 if (!dwc->setup_buf) {
3995 ret = -ENOMEM;
3996 goto err1;
3997 }
3998
3999 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4000 &dwc->bounce_addr, GFP_KERNEL);
4001 if (!dwc->bounce) {
4002 ret = -ENOMEM;
4003 goto err2;
4004 }
4005
4006 init_completion(&dwc->ep0_in_setup);
4007 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4008 if (!dwc->gadget) {
4009 ret = -ENOMEM;
4010 goto err3;
4011 }
4012
4013
4014 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4015 dev = &dwc->gadget->dev;
4016 dev->platform_data = dwc;
4017 dwc->gadget->ops = &dwc3_gadget_ops;
4018 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4019 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4020 dwc->gadget->sg_supported = true;
4021 dwc->gadget->name = "dwc3-gadget";
4022 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
4023
4024 /*
4025 * FIXME We might be setting max_speed to <SUPER, however versions
4026 * <2.20a of dwc3 have an issue with metastability (documented
4027 * elsewhere in this driver) which tells us we can't set max speed to
4028 * anything lower than SUPER.
4029 *
4030 * Because gadget.max_speed is only used by composite.c and function
4031 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4032 * to happen so we avoid sending SuperSpeed Capability descriptor
4033 * together with our BOS descriptor as that could confuse host into
4034 * thinking we can handle super speed.
4035 *
4036 * Note that, in fact, we won't even support GetBOS requests when speed
4037 * is less than super speed because we don't have means, yet, to tell
4038 * composite.c that we are USB 2.0 + LPM ECN.
4039 */
4040 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4041 !dwc->dis_metastability_quirk)
4042 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4043 dwc->revision);
4044
4045 dwc->gadget->max_speed = dwc->maximum_speed;
4046 dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
4047
4048 /*
4049 * REVISIT: Here we should clear all pending IRQs to be
4050 * sure we're starting from a well known location.
4051 */
4052
4053 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4054 if (ret)
4055 goto err4;
4056
4057 ret = usb_add_gadget(dwc->gadget);
4058 if (ret) {
4059 dev_err(dwc->dev, "failed to add gadget\n");
4060 goto err5;
4061 }
4062
4063 if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4064 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4065 else
4066 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4067
4068 return 0;
4069
4070err5:
4071 dwc3_gadget_free_endpoints(dwc);
4072err4:
4073 usb_put_gadget(dwc->gadget);
4074 dwc->gadget = NULL;
4075err3:
4076 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4077 dwc->bounce_addr);
4078
4079err2:
4080 kfree(dwc->setup_buf);
4081
4082err1:
4083 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4084 dwc->ep0_trb, dwc->ep0_trb_addr);
4085
4086err0:
4087 return ret;
4088}
4089
4090/* -------------------------------------------------------------------------- */
4091
4092void dwc3_gadget_exit(struct dwc3 *dwc)
4093{
4094 if (!dwc->gadget)
4095 return;
4096
4097 usb_del_gadget(dwc->gadget);
4098 dwc3_gadget_free_endpoints(dwc);
4099 usb_put_gadget(dwc->gadget);
4100 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4101 dwc->bounce_addr);
4102 kfree(dwc->setup_buf);
4103 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4104 dwc->ep0_trb, dwc->ep0_trb_addr);
4105}
4106
4107int dwc3_gadget_suspend(struct dwc3 *dwc)
4108{
4109 if (!dwc->gadget_driver)
4110 return 0;
4111
4112 dwc3_gadget_run_stop(dwc, false, false);
4113 dwc3_disconnect_gadget(dwc);
4114 __dwc3_gadget_stop(dwc);
4115
4116 return 0;
4117}
4118
4119int dwc3_gadget_resume(struct dwc3 *dwc)
4120{
4121 int ret;
4122
4123 if (!dwc->gadget_driver)
4124 return 0;
4125
4126 ret = __dwc3_gadget_start(dwc);
4127 if (ret < 0)
4128 goto err0;
4129
4130 ret = dwc3_gadget_run_stop(dwc, true, false);
4131 if (ret < 0)
4132 goto err1;
4133
4134 return 0;
4135
4136err1:
4137 __dwc3_gadget_stop(dwc);
4138
4139err0:
4140 return ret;
4141}
4142
4143void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4144{
4145 if (dwc->pending_events) {
4146 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4147 dwc->pending_events = false;
4148 enable_irq(dwc->irq_gadget);
4149 }
4150}