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1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
33#include "debug.h"
34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
97 int retries = 10000;
98 u32 reg;
99
100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
131 /* wait for a change in DSTS */
132 retries = 10000;
133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
139 udelay(5);
140 }
141
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
144
145 return -ETIMEDOUT;
146}
147
148/**
149 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
150 * @dwc: pointer to our context structure
151 *
152 * This function will a best effort FIFO allocation in order
153 * to improve FIFO usage and throughput, while still allowing
154 * us to enable as many endpoints as possible.
155 *
156 * Keep in mind that this operation will be highly dependent
157 * on the configured size for RAM1 - which contains TxFifo -,
158 * the amount of endpoints enabled on coreConsultant tool, and
159 * the width of the Master Bus.
160 *
161 * In the ideal world, we would always be able to satisfy the
162 * following equation:
163 *
164 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
165 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
166 *
167 * Unfortunately, due to many variables that's not always the case.
168 */
169int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
170{
171 int last_fifo_depth = 0;
172 int ram1_depth;
173 int fifo_size;
174 int mdwidth;
175 int num;
176
177 if (!dwc->needs_fifo_resize)
178 return 0;
179
180 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
181 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
182
183 /* MDWIDTH is represented in bits, we need it in bytes */
184 mdwidth >>= 3;
185
186 /*
187 * FIXME For now we will only allocate 1 wMaxPacketSize space
188 * for each enabled endpoint, later patches will come to
189 * improve this algorithm so that we better use the internal
190 * FIFO space
191 */
192 for (num = 0; num < dwc->num_in_eps; num++) {
193 /* bit0 indicates direction; 1 means IN ep */
194 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
195 int mult = 1;
196 int tmp;
197
198 if (!(dep->flags & DWC3_EP_ENABLED))
199 continue;
200
201 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
202 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
203 mult = 3;
204
205 /*
206 * REVISIT: the following assumes we will always have enough
207 * space available on the FIFO RAM for all possible use cases.
208 * Make sure that's true somehow and change FIFO allocation
209 * accordingly.
210 *
211 * If we have Bulk or Isochronous endpoints, we want
212 * them to be able to be very, very fast. So we're giving
213 * those endpoints a fifo_size which is enough for 3 full
214 * packets
215 */
216 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
217 tmp += mdwidth;
218
219 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
220
221 fifo_size |= (last_fifo_depth << 16);
222
223 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
224 dep->name, last_fifo_depth, fifo_size & 0xffff);
225
226 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
227
228 last_fifo_depth += (fifo_size & 0xffff);
229 }
230
231 return 0;
232}
233
234void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
235 int status)
236{
237 struct dwc3 *dwc = dep->dwc;
238 int i;
239
240 if (req->queued) {
241 i = 0;
242 do {
243 dep->busy_slot++;
244 /*
245 * Skip LINK TRB. We can't use req->trb and check for
246 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
247 * just completed (not the LINK TRB).
248 */
249 if (((dep->busy_slot & DWC3_TRB_MASK) ==
250 DWC3_TRB_NUM- 1) &&
251 usb_endpoint_xfer_isoc(dep->endpoint.desc))
252 dep->busy_slot++;
253 } while(++i < req->request.num_mapped_sgs);
254 req->queued = false;
255 }
256 list_del(&req->list);
257 req->trb = NULL;
258
259 if (req->request.status == -EINPROGRESS)
260 req->request.status = status;
261
262 if (dwc->ep0_bounced && dep->number == 0)
263 dwc->ep0_bounced = false;
264 else
265 usb_gadget_unmap_request(&dwc->gadget, &req->request,
266 req->direction);
267
268 trace_dwc3_gadget_giveback(req);
269
270 spin_unlock(&dwc->lock);
271 usb_gadget_giveback_request(&dep->endpoint, &req->request);
272 spin_lock(&dwc->lock);
273}
274
275int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
276{
277 u32 timeout = 500;
278 u32 reg;
279
280 trace_dwc3_gadget_generic_cmd(cmd, param);
281
282 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
283 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
284
285 do {
286 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
287 if (!(reg & DWC3_DGCMD_CMDACT)) {
288 dwc3_trace(trace_dwc3_gadget,
289 "Command Complete --> %d",
290 DWC3_DGCMD_STATUS(reg));
291 if (DWC3_DGCMD_STATUS(reg))
292 return -EINVAL;
293 return 0;
294 }
295
296 /*
297 * We can't sleep here, because it's also called from
298 * interrupt context.
299 */
300 timeout--;
301 if (!timeout) {
302 dwc3_trace(trace_dwc3_gadget,
303 "Command Timed Out");
304 return -ETIMEDOUT;
305 }
306 udelay(1);
307 } while (1);
308}
309
310int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
311 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
312{
313 struct dwc3_ep *dep = dwc->eps[ep];
314 u32 timeout = 500;
315 u32 reg;
316
317 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
318
319 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
320 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
321 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
322
323 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
324 do {
325 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
326 if (!(reg & DWC3_DEPCMD_CMDACT)) {
327 dwc3_trace(trace_dwc3_gadget,
328 "Command Complete --> %d",
329 DWC3_DEPCMD_STATUS(reg));
330 if (DWC3_DEPCMD_STATUS(reg))
331 return -EINVAL;
332 return 0;
333 }
334
335 /*
336 * We can't sleep here, because it is also called from
337 * interrupt context.
338 */
339 timeout--;
340 if (!timeout) {
341 dwc3_trace(trace_dwc3_gadget,
342 "Command Timed Out");
343 return -ETIMEDOUT;
344 }
345
346 udelay(1);
347 } while (1);
348}
349
350static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
351 struct dwc3_trb *trb)
352{
353 u32 offset = (char *) trb - (char *) dep->trb_pool;
354
355 return dep->trb_pool_dma + offset;
356}
357
358static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
359{
360 struct dwc3 *dwc = dep->dwc;
361
362 if (dep->trb_pool)
363 return 0;
364
365 dep->trb_pool = dma_alloc_coherent(dwc->dev,
366 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
367 &dep->trb_pool_dma, GFP_KERNEL);
368 if (!dep->trb_pool) {
369 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
370 dep->name);
371 return -ENOMEM;
372 }
373
374 return 0;
375}
376
377static void dwc3_free_trb_pool(struct dwc3_ep *dep)
378{
379 struct dwc3 *dwc = dep->dwc;
380
381 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
382 dep->trb_pool, dep->trb_pool_dma);
383
384 dep->trb_pool = NULL;
385 dep->trb_pool_dma = 0;
386}
387
388static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
389
390/**
391 * dwc3_gadget_start_config - Configure EP resources
392 * @dwc: pointer to our controller context structure
393 * @dep: endpoint that is being enabled
394 *
395 * The assignment of transfer resources cannot perfectly follow the
396 * data book due to the fact that the controller driver does not have
397 * all knowledge of the configuration in advance. It is given this
398 * information piecemeal by the composite gadget framework after every
399 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
400 * programming model in this scenario can cause errors. For two
401 * reasons:
402 *
403 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
404 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
405 * multiple interfaces.
406 *
407 * 2) The databook does not mention doing more DEPXFERCFG for new
408 * endpoint on alt setting (8.1.6).
409 *
410 * The following simplified method is used instead:
411 *
412 * All hardware endpoints can be assigned a transfer resource and this
413 * setting will stay persistent until either a core reset or
414 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
415 * do DEPXFERCFG for every hardware endpoint as well. We are
416 * guaranteed that there are as many transfer resources as endpoints.
417 *
418 * This function is called for each endpoint when it is being enabled
419 * but is triggered only when called for EP0-out, which always happens
420 * first, and which should only happen in one of the above conditions.
421 */
422static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
423{
424 struct dwc3_gadget_ep_cmd_params params;
425 u32 cmd;
426 int i;
427 int ret;
428
429 if (dep->number)
430 return 0;
431
432 memset(¶ms, 0x00, sizeof(params));
433 cmd = DWC3_DEPCMD_DEPSTARTCFG;
434
435 ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
436 if (ret)
437 return ret;
438
439 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
440 struct dwc3_ep *dep = dwc->eps[i];
441
442 if (!dep)
443 continue;
444
445 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
446 if (ret)
447 return ret;
448 }
449
450 return 0;
451}
452
453static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
454 const struct usb_endpoint_descriptor *desc,
455 const struct usb_ss_ep_comp_descriptor *comp_desc,
456 bool ignore, bool restore)
457{
458 struct dwc3_gadget_ep_cmd_params params;
459
460 memset(¶ms, 0x00, sizeof(params));
461
462 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
463 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
464
465 /* Burst size is only needed in SuperSpeed mode */
466 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
467 u32 burst = dep->endpoint.maxburst - 1;
468
469 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
470 }
471
472 if (ignore)
473 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
474
475 if (restore) {
476 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
477 params.param2 |= dep->saved_state;
478 }
479
480 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
481 | DWC3_DEPCFG_XFER_NOT_READY_EN;
482
483 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
484 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
485 | DWC3_DEPCFG_STREAM_EVENT_EN;
486 dep->stream_capable = true;
487 }
488
489 if (!usb_endpoint_xfer_control(desc))
490 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
491
492 /*
493 * We are doing 1:1 mapping for endpoints, meaning
494 * Physical Endpoints 2 maps to Logical Endpoint 2 and
495 * so on. We consider the direction bit as part of the physical
496 * endpoint number. So USB endpoint 0x81 is 0x03.
497 */
498 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
499
500 /*
501 * We must use the lower 16 TX FIFOs even though
502 * HW might have more
503 */
504 if (dep->direction)
505 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
506
507 if (desc->bInterval) {
508 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
509 dep->interval = 1 << (desc->bInterval - 1);
510 }
511
512 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
513 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
514}
515
516static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
517{
518 struct dwc3_gadget_ep_cmd_params params;
519
520 memset(¶ms, 0x00, sizeof(params));
521
522 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
523
524 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
525 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
526}
527
528/**
529 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
530 * @dep: endpoint to be initialized
531 * @desc: USB Endpoint Descriptor
532 *
533 * Caller should take care of locking
534 */
535static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
536 const struct usb_endpoint_descriptor *desc,
537 const struct usb_ss_ep_comp_descriptor *comp_desc,
538 bool ignore, bool restore)
539{
540 struct dwc3 *dwc = dep->dwc;
541 u32 reg;
542 int ret;
543
544 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
545
546 if (!(dep->flags & DWC3_EP_ENABLED)) {
547 ret = dwc3_gadget_start_config(dwc, dep);
548 if (ret)
549 return ret;
550 }
551
552 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
553 restore);
554 if (ret)
555 return ret;
556
557 if (!(dep->flags & DWC3_EP_ENABLED)) {
558 struct dwc3_trb *trb_st_hw;
559 struct dwc3_trb *trb_link;
560
561 dep->endpoint.desc = desc;
562 dep->comp_desc = comp_desc;
563 dep->type = usb_endpoint_type(desc);
564 dep->flags |= DWC3_EP_ENABLED;
565
566 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
567 reg |= DWC3_DALEPENA_EP(dep->number);
568 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
569
570 if (!usb_endpoint_xfer_isoc(desc))
571 goto out;
572
573 /* Link TRB for ISOC. The HWO bit is never reset */
574 trb_st_hw = &dep->trb_pool[0];
575
576 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
577 memset(trb_link, 0, sizeof(*trb_link));
578
579 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
580 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
581 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
582 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
583 }
584
585out:
586 switch (usb_endpoint_type(desc)) {
587 case USB_ENDPOINT_XFER_CONTROL:
588 /* don't change name */
589 break;
590 case USB_ENDPOINT_XFER_ISOC:
591 strlcat(dep->name, "-isoc", sizeof(dep->name));
592 break;
593 case USB_ENDPOINT_XFER_BULK:
594 strlcat(dep->name, "-bulk", sizeof(dep->name));
595 break;
596 case USB_ENDPOINT_XFER_INT:
597 strlcat(dep->name, "-int", sizeof(dep->name));
598 break;
599 default:
600 dev_err(dwc->dev, "invalid endpoint transfer type\n");
601 }
602
603 return 0;
604}
605
606static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
607static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
608{
609 struct dwc3_request *req;
610
611 if (!list_empty(&dep->req_queued)) {
612 dwc3_stop_active_transfer(dwc, dep->number, true);
613
614 /* - giveback all requests to gadget driver */
615 while (!list_empty(&dep->req_queued)) {
616 req = next_request(&dep->req_queued);
617
618 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
619 }
620 }
621
622 while (!list_empty(&dep->request_list)) {
623 req = next_request(&dep->request_list);
624
625 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
626 }
627}
628
629/**
630 * __dwc3_gadget_ep_disable - Disables a HW endpoint
631 * @dep: the endpoint to disable
632 *
633 * This function also removes requests which are currently processed ny the
634 * hardware and those which are not yet scheduled.
635 * Caller should take care of locking.
636 */
637static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
638{
639 struct dwc3 *dwc = dep->dwc;
640 u32 reg;
641
642 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
643
644 dwc3_remove_requests(dwc, dep);
645
646 /* make sure HW endpoint isn't stalled */
647 if (dep->flags & DWC3_EP_STALL)
648 __dwc3_gadget_ep_set_halt(dep, 0, false);
649
650 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
651 reg &= ~DWC3_DALEPENA_EP(dep->number);
652 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
653
654 dep->stream_capable = false;
655 dep->endpoint.desc = NULL;
656 dep->comp_desc = NULL;
657 dep->type = 0;
658 dep->flags = 0;
659
660 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
661 dep->number >> 1,
662 (dep->number & 1) ? "in" : "out");
663
664 return 0;
665}
666
667/* -------------------------------------------------------------------------- */
668
669static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
670 const struct usb_endpoint_descriptor *desc)
671{
672 return -EINVAL;
673}
674
675static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
676{
677 return -EINVAL;
678}
679
680/* -------------------------------------------------------------------------- */
681
682static int dwc3_gadget_ep_enable(struct usb_ep *ep,
683 const struct usb_endpoint_descriptor *desc)
684{
685 struct dwc3_ep *dep;
686 struct dwc3 *dwc;
687 unsigned long flags;
688 int ret;
689
690 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
691 pr_debug("dwc3: invalid parameters\n");
692 return -EINVAL;
693 }
694
695 if (!desc->wMaxPacketSize) {
696 pr_debug("dwc3: missing wMaxPacketSize\n");
697 return -EINVAL;
698 }
699
700 dep = to_dwc3_ep(ep);
701 dwc = dep->dwc;
702
703 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
704 "%s is already enabled\n",
705 dep->name))
706 return 0;
707
708 spin_lock_irqsave(&dwc->lock, flags);
709 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
710 spin_unlock_irqrestore(&dwc->lock, flags);
711
712 return ret;
713}
714
715static int dwc3_gadget_ep_disable(struct usb_ep *ep)
716{
717 struct dwc3_ep *dep;
718 struct dwc3 *dwc;
719 unsigned long flags;
720 int ret;
721
722 if (!ep) {
723 pr_debug("dwc3: invalid parameters\n");
724 return -EINVAL;
725 }
726
727 dep = to_dwc3_ep(ep);
728 dwc = dep->dwc;
729
730 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
731 "%s is already disabled\n",
732 dep->name))
733 return 0;
734
735 spin_lock_irqsave(&dwc->lock, flags);
736 ret = __dwc3_gadget_ep_disable(dep);
737 spin_unlock_irqrestore(&dwc->lock, flags);
738
739 return ret;
740}
741
742static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
743 gfp_t gfp_flags)
744{
745 struct dwc3_request *req;
746 struct dwc3_ep *dep = to_dwc3_ep(ep);
747
748 req = kzalloc(sizeof(*req), gfp_flags);
749 if (!req)
750 return NULL;
751
752 req->epnum = dep->number;
753 req->dep = dep;
754
755 trace_dwc3_alloc_request(req);
756
757 return &req->request;
758}
759
760static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
761 struct usb_request *request)
762{
763 struct dwc3_request *req = to_dwc3_request(request);
764
765 trace_dwc3_free_request(req);
766 kfree(req);
767}
768
769/**
770 * dwc3_prepare_one_trb - setup one TRB from one request
771 * @dep: endpoint for which this request is prepared
772 * @req: dwc3_request pointer
773 */
774static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
775 struct dwc3_request *req, dma_addr_t dma,
776 unsigned length, unsigned last, unsigned chain, unsigned node)
777{
778 struct dwc3_trb *trb;
779
780 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
781 dep->name, req, (unsigned long long) dma,
782 length, last ? " last" : "",
783 chain ? " chain" : "");
784
785
786 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
787
788 if (!req->trb) {
789 dwc3_gadget_move_request_queued(req);
790 req->trb = trb;
791 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
792 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
793 }
794
795 dep->free_slot++;
796 /* Skip the LINK-TRB on ISOC */
797 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
798 usb_endpoint_xfer_isoc(dep->endpoint.desc))
799 dep->free_slot++;
800
801 trb->size = DWC3_TRB_SIZE_LENGTH(length);
802 trb->bpl = lower_32_bits(dma);
803 trb->bph = upper_32_bits(dma);
804
805 switch (usb_endpoint_type(dep->endpoint.desc)) {
806 case USB_ENDPOINT_XFER_CONTROL:
807 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
808 break;
809
810 case USB_ENDPOINT_XFER_ISOC:
811 if (!node)
812 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
813 else
814 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
815 break;
816
817 case USB_ENDPOINT_XFER_BULK:
818 case USB_ENDPOINT_XFER_INT:
819 trb->ctrl = DWC3_TRBCTL_NORMAL;
820 break;
821 default:
822 /*
823 * This is only possible with faulty memory because we
824 * checked it already :)
825 */
826 BUG();
827 }
828
829 if (!req->request.no_interrupt && !chain)
830 trb->ctrl |= DWC3_TRB_CTRL_IOC;
831
832 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
833 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
834 trb->ctrl |= DWC3_TRB_CTRL_CSP;
835 } else if (last) {
836 trb->ctrl |= DWC3_TRB_CTRL_LST;
837 }
838
839 if (chain)
840 trb->ctrl |= DWC3_TRB_CTRL_CHN;
841
842 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
843 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
844
845 trb->ctrl |= DWC3_TRB_CTRL_HWO;
846
847 trace_dwc3_prepare_trb(dep, trb);
848}
849
850/*
851 * dwc3_prepare_trbs - setup TRBs from requests
852 * @dep: endpoint for which requests are being prepared
853 * @starting: true if the endpoint is idle and no requests are queued.
854 *
855 * The function goes through the requests list and sets up TRBs for the
856 * transfers. The function returns once there are no more TRBs available or
857 * it runs out of requests.
858 */
859static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
860{
861 struct dwc3_request *req, *n;
862 u32 trbs_left;
863 u32 max;
864 unsigned int last_one = 0;
865
866 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
867
868 /* the first request must not be queued */
869 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
870
871 /* Can't wrap around on a non-isoc EP since there's no link TRB */
872 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
873 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
874 if (trbs_left > max)
875 trbs_left = max;
876 }
877
878 /*
879 * If busy & slot are equal than it is either full or empty. If we are
880 * starting to process requests then we are empty. Otherwise we are
881 * full and don't do anything
882 */
883 if (!trbs_left) {
884 if (!starting)
885 return;
886 trbs_left = DWC3_TRB_NUM;
887 /*
888 * In case we start from scratch, we queue the ISOC requests
889 * starting from slot 1. This is done because we use ring
890 * buffer and have no LST bit to stop us. Instead, we place
891 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
892 * after the first request so we start at slot 1 and have
893 * 7 requests proceed before we hit the first IOC.
894 * Other transfer types don't use the ring buffer and are
895 * processed from the first TRB until the last one. Since we
896 * don't wrap around we have to start at the beginning.
897 */
898 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
899 dep->busy_slot = 1;
900 dep->free_slot = 1;
901 } else {
902 dep->busy_slot = 0;
903 dep->free_slot = 0;
904 }
905 }
906
907 /* The last TRB is a link TRB, not used for xfer */
908 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
909 return;
910
911 list_for_each_entry_safe(req, n, &dep->request_list, list) {
912 unsigned length;
913 dma_addr_t dma;
914 last_one = false;
915
916 if (req->request.num_mapped_sgs > 0) {
917 struct usb_request *request = &req->request;
918 struct scatterlist *sg = request->sg;
919 struct scatterlist *s;
920 int i;
921
922 for_each_sg(sg, s, request->num_mapped_sgs, i) {
923 unsigned chain = true;
924
925 length = sg_dma_len(s);
926 dma = sg_dma_address(s);
927
928 if (i == (request->num_mapped_sgs - 1) ||
929 sg_is_last(s)) {
930 if (list_empty(&dep->request_list))
931 last_one = true;
932 chain = false;
933 }
934
935 trbs_left--;
936 if (!trbs_left)
937 last_one = true;
938
939 if (last_one)
940 chain = false;
941
942 dwc3_prepare_one_trb(dep, req, dma, length,
943 last_one, chain, i);
944
945 if (last_one)
946 break;
947 }
948
949 if (last_one)
950 break;
951 } else {
952 dma = req->request.dma;
953 length = req->request.length;
954 trbs_left--;
955
956 if (!trbs_left)
957 last_one = 1;
958
959 /* Is this the last request? */
960 if (list_is_last(&req->list, &dep->request_list))
961 last_one = 1;
962
963 dwc3_prepare_one_trb(dep, req, dma, length,
964 last_one, false, 0);
965
966 if (last_one)
967 break;
968 }
969 }
970}
971
972static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
973 int start_new)
974{
975 struct dwc3_gadget_ep_cmd_params params;
976 struct dwc3_request *req;
977 struct dwc3 *dwc = dep->dwc;
978 int ret;
979 u32 cmd;
980
981 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
982 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
983 return -EBUSY;
984 }
985
986 /*
987 * If we are getting here after a short-out-packet we don't enqueue any
988 * new requests as we try to set the IOC bit only on the last request.
989 */
990 if (start_new) {
991 if (list_empty(&dep->req_queued))
992 dwc3_prepare_trbs(dep, start_new);
993
994 /* req points to the first request which will be sent */
995 req = next_request(&dep->req_queued);
996 } else {
997 dwc3_prepare_trbs(dep, start_new);
998
999 /*
1000 * req points to the first request where HWO changed from 0 to 1
1001 */
1002 req = next_request(&dep->req_queued);
1003 }
1004 if (!req) {
1005 dep->flags |= DWC3_EP_PENDING_REQUEST;
1006 return 0;
1007 }
1008
1009 memset(¶ms, 0, sizeof(params));
1010
1011 if (start_new) {
1012 params.param0 = upper_32_bits(req->trb_dma);
1013 params.param1 = lower_32_bits(req->trb_dma);
1014 cmd = DWC3_DEPCMD_STARTTRANSFER;
1015 } else {
1016 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1017 }
1018
1019 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1020 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1021 if (ret < 0) {
1022 /*
1023 * FIXME we need to iterate over the list of requests
1024 * here and stop, unmap, free and del each of the linked
1025 * requests instead of what we do now.
1026 */
1027 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1028 req->direction);
1029 list_del(&req->list);
1030 return ret;
1031 }
1032
1033 dep->flags |= DWC3_EP_BUSY;
1034
1035 if (start_new) {
1036 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1037 dep->number);
1038 WARN_ON_ONCE(!dep->resource_index);
1039 }
1040
1041 return 0;
1042}
1043
1044static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1045 struct dwc3_ep *dep, u32 cur_uf)
1046{
1047 u32 uf;
1048
1049 if (list_empty(&dep->request_list)) {
1050 dwc3_trace(trace_dwc3_gadget,
1051 "ISOC ep %s run out for requests",
1052 dep->name);
1053 dep->flags |= DWC3_EP_PENDING_REQUEST;
1054 return;
1055 }
1056
1057 /* 4 micro frames in the future */
1058 uf = cur_uf + dep->interval * 4;
1059
1060 __dwc3_gadget_kick_transfer(dep, uf, 1);
1061}
1062
1063static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1064 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1065{
1066 u32 cur_uf, mask;
1067
1068 mask = ~(dep->interval - 1);
1069 cur_uf = event->parameters & mask;
1070
1071 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1072}
1073
1074static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1075{
1076 struct dwc3 *dwc = dep->dwc;
1077 int ret;
1078
1079 if (!dep->endpoint.desc) {
1080 dwc3_trace(trace_dwc3_gadget,
1081 "trying to queue request %p to disabled %s\n",
1082 &req->request, dep->endpoint.name);
1083 return -ESHUTDOWN;
1084 }
1085
1086 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1087 &req->request, req->dep->name)) {
1088 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1089 &req->request, req->dep->name);
1090 return -EINVAL;
1091 }
1092
1093 req->request.actual = 0;
1094 req->request.status = -EINPROGRESS;
1095 req->direction = dep->direction;
1096 req->epnum = dep->number;
1097
1098 trace_dwc3_ep_queue(req);
1099
1100 /*
1101 * We only add to our list of requests now and
1102 * start consuming the list once we get XferNotReady
1103 * IRQ.
1104 *
1105 * That way, we avoid doing anything that we don't need
1106 * to do now and defer it until the point we receive a
1107 * particular token from the Host side.
1108 *
1109 * This will also avoid Host cancelling URBs due to too
1110 * many NAKs.
1111 */
1112 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1113 dep->direction);
1114 if (ret)
1115 return ret;
1116
1117 list_add_tail(&req->list, &dep->request_list);
1118
1119 /*
1120 * If there are no pending requests and the endpoint isn't already
1121 * busy, we will just start the request straight away.
1122 *
1123 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1124 * little bit faster.
1125 */
1126 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1127 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1128 !(dep->flags & DWC3_EP_BUSY)) {
1129 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1130 goto out;
1131 }
1132
1133 /*
1134 * There are a few special cases:
1135 *
1136 * 1. XferNotReady with empty list of requests. We need to kick the
1137 * transfer here in that situation, otherwise we will be NAKing
1138 * forever. If we get XferNotReady before gadget driver has a
1139 * chance to queue a request, we will ACK the IRQ but won't be
1140 * able to receive the data until the next request is queued.
1141 * The following code is handling exactly that.
1142 *
1143 */
1144 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1145 /*
1146 * If xfernotready is already elapsed and it is a case
1147 * of isoc transfer, then issue END TRANSFER, so that
1148 * you can receive xfernotready again and can have
1149 * notion of current microframe.
1150 */
1151 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1152 if (list_empty(&dep->req_queued)) {
1153 dwc3_stop_active_transfer(dwc, dep->number, true);
1154 dep->flags = DWC3_EP_ENABLED;
1155 }
1156 return 0;
1157 }
1158
1159 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1160 if (!ret)
1161 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1162
1163 goto out;
1164 }
1165
1166 /*
1167 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1168 * kick the transfer here after queuing a request, otherwise the
1169 * core may not see the modified TRB(s).
1170 */
1171 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1172 (dep->flags & DWC3_EP_BUSY) &&
1173 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1174 WARN_ON_ONCE(!dep->resource_index);
1175 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1176 false);
1177 goto out;
1178 }
1179
1180 /*
1181 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1182 * right away, otherwise host will not know we have streams to be
1183 * handled.
1184 */
1185 if (dep->stream_capable)
1186 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1187
1188out:
1189 if (ret && ret != -EBUSY)
1190 dwc3_trace(trace_dwc3_gadget,
1191 "%s: failed to kick transfers\n",
1192 dep->name);
1193 if (ret == -EBUSY)
1194 ret = 0;
1195
1196 return ret;
1197}
1198
1199static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1200 struct usb_request *request)
1201{
1202 dwc3_gadget_ep_free_request(ep, request);
1203}
1204
1205static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1206{
1207 struct dwc3_request *req;
1208 struct usb_request *request;
1209 struct usb_ep *ep = &dep->endpoint;
1210
1211 dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1212 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1213 if (!request)
1214 return -ENOMEM;
1215
1216 request->length = 0;
1217 request->buf = dwc->zlp_buf;
1218 request->complete = __dwc3_gadget_ep_zlp_complete;
1219
1220 req = to_dwc3_request(request);
1221
1222 return __dwc3_gadget_ep_queue(dep, req);
1223}
1224
1225static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1226 gfp_t gfp_flags)
1227{
1228 struct dwc3_request *req = to_dwc3_request(request);
1229 struct dwc3_ep *dep = to_dwc3_ep(ep);
1230 struct dwc3 *dwc = dep->dwc;
1231
1232 unsigned long flags;
1233
1234 int ret;
1235
1236 spin_lock_irqsave(&dwc->lock, flags);
1237 ret = __dwc3_gadget_ep_queue(dep, req);
1238
1239 /*
1240 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1241 * setting request->zero, instead of doing magic, we will just queue an
1242 * extra usb_request ourselves so that it gets handled the same way as
1243 * any other request.
1244 */
1245 if (ret == 0 && request->zero && request->length &&
1246 (request->length % ep->maxpacket == 0))
1247 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1248
1249 spin_unlock_irqrestore(&dwc->lock, flags);
1250
1251 return ret;
1252}
1253
1254static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1255 struct usb_request *request)
1256{
1257 struct dwc3_request *req = to_dwc3_request(request);
1258 struct dwc3_request *r = NULL;
1259
1260 struct dwc3_ep *dep = to_dwc3_ep(ep);
1261 struct dwc3 *dwc = dep->dwc;
1262
1263 unsigned long flags;
1264 int ret = 0;
1265
1266 trace_dwc3_ep_dequeue(req);
1267
1268 spin_lock_irqsave(&dwc->lock, flags);
1269
1270 list_for_each_entry(r, &dep->request_list, list) {
1271 if (r == req)
1272 break;
1273 }
1274
1275 if (r != req) {
1276 list_for_each_entry(r, &dep->req_queued, list) {
1277 if (r == req)
1278 break;
1279 }
1280 if (r == req) {
1281 /* wait until it is processed */
1282 dwc3_stop_active_transfer(dwc, dep->number, true);
1283 goto out1;
1284 }
1285 dev_err(dwc->dev, "request %p was not queued to %s\n",
1286 request, ep->name);
1287 ret = -EINVAL;
1288 goto out0;
1289 }
1290
1291out1:
1292 /* giveback the request */
1293 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1294
1295out0:
1296 spin_unlock_irqrestore(&dwc->lock, flags);
1297
1298 return ret;
1299}
1300
1301int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1302{
1303 struct dwc3_gadget_ep_cmd_params params;
1304 struct dwc3 *dwc = dep->dwc;
1305 int ret;
1306
1307 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1308 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1309 return -EINVAL;
1310 }
1311
1312 memset(¶ms, 0x00, sizeof(params));
1313
1314 if (value) {
1315 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1316 (!list_empty(&dep->req_queued) ||
1317 !list_empty(&dep->request_list)))) {
1318 dwc3_trace(trace_dwc3_gadget,
1319 "%s: pending request, cannot halt\n",
1320 dep->name);
1321 return -EAGAIN;
1322 }
1323
1324 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1325 DWC3_DEPCMD_SETSTALL, ¶ms);
1326 if (ret)
1327 dev_err(dwc->dev, "failed to set STALL on %s\n",
1328 dep->name);
1329 else
1330 dep->flags |= DWC3_EP_STALL;
1331 } else {
1332 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1333 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1334 if (ret)
1335 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1336 dep->name);
1337 else
1338 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1339 }
1340
1341 return ret;
1342}
1343
1344static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1345{
1346 struct dwc3_ep *dep = to_dwc3_ep(ep);
1347 struct dwc3 *dwc = dep->dwc;
1348
1349 unsigned long flags;
1350
1351 int ret;
1352
1353 spin_lock_irqsave(&dwc->lock, flags);
1354 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1355 spin_unlock_irqrestore(&dwc->lock, flags);
1356
1357 return ret;
1358}
1359
1360static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1361{
1362 struct dwc3_ep *dep = to_dwc3_ep(ep);
1363 struct dwc3 *dwc = dep->dwc;
1364 unsigned long flags;
1365 int ret;
1366
1367 spin_lock_irqsave(&dwc->lock, flags);
1368 dep->flags |= DWC3_EP_WEDGE;
1369
1370 if (dep->number == 0 || dep->number == 1)
1371 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1372 else
1373 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1374 spin_unlock_irqrestore(&dwc->lock, flags);
1375
1376 return ret;
1377}
1378
1379/* -------------------------------------------------------------------------- */
1380
1381static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1382 .bLength = USB_DT_ENDPOINT_SIZE,
1383 .bDescriptorType = USB_DT_ENDPOINT,
1384 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1385};
1386
1387static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1388 .enable = dwc3_gadget_ep0_enable,
1389 .disable = dwc3_gadget_ep0_disable,
1390 .alloc_request = dwc3_gadget_ep_alloc_request,
1391 .free_request = dwc3_gadget_ep_free_request,
1392 .queue = dwc3_gadget_ep0_queue,
1393 .dequeue = dwc3_gadget_ep_dequeue,
1394 .set_halt = dwc3_gadget_ep0_set_halt,
1395 .set_wedge = dwc3_gadget_ep_set_wedge,
1396};
1397
1398static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1399 .enable = dwc3_gadget_ep_enable,
1400 .disable = dwc3_gadget_ep_disable,
1401 .alloc_request = dwc3_gadget_ep_alloc_request,
1402 .free_request = dwc3_gadget_ep_free_request,
1403 .queue = dwc3_gadget_ep_queue,
1404 .dequeue = dwc3_gadget_ep_dequeue,
1405 .set_halt = dwc3_gadget_ep_set_halt,
1406 .set_wedge = dwc3_gadget_ep_set_wedge,
1407};
1408
1409/* -------------------------------------------------------------------------- */
1410
1411static int dwc3_gadget_get_frame(struct usb_gadget *g)
1412{
1413 struct dwc3 *dwc = gadget_to_dwc(g);
1414 u32 reg;
1415
1416 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1417 return DWC3_DSTS_SOFFN(reg);
1418}
1419
1420static int dwc3_gadget_wakeup(struct usb_gadget *g)
1421{
1422 struct dwc3 *dwc = gadget_to_dwc(g);
1423
1424 unsigned long timeout;
1425 unsigned long flags;
1426
1427 u32 reg;
1428
1429 int ret = 0;
1430
1431 u8 link_state;
1432 u8 speed;
1433
1434 spin_lock_irqsave(&dwc->lock, flags);
1435
1436 /*
1437 * According to the Databook Remote wakeup request should
1438 * be issued only when the device is in early suspend state.
1439 *
1440 * We can check that via USB Link State bits in DSTS register.
1441 */
1442 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1443
1444 speed = reg & DWC3_DSTS_CONNECTSPD;
1445 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1446 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1447 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1448 ret = -EINVAL;
1449 goto out;
1450 }
1451
1452 link_state = DWC3_DSTS_USBLNKST(reg);
1453
1454 switch (link_state) {
1455 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1456 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1457 break;
1458 default:
1459 dwc3_trace(trace_dwc3_gadget,
1460 "can't wakeup from '%s'\n",
1461 dwc3_gadget_link_string(link_state));
1462 ret = -EINVAL;
1463 goto out;
1464 }
1465
1466 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1467 if (ret < 0) {
1468 dev_err(dwc->dev, "failed to put link in Recovery\n");
1469 goto out;
1470 }
1471
1472 /* Recent versions do this automatically */
1473 if (dwc->revision < DWC3_REVISION_194A) {
1474 /* write zeroes to Link Change Request */
1475 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1476 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1477 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1478 }
1479
1480 /* poll until Link State changes to ON */
1481 timeout = jiffies + msecs_to_jiffies(100);
1482
1483 while (!time_after(jiffies, timeout)) {
1484 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1485
1486 /* in HS, means ON */
1487 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1488 break;
1489 }
1490
1491 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1492 dev_err(dwc->dev, "failed to send remote wakeup\n");
1493 ret = -EINVAL;
1494 }
1495
1496out:
1497 spin_unlock_irqrestore(&dwc->lock, flags);
1498
1499 return ret;
1500}
1501
1502static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1503 int is_selfpowered)
1504{
1505 struct dwc3 *dwc = gadget_to_dwc(g);
1506 unsigned long flags;
1507
1508 spin_lock_irqsave(&dwc->lock, flags);
1509 g->is_selfpowered = !!is_selfpowered;
1510 spin_unlock_irqrestore(&dwc->lock, flags);
1511
1512 return 0;
1513}
1514
1515static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1516{
1517 u32 reg;
1518 u32 timeout = 500;
1519
1520 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1521 if (is_on) {
1522 if (dwc->revision <= DWC3_REVISION_187A) {
1523 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1524 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1525 }
1526
1527 if (dwc->revision >= DWC3_REVISION_194A)
1528 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1529 reg |= DWC3_DCTL_RUN_STOP;
1530
1531 if (dwc->has_hibernation)
1532 reg |= DWC3_DCTL_KEEP_CONNECT;
1533
1534 dwc->pullups_connected = true;
1535 } else {
1536 reg &= ~DWC3_DCTL_RUN_STOP;
1537
1538 if (dwc->has_hibernation && !suspend)
1539 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1540
1541 dwc->pullups_connected = false;
1542 }
1543
1544 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1545
1546 do {
1547 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1548 if (is_on) {
1549 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1550 break;
1551 } else {
1552 if (reg & DWC3_DSTS_DEVCTRLHLT)
1553 break;
1554 }
1555 timeout--;
1556 if (!timeout)
1557 return -ETIMEDOUT;
1558 udelay(1);
1559 } while (1);
1560
1561 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1562 dwc->gadget_driver
1563 ? dwc->gadget_driver->function : "no-function",
1564 is_on ? "connect" : "disconnect");
1565
1566 return 0;
1567}
1568
1569static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1570{
1571 struct dwc3 *dwc = gadget_to_dwc(g);
1572 unsigned long flags;
1573 int ret;
1574
1575 is_on = !!is_on;
1576
1577 spin_lock_irqsave(&dwc->lock, flags);
1578 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1579 spin_unlock_irqrestore(&dwc->lock, flags);
1580
1581 return ret;
1582}
1583
1584static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1585{
1586 u32 reg;
1587
1588 /* Enable all but Start and End of Frame IRQs */
1589 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1590 DWC3_DEVTEN_EVNTOVERFLOWEN |
1591 DWC3_DEVTEN_CMDCMPLTEN |
1592 DWC3_DEVTEN_ERRTICERREN |
1593 DWC3_DEVTEN_WKUPEVTEN |
1594 DWC3_DEVTEN_ULSTCNGEN |
1595 DWC3_DEVTEN_CONNECTDONEEN |
1596 DWC3_DEVTEN_USBRSTEN |
1597 DWC3_DEVTEN_DISCONNEVTEN);
1598
1599 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1600}
1601
1602static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1603{
1604 /* mask all interrupts */
1605 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1606}
1607
1608static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1609static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1610
1611static int dwc3_gadget_start(struct usb_gadget *g,
1612 struct usb_gadget_driver *driver)
1613{
1614 struct dwc3 *dwc = gadget_to_dwc(g);
1615 struct dwc3_ep *dep;
1616 unsigned long flags;
1617 int ret = 0;
1618 int irq;
1619 u32 reg;
1620
1621 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1622 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1623 IRQF_SHARED, "dwc3", dwc);
1624 if (ret) {
1625 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1626 irq, ret);
1627 goto err0;
1628 }
1629
1630 spin_lock_irqsave(&dwc->lock, flags);
1631
1632 if (dwc->gadget_driver) {
1633 dev_err(dwc->dev, "%s is already bound to %s\n",
1634 dwc->gadget.name,
1635 dwc->gadget_driver->driver.name);
1636 ret = -EBUSY;
1637 goto err1;
1638 }
1639
1640 dwc->gadget_driver = driver;
1641
1642 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1643 reg &= ~(DWC3_DCFG_SPEED_MASK);
1644
1645 /**
1646 * WORKAROUND: DWC3 revision < 2.20a have an issue
1647 * which would cause metastability state on Run/Stop
1648 * bit if we try to force the IP to USB2-only mode.
1649 *
1650 * Because of that, we cannot configure the IP to any
1651 * speed other than the SuperSpeed
1652 *
1653 * Refers to:
1654 *
1655 * STAR#9000525659: Clock Domain Crossing on DCTL in
1656 * USB 2.0 Mode
1657 */
1658 if (dwc->revision < DWC3_REVISION_220A) {
1659 reg |= DWC3_DCFG_SUPERSPEED;
1660 } else {
1661 switch (dwc->maximum_speed) {
1662 case USB_SPEED_LOW:
1663 reg |= DWC3_DSTS_LOWSPEED;
1664 break;
1665 case USB_SPEED_FULL:
1666 reg |= DWC3_DSTS_FULLSPEED1;
1667 break;
1668 case USB_SPEED_HIGH:
1669 reg |= DWC3_DSTS_HIGHSPEED;
1670 break;
1671 case USB_SPEED_SUPER_PLUS:
1672 reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1673 break;
1674 default:
1675 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1676 dwc->maximum_speed);
1677 /* fall through */
1678 case USB_SPEED_SUPER:
1679 reg |= DWC3_DCFG_SUPERSPEED;
1680 break;
1681 }
1682 }
1683 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1684
1685 /* Start with SuperSpeed Default */
1686 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1687
1688 dep = dwc->eps[0];
1689 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1690 false);
1691 if (ret) {
1692 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1693 goto err2;
1694 }
1695
1696 dep = dwc->eps[1];
1697 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1698 false);
1699 if (ret) {
1700 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1701 goto err3;
1702 }
1703
1704 /* begin to receive SETUP packets */
1705 dwc->ep0state = EP0_SETUP_PHASE;
1706 dwc3_ep0_out_start(dwc);
1707
1708 dwc3_gadget_enable_irq(dwc);
1709
1710 spin_unlock_irqrestore(&dwc->lock, flags);
1711
1712 return 0;
1713
1714err3:
1715 __dwc3_gadget_ep_disable(dwc->eps[0]);
1716
1717err2:
1718 dwc->gadget_driver = NULL;
1719
1720err1:
1721 spin_unlock_irqrestore(&dwc->lock, flags);
1722
1723 free_irq(irq, dwc);
1724
1725err0:
1726 return ret;
1727}
1728
1729static int dwc3_gadget_stop(struct usb_gadget *g)
1730{
1731 struct dwc3 *dwc = gadget_to_dwc(g);
1732 unsigned long flags;
1733 int irq;
1734
1735 spin_lock_irqsave(&dwc->lock, flags);
1736
1737 dwc3_gadget_disable_irq(dwc);
1738 __dwc3_gadget_ep_disable(dwc->eps[0]);
1739 __dwc3_gadget_ep_disable(dwc->eps[1]);
1740
1741 dwc->gadget_driver = NULL;
1742
1743 spin_unlock_irqrestore(&dwc->lock, flags);
1744
1745 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1746 free_irq(irq, dwc);
1747
1748 return 0;
1749}
1750
1751static const struct usb_gadget_ops dwc3_gadget_ops = {
1752 .get_frame = dwc3_gadget_get_frame,
1753 .wakeup = dwc3_gadget_wakeup,
1754 .set_selfpowered = dwc3_gadget_set_selfpowered,
1755 .pullup = dwc3_gadget_pullup,
1756 .udc_start = dwc3_gadget_start,
1757 .udc_stop = dwc3_gadget_stop,
1758};
1759
1760/* -------------------------------------------------------------------------- */
1761
1762static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1763 u8 num, u32 direction)
1764{
1765 struct dwc3_ep *dep;
1766 u8 i;
1767
1768 for (i = 0; i < num; i++) {
1769 u8 epnum = (i << 1) | (!!direction);
1770
1771 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1772 if (!dep)
1773 return -ENOMEM;
1774
1775 dep->dwc = dwc;
1776 dep->number = epnum;
1777 dep->direction = !!direction;
1778 dwc->eps[epnum] = dep;
1779
1780 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1781 (epnum & 1) ? "in" : "out");
1782
1783 dep->endpoint.name = dep->name;
1784
1785 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1786
1787 if (epnum == 0 || epnum == 1) {
1788 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1789 dep->endpoint.maxburst = 1;
1790 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1791 if (!epnum)
1792 dwc->gadget.ep0 = &dep->endpoint;
1793 } else {
1794 int ret;
1795
1796 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1797 dep->endpoint.max_streams = 15;
1798 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1799 list_add_tail(&dep->endpoint.ep_list,
1800 &dwc->gadget.ep_list);
1801
1802 ret = dwc3_alloc_trb_pool(dep);
1803 if (ret)
1804 return ret;
1805 }
1806
1807 if (epnum == 0 || epnum == 1) {
1808 dep->endpoint.caps.type_control = true;
1809 } else {
1810 dep->endpoint.caps.type_iso = true;
1811 dep->endpoint.caps.type_bulk = true;
1812 dep->endpoint.caps.type_int = true;
1813 }
1814
1815 dep->endpoint.caps.dir_in = !!direction;
1816 dep->endpoint.caps.dir_out = !direction;
1817
1818 INIT_LIST_HEAD(&dep->request_list);
1819 INIT_LIST_HEAD(&dep->req_queued);
1820 }
1821
1822 return 0;
1823}
1824
1825static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1826{
1827 int ret;
1828
1829 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1830
1831 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1832 if (ret < 0) {
1833 dwc3_trace(trace_dwc3_gadget,
1834 "failed to allocate OUT endpoints");
1835 return ret;
1836 }
1837
1838 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1839 if (ret < 0) {
1840 dwc3_trace(trace_dwc3_gadget,
1841 "failed to allocate IN endpoints");
1842 return ret;
1843 }
1844
1845 return 0;
1846}
1847
1848static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1849{
1850 struct dwc3_ep *dep;
1851 u8 epnum;
1852
1853 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1854 dep = dwc->eps[epnum];
1855 if (!dep)
1856 continue;
1857 /*
1858 * Physical endpoints 0 and 1 are special; they form the
1859 * bi-directional USB endpoint 0.
1860 *
1861 * For those two physical endpoints, we don't allocate a TRB
1862 * pool nor do we add them the endpoints list. Due to that, we
1863 * shouldn't do these two operations otherwise we would end up
1864 * with all sorts of bugs when removing dwc3.ko.
1865 */
1866 if (epnum != 0 && epnum != 1) {
1867 dwc3_free_trb_pool(dep);
1868 list_del(&dep->endpoint.ep_list);
1869 }
1870
1871 kfree(dep);
1872 }
1873}
1874
1875/* -------------------------------------------------------------------------- */
1876
1877static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1878 struct dwc3_request *req, struct dwc3_trb *trb,
1879 const struct dwc3_event_depevt *event, int status)
1880{
1881 unsigned int count;
1882 unsigned int s_pkt = 0;
1883 unsigned int trb_status;
1884
1885 trace_dwc3_complete_trb(dep, trb);
1886
1887 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1888 /*
1889 * We continue despite the error. There is not much we
1890 * can do. If we don't clean it up we loop forever. If
1891 * we skip the TRB then it gets overwritten after a
1892 * while since we use them in a ring buffer. A BUG()
1893 * would help. Lets hope that if this occurs, someone
1894 * fixes the root cause instead of looking away :)
1895 */
1896 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1897 dep->name, trb);
1898 count = trb->size & DWC3_TRB_SIZE_MASK;
1899
1900 if (dep->direction) {
1901 if (count) {
1902 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1903 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1904 dwc3_trace(trace_dwc3_gadget,
1905 "%s: incomplete IN transfer\n",
1906 dep->name);
1907 /*
1908 * If missed isoc occurred and there is
1909 * no request queued then issue END
1910 * TRANSFER, so that core generates
1911 * next xfernotready and we will issue
1912 * a fresh START TRANSFER.
1913 * If there are still queued request
1914 * then wait, do not issue either END
1915 * or UPDATE TRANSFER, just attach next
1916 * request in request_list during
1917 * giveback.If any future queued request
1918 * is successfully transferred then we
1919 * will issue UPDATE TRANSFER for all
1920 * request in the request_list.
1921 */
1922 dep->flags |= DWC3_EP_MISSED_ISOC;
1923 } else {
1924 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1925 dep->name);
1926 status = -ECONNRESET;
1927 }
1928 } else {
1929 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1930 }
1931 } else {
1932 if (count && (event->status & DEPEVT_STATUS_SHORT))
1933 s_pkt = 1;
1934 }
1935
1936 /*
1937 * We assume here we will always receive the entire data block
1938 * which we should receive. Meaning, if we program RX to
1939 * receive 4K but we receive only 2K, we assume that's all we
1940 * should receive and we simply bounce the request back to the
1941 * gadget driver for further processing.
1942 */
1943 req->request.actual += req->request.length - count;
1944 if (s_pkt)
1945 return 1;
1946 if ((event->status & DEPEVT_STATUS_LST) &&
1947 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1948 DWC3_TRB_CTRL_HWO)))
1949 return 1;
1950 if ((event->status & DEPEVT_STATUS_IOC) &&
1951 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1952 return 1;
1953 return 0;
1954}
1955
1956static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1957 const struct dwc3_event_depevt *event, int status)
1958{
1959 struct dwc3_request *req;
1960 struct dwc3_trb *trb;
1961 unsigned int slot;
1962 unsigned int i;
1963 int ret;
1964
1965 do {
1966 req = next_request(&dep->req_queued);
1967 if (WARN_ON_ONCE(!req))
1968 return 1;
1969
1970 i = 0;
1971 do {
1972 slot = req->start_slot + i;
1973 if ((slot == DWC3_TRB_NUM - 1) &&
1974 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1975 slot++;
1976 slot %= DWC3_TRB_NUM;
1977 trb = &dep->trb_pool[slot];
1978
1979 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1980 event, status);
1981 if (ret)
1982 break;
1983 } while (++i < req->request.num_mapped_sgs);
1984
1985 dwc3_gadget_giveback(dep, req, status);
1986
1987 if (ret)
1988 break;
1989 } while (1);
1990
1991 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1992 list_empty(&dep->req_queued)) {
1993 if (list_empty(&dep->request_list)) {
1994 /*
1995 * If there is no entry in request list then do
1996 * not issue END TRANSFER now. Just set PENDING
1997 * flag, so that END TRANSFER is issued when an
1998 * entry is added into request list.
1999 */
2000 dep->flags = DWC3_EP_PENDING_REQUEST;
2001 } else {
2002 dwc3_stop_active_transfer(dwc, dep->number, true);
2003 dep->flags = DWC3_EP_ENABLED;
2004 }
2005 return 1;
2006 }
2007
2008 return 1;
2009}
2010
2011static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2012 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2013{
2014 unsigned status = 0;
2015 int clean_busy;
2016 u32 is_xfer_complete;
2017
2018 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2019
2020 if (event->status & DEPEVT_STATUS_BUSERR)
2021 status = -ECONNRESET;
2022
2023 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2024 if (clean_busy && (is_xfer_complete ||
2025 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2026 dep->flags &= ~DWC3_EP_BUSY;
2027
2028 /*
2029 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2030 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2031 */
2032 if (dwc->revision < DWC3_REVISION_183A) {
2033 u32 reg;
2034 int i;
2035
2036 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2037 dep = dwc->eps[i];
2038
2039 if (!(dep->flags & DWC3_EP_ENABLED))
2040 continue;
2041
2042 if (!list_empty(&dep->req_queued))
2043 return;
2044 }
2045
2046 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2047 reg |= dwc->u1u2;
2048 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2049
2050 dwc->u1u2 = 0;
2051 }
2052
2053 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2054 int ret;
2055
2056 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2057 if (!ret || ret == -EBUSY)
2058 return;
2059 }
2060}
2061
2062static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2063 const struct dwc3_event_depevt *event)
2064{
2065 struct dwc3_ep *dep;
2066 u8 epnum = event->endpoint_number;
2067
2068 dep = dwc->eps[epnum];
2069
2070 if (!(dep->flags & DWC3_EP_ENABLED))
2071 return;
2072
2073 if (epnum == 0 || epnum == 1) {
2074 dwc3_ep0_interrupt(dwc, event);
2075 return;
2076 }
2077
2078 switch (event->endpoint_event) {
2079 case DWC3_DEPEVT_XFERCOMPLETE:
2080 dep->resource_index = 0;
2081
2082 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2083 dwc3_trace(trace_dwc3_gadget,
2084 "%s is an Isochronous endpoint\n",
2085 dep->name);
2086 return;
2087 }
2088
2089 dwc3_endpoint_transfer_complete(dwc, dep, event);
2090 break;
2091 case DWC3_DEPEVT_XFERINPROGRESS:
2092 dwc3_endpoint_transfer_complete(dwc, dep, event);
2093 break;
2094 case DWC3_DEPEVT_XFERNOTREADY:
2095 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2096 dwc3_gadget_start_isoc(dwc, dep, event);
2097 } else {
2098 int active;
2099 int ret;
2100
2101 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2102
2103 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2104 dep->name, active ? "Transfer Active"
2105 : "Transfer Not Active");
2106
2107 ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2108 if (!ret || ret == -EBUSY)
2109 return;
2110
2111 dwc3_trace(trace_dwc3_gadget,
2112 "%s: failed to kick transfers\n",
2113 dep->name);
2114 }
2115
2116 break;
2117 case DWC3_DEPEVT_STREAMEVT:
2118 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2119 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2120 dep->name);
2121 return;
2122 }
2123
2124 switch (event->status) {
2125 case DEPEVT_STREAMEVT_FOUND:
2126 dwc3_trace(trace_dwc3_gadget,
2127 "Stream %d found and started",
2128 event->parameters);
2129
2130 break;
2131 case DEPEVT_STREAMEVT_NOTFOUND:
2132 /* FALLTHROUGH */
2133 default:
2134 dwc3_trace(trace_dwc3_gadget,
2135 "unable to find suitable stream\n");
2136 }
2137 break;
2138 case DWC3_DEPEVT_RXTXFIFOEVT:
2139 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2140 break;
2141 case DWC3_DEPEVT_EPCMDCMPLT:
2142 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2143 break;
2144 }
2145}
2146
2147static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2148{
2149 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2150 spin_unlock(&dwc->lock);
2151 dwc->gadget_driver->disconnect(&dwc->gadget);
2152 spin_lock(&dwc->lock);
2153 }
2154}
2155
2156static void dwc3_suspend_gadget(struct dwc3 *dwc)
2157{
2158 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2159 spin_unlock(&dwc->lock);
2160 dwc->gadget_driver->suspend(&dwc->gadget);
2161 spin_lock(&dwc->lock);
2162 }
2163}
2164
2165static void dwc3_resume_gadget(struct dwc3 *dwc)
2166{
2167 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2168 spin_unlock(&dwc->lock);
2169 dwc->gadget_driver->resume(&dwc->gadget);
2170 spin_lock(&dwc->lock);
2171 }
2172}
2173
2174static void dwc3_reset_gadget(struct dwc3 *dwc)
2175{
2176 if (!dwc->gadget_driver)
2177 return;
2178
2179 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2180 spin_unlock(&dwc->lock);
2181 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2182 spin_lock(&dwc->lock);
2183 }
2184}
2185
2186static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2187{
2188 struct dwc3_ep *dep;
2189 struct dwc3_gadget_ep_cmd_params params;
2190 u32 cmd;
2191 int ret;
2192
2193 dep = dwc->eps[epnum];
2194
2195 if (!dep->resource_index)
2196 return;
2197
2198 /*
2199 * NOTICE: We are violating what the Databook says about the
2200 * EndTransfer command. Ideally we would _always_ wait for the
2201 * EndTransfer Command Completion IRQ, but that's causing too
2202 * much trouble synchronizing between us and gadget driver.
2203 *
2204 * We have discussed this with the IP Provider and it was
2205 * suggested to giveback all requests here, but give HW some
2206 * extra time to synchronize with the interconnect. We're using
2207 * an arbitrary 100us delay for that.
2208 *
2209 * Note also that a similar handling was tested by Synopsys
2210 * (thanks a lot Paul) and nothing bad has come out of it.
2211 * In short, what we're doing is:
2212 *
2213 * - Issue EndTransfer WITH CMDIOC bit set
2214 * - Wait 100us
2215 */
2216
2217 cmd = DWC3_DEPCMD_ENDTRANSFER;
2218 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2219 cmd |= DWC3_DEPCMD_CMDIOC;
2220 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2221 memset(¶ms, 0, sizeof(params));
2222 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2223 WARN_ON_ONCE(ret);
2224 dep->resource_index = 0;
2225 dep->flags &= ~DWC3_EP_BUSY;
2226 udelay(100);
2227}
2228
2229static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2230{
2231 u32 epnum;
2232
2233 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2234 struct dwc3_ep *dep;
2235
2236 dep = dwc->eps[epnum];
2237 if (!dep)
2238 continue;
2239
2240 if (!(dep->flags & DWC3_EP_ENABLED))
2241 continue;
2242
2243 dwc3_remove_requests(dwc, dep);
2244 }
2245}
2246
2247static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2248{
2249 u32 epnum;
2250
2251 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2252 struct dwc3_ep *dep;
2253 struct dwc3_gadget_ep_cmd_params params;
2254 int ret;
2255
2256 dep = dwc->eps[epnum];
2257 if (!dep)
2258 continue;
2259
2260 if (!(dep->flags & DWC3_EP_STALL))
2261 continue;
2262
2263 dep->flags &= ~DWC3_EP_STALL;
2264
2265 memset(¶ms, 0, sizeof(params));
2266 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2267 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2268 WARN_ON_ONCE(ret);
2269 }
2270}
2271
2272static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2273{
2274 int reg;
2275
2276 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2277 reg &= ~DWC3_DCTL_INITU1ENA;
2278 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2279
2280 reg &= ~DWC3_DCTL_INITU2ENA;
2281 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2282
2283 dwc3_disconnect_gadget(dwc);
2284
2285 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2286 dwc->setup_packet_pending = false;
2287 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2288}
2289
2290static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2291{
2292 u32 reg;
2293
2294 /*
2295 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2296 * would cause a missing Disconnect Event if there's a
2297 * pending Setup Packet in the FIFO.
2298 *
2299 * There's no suggested workaround on the official Bug
2300 * report, which states that "unless the driver/application
2301 * is doing any special handling of a disconnect event,
2302 * there is no functional issue".
2303 *
2304 * Unfortunately, it turns out that we _do_ some special
2305 * handling of a disconnect event, namely complete all
2306 * pending transfers, notify gadget driver of the
2307 * disconnection, and so on.
2308 *
2309 * Our suggested workaround is to follow the Disconnect
2310 * Event steps here, instead, based on a setup_packet_pending
2311 * flag. Such flag gets set whenever we have a SETUP_PENDING
2312 * status for EP0 TRBs and gets cleared on XferComplete for the
2313 * same endpoint.
2314 *
2315 * Refers to:
2316 *
2317 * STAR#9000466709: RTL: Device : Disconnect event not
2318 * generated if setup packet pending in FIFO
2319 */
2320 if (dwc->revision < DWC3_REVISION_188A) {
2321 if (dwc->setup_packet_pending)
2322 dwc3_gadget_disconnect_interrupt(dwc);
2323 }
2324
2325 dwc3_reset_gadget(dwc);
2326
2327 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2328 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2329 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2330 dwc->test_mode = false;
2331
2332 dwc3_stop_active_transfers(dwc);
2333 dwc3_clear_stall_all_ep(dwc);
2334
2335 /* Reset device address to zero */
2336 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2337 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2338 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2339}
2340
2341static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2342{
2343 u32 reg;
2344 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2345
2346 /*
2347 * We change the clock only at SS but I dunno why I would want to do
2348 * this. Maybe it becomes part of the power saving plan.
2349 */
2350
2351 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2352 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2353 return;
2354
2355 /*
2356 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2357 * each time on Connect Done.
2358 */
2359 if (!usb30_clock)
2360 return;
2361
2362 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2363 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2364 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2365}
2366
2367static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2368{
2369 struct dwc3_ep *dep;
2370 int ret;
2371 u32 reg;
2372 u8 speed;
2373
2374 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2375 speed = reg & DWC3_DSTS_CONNECTSPD;
2376 dwc->speed = speed;
2377
2378 dwc3_update_ram_clk_sel(dwc, speed);
2379
2380 switch (speed) {
2381 case DWC3_DCFG_SUPERSPEED_PLUS:
2382 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2383 dwc->gadget.ep0->maxpacket = 512;
2384 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2385 break;
2386 case DWC3_DCFG_SUPERSPEED:
2387 /*
2388 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2389 * would cause a missing USB3 Reset event.
2390 *
2391 * In such situations, we should force a USB3 Reset
2392 * event by calling our dwc3_gadget_reset_interrupt()
2393 * routine.
2394 *
2395 * Refers to:
2396 *
2397 * STAR#9000483510: RTL: SS : USB3 reset event may
2398 * not be generated always when the link enters poll
2399 */
2400 if (dwc->revision < DWC3_REVISION_190A)
2401 dwc3_gadget_reset_interrupt(dwc);
2402
2403 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2404 dwc->gadget.ep0->maxpacket = 512;
2405 dwc->gadget.speed = USB_SPEED_SUPER;
2406 break;
2407 case DWC3_DCFG_HIGHSPEED:
2408 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2409 dwc->gadget.ep0->maxpacket = 64;
2410 dwc->gadget.speed = USB_SPEED_HIGH;
2411 break;
2412 case DWC3_DCFG_FULLSPEED2:
2413 case DWC3_DCFG_FULLSPEED1:
2414 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2415 dwc->gadget.ep0->maxpacket = 64;
2416 dwc->gadget.speed = USB_SPEED_FULL;
2417 break;
2418 case DWC3_DCFG_LOWSPEED:
2419 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2420 dwc->gadget.ep0->maxpacket = 8;
2421 dwc->gadget.speed = USB_SPEED_LOW;
2422 break;
2423 }
2424
2425 /* Enable USB2 LPM Capability */
2426
2427 if ((dwc->revision > DWC3_REVISION_194A) &&
2428 (speed != DWC3_DCFG_SUPERSPEED) &&
2429 (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2430 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2431 reg |= DWC3_DCFG_LPM_CAP;
2432 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2433
2434 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2435 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2436
2437 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2438
2439 /*
2440 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2441 * DCFG.LPMCap is set, core responses with an ACK and the
2442 * BESL value in the LPM token is less than or equal to LPM
2443 * NYET threshold.
2444 */
2445 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2446 && dwc->has_lpm_erratum,
2447 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2448
2449 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2450 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2451
2452 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2453 } else {
2454 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2455 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2456 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2457 }
2458
2459 dep = dwc->eps[0];
2460 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2461 false);
2462 if (ret) {
2463 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2464 return;
2465 }
2466
2467 dep = dwc->eps[1];
2468 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2469 false);
2470 if (ret) {
2471 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2472 return;
2473 }
2474
2475 /*
2476 * Configure PHY via GUSB3PIPECTLn if required.
2477 *
2478 * Update GTXFIFOSIZn
2479 *
2480 * In both cases reset values should be sufficient.
2481 */
2482}
2483
2484static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2485{
2486 /*
2487 * TODO take core out of low power mode when that's
2488 * implemented.
2489 */
2490
2491 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2492 spin_unlock(&dwc->lock);
2493 dwc->gadget_driver->resume(&dwc->gadget);
2494 spin_lock(&dwc->lock);
2495 }
2496}
2497
2498static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2499 unsigned int evtinfo)
2500{
2501 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2502 unsigned int pwropt;
2503
2504 /*
2505 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2506 * Hibernation mode enabled which would show up when device detects
2507 * host-initiated U3 exit.
2508 *
2509 * In that case, device will generate a Link State Change Interrupt
2510 * from U3 to RESUME which is only necessary if Hibernation is
2511 * configured in.
2512 *
2513 * There are no functional changes due to such spurious event and we
2514 * just need to ignore it.
2515 *
2516 * Refers to:
2517 *
2518 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2519 * operational mode
2520 */
2521 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2522 if ((dwc->revision < DWC3_REVISION_250A) &&
2523 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2524 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2525 (next == DWC3_LINK_STATE_RESUME)) {
2526 dwc3_trace(trace_dwc3_gadget,
2527 "ignoring transition U3 -> Resume");
2528 return;
2529 }
2530 }
2531
2532 /*
2533 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2534 * on the link partner, the USB session might do multiple entry/exit
2535 * of low power states before a transfer takes place.
2536 *
2537 * Due to this problem, we might experience lower throughput. The
2538 * suggested workaround is to disable DCTL[12:9] bits if we're
2539 * transitioning from U1/U2 to U0 and enable those bits again
2540 * after a transfer completes and there are no pending transfers
2541 * on any of the enabled endpoints.
2542 *
2543 * This is the first half of that workaround.
2544 *
2545 * Refers to:
2546 *
2547 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2548 * core send LGO_Ux entering U0
2549 */
2550 if (dwc->revision < DWC3_REVISION_183A) {
2551 if (next == DWC3_LINK_STATE_U0) {
2552 u32 u1u2;
2553 u32 reg;
2554
2555 switch (dwc->link_state) {
2556 case DWC3_LINK_STATE_U1:
2557 case DWC3_LINK_STATE_U2:
2558 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2559 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2560 | DWC3_DCTL_ACCEPTU2ENA
2561 | DWC3_DCTL_INITU1ENA
2562 | DWC3_DCTL_ACCEPTU1ENA);
2563
2564 if (!dwc->u1u2)
2565 dwc->u1u2 = reg & u1u2;
2566
2567 reg &= ~u1u2;
2568
2569 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2570 break;
2571 default:
2572 /* do nothing */
2573 break;
2574 }
2575 }
2576 }
2577
2578 switch (next) {
2579 case DWC3_LINK_STATE_U1:
2580 if (dwc->speed == USB_SPEED_SUPER)
2581 dwc3_suspend_gadget(dwc);
2582 break;
2583 case DWC3_LINK_STATE_U2:
2584 case DWC3_LINK_STATE_U3:
2585 dwc3_suspend_gadget(dwc);
2586 break;
2587 case DWC3_LINK_STATE_RESUME:
2588 dwc3_resume_gadget(dwc);
2589 break;
2590 default:
2591 /* do nothing */
2592 break;
2593 }
2594
2595 dwc->link_state = next;
2596}
2597
2598static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2599 unsigned int evtinfo)
2600{
2601 unsigned int is_ss = evtinfo & BIT(4);
2602
2603 /**
2604 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2605 * have a known issue which can cause USB CV TD.9.23 to fail
2606 * randomly.
2607 *
2608 * Because of this issue, core could generate bogus hibernation
2609 * events which SW needs to ignore.
2610 *
2611 * Refers to:
2612 *
2613 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2614 * Device Fallback from SuperSpeed
2615 */
2616 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2617 return;
2618
2619 /* enter hibernation here */
2620}
2621
2622static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2623 const struct dwc3_event_devt *event)
2624{
2625 switch (event->type) {
2626 case DWC3_DEVICE_EVENT_DISCONNECT:
2627 dwc3_gadget_disconnect_interrupt(dwc);
2628 break;
2629 case DWC3_DEVICE_EVENT_RESET:
2630 dwc3_gadget_reset_interrupt(dwc);
2631 break;
2632 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2633 dwc3_gadget_conndone_interrupt(dwc);
2634 break;
2635 case DWC3_DEVICE_EVENT_WAKEUP:
2636 dwc3_gadget_wakeup_interrupt(dwc);
2637 break;
2638 case DWC3_DEVICE_EVENT_HIBER_REQ:
2639 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2640 "unexpected hibernation event\n"))
2641 break;
2642
2643 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2644 break;
2645 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2646 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2647 break;
2648 case DWC3_DEVICE_EVENT_EOPF:
2649 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2650 break;
2651 case DWC3_DEVICE_EVENT_SOF:
2652 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2653 break;
2654 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2655 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2656 break;
2657 case DWC3_DEVICE_EVENT_CMD_CMPL:
2658 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2659 break;
2660 case DWC3_DEVICE_EVENT_OVERFLOW:
2661 dwc3_trace(trace_dwc3_gadget, "Overflow");
2662 break;
2663 default:
2664 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2665 }
2666}
2667
2668static void dwc3_process_event_entry(struct dwc3 *dwc,
2669 const union dwc3_event *event)
2670{
2671 trace_dwc3_event(event->raw);
2672
2673 /* Endpoint IRQ, handle it and return early */
2674 if (event->type.is_devspec == 0) {
2675 /* depevt */
2676 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2677 }
2678
2679 switch (event->type.type) {
2680 case DWC3_EVENT_TYPE_DEV:
2681 dwc3_gadget_interrupt(dwc, &event->devt);
2682 break;
2683 /* REVISIT what to do with Carkit and I2C events ? */
2684 default:
2685 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2686 }
2687}
2688
2689static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2690{
2691 struct dwc3_event_buffer *evt;
2692 irqreturn_t ret = IRQ_NONE;
2693 int left;
2694 u32 reg;
2695
2696 evt = dwc->ev_buffs[buf];
2697 left = evt->count;
2698
2699 if (!(evt->flags & DWC3_EVENT_PENDING))
2700 return IRQ_NONE;
2701
2702 while (left > 0) {
2703 union dwc3_event event;
2704
2705 event.raw = *(u32 *) (evt->buf + evt->lpos);
2706
2707 dwc3_process_event_entry(dwc, &event);
2708
2709 /*
2710 * FIXME we wrap around correctly to the next entry as
2711 * almost all entries are 4 bytes in size. There is one
2712 * entry which has 12 bytes which is a regular entry
2713 * followed by 8 bytes data. ATM I don't know how
2714 * things are organized if we get next to the a
2715 * boundary so I worry about that once we try to handle
2716 * that.
2717 */
2718 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2719 left -= 4;
2720
2721 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2722 }
2723
2724 evt->count = 0;
2725 evt->flags &= ~DWC3_EVENT_PENDING;
2726 ret = IRQ_HANDLED;
2727
2728 /* Unmask interrupt */
2729 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2730 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2731 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2732
2733 return ret;
2734}
2735
2736static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2737{
2738 struct dwc3 *dwc = _dwc;
2739 unsigned long flags;
2740 irqreturn_t ret = IRQ_NONE;
2741 int i;
2742
2743 spin_lock_irqsave(&dwc->lock, flags);
2744
2745 for (i = 0; i < dwc->num_event_buffers; i++)
2746 ret |= dwc3_process_event_buf(dwc, i);
2747
2748 spin_unlock_irqrestore(&dwc->lock, flags);
2749
2750 return ret;
2751}
2752
2753static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2754{
2755 struct dwc3_event_buffer *evt;
2756 u32 count;
2757 u32 reg;
2758
2759 evt = dwc->ev_buffs[buf];
2760
2761 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2762 count &= DWC3_GEVNTCOUNT_MASK;
2763 if (!count)
2764 return IRQ_NONE;
2765
2766 evt->count = count;
2767 evt->flags |= DWC3_EVENT_PENDING;
2768
2769 /* Mask interrupt */
2770 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2771 reg |= DWC3_GEVNTSIZ_INTMASK;
2772 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2773
2774 return IRQ_WAKE_THREAD;
2775}
2776
2777static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2778{
2779 struct dwc3 *dwc = _dwc;
2780 int i;
2781 irqreturn_t ret = IRQ_NONE;
2782
2783 for (i = 0; i < dwc->num_event_buffers; i++) {
2784 irqreturn_t status;
2785
2786 status = dwc3_check_event_buf(dwc, i);
2787 if (status == IRQ_WAKE_THREAD)
2788 ret = status;
2789 }
2790
2791 return ret;
2792}
2793
2794/**
2795 * dwc3_gadget_init - Initializes gadget related registers
2796 * @dwc: pointer to our controller context structure
2797 *
2798 * Returns 0 on success otherwise negative errno.
2799 */
2800int dwc3_gadget_init(struct dwc3 *dwc)
2801{
2802 int ret;
2803
2804 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2805 &dwc->ctrl_req_addr, GFP_KERNEL);
2806 if (!dwc->ctrl_req) {
2807 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2808 ret = -ENOMEM;
2809 goto err0;
2810 }
2811
2812 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2813 &dwc->ep0_trb_addr, GFP_KERNEL);
2814 if (!dwc->ep0_trb) {
2815 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2816 ret = -ENOMEM;
2817 goto err1;
2818 }
2819
2820 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2821 if (!dwc->setup_buf) {
2822 ret = -ENOMEM;
2823 goto err2;
2824 }
2825
2826 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2827 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2828 GFP_KERNEL);
2829 if (!dwc->ep0_bounce) {
2830 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2831 ret = -ENOMEM;
2832 goto err3;
2833 }
2834
2835 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2836 if (!dwc->zlp_buf) {
2837 ret = -ENOMEM;
2838 goto err4;
2839 }
2840
2841 dwc->gadget.ops = &dwc3_gadget_ops;
2842 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2843 dwc->gadget.sg_supported = true;
2844 dwc->gadget.name = "dwc3-gadget";
2845 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
2846
2847 /*
2848 * FIXME We might be setting max_speed to <SUPER, however versions
2849 * <2.20a of dwc3 have an issue with metastability (documented
2850 * elsewhere in this driver) which tells us we can't set max speed to
2851 * anything lower than SUPER.
2852 *
2853 * Because gadget.max_speed is only used by composite.c and function
2854 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2855 * to happen so we avoid sending SuperSpeed Capability descriptor
2856 * together with our BOS descriptor as that could confuse host into
2857 * thinking we can handle super speed.
2858 *
2859 * Note that, in fact, we won't even support GetBOS requests when speed
2860 * is less than super speed because we don't have means, yet, to tell
2861 * composite.c that we are USB 2.0 + LPM ECN.
2862 */
2863 if (dwc->revision < DWC3_REVISION_220A)
2864 dwc3_trace(trace_dwc3_gadget,
2865 "Changing max_speed on rev %08x\n",
2866 dwc->revision);
2867
2868 dwc->gadget.max_speed = dwc->maximum_speed;
2869
2870 /*
2871 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2872 * on ep out.
2873 */
2874 dwc->gadget.quirk_ep_out_aligned_size = true;
2875
2876 /*
2877 * REVISIT: Here we should clear all pending IRQs to be
2878 * sure we're starting from a well known location.
2879 */
2880
2881 ret = dwc3_gadget_init_endpoints(dwc);
2882 if (ret)
2883 goto err5;
2884
2885 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2886 if (ret) {
2887 dev_err(dwc->dev, "failed to register udc\n");
2888 goto err5;
2889 }
2890
2891 return 0;
2892
2893err5:
2894 kfree(dwc->zlp_buf);
2895
2896err4:
2897 dwc3_gadget_free_endpoints(dwc);
2898 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2899 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2900
2901err3:
2902 kfree(dwc->setup_buf);
2903
2904err2:
2905 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2906 dwc->ep0_trb, dwc->ep0_trb_addr);
2907
2908err1:
2909 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2910 dwc->ctrl_req, dwc->ctrl_req_addr);
2911
2912err0:
2913 return ret;
2914}
2915
2916/* -------------------------------------------------------------------------- */
2917
2918void dwc3_gadget_exit(struct dwc3 *dwc)
2919{
2920 usb_del_gadget_udc(&dwc->gadget);
2921
2922 dwc3_gadget_free_endpoints(dwc);
2923
2924 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2925 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2926
2927 kfree(dwc->setup_buf);
2928 kfree(dwc->zlp_buf);
2929
2930 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2931 dwc->ep0_trb, dwc->ep0_trb_addr);
2932
2933 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2934 dwc->ctrl_req, dwc->ctrl_req_addr);
2935}
2936
2937int dwc3_gadget_suspend(struct dwc3 *dwc)
2938{
2939 if (!dwc->gadget_driver)
2940 return 0;
2941
2942 if (dwc->pullups_connected) {
2943 dwc3_gadget_disable_irq(dwc);
2944 dwc3_gadget_run_stop(dwc, true, true);
2945 }
2946
2947 __dwc3_gadget_ep_disable(dwc->eps[0]);
2948 __dwc3_gadget_ep_disable(dwc->eps[1]);
2949
2950 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2951
2952 return 0;
2953}
2954
2955int dwc3_gadget_resume(struct dwc3 *dwc)
2956{
2957 struct dwc3_ep *dep;
2958 int ret;
2959
2960 if (!dwc->gadget_driver)
2961 return 0;
2962
2963 /* Start with SuperSpeed Default */
2964 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2965
2966 dep = dwc->eps[0];
2967 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2968 false);
2969 if (ret)
2970 goto err0;
2971
2972 dep = dwc->eps[1];
2973 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2974 false);
2975 if (ret)
2976 goto err1;
2977
2978 /* begin to receive SETUP packets */
2979 dwc->ep0state = EP0_SETUP_PHASE;
2980 dwc3_ep0_out_start(dwc);
2981
2982 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2983
2984 if (dwc->pullups_connected) {
2985 dwc3_gadget_enable_irq(dwc);
2986 dwc3_gadget_run_stop(dwc, true, false);
2987 }
2988
2989 return 0;
2990
2991err1:
2992 __dwc3_gadget_ep_disable(dwc->eps[0]);
2993
2994err0:
2995 return ret;
2996}
1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57/**
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
61 *
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
64 * is passed
65 */
66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
67{
68 u32 reg;
69
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
72
73 switch (mode) {
74 case TEST_J:
75 case TEST_K:
76 case TEST_SE0_NAK:
77 case TEST_PACKET:
78 case TEST_FORCE_EN:
79 reg |= mode << 1;
80 break;
81 default:
82 return -EINVAL;
83 }
84
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
86
87 return 0;
88}
89
90/**
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
94 *
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
97 */
98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
99{
100 int retries = 10000;
101 u32 reg;
102
103 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
104 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
105
106 /* set requested state */
107 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
108 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
109
110 /* wait for a change in DSTS */
111 while (--retries) {
112 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
113
114 if (DWC3_DSTS_USBLNKST(reg) == state)
115 return 0;
116
117 udelay(5);
118 }
119
120 dev_vdbg(dwc->dev, "link state change request timed out\n");
121
122 return -ETIMEDOUT;
123}
124
125/**
126 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
127 * @dwc: pointer to our context structure
128 *
129 * This function will a best effort FIFO allocation in order
130 * to improve FIFO usage and throughput, while still allowing
131 * us to enable as many endpoints as possible.
132 *
133 * Keep in mind that this operation will be highly dependent
134 * on the configured size for RAM1 - which contains TxFifo -,
135 * the amount of endpoints enabled on coreConsultant tool, and
136 * the width of the Master Bus.
137 *
138 * In the ideal world, we would always be able to satisfy the
139 * following equation:
140 *
141 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
142 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
143 *
144 * Unfortunately, due to many variables that's not always the case.
145 */
146int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
147{
148 int last_fifo_depth = 0;
149 int ram1_depth;
150 int fifo_size;
151 int mdwidth;
152 int num;
153
154 if (!dwc->needs_fifo_resize)
155 return 0;
156
157 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
158 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
159
160 /* MDWIDTH is represented in bits, we need it in bytes */
161 mdwidth >>= 3;
162
163 /*
164 * FIXME For now we will only allocate 1 wMaxPacketSize space
165 * for each enabled endpoint, later patches will come to
166 * improve this algorithm so that we better use the internal
167 * FIFO space
168 */
169 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
170 struct dwc3_ep *dep = dwc->eps[num];
171 int fifo_number = dep->number >> 1;
172 int mult = 1;
173 int tmp;
174
175 if (!(dep->number & 1))
176 continue;
177
178 if (!(dep->flags & DWC3_EP_ENABLED))
179 continue;
180
181 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
182 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
183 mult = 3;
184
185 /*
186 * REVISIT: the following assumes we will always have enough
187 * space available on the FIFO RAM for all possible use cases.
188 * Make sure that's true somehow and change FIFO allocation
189 * accordingly.
190 *
191 * If we have Bulk or Isochronous endpoints, we want
192 * them to be able to be very, very fast. So we're giving
193 * those endpoints a fifo_size which is enough for 3 full
194 * packets
195 */
196 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
197 tmp += mdwidth;
198
199 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
200
201 fifo_size |= (last_fifo_depth << 16);
202
203 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
204 dep->name, last_fifo_depth, fifo_size & 0xffff);
205
206 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
207 fifo_size);
208
209 last_fifo_depth += (fifo_size & 0xffff);
210 }
211
212 return 0;
213}
214
215void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
216 int status)
217{
218 struct dwc3 *dwc = dep->dwc;
219
220 if (req->queued) {
221 if (req->request.num_mapped_sgs)
222 dep->busy_slot += req->request.num_mapped_sgs;
223 else
224 dep->busy_slot++;
225
226 /*
227 * Skip LINK TRB. We can't use req->trb and check for
228 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
229 * completed (not the LINK TRB).
230 */
231 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
232 usb_endpoint_xfer_isoc(dep->endpoint.desc))
233 dep->busy_slot++;
234 }
235 list_del(&req->list);
236 req->trb = NULL;
237
238 if (req->request.status == -EINPROGRESS)
239 req->request.status = status;
240
241 if (dwc->ep0_bounced && dep->number == 0)
242 dwc->ep0_bounced = false;
243 else
244 usb_gadget_unmap_request(&dwc->gadget, &req->request,
245 req->direction);
246
247 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
248 req, dep->name, req->request.actual,
249 req->request.length, status);
250
251 spin_unlock(&dwc->lock);
252 req->request.complete(&dep->endpoint, &req->request);
253 spin_lock(&dwc->lock);
254}
255
256static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
257{
258 switch (cmd) {
259 case DWC3_DEPCMD_DEPSTARTCFG:
260 return "Start New Configuration";
261 case DWC3_DEPCMD_ENDTRANSFER:
262 return "End Transfer";
263 case DWC3_DEPCMD_UPDATETRANSFER:
264 return "Update Transfer";
265 case DWC3_DEPCMD_STARTTRANSFER:
266 return "Start Transfer";
267 case DWC3_DEPCMD_CLEARSTALL:
268 return "Clear Stall";
269 case DWC3_DEPCMD_SETSTALL:
270 return "Set Stall";
271 case DWC3_DEPCMD_GETSEQNUMBER:
272 return "Get Data Sequence Number";
273 case DWC3_DEPCMD_SETTRANSFRESOURCE:
274 return "Set Endpoint Transfer Resource";
275 case DWC3_DEPCMD_SETEPCONFIG:
276 return "Set Endpoint Configuration";
277 default:
278 return "UNKNOWN command";
279 }
280}
281
282int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
283{
284 u32 timeout = 500;
285 u32 reg;
286
287 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
288 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
289
290 do {
291 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
292 if (!(reg & DWC3_DGCMD_CMDACT)) {
293 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
294 DWC3_DGCMD_STATUS(reg));
295 return 0;
296 }
297
298 /*
299 * We can't sleep here, because it's also called from
300 * interrupt context.
301 */
302 timeout--;
303 if (!timeout)
304 return -ETIMEDOUT;
305 udelay(1);
306 } while (1);
307}
308
309int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
310 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
311{
312 struct dwc3_ep *dep = dwc->eps[ep];
313 u32 timeout = 500;
314 u32 reg;
315
316 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
317 dep->name,
318 dwc3_gadget_ep_cmd_string(cmd), params->param0,
319 params->param1, params->param2);
320
321 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
322 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
323 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
324
325 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
326 do {
327 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
328 if (!(reg & DWC3_DEPCMD_CMDACT)) {
329 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
330 DWC3_DEPCMD_STATUS(reg));
331 return 0;
332 }
333
334 /*
335 * We can't sleep here, because it is also called from
336 * interrupt context.
337 */
338 timeout--;
339 if (!timeout)
340 return -ETIMEDOUT;
341
342 udelay(1);
343 } while (1);
344}
345
346static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
347 struct dwc3_trb *trb)
348{
349 u32 offset = (char *) trb - (char *) dep->trb_pool;
350
351 return dep->trb_pool_dma + offset;
352}
353
354static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
355{
356 struct dwc3 *dwc = dep->dwc;
357
358 if (dep->trb_pool)
359 return 0;
360
361 if (dep->number == 0 || dep->number == 1)
362 return 0;
363
364 dep->trb_pool = dma_alloc_coherent(dwc->dev,
365 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
366 &dep->trb_pool_dma, GFP_KERNEL);
367 if (!dep->trb_pool) {
368 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
369 dep->name);
370 return -ENOMEM;
371 }
372
373 return 0;
374}
375
376static void dwc3_free_trb_pool(struct dwc3_ep *dep)
377{
378 struct dwc3 *dwc = dep->dwc;
379
380 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
381 dep->trb_pool, dep->trb_pool_dma);
382
383 dep->trb_pool = NULL;
384 dep->trb_pool_dma = 0;
385}
386
387static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
388{
389 struct dwc3_gadget_ep_cmd_params params;
390 u32 cmd;
391
392 memset(¶ms, 0x00, sizeof(params));
393
394 if (dep->number != 1) {
395 cmd = DWC3_DEPCMD_DEPSTARTCFG;
396 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
397 if (dep->number > 1) {
398 if (dwc->start_config_issued)
399 return 0;
400 dwc->start_config_issued = true;
401 cmd |= DWC3_DEPCMD_PARAM(2);
402 }
403
404 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
405 }
406
407 return 0;
408}
409
410static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
411 const struct usb_endpoint_descriptor *desc,
412 const struct usb_ss_ep_comp_descriptor *comp_desc)
413{
414 struct dwc3_gadget_ep_cmd_params params;
415
416 memset(¶ms, 0x00, sizeof(params));
417
418 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
419 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
420 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
421
422 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
423 | DWC3_DEPCFG_XFER_NOT_READY_EN;
424
425 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
426 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
427 | DWC3_DEPCFG_STREAM_EVENT_EN;
428 dep->stream_capable = true;
429 }
430
431 if (usb_endpoint_xfer_isoc(desc))
432 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
433
434 /*
435 * We are doing 1:1 mapping for endpoints, meaning
436 * Physical Endpoints 2 maps to Logical Endpoint 2 and
437 * so on. We consider the direction bit as part of the physical
438 * endpoint number. So USB endpoint 0x81 is 0x03.
439 */
440 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
441
442 /*
443 * We must use the lower 16 TX FIFOs even though
444 * HW might have more
445 */
446 if (dep->direction)
447 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
448
449 if (desc->bInterval) {
450 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
451 dep->interval = 1 << (desc->bInterval - 1);
452 }
453
454 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
455 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
456}
457
458static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
459{
460 struct dwc3_gadget_ep_cmd_params params;
461
462 memset(¶ms, 0x00, sizeof(params));
463
464 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
465
466 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
467 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
468}
469
470/**
471 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
472 * @dep: endpoint to be initialized
473 * @desc: USB Endpoint Descriptor
474 *
475 * Caller should take care of locking
476 */
477static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
478 const struct usb_endpoint_descriptor *desc,
479 const struct usb_ss_ep_comp_descriptor *comp_desc)
480{
481 struct dwc3 *dwc = dep->dwc;
482 u32 reg;
483 int ret = -ENOMEM;
484
485 if (!(dep->flags & DWC3_EP_ENABLED)) {
486 ret = dwc3_gadget_start_config(dwc, dep);
487 if (ret)
488 return ret;
489 }
490
491 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
492 if (ret)
493 return ret;
494
495 if (!(dep->flags & DWC3_EP_ENABLED)) {
496 struct dwc3_trb *trb_st_hw;
497 struct dwc3_trb *trb_link;
498
499 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
500 if (ret)
501 return ret;
502
503 dep->endpoint.desc = desc;
504 dep->comp_desc = comp_desc;
505 dep->type = usb_endpoint_type(desc);
506 dep->flags |= DWC3_EP_ENABLED;
507
508 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
509 reg |= DWC3_DALEPENA_EP(dep->number);
510 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
511
512 if (!usb_endpoint_xfer_isoc(desc))
513 return 0;
514
515 memset(&trb_link, 0, sizeof(trb_link));
516
517 /* Link TRB for ISOC. The HWO bit is never reset */
518 trb_st_hw = &dep->trb_pool[0];
519
520 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
521
522 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
523 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
524 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
525 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
526 }
527
528 return 0;
529}
530
531static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
532static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
533{
534 struct dwc3_request *req;
535
536 if (!list_empty(&dep->req_queued))
537 dwc3_stop_active_transfer(dwc, dep->number);
538
539 while (!list_empty(&dep->request_list)) {
540 req = next_request(&dep->request_list);
541
542 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
543 }
544}
545
546/**
547 * __dwc3_gadget_ep_disable - Disables a HW endpoint
548 * @dep: the endpoint to disable
549 *
550 * This function also removes requests which are currently processed ny the
551 * hardware and those which are not yet scheduled.
552 * Caller should take care of locking.
553 */
554static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
555{
556 struct dwc3 *dwc = dep->dwc;
557 u32 reg;
558
559 dwc3_remove_requests(dwc, dep);
560
561 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
562 reg &= ~DWC3_DALEPENA_EP(dep->number);
563 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
564
565 dep->stream_capable = false;
566 dep->endpoint.desc = NULL;
567 dep->comp_desc = NULL;
568 dep->type = 0;
569 dep->flags = 0;
570
571 return 0;
572}
573
574/* -------------------------------------------------------------------------- */
575
576static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
577 const struct usb_endpoint_descriptor *desc)
578{
579 return -EINVAL;
580}
581
582static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
583{
584 return -EINVAL;
585}
586
587/* -------------------------------------------------------------------------- */
588
589static int dwc3_gadget_ep_enable(struct usb_ep *ep,
590 const struct usb_endpoint_descriptor *desc)
591{
592 struct dwc3_ep *dep;
593 struct dwc3 *dwc;
594 unsigned long flags;
595 int ret;
596
597 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
598 pr_debug("dwc3: invalid parameters\n");
599 return -EINVAL;
600 }
601
602 if (!desc->wMaxPacketSize) {
603 pr_debug("dwc3: missing wMaxPacketSize\n");
604 return -EINVAL;
605 }
606
607 dep = to_dwc3_ep(ep);
608 dwc = dep->dwc;
609
610 switch (usb_endpoint_type(desc)) {
611 case USB_ENDPOINT_XFER_CONTROL:
612 strlcat(dep->name, "-control", sizeof(dep->name));
613 break;
614 case USB_ENDPOINT_XFER_ISOC:
615 strlcat(dep->name, "-isoc", sizeof(dep->name));
616 break;
617 case USB_ENDPOINT_XFER_BULK:
618 strlcat(dep->name, "-bulk", sizeof(dep->name));
619 break;
620 case USB_ENDPOINT_XFER_INT:
621 strlcat(dep->name, "-int", sizeof(dep->name));
622 break;
623 default:
624 dev_err(dwc->dev, "invalid endpoint transfer type\n");
625 }
626
627 if (dep->flags & DWC3_EP_ENABLED) {
628 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
629 dep->name);
630 return 0;
631 }
632
633 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
634
635 spin_lock_irqsave(&dwc->lock, flags);
636 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
637 spin_unlock_irqrestore(&dwc->lock, flags);
638
639 return ret;
640}
641
642static int dwc3_gadget_ep_disable(struct usb_ep *ep)
643{
644 struct dwc3_ep *dep;
645 struct dwc3 *dwc;
646 unsigned long flags;
647 int ret;
648
649 if (!ep) {
650 pr_debug("dwc3: invalid parameters\n");
651 return -EINVAL;
652 }
653
654 dep = to_dwc3_ep(ep);
655 dwc = dep->dwc;
656
657 if (!(dep->flags & DWC3_EP_ENABLED)) {
658 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
659 dep->name);
660 return 0;
661 }
662
663 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
664 dep->number >> 1,
665 (dep->number & 1) ? "in" : "out");
666
667 spin_lock_irqsave(&dwc->lock, flags);
668 ret = __dwc3_gadget_ep_disable(dep);
669 spin_unlock_irqrestore(&dwc->lock, flags);
670
671 return ret;
672}
673
674static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
675 gfp_t gfp_flags)
676{
677 struct dwc3_request *req;
678 struct dwc3_ep *dep = to_dwc3_ep(ep);
679 struct dwc3 *dwc = dep->dwc;
680
681 req = kzalloc(sizeof(*req), gfp_flags);
682 if (!req) {
683 dev_err(dwc->dev, "not enough memory\n");
684 return NULL;
685 }
686
687 req->epnum = dep->number;
688 req->dep = dep;
689
690 return &req->request;
691}
692
693static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
694 struct usb_request *request)
695{
696 struct dwc3_request *req = to_dwc3_request(request);
697
698 kfree(req);
699}
700
701/**
702 * dwc3_prepare_one_trb - setup one TRB from one request
703 * @dep: endpoint for which this request is prepared
704 * @req: dwc3_request pointer
705 */
706static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
707 struct dwc3_request *req, dma_addr_t dma,
708 unsigned length, unsigned last, unsigned chain)
709{
710 struct dwc3 *dwc = dep->dwc;
711 struct dwc3_trb *trb;
712
713 unsigned int cur_slot;
714
715 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
716 dep->name, req, (unsigned long long) dma,
717 length, last ? " last" : "",
718 chain ? " chain" : "");
719
720 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
721 cur_slot = dep->free_slot;
722 dep->free_slot++;
723
724 /* Skip the LINK-TRB on ISOC */
725 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
726 usb_endpoint_xfer_isoc(dep->endpoint.desc))
727 return;
728
729 if (!req->trb) {
730 dwc3_gadget_move_request_queued(req);
731 req->trb = trb;
732 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
733 }
734
735 trb->size = DWC3_TRB_SIZE_LENGTH(length);
736 trb->bpl = lower_32_bits(dma);
737 trb->bph = upper_32_bits(dma);
738
739 switch (usb_endpoint_type(dep->endpoint.desc)) {
740 case USB_ENDPOINT_XFER_CONTROL:
741 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
742 break;
743
744 case USB_ENDPOINT_XFER_ISOC:
745 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
746
747 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
748 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
749 trb->ctrl |= DWC3_TRB_CTRL_IOC;
750 break;
751
752 case USB_ENDPOINT_XFER_BULK:
753 case USB_ENDPOINT_XFER_INT:
754 trb->ctrl = DWC3_TRBCTL_NORMAL;
755 break;
756 default:
757 /*
758 * This is only possible with faulty memory because we
759 * checked it already :)
760 */
761 BUG();
762 }
763
764 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
765 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
766 trb->ctrl |= DWC3_TRB_CTRL_CSP;
767 } else {
768 if (chain)
769 trb->ctrl |= DWC3_TRB_CTRL_CHN;
770
771 if (last)
772 trb->ctrl |= DWC3_TRB_CTRL_LST;
773 }
774
775 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
776 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
777
778 trb->ctrl |= DWC3_TRB_CTRL_HWO;
779}
780
781/*
782 * dwc3_prepare_trbs - setup TRBs from requests
783 * @dep: endpoint for which requests are being prepared
784 * @starting: true if the endpoint is idle and no requests are queued.
785 *
786 * The function goes through the requests list and sets up TRBs for the
787 * transfers. The function returns once there are no more TRBs available or
788 * it runs out of requests.
789 */
790static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
791{
792 struct dwc3_request *req, *n;
793 u32 trbs_left;
794 u32 max;
795 unsigned int last_one = 0;
796
797 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
798
799 /* the first request must not be queued */
800 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
801
802 /* Can't wrap around on a non-isoc EP since there's no link TRB */
803 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
804 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
805 if (trbs_left > max)
806 trbs_left = max;
807 }
808
809 /*
810 * If busy & slot are equal than it is either full or empty. If we are
811 * starting to process requests then we are empty. Otherwise we are
812 * full and don't do anything
813 */
814 if (!trbs_left) {
815 if (!starting)
816 return;
817 trbs_left = DWC3_TRB_NUM;
818 /*
819 * In case we start from scratch, we queue the ISOC requests
820 * starting from slot 1. This is done because we use ring
821 * buffer and have no LST bit to stop us. Instead, we place
822 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
823 * after the first request so we start at slot 1 and have
824 * 7 requests proceed before we hit the first IOC.
825 * Other transfer types don't use the ring buffer and are
826 * processed from the first TRB until the last one. Since we
827 * don't wrap around we have to start at the beginning.
828 */
829 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
830 dep->busy_slot = 1;
831 dep->free_slot = 1;
832 } else {
833 dep->busy_slot = 0;
834 dep->free_slot = 0;
835 }
836 }
837
838 /* The last TRB is a link TRB, not used for xfer */
839 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
840 return;
841
842 list_for_each_entry_safe(req, n, &dep->request_list, list) {
843 unsigned length;
844 dma_addr_t dma;
845
846 if (req->request.num_mapped_sgs > 0) {
847 struct usb_request *request = &req->request;
848 struct scatterlist *sg = request->sg;
849 struct scatterlist *s;
850 int i;
851
852 for_each_sg(sg, s, request->num_mapped_sgs, i) {
853 unsigned chain = true;
854
855 length = sg_dma_len(s);
856 dma = sg_dma_address(s);
857
858 if (i == (request->num_mapped_sgs - 1) ||
859 sg_is_last(s)) {
860 last_one = true;
861 chain = false;
862 }
863
864 trbs_left--;
865 if (!trbs_left)
866 last_one = true;
867
868 if (last_one)
869 chain = false;
870
871 dwc3_prepare_one_trb(dep, req, dma, length,
872 last_one, chain);
873
874 if (last_one)
875 break;
876 }
877 } else {
878 dma = req->request.dma;
879 length = req->request.length;
880 trbs_left--;
881
882 if (!trbs_left)
883 last_one = 1;
884
885 /* Is this the last request? */
886 if (list_is_last(&req->list, &dep->request_list))
887 last_one = 1;
888
889 dwc3_prepare_one_trb(dep, req, dma, length,
890 last_one, false);
891
892 if (last_one)
893 break;
894 }
895 }
896}
897
898static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
899 int start_new)
900{
901 struct dwc3_gadget_ep_cmd_params params;
902 struct dwc3_request *req;
903 struct dwc3 *dwc = dep->dwc;
904 int ret;
905 u32 cmd;
906
907 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
908 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
909 return -EBUSY;
910 }
911 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
912
913 /*
914 * If we are getting here after a short-out-packet we don't enqueue any
915 * new requests as we try to set the IOC bit only on the last request.
916 */
917 if (start_new) {
918 if (list_empty(&dep->req_queued))
919 dwc3_prepare_trbs(dep, start_new);
920
921 /* req points to the first request which will be sent */
922 req = next_request(&dep->req_queued);
923 } else {
924 dwc3_prepare_trbs(dep, start_new);
925
926 /*
927 * req points to the first request where HWO changed from 0 to 1
928 */
929 req = next_request(&dep->req_queued);
930 }
931 if (!req) {
932 dep->flags |= DWC3_EP_PENDING_REQUEST;
933 return 0;
934 }
935
936 memset(¶ms, 0, sizeof(params));
937 params.param0 = upper_32_bits(req->trb_dma);
938 params.param1 = lower_32_bits(req->trb_dma);
939
940 if (start_new)
941 cmd = DWC3_DEPCMD_STARTTRANSFER;
942 else
943 cmd = DWC3_DEPCMD_UPDATETRANSFER;
944
945 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
946 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
947 if (ret < 0) {
948 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
949
950 /*
951 * FIXME we need to iterate over the list of requests
952 * here and stop, unmap, free and del each of the linked
953 * requests instead of what we do now.
954 */
955 usb_gadget_unmap_request(&dwc->gadget, &req->request,
956 req->direction);
957 list_del(&req->list);
958 return ret;
959 }
960
961 dep->flags |= DWC3_EP_BUSY;
962
963 if (start_new) {
964 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
965 dep->number);
966 WARN_ON_ONCE(!dep->res_trans_idx);
967 }
968
969 return 0;
970}
971
972static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
973{
974 struct dwc3 *dwc = dep->dwc;
975 int ret;
976
977 req->request.actual = 0;
978 req->request.status = -EINPROGRESS;
979 req->direction = dep->direction;
980 req->epnum = dep->number;
981
982 /*
983 * We only add to our list of requests now and
984 * start consuming the list once we get XferNotReady
985 * IRQ.
986 *
987 * That way, we avoid doing anything that we don't need
988 * to do now and defer it until the point we receive a
989 * particular token from the Host side.
990 *
991 * This will also avoid Host cancelling URBs due to too
992 * many NAKs.
993 */
994 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
995 dep->direction);
996 if (ret)
997 return ret;
998
999 list_add_tail(&req->list, &dep->request_list);
1000
1001 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && (dep->flags & DWC3_EP_BUSY))
1002 dep->flags |= DWC3_EP_PENDING_REQUEST;
1003
1004 /*
1005 * There are two special cases:
1006 *
1007 * 1. XferNotReady with empty list of requests. We need to kick the
1008 * transfer here in that situation, otherwise we will be NAKing
1009 * forever. If we get XferNotReady before gadget driver has a
1010 * chance to queue a request, we will ACK the IRQ but won't be
1011 * able to receive the data until the next request is queued.
1012 * The following code is handling exactly that.
1013 *
1014 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1015 * kick the transfer here after queuing a request, otherwise the
1016 * core may not see the modified TRB(s).
1017 */
1018 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1019 int ret;
1020 int start_trans = 1;
1021 u8 trans_idx = dep->res_trans_idx;
1022
1023 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1024 (dep->flags & DWC3_EP_BUSY)) {
1025 start_trans = 0;
1026 WARN_ON_ONCE(!trans_idx);
1027 } else {
1028 trans_idx = 0;
1029 }
1030
1031 ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans);
1032 if (ret && ret != -EBUSY) {
1033 struct dwc3 *dwc = dep->dwc;
1034
1035 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1036 dep->name);
1037 }
1038 };
1039
1040 return 0;
1041}
1042
1043static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1044 gfp_t gfp_flags)
1045{
1046 struct dwc3_request *req = to_dwc3_request(request);
1047 struct dwc3_ep *dep = to_dwc3_ep(ep);
1048 struct dwc3 *dwc = dep->dwc;
1049
1050 unsigned long flags;
1051
1052 int ret;
1053
1054 if (!dep->endpoint.desc) {
1055 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1056 request, ep->name);
1057 return -ESHUTDOWN;
1058 }
1059
1060 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1061 request, ep->name, request->length);
1062
1063 spin_lock_irqsave(&dwc->lock, flags);
1064 ret = __dwc3_gadget_ep_queue(dep, req);
1065 spin_unlock_irqrestore(&dwc->lock, flags);
1066
1067 return ret;
1068}
1069
1070static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1071 struct usb_request *request)
1072{
1073 struct dwc3_request *req = to_dwc3_request(request);
1074 struct dwc3_request *r = NULL;
1075
1076 struct dwc3_ep *dep = to_dwc3_ep(ep);
1077 struct dwc3 *dwc = dep->dwc;
1078
1079 unsigned long flags;
1080 int ret = 0;
1081
1082 spin_lock_irqsave(&dwc->lock, flags);
1083
1084 list_for_each_entry(r, &dep->request_list, list) {
1085 if (r == req)
1086 break;
1087 }
1088
1089 if (r != req) {
1090 list_for_each_entry(r, &dep->req_queued, list) {
1091 if (r == req)
1092 break;
1093 }
1094 if (r == req) {
1095 /* wait until it is processed */
1096 dwc3_stop_active_transfer(dwc, dep->number);
1097 goto out1;
1098 }
1099 dev_err(dwc->dev, "request %p was not queued to %s\n",
1100 request, ep->name);
1101 ret = -EINVAL;
1102 goto out0;
1103 }
1104
1105out1:
1106 /* giveback the request */
1107 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1108
1109out0:
1110 spin_unlock_irqrestore(&dwc->lock, flags);
1111
1112 return ret;
1113}
1114
1115int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1116{
1117 struct dwc3_gadget_ep_cmd_params params;
1118 struct dwc3 *dwc = dep->dwc;
1119 int ret;
1120
1121 memset(¶ms, 0x00, sizeof(params));
1122
1123 if (value) {
1124 if (dep->number == 0 || dep->number == 1) {
1125 /*
1126 * Whenever EP0 is stalled, we will restart
1127 * the state machine, thus moving back to
1128 * Setup Phase
1129 */
1130 dwc->ep0state = EP0_SETUP_PHASE;
1131 }
1132
1133 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1134 DWC3_DEPCMD_SETSTALL, ¶ms);
1135 if (ret)
1136 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1137 value ? "set" : "clear",
1138 dep->name);
1139 else
1140 dep->flags |= DWC3_EP_STALL;
1141 } else {
1142 if (dep->flags & DWC3_EP_WEDGE)
1143 return 0;
1144
1145 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1146 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1147 if (ret)
1148 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1149 value ? "set" : "clear",
1150 dep->name);
1151 else
1152 dep->flags &= ~DWC3_EP_STALL;
1153 }
1154
1155 return ret;
1156}
1157
1158static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1159{
1160 struct dwc3_ep *dep = to_dwc3_ep(ep);
1161 struct dwc3 *dwc = dep->dwc;
1162
1163 unsigned long flags;
1164
1165 int ret;
1166
1167 spin_lock_irqsave(&dwc->lock, flags);
1168
1169 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1170 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1171 ret = -EINVAL;
1172 goto out;
1173 }
1174
1175 ret = __dwc3_gadget_ep_set_halt(dep, value);
1176out:
1177 spin_unlock_irqrestore(&dwc->lock, flags);
1178
1179 return ret;
1180}
1181
1182static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1183{
1184 struct dwc3_ep *dep = to_dwc3_ep(ep);
1185 struct dwc3 *dwc = dep->dwc;
1186 unsigned long flags;
1187
1188 spin_lock_irqsave(&dwc->lock, flags);
1189 dep->flags |= DWC3_EP_WEDGE;
1190 spin_unlock_irqrestore(&dwc->lock, flags);
1191
1192 return dwc3_gadget_ep_set_halt(ep, 1);
1193}
1194
1195/* -------------------------------------------------------------------------- */
1196
1197static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1198 .bLength = USB_DT_ENDPOINT_SIZE,
1199 .bDescriptorType = USB_DT_ENDPOINT,
1200 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1201};
1202
1203static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1204 .enable = dwc3_gadget_ep0_enable,
1205 .disable = dwc3_gadget_ep0_disable,
1206 .alloc_request = dwc3_gadget_ep_alloc_request,
1207 .free_request = dwc3_gadget_ep_free_request,
1208 .queue = dwc3_gadget_ep0_queue,
1209 .dequeue = dwc3_gadget_ep_dequeue,
1210 .set_halt = dwc3_gadget_ep_set_halt,
1211 .set_wedge = dwc3_gadget_ep_set_wedge,
1212};
1213
1214static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1215 .enable = dwc3_gadget_ep_enable,
1216 .disable = dwc3_gadget_ep_disable,
1217 .alloc_request = dwc3_gadget_ep_alloc_request,
1218 .free_request = dwc3_gadget_ep_free_request,
1219 .queue = dwc3_gadget_ep_queue,
1220 .dequeue = dwc3_gadget_ep_dequeue,
1221 .set_halt = dwc3_gadget_ep_set_halt,
1222 .set_wedge = dwc3_gadget_ep_set_wedge,
1223};
1224
1225/* -------------------------------------------------------------------------- */
1226
1227static int dwc3_gadget_get_frame(struct usb_gadget *g)
1228{
1229 struct dwc3 *dwc = gadget_to_dwc(g);
1230 u32 reg;
1231
1232 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1233 return DWC3_DSTS_SOFFN(reg);
1234}
1235
1236static int dwc3_gadget_wakeup(struct usb_gadget *g)
1237{
1238 struct dwc3 *dwc = gadget_to_dwc(g);
1239
1240 unsigned long timeout;
1241 unsigned long flags;
1242
1243 u32 reg;
1244
1245 int ret = 0;
1246
1247 u8 link_state;
1248 u8 speed;
1249
1250 spin_lock_irqsave(&dwc->lock, flags);
1251
1252 /*
1253 * According to the Databook Remote wakeup request should
1254 * be issued only when the device is in early suspend state.
1255 *
1256 * We can check that via USB Link State bits in DSTS register.
1257 */
1258 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1259
1260 speed = reg & DWC3_DSTS_CONNECTSPD;
1261 if (speed == DWC3_DSTS_SUPERSPEED) {
1262 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1263 ret = -EINVAL;
1264 goto out;
1265 }
1266
1267 link_state = DWC3_DSTS_USBLNKST(reg);
1268
1269 switch (link_state) {
1270 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1271 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1272 break;
1273 default:
1274 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1275 link_state);
1276 ret = -EINVAL;
1277 goto out;
1278 }
1279
1280 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1281 if (ret < 0) {
1282 dev_err(dwc->dev, "failed to put link in Recovery\n");
1283 goto out;
1284 }
1285
1286 /* write zeroes to Link Change Request */
1287 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1288 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1289
1290 /* poll until Link State changes to ON */
1291 timeout = jiffies + msecs_to_jiffies(100);
1292
1293 while (!time_after(jiffies, timeout)) {
1294 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1295
1296 /* in HS, means ON */
1297 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1298 break;
1299 }
1300
1301 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1302 dev_err(dwc->dev, "failed to send remote wakeup\n");
1303 ret = -EINVAL;
1304 }
1305
1306out:
1307 spin_unlock_irqrestore(&dwc->lock, flags);
1308
1309 return ret;
1310}
1311
1312static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1313 int is_selfpowered)
1314{
1315 struct dwc3 *dwc = gadget_to_dwc(g);
1316 unsigned long flags;
1317
1318 spin_lock_irqsave(&dwc->lock, flags);
1319 dwc->is_selfpowered = !!is_selfpowered;
1320 spin_unlock_irqrestore(&dwc->lock, flags);
1321
1322 return 0;
1323}
1324
1325static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1326{
1327 u32 reg;
1328 u32 timeout = 500;
1329
1330 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1331 if (is_on) {
1332 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1333 reg |= (DWC3_DCTL_RUN_STOP
1334 | DWC3_DCTL_TRGTULST_RX_DET);
1335 } else {
1336 reg &= ~DWC3_DCTL_RUN_STOP;
1337 }
1338
1339 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1340
1341 do {
1342 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1343 if (is_on) {
1344 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1345 break;
1346 } else {
1347 if (reg & DWC3_DSTS_DEVCTRLHLT)
1348 break;
1349 }
1350 timeout--;
1351 if (!timeout)
1352 break;
1353 udelay(1);
1354 } while (1);
1355
1356 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1357 dwc->gadget_driver
1358 ? dwc->gadget_driver->function : "no-function",
1359 is_on ? "connect" : "disconnect");
1360}
1361
1362static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1363{
1364 struct dwc3 *dwc = gadget_to_dwc(g);
1365 unsigned long flags;
1366
1367 is_on = !!is_on;
1368
1369 spin_lock_irqsave(&dwc->lock, flags);
1370 dwc3_gadget_run_stop(dwc, is_on);
1371 spin_unlock_irqrestore(&dwc->lock, flags);
1372
1373 return 0;
1374}
1375
1376static int dwc3_gadget_start(struct usb_gadget *g,
1377 struct usb_gadget_driver *driver)
1378{
1379 struct dwc3 *dwc = gadget_to_dwc(g);
1380 struct dwc3_ep *dep;
1381 unsigned long flags;
1382 int ret = 0;
1383 u32 reg;
1384
1385 spin_lock_irqsave(&dwc->lock, flags);
1386
1387 if (dwc->gadget_driver) {
1388 dev_err(dwc->dev, "%s is already bound to %s\n",
1389 dwc->gadget.name,
1390 dwc->gadget_driver->driver.name);
1391 ret = -EBUSY;
1392 goto err0;
1393 }
1394
1395 dwc->gadget_driver = driver;
1396 dwc->gadget.dev.driver = &driver->driver;
1397
1398 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1399 reg &= ~(DWC3_DCFG_SPEED_MASK);
1400
1401 /**
1402 * WORKAROUND: DWC3 revision < 2.20a have an issue
1403 * which would cause metastability state on Run/Stop
1404 * bit if we try to force the IP to USB2-only mode.
1405 *
1406 * Because of that, we cannot configure the IP to any
1407 * speed other than the SuperSpeed
1408 *
1409 * Refers to:
1410 *
1411 * STAR#9000525659: Clock Domain Crossing on DCTL in
1412 * USB 2.0 Mode
1413 */
1414 if (dwc->revision < DWC3_REVISION_220A)
1415 reg |= DWC3_DCFG_SUPERSPEED;
1416 else
1417 reg |= dwc->maximum_speed;
1418 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1419
1420 dwc->start_config_issued = false;
1421
1422 /* Start with SuperSpeed Default */
1423 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1424
1425 dep = dwc->eps[0];
1426 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1427 if (ret) {
1428 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1429 goto err0;
1430 }
1431
1432 dep = dwc->eps[1];
1433 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1434 if (ret) {
1435 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1436 goto err1;
1437 }
1438
1439 /* begin to receive SETUP packets */
1440 dwc->ep0state = EP0_SETUP_PHASE;
1441 dwc3_ep0_out_start(dwc);
1442
1443 spin_unlock_irqrestore(&dwc->lock, flags);
1444
1445 return 0;
1446
1447err1:
1448 __dwc3_gadget_ep_disable(dwc->eps[0]);
1449
1450err0:
1451 spin_unlock_irqrestore(&dwc->lock, flags);
1452
1453 return ret;
1454}
1455
1456static int dwc3_gadget_stop(struct usb_gadget *g,
1457 struct usb_gadget_driver *driver)
1458{
1459 struct dwc3 *dwc = gadget_to_dwc(g);
1460 unsigned long flags;
1461
1462 spin_lock_irqsave(&dwc->lock, flags);
1463
1464 __dwc3_gadget_ep_disable(dwc->eps[0]);
1465 __dwc3_gadget_ep_disable(dwc->eps[1]);
1466
1467 dwc->gadget_driver = NULL;
1468 dwc->gadget.dev.driver = NULL;
1469
1470 spin_unlock_irqrestore(&dwc->lock, flags);
1471
1472 return 0;
1473}
1474static const struct usb_gadget_ops dwc3_gadget_ops = {
1475 .get_frame = dwc3_gadget_get_frame,
1476 .wakeup = dwc3_gadget_wakeup,
1477 .set_selfpowered = dwc3_gadget_set_selfpowered,
1478 .pullup = dwc3_gadget_pullup,
1479 .udc_start = dwc3_gadget_start,
1480 .udc_stop = dwc3_gadget_stop,
1481};
1482
1483/* -------------------------------------------------------------------------- */
1484
1485static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1486{
1487 struct dwc3_ep *dep;
1488 u8 epnum;
1489
1490 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1491
1492 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1493 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1494 if (!dep) {
1495 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1496 epnum);
1497 return -ENOMEM;
1498 }
1499
1500 dep->dwc = dwc;
1501 dep->number = epnum;
1502 dwc->eps[epnum] = dep;
1503
1504 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1505 (epnum & 1) ? "in" : "out");
1506 dep->endpoint.name = dep->name;
1507 dep->direction = (epnum & 1);
1508
1509 if (epnum == 0 || epnum == 1) {
1510 dep->endpoint.maxpacket = 512;
1511 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1512 if (!epnum)
1513 dwc->gadget.ep0 = &dep->endpoint;
1514 } else {
1515 int ret;
1516
1517 dep->endpoint.maxpacket = 1024;
1518 dep->endpoint.max_streams = 15;
1519 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1520 list_add_tail(&dep->endpoint.ep_list,
1521 &dwc->gadget.ep_list);
1522
1523 ret = dwc3_alloc_trb_pool(dep);
1524 if (ret)
1525 return ret;
1526 }
1527
1528 INIT_LIST_HEAD(&dep->request_list);
1529 INIT_LIST_HEAD(&dep->req_queued);
1530 }
1531
1532 return 0;
1533}
1534
1535static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1536{
1537 struct dwc3_ep *dep;
1538 u8 epnum;
1539
1540 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1541 dep = dwc->eps[epnum];
1542 dwc3_free_trb_pool(dep);
1543
1544 if (epnum != 0 && epnum != 1)
1545 list_del(&dep->endpoint.ep_list);
1546
1547 kfree(dep);
1548 }
1549}
1550
1551static void dwc3_gadget_release(struct device *dev)
1552{
1553 dev_dbg(dev, "%s\n", __func__);
1554}
1555
1556/* -------------------------------------------------------------------------- */
1557static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1558 const struct dwc3_event_depevt *event, int status)
1559{
1560 struct dwc3_request *req;
1561 struct dwc3_trb *trb;
1562 unsigned int count;
1563 unsigned int s_pkt = 0;
1564
1565 do {
1566 req = next_request(&dep->req_queued);
1567 if (!req) {
1568 WARN_ON_ONCE(1);
1569 return 1;
1570 }
1571
1572 trb = req->trb;
1573
1574 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1575 /*
1576 * We continue despite the error. There is not much we
1577 * can do. If we don't clean it up we loop forever. If
1578 * we skip the TRB then it gets overwritten after a
1579 * while since we use them in a ring buffer. A BUG()
1580 * would help. Lets hope that if this occurs, someone
1581 * fixes the root cause instead of looking away :)
1582 */
1583 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1584 dep->name, req->trb);
1585 count = trb->size & DWC3_TRB_SIZE_MASK;
1586
1587 if (dep->direction) {
1588 if (count) {
1589 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1590 dep->name);
1591 status = -ECONNRESET;
1592 }
1593 } else {
1594 if (count && (event->status & DEPEVT_STATUS_SHORT))
1595 s_pkt = 1;
1596 }
1597
1598 /*
1599 * We assume here we will always receive the entire data block
1600 * which we should receive. Meaning, if we program RX to
1601 * receive 4K but we receive only 2K, we assume that's all we
1602 * should receive and we simply bounce the request back to the
1603 * gadget driver for further processing.
1604 */
1605 req->request.actual += req->request.length - count;
1606 dwc3_gadget_giveback(dep, req, status);
1607 if (s_pkt)
1608 break;
1609 if ((event->status & DEPEVT_STATUS_LST) &&
1610 (trb->ctrl & DWC3_TRB_CTRL_LST))
1611 break;
1612 if ((event->status & DEPEVT_STATUS_IOC) &&
1613 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1614 break;
1615 } while (1);
1616
1617 if ((event->status & DEPEVT_STATUS_IOC) &&
1618 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1619 return 0;
1620 return 1;
1621}
1622
1623static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1624 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1625 int start_new)
1626{
1627 unsigned status = 0;
1628 int clean_busy;
1629
1630 if (event->status & DEPEVT_STATUS_BUSERR)
1631 status = -ECONNRESET;
1632
1633 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1634 if (clean_busy)
1635 dep->flags &= ~DWC3_EP_BUSY;
1636
1637 /*
1638 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1639 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1640 */
1641 if (dwc->revision < DWC3_REVISION_183A) {
1642 u32 reg;
1643 int i;
1644
1645 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1646 struct dwc3_ep *dep = dwc->eps[i];
1647
1648 if (!(dep->flags & DWC3_EP_ENABLED))
1649 continue;
1650
1651 if (!list_empty(&dep->req_queued))
1652 return;
1653 }
1654
1655 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1656 reg |= dwc->u1u2;
1657 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1658
1659 dwc->u1u2 = 0;
1660 }
1661}
1662
1663static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1664 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1665{
1666 u32 uf, mask;
1667
1668 if (list_empty(&dep->request_list)) {
1669 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1670 dep->name);
1671 return;
1672 }
1673
1674 mask = ~(dep->interval - 1);
1675 uf = event->parameters & mask;
1676 /* 4 micro frames in the future */
1677 uf += dep->interval * 4;
1678
1679 __dwc3_gadget_kick_transfer(dep, uf, 1);
1680}
1681
1682static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1683 const struct dwc3_event_depevt *event)
1684{
1685 struct dwc3 *dwc = dep->dwc;
1686 struct dwc3_event_depevt mod_ev = *event;
1687
1688 /*
1689 * We were asked to remove one request. It is possible that this
1690 * request and a few others were started together and have the same
1691 * transfer index. Since we stopped the complete endpoint we don't
1692 * know how many requests were already completed (and not yet)
1693 * reported and how could be done (later). We purge them all until
1694 * the end of the list.
1695 */
1696 mod_ev.status = DEPEVT_STATUS_LST;
1697 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1698 dep->flags &= ~DWC3_EP_BUSY;
1699 /* pending requests are ignored and are queued on XferNotReady */
1700}
1701
1702static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1703 const struct dwc3_event_depevt *event)
1704{
1705 u32 param = event->parameters;
1706 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1707
1708 switch (cmd_type) {
1709 case DWC3_DEPCMD_ENDTRANSFER:
1710 dwc3_process_ep_cmd_complete(dep, event);
1711 break;
1712 case DWC3_DEPCMD_STARTTRANSFER:
1713 dep->res_trans_idx = param & 0x7f;
1714 break;
1715 default:
1716 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1717 __func__, cmd_type);
1718 break;
1719 };
1720}
1721
1722static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1723 const struct dwc3_event_depevt *event)
1724{
1725 struct dwc3_ep *dep;
1726 u8 epnum = event->endpoint_number;
1727
1728 dep = dwc->eps[epnum];
1729
1730 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1731 dwc3_ep_event_string(event->endpoint_event));
1732
1733 if (epnum == 0 || epnum == 1) {
1734 dwc3_ep0_interrupt(dwc, event);
1735 return;
1736 }
1737
1738 switch (event->endpoint_event) {
1739 case DWC3_DEPEVT_XFERCOMPLETE:
1740 dep->res_trans_idx = 0;
1741
1742 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1743 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1744 dep->name);
1745 return;
1746 }
1747
1748 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1749 break;
1750 case DWC3_DEPEVT_XFERINPROGRESS:
1751 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1752 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1753 dep->name);
1754 return;
1755 }
1756
1757 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1758 break;
1759 case DWC3_DEPEVT_XFERNOTREADY:
1760 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1761 dwc3_gadget_start_isoc(dwc, dep, event);
1762 } else {
1763 int ret;
1764
1765 dev_vdbg(dwc->dev, "%s: reason %s\n",
1766 dep->name, event->status &
1767 DEPEVT_STATUS_TRANSFER_ACTIVE
1768 ? "Transfer Active"
1769 : "Transfer Not Active");
1770
1771 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1772 if (!ret || ret == -EBUSY)
1773 return;
1774
1775 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1776 dep->name);
1777 }
1778
1779 break;
1780 case DWC3_DEPEVT_STREAMEVT:
1781 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1782 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1783 dep->name);
1784 return;
1785 }
1786
1787 switch (event->status) {
1788 case DEPEVT_STREAMEVT_FOUND:
1789 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1790 event->parameters);
1791
1792 break;
1793 case DEPEVT_STREAMEVT_NOTFOUND:
1794 /* FALLTHROUGH */
1795 default:
1796 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1797 }
1798 break;
1799 case DWC3_DEPEVT_RXTXFIFOEVT:
1800 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1801 break;
1802 case DWC3_DEPEVT_EPCMDCMPLT:
1803 dwc3_ep_cmd_compl(dep, event);
1804 break;
1805 }
1806}
1807
1808static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1809{
1810 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1811 spin_unlock(&dwc->lock);
1812 dwc->gadget_driver->disconnect(&dwc->gadget);
1813 spin_lock(&dwc->lock);
1814 }
1815}
1816
1817static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1818{
1819 struct dwc3_ep *dep;
1820 struct dwc3_gadget_ep_cmd_params params;
1821 u32 cmd;
1822 int ret;
1823
1824 dep = dwc->eps[epnum];
1825
1826 WARN_ON(!dep->res_trans_idx);
1827 if (dep->res_trans_idx) {
1828 cmd = DWC3_DEPCMD_ENDTRANSFER;
1829 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1830 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1831 memset(¶ms, 0, sizeof(params));
1832 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1833 WARN_ON_ONCE(ret);
1834 dep->res_trans_idx = 0;
1835 }
1836}
1837
1838static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1839{
1840 u32 epnum;
1841
1842 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1843 struct dwc3_ep *dep;
1844
1845 dep = dwc->eps[epnum];
1846 if (!(dep->flags & DWC3_EP_ENABLED))
1847 continue;
1848
1849 dwc3_remove_requests(dwc, dep);
1850 }
1851}
1852
1853static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1854{
1855 u32 epnum;
1856
1857 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1858 struct dwc3_ep *dep;
1859 struct dwc3_gadget_ep_cmd_params params;
1860 int ret;
1861
1862 dep = dwc->eps[epnum];
1863
1864 if (!(dep->flags & DWC3_EP_STALL))
1865 continue;
1866
1867 dep->flags &= ~DWC3_EP_STALL;
1868
1869 memset(¶ms, 0, sizeof(params));
1870 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1871 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1872 WARN_ON_ONCE(ret);
1873 }
1874}
1875
1876static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1877{
1878 dev_vdbg(dwc->dev, "%s\n", __func__);
1879#if 0
1880 XXX
1881 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1882 enable it before we can disable it.
1883
1884 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1885 reg &= ~DWC3_DCTL_INITU1ENA;
1886 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1887
1888 reg &= ~DWC3_DCTL_INITU2ENA;
1889 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1890#endif
1891
1892 dwc3_stop_active_transfers(dwc);
1893 dwc3_disconnect_gadget(dwc);
1894 dwc->start_config_issued = false;
1895
1896 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1897 dwc->setup_packet_pending = false;
1898}
1899
1900static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1901{
1902 u32 reg;
1903
1904 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1905
1906 if (on)
1907 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1908 else
1909 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1910
1911 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1912}
1913
1914static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1915{
1916 u32 reg;
1917
1918 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1919
1920 if (on)
1921 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1922 else
1923 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1924
1925 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1926}
1927
1928static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1929{
1930 u32 reg;
1931
1932 dev_vdbg(dwc->dev, "%s\n", __func__);
1933
1934 /*
1935 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1936 * would cause a missing Disconnect Event if there's a
1937 * pending Setup Packet in the FIFO.
1938 *
1939 * There's no suggested workaround on the official Bug
1940 * report, which states that "unless the driver/application
1941 * is doing any special handling of a disconnect event,
1942 * there is no functional issue".
1943 *
1944 * Unfortunately, it turns out that we _do_ some special
1945 * handling of a disconnect event, namely complete all
1946 * pending transfers, notify gadget driver of the
1947 * disconnection, and so on.
1948 *
1949 * Our suggested workaround is to follow the Disconnect
1950 * Event steps here, instead, based on a setup_packet_pending
1951 * flag. Such flag gets set whenever we have a XferNotReady
1952 * event on EP0 and gets cleared on XferComplete for the
1953 * same endpoint.
1954 *
1955 * Refers to:
1956 *
1957 * STAR#9000466709: RTL: Device : Disconnect event not
1958 * generated if setup packet pending in FIFO
1959 */
1960 if (dwc->revision < DWC3_REVISION_188A) {
1961 if (dwc->setup_packet_pending)
1962 dwc3_gadget_disconnect_interrupt(dwc);
1963 }
1964
1965 /* after reset -> Default State */
1966 dwc->dev_state = DWC3_DEFAULT_STATE;
1967
1968 /* Enable PHYs */
1969 dwc3_gadget_usb2_phy_power(dwc, true);
1970 dwc3_gadget_usb3_phy_power(dwc, true);
1971
1972 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1973 dwc3_disconnect_gadget(dwc);
1974
1975 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1976 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1977 reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
1978 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1979 dwc->test_mode = false;
1980
1981 dwc3_stop_active_transfers(dwc);
1982 dwc3_clear_stall_all_ep(dwc);
1983 dwc->start_config_issued = false;
1984
1985 /* Reset device address to zero */
1986 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1987 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1988 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1989}
1990
1991static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1992{
1993 u32 reg;
1994 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1995
1996 /*
1997 * We change the clock only at SS but I dunno why I would want to do
1998 * this. Maybe it becomes part of the power saving plan.
1999 */
2000
2001 if (speed != DWC3_DSTS_SUPERSPEED)
2002 return;
2003
2004 /*
2005 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2006 * each time on Connect Done.
2007 */
2008 if (!usb30_clock)
2009 return;
2010
2011 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2012 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2013 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2014}
2015
2016static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
2017{
2018 switch (speed) {
2019 case USB_SPEED_SUPER:
2020 dwc3_gadget_usb2_phy_power(dwc, false);
2021 break;
2022 case USB_SPEED_HIGH:
2023 case USB_SPEED_FULL:
2024 case USB_SPEED_LOW:
2025 dwc3_gadget_usb3_phy_power(dwc, false);
2026 break;
2027 }
2028}
2029
2030static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2031{
2032 struct dwc3_gadget_ep_cmd_params params;
2033 struct dwc3_ep *dep;
2034 int ret;
2035 u32 reg;
2036 u8 speed;
2037
2038 dev_vdbg(dwc->dev, "%s\n", __func__);
2039
2040 memset(¶ms, 0x00, sizeof(params));
2041
2042 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2043 speed = reg & DWC3_DSTS_CONNECTSPD;
2044 dwc->speed = speed;
2045
2046 dwc3_update_ram_clk_sel(dwc, speed);
2047
2048 switch (speed) {
2049 case DWC3_DCFG_SUPERSPEED:
2050 /*
2051 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2052 * would cause a missing USB3 Reset event.
2053 *
2054 * In such situations, we should force a USB3 Reset
2055 * event by calling our dwc3_gadget_reset_interrupt()
2056 * routine.
2057 *
2058 * Refers to:
2059 *
2060 * STAR#9000483510: RTL: SS : USB3 reset event may
2061 * not be generated always when the link enters poll
2062 */
2063 if (dwc->revision < DWC3_REVISION_190A)
2064 dwc3_gadget_reset_interrupt(dwc);
2065
2066 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2067 dwc->gadget.ep0->maxpacket = 512;
2068 dwc->gadget.speed = USB_SPEED_SUPER;
2069 break;
2070 case DWC3_DCFG_HIGHSPEED:
2071 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2072 dwc->gadget.ep0->maxpacket = 64;
2073 dwc->gadget.speed = USB_SPEED_HIGH;
2074 break;
2075 case DWC3_DCFG_FULLSPEED2:
2076 case DWC3_DCFG_FULLSPEED1:
2077 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2078 dwc->gadget.ep0->maxpacket = 64;
2079 dwc->gadget.speed = USB_SPEED_FULL;
2080 break;
2081 case DWC3_DCFG_LOWSPEED:
2082 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2083 dwc->gadget.ep0->maxpacket = 8;
2084 dwc->gadget.speed = USB_SPEED_LOW;
2085 break;
2086 }
2087
2088 /* Disable unneded PHY */
2089 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
2090
2091 dep = dwc->eps[0];
2092 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2093 if (ret) {
2094 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2095 return;
2096 }
2097
2098 dep = dwc->eps[1];
2099 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2100 if (ret) {
2101 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2102 return;
2103 }
2104
2105 /*
2106 * Configure PHY via GUSB3PIPECTLn if required.
2107 *
2108 * Update GTXFIFOSIZn
2109 *
2110 * In both cases reset values should be sufficient.
2111 */
2112}
2113
2114static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2115{
2116 dev_vdbg(dwc->dev, "%s\n", __func__);
2117
2118 /*
2119 * TODO take core out of low power mode when that's
2120 * implemented.
2121 */
2122
2123 dwc->gadget_driver->resume(&dwc->gadget);
2124}
2125
2126static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2127 unsigned int evtinfo)
2128{
2129 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2130
2131 /*
2132 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2133 * on the link partner, the USB session might do multiple entry/exit
2134 * of low power states before a transfer takes place.
2135 *
2136 * Due to this problem, we might experience lower throughput. The
2137 * suggested workaround is to disable DCTL[12:9] bits if we're
2138 * transitioning from U1/U2 to U0 and enable those bits again
2139 * after a transfer completes and there are no pending transfers
2140 * on any of the enabled endpoints.
2141 *
2142 * This is the first half of that workaround.
2143 *
2144 * Refers to:
2145 *
2146 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2147 * core send LGO_Ux entering U0
2148 */
2149 if (dwc->revision < DWC3_REVISION_183A) {
2150 if (next == DWC3_LINK_STATE_U0) {
2151 u32 u1u2;
2152 u32 reg;
2153
2154 switch (dwc->link_state) {
2155 case DWC3_LINK_STATE_U1:
2156 case DWC3_LINK_STATE_U2:
2157 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2158 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2159 | DWC3_DCTL_ACCEPTU2ENA
2160 | DWC3_DCTL_INITU1ENA
2161 | DWC3_DCTL_ACCEPTU1ENA);
2162
2163 if (!dwc->u1u2)
2164 dwc->u1u2 = reg & u1u2;
2165
2166 reg &= ~u1u2;
2167
2168 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2169 break;
2170 default:
2171 /* do nothing */
2172 break;
2173 }
2174 }
2175 }
2176
2177 dwc->link_state = next;
2178
2179 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2180}
2181
2182static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2183 const struct dwc3_event_devt *event)
2184{
2185 switch (event->type) {
2186 case DWC3_DEVICE_EVENT_DISCONNECT:
2187 dwc3_gadget_disconnect_interrupt(dwc);
2188 break;
2189 case DWC3_DEVICE_EVENT_RESET:
2190 dwc3_gadget_reset_interrupt(dwc);
2191 break;
2192 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2193 dwc3_gadget_conndone_interrupt(dwc);
2194 break;
2195 case DWC3_DEVICE_EVENT_WAKEUP:
2196 dwc3_gadget_wakeup_interrupt(dwc);
2197 break;
2198 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2199 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2200 break;
2201 case DWC3_DEVICE_EVENT_EOPF:
2202 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2203 break;
2204 case DWC3_DEVICE_EVENT_SOF:
2205 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2206 break;
2207 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2208 dev_vdbg(dwc->dev, "Erratic Error\n");
2209 break;
2210 case DWC3_DEVICE_EVENT_CMD_CMPL:
2211 dev_vdbg(dwc->dev, "Command Complete\n");
2212 break;
2213 case DWC3_DEVICE_EVENT_OVERFLOW:
2214 dev_vdbg(dwc->dev, "Overflow\n");
2215 break;
2216 default:
2217 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2218 }
2219}
2220
2221static void dwc3_process_event_entry(struct dwc3 *dwc,
2222 const union dwc3_event *event)
2223{
2224 /* Endpoint IRQ, handle it and return early */
2225 if (event->type.is_devspec == 0) {
2226 /* depevt */
2227 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2228 }
2229
2230 switch (event->type.type) {
2231 case DWC3_EVENT_TYPE_DEV:
2232 dwc3_gadget_interrupt(dwc, &event->devt);
2233 break;
2234 /* REVISIT what to do with Carkit and I2C events ? */
2235 default:
2236 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2237 }
2238}
2239
2240static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2241{
2242 struct dwc3_event_buffer *evt;
2243 int left;
2244 u32 count;
2245
2246 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2247 count &= DWC3_GEVNTCOUNT_MASK;
2248 if (!count)
2249 return IRQ_NONE;
2250
2251 evt = dwc->ev_buffs[buf];
2252 left = count;
2253
2254 while (left > 0) {
2255 union dwc3_event event;
2256
2257 event.raw = *(u32 *) (evt->buf + evt->lpos);
2258
2259 dwc3_process_event_entry(dwc, &event);
2260 /*
2261 * XXX we wrap around correctly to the next entry as almost all
2262 * entries are 4 bytes in size. There is one entry which has 12
2263 * bytes which is a regular entry followed by 8 bytes data. ATM
2264 * I don't know how things are organized if were get next to the
2265 * a boundary so I worry about that once we try to handle that.
2266 */
2267 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2268 left -= 4;
2269
2270 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2271 }
2272
2273 return IRQ_HANDLED;
2274}
2275
2276static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2277{
2278 struct dwc3 *dwc = _dwc;
2279 int i;
2280 irqreturn_t ret = IRQ_NONE;
2281
2282 spin_lock(&dwc->lock);
2283
2284 for (i = 0; i < dwc->num_event_buffers; i++) {
2285 irqreturn_t status;
2286
2287 status = dwc3_process_event_buf(dwc, i);
2288 if (status == IRQ_HANDLED)
2289 ret = status;
2290 }
2291
2292 spin_unlock(&dwc->lock);
2293
2294 return ret;
2295}
2296
2297/**
2298 * dwc3_gadget_init - Initializes gadget related registers
2299 * @dwc: pointer to our controller context structure
2300 *
2301 * Returns 0 on success otherwise negative errno.
2302 */
2303int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2304{
2305 u32 reg;
2306 int ret;
2307 int irq;
2308
2309 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2310 &dwc->ctrl_req_addr, GFP_KERNEL);
2311 if (!dwc->ctrl_req) {
2312 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2313 ret = -ENOMEM;
2314 goto err0;
2315 }
2316
2317 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2318 &dwc->ep0_trb_addr, GFP_KERNEL);
2319 if (!dwc->ep0_trb) {
2320 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2321 ret = -ENOMEM;
2322 goto err1;
2323 }
2324
2325 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2326 if (!dwc->setup_buf) {
2327 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2328 ret = -ENOMEM;
2329 goto err2;
2330 }
2331
2332 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2333 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2334 GFP_KERNEL);
2335 if (!dwc->ep0_bounce) {
2336 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2337 ret = -ENOMEM;
2338 goto err3;
2339 }
2340
2341 dev_set_name(&dwc->gadget.dev, "gadget");
2342
2343 dwc->gadget.ops = &dwc3_gadget_ops;
2344 dwc->gadget.max_speed = USB_SPEED_SUPER;
2345 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2346 dwc->gadget.dev.parent = dwc->dev;
2347 dwc->gadget.sg_supported = true;
2348
2349 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2350
2351 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2352 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2353 dwc->gadget.dev.release = dwc3_gadget_release;
2354 dwc->gadget.name = "dwc3-gadget";
2355
2356 /*
2357 * REVISIT: Here we should clear all pending IRQs to be
2358 * sure we're starting from a well known location.
2359 */
2360
2361 ret = dwc3_gadget_init_endpoints(dwc);
2362 if (ret)
2363 goto err4;
2364
2365 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2366
2367 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2368 "dwc3", dwc);
2369 if (ret) {
2370 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2371 irq, ret);
2372 goto err5;
2373 }
2374
2375 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2376 reg |= DWC3_DCFG_LPM_CAP;
2377 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2378
2379 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2380 reg |= DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA;
2381 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2382
2383 /* Enable all but Start and End of Frame IRQs */
2384 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2385 DWC3_DEVTEN_EVNTOVERFLOWEN |
2386 DWC3_DEVTEN_CMDCMPLTEN |
2387 DWC3_DEVTEN_ERRTICERREN |
2388 DWC3_DEVTEN_WKUPEVTEN |
2389 DWC3_DEVTEN_ULSTCNGEN |
2390 DWC3_DEVTEN_CONNECTDONEEN |
2391 DWC3_DEVTEN_USBRSTEN |
2392 DWC3_DEVTEN_DISCONNEVTEN);
2393 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2394
2395 ret = device_register(&dwc->gadget.dev);
2396 if (ret) {
2397 dev_err(dwc->dev, "failed to register gadget device\n");
2398 put_device(&dwc->gadget.dev);
2399 goto err6;
2400 }
2401
2402 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2403 if (ret) {
2404 dev_err(dwc->dev, "failed to register udc\n");
2405 goto err7;
2406 }
2407
2408 return 0;
2409
2410err7:
2411 device_unregister(&dwc->gadget.dev);
2412
2413err6:
2414 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2415 free_irq(irq, dwc);
2416
2417err5:
2418 dwc3_gadget_free_endpoints(dwc);
2419
2420err4:
2421 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2422 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2423
2424err3:
2425 kfree(dwc->setup_buf);
2426
2427err2:
2428 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2429 dwc->ep0_trb, dwc->ep0_trb_addr);
2430
2431err1:
2432 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2433 dwc->ctrl_req, dwc->ctrl_req_addr);
2434
2435err0:
2436 return ret;
2437}
2438
2439void dwc3_gadget_exit(struct dwc3 *dwc)
2440{
2441 int irq;
2442
2443 usb_del_gadget_udc(&dwc->gadget);
2444 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2445
2446 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2447 free_irq(irq, dwc);
2448
2449 dwc3_gadget_free_endpoints(dwc);
2450
2451 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2452 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2453
2454 kfree(dwc->setup_buf);
2455
2456 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2457 dwc->ep0_trb, dwc->ep0_trb_addr);
2458
2459 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2460 dwc->ctrl_req, dwc->ctrl_req_addr);
2461
2462 device_unregister(&dwc->gadget.dev);
2463}