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1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
33#include "debug.h"
34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
97 int retries = 10000;
98 u32 reg;
99
100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
131 /* wait for a change in DSTS */
132 retries = 10000;
133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
139 udelay(5);
140 }
141
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
144
145 return -ETIMEDOUT;
146}
147
148/**
149 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
150 * @dwc: pointer to our context structure
151 *
152 * This function will a best effort FIFO allocation in order
153 * to improve FIFO usage and throughput, while still allowing
154 * us to enable as many endpoints as possible.
155 *
156 * Keep in mind that this operation will be highly dependent
157 * on the configured size for RAM1 - which contains TxFifo -,
158 * the amount of endpoints enabled on coreConsultant tool, and
159 * the width of the Master Bus.
160 *
161 * In the ideal world, we would always be able to satisfy the
162 * following equation:
163 *
164 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
165 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
166 *
167 * Unfortunately, due to many variables that's not always the case.
168 */
169int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
170{
171 int last_fifo_depth = 0;
172 int ram1_depth;
173 int fifo_size;
174 int mdwidth;
175 int num;
176
177 if (!dwc->needs_fifo_resize)
178 return 0;
179
180 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
181 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
182
183 /* MDWIDTH is represented in bits, we need it in bytes */
184 mdwidth >>= 3;
185
186 /*
187 * FIXME For now we will only allocate 1 wMaxPacketSize space
188 * for each enabled endpoint, later patches will come to
189 * improve this algorithm so that we better use the internal
190 * FIFO space
191 */
192 for (num = 0; num < dwc->num_in_eps; num++) {
193 /* bit0 indicates direction; 1 means IN ep */
194 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
195 int mult = 1;
196 int tmp;
197
198 if (!(dep->flags & DWC3_EP_ENABLED))
199 continue;
200
201 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
202 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
203 mult = 3;
204
205 /*
206 * REVISIT: the following assumes we will always have enough
207 * space available on the FIFO RAM for all possible use cases.
208 * Make sure that's true somehow and change FIFO allocation
209 * accordingly.
210 *
211 * If we have Bulk or Isochronous endpoints, we want
212 * them to be able to be very, very fast. So we're giving
213 * those endpoints a fifo_size which is enough for 3 full
214 * packets
215 */
216 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
217 tmp += mdwidth;
218
219 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
220
221 fifo_size |= (last_fifo_depth << 16);
222
223 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
224 dep->name, last_fifo_depth, fifo_size & 0xffff);
225
226 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
227
228 last_fifo_depth += (fifo_size & 0xffff);
229 }
230
231 return 0;
232}
233
234void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
235 int status)
236{
237 struct dwc3 *dwc = dep->dwc;
238 int i;
239
240 if (req->queued) {
241 i = 0;
242 do {
243 dep->busy_slot++;
244 /*
245 * Skip LINK TRB. We can't use req->trb and check for
246 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
247 * just completed (not the LINK TRB).
248 */
249 if (((dep->busy_slot & DWC3_TRB_MASK) ==
250 DWC3_TRB_NUM- 1) &&
251 usb_endpoint_xfer_isoc(dep->endpoint.desc))
252 dep->busy_slot++;
253 } while(++i < req->request.num_mapped_sgs);
254 req->queued = false;
255 }
256 list_del(&req->list);
257 req->trb = NULL;
258
259 if (req->request.status == -EINPROGRESS)
260 req->request.status = status;
261
262 if (dwc->ep0_bounced && dep->number == 0)
263 dwc->ep0_bounced = false;
264 else
265 usb_gadget_unmap_request(&dwc->gadget, &req->request,
266 req->direction);
267
268 trace_dwc3_gadget_giveback(req);
269
270 spin_unlock(&dwc->lock);
271 usb_gadget_giveback_request(&dep->endpoint, &req->request);
272 spin_lock(&dwc->lock);
273}
274
275int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
276{
277 u32 timeout = 500;
278 u32 reg;
279
280 trace_dwc3_gadget_generic_cmd(cmd, param);
281
282 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
283 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
284
285 do {
286 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
287 if (!(reg & DWC3_DGCMD_CMDACT)) {
288 dwc3_trace(trace_dwc3_gadget,
289 "Command Complete --> %d",
290 DWC3_DGCMD_STATUS(reg));
291 if (DWC3_DGCMD_STATUS(reg))
292 return -EINVAL;
293 return 0;
294 }
295
296 /*
297 * We can't sleep here, because it's also called from
298 * interrupt context.
299 */
300 timeout--;
301 if (!timeout) {
302 dwc3_trace(trace_dwc3_gadget,
303 "Command Timed Out");
304 return -ETIMEDOUT;
305 }
306 udelay(1);
307 } while (1);
308}
309
310int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
311 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
312{
313 struct dwc3_ep *dep = dwc->eps[ep];
314 u32 timeout = 500;
315 u32 reg;
316
317 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
318
319 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
320 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
321 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
322
323 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
324 do {
325 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
326 if (!(reg & DWC3_DEPCMD_CMDACT)) {
327 dwc3_trace(trace_dwc3_gadget,
328 "Command Complete --> %d",
329 DWC3_DEPCMD_STATUS(reg));
330 if (DWC3_DEPCMD_STATUS(reg))
331 return -EINVAL;
332 return 0;
333 }
334
335 /*
336 * We can't sleep here, because it is also called from
337 * interrupt context.
338 */
339 timeout--;
340 if (!timeout) {
341 dwc3_trace(trace_dwc3_gadget,
342 "Command Timed Out");
343 return -ETIMEDOUT;
344 }
345
346 udelay(1);
347 } while (1);
348}
349
350static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
351 struct dwc3_trb *trb)
352{
353 u32 offset = (char *) trb - (char *) dep->trb_pool;
354
355 return dep->trb_pool_dma + offset;
356}
357
358static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
359{
360 struct dwc3 *dwc = dep->dwc;
361
362 if (dep->trb_pool)
363 return 0;
364
365 dep->trb_pool = dma_alloc_coherent(dwc->dev,
366 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
367 &dep->trb_pool_dma, GFP_KERNEL);
368 if (!dep->trb_pool) {
369 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
370 dep->name);
371 return -ENOMEM;
372 }
373
374 return 0;
375}
376
377static void dwc3_free_trb_pool(struct dwc3_ep *dep)
378{
379 struct dwc3 *dwc = dep->dwc;
380
381 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
382 dep->trb_pool, dep->trb_pool_dma);
383
384 dep->trb_pool = NULL;
385 dep->trb_pool_dma = 0;
386}
387
388static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
389
390/**
391 * dwc3_gadget_start_config - Configure EP resources
392 * @dwc: pointer to our controller context structure
393 * @dep: endpoint that is being enabled
394 *
395 * The assignment of transfer resources cannot perfectly follow the
396 * data book due to the fact that the controller driver does not have
397 * all knowledge of the configuration in advance. It is given this
398 * information piecemeal by the composite gadget framework after every
399 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
400 * programming model in this scenario can cause errors. For two
401 * reasons:
402 *
403 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
404 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
405 * multiple interfaces.
406 *
407 * 2) The databook does not mention doing more DEPXFERCFG for new
408 * endpoint on alt setting (8.1.6).
409 *
410 * The following simplified method is used instead:
411 *
412 * All hardware endpoints can be assigned a transfer resource and this
413 * setting will stay persistent until either a core reset or
414 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
415 * do DEPXFERCFG for every hardware endpoint as well. We are
416 * guaranteed that there are as many transfer resources as endpoints.
417 *
418 * This function is called for each endpoint when it is being enabled
419 * but is triggered only when called for EP0-out, which always happens
420 * first, and which should only happen in one of the above conditions.
421 */
422static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
423{
424 struct dwc3_gadget_ep_cmd_params params;
425 u32 cmd;
426 int i;
427 int ret;
428
429 if (dep->number)
430 return 0;
431
432 memset(¶ms, 0x00, sizeof(params));
433 cmd = DWC3_DEPCMD_DEPSTARTCFG;
434
435 ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
436 if (ret)
437 return ret;
438
439 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
440 struct dwc3_ep *dep = dwc->eps[i];
441
442 if (!dep)
443 continue;
444
445 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
446 if (ret)
447 return ret;
448 }
449
450 return 0;
451}
452
453static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
454 const struct usb_endpoint_descriptor *desc,
455 const struct usb_ss_ep_comp_descriptor *comp_desc,
456 bool ignore, bool restore)
457{
458 struct dwc3_gadget_ep_cmd_params params;
459
460 memset(¶ms, 0x00, sizeof(params));
461
462 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
463 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
464
465 /* Burst size is only needed in SuperSpeed mode */
466 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
467 u32 burst = dep->endpoint.maxburst - 1;
468
469 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
470 }
471
472 if (ignore)
473 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
474
475 if (restore) {
476 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
477 params.param2 |= dep->saved_state;
478 }
479
480 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
481 | DWC3_DEPCFG_XFER_NOT_READY_EN;
482
483 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
484 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
485 | DWC3_DEPCFG_STREAM_EVENT_EN;
486 dep->stream_capable = true;
487 }
488
489 if (!usb_endpoint_xfer_control(desc))
490 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
491
492 /*
493 * We are doing 1:1 mapping for endpoints, meaning
494 * Physical Endpoints 2 maps to Logical Endpoint 2 and
495 * so on. We consider the direction bit as part of the physical
496 * endpoint number. So USB endpoint 0x81 is 0x03.
497 */
498 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
499
500 /*
501 * We must use the lower 16 TX FIFOs even though
502 * HW might have more
503 */
504 if (dep->direction)
505 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
506
507 if (desc->bInterval) {
508 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
509 dep->interval = 1 << (desc->bInterval - 1);
510 }
511
512 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
513 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
514}
515
516static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
517{
518 struct dwc3_gadget_ep_cmd_params params;
519
520 memset(¶ms, 0x00, sizeof(params));
521
522 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
523
524 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
525 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
526}
527
528/**
529 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
530 * @dep: endpoint to be initialized
531 * @desc: USB Endpoint Descriptor
532 *
533 * Caller should take care of locking
534 */
535static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
536 const struct usb_endpoint_descriptor *desc,
537 const struct usb_ss_ep_comp_descriptor *comp_desc,
538 bool ignore, bool restore)
539{
540 struct dwc3 *dwc = dep->dwc;
541 u32 reg;
542 int ret;
543
544 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
545
546 if (!(dep->flags & DWC3_EP_ENABLED)) {
547 ret = dwc3_gadget_start_config(dwc, dep);
548 if (ret)
549 return ret;
550 }
551
552 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
553 restore);
554 if (ret)
555 return ret;
556
557 if (!(dep->flags & DWC3_EP_ENABLED)) {
558 struct dwc3_trb *trb_st_hw;
559 struct dwc3_trb *trb_link;
560
561 dep->endpoint.desc = desc;
562 dep->comp_desc = comp_desc;
563 dep->type = usb_endpoint_type(desc);
564 dep->flags |= DWC3_EP_ENABLED;
565
566 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
567 reg |= DWC3_DALEPENA_EP(dep->number);
568 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
569
570 if (!usb_endpoint_xfer_isoc(desc))
571 goto out;
572
573 /* Link TRB for ISOC. The HWO bit is never reset */
574 trb_st_hw = &dep->trb_pool[0];
575
576 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
577 memset(trb_link, 0, sizeof(*trb_link));
578
579 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
580 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
581 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
582 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
583 }
584
585out:
586 switch (usb_endpoint_type(desc)) {
587 case USB_ENDPOINT_XFER_CONTROL:
588 /* don't change name */
589 break;
590 case USB_ENDPOINT_XFER_ISOC:
591 strlcat(dep->name, "-isoc", sizeof(dep->name));
592 break;
593 case USB_ENDPOINT_XFER_BULK:
594 strlcat(dep->name, "-bulk", sizeof(dep->name));
595 break;
596 case USB_ENDPOINT_XFER_INT:
597 strlcat(dep->name, "-int", sizeof(dep->name));
598 break;
599 default:
600 dev_err(dwc->dev, "invalid endpoint transfer type\n");
601 }
602
603 return 0;
604}
605
606static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
607static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
608{
609 struct dwc3_request *req;
610
611 if (!list_empty(&dep->req_queued)) {
612 dwc3_stop_active_transfer(dwc, dep->number, true);
613
614 /* - giveback all requests to gadget driver */
615 while (!list_empty(&dep->req_queued)) {
616 req = next_request(&dep->req_queued);
617
618 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
619 }
620 }
621
622 while (!list_empty(&dep->request_list)) {
623 req = next_request(&dep->request_list);
624
625 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
626 }
627}
628
629/**
630 * __dwc3_gadget_ep_disable - Disables a HW endpoint
631 * @dep: the endpoint to disable
632 *
633 * This function also removes requests which are currently processed ny the
634 * hardware and those which are not yet scheduled.
635 * Caller should take care of locking.
636 */
637static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
638{
639 struct dwc3 *dwc = dep->dwc;
640 u32 reg;
641
642 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
643
644 dwc3_remove_requests(dwc, dep);
645
646 /* make sure HW endpoint isn't stalled */
647 if (dep->flags & DWC3_EP_STALL)
648 __dwc3_gadget_ep_set_halt(dep, 0, false);
649
650 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
651 reg &= ~DWC3_DALEPENA_EP(dep->number);
652 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
653
654 dep->stream_capable = false;
655 dep->endpoint.desc = NULL;
656 dep->comp_desc = NULL;
657 dep->type = 0;
658 dep->flags = 0;
659
660 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
661 dep->number >> 1,
662 (dep->number & 1) ? "in" : "out");
663
664 return 0;
665}
666
667/* -------------------------------------------------------------------------- */
668
669static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
670 const struct usb_endpoint_descriptor *desc)
671{
672 return -EINVAL;
673}
674
675static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
676{
677 return -EINVAL;
678}
679
680/* -------------------------------------------------------------------------- */
681
682static int dwc3_gadget_ep_enable(struct usb_ep *ep,
683 const struct usb_endpoint_descriptor *desc)
684{
685 struct dwc3_ep *dep;
686 struct dwc3 *dwc;
687 unsigned long flags;
688 int ret;
689
690 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
691 pr_debug("dwc3: invalid parameters\n");
692 return -EINVAL;
693 }
694
695 if (!desc->wMaxPacketSize) {
696 pr_debug("dwc3: missing wMaxPacketSize\n");
697 return -EINVAL;
698 }
699
700 dep = to_dwc3_ep(ep);
701 dwc = dep->dwc;
702
703 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
704 "%s is already enabled\n",
705 dep->name))
706 return 0;
707
708 spin_lock_irqsave(&dwc->lock, flags);
709 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
710 spin_unlock_irqrestore(&dwc->lock, flags);
711
712 return ret;
713}
714
715static int dwc3_gadget_ep_disable(struct usb_ep *ep)
716{
717 struct dwc3_ep *dep;
718 struct dwc3 *dwc;
719 unsigned long flags;
720 int ret;
721
722 if (!ep) {
723 pr_debug("dwc3: invalid parameters\n");
724 return -EINVAL;
725 }
726
727 dep = to_dwc3_ep(ep);
728 dwc = dep->dwc;
729
730 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
731 "%s is already disabled\n",
732 dep->name))
733 return 0;
734
735 spin_lock_irqsave(&dwc->lock, flags);
736 ret = __dwc3_gadget_ep_disable(dep);
737 spin_unlock_irqrestore(&dwc->lock, flags);
738
739 return ret;
740}
741
742static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
743 gfp_t gfp_flags)
744{
745 struct dwc3_request *req;
746 struct dwc3_ep *dep = to_dwc3_ep(ep);
747
748 req = kzalloc(sizeof(*req), gfp_flags);
749 if (!req)
750 return NULL;
751
752 req->epnum = dep->number;
753 req->dep = dep;
754
755 trace_dwc3_alloc_request(req);
756
757 return &req->request;
758}
759
760static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
761 struct usb_request *request)
762{
763 struct dwc3_request *req = to_dwc3_request(request);
764
765 trace_dwc3_free_request(req);
766 kfree(req);
767}
768
769/**
770 * dwc3_prepare_one_trb - setup one TRB from one request
771 * @dep: endpoint for which this request is prepared
772 * @req: dwc3_request pointer
773 */
774static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
775 struct dwc3_request *req, dma_addr_t dma,
776 unsigned length, unsigned last, unsigned chain, unsigned node)
777{
778 struct dwc3_trb *trb;
779
780 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
781 dep->name, req, (unsigned long long) dma,
782 length, last ? " last" : "",
783 chain ? " chain" : "");
784
785
786 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
787
788 if (!req->trb) {
789 dwc3_gadget_move_request_queued(req);
790 req->trb = trb;
791 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
792 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
793 }
794
795 dep->free_slot++;
796 /* Skip the LINK-TRB on ISOC */
797 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
798 usb_endpoint_xfer_isoc(dep->endpoint.desc))
799 dep->free_slot++;
800
801 trb->size = DWC3_TRB_SIZE_LENGTH(length);
802 trb->bpl = lower_32_bits(dma);
803 trb->bph = upper_32_bits(dma);
804
805 switch (usb_endpoint_type(dep->endpoint.desc)) {
806 case USB_ENDPOINT_XFER_CONTROL:
807 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
808 break;
809
810 case USB_ENDPOINT_XFER_ISOC:
811 if (!node)
812 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
813 else
814 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
815 break;
816
817 case USB_ENDPOINT_XFER_BULK:
818 case USB_ENDPOINT_XFER_INT:
819 trb->ctrl = DWC3_TRBCTL_NORMAL;
820 break;
821 default:
822 /*
823 * This is only possible with faulty memory because we
824 * checked it already :)
825 */
826 BUG();
827 }
828
829 if (!req->request.no_interrupt && !chain)
830 trb->ctrl |= DWC3_TRB_CTRL_IOC;
831
832 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
833 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
834 trb->ctrl |= DWC3_TRB_CTRL_CSP;
835 } else if (last) {
836 trb->ctrl |= DWC3_TRB_CTRL_LST;
837 }
838
839 if (chain)
840 trb->ctrl |= DWC3_TRB_CTRL_CHN;
841
842 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
843 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
844
845 trb->ctrl |= DWC3_TRB_CTRL_HWO;
846
847 trace_dwc3_prepare_trb(dep, trb);
848}
849
850/*
851 * dwc3_prepare_trbs - setup TRBs from requests
852 * @dep: endpoint for which requests are being prepared
853 * @starting: true if the endpoint is idle and no requests are queued.
854 *
855 * The function goes through the requests list and sets up TRBs for the
856 * transfers. The function returns once there are no more TRBs available or
857 * it runs out of requests.
858 */
859static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
860{
861 struct dwc3_request *req, *n;
862 u32 trbs_left;
863 u32 max;
864 unsigned int last_one = 0;
865
866 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
867
868 /* the first request must not be queued */
869 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
870
871 /* Can't wrap around on a non-isoc EP since there's no link TRB */
872 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
873 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
874 if (trbs_left > max)
875 trbs_left = max;
876 }
877
878 /*
879 * If busy & slot are equal than it is either full or empty. If we are
880 * starting to process requests then we are empty. Otherwise we are
881 * full and don't do anything
882 */
883 if (!trbs_left) {
884 if (!starting)
885 return;
886 trbs_left = DWC3_TRB_NUM;
887 /*
888 * In case we start from scratch, we queue the ISOC requests
889 * starting from slot 1. This is done because we use ring
890 * buffer and have no LST bit to stop us. Instead, we place
891 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
892 * after the first request so we start at slot 1 and have
893 * 7 requests proceed before we hit the first IOC.
894 * Other transfer types don't use the ring buffer and are
895 * processed from the first TRB until the last one. Since we
896 * don't wrap around we have to start at the beginning.
897 */
898 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
899 dep->busy_slot = 1;
900 dep->free_slot = 1;
901 } else {
902 dep->busy_slot = 0;
903 dep->free_slot = 0;
904 }
905 }
906
907 /* The last TRB is a link TRB, not used for xfer */
908 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
909 return;
910
911 list_for_each_entry_safe(req, n, &dep->request_list, list) {
912 unsigned length;
913 dma_addr_t dma;
914 last_one = false;
915
916 if (req->request.num_mapped_sgs > 0) {
917 struct usb_request *request = &req->request;
918 struct scatterlist *sg = request->sg;
919 struct scatterlist *s;
920 int i;
921
922 for_each_sg(sg, s, request->num_mapped_sgs, i) {
923 unsigned chain = true;
924
925 length = sg_dma_len(s);
926 dma = sg_dma_address(s);
927
928 if (i == (request->num_mapped_sgs - 1) ||
929 sg_is_last(s)) {
930 if (list_empty(&dep->request_list))
931 last_one = true;
932 chain = false;
933 }
934
935 trbs_left--;
936 if (!trbs_left)
937 last_one = true;
938
939 if (last_one)
940 chain = false;
941
942 dwc3_prepare_one_trb(dep, req, dma, length,
943 last_one, chain, i);
944
945 if (last_one)
946 break;
947 }
948
949 if (last_one)
950 break;
951 } else {
952 dma = req->request.dma;
953 length = req->request.length;
954 trbs_left--;
955
956 if (!trbs_left)
957 last_one = 1;
958
959 /* Is this the last request? */
960 if (list_is_last(&req->list, &dep->request_list))
961 last_one = 1;
962
963 dwc3_prepare_one_trb(dep, req, dma, length,
964 last_one, false, 0);
965
966 if (last_one)
967 break;
968 }
969 }
970}
971
972static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
973 int start_new)
974{
975 struct dwc3_gadget_ep_cmd_params params;
976 struct dwc3_request *req;
977 struct dwc3 *dwc = dep->dwc;
978 int ret;
979 u32 cmd;
980
981 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
982 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
983 return -EBUSY;
984 }
985
986 /*
987 * If we are getting here after a short-out-packet we don't enqueue any
988 * new requests as we try to set the IOC bit only on the last request.
989 */
990 if (start_new) {
991 if (list_empty(&dep->req_queued))
992 dwc3_prepare_trbs(dep, start_new);
993
994 /* req points to the first request which will be sent */
995 req = next_request(&dep->req_queued);
996 } else {
997 dwc3_prepare_trbs(dep, start_new);
998
999 /*
1000 * req points to the first request where HWO changed from 0 to 1
1001 */
1002 req = next_request(&dep->req_queued);
1003 }
1004 if (!req) {
1005 dep->flags |= DWC3_EP_PENDING_REQUEST;
1006 return 0;
1007 }
1008
1009 memset(¶ms, 0, sizeof(params));
1010
1011 if (start_new) {
1012 params.param0 = upper_32_bits(req->trb_dma);
1013 params.param1 = lower_32_bits(req->trb_dma);
1014 cmd = DWC3_DEPCMD_STARTTRANSFER;
1015 } else {
1016 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1017 }
1018
1019 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1020 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1021 if (ret < 0) {
1022 /*
1023 * FIXME we need to iterate over the list of requests
1024 * here and stop, unmap, free and del each of the linked
1025 * requests instead of what we do now.
1026 */
1027 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1028 req->direction);
1029 list_del(&req->list);
1030 return ret;
1031 }
1032
1033 dep->flags |= DWC3_EP_BUSY;
1034
1035 if (start_new) {
1036 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1037 dep->number);
1038 WARN_ON_ONCE(!dep->resource_index);
1039 }
1040
1041 return 0;
1042}
1043
1044static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1045 struct dwc3_ep *dep, u32 cur_uf)
1046{
1047 u32 uf;
1048
1049 if (list_empty(&dep->request_list)) {
1050 dwc3_trace(trace_dwc3_gadget,
1051 "ISOC ep %s run out for requests",
1052 dep->name);
1053 dep->flags |= DWC3_EP_PENDING_REQUEST;
1054 return;
1055 }
1056
1057 /* 4 micro frames in the future */
1058 uf = cur_uf + dep->interval * 4;
1059
1060 __dwc3_gadget_kick_transfer(dep, uf, 1);
1061}
1062
1063static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1064 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1065{
1066 u32 cur_uf, mask;
1067
1068 mask = ~(dep->interval - 1);
1069 cur_uf = event->parameters & mask;
1070
1071 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1072}
1073
1074static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1075{
1076 struct dwc3 *dwc = dep->dwc;
1077 int ret;
1078
1079 if (!dep->endpoint.desc) {
1080 dwc3_trace(trace_dwc3_gadget,
1081 "trying to queue request %p to disabled %s\n",
1082 &req->request, dep->endpoint.name);
1083 return -ESHUTDOWN;
1084 }
1085
1086 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1087 &req->request, req->dep->name)) {
1088 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1089 &req->request, req->dep->name);
1090 return -EINVAL;
1091 }
1092
1093 req->request.actual = 0;
1094 req->request.status = -EINPROGRESS;
1095 req->direction = dep->direction;
1096 req->epnum = dep->number;
1097
1098 trace_dwc3_ep_queue(req);
1099
1100 /*
1101 * We only add to our list of requests now and
1102 * start consuming the list once we get XferNotReady
1103 * IRQ.
1104 *
1105 * That way, we avoid doing anything that we don't need
1106 * to do now and defer it until the point we receive a
1107 * particular token from the Host side.
1108 *
1109 * This will also avoid Host cancelling URBs due to too
1110 * many NAKs.
1111 */
1112 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1113 dep->direction);
1114 if (ret)
1115 return ret;
1116
1117 list_add_tail(&req->list, &dep->request_list);
1118
1119 /*
1120 * If there are no pending requests and the endpoint isn't already
1121 * busy, we will just start the request straight away.
1122 *
1123 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1124 * little bit faster.
1125 */
1126 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1127 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1128 !(dep->flags & DWC3_EP_BUSY)) {
1129 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1130 goto out;
1131 }
1132
1133 /*
1134 * There are a few special cases:
1135 *
1136 * 1. XferNotReady with empty list of requests. We need to kick the
1137 * transfer here in that situation, otherwise we will be NAKing
1138 * forever. If we get XferNotReady before gadget driver has a
1139 * chance to queue a request, we will ACK the IRQ but won't be
1140 * able to receive the data until the next request is queued.
1141 * The following code is handling exactly that.
1142 *
1143 */
1144 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1145 /*
1146 * If xfernotready is already elapsed and it is a case
1147 * of isoc transfer, then issue END TRANSFER, so that
1148 * you can receive xfernotready again and can have
1149 * notion of current microframe.
1150 */
1151 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1152 if (list_empty(&dep->req_queued)) {
1153 dwc3_stop_active_transfer(dwc, dep->number, true);
1154 dep->flags = DWC3_EP_ENABLED;
1155 }
1156 return 0;
1157 }
1158
1159 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1160 if (!ret)
1161 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1162
1163 goto out;
1164 }
1165
1166 /*
1167 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1168 * kick the transfer here after queuing a request, otherwise the
1169 * core may not see the modified TRB(s).
1170 */
1171 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1172 (dep->flags & DWC3_EP_BUSY) &&
1173 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1174 WARN_ON_ONCE(!dep->resource_index);
1175 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1176 false);
1177 goto out;
1178 }
1179
1180 /*
1181 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1182 * right away, otherwise host will not know we have streams to be
1183 * handled.
1184 */
1185 if (dep->stream_capable)
1186 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1187
1188out:
1189 if (ret && ret != -EBUSY)
1190 dwc3_trace(trace_dwc3_gadget,
1191 "%s: failed to kick transfers\n",
1192 dep->name);
1193 if (ret == -EBUSY)
1194 ret = 0;
1195
1196 return ret;
1197}
1198
1199static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1200 struct usb_request *request)
1201{
1202 dwc3_gadget_ep_free_request(ep, request);
1203}
1204
1205static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1206{
1207 struct dwc3_request *req;
1208 struct usb_request *request;
1209 struct usb_ep *ep = &dep->endpoint;
1210
1211 dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1212 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1213 if (!request)
1214 return -ENOMEM;
1215
1216 request->length = 0;
1217 request->buf = dwc->zlp_buf;
1218 request->complete = __dwc3_gadget_ep_zlp_complete;
1219
1220 req = to_dwc3_request(request);
1221
1222 return __dwc3_gadget_ep_queue(dep, req);
1223}
1224
1225static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1226 gfp_t gfp_flags)
1227{
1228 struct dwc3_request *req = to_dwc3_request(request);
1229 struct dwc3_ep *dep = to_dwc3_ep(ep);
1230 struct dwc3 *dwc = dep->dwc;
1231
1232 unsigned long flags;
1233
1234 int ret;
1235
1236 spin_lock_irqsave(&dwc->lock, flags);
1237 ret = __dwc3_gadget_ep_queue(dep, req);
1238
1239 /*
1240 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1241 * setting request->zero, instead of doing magic, we will just queue an
1242 * extra usb_request ourselves so that it gets handled the same way as
1243 * any other request.
1244 */
1245 if (ret == 0 && request->zero && request->length &&
1246 (request->length % ep->maxpacket == 0))
1247 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1248
1249 spin_unlock_irqrestore(&dwc->lock, flags);
1250
1251 return ret;
1252}
1253
1254static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1255 struct usb_request *request)
1256{
1257 struct dwc3_request *req = to_dwc3_request(request);
1258 struct dwc3_request *r = NULL;
1259
1260 struct dwc3_ep *dep = to_dwc3_ep(ep);
1261 struct dwc3 *dwc = dep->dwc;
1262
1263 unsigned long flags;
1264 int ret = 0;
1265
1266 trace_dwc3_ep_dequeue(req);
1267
1268 spin_lock_irqsave(&dwc->lock, flags);
1269
1270 list_for_each_entry(r, &dep->request_list, list) {
1271 if (r == req)
1272 break;
1273 }
1274
1275 if (r != req) {
1276 list_for_each_entry(r, &dep->req_queued, list) {
1277 if (r == req)
1278 break;
1279 }
1280 if (r == req) {
1281 /* wait until it is processed */
1282 dwc3_stop_active_transfer(dwc, dep->number, true);
1283 goto out1;
1284 }
1285 dev_err(dwc->dev, "request %p was not queued to %s\n",
1286 request, ep->name);
1287 ret = -EINVAL;
1288 goto out0;
1289 }
1290
1291out1:
1292 /* giveback the request */
1293 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1294
1295out0:
1296 spin_unlock_irqrestore(&dwc->lock, flags);
1297
1298 return ret;
1299}
1300
1301int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1302{
1303 struct dwc3_gadget_ep_cmd_params params;
1304 struct dwc3 *dwc = dep->dwc;
1305 int ret;
1306
1307 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1308 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1309 return -EINVAL;
1310 }
1311
1312 memset(¶ms, 0x00, sizeof(params));
1313
1314 if (value) {
1315 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1316 (!list_empty(&dep->req_queued) ||
1317 !list_empty(&dep->request_list)))) {
1318 dwc3_trace(trace_dwc3_gadget,
1319 "%s: pending request, cannot halt\n",
1320 dep->name);
1321 return -EAGAIN;
1322 }
1323
1324 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1325 DWC3_DEPCMD_SETSTALL, ¶ms);
1326 if (ret)
1327 dev_err(dwc->dev, "failed to set STALL on %s\n",
1328 dep->name);
1329 else
1330 dep->flags |= DWC3_EP_STALL;
1331 } else {
1332 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1333 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1334 if (ret)
1335 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1336 dep->name);
1337 else
1338 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1339 }
1340
1341 return ret;
1342}
1343
1344static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1345{
1346 struct dwc3_ep *dep = to_dwc3_ep(ep);
1347 struct dwc3 *dwc = dep->dwc;
1348
1349 unsigned long flags;
1350
1351 int ret;
1352
1353 spin_lock_irqsave(&dwc->lock, flags);
1354 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1355 spin_unlock_irqrestore(&dwc->lock, flags);
1356
1357 return ret;
1358}
1359
1360static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1361{
1362 struct dwc3_ep *dep = to_dwc3_ep(ep);
1363 struct dwc3 *dwc = dep->dwc;
1364 unsigned long flags;
1365 int ret;
1366
1367 spin_lock_irqsave(&dwc->lock, flags);
1368 dep->flags |= DWC3_EP_WEDGE;
1369
1370 if (dep->number == 0 || dep->number == 1)
1371 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1372 else
1373 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1374 spin_unlock_irqrestore(&dwc->lock, flags);
1375
1376 return ret;
1377}
1378
1379/* -------------------------------------------------------------------------- */
1380
1381static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1382 .bLength = USB_DT_ENDPOINT_SIZE,
1383 .bDescriptorType = USB_DT_ENDPOINT,
1384 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1385};
1386
1387static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1388 .enable = dwc3_gadget_ep0_enable,
1389 .disable = dwc3_gadget_ep0_disable,
1390 .alloc_request = dwc3_gadget_ep_alloc_request,
1391 .free_request = dwc3_gadget_ep_free_request,
1392 .queue = dwc3_gadget_ep0_queue,
1393 .dequeue = dwc3_gadget_ep_dequeue,
1394 .set_halt = dwc3_gadget_ep0_set_halt,
1395 .set_wedge = dwc3_gadget_ep_set_wedge,
1396};
1397
1398static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1399 .enable = dwc3_gadget_ep_enable,
1400 .disable = dwc3_gadget_ep_disable,
1401 .alloc_request = dwc3_gadget_ep_alloc_request,
1402 .free_request = dwc3_gadget_ep_free_request,
1403 .queue = dwc3_gadget_ep_queue,
1404 .dequeue = dwc3_gadget_ep_dequeue,
1405 .set_halt = dwc3_gadget_ep_set_halt,
1406 .set_wedge = dwc3_gadget_ep_set_wedge,
1407};
1408
1409/* -------------------------------------------------------------------------- */
1410
1411static int dwc3_gadget_get_frame(struct usb_gadget *g)
1412{
1413 struct dwc3 *dwc = gadget_to_dwc(g);
1414 u32 reg;
1415
1416 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1417 return DWC3_DSTS_SOFFN(reg);
1418}
1419
1420static int dwc3_gadget_wakeup(struct usb_gadget *g)
1421{
1422 struct dwc3 *dwc = gadget_to_dwc(g);
1423
1424 unsigned long timeout;
1425 unsigned long flags;
1426
1427 u32 reg;
1428
1429 int ret = 0;
1430
1431 u8 link_state;
1432 u8 speed;
1433
1434 spin_lock_irqsave(&dwc->lock, flags);
1435
1436 /*
1437 * According to the Databook Remote wakeup request should
1438 * be issued only when the device is in early suspend state.
1439 *
1440 * We can check that via USB Link State bits in DSTS register.
1441 */
1442 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1443
1444 speed = reg & DWC3_DSTS_CONNECTSPD;
1445 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1446 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1447 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1448 ret = -EINVAL;
1449 goto out;
1450 }
1451
1452 link_state = DWC3_DSTS_USBLNKST(reg);
1453
1454 switch (link_state) {
1455 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1456 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1457 break;
1458 default:
1459 dwc3_trace(trace_dwc3_gadget,
1460 "can't wakeup from '%s'\n",
1461 dwc3_gadget_link_string(link_state));
1462 ret = -EINVAL;
1463 goto out;
1464 }
1465
1466 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1467 if (ret < 0) {
1468 dev_err(dwc->dev, "failed to put link in Recovery\n");
1469 goto out;
1470 }
1471
1472 /* Recent versions do this automatically */
1473 if (dwc->revision < DWC3_REVISION_194A) {
1474 /* write zeroes to Link Change Request */
1475 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1476 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1477 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1478 }
1479
1480 /* poll until Link State changes to ON */
1481 timeout = jiffies + msecs_to_jiffies(100);
1482
1483 while (!time_after(jiffies, timeout)) {
1484 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1485
1486 /* in HS, means ON */
1487 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1488 break;
1489 }
1490
1491 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1492 dev_err(dwc->dev, "failed to send remote wakeup\n");
1493 ret = -EINVAL;
1494 }
1495
1496out:
1497 spin_unlock_irqrestore(&dwc->lock, flags);
1498
1499 return ret;
1500}
1501
1502static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1503 int is_selfpowered)
1504{
1505 struct dwc3 *dwc = gadget_to_dwc(g);
1506 unsigned long flags;
1507
1508 spin_lock_irqsave(&dwc->lock, flags);
1509 g->is_selfpowered = !!is_selfpowered;
1510 spin_unlock_irqrestore(&dwc->lock, flags);
1511
1512 return 0;
1513}
1514
1515static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1516{
1517 u32 reg;
1518 u32 timeout = 500;
1519
1520 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1521 if (is_on) {
1522 if (dwc->revision <= DWC3_REVISION_187A) {
1523 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1524 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1525 }
1526
1527 if (dwc->revision >= DWC3_REVISION_194A)
1528 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1529 reg |= DWC3_DCTL_RUN_STOP;
1530
1531 if (dwc->has_hibernation)
1532 reg |= DWC3_DCTL_KEEP_CONNECT;
1533
1534 dwc->pullups_connected = true;
1535 } else {
1536 reg &= ~DWC3_DCTL_RUN_STOP;
1537
1538 if (dwc->has_hibernation && !suspend)
1539 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1540
1541 dwc->pullups_connected = false;
1542 }
1543
1544 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1545
1546 do {
1547 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1548 if (is_on) {
1549 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1550 break;
1551 } else {
1552 if (reg & DWC3_DSTS_DEVCTRLHLT)
1553 break;
1554 }
1555 timeout--;
1556 if (!timeout)
1557 return -ETIMEDOUT;
1558 udelay(1);
1559 } while (1);
1560
1561 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1562 dwc->gadget_driver
1563 ? dwc->gadget_driver->function : "no-function",
1564 is_on ? "connect" : "disconnect");
1565
1566 return 0;
1567}
1568
1569static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1570{
1571 struct dwc3 *dwc = gadget_to_dwc(g);
1572 unsigned long flags;
1573 int ret;
1574
1575 is_on = !!is_on;
1576
1577 spin_lock_irqsave(&dwc->lock, flags);
1578 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1579 spin_unlock_irqrestore(&dwc->lock, flags);
1580
1581 return ret;
1582}
1583
1584static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1585{
1586 u32 reg;
1587
1588 /* Enable all but Start and End of Frame IRQs */
1589 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1590 DWC3_DEVTEN_EVNTOVERFLOWEN |
1591 DWC3_DEVTEN_CMDCMPLTEN |
1592 DWC3_DEVTEN_ERRTICERREN |
1593 DWC3_DEVTEN_WKUPEVTEN |
1594 DWC3_DEVTEN_ULSTCNGEN |
1595 DWC3_DEVTEN_CONNECTDONEEN |
1596 DWC3_DEVTEN_USBRSTEN |
1597 DWC3_DEVTEN_DISCONNEVTEN);
1598
1599 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1600}
1601
1602static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1603{
1604 /* mask all interrupts */
1605 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1606}
1607
1608static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1609static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1610
1611static int dwc3_gadget_start(struct usb_gadget *g,
1612 struct usb_gadget_driver *driver)
1613{
1614 struct dwc3 *dwc = gadget_to_dwc(g);
1615 struct dwc3_ep *dep;
1616 unsigned long flags;
1617 int ret = 0;
1618 int irq;
1619 u32 reg;
1620
1621 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1622 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1623 IRQF_SHARED, "dwc3", dwc);
1624 if (ret) {
1625 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1626 irq, ret);
1627 goto err0;
1628 }
1629
1630 spin_lock_irqsave(&dwc->lock, flags);
1631
1632 if (dwc->gadget_driver) {
1633 dev_err(dwc->dev, "%s is already bound to %s\n",
1634 dwc->gadget.name,
1635 dwc->gadget_driver->driver.name);
1636 ret = -EBUSY;
1637 goto err1;
1638 }
1639
1640 dwc->gadget_driver = driver;
1641
1642 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1643 reg &= ~(DWC3_DCFG_SPEED_MASK);
1644
1645 /**
1646 * WORKAROUND: DWC3 revision < 2.20a have an issue
1647 * which would cause metastability state on Run/Stop
1648 * bit if we try to force the IP to USB2-only mode.
1649 *
1650 * Because of that, we cannot configure the IP to any
1651 * speed other than the SuperSpeed
1652 *
1653 * Refers to:
1654 *
1655 * STAR#9000525659: Clock Domain Crossing on DCTL in
1656 * USB 2.0 Mode
1657 */
1658 if (dwc->revision < DWC3_REVISION_220A) {
1659 reg |= DWC3_DCFG_SUPERSPEED;
1660 } else {
1661 switch (dwc->maximum_speed) {
1662 case USB_SPEED_LOW:
1663 reg |= DWC3_DSTS_LOWSPEED;
1664 break;
1665 case USB_SPEED_FULL:
1666 reg |= DWC3_DSTS_FULLSPEED1;
1667 break;
1668 case USB_SPEED_HIGH:
1669 reg |= DWC3_DSTS_HIGHSPEED;
1670 break;
1671 case USB_SPEED_SUPER_PLUS:
1672 reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1673 break;
1674 default:
1675 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1676 dwc->maximum_speed);
1677 /* fall through */
1678 case USB_SPEED_SUPER:
1679 reg |= DWC3_DCFG_SUPERSPEED;
1680 break;
1681 }
1682 }
1683 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1684
1685 /* Start with SuperSpeed Default */
1686 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1687
1688 dep = dwc->eps[0];
1689 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1690 false);
1691 if (ret) {
1692 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1693 goto err2;
1694 }
1695
1696 dep = dwc->eps[1];
1697 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1698 false);
1699 if (ret) {
1700 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1701 goto err3;
1702 }
1703
1704 /* begin to receive SETUP packets */
1705 dwc->ep0state = EP0_SETUP_PHASE;
1706 dwc3_ep0_out_start(dwc);
1707
1708 dwc3_gadget_enable_irq(dwc);
1709
1710 spin_unlock_irqrestore(&dwc->lock, flags);
1711
1712 return 0;
1713
1714err3:
1715 __dwc3_gadget_ep_disable(dwc->eps[0]);
1716
1717err2:
1718 dwc->gadget_driver = NULL;
1719
1720err1:
1721 spin_unlock_irqrestore(&dwc->lock, flags);
1722
1723 free_irq(irq, dwc);
1724
1725err0:
1726 return ret;
1727}
1728
1729static int dwc3_gadget_stop(struct usb_gadget *g)
1730{
1731 struct dwc3 *dwc = gadget_to_dwc(g);
1732 unsigned long flags;
1733 int irq;
1734
1735 spin_lock_irqsave(&dwc->lock, flags);
1736
1737 dwc3_gadget_disable_irq(dwc);
1738 __dwc3_gadget_ep_disable(dwc->eps[0]);
1739 __dwc3_gadget_ep_disable(dwc->eps[1]);
1740
1741 dwc->gadget_driver = NULL;
1742
1743 spin_unlock_irqrestore(&dwc->lock, flags);
1744
1745 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1746 free_irq(irq, dwc);
1747
1748 return 0;
1749}
1750
1751static const struct usb_gadget_ops dwc3_gadget_ops = {
1752 .get_frame = dwc3_gadget_get_frame,
1753 .wakeup = dwc3_gadget_wakeup,
1754 .set_selfpowered = dwc3_gadget_set_selfpowered,
1755 .pullup = dwc3_gadget_pullup,
1756 .udc_start = dwc3_gadget_start,
1757 .udc_stop = dwc3_gadget_stop,
1758};
1759
1760/* -------------------------------------------------------------------------- */
1761
1762static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1763 u8 num, u32 direction)
1764{
1765 struct dwc3_ep *dep;
1766 u8 i;
1767
1768 for (i = 0; i < num; i++) {
1769 u8 epnum = (i << 1) | (!!direction);
1770
1771 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1772 if (!dep)
1773 return -ENOMEM;
1774
1775 dep->dwc = dwc;
1776 dep->number = epnum;
1777 dep->direction = !!direction;
1778 dwc->eps[epnum] = dep;
1779
1780 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1781 (epnum & 1) ? "in" : "out");
1782
1783 dep->endpoint.name = dep->name;
1784
1785 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1786
1787 if (epnum == 0 || epnum == 1) {
1788 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1789 dep->endpoint.maxburst = 1;
1790 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1791 if (!epnum)
1792 dwc->gadget.ep0 = &dep->endpoint;
1793 } else {
1794 int ret;
1795
1796 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1797 dep->endpoint.max_streams = 15;
1798 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1799 list_add_tail(&dep->endpoint.ep_list,
1800 &dwc->gadget.ep_list);
1801
1802 ret = dwc3_alloc_trb_pool(dep);
1803 if (ret)
1804 return ret;
1805 }
1806
1807 if (epnum == 0 || epnum == 1) {
1808 dep->endpoint.caps.type_control = true;
1809 } else {
1810 dep->endpoint.caps.type_iso = true;
1811 dep->endpoint.caps.type_bulk = true;
1812 dep->endpoint.caps.type_int = true;
1813 }
1814
1815 dep->endpoint.caps.dir_in = !!direction;
1816 dep->endpoint.caps.dir_out = !direction;
1817
1818 INIT_LIST_HEAD(&dep->request_list);
1819 INIT_LIST_HEAD(&dep->req_queued);
1820 }
1821
1822 return 0;
1823}
1824
1825static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1826{
1827 int ret;
1828
1829 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1830
1831 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1832 if (ret < 0) {
1833 dwc3_trace(trace_dwc3_gadget,
1834 "failed to allocate OUT endpoints");
1835 return ret;
1836 }
1837
1838 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1839 if (ret < 0) {
1840 dwc3_trace(trace_dwc3_gadget,
1841 "failed to allocate IN endpoints");
1842 return ret;
1843 }
1844
1845 return 0;
1846}
1847
1848static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1849{
1850 struct dwc3_ep *dep;
1851 u8 epnum;
1852
1853 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1854 dep = dwc->eps[epnum];
1855 if (!dep)
1856 continue;
1857 /*
1858 * Physical endpoints 0 and 1 are special; they form the
1859 * bi-directional USB endpoint 0.
1860 *
1861 * For those two physical endpoints, we don't allocate a TRB
1862 * pool nor do we add them the endpoints list. Due to that, we
1863 * shouldn't do these two operations otherwise we would end up
1864 * with all sorts of bugs when removing dwc3.ko.
1865 */
1866 if (epnum != 0 && epnum != 1) {
1867 dwc3_free_trb_pool(dep);
1868 list_del(&dep->endpoint.ep_list);
1869 }
1870
1871 kfree(dep);
1872 }
1873}
1874
1875/* -------------------------------------------------------------------------- */
1876
1877static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1878 struct dwc3_request *req, struct dwc3_trb *trb,
1879 const struct dwc3_event_depevt *event, int status)
1880{
1881 unsigned int count;
1882 unsigned int s_pkt = 0;
1883 unsigned int trb_status;
1884
1885 trace_dwc3_complete_trb(dep, trb);
1886
1887 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1888 /*
1889 * We continue despite the error. There is not much we
1890 * can do. If we don't clean it up we loop forever. If
1891 * we skip the TRB then it gets overwritten after a
1892 * while since we use them in a ring buffer. A BUG()
1893 * would help. Lets hope that if this occurs, someone
1894 * fixes the root cause instead of looking away :)
1895 */
1896 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1897 dep->name, trb);
1898 count = trb->size & DWC3_TRB_SIZE_MASK;
1899
1900 if (dep->direction) {
1901 if (count) {
1902 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1903 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1904 dwc3_trace(trace_dwc3_gadget,
1905 "%s: incomplete IN transfer\n",
1906 dep->name);
1907 /*
1908 * If missed isoc occurred and there is
1909 * no request queued then issue END
1910 * TRANSFER, so that core generates
1911 * next xfernotready and we will issue
1912 * a fresh START TRANSFER.
1913 * If there are still queued request
1914 * then wait, do not issue either END
1915 * or UPDATE TRANSFER, just attach next
1916 * request in request_list during
1917 * giveback.If any future queued request
1918 * is successfully transferred then we
1919 * will issue UPDATE TRANSFER for all
1920 * request in the request_list.
1921 */
1922 dep->flags |= DWC3_EP_MISSED_ISOC;
1923 } else {
1924 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1925 dep->name);
1926 status = -ECONNRESET;
1927 }
1928 } else {
1929 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1930 }
1931 } else {
1932 if (count && (event->status & DEPEVT_STATUS_SHORT))
1933 s_pkt = 1;
1934 }
1935
1936 /*
1937 * We assume here we will always receive the entire data block
1938 * which we should receive. Meaning, if we program RX to
1939 * receive 4K but we receive only 2K, we assume that's all we
1940 * should receive and we simply bounce the request back to the
1941 * gadget driver for further processing.
1942 */
1943 req->request.actual += req->request.length - count;
1944 if (s_pkt)
1945 return 1;
1946 if ((event->status & DEPEVT_STATUS_LST) &&
1947 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1948 DWC3_TRB_CTRL_HWO)))
1949 return 1;
1950 if ((event->status & DEPEVT_STATUS_IOC) &&
1951 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1952 return 1;
1953 return 0;
1954}
1955
1956static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1957 const struct dwc3_event_depevt *event, int status)
1958{
1959 struct dwc3_request *req;
1960 struct dwc3_trb *trb;
1961 unsigned int slot;
1962 unsigned int i;
1963 int ret;
1964
1965 do {
1966 req = next_request(&dep->req_queued);
1967 if (WARN_ON_ONCE(!req))
1968 return 1;
1969
1970 i = 0;
1971 do {
1972 slot = req->start_slot + i;
1973 if ((slot == DWC3_TRB_NUM - 1) &&
1974 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1975 slot++;
1976 slot %= DWC3_TRB_NUM;
1977 trb = &dep->trb_pool[slot];
1978
1979 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1980 event, status);
1981 if (ret)
1982 break;
1983 } while (++i < req->request.num_mapped_sgs);
1984
1985 dwc3_gadget_giveback(dep, req, status);
1986
1987 if (ret)
1988 break;
1989 } while (1);
1990
1991 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1992 list_empty(&dep->req_queued)) {
1993 if (list_empty(&dep->request_list)) {
1994 /*
1995 * If there is no entry in request list then do
1996 * not issue END TRANSFER now. Just set PENDING
1997 * flag, so that END TRANSFER is issued when an
1998 * entry is added into request list.
1999 */
2000 dep->flags = DWC3_EP_PENDING_REQUEST;
2001 } else {
2002 dwc3_stop_active_transfer(dwc, dep->number, true);
2003 dep->flags = DWC3_EP_ENABLED;
2004 }
2005 return 1;
2006 }
2007
2008 return 1;
2009}
2010
2011static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2012 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2013{
2014 unsigned status = 0;
2015 int clean_busy;
2016 u32 is_xfer_complete;
2017
2018 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2019
2020 if (event->status & DEPEVT_STATUS_BUSERR)
2021 status = -ECONNRESET;
2022
2023 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2024 if (clean_busy && (is_xfer_complete ||
2025 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2026 dep->flags &= ~DWC3_EP_BUSY;
2027
2028 /*
2029 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2030 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2031 */
2032 if (dwc->revision < DWC3_REVISION_183A) {
2033 u32 reg;
2034 int i;
2035
2036 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2037 dep = dwc->eps[i];
2038
2039 if (!(dep->flags & DWC3_EP_ENABLED))
2040 continue;
2041
2042 if (!list_empty(&dep->req_queued))
2043 return;
2044 }
2045
2046 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2047 reg |= dwc->u1u2;
2048 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2049
2050 dwc->u1u2 = 0;
2051 }
2052
2053 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2054 int ret;
2055
2056 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2057 if (!ret || ret == -EBUSY)
2058 return;
2059 }
2060}
2061
2062static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2063 const struct dwc3_event_depevt *event)
2064{
2065 struct dwc3_ep *dep;
2066 u8 epnum = event->endpoint_number;
2067
2068 dep = dwc->eps[epnum];
2069
2070 if (!(dep->flags & DWC3_EP_ENABLED))
2071 return;
2072
2073 if (epnum == 0 || epnum == 1) {
2074 dwc3_ep0_interrupt(dwc, event);
2075 return;
2076 }
2077
2078 switch (event->endpoint_event) {
2079 case DWC3_DEPEVT_XFERCOMPLETE:
2080 dep->resource_index = 0;
2081
2082 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2083 dwc3_trace(trace_dwc3_gadget,
2084 "%s is an Isochronous endpoint\n",
2085 dep->name);
2086 return;
2087 }
2088
2089 dwc3_endpoint_transfer_complete(dwc, dep, event);
2090 break;
2091 case DWC3_DEPEVT_XFERINPROGRESS:
2092 dwc3_endpoint_transfer_complete(dwc, dep, event);
2093 break;
2094 case DWC3_DEPEVT_XFERNOTREADY:
2095 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2096 dwc3_gadget_start_isoc(dwc, dep, event);
2097 } else {
2098 int active;
2099 int ret;
2100
2101 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2102
2103 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2104 dep->name, active ? "Transfer Active"
2105 : "Transfer Not Active");
2106
2107 ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2108 if (!ret || ret == -EBUSY)
2109 return;
2110
2111 dwc3_trace(trace_dwc3_gadget,
2112 "%s: failed to kick transfers\n",
2113 dep->name);
2114 }
2115
2116 break;
2117 case DWC3_DEPEVT_STREAMEVT:
2118 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2119 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2120 dep->name);
2121 return;
2122 }
2123
2124 switch (event->status) {
2125 case DEPEVT_STREAMEVT_FOUND:
2126 dwc3_trace(trace_dwc3_gadget,
2127 "Stream %d found and started",
2128 event->parameters);
2129
2130 break;
2131 case DEPEVT_STREAMEVT_NOTFOUND:
2132 /* FALLTHROUGH */
2133 default:
2134 dwc3_trace(trace_dwc3_gadget,
2135 "unable to find suitable stream\n");
2136 }
2137 break;
2138 case DWC3_DEPEVT_RXTXFIFOEVT:
2139 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2140 break;
2141 case DWC3_DEPEVT_EPCMDCMPLT:
2142 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2143 break;
2144 }
2145}
2146
2147static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2148{
2149 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2150 spin_unlock(&dwc->lock);
2151 dwc->gadget_driver->disconnect(&dwc->gadget);
2152 spin_lock(&dwc->lock);
2153 }
2154}
2155
2156static void dwc3_suspend_gadget(struct dwc3 *dwc)
2157{
2158 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2159 spin_unlock(&dwc->lock);
2160 dwc->gadget_driver->suspend(&dwc->gadget);
2161 spin_lock(&dwc->lock);
2162 }
2163}
2164
2165static void dwc3_resume_gadget(struct dwc3 *dwc)
2166{
2167 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2168 spin_unlock(&dwc->lock);
2169 dwc->gadget_driver->resume(&dwc->gadget);
2170 spin_lock(&dwc->lock);
2171 }
2172}
2173
2174static void dwc3_reset_gadget(struct dwc3 *dwc)
2175{
2176 if (!dwc->gadget_driver)
2177 return;
2178
2179 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2180 spin_unlock(&dwc->lock);
2181 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2182 spin_lock(&dwc->lock);
2183 }
2184}
2185
2186static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2187{
2188 struct dwc3_ep *dep;
2189 struct dwc3_gadget_ep_cmd_params params;
2190 u32 cmd;
2191 int ret;
2192
2193 dep = dwc->eps[epnum];
2194
2195 if (!dep->resource_index)
2196 return;
2197
2198 /*
2199 * NOTICE: We are violating what the Databook says about the
2200 * EndTransfer command. Ideally we would _always_ wait for the
2201 * EndTransfer Command Completion IRQ, but that's causing too
2202 * much trouble synchronizing between us and gadget driver.
2203 *
2204 * We have discussed this with the IP Provider and it was
2205 * suggested to giveback all requests here, but give HW some
2206 * extra time to synchronize with the interconnect. We're using
2207 * an arbitrary 100us delay for that.
2208 *
2209 * Note also that a similar handling was tested by Synopsys
2210 * (thanks a lot Paul) and nothing bad has come out of it.
2211 * In short, what we're doing is:
2212 *
2213 * - Issue EndTransfer WITH CMDIOC bit set
2214 * - Wait 100us
2215 */
2216
2217 cmd = DWC3_DEPCMD_ENDTRANSFER;
2218 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2219 cmd |= DWC3_DEPCMD_CMDIOC;
2220 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2221 memset(¶ms, 0, sizeof(params));
2222 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2223 WARN_ON_ONCE(ret);
2224 dep->resource_index = 0;
2225 dep->flags &= ~DWC3_EP_BUSY;
2226 udelay(100);
2227}
2228
2229static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2230{
2231 u32 epnum;
2232
2233 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2234 struct dwc3_ep *dep;
2235
2236 dep = dwc->eps[epnum];
2237 if (!dep)
2238 continue;
2239
2240 if (!(dep->flags & DWC3_EP_ENABLED))
2241 continue;
2242
2243 dwc3_remove_requests(dwc, dep);
2244 }
2245}
2246
2247static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2248{
2249 u32 epnum;
2250
2251 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2252 struct dwc3_ep *dep;
2253 struct dwc3_gadget_ep_cmd_params params;
2254 int ret;
2255
2256 dep = dwc->eps[epnum];
2257 if (!dep)
2258 continue;
2259
2260 if (!(dep->flags & DWC3_EP_STALL))
2261 continue;
2262
2263 dep->flags &= ~DWC3_EP_STALL;
2264
2265 memset(¶ms, 0, sizeof(params));
2266 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2267 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2268 WARN_ON_ONCE(ret);
2269 }
2270}
2271
2272static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2273{
2274 int reg;
2275
2276 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2277 reg &= ~DWC3_DCTL_INITU1ENA;
2278 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2279
2280 reg &= ~DWC3_DCTL_INITU2ENA;
2281 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2282
2283 dwc3_disconnect_gadget(dwc);
2284
2285 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2286 dwc->setup_packet_pending = false;
2287 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2288}
2289
2290static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2291{
2292 u32 reg;
2293
2294 /*
2295 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2296 * would cause a missing Disconnect Event if there's a
2297 * pending Setup Packet in the FIFO.
2298 *
2299 * There's no suggested workaround on the official Bug
2300 * report, which states that "unless the driver/application
2301 * is doing any special handling of a disconnect event,
2302 * there is no functional issue".
2303 *
2304 * Unfortunately, it turns out that we _do_ some special
2305 * handling of a disconnect event, namely complete all
2306 * pending transfers, notify gadget driver of the
2307 * disconnection, and so on.
2308 *
2309 * Our suggested workaround is to follow the Disconnect
2310 * Event steps here, instead, based on a setup_packet_pending
2311 * flag. Such flag gets set whenever we have a SETUP_PENDING
2312 * status for EP0 TRBs and gets cleared on XferComplete for the
2313 * same endpoint.
2314 *
2315 * Refers to:
2316 *
2317 * STAR#9000466709: RTL: Device : Disconnect event not
2318 * generated if setup packet pending in FIFO
2319 */
2320 if (dwc->revision < DWC3_REVISION_188A) {
2321 if (dwc->setup_packet_pending)
2322 dwc3_gadget_disconnect_interrupt(dwc);
2323 }
2324
2325 dwc3_reset_gadget(dwc);
2326
2327 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2328 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2329 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2330 dwc->test_mode = false;
2331
2332 dwc3_stop_active_transfers(dwc);
2333 dwc3_clear_stall_all_ep(dwc);
2334
2335 /* Reset device address to zero */
2336 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2337 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2338 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2339}
2340
2341static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2342{
2343 u32 reg;
2344 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2345
2346 /*
2347 * We change the clock only at SS but I dunno why I would want to do
2348 * this. Maybe it becomes part of the power saving plan.
2349 */
2350
2351 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2352 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2353 return;
2354
2355 /*
2356 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2357 * each time on Connect Done.
2358 */
2359 if (!usb30_clock)
2360 return;
2361
2362 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2363 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2364 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2365}
2366
2367static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2368{
2369 struct dwc3_ep *dep;
2370 int ret;
2371 u32 reg;
2372 u8 speed;
2373
2374 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2375 speed = reg & DWC3_DSTS_CONNECTSPD;
2376 dwc->speed = speed;
2377
2378 dwc3_update_ram_clk_sel(dwc, speed);
2379
2380 switch (speed) {
2381 case DWC3_DCFG_SUPERSPEED_PLUS:
2382 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2383 dwc->gadget.ep0->maxpacket = 512;
2384 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2385 break;
2386 case DWC3_DCFG_SUPERSPEED:
2387 /*
2388 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2389 * would cause a missing USB3 Reset event.
2390 *
2391 * In such situations, we should force a USB3 Reset
2392 * event by calling our dwc3_gadget_reset_interrupt()
2393 * routine.
2394 *
2395 * Refers to:
2396 *
2397 * STAR#9000483510: RTL: SS : USB3 reset event may
2398 * not be generated always when the link enters poll
2399 */
2400 if (dwc->revision < DWC3_REVISION_190A)
2401 dwc3_gadget_reset_interrupt(dwc);
2402
2403 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2404 dwc->gadget.ep0->maxpacket = 512;
2405 dwc->gadget.speed = USB_SPEED_SUPER;
2406 break;
2407 case DWC3_DCFG_HIGHSPEED:
2408 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2409 dwc->gadget.ep0->maxpacket = 64;
2410 dwc->gadget.speed = USB_SPEED_HIGH;
2411 break;
2412 case DWC3_DCFG_FULLSPEED2:
2413 case DWC3_DCFG_FULLSPEED1:
2414 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2415 dwc->gadget.ep0->maxpacket = 64;
2416 dwc->gadget.speed = USB_SPEED_FULL;
2417 break;
2418 case DWC3_DCFG_LOWSPEED:
2419 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2420 dwc->gadget.ep0->maxpacket = 8;
2421 dwc->gadget.speed = USB_SPEED_LOW;
2422 break;
2423 }
2424
2425 /* Enable USB2 LPM Capability */
2426
2427 if ((dwc->revision > DWC3_REVISION_194A) &&
2428 (speed != DWC3_DCFG_SUPERSPEED) &&
2429 (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2430 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2431 reg |= DWC3_DCFG_LPM_CAP;
2432 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2433
2434 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2435 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2436
2437 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2438
2439 /*
2440 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2441 * DCFG.LPMCap is set, core responses with an ACK and the
2442 * BESL value in the LPM token is less than or equal to LPM
2443 * NYET threshold.
2444 */
2445 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2446 && dwc->has_lpm_erratum,
2447 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2448
2449 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2450 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2451
2452 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2453 } else {
2454 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2455 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2456 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2457 }
2458
2459 dep = dwc->eps[0];
2460 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2461 false);
2462 if (ret) {
2463 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2464 return;
2465 }
2466
2467 dep = dwc->eps[1];
2468 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2469 false);
2470 if (ret) {
2471 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2472 return;
2473 }
2474
2475 /*
2476 * Configure PHY via GUSB3PIPECTLn if required.
2477 *
2478 * Update GTXFIFOSIZn
2479 *
2480 * In both cases reset values should be sufficient.
2481 */
2482}
2483
2484static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2485{
2486 /*
2487 * TODO take core out of low power mode when that's
2488 * implemented.
2489 */
2490
2491 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2492 spin_unlock(&dwc->lock);
2493 dwc->gadget_driver->resume(&dwc->gadget);
2494 spin_lock(&dwc->lock);
2495 }
2496}
2497
2498static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2499 unsigned int evtinfo)
2500{
2501 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2502 unsigned int pwropt;
2503
2504 /*
2505 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2506 * Hibernation mode enabled which would show up when device detects
2507 * host-initiated U3 exit.
2508 *
2509 * In that case, device will generate a Link State Change Interrupt
2510 * from U3 to RESUME which is only necessary if Hibernation is
2511 * configured in.
2512 *
2513 * There are no functional changes due to such spurious event and we
2514 * just need to ignore it.
2515 *
2516 * Refers to:
2517 *
2518 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2519 * operational mode
2520 */
2521 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2522 if ((dwc->revision < DWC3_REVISION_250A) &&
2523 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2524 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2525 (next == DWC3_LINK_STATE_RESUME)) {
2526 dwc3_trace(trace_dwc3_gadget,
2527 "ignoring transition U3 -> Resume");
2528 return;
2529 }
2530 }
2531
2532 /*
2533 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2534 * on the link partner, the USB session might do multiple entry/exit
2535 * of low power states before a transfer takes place.
2536 *
2537 * Due to this problem, we might experience lower throughput. The
2538 * suggested workaround is to disable DCTL[12:9] bits if we're
2539 * transitioning from U1/U2 to U0 and enable those bits again
2540 * after a transfer completes and there are no pending transfers
2541 * on any of the enabled endpoints.
2542 *
2543 * This is the first half of that workaround.
2544 *
2545 * Refers to:
2546 *
2547 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2548 * core send LGO_Ux entering U0
2549 */
2550 if (dwc->revision < DWC3_REVISION_183A) {
2551 if (next == DWC3_LINK_STATE_U0) {
2552 u32 u1u2;
2553 u32 reg;
2554
2555 switch (dwc->link_state) {
2556 case DWC3_LINK_STATE_U1:
2557 case DWC3_LINK_STATE_U2:
2558 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2559 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2560 | DWC3_DCTL_ACCEPTU2ENA
2561 | DWC3_DCTL_INITU1ENA
2562 | DWC3_DCTL_ACCEPTU1ENA);
2563
2564 if (!dwc->u1u2)
2565 dwc->u1u2 = reg & u1u2;
2566
2567 reg &= ~u1u2;
2568
2569 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2570 break;
2571 default:
2572 /* do nothing */
2573 break;
2574 }
2575 }
2576 }
2577
2578 switch (next) {
2579 case DWC3_LINK_STATE_U1:
2580 if (dwc->speed == USB_SPEED_SUPER)
2581 dwc3_suspend_gadget(dwc);
2582 break;
2583 case DWC3_LINK_STATE_U2:
2584 case DWC3_LINK_STATE_U3:
2585 dwc3_suspend_gadget(dwc);
2586 break;
2587 case DWC3_LINK_STATE_RESUME:
2588 dwc3_resume_gadget(dwc);
2589 break;
2590 default:
2591 /* do nothing */
2592 break;
2593 }
2594
2595 dwc->link_state = next;
2596}
2597
2598static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2599 unsigned int evtinfo)
2600{
2601 unsigned int is_ss = evtinfo & BIT(4);
2602
2603 /**
2604 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2605 * have a known issue which can cause USB CV TD.9.23 to fail
2606 * randomly.
2607 *
2608 * Because of this issue, core could generate bogus hibernation
2609 * events which SW needs to ignore.
2610 *
2611 * Refers to:
2612 *
2613 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2614 * Device Fallback from SuperSpeed
2615 */
2616 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2617 return;
2618
2619 /* enter hibernation here */
2620}
2621
2622static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2623 const struct dwc3_event_devt *event)
2624{
2625 switch (event->type) {
2626 case DWC3_DEVICE_EVENT_DISCONNECT:
2627 dwc3_gadget_disconnect_interrupt(dwc);
2628 break;
2629 case DWC3_DEVICE_EVENT_RESET:
2630 dwc3_gadget_reset_interrupt(dwc);
2631 break;
2632 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2633 dwc3_gadget_conndone_interrupt(dwc);
2634 break;
2635 case DWC3_DEVICE_EVENT_WAKEUP:
2636 dwc3_gadget_wakeup_interrupt(dwc);
2637 break;
2638 case DWC3_DEVICE_EVENT_HIBER_REQ:
2639 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2640 "unexpected hibernation event\n"))
2641 break;
2642
2643 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2644 break;
2645 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2646 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2647 break;
2648 case DWC3_DEVICE_EVENT_EOPF:
2649 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2650 break;
2651 case DWC3_DEVICE_EVENT_SOF:
2652 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2653 break;
2654 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2655 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2656 break;
2657 case DWC3_DEVICE_EVENT_CMD_CMPL:
2658 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2659 break;
2660 case DWC3_DEVICE_EVENT_OVERFLOW:
2661 dwc3_trace(trace_dwc3_gadget, "Overflow");
2662 break;
2663 default:
2664 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2665 }
2666}
2667
2668static void dwc3_process_event_entry(struct dwc3 *dwc,
2669 const union dwc3_event *event)
2670{
2671 trace_dwc3_event(event->raw);
2672
2673 /* Endpoint IRQ, handle it and return early */
2674 if (event->type.is_devspec == 0) {
2675 /* depevt */
2676 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2677 }
2678
2679 switch (event->type.type) {
2680 case DWC3_EVENT_TYPE_DEV:
2681 dwc3_gadget_interrupt(dwc, &event->devt);
2682 break;
2683 /* REVISIT what to do with Carkit and I2C events ? */
2684 default:
2685 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2686 }
2687}
2688
2689static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2690{
2691 struct dwc3_event_buffer *evt;
2692 irqreturn_t ret = IRQ_NONE;
2693 int left;
2694 u32 reg;
2695
2696 evt = dwc->ev_buffs[buf];
2697 left = evt->count;
2698
2699 if (!(evt->flags & DWC3_EVENT_PENDING))
2700 return IRQ_NONE;
2701
2702 while (left > 0) {
2703 union dwc3_event event;
2704
2705 event.raw = *(u32 *) (evt->buf + evt->lpos);
2706
2707 dwc3_process_event_entry(dwc, &event);
2708
2709 /*
2710 * FIXME we wrap around correctly to the next entry as
2711 * almost all entries are 4 bytes in size. There is one
2712 * entry which has 12 bytes which is a regular entry
2713 * followed by 8 bytes data. ATM I don't know how
2714 * things are organized if we get next to the a
2715 * boundary so I worry about that once we try to handle
2716 * that.
2717 */
2718 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2719 left -= 4;
2720
2721 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2722 }
2723
2724 evt->count = 0;
2725 evt->flags &= ~DWC3_EVENT_PENDING;
2726 ret = IRQ_HANDLED;
2727
2728 /* Unmask interrupt */
2729 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2730 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2731 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2732
2733 return ret;
2734}
2735
2736static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2737{
2738 struct dwc3 *dwc = _dwc;
2739 unsigned long flags;
2740 irqreturn_t ret = IRQ_NONE;
2741 int i;
2742
2743 spin_lock_irqsave(&dwc->lock, flags);
2744
2745 for (i = 0; i < dwc->num_event_buffers; i++)
2746 ret |= dwc3_process_event_buf(dwc, i);
2747
2748 spin_unlock_irqrestore(&dwc->lock, flags);
2749
2750 return ret;
2751}
2752
2753static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2754{
2755 struct dwc3_event_buffer *evt;
2756 u32 count;
2757 u32 reg;
2758
2759 evt = dwc->ev_buffs[buf];
2760
2761 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2762 count &= DWC3_GEVNTCOUNT_MASK;
2763 if (!count)
2764 return IRQ_NONE;
2765
2766 evt->count = count;
2767 evt->flags |= DWC3_EVENT_PENDING;
2768
2769 /* Mask interrupt */
2770 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2771 reg |= DWC3_GEVNTSIZ_INTMASK;
2772 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2773
2774 return IRQ_WAKE_THREAD;
2775}
2776
2777static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2778{
2779 struct dwc3 *dwc = _dwc;
2780 int i;
2781 irqreturn_t ret = IRQ_NONE;
2782
2783 for (i = 0; i < dwc->num_event_buffers; i++) {
2784 irqreturn_t status;
2785
2786 status = dwc3_check_event_buf(dwc, i);
2787 if (status == IRQ_WAKE_THREAD)
2788 ret = status;
2789 }
2790
2791 return ret;
2792}
2793
2794/**
2795 * dwc3_gadget_init - Initializes gadget related registers
2796 * @dwc: pointer to our controller context structure
2797 *
2798 * Returns 0 on success otherwise negative errno.
2799 */
2800int dwc3_gadget_init(struct dwc3 *dwc)
2801{
2802 int ret;
2803
2804 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2805 &dwc->ctrl_req_addr, GFP_KERNEL);
2806 if (!dwc->ctrl_req) {
2807 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2808 ret = -ENOMEM;
2809 goto err0;
2810 }
2811
2812 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2813 &dwc->ep0_trb_addr, GFP_KERNEL);
2814 if (!dwc->ep0_trb) {
2815 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2816 ret = -ENOMEM;
2817 goto err1;
2818 }
2819
2820 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2821 if (!dwc->setup_buf) {
2822 ret = -ENOMEM;
2823 goto err2;
2824 }
2825
2826 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2827 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2828 GFP_KERNEL);
2829 if (!dwc->ep0_bounce) {
2830 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2831 ret = -ENOMEM;
2832 goto err3;
2833 }
2834
2835 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2836 if (!dwc->zlp_buf) {
2837 ret = -ENOMEM;
2838 goto err4;
2839 }
2840
2841 dwc->gadget.ops = &dwc3_gadget_ops;
2842 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2843 dwc->gadget.sg_supported = true;
2844 dwc->gadget.name = "dwc3-gadget";
2845 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
2846
2847 /*
2848 * FIXME We might be setting max_speed to <SUPER, however versions
2849 * <2.20a of dwc3 have an issue with metastability (documented
2850 * elsewhere in this driver) which tells us we can't set max speed to
2851 * anything lower than SUPER.
2852 *
2853 * Because gadget.max_speed is only used by composite.c and function
2854 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2855 * to happen so we avoid sending SuperSpeed Capability descriptor
2856 * together with our BOS descriptor as that could confuse host into
2857 * thinking we can handle super speed.
2858 *
2859 * Note that, in fact, we won't even support GetBOS requests when speed
2860 * is less than super speed because we don't have means, yet, to tell
2861 * composite.c that we are USB 2.0 + LPM ECN.
2862 */
2863 if (dwc->revision < DWC3_REVISION_220A)
2864 dwc3_trace(trace_dwc3_gadget,
2865 "Changing max_speed on rev %08x\n",
2866 dwc->revision);
2867
2868 dwc->gadget.max_speed = dwc->maximum_speed;
2869
2870 /*
2871 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2872 * on ep out.
2873 */
2874 dwc->gadget.quirk_ep_out_aligned_size = true;
2875
2876 /*
2877 * REVISIT: Here we should clear all pending IRQs to be
2878 * sure we're starting from a well known location.
2879 */
2880
2881 ret = dwc3_gadget_init_endpoints(dwc);
2882 if (ret)
2883 goto err5;
2884
2885 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2886 if (ret) {
2887 dev_err(dwc->dev, "failed to register udc\n");
2888 goto err5;
2889 }
2890
2891 return 0;
2892
2893err5:
2894 kfree(dwc->zlp_buf);
2895
2896err4:
2897 dwc3_gadget_free_endpoints(dwc);
2898 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2899 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2900
2901err3:
2902 kfree(dwc->setup_buf);
2903
2904err2:
2905 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2906 dwc->ep0_trb, dwc->ep0_trb_addr);
2907
2908err1:
2909 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2910 dwc->ctrl_req, dwc->ctrl_req_addr);
2911
2912err0:
2913 return ret;
2914}
2915
2916/* -------------------------------------------------------------------------- */
2917
2918void dwc3_gadget_exit(struct dwc3 *dwc)
2919{
2920 usb_del_gadget_udc(&dwc->gadget);
2921
2922 dwc3_gadget_free_endpoints(dwc);
2923
2924 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2925 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2926
2927 kfree(dwc->setup_buf);
2928 kfree(dwc->zlp_buf);
2929
2930 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2931 dwc->ep0_trb, dwc->ep0_trb_addr);
2932
2933 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2934 dwc->ctrl_req, dwc->ctrl_req_addr);
2935}
2936
2937int dwc3_gadget_suspend(struct dwc3 *dwc)
2938{
2939 if (!dwc->gadget_driver)
2940 return 0;
2941
2942 if (dwc->pullups_connected) {
2943 dwc3_gadget_disable_irq(dwc);
2944 dwc3_gadget_run_stop(dwc, true, true);
2945 }
2946
2947 __dwc3_gadget_ep_disable(dwc->eps[0]);
2948 __dwc3_gadget_ep_disable(dwc->eps[1]);
2949
2950 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2951
2952 return 0;
2953}
2954
2955int dwc3_gadget_resume(struct dwc3 *dwc)
2956{
2957 struct dwc3_ep *dep;
2958 int ret;
2959
2960 if (!dwc->gadget_driver)
2961 return 0;
2962
2963 /* Start with SuperSpeed Default */
2964 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2965
2966 dep = dwc->eps[0];
2967 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2968 false);
2969 if (ret)
2970 goto err0;
2971
2972 dep = dwc->eps[1];
2973 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2974 false);
2975 if (ret)
2976 goto err1;
2977
2978 /* begin to receive SETUP packets */
2979 dwc->ep0state = EP0_SETUP_PHASE;
2980 dwc3_ep0_out_start(dwc);
2981
2982 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2983
2984 if (dwc->pullups_connected) {
2985 dwc3_gadget_enable_irq(dwc);
2986 dwc3_gadget_run_stop(dwc, true, false);
2987 }
2988
2989 return 0;
2990
2991err1:
2992 __dwc3_gadget_ep_disable(dwc->eps[0]);
2993
2994err0:
2995 return ret;
2996}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30/**
31 * dwc3_gadget_set_test_mode - enables usb2 test modes
32 * @dwc: pointer to our context structure
33 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
34 *
35 * Caller should take care of locking. This function will return 0 on
36 * success or -EINVAL if wrong Test Selector is passed.
37 */
38int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
39{
40 u32 reg;
41
42 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
43 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
44
45 switch (mode) {
46 case TEST_J:
47 case TEST_K:
48 case TEST_SE0_NAK:
49 case TEST_PACKET:
50 case TEST_FORCE_EN:
51 reg |= mode << 1;
52 break;
53 default:
54 return -EINVAL;
55 }
56
57 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
58
59 return 0;
60}
61
62/**
63 * dwc3_gadget_get_link_state - gets current state of usb link
64 * @dwc: pointer to our context structure
65 *
66 * Caller should take care of locking. This function will
67 * return the link state on success (>= 0) or -ETIMEDOUT.
68 */
69int dwc3_gadget_get_link_state(struct dwc3 *dwc)
70{
71 u32 reg;
72
73 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
74
75 return DWC3_DSTS_USBLNKST(reg);
76}
77
78/**
79 * dwc3_gadget_set_link_state - sets usb link to a particular state
80 * @dwc: pointer to our context structure
81 * @state: the state to put link into
82 *
83 * Caller should take care of locking. This function will
84 * return 0 on success or -ETIMEDOUT.
85 */
86int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
87{
88 int retries = 10000;
89 u32 reg;
90
91 /*
92 * Wait until device controller is ready. Only applies to 1.94a and
93 * later RTL.
94 */
95 if (dwc->revision >= DWC3_REVISION_194A) {
96 while (--retries) {
97 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
98 if (reg & DWC3_DSTS_DCNRD)
99 udelay(5);
100 else
101 break;
102 }
103
104 if (retries <= 0)
105 return -ETIMEDOUT;
106 }
107
108 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
109 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
110
111 /* set requested state */
112 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
113 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
114
115 /*
116 * The following code is racy when called from dwc3_gadget_wakeup,
117 * and is not needed, at least on newer versions
118 */
119 if (dwc->revision >= DWC3_REVISION_194A)
120 return 0;
121
122 /* wait for a change in DSTS */
123 retries = 10000;
124 while (--retries) {
125 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
126
127 if (DWC3_DSTS_USBLNKST(reg) == state)
128 return 0;
129
130 udelay(5);
131 }
132
133 return -ETIMEDOUT;
134}
135
136/**
137 * dwc3_ep_inc_trb - increment a trb index.
138 * @index: Pointer to the TRB index to increment.
139 *
140 * The index should never point to the link TRB. After incrementing,
141 * if it is point to the link TRB, wrap around to the beginning. The
142 * link TRB is always at the last TRB entry.
143 */
144static void dwc3_ep_inc_trb(u8 *index)
145{
146 (*index)++;
147 if (*index == (DWC3_TRB_NUM - 1))
148 *index = 0;
149}
150
151/**
152 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
153 * @dep: The endpoint whose enqueue pointer we're incrementing
154 */
155static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
156{
157 dwc3_ep_inc_trb(&dep->trb_enqueue);
158}
159
160/**
161 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
162 * @dep: The endpoint whose enqueue pointer we're incrementing
163 */
164static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
165{
166 dwc3_ep_inc_trb(&dep->trb_dequeue);
167}
168
169static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
170 struct dwc3_request *req, int status)
171{
172 struct dwc3 *dwc = dep->dwc;
173
174 req->started = false;
175 list_del(&req->list);
176 req->remaining = 0;
177
178 if (req->request.status == -EINPROGRESS)
179 req->request.status = status;
180
181 if (req->trb)
182 usb_gadget_unmap_request_by_dev(dwc->sysdev,
183 &req->request, req->direction);
184
185 req->trb = NULL;
186 trace_dwc3_gadget_giveback(req);
187
188 if (dep->number > 1)
189 pm_runtime_put(dwc->dev);
190}
191
192/**
193 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
194 * @dep: The endpoint to whom the request belongs to
195 * @req: The request we're giving back
196 * @status: completion code for the request
197 *
198 * Must be called with controller's lock held and interrupts disabled. This
199 * function will unmap @req and call its ->complete() callback to notify upper
200 * layers that it has completed.
201 */
202void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
203 int status)
204{
205 struct dwc3 *dwc = dep->dwc;
206
207 dwc3_gadget_del_and_unmap_request(dep, req, status);
208
209 spin_unlock(&dwc->lock);
210 usb_gadget_giveback_request(&dep->endpoint, &req->request);
211 spin_lock(&dwc->lock);
212}
213
214/**
215 * dwc3_send_gadget_generic_command - issue a generic command for the controller
216 * @dwc: pointer to the controller context
217 * @cmd: the command to be issued
218 * @param: command parameter
219 *
220 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
221 * and wait for its completion.
222 */
223int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
224{
225 u32 timeout = 500;
226 int status = 0;
227 int ret = 0;
228 u32 reg;
229
230 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
231 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
232
233 do {
234 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
235 if (!(reg & DWC3_DGCMD_CMDACT)) {
236 status = DWC3_DGCMD_STATUS(reg);
237 if (status)
238 ret = -EINVAL;
239 break;
240 }
241 } while (--timeout);
242
243 if (!timeout) {
244 ret = -ETIMEDOUT;
245 status = -ETIMEDOUT;
246 }
247
248 trace_dwc3_gadget_generic_cmd(cmd, param, status);
249
250 return ret;
251}
252
253static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
254
255/**
256 * dwc3_send_gadget_ep_cmd - issue an endpoint command
257 * @dep: the endpoint to which the command is going to be issued
258 * @cmd: the command to be issued
259 * @params: parameters to the command
260 *
261 * Caller should handle locking. This function will issue @cmd with given
262 * @params to @dep and wait for its completion.
263 */
264int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
265 struct dwc3_gadget_ep_cmd_params *params)
266{
267 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
268 struct dwc3 *dwc = dep->dwc;
269 u32 timeout = 1000;
270 u32 reg;
271
272 int cmd_status = 0;
273 int susphy = false;
274 int ret = -EINVAL;
275
276 /*
277 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
278 * we're issuing an endpoint command, we must check if
279 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
280 *
281 * We will also set SUSPHY bit to what it was before returning as stated
282 * by the same section on Synopsys databook.
283 */
284 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
285 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
286 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
287 susphy = true;
288 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
289 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
290 }
291 }
292
293 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
294 int needs_wakeup;
295
296 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
297 dwc->link_state == DWC3_LINK_STATE_U2 ||
298 dwc->link_state == DWC3_LINK_STATE_U3);
299
300 if (unlikely(needs_wakeup)) {
301 ret = __dwc3_gadget_wakeup(dwc);
302 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
303 ret);
304 }
305 }
306
307 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
308 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
309 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
310
311 /*
312 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
313 * not relying on XferNotReady, we can make use of a special "No
314 * Response Update Transfer" command where we should clear both CmdAct
315 * and CmdIOC bits.
316 *
317 * With this, we don't need to wait for command completion and can
318 * straight away issue further commands to the endpoint.
319 *
320 * NOTICE: We're making an assumption that control endpoints will never
321 * make use of Update Transfer command. This is a safe assumption
322 * because we can never have more than one request at a time with
323 * Control Endpoints. If anybody changes that assumption, this chunk
324 * needs to be updated accordingly.
325 */
326 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
327 !usb_endpoint_xfer_isoc(desc))
328 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
329 else
330 cmd |= DWC3_DEPCMD_CMDACT;
331
332 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
333 do {
334 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
335 if (!(reg & DWC3_DEPCMD_CMDACT)) {
336 cmd_status = DWC3_DEPCMD_STATUS(reg);
337
338 switch (cmd_status) {
339 case 0:
340 ret = 0;
341 break;
342 case DEPEVT_TRANSFER_NO_RESOURCE:
343 ret = -EINVAL;
344 break;
345 case DEPEVT_TRANSFER_BUS_EXPIRY:
346 /*
347 * SW issues START TRANSFER command to
348 * isochronous ep with future frame interval. If
349 * future interval time has already passed when
350 * core receives the command, it will respond
351 * with an error status of 'Bus Expiry'.
352 *
353 * Instead of always returning -EINVAL, let's
354 * give a hint to the gadget driver that this is
355 * the case by returning -EAGAIN.
356 */
357 ret = -EAGAIN;
358 break;
359 default:
360 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
361 }
362
363 break;
364 }
365 } while (--timeout);
366
367 if (timeout == 0) {
368 ret = -ETIMEDOUT;
369 cmd_status = -ETIMEDOUT;
370 }
371
372 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
373
374 if (ret == 0) {
375 switch (DWC3_DEPCMD_CMD(cmd)) {
376 case DWC3_DEPCMD_STARTTRANSFER:
377 dep->flags |= DWC3_EP_TRANSFER_STARTED;
378 break;
379 case DWC3_DEPCMD_ENDTRANSFER:
380 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
381 break;
382 default:
383 /* nothing */
384 break;
385 }
386 }
387
388 if (unlikely(susphy)) {
389 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
390 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
391 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
392 }
393
394 return ret;
395}
396
397static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
398{
399 struct dwc3 *dwc = dep->dwc;
400 struct dwc3_gadget_ep_cmd_params params;
401 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
402
403 /*
404 * As of core revision 2.60a the recommended programming model
405 * is to set the ClearPendIN bit when issuing a Clear Stall EP
406 * command for IN endpoints. This is to prevent an issue where
407 * some (non-compliant) hosts may not send ACK TPs for pending
408 * IN transfers due to a mishandled error condition. Synopsys
409 * STAR 9000614252.
410 */
411 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
412 (dwc->gadget.speed >= USB_SPEED_SUPER))
413 cmd |= DWC3_DEPCMD_CLEARPENDIN;
414
415 memset(¶ms, 0, sizeof(params));
416
417 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
418}
419
420static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
421 struct dwc3_trb *trb)
422{
423 u32 offset = (char *) trb - (char *) dep->trb_pool;
424
425 return dep->trb_pool_dma + offset;
426}
427
428static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
429{
430 struct dwc3 *dwc = dep->dwc;
431
432 if (dep->trb_pool)
433 return 0;
434
435 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
436 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
437 &dep->trb_pool_dma, GFP_KERNEL);
438 if (!dep->trb_pool) {
439 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
440 dep->name);
441 return -ENOMEM;
442 }
443
444 return 0;
445}
446
447static void dwc3_free_trb_pool(struct dwc3_ep *dep)
448{
449 struct dwc3 *dwc = dep->dwc;
450
451 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
452 dep->trb_pool, dep->trb_pool_dma);
453
454 dep->trb_pool = NULL;
455 dep->trb_pool_dma = 0;
456}
457
458static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
459
460/**
461 * dwc3_gadget_start_config - configure ep resources
462 * @dwc: pointer to our controller context structure
463 * @dep: endpoint that is being enabled
464 *
465 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
466 * completion, it will set Transfer Resource for all available endpoints.
467 *
468 * The assignment of transfer resources cannot perfectly follow the data book
469 * due to the fact that the controller driver does not have all knowledge of the
470 * configuration in advance. It is given this information piecemeal by the
471 * composite gadget framework after every SET_CONFIGURATION and
472 * SET_INTERFACE. Trying to follow the databook programming model in this
473 * scenario can cause errors. For two reasons:
474 *
475 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
476 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
477 * incorrect in the scenario of multiple interfaces.
478 *
479 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
480 * endpoint on alt setting (8.1.6).
481 *
482 * The following simplified method is used instead:
483 *
484 * All hardware endpoints can be assigned a transfer resource and this setting
485 * will stay persistent until either a core reset or hibernation. So whenever we
486 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
487 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
488 * guaranteed that there are as many transfer resources as endpoints.
489 *
490 * This function is called for each endpoint when it is being enabled but is
491 * triggered only when called for EP0-out, which always happens first, and which
492 * should only happen in one of the above conditions.
493 */
494static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
495{
496 struct dwc3_gadget_ep_cmd_params params;
497 u32 cmd;
498 int i;
499 int ret;
500
501 if (dep->number)
502 return 0;
503
504 memset(¶ms, 0x00, sizeof(params));
505 cmd = DWC3_DEPCMD_DEPSTARTCFG;
506
507 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
508 if (ret)
509 return ret;
510
511 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
512 struct dwc3_ep *dep = dwc->eps[i];
513
514 if (!dep)
515 continue;
516
517 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
518 if (ret)
519 return ret;
520 }
521
522 return 0;
523}
524
525static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
526 bool modify, bool restore)
527{
528 const struct usb_ss_ep_comp_descriptor *comp_desc;
529 const struct usb_endpoint_descriptor *desc;
530 struct dwc3_gadget_ep_cmd_params params;
531
532 if (dev_WARN_ONCE(dwc->dev, modify && restore,
533 "Can't modify and restore\n"))
534 return -EINVAL;
535
536 comp_desc = dep->endpoint.comp_desc;
537 desc = dep->endpoint.desc;
538
539 memset(¶ms, 0x00, sizeof(params));
540
541 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
542 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
543
544 /* Burst size is only needed in SuperSpeed mode */
545 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
546 u32 burst = dep->endpoint.maxburst;
547 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
548 }
549
550 if (modify) {
551 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
552 } else if (restore) {
553 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
554 params.param2 |= dep->saved_state;
555 } else {
556 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
557 }
558
559 if (usb_endpoint_xfer_control(desc))
560 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
561
562 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
563 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
564
565 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
566 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
567 | DWC3_DEPCFG_STREAM_EVENT_EN;
568 dep->stream_capable = true;
569 }
570
571 if (!usb_endpoint_xfer_control(desc))
572 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
573
574 /*
575 * We are doing 1:1 mapping for endpoints, meaning
576 * Physical Endpoints 2 maps to Logical Endpoint 2 and
577 * so on. We consider the direction bit as part of the physical
578 * endpoint number. So USB endpoint 0x81 is 0x03.
579 */
580 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
581
582 /*
583 * We must use the lower 16 TX FIFOs even though
584 * HW might have more
585 */
586 if (dep->direction)
587 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
588
589 if (desc->bInterval) {
590 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
591 dep->interval = 1 << (desc->bInterval - 1);
592 }
593
594 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
595}
596
597static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
598{
599 struct dwc3_gadget_ep_cmd_params params;
600
601 memset(¶ms, 0x00, sizeof(params));
602
603 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
604
605 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
606 ¶ms);
607}
608
609/**
610 * __dwc3_gadget_ep_enable - initializes a hw endpoint
611 * @dep: endpoint to be initialized
612 * @modify: if true, modify existing endpoint configuration
613 * @restore: if true, restore endpoint configuration from scratch buffer
614 *
615 * Caller should take care of locking. Execute all necessary commands to
616 * initialize a HW endpoint so it can be used by a gadget driver.
617 */
618static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
619 bool modify, bool restore)
620{
621 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
622 struct dwc3 *dwc = dep->dwc;
623
624 u32 reg;
625 int ret;
626
627 if (!(dep->flags & DWC3_EP_ENABLED)) {
628 ret = dwc3_gadget_start_config(dwc, dep);
629 if (ret)
630 return ret;
631 }
632
633 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
634 if (ret)
635 return ret;
636
637 if (!(dep->flags & DWC3_EP_ENABLED)) {
638 struct dwc3_trb *trb_st_hw;
639 struct dwc3_trb *trb_link;
640
641 dep->type = usb_endpoint_type(desc);
642 dep->flags |= DWC3_EP_ENABLED;
643 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
644
645 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
646 reg |= DWC3_DALEPENA_EP(dep->number);
647 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
648
649 init_waitqueue_head(&dep->wait_end_transfer);
650
651 if (usb_endpoint_xfer_control(desc))
652 goto out;
653
654 /* Initialize the TRB ring */
655 dep->trb_dequeue = 0;
656 dep->trb_enqueue = 0;
657 memset(dep->trb_pool, 0,
658 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
659
660 /* Link TRB. The HWO bit is never reset */
661 trb_st_hw = &dep->trb_pool[0];
662
663 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
664 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
665 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
666 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
667 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
668 }
669
670 /*
671 * Issue StartTransfer here with no-op TRB so we can always rely on No
672 * Response Update Transfer command.
673 */
674 if (usb_endpoint_xfer_bulk(desc)) {
675 struct dwc3_gadget_ep_cmd_params params;
676 struct dwc3_trb *trb;
677 dma_addr_t trb_dma;
678 u32 cmd;
679
680 memset(¶ms, 0, sizeof(params));
681 trb = &dep->trb_pool[0];
682 trb_dma = dwc3_trb_dma_offset(dep, trb);
683
684 params.param0 = upper_32_bits(trb_dma);
685 params.param1 = lower_32_bits(trb_dma);
686
687 cmd = DWC3_DEPCMD_STARTTRANSFER;
688
689 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
690 if (ret < 0)
691 return ret;
692
693 dep->flags |= DWC3_EP_BUSY;
694
695 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
696 WARN_ON_ONCE(!dep->resource_index);
697 }
698
699
700out:
701 trace_dwc3_gadget_ep_enable(dep);
702
703 return 0;
704}
705
706static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
707static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
708{
709 struct dwc3_request *req;
710
711 dwc3_stop_active_transfer(dwc, dep->number, true);
712
713 /* - giveback all requests to gadget driver */
714 while (!list_empty(&dep->started_list)) {
715 req = next_request(&dep->started_list);
716
717 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
718 }
719
720 while (!list_empty(&dep->pending_list)) {
721 req = next_request(&dep->pending_list);
722
723 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
724 }
725}
726
727/**
728 * __dwc3_gadget_ep_disable - disables a hw endpoint
729 * @dep: the endpoint to disable
730 *
731 * This function undoes what __dwc3_gadget_ep_enable did and also removes
732 * requests which are currently being processed by the hardware and those which
733 * are not yet scheduled.
734 *
735 * Caller should take care of locking.
736 */
737static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
738{
739 struct dwc3 *dwc = dep->dwc;
740 u32 reg;
741
742 trace_dwc3_gadget_ep_disable(dep);
743
744 dwc3_remove_requests(dwc, dep);
745
746 /* make sure HW endpoint isn't stalled */
747 if (dep->flags & DWC3_EP_STALL)
748 __dwc3_gadget_ep_set_halt(dep, 0, false);
749
750 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
751 reg &= ~DWC3_DALEPENA_EP(dep->number);
752 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
753
754 dep->stream_capable = false;
755 dep->type = 0;
756 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
757
758 /* Clear out the ep descriptors for non-ep0 */
759 if (dep->number > 1) {
760 dep->endpoint.comp_desc = NULL;
761 dep->endpoint.desc = NULL;
762 }
763
764 return 0;
765}
766
767/* -------------------------------------------------------------------------- */
768
769static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
770 const struct usb_endpoint_descriptor *desc)
771{
772 return -EINVAL;
773}
774
775static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
776{
777 return -EINVAL;
778}
779
780/* -------------------------------------------------------------------------- */
781
782static int dwc3_gadget_ep_enable(struct usb_ep *ep,
783 const struct usb_endpoint_descriptor *desc)
784{
785 struct dwc3_ep *dep;
786 struct dwc3 *dwc;
787 unsigned long flags;
788 int ret;
789
790 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
791 pr_debug("dwc3: invalid parameters\n");
792 return -EINVAL;
793 }
794
795 if (!desc->wMaxPacketSize) {
796 pr_debug("dwc3: missing wMaxPacketSize\n");
797 return -EINVAL;
798 }
799
800 dep = to_dwc3_ep(ep);
801 dwc = dep->dwc;
802
803 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
804 "%s is already enabled\n",
805 dep->name))
806 return 0;
807
808 spin_lock_irqsave(&dwc->lock, flags);
809 ret = __dwc3_gadget_ep_enable(dep, false, false);
810 spin_unlock_irqrestore(&dwc->lock, flags);
811
812 return ret;
813}
814
815static int dwc3_gadget_ep_disable(struct usb_ep *ep)
816{
817 struct dwc3_ep *dep;
818 struct dwc3 *dwc;
819 unsigned long flags;
820 int ret;
821
822 if (!ep) {
823 pr_debug("dwc3: invalid parameters\n");
824 return -EINVAL;
825 }
826
827 dep = to_dwc3_ep(ep);
828 dwc = dep->dwc;
829
830 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
831 "%s is already disabled\n",
832 dep->name))
833 return 0;
834
835 spin_lock_irqsave(&dwc->lock, flags);
836 ret = __dwc3_gadget_ep_disable(dep);
837 spin_unlock_irqrestore(&dwc->lock, flags);
838
839 return ret;
840}
841
842static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
843 gfp_t gfp_flags)
844{
845 struct dwc3_request *req;
846 struct dwc3_ep *dep = to_dwc3_ep(ep);
847
848 req = kzalloc(sizeof(*req), gfp_flags);
849 if (!req)
850 return NULL;
851
852 req->epnum = dep->number;
853 req->dep = dep;
854
855 dep->allocated_requests++;
856
857 trace_dwc3_alloc_request(req);
858
859 return &req->request;
860}
861
862static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
863 struct usb_request *request)
864{
865 struct dwc3_request *req = to_dwc3_request(request);
866 struct dwc3_ep *dep = to_dwc3_ep(ep);
867
868 dep->allocated_requests--;
869 trace_dwc3_free_request(req);
870 kfree(req);
871}
872
873static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
874
875static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
876 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
877 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
878{
879 struct dwc3 *dwc = dep->dwc;
880 struct usb_gadget *gadget = &dwc->gadget;
881 enum usb_device_speed speed = gadget->speed;
882
883 dwc3_ep_inc_enq(dep);
884
885 trb->size = DWC3_TRB_SIZE_LENGTH(length);
886 trb->bpl = lower_32_bits(dma);
887 trb->bph = upper_32_bits(dma);
888
889 switch (usb_endpoint_type(dep->endpoint.desc)) {
890 case USB_ENDPOINT_XFER_CONTROL:
891 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
892 break;
893
894 case USB_ENDPOINT_XFER_ISOC:
895 if (!node) {
896 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
897
898 /*
899 * USB Specification 2.0 Section 5.9.2 states that: "If
900 * there is only a single transaction in the microframe,
901 * only a DATA0 data packet PID is used. If there are
902 * two transactions per microframe, DATA1 is used for
903 * the first transaction data packet and DATA0 is used
904 * for the second transaction data packet. If there are
905 * three transactions per microframe, DATA2 is used for
906 * the first transaction data packet, DATA1 is used for
907 * the second, and DATA0 is used for the third."
908 *
909 * IOW, we should satisfy the following cases:
910 *
911 * 1) length <= maxpacket
912 * - DATA0
913 *
914 * 2) maxpacket < length <= (2 * maxpacket)
915 * - DATA1, DATA0
916 *
917 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
918 * - DATA2, DATA1, DATA0
919 */
920 if (speed == USB_SPEED_HIGH) {
921 struct usb_ep *ep = &dep->endpoint;
922 unsigned int mult = 2;
923 unsigned int maxp = usb_endpoint_maxp(ep->desc);
924
925 if (length <= (2 * maxp))
926 mult--;
927
928 if (length <= maxp)
929 mult--;
930
931 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
932 }
933 } else {
934 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
935 }
936
937 /* always enable Interrupt on Missed ISOC */
938 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
939 break;
940
941 case USB_ENDPOINT_XFER_BULK:
942 case USB_ENDPOINT_XFER_INT:
943 trb->ctrl = DWC3_TRBCTL_NORMAL;
944 break;
945 default:
946 /*
947 * This is only possible with faulty memory because we
948 * checked it already :)
949 */
950 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
951 usb_endpoint_type(dep->endpoint.desc));
952 }
953
954 /* always enable Continue on Short Packet */
955 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
956 trb->ctrl |= DWC3_TRB_CTRL_CSP;
957
958 if (short_not_ok)
959 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
960 }
961
962 if ((!no_interrupt && !chain) ||
963 (dwc3_calc_trbs_left(dep) == 0))
964 trb->ctrl |= DWC3_TRB_CTRL_IOC;
965
966 if (chain)
967 trb->ctrl |= DWC3_TRB_CTRL_CHN;
968
969 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
970 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
971
972 trb->ctrl |= DWC3_TRB_CTRL_HWO;
973
974 trace_dwc3_prepare_trb(dep, trb);
975}
976
977/**
978 * dwc3_prepare_one_trb - setup one TRB from one request
979 * @dep: endpoint for which this request is prepared
980 * @req: dwc3_request pointer
981 * @chain: should this TRB be chained to the next?
982 * @node: only for isochronous endpoints. First TRB needs different type.
983 */
984static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
985 struct dwc3_request *req, unsigned chain, unsigned node)
986{
987 struct dwc3_trb *trb;
988 unsigned length = req->request.length;
989 unsigned stream_id = req->request.stream_id;
990 unsigned short_not_ok = req->request.short_not_ok;
991 unsigned no_interrupt = req->request.no_interrupt;
992 dma_addr_t dma = req->request.dma;
993
994 trb = &dep->trb_pool[dep->trb_enqueue];
995
996 if (!req->trb) {
997 dwc3_gadget_move_started_request(req);
998 req->trb = trb;
999 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1000 dep->queued_requests++;
1001 }
1002
1003 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1004 stream_id, short_not_ok, no_interrupt);
1005}
1006
1007/**
1008 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1009 * @dep: The endpoint with the TRB ring
1010 * @index: The index of the current TRB in the ring
1011 *
1012 * Returns the TRB prior to the one pointed to by the index. If the
1013 * index is 0, we will wrap backwards, skip the link TRB, and return
1014 * the one just before that.
1015 */
1016static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1017{
1018 u8 tmp = index;
1019
1020 if (!tmp)
1021 tmp = DWC3_TRB_NUM - 1;
1022
1023 return &dep->trb_pool[tmp - 1];
1024}
1025
1026static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1027{
1028 struct dwc3_trb *tmp;
1029 u8 trbs_left;
1030
1031 /*
1032 * If enqueue & dequeue are equal than it is either full or empty.
1033 *
1034 * One way to know for sure is if the TRB right before us has HWO bit
1035 * set or not. If it has, then we're definitely full and can't fit any
1036 * more transfers in our ring.
1037 */
1038 if (dep->trb_enqueue == dep->trb_dequeue) {
1039 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1040 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
1041 return 0;
1042
1043 return DWC3_TRB_NUM - 1;
1044 }
1045
1046 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1047 trbs_left &= (DWC3_TRB_NUM - 1);
1048
1049 if (dep->trb_dequeue < dep->trb_enqueue)
1050 trbs_left--;
1051
1052 return trbs_left;
1053}
1054
1055static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1056 struct dwc3_request *req)
1057{
1058 struct scatterlist *sg = req->sg;
1059 struct scatterlist *s;
1060 int i;
1061
1062 for_each_sg(sg, s, req->num_pending_sgs, i) {
1063 unsigned int length = req->request.length;
1064 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1065 unsigned int rem = length % maxp;
1066 unsigned chain = true;
1067
1068 if (sg_is_last(s))
1069 chain = false;
1070
1071 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1072 struct dwc3 *dwc = dep->dwc;
1073 struct dwc3_trb *trb;
1074
1075 req->unaligned = true;
1076
1077 /* prepare normal TRB */
1078 dwc3_prepare_one_trb(dep, req, true, i);
1079
1080 /* Now prepare one extra TRB to align transfer size */
1081 trb = &dep->trb_pool[dep->trb_enqueue];
1082 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1083 maxp - rem, false, 0,
1084 req->request.stream_id,
1085 req->request.short_not_ok,
1086 req->request.no_interrupt);
1087 } else {
1088 dwc3_prepare_one_trb(dep, req, chain, i);
1089 }
1090
1091 if (!dwc3_calc_trbs_left(dep))
1092 break;
1093 }
1094}
1095
1096static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1097 struct dwc3_request *req)
1098{
1099 unsigned int length = req->request.length;
1100 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1101 unsigned int rem = length % maxp;
1102
1103 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1104 struct dwc3 *dwc = dep->dwc;
1105 struct dwc3_trb *trb;
1106
1107 req->unaligned = true;
1108
1109 /* prepare normal TRB */
1110 dwc3_prepare_one_trb(dep, req, true, 0);
1111
1112 /* Now prepare one extra TRB to align transfer size */
1113 trb = &dep->trb_pool[dep->trb_enqueue];
1114 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1115 false, 0, req->request.stream_id,
1116 req->request.short_not_ok,
1117 req->request.no_interrupt);
1118 } else if (req->request.zero && req->request.length &&
1119 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1120 struct dwc3 *dwc = dep->dwc;
1121 struct dwc3_trb *trb;
1122
1123 req->zero = true;
1124
1125 /* prepare normal TRB */
1126 dwc3_prepare_one_trb(dep, req, true, 0);
1127
1128 /* Now prepare one extra TRB to handle ZLP */
1129 trb = &dep->trb_pool[dep->trb_enqueue];
1130 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1131 false, 0, req->request.stream_id,
1132 req->request.short_not_ok,
1133 req->request.no_interrupt);
1134 } else {
1135 dwc3_prepare_one_trb(dep, req, false, 0);
1136 }
1137}
1138
1139/*
1140 * dwc3_prepare_trbs - setup TRBs from requests
1141 * @dep: endpoint for which requests are being prepared
1142 *
1143 * The function goes through the requests list and sets up TRBs for the
1144 * transfers. The function returns once there are no more TRBs available or
1145 * it runs out of requests.
1146 */
1147static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1148{
1149 struct dwc3_request *req, *n;
1150
1151 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1152
1153 /*
1154 * We can get in a situation where there's a request in the started list
1155 * but there weren't enough TRBs to fully kick it in the first time
1156 * around, so it has been waiting for more TRBs to be freed up.
1157 *
1158 * In that case, we should check if we have a request with pending_sgs
1159 * in the started list and prepare TRBs for that request first,
1160 * otherwise we will prepare TRBs completely out of order and that will
1161 * break things.
1162 */
1163 list_for_each_entry(req, &dep->started_list, list) {
1164 if (req->num_pending_sgs > 0)
1165 dwc3_prepare_one_trb_sg(dep, req);
1166
1167 if (!dwc3_calc_trbs_left(dep))
1168 return;
1169 }
1170
1171 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1172 struct dwc3 *dwc = dep->dwc;
1173 int ret;
1174
1175 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1176 dep->direction);
1177 if (ret)
1178 return;
1179
1180 req->sg = req->request.sg;
1181 req->num_pending_sgs = req->request.num_mapped_sgs;
1182
1183 if (req->num_pending_sgs > 0)
1184 dwc3_prepare_one_trb_sg(dep, req);
1185 else
1186 dwc3_prepare_one_trb_linear(dep, req);
1187
1188 if (!dwc3_calc_trbs_left(dep))
1189 return;
1190 }
1191}
1192
1193static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1194{
1195 struct dwc3_gadget_ep_cmd_params params;
1196 struct dwc3_request *req;
1197 int starting;
1198 int ret;
1199 u32 cmd;
1200
1201 if (!dwc3_calc_trbs_left(dep))
1202 return 0;
1203
1204 starting = !(dep->flags & DWC3_EP_BUSY);
1205
1206 dwc3_prepare_trbs(dep);
1207 req = next_request(&dep->started_list);
1208 if (!req) {
1209 dep->flags |= DWC3_EP_PENDING_REQUEST;
1210 return 0;
1211 }
1212
1213 memset(¶ms, 0, sizeof(params));
1214
1215 if (starting) {
1216 params.param0 = upper_32_bits(req->trb_dma);
1217 params.param1 = lower_32_bits(req->trb_dma);
1218 cmd = DWC3_DEPCMD_STARTTRANSFER;
1219
1220 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1221 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1222 } else {
1223 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1224 DWC3_DEPCMD_PARAM(dep->resource_index);
1225 }
1226
1227 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1228 if (ret < 0) {
1229 /*
1230 * FIXME we need to iterate over the list of requests
1231 * here and stop, unmap, free and del each of the linked
1232 * requests instead of what we do now.
1233 */
1234 if (req->trb)
1235 memset(req->trb, 0, sizeof(struct dwc3_trb));
1236 dep->queued_requests--;
1237 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1238 return ret;
1239 }
1240
1241 dep->flags |= DWC3_EP_BUSY;
1242
1243 if (starting) {
1244 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1245 WARN_ON_ONCE(!dep->resource_index);
1246 }
1247
1248 return 0;
1249}
1250
1251static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1252{
1253 u32 reg;
1254
1255 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1256 return DWC3_DSTS_SOFFN(reg);
1257}
1258
1259static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1260 struct dwc3_ep *dep, u32 cur_uf)
1261{
1262 if (list_empty(&dep->pending_list)) {
1263 dev_info(dwc->dev, "%s: ran out of requests\n",
1264 dep->name);
1265 dep->flags |= DWC3_EP_PENDING_REQUEST;
1266 return;
1267 }
1268
1269 /*
1270 * Schedule the first trb for one interval in the future or at
1271 * least 4 microframes.
1272 */
1273 dep->frame_number = cur_uf + max_t(u32, 4, dep->interval);
1274 __dwc3_gadget_kick_transfer(dep);
1275}
1276
1277static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1278 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1279{
1280 u32 cur_uf, mask;
1281
1282 mask = ~(dep->interval - 1);
1283 cur_uf = event->parameters & mask;
1284
1285 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1286}
1287
1288static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1289{
1290 struct dwc3 *dwc = dep->dwc;
1291
1292 if (!dep->endpoint.desc) {
1293 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1294 dep->name);
1295 return -ESHUTDOWN;
1296 }
1297
1298 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1299 &req->request, req->dep->name))
1300 return -EINVAL;
1301
1302 pm_runtime_get(dwc->dev);
1303
1304 req->request.actual = 0;
1305 req->request.status = -EINPROGRESS;
1306 req->direction = dep->direction;
1307 req->epnum = dep->number;
1308
1309 trace_dwc3_ep_queue(req);
1310
1311 list_add_tail(&req->list, &dep->pending_list);
1312
1313 /*
1314 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1315 * wait for a XferNotReady event so we will know what's the current
1316 * (micro-)frame number.
1317 *
1318 * Without this trick, we are very, very likely gonna get Bus Expiry
1319 * errors which will force us issue EndTransfer command.
1320 */
1321 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1322 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1323 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1324 dwc3_stop_active_transfer(dwc, dep->number, true);
1325 dep->flags = DWC3_EP_ENABLED;
1326 } else {
1327 u32 cur_uf;
1328
1329 cur_uf = __dwc3_gadget_get_frame(dwc);
1330 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1331 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1332 }
1333 return 0;
1334 }
1335
1336 if ((dep->flags & DWC3_EP_BUSY) &&
1337 !(dep->flags & DWC3_EP_MISSED_ISOC))
1338 goto out;
1339
1340 return 0;
1341 }
1342
1343out:
1344 return __dwc3_gadget_kick_transfer(dep);
1345}
1346
1347static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1348 gfp_t gfp_flags)
1349{
1350 struct dwc3_request *req = to_dwc3_request(request);
1351 struct dwc3_ep *dep = to_dwc3_ep(ep);
1352 struct dwc3 *dwc = dep->dwc;
1353
1354 unsigned long flags;
1355
1356 int ret;
1357
1358 spin_lock_irqsave(&dwc->lock, flags);
1359 ret = __dwc3_gadget_ep_queue(dep, req);
1360 spin_unlock_irqrestore(&dwc->lock, flags);
1361
1362 return ret;
1363}
1364
1365static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1366 struct usb_request *request)
1367{
1368 struct dwc3_request *req = to_dwc3_request(request);
1369 struct dwc3_request *r = NULL;
1370
1371 struct dwc3_ep *dep = to_dwc3_ep(ep);
1372 struct dwc3 *dwc = dep->dwc;
1373
1374 unsigned long flags;
1375 int ret = 0;
1376
1377 trace_dwc3_ep_dequeue(req);
1378
1379 spin_lock_irqsave(&dwc->lock, flags);
1380
1381 list_for_each_entry(r, &dep->pending_list, list) {
1382 if (r == req)
1383 break;
1384 }
1385
1386 if (r != req) {
1387 list_for_each_entry(r, &dep->started_list, list) {
1388 if (r == req)
1389 break;
1390 }
1391 if (r == req) {
1392 /* wait until it is processed */
1393 dwc3_stop_active_transfer(dwc, dep->number, true);
1394
1395 /*
1396 * If request was already started, this means we had to
1397 * stop the transfer. With that we also need to ignore
1398 * all TRBs used by the request, however TRBs can only
1399 * be modified after completion of END_TRANSFER
1400 * command. So what we do here is that we wait for
1401 * END_TRANSFER completion and only after that, we jump
1402 * over TRBs by clearing HWO and incrementing dequeue
1403 * pointer.
1404 *
1405 * Note that we have 2 possible types of transfers here:
1406 *
1407 * i) Linear buffer request
1408 * ii) SG-list based request
1409 *
1410 * SG-list based requests will have r->num_pending_sgs
1411 * set to a valid number (> 0). Linear requests,
1412 * normally use a single TRB.
1413 *
1414 * For each of these two cases, if r->unaligned flag is
1415 * set, one extra TRB has been used to align transfer
1416 * size to wMaxPacketSize.
1417 *
1418 * All of these cases need to be taken into
1419 * consideration so we don't mess up our TRB ring
1420 * pointers.
1421 */
1422 wait_event_lock_irq(dep->wait_end_transfer,
1423 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1424 dwc->lock);
1425
1426 if (!r->trb)
1427 goto out0;
1428
1429 if (r->num_pending_sgs) {
1430 struct dwc3_trb *trb;
1431 int i = 0;
1432
1433 for (i = 0; i < r->num_pending_sgs; i++) {
1434 trb = r->trb + i;
1435 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1436 dwc3_ep_inc_deq(dep);
1437 }
1438
1439 if (r->unaligned || r->zero) {
1440 trb = r->trb + r->num_pending_sgs + 1;
1441 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1442 dwc3_ep_inc_deq(dep);
1443 }
1444 } else {
1445 struct dwc3_trb *trb = r->trb;
1446
1447 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1448 dwc3_ep_inc_deq(dep);
1449
1450 if (r->unaligned || r->zero) {
1451 trb = r->trb + 1;
1452 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1453 dwc3_ep_inc_deq(dep);
1454 }
1455 }
1456 goto out1;
1457 }
1458 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1459 request, ep->name);
1460 ret = -EINVAL;
1461 goto out0;
1462 }
1463
1464out1:
1465 /* giveback the request */
1466 dep->queued_requests--;
1467 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1468
1469out0:
1470 spin_unlock_irqrestore(&dwc->lock, flags);
1471
1472 return ret;
1473}
1474
1475int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1476{
1477 struct dwc3_gadget_ep_cmd_params params;
1478 struct dwc3 *dwc = dep->dwc;
1479 int ret;
1480
1481 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1482 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1483 return -EINVAL;
1484 }
1485
1486 memset(¶ms, 0x00, sizeof(params));
1487
1488 if (value) {
1489 struct dwc3_trb *trb;
1490
1491 unsigned transfer_in_flight;
1492 unsigned started;
1493
1494 if (dep->flags & DWC3_EP_STALL)
1495 return 0;
1496
1497 if (dep->number > 1)
1498 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1499 else
1500 trb = &dwc->ep0_trb[dep->trb_enqueue];
1501
1502 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1503 started = !list_empty(&dep->started_list);
1504
1505 if (!protocol && ((dep->direction && transfer_in_flight) ||
1506 (!dep->direction && started))) {
1507 return -EAGAIN;
1508 }
1509
1510 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1511 ¶ms);
1512 if (ret)
1513 dev_err(dwc->dev, "failed to set STALL on %s\n",
1514 dep->name);
1515 else
1516 dep->flags |= DWC3_EP_STALL;
1517 } else {
1518 if (!(dep->flags & DWC3_EP_STALL))
1519 return 0;
1520
1521 ret = dwc3_send_clear_stall_ep_cmd(dep);
1522 if (ret)
1523 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1524 dep->name);
1525 else
1526 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1527 }
1528
1529 return ret;
1530}
1531
1532static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1533{
1534 struct dwc3_ep *dep = to_dwc3_ep(ep);
1535 struct dwc3 *dwc = dep->dwc;
1536
1537 unsigned long flags;
1538
1539 int ret;
1540
1541 spin_lock_irqsave(&dwc->lock, flags);
1542 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1543 spin_unlock_irqrestore(&dwc->lock, flags);
1544
1545 return ret;
1546}
1547
1548static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1549{
1550 struct dwc3_ep *dep = to_dwc3_ep(ep);
1551 struct dwc3 *dwc = dep->dwc;
1552 unsigned long flags;
1553 int ret;
1554
1555 spin_lock_irqsave(&dwc->lock, flags);
1556 dep->flags |= DWC3_EP_WEDGE;
1557
1558 if (dep->number == 0 || dep->number == 1)
1559 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1560 else
1561 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1562 spin_unlock_irqrestore(&dwc->lock, flags);
1563
1564 return ret;
1565}
1566
1567/* -------------------------------------------------------------------------- */
1568
1569static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1570 .bLength = USB_DT_ENDPOINT_SIZE,
1571 .bDescriptorType = USB_DT_ENDPOINT,
1572 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1573};
1574
1575static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1576 .enable = dwc3_gadget_ep0_enable,
1577 .disable = dwc3_gadget_ep0_disable,
1578 .alloc_request = dwc3_gadget_ep_alloc_request,
1579 .free_request = dwc3_gadget_ep_free_request,
1580 .queue = dwc3_gadget_ep0_queue,
1581 .dequeue = dwc3_gadget_ep_dequeue,
1582 .set_halt = dwc3_gadget_ep0_set_halt,
1583 .set_wedge = dwc3_gadget_ep_set_wedge,
1584};
1585
1586static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1587 .enable = dwc3_gadget_ep_enable,
1588 .disable = dwc3_gadget_ep_disable,
1589 .alloc_request = dwc3_gadget_ep_alloc_request,
1590 .free_request = dwc3_gadget_ep_free_request,
1591 .queue = dwc3_gadget_ep_queue,
1592 .dequeue = dwc3_gadget_ep_dequeue,
1593 .set_halt = dwc3_gadget_ep_set_halt,
1594 .set_wedge = dwc3_gadget_ep_set_wedge,
1595};
1596
1597/* -------------------------------------------------------------------------- */
1598
1599static int dwc3_gadget_get_frame(struct usb_gadget *g)
1600{
1601 struct dwc3 *dwc = gadget_to_dwc(g);
1602
1603 return __dwc3_gadget_get_frame(dwc);
1604}
1605
1606static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1607{
1608 int retries;
1609
1610 int ret;
1611 u32 reg;
1612
1613 u8 link_state;
1614 u8 speed;
1615
1616 /*
1617 * According to the Databook Remote wakeup request should
1618 * be issued only when the device is in early suspend state.
1619 *
1620 * We can check that via USB Link State bits in DSTS register.
1621 */
1622 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1623
1624 speed = reg & DWC3_DSTS_CONNECTSPD;
1625 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1626 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1627 return 0;
1628
1629 link_state = DWC3_DSTS_USBLNKST(reg);
1630
1631 switch (link_state) {
1632 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1633 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1634 break;
1635 default:
1636 return -EINVAL;
1637 }
1638
1639 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1640 if (ret < 0) {
1641 dev_err(dwc->dev, "failed to put link in Recovery\n");
1642 return ret;
1643 }
1644
1645 /* Recent versions do this automatically */
1646 if (dwc->revision < DWC3_REVISION_194A) {
1647 /* write zeroes to Link Change Request */
1648 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1649 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1650 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1651 }
1652
1653 /* poll until Link State changes to ON */
1654 retries = 20000;
1655
1656 while (retries--) {
1657 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1658
1659 /* in HS, means ON */
1660 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1661 break;
1662 }
1663
1664 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1665 dev_err(dwc->dev, "failed to send remote wakeup\n");
1666 return -EINVAL;
1667 }
1668
1669 return 0;
1670}
1671
1672static int dwc3_gadget_wakeup(struct usb_gadget *g)
1673{
1674 struct dwc3 *dwc = gadget_to_dwc(g);
1675 unsigned long flags;
1676 int ret;
1677
1678 spin_lock_irqsave(&dwc->lock, flags);
1679 ret = __dwc3_gadget_wakeup(dwc);
1680 spin_unlock_irqrestore(&dwc->lock, flags);
1681
1682 return ret;
1683}
1684
1685static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1686 int is_selfpowered)
1687{
1688 struct dwc3 *dwc = gadget_to_dwc(g);
1689 unsigned long flags;
1690
1691 spin_lock_irqsave(&dwc->lock, flags);
1692 g->is_selfpowered = !!is_selfpowered;
1693 spin_unlock_irqrestore(&dwc->lock, flags);
1694
1695 return 0;
1696}
1697
1698static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1699{
1700 u32 reg;
1701 u32 timeout = 500;
1702
1703 if (pm_runtime_suspended(dwc->dev))
1704 return 0;
1705
1706 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1707 if (is_on) {
1708 if (dwc->revision <= DWC3_REVISION_187A) {
1709 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1710 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1711 }
1712
1713 if (dwc->revision >= DWC3_REVISION_194A)
1714 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1715 reg |= DWC3_DCTL_RUN_STOP;
1716
1717 if (dwc->has_hibernation)
1718 reg |= DWC3_DCTL_KEEP_CONNECT;
1719
1720 dwc->pullups_connected = true;
1721 } else {
1722 reg &= ~DWC3_DCTL_RUN_STOP;
1723
1724 if (dwc->has_hibernation && !suspend)
1725 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1726
1727 dwc->pullups_connected = false;
1728 }
1729
1730 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1731
1732 do {
1733 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1734 reg &= DWC3_DSTS_DEVCTRLHLT;
1735 } while (--timeout && !(!is_on ^ !reg));
1736
1737 if (!timeout)
1738 return -ETIMEDOUT;
1739
1740 return 0;
1741}
1742
1743static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1744{
1745 struct dwc3 *dwc = gadget_to_dwc(g);
1746 unsigned long flags;
1747 int ret;
1748
1749 is_on = !!is_on;
1750
1751 /*
1752 * Per databook, when we want to stop the gadget, if a control transfer
1753 * is still in process, complete it and get the core into setup phase.
1754 */
1755 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1756 reinit_completion(&dwc->ep0_in_setup);
1757
1758 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1759 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1760 if (ret == 0) {
1761 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1762 return -ETIMEDOUT;
1763 }
1764 }
1765
1766 spin_lock_irqsave(&dwc->lock, flags);
1767 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1768 spin_unlock_irqrestore(&dwc->lock, flags);
1769
1770 return ret;
1771}
1772
1773static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1774{
1775 u32 reg;
1776
1777 /* Enable all but Start and End of Frame IRQs */
1778 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1779 DWC3_DEVTEN_EVNTOVERFLOWEN |
1780 DWC3_DEVTEN_CMDCMPLTEN |
1781 DWC3_DEVTEN_ERRTICERREN |
1782 DWC3_DEVTEN_WKUPEVTEN |
1783 DWC3_DEVTEN_CONNECTDONEEN |
1784 DWC3_DEVTEN_USBRSTEN |
1785 DWC3_DEVTEN_DISCONNEVTEN);
1786
1787 if (dwc->revision < DWC3_REVISION_250A)
1788 reg |= DWC3_DEVTEN_ULSTCNGEN;
1789
1790 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1791}
1792
1793static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1794{
1795 /* mask all interrupts */
1796 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1797}
1798
1799static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1800static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1801
1802/**
1803 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1804 * @dwc: pointer to our context structure
1805 *
1806 * The following looks like complex but it's actually very simple. In order to
1807 * calculate the number of packets we can burst at once on OUT transfers, we're
1808 * gonna use RxFIFO size.
1809 *
1810 * To calculate RxFIFO size we need two numbers:
1811 * MDWIDTH = size, in bits, of the internal memory bus
1812 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1813 *
1814 * Given these two numbers, the formula is simple:
1815 *
1816 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1817 *
1818 * 24 bytes is for 3x SETUP packets
1819 * 16 bytes is a clock domain crossing tolerance
1820 *
1821 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1822 */
1823static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1824{
1825 u32 ram2_depth;
1826 u32 mdwidth;
1827 u32 nump;
1828 u32 reg;
1829
1830 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1831 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1832
1833 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1834 nump = min_t(u32, nump, 16);
1835
1836 /* update NumP */
1837 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1838 reg &= ~DWC3_DCFG_NUMP_MASK;
1839 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1840 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1841}
1842
1843static int __dwc3_gadget_start(struct dwc3 *dwc)
1844{
1845 struct dwc3_ep *dep;
1846 int ret = 0;
1847 u32 reg;
1848
1849 /*
1850 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1851 * the core supports IMOD, disable it.
1852 */
1853 if (dwc->imod_interval) {
1854 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1855 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1856 } else if (dwc3_has_imod(dwc)) {
1857 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1858 }
1859
1860 /*
1861 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1862 * field instead of letting dwc3 itself calculate that automatically.
1863 *
1864 * This way, we maximize the chances that we'll be able to get several
1865 * bursts of data without going through any sort of endpoint throttling.
1866 */
1867 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1868 if (dwc3_is_usb31(dwc))
1869 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1870 else
1871 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1872
1873 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1874
1875 dwc3_gadget_setup_nump(dwc);
1876
1877 /* Start with SuperSpeed Default */
1878 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1879
1880 dep = dwc->eps[0];
1881 ret = __dwc3_gadget_ep_enable(dep, false, false);
1882 if (ret) {
1883 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1884 goto err0;
1885 }
1886
1887 dep = dwc->eps[1];
1888 ret = __dwc3_gadget_ep_enable(dep, false, false);
1889 if (ret) {
1890 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1891 goto err1;
1892 }
1893
1894 /* begin to receive SETUP packets */
1895 dwc->ep0state = EP0_SETUP_PHASE;
1896 dwc3_ep0_out_start(dwc);
1897
1898 dwc3_gadget_enable_irq(dwc);
1899
1900 return 0;
1901
1902err1:
1903 __dwc3_gadget_ep_disable(dwc->eps[0]);
1904
1905err0:
1906 return ret;
1907}
1908
1909static int dwc3_gadget_start(struct usb_gadget *g,
1910 struct usb_gadget_driver *driver)
1911{
1912 struct dwc3 *dwc = gadget_to_dwc(g);
1913 unsigned long flags;
1914 int ret = 0;
1915 int irq;
1916
1917 irq = dwc->irq_gadget;
1918 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1919 IRQF_SHARED, "dwc3", dwc->ev_buf);
1920 if (ret) {
1921 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1922 irq, ret);
1923 goto err0;
1924 }
1925
1926 spin_lock_irqsave(&dwc->lock, flags);
1927 if (dwc->gadget_driver) {
1928 dev_err(dwc->dev, "%s is already bound to %s\n",
1929 dwc->gadget.name,
1930 dwc->gadget_driver->driver.name);
1931 ret = -EBUSY;
1932 goto err1;
1933 }
1934
1935 dwc->gadget_driver = driver;
1936
1937 if (pm_runtime_active(dwc->dev))
1938 __dwc3_gadget_start(dwc);
1939
1940 spin_unlock_irqrestore(&dwc->lock, flags);
1941
1942 return 0;
1943
1944err1:
1945 spin_unlock_irqrestore(&dwc->lock, flags);
1946 free_irq(irq, dwc);
1947
1948err0:
1949 return ret;
1950}
1951
1952static void __dwc3_gadget_stop(struct dwc3 *dwc)
1953{
1954 dwc3_gadget_disable_irq(dwc);
1955 __dwc3_gadget_ep_disable(dwc->eps[0]);
1956 __dwc3_gadget_ep_disable(dwc->eps[1]);
1957}
1958
1959static int dwc3_gadget_stop(struct usb_gadget *g)
1960{
1961 struct dwc3 *dwc = gadget_to_dwc(g);
1962 unsigned long flags;
1963 int epnum;
1964 u32 tmo_eps = 0;
1965
1966 spin_lock_irqsave(&dwc->lock, flags);
1967
1968 if (pm_runtime_suspended(dwc->dev))
1969 goto out;
1970
1971 __dwc3_gadget_stop(dwc);
1972
1973 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1974 struct dwc3_ep *dep = dwc->eps[epnum];
1975 int ret;
1976
1977 if (!dep)
1978 continue;
1979
1980 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1981 continue;
1982
1983 ret = wait_event_interruptible_lock_irq_timeout(dep->wait_end_transfer,
1984 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1985 dwc->lock, msecs_to_jiffies(5));
1986
1987 if (ret <= 0) {
1988 /* Timed out or interrupted! There's nothing much
1989 * we can do so we just log here and print which
1990 * endpoints timed out at the end.
1991 */
1992 tmo_eps |= 1 << epnum;
1993 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
1994 }
1995 }
1996
1997 if (tmo_eps) {
1998 dev_err(dwc->dev,
1999 "end transfer timed out on endpoints 0x%x [bitmap]\n",
2000 tmo_eps);
2001 }
2002
2003out:
2004 dwc->gadget_driver = NULL;
2005 spin_unlock_irqrestore(&dwc->lock, flags);
2006
2007 free_irq(dwc->irq_gadget, dwc->ev_buf);
2008
2009 return 0;
2010}
2011
2012static void dwc3_gadget_set_speed(struct usb_gadget *g,
2013 enum usb_device_speed speed)
2014{
2015 struct dwc3 *dwc = gadget_to_dwc(g);
2016 unsigned long flags;
2017 u32 reg;
2018
2019 spin_lock_irqsave(&dwc->lock, flags);
2020 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2021 reg &= ~(DWC3_DCFG_SPEED_MASK);
2022
2023 /*
2024 * WORKAROUND: DWC3 revision < 2.20a have an issue
2025 * which would cause metastability state on Run/Stop
2026 * bit if we try to force the IP to USB2-only mode.
2027 *
2028 * Because of that, we cannot configure the IP to any
2029 * speed other than the SuperSpeed
2030 *
2031 * Refers to:
2032 *
2033 * STAR#9000525659: Clock Domain Crossing on DCTL in
2034 * USB 2.0 Mode
2035 */
2036 if (dwc->revision < DWC3_REVISION_220A &&
2037 !dwc->dis_metastability_quirk) {
2038 reg |= DWC3_DCFG_SUPERSPEED;
2039 } else {
2040 switch (speed) {
2041 case USB_SPEED_LOW:
2042 reg |= DWC3_DCFG_LOWSPEED;
2043 break;
2044 case USB_SPEED_FULL:
2045 reg |= DWC3_DCFG_FULLSPEED;
2046 break;
2047 case USB_SPEED_HIGH:
2048 reg |= DWC3_DCFG_HIGHSPEED;
2049 break;
2050 case USB_SPEED_SUPER:
2051 reg |= DWC3_DCFG_SUPERSPEED;
2052 break;
2053 case USB_SPEED_SUPER_PLUS:
2054 if (dwc3_is_usb31(dwc))
2055 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2056 else
2057 reg |= DWC3_DCFG_SUPERSPEED;
2058 break;
2059 default:
2060 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2061
2062 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2063 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2064 else
2065 reg |= DWC3_DCFG_SUPERSPEED;
2066 }
2067 }
2068 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2069
2070 spin_unlock_irqrestore(&dwc->lock, flags);
2071}
2072
2073static const struct usb_gadget_ops dwc3_gadget_ops = {
2074 .get_frame = dwc3_gadget_get_frame,
2075 .wakeup = dwc3_gadget_wakeup,
2076 .set_selfpowered = dwc3_gadget_set_selfpowered,
2077 .pullup = dwc3_gadget_pullup,
2078 .udc_start = dwc3_gadget_start,
2079 .udc_stop = dwc3_gadget_stop,
2080 .udc_set_speed = dwc3_gadget_set_speed,
2081};
2082
2083/* -------------------------------------------------------------------------- */
2084
2085static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2086{
2087 struct dwc3_ep *dep;
2088 u8 epnum;
2089
2090 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2091
2092 for (epnum = 0; epnum < total; epnum++) {
2093 bool direction = epnum & 1;
2094 u8 num = epnum >> 1;
2095
2096 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2097 if (!dep)
2098 return -ENOMEM;
2099
2100 dep->dwc = dwc;
2101 dep->number = epnum;
2102 dep->direction = direction;
2103 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2104 dwc->eps[epnum] = dep;
2105
2106 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2107 direction ? "in" : "out");
2108
2109 dep->endpoint.name = dep->name;
2110
2111 if (!(dep->number > 1)) {
2112 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2113 dep->endpoint.comp_desc = NULL;
2114 }
2115
2116 spin_lock_init(&dep->lock);
2117
2118 if (num == 0) {
2119 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2120 dep->endpoint.maxburst = 1;
2121 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2122 if (!direction)
2123 dwc->gadget.ep0 = &dep->endpoint;
2124 } else if (direction) {
2125 int mdwidth;
2126 int kbytes;
2127 int size;
2128 int ret;
2129
2130 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2131 /* MDWIDTH is represented in bits, we need it in bytes */
2132 mdwidth /= 8;
2133
2134 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num));
2135 if (dwc3_is_usb31(dwc))
2136 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2137 else
2138 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2139
2140 /* FIFO Depth is in MDWDITH bytes. Multiply */
2141 size *= mdwidth;
2142
2143 kbytes = size / 1024;
2144 if (kbytes == 0)
2145 kbytes = 1;
2146
2147 /*
2148 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2149 * internal overhead. We don't really know how these are used,
2150 * but documentation say it exists.
2151 */
2152 size -= mdwidth * (kbytes + 1);
2153 size /= kbytes;
2154
2155 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2156
2157 dep->endpoint.max_streams = 15;
2158 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2159 list_add_tail(&dep->endpoint.ep_list,
2160 &dwc->gadget.ep_list);
2161
2162 ret = dwc3_alloc_trb_pool(dep);
2163 if (ret)
2164 return ret;
2165 } else {
2166 int ret;
2167
2168 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2169 dep->endpoint.max_streams = 15;
2170 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2171 list_add_tail(&dep->endpoint.ep_list,
2172 &dwc->gadget.ep_list);
2173
2174 ret = dwc3_alloc_trb_pool(dep);
2175 if (ret)
2176 return ret;
2177 }
2178
2179 if (num == 0) {
2180 dep->endpoint.caps.type_control = true;
2181 } else {
2182 dep->endpoint.caps.type_iso = true;
2183 dep->endpoint.caps.type_bulk = true;
2184 dep->endpoint.caps.type_int = true;
2185 }
2186
2187 dep->endpoint.caps.dir_in = direction;
2188 dep->endpoint.caps.dir_out = !direction;
2189
2190 INIT_LIST_HEAD(&dep->pending_list);
2191 INIT_LIST_HEAD(&dep->started_list);
2192 }
2193
2194 return 0;
2195}
2196
2197static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2198{
2199 struct dwc3_ep *dep;
2200 u8 epnum;
2201
2202 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2203 dep = dwc->eps[epnum];
2204 if (!dep)
2205 continue;
2206 /*
2207 * Physical endpoints 0 and 1 are special; they form the
2208 * bi-directional USB endpoint 0.
2209 *
2210 * For those two physical endpoints, we don't allocate a TRB
2211 * pool nor do we add them the endpoints list. Due to that, we
2212 * shouldn't do these two operations otherwise we would end up
2213 * with all sorts of bugs when removing dwc3.ko.
2214 */
2215 if (epnum != 0 && epnum != 1) {
2216 dwc3_free_trb_pool(dep);
2217 list_del(&dep->endpoint.ep_list);
2218 }
2219
2220 kfree(dep);
2221 }
2222}
2223
2224/* -------------------------------------------------------------------------- */
2225
2226static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2227 struct dwc3_request *req, struct dwc3_trb *trb,
2228 const struct dwc3_event_depevt *event, int status,
2229 int chain)
2230{
2231 unsigned int count;
2232 unsigned int s_pkt = 0;
2233 unsigned int trb_status;
2234
2235 dwc3_ep_inc_deq(dep);
2236
2237 if (req->trb == trb)
2238 dep->queued_requests--;
2239
2240 trace_dwc3_complete_trb(dep, trb);
2241
2242 /*
2243 * If we're in the middle of series of chained TRBs and we
2244 * receive a short transfer along the way, DWC3 will skip
2245 * through all TRBs including the last TRB in the chain (the
2246 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2247 * bit and SW has to do it manually.
2248 *
2249 * We're going to do that here to avoid problems of HW trying
2250 * to use bogus TRBs for transfers.
2251 */
2252 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2253 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2254
2255 /*
2256 * If we're dealing with unaligned size OUT transfer, we will be left
2257 * with one TRB pending in the ring. We need to manually clear HWO bit
2258 * from that TRB.
2259 */
2260 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2261 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2262 return 1;
2263 }
2264
2265 count = trb->size & DWC3_TRB_SIZE_MASK;
2266 req->remaining += count;
2267
2268 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2269 return 1;
2270
2271 if (dep->direction) {
2272 if (count) {
2273 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2274 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2275 /*
2276 * If missed isoc occurred and there is
2277 * no request queued then issue END
2278 * TRANSFER, so that core generates
2279 * next xfernotready and we will issue
2280 * a fresh START TRANSFER.
2281 * If there are still queued request
2282 * then wait, do not issue either END
2283 * or UPDATE TRANSFER, just attach next
2284 * request in pending_list during
2285 * giveback.If any future queued request
2286 * is successfully transferred then we
2287 * will issue UPDATE TRANSFER for all
2288 * request in the pending_list.
2289 */
2290 dep->flags |= DWC3_EP_MISSED_ISOC;
2291 } else {
2292 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2293 dep->name);
2294 status = -ECONNRESET;
2295 }
2296 } else {
2297 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2298 }
2299 } else {
2300 if (count && (event->status & DEPEVT_STATUS_SHORT))
2301 s_pkt = 1;
2302 }
2303
2304 if (s_pkt && !chain)
2305 return 1;
2306
2307 if ((event->status & DEPEVT_STATUS_IOC) &&
2308 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2309 return 1;
2310
2311 return 0;
2312}
2313
2314static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2315 const struct dwc3_event_depevt *event, int status)
2316{
2317 struct dwc3_request *req, *n;
2318 struct dwc3_trb *trb;
2319 bool ioc = false;
2320 int ret = 0;
2321
2322 list_for_each_entry_safe(req, n, &dep->started_list, list) {
2323 unsigned length;
2324 int chain;
2325
2326 length = req->request.length;
2327 chain = req->num_pending_sgs > 0;
2328 if (chain) {
2329 struct scatterlist *sg = req->sg;
2330 struct scatterlist *s;
2331 unsigned int pending = req->num_pending_sgs;
2332 unsigned int i;
2333
2334 for_each_sg(sg, s, pending, i) {
2335 trb = &dep->trb_pool[dep->trb_dequeue];
2336
2337 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2338 break;
2339
2340 req->sg = sg_next(s);
2341 req->num_pending_sgs--;
2342
2343 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2344 event, status, chain);
2345 if (ret)
2346 break;
2347 }
2348 } else {
2349 trb = &dep->trb_pool[dep->trb_dequeue];
2350 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2351 event, status, chain);
2352 }
2353
2354 if (req->unaligned || req->zero) {
2355 trb = &dep->trb_pool[dep->trb_dequeue];
2356 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2357 event, status, false);
2358 req->unaligned = false;
2359 req->zero = false;
2360 }
2361
2362 req->request.actual = length - req->remaining;
2363
2364 if ((req->request.actual < length) && req->num_pending_sgs)
2365 return __dwc3_gadget_kick_transfer(dep);
2366
2367 dwc3_gadget_giveback(dep, req, status);
2368
2369 if (ret) {
2370 if ((event->status & DEPEVT_STATUS_IOC) &&
2371 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2372 ioc = true;
2373 break;
2374 }
2375 }
2376
2377 /*
2378 * Our endpoint might get disabled by another thread during
2379 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2380 * early on so DWC3_EP_BUSY flag gets cleared
2381 */
2382 if (!dep->endpoint.desc)
2383 return 1;
2384
2385 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2386 list_empty(&dep->started_list)) {
2387 if (list_empty(&dep->pending_list)) {
2388 /*
2389 * If there is no entry in request list then do
2390 * not issue END TRANSFER now. Just set PENDING
2391 * flag, so that END TRANSFER is issued when an
2392 * entry is added into request list.
2393 */
2394 dep->flags = DWC3_EP_PENDING_REQUEST;
2395 } else {
2396 dwc3_stop_active_transfer(dwc, dep->number, true);
2397 dep->flags = DWC3_EP_ENABLED;
2398 }
2399 return 1;
2400 }
2401
2402 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2403 return 0;
2404
2405 return 1;
2406}
2407
2408static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2409 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2410{
2411 unsigned status = 0;
2412 int clean_busy;
2413 u32 is_xfer_complete;
2414
2415 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2416
2417 if (event->status & DEPEVT_STATUS_BUSERR)
2418 status = -ECONNRESET;
2419
2420 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2421 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2422 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2423 dep->flags &= ~DWC3_EP_BUSY;
2424
2425 /*
2426 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2427 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2428 */
2429 if (dwc->revision < DWC3_REVISION_183A) {
2430 u32 reg;
2431 int i;
2432
2433 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2434 dep = dwc->eps[i];
2435
2436 if (!(dep->flags & DWC3_EP_ENABLED))
2437 continue;
2438
2439 if (!list_empty(&dep->started_list))
2440 return;
2441 }
2442
2443 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2444 reg |= dwc->u1u2;
2445 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2446
2447 dwc->u1u2 = 0;
2448 }
2449
2450 /*
2451 * Our endpoint might get disabled by another thread during
2452 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2453 * early on so DWC3_EP_BUSY flag gets cleared
2454 */
2455 if (!dep->endpoint.desc)
2456 return;
2457
2458 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc))
2459 __dwc3_gadget_kick_transfer(dep);
2460}
2461
2462static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2463 const struct dwc3_event_depevt *event)
2464{
2465 struct dwc3_ep *dep;
2466 u8 epnum = event->endpoint_number;
2467 u8 cmd;
2468
2469 dep = dwc->eps[epnum];
2470
2471 if (!(dep->flags & DWC3_EP_ENABLED)) {
2472 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2473 return;
2474
2475 /* Handle only EPCMDCMPLT when EP disabled */
2476 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2477 return;
2478 }
2479
2480 if (epnum == 0 || epnum == 1) {
2481 dwc3_ep0_interrupt(dwc, event);
2482 return;
2483 }
2484
2485 switch (event->endpoint_event) {
2486 case DWC3_DEPEVT_XFERCOMPLETE:
2487 dep->resource_index = 0;
2488
2489 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2490 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2491 return;
2492 }
2493
2494 dwc3_endpoint_transfer_complete(dwc, dep, event);
2495 break;
2496 case DWC3_DEPEVT_XFERINPROGRESS:
2497 dwc3_endpoint_transfer_complete(dwc, dep, event);
2498 break;
2499 case DWC3_DEPEVT_XFERNOTREADY:
2500 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2501 dwc3_gadget_start_isoc(dwc, dep, event);
2502 else
2503 __dwc3_gadget_kick_transfer(dep);
2504
2505 break;
2506 case DWC3_DEPEVT_STREAMEVT:
2507 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2508 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2509 dep->name);
2510 return;
2511 }
2512 break;
2513 case DWC3_DEPEVT_EPCMDCMPLT:
2514 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2515
2516 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2517 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2518 wake_up(&dep->wait_end_transfer);
2519 }
2520 break;
2521 case DWC3_DEPEVT_RXTXFIFOEVT:
2522 break;
2523 }
2524}
2525
2526static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2527{
2528 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2529 spin_unlock(&dwc->lock);
2530 dwc->gadget_driver->disconnect(&dwc->gadget);
2531 spin_lock(&dwc->lock);
2532 }
2533}
2534
2535static void dwc3_suspend_gadget(struct dwc3 *dwc)
2536{
2537 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2538 spin_unlock(&dwc->lock);
2539 dwc->gadget_driver->suspend(&dwc->gadget);
2540 spin_lock(&dwc->lock);
2541 }
2542}
2543
2544static void dwc3_resume_gadget(struct dwc3 *dwc)
2545{
2546 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2547 spin_unlock(&dwc->lock);
2548 dwc->gadget_driver->resume(&dwc->gadget);
2549 spin_lock(&dwc->lock);
2550 }
2551}
2552
2553static void dwc3_reset_gadget(struct dwc3 *dwc)
2554{
2555 if (!dwc->gadget_driver)
2556 return;
2557
2558 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2559 spin_unlock(&dwc->lock);
2560 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2561 spin_lock(&dwc->lock);
2562 }
2563}
2564
2565static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2566{
2567 struct dwc3_ep *dep;
2568 struct dwc3_gadget_ep_cmd_params params;
2569 u32 cmd;
2570 int ret;
2571
2572 dep = dwc->eps[epnum];
2573
2574 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2575 !dep->resource_index)
2576 return;
2577
2578 /*
2579 * NOTICE: We are violating what the Databook says about the
2580 * EndTransfer command. Ideally we would _always_ wait for the
2581 * EndTransfer Command Completion IRQ, but that's causing too
2582 * much trouble synchronizing between us and gadget driver.
2583 *
2584 * We have discussed this with the IP Provider and it was
2585 * suggested to giveback all requests here, but give HW some
2586 * extra time to synchronize with the interconnect. We're using
2587 * an arbitrary 100us delay for that.
2588 *
2589 * Note also that a similar handling was tested by Synopsys
2590 * (thanks a lot Paul) and nothing bad has come out of it.
2591 * In short, what we're doing is:
2592 *
2593 * - Issue EndTransfer WITH CMDIOC bit set
2594 * - Wait 100us
2595 *
2596 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2597 * supports a mode to work around the above limitation. The
2598 * software can poll the CMDACT bit in the DEPCMD register
2599 * after issuing a EndTransfer command. This mode is enabled
2600 * by writing GUCTL2[14]. This polling is already done in the
2601 * dwc3_send_gadget_ep_cmd() function so if the mode is
2602 * enabled, the EndTransfer command will have completed upon
2603 * returning from this function and we don't need to delay for
2604 * 100us.
2605 *
2606 * This mode is NOT available on the DWC_usb31 IP.
2607 */
2608
2609 cmd = DWC3_DEPCMD_ENDTRANSFER;
2610 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2611 cmd |= DWC3_DEPCMD_CMDIOC;
2612 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2613 memset(¶ms, 0, sizeof(params));
2614 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2615 WARN_ON_ONCE(ret);
2616 dep->resource_index = 0;
2617 dep->flags &= ~DWC3_EP_BUSY;
2618
2619 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2620 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2621 udelay(100);
2622 }
2623}
2624
2625static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2626{
2627 u32 epnum;
2628
2629 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2630 struct dwc3_ep *dep;
2631 int ret;
2632
2633 dep = dwc->eps[epnum];
2634 if (!dep)
2635 continue;
2636
2637 if (!(dep->flags & DWC3_EP_STALL))
2638 continue;
2639
2640 dep->flags &= ~DWC3_EP_STALL;
2641
2642 ret = dwc3_send_clear_stall_ep_cmd(dep);
2643 WARN_ON_ONCE(ret);
2644 }
2645}
2646
2647static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2648{
2649 int reg;
2650
2651 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2652 reg &= ~DWC3_DCTL_INITU1ENA;
2653 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2654
2655 reg &= ~DWC3_DCTL_INITU2ENA;
2656 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2657
2658 dwc3_disconnect_gadget(dwc);
2659
2660 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2661 dwc->setup_packet_pending = false;
2662 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2663
2664 dwc->connected = false;
2665}
2666
2667static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2668{
2669 u32 reg;
2670
2671 dwc->connected = true;
2672
2673 /*
2674 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2675 * would cause a missing Disconnect Event if there's a
2676 * pending Setup Packet in the FIFO.
2677 *
2678 * There's no suggested workaround on the official Bug
2679 * report, which states that "unless the driver/application
2680 * is doing any special handling of a disconnect event,
2681 * there is no functional issue".
2682 *
2683 * Unfortunately, it turns out that we _do_ some special
2684 * handling of a disconnect event, namely complete all
2685 * pending transfers, notify gadget driver of the
2686 * disconnection, and so on.
2687 *
2688 * Our suggested workaround is to follow the Disconnect
2689 * Event steps here, instead, based on a setup_packet_pending
2690 * flag. Such flag gets set whenever we have a SETUP_PENDING
2691 * status for EP0 TRBs and gets cleared on XferComplete for the
2692 * same endpoint.
2693 *
2694 * Refers to:
2695 *
2696 * STAR#9000466709: RTL: Device : Disconnect event not
2697 * generated if setup packet pending in FIFO
2698 */
2699 if (dwc->revision < DWC3_REVISION_188A) {
2700 if (dwc->setup_packet_pending)
2701 dwc3_gadget_disconnect_interrupt(dwc);
2702 }
2703
2704 dwc3_reset_gadget(dwc);
2705
2706 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2707 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2708 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2709 dwc->test_mode = false;
2710 dwc3_clear_stall_all_ep(dwc);
2711
2712 /* Reset device address to zero */
2713 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2714 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2715 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2716}
2717
2718static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2719{
2720 struct dwc3_ep *dep;
2721 int ret;
2722 u32 reg;
2723 u8 speed;
2724
2725 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2726 speed = reg & DWC3_DSTS_CONNECTSPD;
2727 dwc->speed = speed;
2728
2729 /*
2730 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2731 * each time on Connect Done.
2732 *
2733 * Currently we always use the reset value. If any platform
2734 * wants to set this to a different value, we need to add a
2735 * setting and update GCTL.RAMCLKSEL here.
2736 */
2737
2738 switch (speed) {
2739 case DWC3_DSTS_SUPERSPEED_PLUS:
2740 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2741 dwc->gadget.ep0->maxpacket = 512;
2742 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2743 break;
2744 case DWC3_DSTS_SUPERSPEED:
2745 /*
2746 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2747 * would cause a missing USB3 Reset event.
2748 *
2749 * In such situations, we should force a USB3 Reset
2750 * event by calling our dwc3_gadget_reset_interrupt()
2751 * routine.
2752 *
2753 * Refers to:
2754 *
2755 * STAR#9000483510: RTL: SS : USB3 reset event may
2756 * not be generated always when the link enters poll
2757 */
2758 if (dwc->revision < DWC3_REVISION_190A)
2759 dwc3_gadget_reset_interrupt(dwc);
2760
2761 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2762 dwc->gadget.ep0->maxpacket = 512;
2763 dwc->gadget.speed = USB_SPEED_SUPER;
2764 break;
2765 case DWC3_DSTS_HIGHSPEED:
2766 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2767 dwc->gadget.ep0->maxpacket = 64;
2768 dwc->gadget.speed = USB_SPEED_HIGH;
2769 break;
2770 case DWC3_DSTS_FULLSPEED:
2771 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2772 dwc->gadget.ep0->maxpacket = 64;
2773 dwc->gadget.speed = USB_SPEED_FULL;
2774 break;
2775 case DWC3_DSTS_LOWSPEED:
2776 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2777 dwc->gadget.ep0->maxpacket = 8;
2778 dwc->gadget.speed = USB_SPEED_LOW;
2779 break;
2780 }
2781
2782 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2783
2784 /* Enable USB2 LPM Capability */
2785
2786 if ((dwc->revision > DWC3_REVISION_194A) &&
2787 (speed != DWC3_DSTS_SUPERSPEED) &&
2788 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2789 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2790 reg |= DWC3_DCFG_LPM_CAP;
2791 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2792
2793 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2794 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2795
2796 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2797
2798 /*
2799 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2800 * DCFG.LPMCap is set, core responses with an ACK and the
2801 * BESL value in the LPM token is less than or equal to LPM
2802 * NYET threshold.
2803 */
2804 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2805 && dwc->has_lpm_erratum,
2806 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2807
2808 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2809 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2810
2811 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2812 } else {
2813 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2814 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2815 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2816 }
2817
2818 dep = dwc->eps[0];
2819 ret = __dwc3_gadget_ep_enable(dep, true, false);
2820 if (ret) {
2821 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2822 return;
2823 }
2824
2825 dep = dwc->eps[1];
2826 ret = __dwc3_gadget_ep_enable(dep, true, false);
2827 if (ret) {
2828 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2829 return;
2830 }
2831
2832 /*
2833 * Configure PHY via GUSB3PIPECTLn if required.
2834 *
2835 * Update GTXFIFOSIZn
2836 *
2837 * In both cases reset values should be sufficient.
2838 */
2839}
2840
2841static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2842{
2843 /*
2844 * TODO take core out of low power mode when that's
2845 * implemented.
2846 */
2847
2848 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2849 spin_unlock(&dwc->lock);
2850 dwc->gadget_driver->resume(&dwc->gadget);
2851 spin_lock(&dwc->lock);
2852 }
2853}
2854
2855static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2856 unsigned int evtinfo)
2857{
2858 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2859 unsigned int pwropt;
2860
2861 /*
2862 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2863 * Hibernation mode enabled which would show up when device detects
2864 * host-initiated U3 exit.
2865 *
2866 * In that case, device will generate a Link State Change Interrupt
2867 * from U3 to RESUME which is only necessary if Hibernation is
2868 * configured in.
2869 *
2870 * There are no functional changes due to such spurious event and we
2871 * just need to ignore it.
2872 *
2873 * Refers to:
2874 *
2875 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2876 * operational mode
2877 */
2878 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2879 if ((dwc->revision < DWC3_REVISION_250A) &&
2880 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2881 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2882 (next == DWC3_LINK_STATE_RESUME)) {
2883 return;
2884 }
2885 }
2886
2887 /*
2888 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2889 * on the link partner, the USB session might do multiple entry/exit
2890 * of low power states before a transfer takes place.
2891 *
2892 * Due to this problem, we might experience lower throughput. The
2893 * suggested workaround is to disable DCTL[12:9] bits if we're
2894 * transitioning from U1/U2 to U0 and enable those bits again
2895 * after a transfer completes and there are no pending transfers
2896 * on any of the enabled endpoints.
2897 *
2898 * This is the first half of that workaround.
2899 *
2900 * Refers to:
2901 *
2902 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2903 * core send LGO_Ux entering U0
2904 */
2905 if (dwc->revision < DWC3_REVISION_183A) {
2906 if (next == DWC3_LINK_STATE_U0) {
2907 u32 u1u2;
2908 u32 reg;
2909
2910 switch (dwc->link_state) {
2911 case DWC3_LINK_STATE_U1:
2912 case DWC3_LINK_STATE_U2:
2913 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2914 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2915 | DWC3_DCTL_ACCEPTU2ENA
2916 | DWC3_DCTL_INITU1ENA
2917 | DWC3_DCTL_ACCEPTU1ENA);
2918
2919 if (!dwc->u1u2)
2920 dwc->u1u2 = reg & u1u2;
2921
2922 reg &= ~u1u2;
2923
2924 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2925 break;
2926 default:
2927 /* do nothing */
2928 break;
2929 }
2930 }
2931 }
2932
2933 switch (next) {
2934 case DWC3_LINK_STATE_U1:
2935 if (dwc->speed == USB_SPEED_SUPER)
2936 dwc3_suspend_gadget(dwc);
2937 break;
2938 case DWC3_LINK_STATE_U2:
2939 case DWC3_LINK_STATE_U3:
2940 dwc3_suspend_gadget(dwc);
2941 break;
2942 case DWC3_LINK_STATE_RESUME:
2943 dwc3_resume_gadget(dwc);
2944 break;
2945 default:
2946 /* do nothing */
2947 break;
2948 }
2949
2950 dwc->link_state = next;
2951}
2952
2953static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2954 unsigned int evtinfo)
2955{
2956 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2957
2958 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2959 dwc3_suspend_gadget(dwc);
2960
2961 dwc->link_state = next;
2962}
2963
2964static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2965 unsigned int evtinfo)
2966{
2967 unsigned int is_ss = evtinfo & BIT(4);
2968
2969 /*
2970 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2971 * have a known issue which can cause USB CV TD.9.23 to fail
2972 * randomly.
2973 *
2974 * Because of this issue, core could generate bogus hibernation
2975 * events which SW needs to ignore.
2976 *
2977 * Refers to:
2978 *
2979 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2980 * Device Fallback from SuperSpeed
2981 */
2982 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2983 return;
2984
2985 /* enter hibernation here */
2986}
2987
2988static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2989 const struct dwc3_event_devt *event)
2990{
2991 switch (event->type) {
2992 case DWC3_DEVICE_EVENT_DISCONNECT:
2993 dwc3_gadget_disconnect_interrupt(dwc);
2994 break;
2995 case DWC3_DEVICE_EVENT_RESET:
2996 dwc3_gadget_reset_interrupt(dwc);
2997 break;
2998 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2999 dwc3_gadget_conndone_interrupt(dwc);
3000 break;
3001 case DWC3_DEVICE_EVENT_WAKEUP:
3002 dwc3_gadget_wakeup_interrupt(dwc);
3003 break;
3004 case DWC3_DEVICE_EVENT_HIBER_REQ:
3005 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3006 "unexpected hibernation event\n"))
3007 break;
3008
3009 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3010 break;
3011 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3012 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3013 break;
3014 case DWC3_DEVICE_EVENT_EOPF:
3015 /* It changed to be suspend event for version 2.30a and above */
3016 if (dwc->revision >= DWC3_REVISION_230A) {
3017 /*
3018 * Ignore suspend event until the gadget enters into
3019 * USB_STATE_CONFIGURED state.
3020 */
3021 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3022 dwc3_gadget_suspend_interrupt(dwc,
3023 event->event_info);
3024 }
3025 break;
3026 case DWC3_DEVICE_EVENT_SOF:
3027 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3028 case DWC3_DEVICE_EVENT_CMD_CMPL:
3029 case DWC3_DEVICE_EVENT_OVERFLOW:
3030 break;
3031 default:
3032 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3033 }
3034}
3035
3036static void dwc3_process_event_entry(struct dwc3 *dwc,
3037 const union dwc3_event *event)
3038{
3039 trace_dwc3_event(event->raw, dwc);
3040
3041 if (!event->type.is_devspec)
3042 dwc3_endpoint_interrupt(dwc, &event->depevt);
3043 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3044 dwc3_gadget_interrupt(dwc, &event->devt);
3045 else
3046 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3047}
3048
3049static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3050{
3051 struct dwc3 *dwc = evt->dwc;
3052 irqreturn_t ret = IRQ_NONE;
3053 int left;
3054 u32 reg;
3055
3056 left = evt->count;
3057
3058 if (!(evt->flags & DWC3_EVENT_PENDING))
3059 return IRQ_NONE;
3060
3061 while (left > 0) {
3062 union dwc3_event event;
3063
3064 event.raw = *(u32 *) (evt->cache + evt->lpos);
3065
3066 dwc3_process_event_entry(dwc, &event);
3067
3068 /*
3069 * FIXME we wrap around correctly to the next entry as
3070 * almost all entries are 4 bytes in size. There is one
3071 * entry which has 12 bytes which is a regular entry
3072 * followed by 8 bytes data. ATM I don't know how
3073 * things are organized if we get next to the a
3074 * boundary so I worry about that once we try to handle
3075 * that.
3076 */
3077 evt->lpos = (evt->lpos + 4) % evt->length;
3078 left -= 4;
3079 }
3080
3081 evt->count = 0;
3082 evt->flags &= ~DWC3_EVENT_PENDING;
3083 ret = IRQ_HANDLED;
3084
3085 /* Unmask interrupt */
3086 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3087 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3088 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3089
3090 if (dwc->imod_interval) {
3091 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3092 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3093 }
3094
3095 return ret;
3096}
3097
3098static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3099{
3100 struct dwc3_event_buffer *evt = _evt;
3101 struct dwc3 *dwc = evt->dwc;
3102 unsigned long flags;
3103 irqreturn_t ret = IRQ_NONE;
3104
3105 spin_lock_irqsave(&dwc->lock, flags);
3106 ret = dwc3_process_event_buf(evt);
3107 spin_unlock_irqrestore(&dwc->lock, flags);
3108
3109 return ret;
3110}
3111
3112static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3113{
3114 struct dwc3 *dwc = evt->dwc;
3115 u32 amount;
3116 u32 count;
3117 u32 reg;
3118
3119 if (pm_runtime_suspended(dwc->dev)) {
3120 pm_runtime_get(dwc->dev);
3121 disable_irq_nosync(dwc->irq_gadget);
3122 dwc->pending_events = true;
3123 return IRQ_HANDLED;
3124 }
3125
3126 /*
3127 * With PCIe legacy interrupt, test shows that top-half irq handler can
3128 * be called again after HW interrupt deassertion. Check if bottom-half
3129 * irq event handler completes before caching new event to prevent
3130 * losing events.
3131 */
3132 if (evt->flags & DWC3_EVENT_PENDING)
3133 return IRQ_HANDLED;
3134
3135 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3136 count &= DWC3_GEVNTCOUNT_MASK;
3137 if (!count)
3138 return IRQ_NONE;
3139
3140 evt->count = count;
3141 evt->flags |= DWC3_EVENT_PENDING;
3142
3143 /* Mask interrupt */
3144 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3145 reg |= DWC3_GEVNTSIZ_INTMASK;
3146 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3147
3148 amount = min(count, evt->length - evt->lpos);
3149 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3150
3151 if (amount < count)
3152 memcpy(evt->cache, evt->buf, count - amount);
3153
3154 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3155
3156 return IRQ_WAKE_THREAD;
3157}
3158
3159static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3160{
3161 struct dwc3_event_buffer *evt = _evt;
3162
3163 return dwc3_check_event_buf(evt);
3164}
3165
3166static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3167{
3168 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3169 int irq;
3170
3171 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3172 if (irq > 0)
3173 goto out;
3174
3175 if (irq == -EPROBE_DEFER)
3176 goto out;
3177
3178 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3179 if (irq > 0)
3180 goto out;
3181
3182 if (irq == -EPROBE_DEFER)
3183 goto out;
3184
3185 irq = platform_get_irq(dwc3_pdev, 0);
3186 if (irq > 0)
3187 goto out;
3188
3189 if (irq != -EPROBE_DEFER)
3190 dev_err(dwc->dev, "missing peripheral IRQ\n");
3191
3192 if (!irq)
3193 irq = -EINVAL;
3194
3195out:
3196 return irq;
3197}
3198
3199/**
3200 * dwc3_gadget_init - initializes gadget related registers
3201 * @dwc: pointer to our controller context structure
3202 *
3203 * Returns 0 on success otherwise negative errno.
3204 */
3205int dwc3_gadget_init(struct dwc3 *dwc)
3206{
3207 int ret;
3208 int irq;
3209
3210 irq = dwc3_gadget_get_irq(dwc);
3211 if (irq < 0) {
3212 ret = irq;
3213 goto err0;
3214 }
3215
3216 dwc->irq_gadget = irq;
3217
3218 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3219 sizeof(*dwc->ep0_trb) * 2,
3220 &dwc->ep0_trb_addr, GFP_KERNEL);
3221 if (!dwc->ep0_trb) {
3222 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3223 ret = -ENOMEM;
3224 goto err0;
3225 }
3226
3227 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3228 if (!dwc->setup_buf) {
3229 ret = -ENOMEM;
3230 goto err1;
3231 }
3232
3233 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3234 &dwc->bounce_addr, GFP_KERNEL);
3235 if (!dwc->bounce) {
3236 ret = -ENOMEM;
3237 goto err2;
3238 }
3239
3240 init_completion(&dwc->ep0_in_setup);
3241
3242 dwc->gadget.ops = &dwc3_gadget_ops;
3243 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3244 dwc->gadget.sg_supported = true;
3245 dwc->gadget.name = "dwc3-gadget";
3246 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3247
3248 /*
3249 * FIXME We might be setting max_speed to <SUPER, however versions
3250 * <2.20a of dwc3 have an issue with metastability (documented
3251 * elsewhere in this driver) which tells us we can't set max speed to
3252 * anything lower than SUPER.
3253 *
3254 * Because gadget.max_speed is only used by composite.c and function
3255 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3256 * to happen so we avoid sending SuperSpeed Capability descriptor
3257 * together with our BOS descriptor as that could confuse host into
3258 * thinking we can handle super speed.
3259 *
3260 * Note that, in fact, we won't even support GetBOS requests when speed
3261 * is less than super speed because we don't have means, yet, to tell
3262 * composite.c that we are USB 2.0 + LPM ECN.
3263 */
3264 if (dwc->revision < DWC3_REVISION_220A &&
3265 !dwc->dis_metastability_quirk)
3266 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3267 dwc->revision);
3268
3269 dwc->gadget.max_speed = dwc->maximum_speed;
3270
3271 /*
3272 * REVISIT: Here we should clear all pending IRQs to be
3273 * sure we're starting from a well known location.
3274 */
3275
3276 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3277 if (ret)
3278 goto err3;
3279
3280 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3281 if (ret) {
3282 dev_err(dwc->dev, "failed to register udc\n");
3283 goto err4;
3284 }
3285
3286 return 0;
3287
3288err4:
3289 dwc3_gadget_free_endpoints(dwc);
3290
3291err3:
3292 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3293 dwc->bounce_addr);
3294
3295err2:
3296 kfree(dwc->setup_buf);
3297
3298err1:
3299 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3300 dwc->ep0_trb, dwc->ep0_trb_addr);
3301
3302err0:
3303 return ret;
3304}
3305
3306/* -------------------------------------------------------------------------- */
3307
3308void dwc3_gadget_exit(struct dwc3 *dwc)
3309{
3310 usb_del_gadget_udc(&dwc->gadget);
3311 dwc3_gadget_free_endpoints(dwc);
3312 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3313 dwc->bounce_addr);
3314 kfree(dwc->setup_buf);
3315 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3316 dwc->ep0_trb, dwc->ep0_trb_addr);
3317}
3318
3319int dwc3_gadget_suspend(struct dwc3 *dwc)
3320{
3321 if (!dwc->gadget_driver)
3322 return 0;
3323
3324 dwc3_gadget_run_stop(dwc, false, false);
3325 dwc3_disconnect_gadget(dwc);
3326 __dwc3_gadget_stop(dwc);
3327
3328 return 0;
3329}
3330
3331int dwc3_gadget_resume(struct dwc3 *dwc)
3332{
3333 int ret;
3334
3335 if (!dwc->gadget_driver)
3336 return 0;
3337
3338 ret = __dwc3_gadget_start(dwc);
3339 if (ret < 0)
3340 goto err0;
3341
3342 ret = dwc3_gadget_run_stop(dwc, true, false);
3343 if (ret < 0)
3344 goto err1;
3345
3346 return 0;
3347
3348err1:
3349 __dwc3_gadget_stop(dwc);
3350
3351err0:
3352 return ret;
3353}
3354
3355void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3356{
3357 if (dwc->pending_events) {
3358 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3359 dwc->pending_events = false;
3360 enable_irq(dwc->irq_gadget);
3361 }
3362}