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1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
33#include "debug.h"
34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
97 int retries = 10000;
98 u32 reg;
99
100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
131 /* wait for a change in DSTS */
132 retries = 10000;
133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
139 udelay(5);
140 }
141
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
144
145 return -ETIMEDOUT;
146}
147
148/**
149 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
150 * @dwc: pointer to our context structure
151 *
152 * This function will a best effort FIFO allocation in order
153 * to improve FIFO usage and throughput, while still allowing
154 * us to enable as many endpoints as possible.
155 *
156 * Keep in mind that this operation will be highly dependent
157 * on the configured size for RAM1 - which contains TxFifo -,
158 * the amount of endpoints enabled on coreConsultant tool, and
159 * the width of the Master Bus.
160 *
161 * In the ideal world, we would always be able to satisfy the
162 * following equation:
163 *
164 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
165 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
166 *
167 * Unfortunately, due to many variables that's not always the case.
168 */
169int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
170{
171 int last_fifo_depth = 0;
172 int ram1_depth;
173 int fifo_size;
174 int mdwidth;
175 int num;
176
177 if (!dwc->needs_fifo_resize)
178 return 0;
179
180 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
181 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
182
183 /* MDWIDTH is represented in bits, we need it in bytes */
184 mdwidth >>= 3;
185
186 /*
187 * FIXME For now we will only allocate 1 wMaxPacketSize space
188 * for each enabled endpoint, later patches will come to
189 * improve this algorithm so that we better use the internal
190 * FIFO space
191 */
192 for (num = 0; num < dwc->num_in_eps; num++) {
193 /* bit0 indicates direction; 1 means IN ep */
194 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
195 int mult = 1;
196 int tmp;
197
198 if (!(dep->flags & DWC3_EP_ENABLED))
199 continue;
200
201 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
202 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
203 mult = 3;
204
205 /*
206 * REVISIT: the following assumes we will always have enough
207 * space available on the FIFO RAM for all possible use cases.
208 * Make sure that's true somehow and change FIFO allocation
209 * accordingly.
210 *
211 * If we have Bulk or Isochronous endpoints, we want
212 * them to be able to be very, very fast. So we're giving
213 * those endpoints a fifo_size which is enough for 3 full
214 * packets
215 */
216 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
217 tmp += mdwidth;
218
219 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
220
221 fifo_size |= (last_fifo_depth << 16);
222
223 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
224 dep->name, last_fifo_depth, fifo_size & 0xffff);
225
226 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
227
228 last_fifo_depth += (fifo_size & 0xffff);
229 }
230
231 return 0;
232}
233
234void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
235 int status)
236{
237 struct dwc3 *dwc = dep->dwc;
238 int i;
239
240 if (req->queued) {
241 i = 0;
242 do {
243 dep->busy_slot++;
244 /*
245 * Skip LINK TRB. We can't use req->trb and check for
246 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
247 * just completed (not the LINK TRB).
248 */
249 if (((dep->busy_slot & DWC3_TRB_MASK) ==
250 DWC3_TRB_NUM- 1) &&
251 usb_endpoint_xfer_isoc(dep->endpoint.desc))
252 dep->busy_slot++;
253 } while(++i < req->request.num_mapped_sgs);
254 req->queued = false;
255 }
256 list_del(&req->list);
257 req->trb = NULL;
258
259 if (req->request.status == -EINPROGRESS)
260 req->request.status = status;
261
262 if (dwc->ep0_bounced && dep->number == 0)
263 dwc->ep0_bounced = false;
264 else
265 usb_gadget_unmap_request(&dwc->gadget, &req->request,
266 req->direction);
267
268 trace_dwc3_gadget_giveback(req);
269
270 spin_unlock(&dwc->lock);
271 usb_gadget_giveback_request(&dep->endpoint, &req->request);
272 spin_lock(&dwc->lock);
273}
274
275int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
276{
277 u32 timeout = 500;
278 u32 reg;
279
280 trace_dwc3_gadget_generic_cmd(cmd, param);
281
282 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
283 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
284
285 do {
286 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
287 if (!(reg & DWC3_DGCMD_CMDACT)) {
288 dwc3_trace(trace_dwc3_gadget,
289 "Command Complete --> %d",
290 DWC3_DGCMD_STATUS(reg));
291 if (DWC3_DGCMD_STATUS(reg))
292 return -EINVAL;
293 return 0;
294 }
295
296 /*
297 * We can't sleep here, because it's also called from
298 * interrupt context.
299 */
300 timeout--;
301 if (!timeout) {
302 dwc3_trace(trace_dwc3_gadget,
303 "Command Timed Out");
304 return -ETIMEDOUT;
305 }
306 udelay(1);
307 } while (1);
308}
309
310int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
311 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
312{
313 struct dwc3_ep *dep = dwc->eps[ep];
314 u32 timeout = 500;
315 u32 reg;
316
317 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
318
319 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
320 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
321 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
322
323 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
324 do {
325 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
326 if (!(reg & DWC3_DEPCMD_CMDACT)) {
327 dwc3_trace(trace_dwc3_gadget,
328 "Command Complete --> %d",
329 DWC3_DEPCMD_STATUS(reg));
330 if (DWC3_DEPCMD_STATUS(reg))
331 return -EINVAL;
332 return 0;
333 }
334
335 /*
336 * We can't sleep here, because it is also called from
337 * interrupt context.
338 */
339 timeout--;
340 if (!timeout) {
341 dwc3_trace(trace_dwc3_gadget,
342 "Command Timed Out");
343 return -ETIMEDOUT;
344 }
345
346 udelay(1);
347 } while (1);
348}
349
350static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
351 struct dwc3_trb *trb)
352{
353 u32 offset = (char *) trb - (char *) dep->trb_pool;
354
355 return dep->trb_pool_dma + offset;
356}
357
358static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
359{
360 struct dwc3 *dwc = dep->dwc;
361
362 if (dep->trb_pool)
363 return 0;
364
365 dep->trb_pool = dma_alloc_coherent(dwc->dev,
366 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
367 &dep->trb_pool_dma, GFP_KERNEL);
368 if (!dep->trb_pool) {
369 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
370 dep->name);
371 return -ENOMEM;
372 }
373
374 return 0;
375}
376
377static void dwc3_free_trb_pool(struct dwc3_ep *dep)
378{
379 struct dwc3 *dwc = dep->dwc;
380
381 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
382 dep->trb_pool, dep->trb_pool_dma);
383
384 dep->trb_pool = NULL;
385 dep->trb_pool_dma = 0;
386}
387
388static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
389
390/**
391 * dwc3_gadget_start_config - Configure EP resources
392 * @dwc: pointer to our controller context structure
393 * @dep: endpoint that is being enabled
394 *
395 * The assignment of transfer resources cannot perfectly follow the
396 * data book due to the fact that the controller driver does not have
397 * all knowledge of the configuration in advance. It is given this
398 * information piecemeal by the composite gadget framework after every
399 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
400 * programming model in this scenario can cause errors. For two
401 * reasons:
402 *
403 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
404 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
405 * multiple interfaces.
406 *
407 * 2) The databook does not mention doing more DEPXFERCFG for new
408 * endpoint on alt setting (8.1.6).
409 *
410 * The following simplified method is used instead:
411 *
412 * All hardware endpoints can be assigned a transfer resource and this
413 * setting will stay persistent until either a core reset or
414 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
415 * do DEPXFERCFG for every hardware endpoint as well. We are
416 * guaranteed that there are as many transfer resources as endpoints.
417 *
418 * This function is called for each endpoint when it is being enabled
419 * but is triggered only when called for EP0-out, which always happens
420 * first, and which should only happen in one of the above conditions.
421 */
422static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
423{
424 struct dwc3_gadget_ep_cmd_params params;
425 u32 cmd;
426 int i;
427 int ret;
428
429 if (dep->number)
430 return 0;
431
432 memset(¶ms, 0x00, sizeof(params));
433 cmd = DWC3_DEPCMD_DEPSTARTCFG;
434
435 ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
436 if (ret)
437 return ret;
438
439 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
440 struct dwc3_ep *dep = dwc->eps[i];
441
442 if (!dep)
443 continue;
444
445 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
446 if (ret)
447 return ret;
448 }
449
450 return 0;
451}
452
453static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
454 const struct usb_endpoint_descriptor *desc,
455 const struct usb_ss_ep_comp_descriptor *comp_desc,
456 bool ignore, bool restore)
457{
458 struct dwc3_gadget_ep_cmd_params params;
459
460 memset(¶ms, 0x00, sizeof(params));
461
462 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
463 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
464
465 /* Burst size is only needed in SuperSpeed mode */
466 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
467 u32 burst = dep->endpoint.maxburst - 1;
468
469 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
470 }
471
472 if (ignore)
473 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
474
475 if (restore) {
476 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
477 params.param2 |= dep->saved_state;
478 }
479
480 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
481 | DWC3_DEPCFG_XFER_NOT_READY_EN;
482
483 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
484 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
485 | DWC3_DEPCFG_STREAM_EVENT_EN;
486 dep->stream_capable = true;
487 }
488
489 if (!usb_endpoint_xfer_control(desc))
490 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
491
492 /*
493 * We are doing 1:1 mapping for endpoints, meaning
494 * Physical Endpoints 2 maps to Logical Endpoint 2 and
495 * so on. We consider the direction bit as part of the physical
496 * endpoint number. So USB endpoint 0x81 is 0x03.
497 */
498 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
499
500 /*
501 * We must use the lower 16 TX FIFOs even though
502 * HW might have more
503 */
504 if (dep->direction)
505 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
506
507 if (desc->bInterval) {
508 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
509 dep->interval = 1 << (desc->bInterval - 1);
510 }
511
512 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
513 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
514}
515
516static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
517{
518 struct dwc3_gadget_ep_cmd_params params;
519
520 memset(¶ms, 0x00, sizeof(params));
521
522 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
523
524 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
525 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
526}
527
528/**
529 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
530 * @dep: endpoint to be initialized
531 * @desc: USB Endpoint Descriptor
532 *
533 * Caller should take care of locking
534 */
535static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
536 const struct usb_endpoint_descriptor *desc,
537 const struct usb_ss_ep_comp_descriptor *comp_desc,
538 bool ignore, bool restore)
539{
540 struct dwc3 *dwc = dep->dwc;
541 u32 reg;
542 int ret;
543
544 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
545
546 if (!(dep->flags & DWC3_EP_ENABLED)) {
547 ret = dwc3_gadget_start_config(dwc, dep);
548 if (ret)
549 return ret;
550 }
551
552 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
553 restore);
554 if (ret)
555 return ret;
556
557 if (!(dep->flags & DWC3_EP_ENABLED)) {
558 struct dwc3_trb *trb_st_hw;
559 struct dwc3_trb *trb_link;
560
561 dep->endpoint.desc = desc;
562 dep->comp_desc = comp_desc;
563 dep->type = usb_endpoint_type(desc);
564 dep->flags |= DWC3_EP_ENABLED;
565
566 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
567 reg |= DWC3_DALEPENA_EP(dep->number);
568 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
569
570 if (!usb_endpoint_xfer_isoc(desc))
571 goto out;
572
573 /* Link TRB for ISOC. The HWO bit is never reset */
574 trb_st_hw = &dep->trb_pool[0];
575
576 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
577 memset(trb_link, 0, sizeof(*trb_link));
578
579 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
580 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
581 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
582 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
583 }
584
585out:
586 switch (usb_endpoint_type(desc)) {
587 case USB_ENDPOINT_XFER_CONTROL:
588 /* don't change name */
589 break;
590 case USB_ENDPOINT_XFER_ISOC:
591 strlcat(dep->name, "-isoc", sizeof(dep->name));
592 break;
593 case USB_ENDPOINT_XFER_BULK:
594 strlcat(dep->name, "-bulk", sizeof(dep->name));
595 break;
596 case USB_ENDPOINT_XFER_INT:
597 strlcat(dep->name, "-int", sizeof(dep->name));
598 break;
599 default:
600 dev_err(dwc->dev, "invalid endpoint transfer type\n");
601 }
602
603 return 0;
604}
605
606static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
607static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
608{
609 struct dwc3_request *req;
610
611 if (!list_empty(&dep->req_queued)) {
612 dwc3_stop_active_transfer(dwc, dep->number, true);
613
614 /* - giveback all requests to gadget driver */
615 while (!list_empty(&dep->req_queued)) {
616 req = next_request(&dep->req_queued);
617
618 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
619 }
620 }
621
622 while (!list_empty(&dep->request_list)) {
623 req = next_request(&dep->request_list);
624
625 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
626 }
627}
628
629/**
630 * __dwc3_gadget_ep_disable - Disables a HW endpoint
631 * @dep: the endpoint to disable
632 *
633 * This function also removes requests which are currently processed ny the
634 * hardware and those which are not yet scheduled.
635 * Caller should take care of locking.
636 */
637static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
638{
639 struct dwc3 *dwc = dep->dwc;
640 u32 reg;
641
642 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
643
644 dwc3_remove_requests(dwc, dep);
645
646 /* make sure HW endpoint isn't stalled */
647 if (dep->flags & DWC3_EP_STALL)
648 __dwc3_gadget_ep_set_halt(dep, 0, false);
649
650 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
651 reg &= ~DWC3_DALEPENA_EP(dep->number);
652 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
653
654 dep->stream_capable = false;
655 dep->endpoint.desc = NULL;
656 dep->comp_desc = NULL;
657 dep->type = 0;
658 dep->flags = 0;
659
660 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
661 dep->number >> 1,
662 (dep->number & 1) ? "in" : "out");
663
664 return 0;
665}
666
667/* -------------------------------------------------------------------------- */
668
669static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
670 const struct usb_endpoint_descriptor *desc)
671{
672 return -EINVAL;
673}
674
675static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
676{
677 return -EINVAL;
678}
679
680/* -------------------------------------------------------------------------- */
681
682static int dwc3_gadget_ep_enable(struct usb_ep *ep,
683 const struct usb_endpoint_descriptor *desc)
684{
685 struct dwc3_ep *dep;
686 struct dwc3 *dwc;
687 unsigned long flags;
688 int ret;
689
690 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
691 pr_debug("dwc3: invalid parameters\n");
692 return -EINVAL;
693 }
694
695 if (!desc->wMaxPacketSize) {
696 pr_debug("dwc3: missing wMaxPacketSize\n");
697 return -EINVAL;
698 }
699
700 dep = to_dwc3_ep(ep);
701 dwc = dep->dwc;
702
703 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
704 "%s is already enabled\n",
705 dep->name))
706 return 0;
707
708 spin_lock_irqsave(&dwc->lock, flags);
709 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
710 spin_unlock_irqrestore(&dwc->lock, flags);
711
712 return ret;
713}
714
715static int dwc3_gadget_ep_disable(struct usb_ep *ep)
716{
717 struct dwc3_ep *dep;
718 struct dwc3 *dwc;
719 unsigned long flags;
720 int ret;
721
722 if (!ep) {
723 pr_debug("dwc3: invalid parameters\n");
724 return -EINVAL;
725 }
726
727 dep = to_dwc3_ep(ep);
728 dwc = dep->dwc;
729
730 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
731 "%s is already disabled\n",
732 dep->name))
733 return 0;
734
735 spin_lock_irqsave(&dwc->lock, flags);
736 ret = __dwc3_gadget_ep_disable(dep);
737 spin_unlock_irqrestore(&dwc->lock, flags);
738
739 return ret;
740}
741
742static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
743 gfp_t gfp_flags)
744{
745 struct dwc3_request *req;
746 struct dwc3_ep *dep = to_dwc3_ep(ep);
747
748 req = kzalloc(sizeof(*req), gfp_flags);
749 if (!req)
750 return NULL;
751
752 req->epnum = dep->number;
753 req->dep = dep;
754
755 trace_dwc3_alloc_request(req);
756
757 return &req->request;
758}
759
760static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
761 struct usb_request *request)
762{
763 struct dwc3_request *req = to_dwc3_request(request);
764
765 trace_dwc3_free_request(req);
766 kfree(req);
767}
768
769/**
770 * dwc3_prepare_one_trb - setup one TRB from one request
771 * @dep: endpoint for which this request is prepared
772 * @req: dwc3_request pointer
773 */
774static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
775 struct dwc3_request *req, dma_addr_t dma,
776 unsigned length, unsigned last, unsigned chain, unsigned node)
777{
778 struct dwc3_trb *trb;
779
780 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
781 dep->name, req, (unsigned long long) dma,
782 length, last ? " last" : "",
783 chain ? " chain" : "");
784
785
786 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
787
788 if (!req->trb) {
789 dwc3_gadget_move_request_queued(req);
790 req->trb = trb;
791 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
792 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
793 }
794
795 dep->free_slot++;
796 /* Skip the LINK-TRB on ISOC */
797 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
798 usb_endpoint_xfer_isoc(dep->endpoint.desc))
799 dep->free_slot++;
800
801 trb->size = DWC3_TRB_SIZE_LENGTH(length);
802 trb->bpl = lower_32_bits(dma);
803 trb->bph = upper_32_bits(dma);
804
805 switch (usb_endpoint_type(dep->endpoint.desc)) {
806 case USB_ENDPOINT_XFER_CONTROL:
807 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
808 break;
809
810 case USB_ENDPOINT_XFER_ISOC:
811 if (!node)
812 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
813 else
814 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
815 break;
816
817 case USB_ENDPOINT_XFER_BULK:
818 case USB_ENDPOINT_XFER_INT:
819 trb->ctrl = DWC3_TRBCTL_NORMAL;
820 break;
821 default:
822 /*
823 * This is only possible with faulty memory because we
824 * checked it already :)
825 */
826 BUG();
827 }
828
829 if (!req->request.no_interrupt && !chain)
830 trb->ctrl |= DWC3_TRB_CTRL_IOC;
831
832 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
833 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
834 trb->ctrl |= DWC3_TRB_CTRL_CSP;
835 } else if (last) {
836 trb->ctrl |= DWC3_TRB_CTRL_LST;
837 }
838
839 if (chain)
840 trb->ctrl |= DWC3_TRB_CTRL_CHN;
841
842 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
843 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
844
845 trb->ctrl |= DWC3_TRB_CTRL_HWO;
846
847 trace_dwc3_prepare_trb(dep, trb);
848}
849
850/*
851 * dwc3_prepare_trbs - setup TRBs from requests
852 * @dep: endpoint for which requests are being prepared
853 * @starting: true if the endpoint is idle and no requests are queued.
854 *
855 * The function goes through the requests list and sets up TRBs for the
856 * transfers. The function returns once there are no more TRBs available or
857 * it runs out of requests.
858 */
859static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
860{
861 struct dwc3_request *req, *n;
862 u32 trbs_left;
863 u32 max;
864 unsigned int last_one = 0;
865
866 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
867
868 /* the first request must not be queued */
869 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
870
871 /* Can't wrap around on a non-isoc EP since there's no link TRB */
872 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
873 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
874 if (trbs_left > max)
875 trbs_left = max;
876 }
877
878 /*
879 * If busy & slot are equal than it is either full or empty. If we are
880 * starting to process requests then we are empty. Otherwise we are
881 * full and don't do anything
882 */
883 if (!trbs_left) {
884 if (!starting)
885 return;
886 trbs_left = DWC3_TRB_NUM;
887 /*
888 * In case we start from scratch, we queue the ISOC requests
889 * starting from slot 1. This is done because we use ring
890 * buffer and have no LST bit to stop us. Instead, we place
891 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
892 * after the first request so we start at slot 1 and have
893 * 7 requests proceed before we hit the first IOC.
894 * Other transfer types don't use the ring buffer and are
895 * processed from the first TRB until the last one. Since we
896 * don't wrap around we have to start at the beginning.
897 */
898 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
899 dep->busy_slot = 1;
900 dep->free_slot = 1;
901 } else {
902 dep->busy_slot = 0;
903 dep->free_slot = 0;
904 }
905 }
906
907 /* The last TRB is a link TRB, not used for xfer */
908 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
909 return;
910
911 list_for_each_entry_safe(req, n, &dep->request_list, list) {
912 unsigned length;
913 dma_addr_t dma;
914 last_one = false;
915
916 if (req->request.num_mapped_sgs > 0) {
917 struct usb_request *request = &req->request;
918 struct scatterlist *sg = request->sg;
919 struct scatterlist *s;
920 int i;
921
922 for_each_sg(sg, s, request->num_mapped_sgs, i) {
923 unsigned chain = true;
924
925 length = sg_dma_len(s);
926 dma = sg_dma_address(s);
927
928 if (i == (request->num_mapped_sgs - 1) ||
929 sg_is_last(s)) {
930 if (list_empty(&dep->request_list))
931 last_one = true;
932 chain = false;
933 }
934
935 trbs_left--;
936 if (!trbs_left)
937 last_one = true;
938
939 if (last_one)
940 chain = false;
941
942 dwc3_prepare_one_trb(dep, req, dma, length,
943 last_one, chain, i);
944
945 if (last_one)
946 break;
947 }
948
949 if (last_one)
950 break;
951 } else {
952 dma = req->request.dma;
953 length = req->request.length;
954 trbs_left--;
955
956 if (!trbs_left)
957 last_one = 1;
958
959 /* Is this the last request? */
960 if (list_is_last(&req->list, &dep->request_list))
961 last_one = 1;
962
963 dwc3_prepare_one_trb(dep, req, dma, length,
964 last_one, false, 0);
965
966 if (last_one)
967 break;
968 }
969 }
970}
971
972static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
973 int start_new)
974{
975 struct dwc3_gadget_ep_cmd_params params;
976 struct dwc3_request *req;
977 struct dwc3 *dwc = dep->dwc;
978 int ret;
979 u32 cmd;
980
981 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
982 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
983 return -EBUSY;
984 }
985
986 /*
987 * If we are getting here after a short-out-packet we don't enqueue any
988 * new requests as we try to set the IOC bit only on the last request.
989 */
990 if (start_new) {
991 if (list_empty(&dep->req_queued))
992 dwc3_prepare_trbs(dep, start_new);
993
994 /* req points to the first request which will be sent */
995 req = next_request(&dep->req_queued);
996 } else {
997 dwc3_prepare_trbs(dep, start_new);
998
999 /*
1000 * req points to the first request where HWO changed from 0 to 1
1001 */
1002 req = next_request(&dep->req_queued);
1003 }
1004 if (!req) {
1005 dep->flags |= DWC3_EP_PENDING_REQUEST;
1006 return 0;
1007 }
1008
1009 memset(¶ms, 0, sizeof(params));
1010
1011 if (start_new) {
1012 params.param0 = upper_32_bits(req->trb_dma);
1013 params.param1 = lower_32_bits(req->trb_dma);
1014 cmd = DWC3_DEPCMD_STARTTRANSFER;
1015 } else {
1016 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1017 }
1018
1019 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1020 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1021 if (ret < 0) {
1022 /*
1023 * FIXME we need to iterate over the list of requests
1024 * here and stop, unmap, free and del each of the linked
1025 * requests instead of what we do now.
1026 */
1027 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1028 req->direction);
1029 list_del(&req->list);
1030 return ret;
1031 }
1032
1033 dep->flags |= DWC3_EP_BUSY;
1034
1035 if (start_new) {
1036 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1037 dep->number);
1038 WARN_ON_ONCE(!dep->resource_index);
1039 }
1040
1041 return 0;
1042}
1043
1044static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1045 struct dwc3_ep *dep, u32 cur_uf)
1046{
1047 u32 uf;
1048
1049 if (list_empty(&dep->request_list)) {
1050 dwc3_trace(trace_dwc3_gadget,
1051 "ISOC ep %s run out for requests",
1052 dep->name);
1053 dep->flags |= DWC3_EP_PENDING_REQUEST;
1054 return;
1055 }
1056
1057 /* 4 micro frames in the future */
1058 uf = cur_uf + dep->interval * 4;
1059
1060 __dwc3_gadget_kick_transfer(dep, uf, 1);
1061}
1062
1063static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1064 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1065{
1066 u32 cur_uf, mask;
1067
1068 mask = ~(dep->interval - 1);
1069 cur_uf = event->parameters & mask;
1070
1071 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1072}
1073
1074static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1075{
1076 struct dwc3 *dwc = dep->dwc;
1077 int ret;
1078
1079 if (!dep->endpoint.desc) {
1080 dwc3_trace(trace_dwc3_gadget,
1081 "trying to queue request %p to disabled %s\n",
1082 &req->request, dep->endpoint.name);
1083 return -ESHUTDOWN;
1084 }
1085
1086 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1087 &req->request, req->dep->name)) {
1088 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1089 &req->request, req->dep->name);
1090 return -EINVAL;
1091 }
1092
1093 req->request.actual = 0;
1094 req->request.status = -EINPROGRESS;
1095 req->direction = dep->direction;
1096 req->epnum = dep->number;
1097
1098 trace_dwc3_ep_queue(req);
1099
1100 /*
1101 * We only add to our list of requests now and
1102 * start consuming the list once we get XferNotReady
1103 * IRQ.
1104 *
1105 * That way, we avoid doing anything that we don't need
1106 * to do now and defer it until the point we receive a
1107 * particular token from the Host side.
1108 *
1109 * This will also avoid Host cancelling URBs due to too
1110 * many NAKs.
1111 */
1112 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1113 dep->direction);
1114 if (ret)
1115 return ret;
1116
1117 list_add_tail(&req->list, &dep->request_list);
1118
1119 /*
1120 * If there are no pending requests and the endpoint isn't already
1121 * busy, we will just start the request straight away.
1122 *
1123 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1124 * little bit faster.
1125 */
1126 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1127 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1128 !(dep->flags & DWC3_EP_BUSY)) {
1129 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1130 goto out;
1131 }
1132
1133 /*
1134 * There are a few special cases:
1135 *
1136 * 1. XferNotReady with empty list of requests. We need to kick the
1137 * transfer here in that situation, otherwise we will be NAKing
1138 * forever. If we get XferNotReady before gadget driver has a
1139 * chance to queue a request, we will ACK the IRQ but won't be
1140 * able to receive the data until the next request is queued.
1141 * The following code is handling exactly that.
1142 *
1143 */
1144 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1145 /*
1146 * If xfernotready is already elapsed and it is a case
1147 * of isoc transfer, then issue END TRANSFER, so that
1148 * you can receive xfernotready again and can have
1149 * notion of current microframe.
1150 */
1151 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1152 if (list_empty(&dep->req_queued)) {
1153 dwc3_stop_active_transfer(dwc, dep->number, true);
1154 dep->flags = DWC3_EP_ENABLED;
1155 }
1156 return 0;
1157 }
1158
1159 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1160 if (!ret)
1161 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1162
1163 goto out;
1164 }
1165
1166 /*
1167 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1168 * kick the transfer here after queuing a request, otherwise the
1169 * core may not see the modified TRB(s).
1170 */
1171 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1172 (dep->flags & DWC3_EP_BUSY) &&
1173 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1174 WARN_ON_ONCE(!dep->resource_index);
1175 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1176 false);
1177 goto out;
1178 }
1179
1180 /*
1181 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1182 * right away, otherwise host will not know we have streams to be
1183 * handled.
1184 */
1185 if (dep->stream_capable)
1186 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1187
1188out:
1189 if (ret && ret != -EBUSY)
1190 dwc3_trace(trace_dwc3_gadget,
1191 "%s: failed to kick transfers\n",
1192 dep->name);
1193 if (ret == -EBUSY)
1194 ret = 0;
1195
1196 return ret;
1197}
1198
1199static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1200 struct usb_request *request)
1201{
1202 dwc3_gadget_ep_free_request(ep, request);
1203}
1204
1205static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1206{
1207 struct dwc3_request *req;
1208 struct usb_request *request;
1209 struct usb_ep *ep = &dep->endpoint;
1210
1211 dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1212 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1213 if (!request)
1214 return -ENOMEM;
1215
1216 request->length = 0;
1217 request->buf = dwc->zlp_buf;
1218 request->complete = __dwc3_gadget_ep_zlp_complete;
1219
1220 req = to_dwc3_request(request);
1221
1222 return __dwc3_gadget_ep_queue(dep, req);
1223}
1224
1225static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1226 gfp_t gfp_flags)
1227{
1228 struct dwc3_request *req = to_dwc3_request(request);
1229 struct dwc3_ep *dep = to_dwc3_ep(ep);
1230 struct dwc3 *dwc = dep->dwc;
1231
1232 unsigned long flags;
1233
1234 int ret;
1235
1236 spin_lock_irqsave(&dwc->lock, flags);
1237 ret = __dwc3_gadget_ep_queue(dep, req);
1238
1239 /*
1240 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1241 * setting request->zero, instead of doing magic, we will just queue an
1242 * extra usb_request ourselves so that it gets handled the same way as
1243 * any other request.
1244 */
1245 if (ret == 0 && request->zero && request->length &&
1246 (request->length % ep->maxpacket == 0))
1247 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1248
1249 spin_unlock_irqrestore(&dwc->lock, flags);
1250
1251 return ret;
1252}
1253
1254static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1255 struct usb_request *request)
1256{
1257 struct dwc3_request *req = to_dwc3_request(request);
1258 struct dwc3_request *r = NULL;
1259
1260 struct dwc3_ep *dep = to_dwc3_ep(ep);
1261 struct dwc3 *dwc = dep->dwc;
1262
1263 unsigned long flags;
1264 int ret = 0;
1265
1266 trace_dwc3_ep_dequeue(req);
1267
1268 spin_lock_irqsave(&dwc->lock, flags);
1269
1270 list_for_each_entry(r, &dep->request_list, list) {
1271 if (r == req)
1272 break;
1273 }
1274
1275 if (r != req) {
1276 list_for_each_entry(r, &dep->req_queued, list) {
1277 if (r == req)
1278 break;
1279 }
1280 if (r == req) {
1281 /* wait until it is processed */
1282 dwc3_stop_active_transfer(dwc, dep->number, true);
1283 goto out1;
1284 }
1285 dev_err(dwc->dev, "request %p was not queued to %s\n",
1286 request, ep->name);
1287 ret = -EINVAL;
1288 goto out0;
1289 }
1290
1291out1:
1292 /* giveback the request */
1293 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1294
1295out0:
1296 spin_unlock_irqrestore(&dwc->lock, flags);
1297
1298 return ret;
1299}
1300
1301int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1302{
1303 struct dwc3_gadget_ep_cmd_params params;
1304 struct dwc3 *dwc = dep->dwc;
1305 int ret;
1306
1307 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1308 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1309 return -EINVAL;
1310 }
1311
1312 memset(¶ms, 0x00, sizeof(params));
1313
1314 if (value) {
1315 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1316 (!list_empty(&dep->req_queued) ||
1317 !list_empty(&dep->request_list)))) {
1318 dwc3_trace(trace_dwc3_gadget,
1319 "%s: pending request, cannot halt\n",
1320 dep->name);
1321 return -EAGAIN;
1322 }
1323
1324 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1325 DWC3_DEPCMD_SETSTALL, ¶ms);
1326 if (ret)
1327 dev_err(dwc->dev, "failed to set STALL on %s\n",
1328 dep->name);
1329 else
1330 dep->flags |= DWC3_EP_STALL;
1331 } else {
1332 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1333 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1334 if (ret)
1335 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1336 dep->name);
1337 else
1338 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1339 }
1340
1341 return ret;
1342}
1343
1344static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1345{
1346 struct dwc3_ep *dep = to_dwc3_ep(ep);
1347 struct dwc3 *dwc = dep->dwc;
1348
1349 unsigned long flags;
1350
1351 int ret;
1352
1353 spin_lock_irqsave(&dwc->lock, flags);
1354 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1355 spin_unlock_irqrestore(&dwc->lock, flags);
1356
1357 return ret;
1358}
1359
1360static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1361{
1362 struct dwc3_ep *dep = to_dwc3_ep(ep);
1363 struct dwc3 *dwc = dep->dwc;
1364 unsigned long flags;
1365 int ret;
1366
1367 spin_lock_irqsave(&dwc->lock, flags);
1368 dep->flags |= DWC3_EP_WEDGE;
1369
1370 if (dep->number == 0 || dep->number == 1)
1371 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1372 else
1373 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1374 spin_unlock_irqrestore(&dwc->lock, flags);
1375
1376 return ret;
1377}
1378
1379/* -------------------------------------------------------------------------- */
1380
1381static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1382 .bLength = USB_DT_ENDPOINT_SIZE,
1383 .bDescriptorType = USB_DT_ENDPOINT,
1384 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1385};
1386
1387static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1388 .enable = dwc3_gadget_ep0_enable,
1389 .disable = dwc3_gadget_ep0_disable,
1390 .alloc_request = dwc3_gadget_ep_alloc_request,
1391 .free_request = dwc3_gadget_ep_free_request,
1392 .queue = dwc3_gadget_ep0_queue,
1393 .dequeue = dwc3_gadget_ep_dequeue,
1394 .set_halt = dwc3_gadget_ep0_set_halt,
1395 .set_wedge = dwc3_gadget_ep_set_wedge,
1396};
1397
1398static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1399 .enable = dwc3_gadget_ep_enable,
1400 .disable = dwc3_gadget_ep_disable,
1401 .alloc_request = dwc3_gadget_ep_alloc_request,
1402 .free_request = dwc3_gadget_ep_free_request,
1403 .queue = dwc3_gadget_ep_queue,
1404 .dequeue = dwc3_gadget_ep_dequeue,
1405 .set_halt = dwc3_gadget_ep_set_halt,
1406 .set_wedge = dwc3_gadget_ep_set_wedge,
1407};
1408
1409/* -------------------------------------------------------------------------- */
1410
1411static int dwc3_gadget_get_frame(struct usb_gadget *g)
1412{
1413 struct dwc3 *dwc = gadget_to_dwc(g);
1414 u32 reg;
1415
1416 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1417 return DWC3_DSTS_SOFFN(reg);
1418}
1419
1420static int dwc3_gadget_wakeup(struct usb_gadget *g)
1421{
1422 struct dwc3 *dwc = gadget_to_dwc(g);
1423
1424 unsigned long timeout;
1425 unsigned long flags;
1426
1427 u32 reg;
1428
1429 int ret = 0;
1430
1431 u8 link_state;
1432 u8 speed;
1433
1434 spin_lock_irqsave(&dwc->lock, flags);
1435
1436 /*
1437 * According to the Databook Remote wakeup request should
1438 * be issued only when the device is in early suspend state.
1439 *
1440 * We can check that via USB Link State bits in DSTS register.
1441 */
1442 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1443
1444 speed = reg & DWC3_DSTS_CONNECTSPD;
1445 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1446 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1447 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1448 ret = -EINVAL;
1449 goto out;
1450 }
1451
1452 link_state = DWC3_DSTS_USBLNKST(reg);
1453
1454 switch (link_state) {
1455 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1456 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1457 break;
1458 default:
1459 dwc3_trace(trace_dwc3_gadget,
1460 "can't wakeup from '%s'\n",
1461 dwc3_gadget_link_string(link_state));
1462 ret = -EINVAL;
1463 goto out;
1464 }
1465
1466 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1467 if (ret < 0) {
1468 dev_err(dwc->dev, "failed to put link in Recovery\n");
1469 goto out;
1470 }
1471
1472 /* Recent versions do this automatically */
1473 if (dwc->revision < DWC3_REVISION_194A) {
1474 /* write zeroes to Link Change Request */
1475 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1476 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1477 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1478 }
1479
1480 /* poll until Link State changes to ON */
1481 timeout = jiffies + msecs_to_jiffies(100);
1482
1483 while (!time_after(jiffies, timeout)) {
1484 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1485
1486 /* in HS, means ON */
1487 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1488 break;
1489 }
1490
1491 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1492 dev_err(dwc->dev, "failed to send remote wakeup\n");
1493 ret = -EINVAL;
1494 }
1495
1496out:
1497 spin_unlock_irqrestore(&dwc->lock, flags);
1498
1499 return ret;
1500}
1501
1502static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1503 int is_selfpowered)
1504{
1505 struct dwc3 *dwc = gadget_to_dwc(g);
1506 unsigned long flags;
1507
1508 spin_lock_irqsave(&dwc->lock, flags);
1509 g->is_selfpowered = !!is_selfpowered;
1510 spin_unlock_irqrestore(&dwc->lock, flags);
1511
1512 return 0;
1513}
1514
1515static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1516{
1517 u32 reg;
1518 u32 timeout = 500;
1519
1520 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1521 if (is_on) {
1522 if (dwc->revision <= DWC3_REVISION_187A) {
1523 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1524 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1525 }
1526
1527 if (dwc->revision >= DWC3_REVISION_194A)
1528 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1529 reg |= DWC3_DCTL_RUN_STOP;
1530
1531 if (dwc->has_hibernation)
1532 reg |= DWC3_DCTL_KEEP_CONNECT;
1533
1534 dwc->pullups_connected = true;
1535 } else {
1536 reg &= ~DWC3_DCTL_RUN_STOP;
1537
1538 if (dwc->has_hibernation && !suspend)
1539 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1540
1541 dwc->pullups_connected = false;
1542 }
1543
1544 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1545
1546 do {
1547 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1548 if (is_on) {
1549 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1550 break;
1551 } else {
1552 if (reg & DWC3_DSTS_DEVCTRLHLT)
1553 break;
1554 }
1555 timeout--;
1556 if (!timeout)
1557 return -ETIMEDOUT;
1558 udelay(1);
1559 } while (1);
1560
1561 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1562 dwc->gadget_driver
1563 ? dwc->gadget_driver->function : "no-function",
1564 is_on ? "connect" : "disconnect");
1565
1566 return 0;
1567}
1568
1569static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1570{
1571 struct dwc3 *dwc = gadget_to_dwc(g);
1572 unsigned long flags;
1573 int ret;
1574
1575 is_on = !!is_on;
1576
1577 spin_lock_irqsave(&dwc->lock, flags);
1578 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1579 spin_unlock_irqrestore(&dwc->lock, flags);
1580
1581 return ret;
1582}
1583
1584static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1585{
1586 u32 reg;
1587
1588 /* Enable all but Start and End of Frame IRQs */
1589 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1590 DWC3_DEVTEN_EVNTOVERFLOWEN |
1591 DWC3_DEVTEN_CMDCMPLTEN |
1592 DWC3_DEVTEN_ERRTICERREN |
1593 DWC3_DEVTEN_WKUPEVTEN |
1594 DWC3_DEVTEN_ULSTCNGEN |
1595 DWC3_DEVTEN_CONNECTDONEEN |
1596 DWC3_DEVTEN_USBRSTEN |
1597 DWC3_DEVTEN_DISCONNEVTEN);
1598
1599 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1600}
1601
1602static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1603{
1604 /* mask all interrupts */
1605 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1606}
1607
1608static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1609static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1610
1611static int dwc3_gadget_start(struct usb_gadget *g,
1612 struct usb_gadget_driver *driver)
1613{
1614 struct dwc3 *dwc = gadget_to_dwc(g);
1615 struct dwc3_ep *dep;
1616 unsigned long flags;
1617 int ret = 0;
1618 int irq;
1619 u32 reg;
1620
1621 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1622 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1623 IRQF_SHARED, "dwc3", dwc);
1624 if (ret) {
1625 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1626 irq, ret);
1627 goto err0;
1628 }
1629
1630 spin_lock_irqsave(&dwc->lock, flags);
1631
1632 if (dwc->gadget_driver) {
1633 dev_err(dwc->dev, "%s is already bound to %s\n",
1634 dwc->gadget.name,
1635 dwc->gadget_driver->driver.name);
1636 ret = -EBUSY;
1637 goto err1;
1638 }
1639
1640 dwc->gadget_driver = driver;
1641
1642 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1643 reg &= ~(DWC3_DCFG_SPEED_MASK);
1644
1645 /**
1646 * WORKAROUND: DWC3 revision < 2.20a have an issue
1647 * which would cause metastability state on Run/Stop
1648 * bit if we try to force the IP to USB2-only mode.
1649 *
1650 * Because of that, we cannot configure the IP to any
1651 * speed other than the SuperSpeed
1652 *
1653 * Refers to:
1654 *
1655 * STAR#9000525659: Clock Domain Crossing on DCTL in
1656 * USB 2.0 Mode
1657 */
1658 if (dwc->revision < DWC3_REVISION_220A) {
1659 reg |= DWC3_DCFG_SUPERSPEED;
1660 } else {
1661 switch (dwc->maximum_speed) {
1662 case USB_SPEED_LOW:
1663 reg |= DWC3_DSTS_LOWSPEED;
1664 break;
1665 case USB_SPEED_FULL:
1666 reg |= DWC3_DSTS_FULLSPEED1;
1667 break;
1668 case USB_SPEED_HIGH:
1669 reg |= DWC3_DSTS_HIGHSPEED;
1670 break;
1671 case USB_SPEED_SUPER_PLUS:
1672 reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1673 break;
1674 default:
1675 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1676 dwc->maximum_speed);
1677 /* fall through */
1678 case USB_SPEED_SUPER:
1679 reg |= DWC3_DCFG_SUPERSPEED;
1680 break;
1681 }
1682 }
1683 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1684
1685 /* Start with SuperSpeed Default */
1686 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1687
1688 dep = dwc->eps[0];
1689 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1690 false);
1691 if (ret) {
1692 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1693 goto err2;
1694 }
1695
1696 dep = dwc->eps[1];
1697 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1698 false);
1699 if (ret) {
1700 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1701 goto err3;
1702 }
1703
1704 /* begin to receive SETUP packets */
1705 dwc->ep0state = EP0_SETUP_PHASE;
1706 dwc3_ep0_out_start(dwc);
1707
1708 dwc3_gadget_enable_irq(dwc);
1709
1710 spin_unlock_irqrestore(&dwc->lock, flags);
1711
1712 return 0;
1713
1714err3:
1715 __dwc3_gadget_ep_disable(dwc->eps[0]);
1716
1717err2:
1718 dwc->gadget_driver = NULL;
1719
1720err1:
1721 spin_unlock_irqrestore(&dwc->lock, flags);
1722
1723 free_irq(irq, dwc);
1724
1725err0:
1726 return ret;
1727}
1728
1729static int dwc3_gadget_stop(struct usb_gadget *g)
1730{
1731 struct dwc3 *dwc = gadget_to_dwc(g);
1732 unsigned long flags;
1733 int irq;
1734
1735 spin_lock_irqsave(&dwc->lock, flags);
1736
1737 dwc3_gadget_disable_irq(dwc);
1738 __dwc3_gadget_ep_disable(dwc->eps[0]);
1739 __dwc3_gadget_ep_disable(dwc->eps[1]);
1740
1741 dwc->gadget_driver = NULL;
1742
1743 spin_unlock_irqrestore(&dwc->lock, flags);
1744
1745 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1746 free_irq(irq, dwc);
1747
1748 return 0;
1749}
1750
1751static const struct usb_gadget_ops dwc3_gadget_ops = {
1752 .get_frame = dwc3_gadget_get_frame,
1753 .wakeup = dwc3_gadget_wakeup,
1754 .set_selfpowered = dwc3_gadget_set_selfpowered,
1755 .pullup = dwc3_gadget_pullup,
1756 .udc_start = dwc3_gadget_start,
1757 .udc_stop = dwc3_gadget_stop,
1758};
1759
1760/* -------------------------------------------------------------------------- */
1761
1762static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1763 u8 num, u32 direction)
1764{
1765 struct dwc3_ep *dep;
1766 u8 i;
1767
1768 for (i = 0; i < num; i++) {
1769 u8 epnum = (i << 1) | (!!direction);
1770
1771 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1772 if (!dep)
1773 return -ENOMEM;
1774
1775 dep->dwc = dwc;
1776 dep->number = epnum;
1777 dep->direction = !!direction;
1778 dwc->eps[epnum] = dep;
1779
1780 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1781 (epnum & 1) ? "in" : "out");
1782
1783 dep->endpoint.name = dep->name;
1784
1785 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1786
1787 if (epnum == 0 || epnum == 1) {
1788 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1789 dep->endpoint.maxburst = 1;
1790 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1791 if (!epnum)
1792 dwc->gadget.ep0 = &dep->endpoint;
1793 } else {
1794 int ret;
1795
1796 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1797 dep->endpoint.max_streams = 15;
1798 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1799 list_add_tail(&dep->endpoint.ep_list,
1800 &dwc->gadget.ep_list);
1801
1802 ret = dwc3_alloc_trb_pool(dep);
1803 if (ret)
1804 return ret;
1805 }
1806
1807 if (epnum == 0 || epnum == 1) {
1808 dep->endpoint.caps.type_control = true;
1809 } else {
1810 dep->endpoint.caps.type_iso = true;
1811 dep->endpoint.caps.type_bulk = true;
1812 dep->endpoint.caps.type_int = true;
1813 }
1814
1815 dep->endpoint.caps.dir_in = !!direction;
1816 dep->endpoint.caps.dir_out = !direction;
1817
1818 INIT_LIST_HEAD(&dep->request_list);
1819 INIT_LIST_HEAD(&dep->req_queued);
1820 }
1821
1822 return 0;
1823}
1824
1825static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1826{
1827 int ret;
1828
1829 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1830
1831 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1832 if (ret < 0) {
1833 dwc3_trace(trace_dwc3_gadget,
1834 "failed to allocate OUT endpoints");
1835 return ret;
1836 }
1837
1838 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1839 if (ret < 0) {
1840 dwc3_trace(trace_dwc3_gadget,
1841 "failed to allocate IN endpoints");
1842 return ret;
1843 }
1844
1845 return 0;
1846}
1847
1848static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1849{
1850 struct dwc3_ep *dep;
1851 u8 epnum;
1852
1853 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1854 dep = dwc->eps[epnum];
1855 if (!dep)
1856 continue;
1857 /*
1858 * Physical endpoints 0 and 1 are special; they form the
1859 * bi-directional USB endpoint 0.
1860 *
1861 * For those two physical endpoints, we don't allocate a TRB
1862 * pool nor do we add them the endpoints list. Due to that, we
1863 * shouldn't do these two operations otherwise we would end up
1864 * with all sorts of bugs when removing dwc3.ko.
1865 */
1866 if (epnum != 0 && epnum != 1) {
1867 dwc3_free_trb_pool(dep);
1868 list_del(&dep->endpoint.ep_list);
1869 }
1870
1871 kfree(dep);
1872 }
1873}
1874
1875/* -------------------------------------------------------------------------- */
1876
1877static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1878 struct dwc3_request *req, struct dwc3_trb *trb,
1879 const struct dwc3_event_depevt *event, int status)
1880{
1881 unsigned int count;
1882 unsigned int s_pkt = 0;
1883 unsigned int trb_status;
1884
1885 trace_dwc3_complete_trb(dep, trb);
1886
1887 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1888 /*
1889 * We continue despite the error. There is not much we
1890 * can do. If we don't clean it up we loop forever. If
1891 * we skip the TRB then it gets overwritten after a
1892 * while since we use them in a ring buffer. A BUG()
1893 * would help. Lets hope that if this occurs, someone
1894 * fixes the root cause instead of looking away :)
1895 */
1896 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1897 dep->name, trb);
1898 count = trb->size & DWC3_TRB_SIZE_MASK;
1899
1900 if (dep->direction) {
1901 if (count) {
1902 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1903 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1904 dwc3_trace(trace_dwc3_gadget,
1905 "%s: incomplete IN transfer\n",
1906 dep->name);
1907 /*
1908 * If missed isoc occurred and there is
1909 * no request queued then issue END
1910 * TRANSFER, so that core generates
1911 * next xfernotready and we will issue
1912 * a fresh START TRANSFER.
1913 * If there are still queued request
1914 * then wait, do not issue either END
1915 * or UPDATE TRANSFER, just attach next
1916 * request in request_list during
1917 * giveback.If any future queued request
1918 * is successfully transferred then we
1919 * will issue UPDATE TRANSFER for all
1920 * request in the request_list.
1921 */
1922 dep->flags |= DWC3_EP_MISSED_ISOC;
1923 } else {
1924 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1925 dep->name);
1926 status = -ECONNRESET;
1927 }
1928 } else {
1929 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1930 }
1931 } else {
1932 if (count && (event->status & DEPEVT_STATUS_SHORT))
1933 s_pkt = 1;
1934 }
1935
1936 /*
1937 * We assume here we will always receive the entire data block
1938 * which we should receive. Meaning, if we program RX to
1939 * receive 4K but we receive only 2K, we assume that's all we
1940 * should receive and we simply bounce the request back to the
1941 * gadget driver for further processing.
1942 */
1943 req->request.actual += req->request.length - count;
1944 if (s_pkt)
1945 return 1;
1946 if ((event->status & DEPEVT_STATUS_LST) &&
1947 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1948 DWC3_TRB_CTRL_HWO)))
1949 return 1;
1950 if ((event->status & DEPEVT_STATUS_IOC) &&
1951 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1952 return 1;
1953 return 0;
1954}
1955
1956static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1957 const struct dwc3_event_depevt *event, int status)
1958{
1959 struct dwc3_request *req;
1960 struct dwc3_trb *trb;
1961 unsigned int slot;
1962 unsigned int i;
1963 int ret;
1964
1965 do {
1966 req = next_request(&dep->req_queued);
1967 if (WARN_ON_ONCE(!req))
1968 return 1;
1969
1970 i = 0;
1971 do {
1972 slot = req->start_slot + i;
1973 if ((slot == DWC3_TRB_NUM - 1) &&
1974 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1975 slot++;
1976 slot %= DWC3_TRB_NUM;
1977 trb = &dep->trb_pool[slot];
1978
1979 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1980 event, status);
1981 if (ret)
1982 break;
1983 } while (++i < req->request.num_mapped_sgs);
1984
1985 dwc3_gadget_giveback(dep, req, status);
1986
1987 if (ret)
1988 break;
1989 } while (1);
1990
1991 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1992 list_empty(&dep->req_queued)) {
1993 if (list_empty(&dep->request_list)) {
1994 /*
1995 * If there is no entry in request list then do
1996 * not issue END TRANSFER now. Just set PENDING
1997 * flag, so that END TRANSFER is issued when an
1998 * entry is added into request list.
1999 */
2000 dep->flags = DWC3_EP_PENDING_REQUEST;
2001 } else {
2002 dwc3_stop_active_transfer(dwc, dep->number, true);
2003 dep->flags = DWC3_EP_ENABLED;
2004 }
2005 return 1;
2006 }
2007
2008 return 1;
2009}
2010
2011static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2012 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2013{
2014 unsigned status = 0;
2015 int clean_busy;
2016 u32 is_xfer_complete;
2017
2018 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2019
2020 if (event->status & DEPEVT_STATUS_BUSERR)
2021 status = -ECONNRESET;
2022
2023 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2024 if (clean_busy && (is_xfer_complete ||
2025 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2026 dep->flags &= ~DWC3_EP_BUSY;
2027
2028 /*
2029 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2030 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2031 */
2032 if (dwc->revision < DWC3_REVISION_183A) {
2033 u32 reg;
2034 int i;
2035
2036 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2037 dep = dwc->eps[i];
2038
2039 if (!(dep->flags & DWC3_EP_ENABLED))
2040 continue;
2041
2042 if (!list_empty(&dep->req_queued))
2043 return;
2044 }
2045
2046 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2047 reg |= dwc->u1u2;
2048 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2049
2050 dwc->u1u2 = 0;
2051 }
2052
2053 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2054 int ret;
2055
2056 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2057 if (!ret || ret == -EBUSY)
2058 return;
2059 }
2060}
2061
2062static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2063 const struct dwc3_event_depevt *event)
2064{
2065 struct dwc3_ep *dep;
2066 u8 epnum = event->endpoint_number;
2067
2068 dep = dwc->eps[epnum];
2069
2070 if (!(dep->flags & DWC3_EP_ENABLED))
2071 return;
2072
2073 if (epnum == 0 || epnum == 1) {
2074 dwc3_ep0_interrupt(dwc, event);
2075 return;
2076 }
2077
2078 switch (event->endpoint_event) {
2079 case DWC3_DEPEVT_XFERCOMPLETE:
2080 dep->resource_index = 0;
2081
2082 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2083 dwc3_trace(trace_dwc3_gadget,
2084 "%s is an Isochronous endpoint\n",
2085 dep->name);
2086 return;
2087 }
2088
2089 dwc3_endpoint_transfer_complete(dwc, dep, event);
2090 break;
2091 case DWC3_DEPEVT_XFERINPROGRESS:
2092 dwc3_endpoint_transfer_complete(dwc, dep, event);
2093 break;
2094 case DWC3_DEPEVT_XFERNOTREADY:
2095 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2096 dwc3_gadget_start_isoc(dwc, dep, event);
2097 } else {
2098 int active;
2099 int ret;
2100
2101 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2102
2103 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2104 dep->name, active ? "Transfer Active"
2105 : "Transfer Not Active");
2106
2107 ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2108 if (!ret || ret == -EBUSY)
2109 return;
2110
2111 dwc3_trace(trace_dwc3_gadget,
2112 "%s: failed to kick transfers\n",
2113 dep->name);
2114 }
2115
2116 break;
2117 case DWC3_DEPEVT_STREAMEVT:
2118 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2119 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2120 dep->name);
2121 return;
2122 }
2123
2124 switch (event->status) {
2125 case DEPEVT_STREAMEVT_FOUND:
2126 dwc3_trace(trace_dwc3_gadget,
2127 "Stream %d found and started",
2128 event->parameters);
2129
2130 break;
2131 case DEPEVT_STREAMEVT_NOTFOUND:
2132 /* FALLTHROUGH */
2133 default:
2134 dwc3_trace(trace_dwc3_gadget,
2135 "unable to find suitable stream\n");
2136 }
2137 break;
2138 case DWC3_DEPEVT_RXTXFIFOEVT:
2139 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2140 break;
2141 case DWC3_DEPEVT_EPCMDCMPLT:
2142 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2143 break;
2144 }
2145}
2146
2147static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2148{
2149 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2150 spin_unlock(&dwc->lock);
2151 dwc->gadget_driver->disconnect(&dwc->gadget);
2152 spin_lock(&dwc->lock);
2153 }
2154}
2155
2156static void dwc3_suspend_gadget(struct dwc3 *dwc)
2157{
2158 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2159 spin_unlock(&dwc->lock);
2160 dwc->gadget_driver->suspend(&dwc->gadget);
2161 spin_lock(&dwc->lock);
2162 }
2163}
2164
2165static void dwc3_resume_gadget(struct dwc3 *dwc)
2166{
2167 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2168 spin_unlock(&dwc->lock);
2169 dwc->gadget_driver->resume(&dwc->gadget);
2170 spin_lock(&dwc->lock);
2171 }
2172}
2173
2174static void dwc3_reset_gadget(struct dwc3 *dwc)
2175{
2176 if (!dwc->gadget_driver)
2177 return;
2178
2179 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2180 spin_unlock(&dwc->lock);
2181 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2182 spin_lock(&dwc->lock);
2183 }
2184}
2185
2186static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2187{
2188 struct dwc3_ep *dep;
2189 struct dwc3_gadget_ep_cmd_params params;
2190 u32 cmd;
2191 int ret;
2192
2193 dep = dwc->eps[epnum];
2194
2195 if (!dep->resource_index)
2196 return;
2197
2198 /*
2199 * NOTICE: We are violating what the Databook says about the
2200 * EndTransfer command. Ideally we would _always_ wait for the
2201 * EndTransfer Command Completion IRQ, but that's causing too
2202 * much trouble synchronizing between us and gadget driver.
2203 *
2204 * We have discussed this with the IP Provider and it was
2205 * suggested to giveback all requests here, but give HW some
2206 * extra time to synchronize with the interconnect. We're using
2207 * an arbitrary 100us delay for that.
2208 *
2209 * Note also that a similar handling was tested by Synopsys
2210 * (thanks a lot Paul) and nothing bad has come out of it.
2211 * In short, what we're doing is:
2212 *
2213 * - Issue EndTransfer WITH CMDIOC bit set
2214 * - Wait 100us
2215 */
2216
2217 cmd = DWC3_DEPCMD_ENDTRANSFER;
2218 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2219 cmd |= DWC3_DEPCMD_CMDIOC;
2220 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2221 memset(¶ms, 0, sizeof(params));
2222 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2223 WARN_ON_ONCE(ret);
2224 dep->resource_index = 0;
2225 dep->flags &= ~DWC3_EP_BUSY;
2226 udelay(100);
2227}
2228
2229static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2230{
2231 u32 epnum;
2232
2233 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2234 struct dwc3_ep *dep;
2235
2236 dep = dwc->eps[epnum];
2237 if (!dep)
2238 continue;
2239
2240 if (!(dep->flags & DWC3_EP_ENABLED))
2241 continue;
2242
2243 dwc3_remove_requests(dwc, dep);
2244 }
2245}
2246
2247static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2248{
2249 u32 epnum;
2250
2251 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2252 struct dwc3_ep *dep;
2253 struct dwc3_gadget_ep_cmd_params params;
2254 int ret;
2255
2256 dep = dwc->eps[epnum];
2257 if (!dep)
2258 continue;
2259
2260 if (!(dep->flags & DWC3_EP_STALL))
2261 continue;
2262
2263 dep->flags &= ~DWC3_EP_STALL;
2264
2265 memset(¶ms, 0, sizeof(params));
2266 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2267 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2268 WARN_ON_ONCE(ret);
2269 }
2270}
2271
2272static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2273{
2274 int reg;
2275
2276 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2277 reg &= ~DWC3_DCTL_INITU1ENA;
2278 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2279
2280 reg &= ~DWC3_DCTL_INITU2ENA;
2281 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2282
2283 dwc3_disconnect_gadget(dwc);
2284
2285 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2286 dwc->setup_packet_pending = false;
2287 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2288}
2289
2290static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2291{
2292 u32 reg;
2293
2294 /*
2295 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2296 * would cause a missing Disconnect Event if there's a
2297 * pending Setup Packet in the FIFO.
2298 *
2299 * There's no suggested workaround on the official Bug
2300 * report, which states that "unless the driver/application
2301 * is doing any special handling of a disconnect event,
2302 * there is no functional issue".
2303 *
2304 * Unfortunately, it turns out that we _do_ some special
2305 * handling of a disconnect event, namely complete all
2306 * pending transfers, notify gadget driver of the
2307 * disconnection, and so on.
2308 *
2309 * Our suggested workaround is to follow the Disconnect
2310 * Event steps here, instead, based on a setup_packet_pending
2311 * flag. Such flag gets set whenever we have a SETUP_PENDING
2312 * status for EP0 TRBs and gets cleared on XferComplete for the
2313 * same endpoint.
2314 *
2315 * Refers to:
2316 *
2317 * STAR#9000466709: RTL: Device : Disconnect event not
2318 * generated if setup packet pending in FIFO
2319 */
2320 if (dwc->revision < DWC3_REVISION_188A) {
2321 if (dwc->setup_packet_pending)
2322 dwc3_gadget_disconnect_interrupt(dwc);
2323 }
2324
2325 dwc3_reset_gadget(dwc);
2326
2327 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2328 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2329 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2330 dwc->test_mode = false;
2331
2332 dwc3_stop_active_transfers(dwc);
2333 dwc3_clear_stall_all_ep(dwc);
2334
2335 /* Reset device address to zero */
2336 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2337 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2338 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2339}
2340
2341static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2342{
2343 u32 reg;
2344 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2345
2346 /*
2347 * We change the clock only at SS but I dunno why I would want to do
2348 * this. Maybe it becomes part of the power saving plan.
2349 */
2350
2351 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2352 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2353 return;
2354
2355 /*
2356 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2357 * each time on Connect Done.
2358 */
2359 if (!usb30_clock)
2360 return;
2361
2362 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2363 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2364 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2365}
2366
2367static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2368{
2369 struct dwc3_ep *dep;
2370 int ret;
2371 u32 reg;
2372 u8 speed;
2373
2374 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2375 speed = reg & DWC3_DSTS_CONNECTSPD;
2376 dwc->speed = speed;
2377
2378 dwc3_update_ram_clk_sel(dwc, speed);
2379
2380 switch (speed) {
2381 case DWC3_DCFG_SUPERSPEED_PLUS:
2382 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2383 dwc->gadget.ep0->maxpacket = 512;
2384 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2385 break;
2386 case DWC3_DCFG_SUPERSPEED:
2387 /*
2388 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2389 * would cause a missing USB3 Reset event.
2390 *
2391 * In such situations, we should force a USB3 Reset
2392 * event by calling our dwc3_gadget_reset_interrupt()
2393 * routine.
2394 *
2395 * Refers to:
2396 *
2397 * STAR#9000483510: RTL: SS : USB3 reset event may
2398 * not be generated always when the link enters poll
2399 */
2400 if (dwc->revision < DWC3_REVISION_190A)
2401 dwc3_gadget_reset_interrupt(dwc);
2402
2403 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2404 dwc->gadget.ep0->maxpacket = 512;
2405 dwc->gadget.speed = USB_SPEED_SUPER;
2406 break;
2407 case DWC3_DCFG_HIGHSPEED:
2408 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2409 dwc->gadget.ep0->maxpacket = 64;
2410 dwc->gadget.speed = USB_SPEED_HIGH;
2411 break;
2412 case DWC3_DCFG_FULLSPEED2:
2413 case DWC3_DCFG_FULLSPEED1:
2414 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2415 dwc->gadget.ep0->maxpacket = 64;
2416 dwc->gadget.speed = USB_SPEED_FULL;
2417 break;
2418 case DWC3_DCFG_LOWSPEED:
2419 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2420 dwc->gadget.ep0->maxpacket = 8;
2421 dwc->gadget.speed = USB_SPEED_LOW;
2422 break;
2423 }
2424
2425 /* Enable USB2 LPM Capability */
2426
2427 if ((dwc->revision > DWC3_REVISION_194A) &&
2428 (speed != DWC3_DCFG_SUPERSPEED) &&
2429 (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2430 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2431 reg |= DWC3_DCFG_LPM_CAP;
2432 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2433
2434 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2435 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2436
2437 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2438
2439 /*
2440 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2441 * DCFG.LPMCap is set, core responses with an ACK and the
2442 * BESL value in the LPM token is less than or equal to LPM
2443 * NYET threshold.
2444 */
2445 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2446 && dwc->has_lpm_erratum,
2447 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2448
2449 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2450 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2451
2452 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2453 } else {
2454 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2455 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2456 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2457 }
2458
2459 dep = dwc->eps[0];
2460 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2461 false);
2462 if (ret) {
2463 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2464 return;
2465 }
2466
2467 dep = dwc->eps[1];
2468 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2469 false);
2470 if (ret) {
2471 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2472 return;
2473 }
2474
2475 /*
2476 * Configure PHY via GUSB3PIPECTLn if required.
2477 *
2478 * Update GTXFIFOSIZn
2479 *
2480 * In both cases reset values should be sufficient.
2481 */
2482}
2483
2484static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2485{
2486 /*
2487 * TODO take core out of low power mode when that's
2488 * implemented.
2489 */
2490
2491 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2492 spin_unlock(&dwc->lock);
2493 dwc->gadget_driver->resume(&dwc->gadget);
2494 spin_lock(&dwc->lock);
2495 }
2496}
2497
2498static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2499 unsigned int evtinfo)
2500{
2501 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2502 unsigned int pwropt;
2503
2504 /*
2505 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2506 * Hibernation mode enabled which would show up when device detects
2507 * host-initiated U3 exit.
2508 *
2509 * In that case, device will generate a Link State Change Interrupt
2510 * from U3 to RESUME which is only necessary if Hibernation is
2511 * configured in.
2512 *
2513 * There are no functional changes due to such spurious event and we
2514 * just need to ignore it.
2515 *
2516 * Refers to:
2517 *
2518 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2519 * operational mode
2520 */
2521 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2522 if ((dwc->revision < DWC3_REVISION_250A) &&
2523 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2524 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2525 (next == DWC3_LINK_STATE_RESUME)) {
2526 dwc3_trace(trace_dwc3_gadget,
2527 "ignoring transition U3 -> Resume");
2528 return;
2529 }
2530 }
2531
2532 /*
2533 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2534 * on the link partner, the USB session might do multiple entry/exit
2535 * of low power states before a transfer takes place.
2536 *
2537 * Due to this problem, we might experience lower throughput. The
2538 * suggested workaround is to disable DCTL[12:9] bits if we're
2539 * transitioning from U1/U2 to U0 and enable those bits again
2540 * after a transfer completes and there are no pending transfers
2541 * on any of the enabled endpoints.
2542 *
2543 * This is the first half of that workaround.
2544 *
2545 * Refers to:
2546 *
2547 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2548 * core send LGO_Ux entering U0
2549 */
2550 if (dwc->revision < DWC3_REVISION_183A) {
2551 if (next == DWC3_LINK_STATE_U0) {
2552 u32 u1u2;
2553 u32 reg;
2554
2555 switch (dwc->link_state) {
2556 case DWC3_LINK_STATE_U1:
2557 case DWC3_LINK_STATE_U2:
2558 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2559 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2560 | DWC3_DCTL_ACCEPTU2ENA
2561 | DWC3_DCTL_INITU1ENA
2562 | DWC3_DCTL_ACCEPTU1ENA);
2563
2564 if (!dwc->u1u2)
2565 dwc->u1u2 = reg & u1u2;
2566
2567 reg &= ~u1u2;
2568
2569 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2570 break;
2571 default:
2572 /* do nothing */
2573 break;
2574 }
2575 }
2576 }
2577
2578 switch (next) {
2579 case DWC3_LINK_STATE_U1:
2580 if (dwc->speed == USB_SPEED_SUPER)
2581 dwc3_suspend_gadget(dwc);
2582 break;
2583 case DWC3_LINK_STATE_U2:
2584 case DWC3_LINK_STATE_U3:
2585 dwc3_suspend_gadget(dwc);
2586 break;
2587 case DWC3_LINK_STATE_RESUME:
2588 dwc3_resume_gadget(dwc);
2589 break;
2590 default:
2591 /* do nothing */
2592 break;
2593 }
2594
2595 dwc->link_state = next;
2596}
2597
2598static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2599 unsigned int evtinfo)
2600{
2601 unsigned int is_ss = evtinfo & BIT(4);
2602
2603 /**
2604 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2605 * have a known issue which can cause USB CV TD.9.23 to fail
2606 * randomly.
2607 *
2608 * Because of this issue, core could generate bogus hibernation
2609 * events which SW needs to ignore.
2610 *
2611 * Refers to:
2612 *
2613 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2614 * Device Fallback from SuperSpeed
2615 */
2616 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2617 return;
2618
2619 /* enter hibernation here */
2620}
2621
2622static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2623 const struct dwc3_event_devt *event)
2624{
2625 switch (event->type) {
2626 case DWC3_DEVICE_EVENT_DISCONNECT:
2627 dwc3_gadget_disconnect_interrupt(dwc);
2628 break;
2629 case DWC3_DEVICE_EVENT_RESET:
2630 dwc3_gadget_reset_interrupt(dwc);
2631 break;
2632 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2633 dwc3_gadget_conndone_interrupt(dwc);
2634 break;
2635 case DWC3_DEVICE_EVENT_WAKEUP:
2636 dwc3_gadget_wakeup_interrupt(dwc);
2637 break;
2638 case DWC3_DEVICE_EVENT_HIBER_REQ:
2639 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2640 "unexpected hibernation event\n"))
2641 break;
2642
2643 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2644 break;
2645 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2646 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2647 break;
2648 case DWC3_DEVICE_EVENT_EOPF:
2649 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2650 break;
2651 case DWC3_DEVICE_EVENT_SOF:
2652 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2653 break;
2654 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2655 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2656 break;
2657 case DWC3_DEVICE_EVENT_CMD_CMPL:
2658 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2659 break;
2660 case DWC3_DEVICE_EVENT_OVERFLOW:
2661 dwc3_trace(trace_dwc3_gadget, "Overflow");
2662 break;
2663 default:
2664 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2665 }
2666}
2667
2668static void dwc3_process_event_entry(struct dwc3 *dwc,
2669 const union dwc3_event *event)
2670{
2671 trace_dwc3_event(event->raw);
2672
2673 /* Endpoint IRQ, handle it and return early */
2674 if (event->type.is_devspec == 0) {
2675 /* depevt */
2676 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2677 }
2678
2679 switch (event->type.type) {
2680 case DWC3_EVENT_TYPE_DEV:
2681 dwc3_gadget_interrupt(dwc, &event->devt);
2682 break;
2683 /* REVISIT what to do with Carkit and I2C events ? */
2684 default:
2685 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2686 }
2687}
2688
2689static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2690{
2691 struct dwc3_event_buffer *evt;
2692 irqreturn_t ret = IRQ_NONE;
2693 int left;
2694 u32 reg;
2695
2696 evt = dwc->ev_buffs[buf];
2697 left = evt->count;
2698
2699 if (!(evt->flags & DWC3_EVENT_PENDING))
2700 return IRQ_NONE;
2701
2702 while (left > 0) {
2703 union dwc3_event event;
2704
2705 event.raw = *(u32 *) (evt->buf + evt->lpos);
2706
2707 dwc3_process_event_entry(dwc, &event);
2708
2709 /*
2710 * FIXME we wrap around correctly to the next entry as
2711 * almost all entries are 4 bytes in size. There is one
2712 * entry which has 12 bytes which is a regular entry
2713 * followed by 8 bytes data. ATM I don't know how
2714 * things are organized if we get next to the a
2715 * boundary so I worry about that once we try to handle
2716 * that.
2717 */
2718 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2719 left -= 4;
2720
2721 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2722 }
2723
2724 evt->count = 0;
2725 evt->flags &= ~DWC3_EVENT_PENDING;
2726 ret = IRQ_HANDLED;
2727
2728 /* Unmask interrupt */
2729 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2730 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2731 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2732
2733 return ret;
2734}
2735
2736static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2737{
2738 struct dwc3 *dwc = _dwc;
2739 unsigned long flags;
2740 irqreturn_t ret = IRQ_NONE;
2741 int i;
2742
2743 spin_lock_irqsave(&dwc->lock, flags);
2744
2745 for (i = 0; i < dwc->num_event_buffers; i++)
2746 ret |= dwc3_process_event_buf(dwc, i);
2747
2748 spin_unlock_irqrestore(&dwc->lock, flags);
2749
2750 return ret;
2751}
2752
2753static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2754{
2755 struct dwc3_event_buffer *evt;
2756 u32 count;
2757 u32 reg;
2758
2759 evt = dwc->ev_buffs[buf];
2760
2761 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2762 count &= DWC3_GEVNTCOUNT_MASK;
2763 if (!count)
2764 return IRQ_NONE;
2765
2766 evt->count = count;
2767 evt->flags |= DWC3_EVENT_PENDING;
2768
2769 /* Mask interrupt */
2770 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2771 reg |= DWC3_GEVNTSIZ_INTMASK;
2772 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2773
2774 return IRQ_WAKE_THREAD;
2775}
2776
2777static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2778{
2779 struct dwc3 *dwc = _dwc;
2780 int i;
2781 irqreturn_t ret = IRQ_NONE;
2782
2783 for (i = 0; i < dwc->num_event_buffers; i++) {
2784 irqreturn_t status;
2785
2786 status = dwc3_check_event_buf(dwc, i);
2787 if (status == IRQ_WAKE_THREAD)
2788 ret = status;
2789 }
2790
2791 return ret;
2792}
2793
2794/**
2795 * dwc3_gadget_init - Initializes gadget related registers
2796 * @dwc: pointer to our controller context structure
2797 *
2798 * Returns 0 on success otherwise negative errno.
2799 */
2800int dwc3_gadget_init(struct dwc3 *dwc)
2801{
2802 int ret;
2803
2804 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2805 &dwc->ctrl_req_addr, GFP_KERNEL);
2806 if (!dwc->ctrl_req) {
2807 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2808 ret = -ENOMEM;
2809 goto err0;
2810 }
2811
2812 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2813 &dwc->ep0_trb_addr, GFP_KERNEL);
2814 if (!dwc->ep0_trb) {
2815 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2816 ret = -ENOMEM;
2817 goto err1;
2818 }
2819
2820 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2821 if (!dwc->setup_buf) {
2822 ret = -ENOMEM;
2823 goto err2;
2824 }
2825
2826 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2827 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2828 GFP_KERNEL);
2829 if (!dwc->ep0_bounce) {
2830 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2831 ret = -ENOMEM;
2832 goto err3;
2833 }
2834
2835 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2836 if (!dwc->zlp_buf) {
2837 ret = -ENOMEM;
2838 goto err4;
2839 }
2840
2841 dwc->gadget.ops = &dwc3_gadget_ops;
2842 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2843 dwc->gadget.sg_supported = true;
2844 dwc->gadget.name = "dwc3-gadget";
2845 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
2846
2847 /*
2848 * FIXME We might be setting max_speed to <SUPER, however versions
2849 * <2.20a of dwc3 have an issue with metastability (documented
2850 * elsewhere in this driver) which tells us we can't set max speed to
2851 * anything lower than SUPER.
2852 *
2853 * Because gadget.max_speed is only used by composite.c and function
2854 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2855 * to happen so we avoid sending SuperSpeed Capability descriptor
2856 * together with our BOS descriptor as that could confuse host into
2857 * thinking we can handle super speed.
2858 *
2859 * Note that, in fact, we won't even support GetBOS requests when speed
2860 * is less than super speed because we don't have means, yet, to tell
2861 * composite.c that we are USB 2.0 + LPM ECN.
2862 */
2863 if (dwc->revision < DWC3_REVISION_220A)
2864 dwc3_trace(trace_dwc3_gadget,
2865 "Changing max_speed on rev %08x\n",
2866 dwc->revision);
2867
2868 dwc->gadget.max_speed = dwc->maximum_speed;
2869
2870 /*
2871 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2872 * on ep out.
2873 */
2874 dwc->gadget.quirk_ep_out_aligned_size = true;
2875
2876 /*
2877 * REVISIT: Here we should clear all pending IRQs to be
2878 * sure we're starting from a well known location.
2879 */
2880
2881 ret = dwc3_gadget_init_endpoints(dwc);
2882 if (ret)
2883 goto err5;
2884
2885 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2886 if (ret) {
2887 dev_err(dwc->dev, "failed to register udc\n");
2888 goto err5;
2889 }
2890
2891 return 0;
2892
2893err5:
2894 kfree(dwc->zlp_buf);
2895
2896err4:
2897 dwc3_gadget_free_endpoints(dwc);
2898 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2899 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2900
2901err3:
2902 kfree(dwc->setup_buf);
2903
2904err2:
2905 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2906 dwc->ep0_trb, dwc->ep0_trb_addr);
2907
2908err1:
2909 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2910 dwc->ctrl_req, dwc->ctrl_req_addr);
2911
2912err0:
2913 return ret;
2914}
2915
2916/* -------------------------------------------------------------------------- */
2917
2918void dwc3_gadget_exit(struct dwc3 *dwc)
2919{
2920 usb_del_gadget_udc(&dwc->gadget);
2921
2922 dwc3_gadget_free_endpoints(dwc);
2923
2924 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2925 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2926
2927 kfree(dwc->setup_buf);
2928 kfree(dwc->zlp_buf);
2929
2930 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2931 dwc->ep0_trb, dwc->ep0_trb_addr);
2932
2933 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2934 dwc->ctrl_req, dwc->ctrl_req_addr);
2935}
2936
2937int dwc3_gadget_suspend(struct dwc3 *dwc)
2938{
2939 if (!dwc->gadget_driver)
2940 return 0;
2941
2942 if (dwc->pullups_connected) {
2943 dwc3_gadget_disable_irq(dwc);
2944 dwc3_gadget_run_stop(dwc, true, true);
2945 }
2946
2947 __dwc3_gadget_ep_disable(dwc->eps[0]);
2948 __dwc3_gadget_ep_disable(dwc->eps[1]);
2949
2950 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2951
2952 return 0;
2953}
2954
2955int dwc3_gadget_resume(struct dwc3 *dwc)
2956{
2957 struct dwc3_ep *dep;
2958 int ret;
2959
2960 if (!dwc->gadget_driver)
2961 return 0;
2962
2963 /* Start with SuperSpeed Default */
2964 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2965
2966 dep = dwc->eps[0];
2967 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2968 false);
2969 if (ret)
2970 goto err0;
2971
2972 dep = dwc->eps[1];
2973 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2974 false);
2975 if (ret)
2976 goto err1;
2977
2978 /* begin to receive SETUP packets */
2979 dwc->ep0state = EP0_SETUP_PHASE;
2980 dwc3_ep0_out_start(dwc);
2981
2982 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2983
2984 if (dwc->pullups_connected) {
2985 dwc3_gadget_enable_irq(dwc);
2986 dwc3_gadget_run_stop(dwc, true, false);
2987 }
2988
2989 return 0;
2990
2991err1:
2992 __dwc3_gadget_ep_disable(dwc->eps[0]);
2993
2994err0:
2995 return ret;
2996}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30#define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
32
33/**
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37 *
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
40 */
41int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42{
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48 switch (mode) {
49 case TEST_J:
50 case TEST_K:
51 case TEST_SE0_NAK:
52 case TEST_PACKET:
53 case TEST_FORCE_EN:
54 reg |= mode << 1;
55 break;
56 default:
57 return -EINVAL;
58 }
59
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
61
62 return 0;
63}
64
65/**
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
68 *
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
71 */
72int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73{
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78 return DWC3_DSTS_USBLNKST(reg);
79}
80
81/**
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
85 *
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
88 */
89int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90{
91 int retries = 10000;
92 u32 reg;
93
94 /*
95 * Wait until device controller is ready. Only applies to 1.94a and
96 * later RTL.
97 */
98 if (dwc->revision >= DWC3_REVISION_194A) {
99 while (--retries) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
102 udelay(5);
103 else
104 break;
105 }
106
107 if (retries <= 0)
108 return -ETIMEDOUT;
109 }
110
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117
118 /*
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
121 */
122 if (dwc->revision >= DWC3_REVISION_194A)
123 return 0;
124
125 /* wait for a change in DSTS */
126 retries = 10000;
127 while (--retries) {
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
129
130 if (DWC3_DSTS_USBLNKST(reg) == state)
131 return 0;
132
133 udelay(5);
134 }
135
136 return -ETIMEDOUT;
137}
138
139/**
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
142 *
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
146 */
147static void dwc3_ep_inc_trb(u8 *index)
148{
149 (*index)++;
150 if (*index == (DWC3_TRB_NUM - 1))
151 *index = 0;
152}
153
154/**
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
157 */
158static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
159{
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
161}
162
163/**
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
166 */
167static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
168{
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
170}
171
172static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
174{
175 struct dwc3 *dwc = dep->dwc;
176
177 list_del(&req->list);
178 req->remaining = 0;
179 req->needs_extra_trb = false;
180
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
183
184 if (req->trb)
185 usb_gadget_unmap_request_by_dev(dwc->sysdev,
186 &req->request, req->direction);
187
188 req->trb = NULL;
189 trace_dwc3_gadget_giveback(req);
190
191 if (dep->number > 1)
192 pm_runtime_put(dwc->dev);
193}
194
195/**
196 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
197 * @dep: The endpoint to whom the request belongs to
198 * @req: The request we're giving back
199 * @status: completion code for the request
200 *
201 * Must be called with controller's lock held and interrupts disabled. This
202 * function will unmap @req and call its ->complete() callback to notify upper
203 * layers that it has completed.
204 */
205void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
206 int status)
207{
208 struct dwc3 *dwc = dep->dwc;
209
210 dwc3_gadget_del_and_unmap_request(dep, req, status);
211 req->status = DWC3_REQUEST_STATUS_COMPLETED;
212
213 spin_unlock(&dwc->lock);
214 usb_gadget_giveback_request(&dep->endpoint, &req->request);
215 spin_lock(&dwc->lock);
216}
217
218/**
219 * dwc3_send_gadget_generic_command - issue a generic command for the controller
220 * @dwc: pointer to the controller context
221 * @cmd: the command to be issued
222 * @param: command parameter
223 *
224 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
225 * and wait for its completion.
226 */
227int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
228{
229 u32 timeout = 500;
230 int status = 0;
231 int ret = 0;
232 u32 reg;
233
234 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
235 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
236
237 do {
238 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
239 if (!(reg & DWC3_DGCMD_CMDACT)) {
240 status = DWC3_DGCMD_STATUS(reg);
241 if (status)
242 ret = -EINVAL;
243 break;
244 }
245 } while (--timeout);
246
247 if (!timeout) {
248 ret = -ETIMEDOUT;
249 status = -ETIMEDOUT;
250 }
251
252 trace_dwc3_gadget_generic_cmd(cmd, param, status);
253
254 return ret;
255}
256
257static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
258
259/**
260 * dwc3_send_gadget_ep_cmd - issue an endpoint command
261 * @dep: the endpoint to which the command is going to be issued
262 * @cmd: the command to be issued
263 * @params: parameters to the command
264 *
265 * Caller should handle locking. This function will issue @cmd with given
266 * @params to @dep and wait for its completion.
267 */
268int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
269 struct dwc3_gadget_ep_cmd_params *params)
270{
271 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
272 struct dwc3 *dwc = dep->dwc;
273 u32 timeout = 1000;
274 u32 saved_config = 0;
275 u32 reg;
276
277 int cmd_status = 0;
278 int ret = -EINVAL;
279
280 /*
281 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
282 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
283 * endpoint command.
284 *
285 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
286 * settings. Restore them after the command is completed.
287 *
288 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
289 */
290 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
291 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
292 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
293 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
294 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
295 }
296
297 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
298 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
299 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
300 }
301
302 if (saved_config)
303 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
304 }
305
306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
307 int needs_wakeup;
308
309 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
310 dwc->link_state == DWC3_LINK_STATE_U2 ||
311 dwc->link_state == DWC3_LINK_STATE_U3);
312
313 if (unlikely(needs_wakeup)) {
314 ret = __dwc3_gadget_wakeup(dwc);
315 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
316 ret);
317 }
318 }
319
320 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
322 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
323
324 /*
325 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
326 * not relying on XferNotReady, we can make use of a special "No
327 * Response Update Transfer" command where we should clear both CmdAct
328 * and CmdIOC bits.
329 *
330 * With this, we don't need to wait for command completion and can
331 * straight away issue further commands to the endpoint.
332 *
333 * NOTICE: We're making an assumption that control endpoints will never
334 * make use of Update Transfer command. This is a safe assumption
335 * because we can never have more than one request at a time with
336 * Control Endpoints. If anybody changes that assumption, this chunk
337 * needs to be updated accordingly.
338 */
339 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
340 !usb_endpoint_xfer_isoc(desc))
341 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
342 else
343 cmd |= DWC3_DEPCMD_CMDACT;
344
345 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
346 do {
347 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
348 if (!(reg & DWC3_DEPCMD_CMDACT)) {
349 cmd_status = DWC3_DEPCMD_STATUS(reg);
350
351 switch (cmd_status) {
352 case 0:
353 ret = 0;
354 break;
355 case DEPEVT_TRANSFER_NO_RESOURCE:
356 ret = -EINVAL;
357 break;
358 case DEPEVT_TRANSFER_BUS_EXPIRY:
359 /*
360 * SW issues START TRANSFER command to
361 * isochronous ep with future frame interval. If
362 * future interval time has already passed when
363 * core receives the command, it will respond
364 * with an error status of 'Bus Expiry'.
365 *
366 * Instead of always returning -EINVAL, let's
367 * give a hint to the gadget driver that this is
368 * the case by returning -EAGAIN.
369 */
370 ret = -EAGAIN;
371 break;
372 default:
373 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
374 }
375
376 break;
377 }
378 } while (--timeout);
379
380 if (timeout == 0) {
381 ret = -ETIMEDOUT;
382 cmd_status = -ETIMEDOUT;
383 }
384
385 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
386
387 if (ret == 0 && DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
388 dep->flags |= DWC3_EP_TRANSFER_STARTED;
389 dwc3_gadget_ep_get_transfer_index(dep);
390 }
391
392 if (saved_config) {
393 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
394 reg |= saved_config;
395 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
396 }
397
398 return ret;
399}
400
401static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
402{
403 struct dwc3 *dwc = dep->dwc;
404 struct dwc3_gadget_ep_cmd_params params;
405 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
406
407 /*
408 * As of core revision 2.60a the recommended programming model
409 * is to set the ClearPendIN bit when issuing a Clear Stall EP
410 * command for IN endpoints. This is to prevent an issue where
411 * some (non-compliant) hosts may not send ACK TPs for pending
412 * IN transfers due to a mishandled error condition. Synopsys
413 * STAR 9000614252.
414 */
415 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
416 (dwc->gadget.speed >= USB_SPEED_SUPER))
417 cmd |= DWC3_DEPCMD_CLEARPENDIN;
418
419 memset(¶ms, 0, sizeof(params));
420
421 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
422}
423
424static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
425 struct dwc3_trb *trb)
426{
427 u32 offset = (char *) trb - (char *) dep->trb_pool;
428
429 return dep->trb_pool_dma + offset;
430}
431
432static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
433{
434 struct dwc3 *dwc = dep->dwc;
435
436 if (dep->trb_pool)
437 return 0;
438
439 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
440 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
441 &dep->trb_pool_dma, GFP_KERNEL);
442 if (!dep->trb_pool) {
443 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
444 dep->name);
445 return -ENOMEM;
446 }
447
448 return 0;
449}
450
451static void dwc3_free_trb_pool(struct dwc3_ep *dep)
452{
453 struct dwc3 *dwc = dep->dwc;
454
455 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
456 dep->trb_pool, dep->trb_pool_dma);
457
458 dep->trb_pool = NULL;
459 dep->trb_pool_dma = 0;
460}
461
462static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
463{
464 struct dwc3_gadget_ep_cmd_params params;
465
466 memset(¶ms, 0x00, sizeof(params));
467
468 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
469
470 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
471 ¶ms);
472}
473
474/**
475 * dwc3_gadget_start_config - configure ep resources
476 * @dep: endpoint that is being enabled
477 *
478 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
479 * completion, it will set Transfer Resource for all available endpoints.
480 *
481 * The assignment of transfer resources cannot perfectly follow the data book
482 * due to the fact that the controller driver does not have all knowledge of the
483 * configuration in advance. It is given this information piecemeal by the
484 * composite gadget framework after every SET_CONFIGURATION and
485 * SET_INTERFACE. Trying to follow the databook programming model in this
486 * scenario can cause errors. For two reasons:
487 *
488 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
489 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
490 * incorrect in the scenario of multiple interfaces.
491 *
492 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
493 * endpoint on alt setting (8.1.6).
494 *
495 * The following simplified method is used instead:
496 *
497 * All hardware endpoints can be assigned a transfer resource and this setting
498 * will stay persistent until either a core reset or hibernation. So whenever we
499 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
500 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
501 * guaranteed that there are as many transfer resources as endpoints.
502 *
503 * This function is called for each endpoint when it is being enabled but is
504 * triggered only when called for EP0-out, which always happens first, and which
505 * should only happen in one of the above conditions.
506 */
507static int dwc3_gadget_start_config(struct dwc3_ep *dep)
508{
509 struct dwc3_gadget_ep_cmd_params params;
510 struct dwc3 *dwc;
511 u32 cmd;
512 int i;
513 int ret;
514
515 if (dep->number)
516 return 0;
517
518 memset(¶ms, 0x00, sizeof(params));
519 cmd = DWC3_DEPCMD_DEPSTARTCFG;
520 dwc = dep->dwc;
521
522 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
523 if (ret)
524 return ret;
525
526 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
527 struct dwc3_ep *dep = dwc->eps[i];
528
529 if (!dep)
530 continue;
531
532 ret = dwc3_gadget_set_xfer_resource(dep);
533 if (ret)
534 return ret;
535 }
536
537 return 0;
538}
539
540static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
541{
542 const struct usb_ss_ep_comp_descriptor *comp_desc;
543 const struct usb_endpoint_descriptor *desc;
544 struct dwc3_gadget_ep_cmd_params params;
545 struct dwc3 *dwc = dep->dwc;
546
547 comp_desc = dep->endpoint.comp_desc;
548 desc = dep->endpoint.desc;
549
550 memset(¶ms, 0x00, sizeof(params));
551
552 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
553 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
554
555 /* Burst size is only needed in SuperSpeed mode */
556 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
557 u32 burst = dep->endpoint.maxburst;
558 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
559 }
560
561 params.param0 |= action;
562 if (action == DWC3_DEPCFG_ACTION_RESTORE)
563 params.param2 |= dep->saved_state;
564
565 if (usb_endpoint_xfer_control(desc))
566 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
567
568 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
569 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
570
571 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
572 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
573 | DWC3_DEPCFG_STREAM_EVENT_EN;
574 dep->stream_capable = true;
575 }
576
577 if (!usb_endpoint_xfer_control(desc))
578 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
579
580 /*
581 * We are doing 1:1 mapping for endpoints, meaning
582 * Physical Endpoints 2 maps to Logical Endpoint 2 and
583 * so on. We consider the direction bit as part of the physical
584 * endpoint number. So USB endpoint 0x81 is 0x03.
585 */
586 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
587
588 /*
589 * We must use the lower 16 TX FIFOs even though
590 * HW might have more
591 */
592 if (dep->direction)
593 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
594
595 if (desc->bInterval) {
596 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
597 dep->interval = 1 << (desc->bInterval - 1);
598 }
599
600 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
601}
602
603/**
604 * __dwc3_gadget_ep_enable - initializes a hw endpoint
605 * @dep: endpoint to be initialized
606 * @action: one of INIT, MODIFY or RESTORE
607 *
608 * Caller should take care of locking. Execute all necessary commands to
609 * initialize a HW endpoint so it can be used by a gadget driver.
610 */
611static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
612{
613 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
614 struct dwc3 *dwc = dep->dwc;
615
616 u32 reg;
617 int ret;
618
619 if (!(dep->flags & DWC3_EP_ENABLED)) {
620 ret = dwc3_gadget_start_config(dep);
621 if (ret)
622 return ret;
623 }
624
625 ret = dwc3_gadget_set_ep_config(dep, action);
626 if (ret)
627 return ret;
628
629 if (!(dep->flags & DWC3_EP_ENABLED)) {
630 struct dwc3_trb *trb_st_hw;
631 struct dwc3_trb *trb_link;
632
633 dep->type = usb_endpoint_type(desc);
634 dep->flags |= DWC3_EP_ENABLED;
635
636 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
637 reg |= DWC3_DALEPENA_EP(dep->number);
638 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
639
640 if (usb_endpoint_xfer_control(desc))
641 goto out;
642
643 /* Initialize the TRB ring */
644 dep->trb_dequeue = 0;
645 dep->trb_enqueue = 0;
646 memset(dep->trb_pool, 0,
647 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
648
649 /* Link TRB. The HWO bit is never reset */
650 trb_st_hw = &dep->trb_pool[0];
651
652 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
653 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
654 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
655 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
656 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
657 }
658
659 /*
660 * Issue StartTransfer here with no-op TRB so we can always rely on No
661 * Response Update Transfer command.
662 */
663 if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) ||
664 usb_endpoint_xfer_int(desc)) {
665 struct dwc3_gadget_ep_cmd_params params;
666 struct dwc3_trb *trb;
667 dma_addr_t trb_dma;
668 u32 cmd;
669
670 memset(¶ms, 0, sizeof(params));
671 trb = &dep->trb_pool[0];
672 trb_dma = dwc3_trb_dma_offset(dep, trb);
673
674 params.param0 = upper_32_bits(trb_dma);
675 params.param1 = lower_32_bits(trb_dma);
676
677 cmd = DWC3_DEPCMD_STARTTRANSFER;
678
679 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
680 if (ret < 0)
681 return ret;
682 }
683
684out:
685 trace_dwc3_gadget_ep_enable(dep);
686
687 return 0;
688}
689
690static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
691 bool interrupt);
692static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
693{
694 struct dwc3_request *req;
695
696 dwc3_stop_active_transfer(dep, true, false);
697
698 /* - giveback all requests to gadget driver */
699 while (!list_empty(&dep->started_list)) {
700 req = next_request(&dep->started_list);
701
702 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
703 }
704
705 while (!list_empty(&dep->pending_list)) {
706 req = next_request(&dep->pending_list);
707
708 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
709 }
710
711 while (!list_empty(&dep->cancelled_list)) {
712 req = next_request(&dep->cancelled_list);
713
714 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
715 }
716}
717
718/**
719 * __dwc3_gadget_ep_disable - disables a hw endpoint
720 * @dep: the endpoint to disable
721 *
722 * This function undoes what __dwc3_gadget_ep_enable did and also removes
723 * requests which are currently being processed by the hardware and those which
724 * are not yet scheduled.
725 *
726 * Caller should take care of locking.
727 */
728static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
729{
730 struct dwc3 *dwc = dep->dwc;
731 u32 reg;
732
733 trace_dwc3_gadget_ep_disable(dep);
734
735 dwc3_remove_requests(dwc, dep);
736
737 /* make sure HW endpoint isn't stalled */
738 if (dep->flags & DWC3_EP_STALL)
739 __dwc3_gadget_ep_set_halt(dep, 0, false);
740
741 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
742 reg &= ~DWC3_DALEPENA_EP(dep->number);
743 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
744
745 dep->stream_capable = false;
746 dep->type = 0;
747 dep->flags = 0;
748
749 /* Clear out the ep descriptors for non-ep0 */
750 if (dep->number > 1) {
751 dep->endpoint.comp_desc = NULL;
752 dep->endpoint.desc = NULL;
753 }
754
755 return 0;
756}
757
758/* -------------------------------------------------------------------------- */
759
760static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
761 const struct usb_endpoint_descriptor *desc)
762{
763 return -EINVAL;
764}
765
766static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
767{
768 return -EINVAL;
769}
770
771/* -------------------------------------------------------------------------- */
772
773static int dwc3_gadget_ep_enable(struct usb_ep *ep,
774 const struct usb_endpoint_descriptor *desc)
775{
776 struct dwc3_ep *dep;
777 struct dwc3 *dwc;
778 unsigned long flags;
779 int ret;
780
781 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
782 pr_debug("dwc3: invalid parameters\n");
783 return -EINVAL;
784 }
785
786 if (!desc->wMaxPacketSize) {
787 pr_debug("dwc3: missing wMaxPacketSize\n");
788 return -EINVAL;
789 }
790
791 dep = to_dwc3_ep(ep);
792 dwc = dep->dwc;
793
794 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
795 "%s is already enabled\n",
796 dep->name))
797 return 0;
798
799 spin_lock_irqsave(&dwc->lock, flags);
800 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
801 spin_unlock_irqrestore(&dwc->lock, flags);
802
803 return ret;
804}
805
806static int dwc3_gadget_ep_disable(struct usb_ep *ep)
807{
808 struct dwc3_ep *dep;
809 struct dwc3 *dwc;
810 unsigned long flags;
811 int ret;
812
813 if (!ep) {
814 pr_debug("dwc3: invalid parameters\n");
815 return -EINVAL;
816 }
817
818 dep = to_dwc3_ep(ep);
819 dwc = dep->dwc;
820
821 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
822 "%s is already disabled\n",
823 dep->name))
824 return 0;
825
826 spin_lock_irqsave(&dwc->lock, flags);
827 ret = __dwc3_gadget_ep_disable(dep);
828 spin_unlock_irqrestore(&dwc->lock, flags);
829
830 return ret;
831}
832
833static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
834 gfp_t gfp_flags)
835{
836 struct dwc3_request *req;
837 struct dwc3_ep *dep = to_dwc3_ep(ep);
838
839 req = kzalloc(sizeof(*req), gfp_flags);
840 if (!req)
841 return NULL;
842
843 req->direction = dep->direction;
844 req->epnum = dep->number;
845 req->dep = dep;
846 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
847
848 trace_dwc3_alloc_request(req);
849
850 return &req->request;
851}
852
853static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
854 struct usb_request *request)
855{
856 struct dwc3_request *req = to_dwc3_request(request);
857
858 trace_dwc3_free_request(req);
859 kfree(req);
860}
861
862/**
863 * dwc3_ep_prev_trb - returns the previous TRB in the ring
864 * @dep: The endpoint with the TRB ring
865 * @index: The index of the current TRB in the ring
866 *
867 * Returns the TRB prior to the one pointed to by the index. If the
868 * index is 0, we will wrap backwards, skip the link TRB, and return
869 * the one just before that.
870 */
871static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
872{
873 u8 tmp = index;
874
875 if (!tmp)
876 tmp = DWC3_TRB_NUM - 1;
877
878 return &dep->trb_pool[tmp - 1];
879}
880
881static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
882{
883 struct dwc3_trb *tmp;
884 u8 trbs_left;
885
886 /*
887 * If enqueue & dequeue are equal than it is either full or empty.
888 *
889 * One way to know for sure is if the TRB right before us has HWO bit
890 * set or not. If it has, then we're definitely full and can't fit any
891 * more transfers in our ring.
892 */
893 if (dep->trb_enqueue == dep->trb_dequeue) {
894 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
895 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
896 return 0;
897
898 return DWC3_TRB_NUM - 1;
899 }
900
901 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
902 trbs_left &= (DWC3_TRB_NUM - 1);
903
904 if (dep->trb_dequeue < dep->trb_enqueue)
905 trbs_left--;
906
907 return trbs_left;
908}
909
910static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
911 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
912 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
913{
914 struct dwc3 *dwc = dep->dwc;
915 struct usb_gadget *gadget = &dwc->gadget;
916 enum usb_device_speed speed = gadget->speed;
917
918 trb->size = DWC3_TRB_SIZE_LENGTH(length);
919 trb->bpl = lower_32_bits(dma);
920 trb->bph = upper_32_bits(dma);
921
922 switch (usb_endpoint_type(dep->endpoint.desc)) {
923 case USB_ENDPOINT_XFER_CONTROL:
924 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
925 break;
926
927 case USB_ENDPOINT_XFER_ISOC:
928 if (!node) {
929 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
930
931 /*
932 * USB Specification 2.0 Section 5.9.2 states that: "If
933 * there is only a single transaction in the microframe,
934 * only a DATA0 data packet PID is used. If there are
935 * two transactions per microframe, DATA1 is used for
936 * the first transaction data packet and DATA0 is used
937 * for the second transaction data packet. If there are
938 * three transactions per microframe, DATA2 is used for
939 * the first transaction data packet, DATA1 is used for
940 * the second, and DATA0 is used for the third."
941 *
942 * IOW, we should satisfy the following cases:
943 *
944 * 1) length <= maxpacket
945 * - DATA0
946 *
947 * 2) maxpacket < length <= (2 * maxpacket)
948 * - DATA1, DATA0
949 *
950 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
951 * - DATA2, DATA1, DATA0
952 */
953 if (speed == USB_SPEED_HIGH) {
954 struct usb_ep *ep = &dep->endpoint;
955 unsigned int mult = 2;
956 unsigned int maxp = usb_endpoint_maxp(ep->desc);
957
958 if (length <= (2 * maxp))
959 mult--;
960
961 if (length <= maxp)
962 mult--;
963
964 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
965 }
966 } else {
967 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
968 }
969
970 /* always enable Interrupt on Missed ISOC */
971 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
972 break;
973
974 case USB_ENDPOINT_XFER_BULK:
975 case USB_ENDPOINT_XFER_INT:
976 trb->ctrl = DWC3_TRBCTL_NORMAL;
977 break;
978 default:
979 /*
980 * This is only possible with faulty memory because we
981 * checked it already :)
982 */
983 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
984 usb_endpoint_type(dep->endpoint.desc));
985 }
986
987 /*
988 * Enable Continue on Short Packet
989 * when endpoint is not a stream capable
990 */
991 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
992 if (!dep->stream_capable)
993 trb->ctrl |= DWC3_TRB_CTRL_CSP;
994
995 if (short_not_ok)
996 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
997 }
998
999 if ((!no_interrupt && !chain) ||
1000 (dwc3_calc_trbs_left(dep) == 1))
1001 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1002
1003 if (chain)
1004 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1005
1006 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1007 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1008
1009 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1010
1011 dwc3_ep_inc_enq(dep);
1012
1013 trace_dwc3_prepare_trb(dep, trb);
1014}
1015
1016/**
1017 * dwc3_prepare_one_trb - setup one TRB from one request
1018 * @dep: endpoint for which this request is prepared
1019 * @req: dwc3_request pointer
1020 * @chain: should this TRB be chained to the next?
1021 * @node: only for isochronous endpoints. First TRB needs different type.
1022 */
1023static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1024 struct dwc3_request *req, unsigned chain, unsigned node)
1025{
1026 struct dwc3_trb *trb;
1027 unsigned int length;
1028 dma_addr_t dma;
1029 unsigned stream_id = req->request.stream_id;
1030 unsigned short_not_ok = req->request.short_not_ok;
1031 unsigned no_interrupt = req->request.no_interrupt;
1032
1033 if (req->request.num_sgs > 0) {
1034 length = sg_dma_len(req->start_sg);
1035 dma = sg_dma_address(req->start_sg);
1036 } else {
1037 length = req->request.length;
1038 dma = req->request.dma;
1039 }
1040
1041 trb = &dep->trb_pool[dep->trb_enqueue];
1042
1043 if (!req->trb) {
1044 dwc3_gadget_move_started_request(req);
1045 req->trb = trb;
1046 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1047 }
1048
1049 req->num_trbs++;
1050
1051 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1052 stream_id, short_not_ok, no_interrupt);
1053}
1054
1055static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1056 struct dwc3_request *req)
1057{
1058 struct scatterlist *sg = req->start_sg;
1059 struct scatterlist *s;
1060 int i;
1061
1062 unsigned int remaining = req->request.num_mapped_sgs
1063 - req->num_queued_sgs;
1064
1065 for_each_sg(sg, s, remaining, i) {
1066 unsigned int length = req->request.length;
1067 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1068 unsigned int rem = length % maxp;
1069 unsigned chain = true;
1070
1071 if (sg_is_last(s))
1072 chain = false;
1073
1074 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1075 struct dwc3 *dwc = dep->dwc;
1076 struct dwc3_trb *trb;
1077
1078 req->needs_extra_trb = true;
1079
1080 /* prepare normal TRB */
1081 dwc3_prepare_one_trb(dep, req, true, i);
1082
1083 /* Now prepare one extra TRB to align transfer size */
1084 trb = &dep->trb_pool[dep->trb_enqueue];
1085 req->num_trbs++;
1086 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1087 maxp - rem, false, 1,
1088 req->request.stream_id,
1089 req->request.short_not_ok,
1090 req->request.no_interrupt);
1091 } else {
1092 dwc3_prepare_one_trb(dep, req, chain, i);
1093 }
1094
1095 /*
1096 * There can be a situation where all sgs in sglist are not
1097 * queued because of insufficient trb number. To handle this
1098 * case, update start_sg to next sg to be queued, so that
1099 * we have free trbs we can continue queuing from where we
1100 * previously stopped
1101 */
1102 if (chain)
1103 req->start_sg = sg_next(s);
1104
1105 req->num_queued_sgs++;
1106
1107 if (!dwc3_calc_trbs_left(dep))
1108 break;
1109 }
1110}
1111
1112static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1113 struct dwc3_request *req)
1114{
1115 unsigned int length = req->request.length;
1116 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1117 unsigned int rem = length % maxp;
1118
1119 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1120 struct dwc3 *dwc = dep->dwc;
1121 struct dwc3_trb *trb;
1122
1123 req->needs_extra_trb = true;
1124
1125 /* prepare normal TRB */
1126 dwc3_prepare_one_trb(dep, req, true, 0);
1127
1128 /* Now prepare one extra TRB to align transfer size */
1129 trb = &dep->trb_pool[dep->trb_enqueue];
1130 req->num_trbs++;
1131 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1132 false, 1, req->request.stream_id,
1133 req->request.short_not_ok,
1134 req->request.no_interrupt);
1135 } else if (req->request.zero && req->request.length &&
1136 (IS_ALIGNED(req->request.length, maxp))) {
1137 struct dwc3 *dwc = dep->dwc;
1138 struct dwc3_trb *trb;
1139
1140 req->needs_extra_trb = true;
1141
1142 /* prepare normal TRB */
1143 dwc3_prepare_one_trb(dep, req, true, 0);
1144
1145 /* Now prepare one extra TRB to handle ZLP */
1146 trb = &dep->trb_pool[dep->trb_enqueue];
1147 req->num_trbs++;
1148 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1149 false, 1, req->request.stream_id,
1150 req->request.short_not_ok,
1151 req->request.no_interrupt);
1152 } else {
1153 dwc3_prepare_one_trb(dep, req, false, 0);
1154 }
1155}
1156
1157/*
1158 * dwc3_prepare_trbs - setup TRBs from requests
1159 * @dep: endpoint for which requests are being prepared
1160 *
1161 * The function goes through the requests list and sets up TRBs for the
1162 * transfers. The function returns once there are no more TRBs available or
1163 * it runs out of requests.
1164 */
1165static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1166{
1167 struct dwc3_request *req, *n;
1168
1169 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1170
1171 /*
1172 * We can get in a situation where there's a request in the started list
1173 * but there weren't enough TRBs to fully kick it in the first time
1174 * around, so it has been waiting for more TRBs to be freed up.
1175 *
1176 * In that case, we should check if we have a request with pending_sgs
1177 * in the started list and prepare TRBs for that request first,
1178 * otherwise we will prepare TRBs completely out of order and that will
1179 * break things.
1180 */
1181 list_for_each_entry(req, &dep->started_list, list) {
1182 if (req->num_pending_sgs > 0)
1183 dwc3_prepare_one_trb_sg(dep, req);
1184
1185 if (!dwc3_calc_trbs_left(dep))
1186 return;
1187 }
1188
1189 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1190 struct dwc3 *dwc = dep->dwc;
1191 int ret;
1192
1193 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1194 dep->direction);
1195 if (ret)
1196 return;
1197
1198 req->sg = req->request.sg;
1199 req->start_sg = req->sg;
1200 req->num_queued_sgs = 0;
1201 req->num_pending_sgs = req->request.num_mapped_sgs;
1202
1203 if (req->num_pending_sgs > 0)
1204 dwc3_prepare_one_trb_sg(dep, req);
1205 else
1206 dwc3_prepare_one_trb_linear(dep, req);
1207
1208 if (!dwc3_calc_trbs_left(dep))
1209 return;
1210 }
1211}
1212
1213static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1214{
1215 struct dwc3_gadget_ep_cmd_params params;
1216 struct dwc3_request *req;
1217 int starting;
1218 int ret;
1219 u32 cmd;
1220
1221 if (!dwc3_calc_trbs_left(dep))
1222 return 0;
1223
1224 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1225
1226 dwc3_prepare_trbs(dep);
1227 req = next_request(&dep->started_list);
1228 if (!req) {
1229 dep->flags |= DWC3_EP_PENDING_REQUEST;
1230 return 0;
1231 }
1232
1233 memset(¶ms, 0, sizeof(params));
1234
1235 if (starting) {
1236 params.param0 = upper_32_bits(req->trb_dma);
1237 params.param1 = lower_32_bits(req->trb_dma);
1238 cmd = DWC3_DEPCMD_STARTTRANSFER;
1239
1240 if (dep->stream_capable)
1241 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1242
1243 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1244 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1245 } else {
1246 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1247 DWC3_DEPCMD_PARAM(dep->resource_index);
1248 }
1249
1250 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1251 if (ret < 0) {
1252 /*
1253 * FIXME we need to iterate over the list of requests
1254 * here and stop, unmap, free and del each of the linked
1255 * requests instead of what we do now.
1256 */
1257 if (req->trb)
1258 memset(req->trb, 0, sizeof(struct dwc3_trb));
1259 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1260 return ret;
1261 }
1262
1263 return 0;
1264}
1265
1266static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1267{
1268 u32 reg;
1269
1270 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1271 return DWC3_DSTS_SOFFN(reg);
1272}
1273
1274/**
1275 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1276 * @dep: isoc endpoint
1277 *
1278 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1279 * microframe number reported by the XferNotReady event for the future frame
1280 * number to start the isoc transfer.
1281 *
1282 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1283 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1284 * XferNotReady event are invalid. The driver uses this number to schedule the
1285 * isochronous transfer and passes it to the START TRANSFER command. Because
1286 * this number is invalid, the command may fail. If BIT[15:14] matches the
1287 * internal 16-bit microframe, the START TRANSFER command will pass and the
1288 * transfer will start at the scheduled time, if it is off by 1, the command
1289 * will still pass, but the transfer will start 2 seconds in the future. For all
1290 * other conditions, the START TRANSFER command will fail with bus-expiry.
1291 *
1292 * In order to workaround this issue, we can test for the correct combination of
1293 * BIT[15:14] by sending START TRANSFER commands with different values of
1294 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1295 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1296 * As the result, within the 4 possible combinations for BIT[15:14], there will
1297 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1298 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1299 * value is the correct combination.
1300 *
1301 * Since there are only 4 outcomes and the results are ordered, we can simply
1302 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1303 * deduce the smaller successful combination.
1304 *
1305 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1306 * of BIT[15:14]. The correct combination is as follow:
1307 *
1308 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1309 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1310 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1311 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1312 *
1313 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1314 * endpoints.
1315 */
1316static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1317{
1318 int cmd_status = 0;
1319 bool test0;
1320 bool test1;
1321
1322 while (dep->combo_num < 2) {
1323 struct dwc3_gadget_ep_cmd_params params;
1324 u32 test_frame_number;
1325 u32 cmd;
1326
1327 /*
1328 * Check if we can start isoc transfer on the next interval or
1329 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1330 */
1331 test_frame_number = dep->frame_number & 0x3fff;
1332 test_frame_number |= dep->combo_num << 14;
1333 test_frame_number += max_t(u32, 4, dep->interval);
1334
1335 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1336 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1337
1338 cmd = DWC3_DEPCMD_STARTTRANSFER;
1339 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1340 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1341
1342 /* Redo if some other failure beside bus-expiry is received */
1343 if (cmd_status && cmd_status != -EAGAIN) {
1344 dep->start_cmd_status = 0;
1345 dep->combo_num = 0;
1346 return 0;
1347 }
1348
1349 /* Store the first test status */
1350 if (dep->combo_num == 0)
1351 dep->start_cmd_status = cmd_status;
1352
1353 dep->combo_num++;
1354
1355 /*
1356 * End the transfer if the START_TRANSFER command is successful
1357 * to wait for the next XferNotReady to test the command again
1358 */
1359 if (cmd_status == 0) {
1360 dwc3_stop_active_transfer(dep, true, true);
1361 return 0;
1362 }
1363 }
1364
1365 /* test0 and test1 are both completed at this point */
1366 test0 = (dep->start_cmd_status == 0);
1367 test1 = (cmd_status == 0);
1368
1369 if (!test0 && test1)
1370 dep->combo_num = 1;
1371 else if (!test0 && !test1)
1372 dep->combo_num = 2;
1373 else if (test0 && !test1)
1374 dep->combo_num = 3;
1375 else if (test0 && test1)
1376 dep->combo_num = 0;
1377
1378 dep->frame_number &= 0x3fff;
1379 dep->frame_number |= dep->combo_num << 14;
1380 dep->frame_number += max_t(u32, 4, dep->interval);
1381
1382 /* Reinitialize test variables */
1383 dep->start_cmd_status = 0;
1384 dep->combo_num = 0;
1385
1386 return __dwc3_gadget_kick_transfer(dep);
1387}
1388
1389static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1390{
1391 struct dwc3 *dwc = dep->dwc;
1392 int ret;
1393 int i;
1394
1395 if (list_empty(&dep->pending_list)) {
1396 dep->flags |= DWC3_EP_PENDING_REQUEST;
1397 return -EAGAIN;
1398 }
1399
1400 if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
1401 (dwc->revision <= DWC3_USB31_REVISION_160A ||
1402 (dwc->revision == DWC3_USB31_REVISION_170A &&
1403 dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
1404 dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {
1405
1406 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
1407 return dwc3_gadget_start_isoc_quirk(dep);
1408 }
1409
1410 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1411 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1412
1413 ret = __dwc3_gadget_kick_transfer(dep);
1414 if (ret != -EAGAIN)
1415 break;
1416 }
1417
1418 return ret;
1419}
1420
1421static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1422{
1423 struct dwc3 *dwc = dep->dwc;
1424
1425 if (!dep->endpoint.desc) {
1426 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1427 dep->name);
1428 return -ESHUTDOWN;
1429 }
1430
1431 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1432 &req->request, req->dep->name))
1433 return -EINVAL;
1434
1435 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1436 "%s: request %pK already in flight\n",
1437 dep->name, &req->request))
1438 return -EINVAL;
1439
1440 pm_runtime_get(dwc->dev);
1441
1442 req->request.actual = 0;
1443 req->request.status = -EINPROGRESS;
1444
1445 trace_dwc3_ep_queue(req);
1446
1447 list_add_tail(&req->list, &dep->pending_list);
1448 req->status = DWC3_REQUEST_STATUS_QUEUED;
1449
1450 /*
1451 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1452 * wait for a XferNotReady event so we will know what's the current
1453 * (micro-)frame number.
1454 *
1455 * Without this trick, we are very, very likely gonna get Bus Expiry
1456 * errors which will force us issue EndTransfer command.
1457 */
1458 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1459 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1460 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1461 return 0;
1462
1463 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1464 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1465 return __dwc3_gadget_start_isoc(dep);
1466 }
1467 }
1468 }
1469
1470 return __dwc3_gadget_kick_transfer(dep);
1471}
1472
1473static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1474 gfp_t gfp_flags)
1475{
1476 struct dwc3_request *req = to_dwc3_request(request);
1477 struct dwc3_ep *dep = to_dwc3_ep(ep);
1478 struct dwc3 *dwc = dep->dwc;
1479
1480 unsigned long flags;
1481
1482 int ret;
1483
1484 spin_lock_irqsave(&dwc->lock, flags);
1485 ret = __dwc3_gadget_ep_queue(dep, req);
1486 spin_unlock_irqrestore(&dwc->lock, flags);
1487
1488 return ret;
1489}
1490
1491static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1492{
1493 int i;
1494
1495 /*
1496 * If request was already started, this means we had to
1497 * stop the transfer. With that we also need to ignore
1498 * all TRBs used by the request, however TRBs can only
1499 * be modified after completion of END_TRANSFER
1500 * command. So what we do here is that we wait for
1501 * END_TRANSFER completion and only after that, we jump
1502 * over TRBs by clearing HWO and incrementing dequeue
1503 * pointer.
1504 */
1505 for (i = 0; i < req->num_trbs; i++) {
1506 struct dwc3_trb *trb;
1507
1508 trb = req->trb + i;
1509 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1510 dwc3_ep_inc_deq(dep);
1511 }
1512
1513 req->num_trbs = 0;
1514}
1515
1516static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1517{
1518 struct dwc3_request *req;
1519 struct dwc3_request *tmp;
1520
1521 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1522 dwc3_gadget_ep_skip_trbs(dep, req);
1523 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1524 }
1525}
1526
1527static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1528 struct usb_request *request)
1529{
1530 struct dwc3_request *req = to_dwc3_request(request);
1531 struct dwc3_request *r = NULL;
1532
1533 struct dwc3_ep *dep = to_dwc3_ep(ep);
1534 struct dwc3 *dwc = dep->dwc;
1535
1536 unsigned long flags;
1537 int ret = 0;
1538
1539 trace_dwc3_ep_dequeue(req);
1540
1541 spin_lock_irqsave(&dwc->lock, flags);
1542
1543 list_for_each_entry(r, &dep->pending_list, list) {
1544 if (r == req)
1545 break;
1546 }
1547
1548 if (r != req) {
1549 list_for_each_entry(r, &dep->started_list, list) {
1550 if (r == req)
1551 break;
1552 }
1553 if (r == req) {
1554 /* wait until it is processed */
1555 dwc3_stop_active_transfer(dep, true, true);
1556
1557 if (!r->trb)
1558 goto out0;
1559
1560 dwc3_gadget_move_cancelled_request(req);
1561 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
1562 goto out0;
1563 else
1564 goto out1;
1565 }
1566 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1567 request, ep->name);
1568 ret = -EINVAL;
1569 goto out0;
1570 }
1571
1572out1:
1573 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1574
1575out0:
1576 spin_unlock_irqrestore(&dwc->lock, flags);
1577
1578 return ret;
1579}
1580
1581int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1582{
1583 struct dwc3_gadget_ep_cmd_params params;
1584 struct dwc3 *dwc = dep->dwc;
1585 int ret;
1586
1587 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1588 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1589 return -EINVAL;
1590 }
1591
1592 memset(¶ms, 0x00, sizeof(params));
1593
1594 if (value) {
1595 struct dwc3_trb *trb;
1596
1597 unsigned transfer_in_flight;
1598 unsigned started;
1599
1600 if (dep->number > 1)
1601 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1602 else
1603 trb = &dwc->ep0_trb[dep->trb_enqueue];
1604
1605 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1606 started = !list_empty(&dep->started_list);
1607
1608 if (!protocol && ((dep->direction && transfer_in_flight) ||
1609 (!dep->direction && started))) {
1610 return -EAGAIN;
1611 }
1612
1613 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1614 ¶ms);
1615 if (ret)
1616 dev_err(dwc->dev, "failed to set STALL on %s\n",
1617 dep->name);
1618 else
1619 dep->flags |= DWC3_EP_STALL;
1620 } else {
1621
1622 ret = dwc3_send_clear_stall_ep_cmd(dep);
1623 if (ret)
1624 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1625 dep->name);
1626 else
1627 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1628 }
1629
1630 return ret;
1631}
1632
1633static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1634{
1635 struct dwc3_ep *dep = to_dwc3_ep(ep);
1636 struct dwc3 *dwc = dep->dwc;
1637
1638 unsigned long flags;
1639
1640 int ret;
1641
1642 spin_lock_irqsave(&dwc->lock, flags);
1643 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1644 spin_unlock_irqrestore(&dwc->lock, flags);
1645
1646 return ret;
1647}
1648
1649static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1650{
1651 struct dwc3_ep *dep = to_dwc3_ep(ep);
1652 struct dwc3 *dwc = dep->dwc;
1653 unsigned long flags;
1654 int ret;
1655
1656 spin_lock_irqsave(&dwc->lock, flags);
1657 dep->flags |= DWC3_EP_WEDGE;
1658
1659 if (dep->number == 0 || dep->number == 1)
1660 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1661 else
1662 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1663 spin_unlock_irqrestore(&dwc->lock, flags);
1664
1665 return ret;
1666}
1667
1668/* -------------------------------------------------------------------------- */
1669
1670static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1671 .bLength = USB_DT_ENDPOINT_SIZE,
1672 .bDescriptorType = USB_DT_ENDPOINT,
1673 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1674};
1675
1676static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1677 .enable = dwc3_gadget_ep0_enable,
1678 .disable = dwc3_gadget_ep0_disable,
1679 .alloc_request = dwc3_gadget_ep_alloc_request,
1680 .free_request = dwc3_gadget_ep_free_request,
1681 .queue = dwc3_gadget_ep0_queue,
1682 .dequeue = dwc3_gadget_ep_dequeue,
1683 .set_halt = dwc3_gadget_ep0_set_halt,
1684 .set_wedge = dwc3_gadget_ep_set_wedge,
1685};
1686
1687static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1688 .enable = dwc3_gadget_ep_enable,
1689 .disable = dwc3_gadget_ep_disable,
1690 .alloc_request = dwc3_gadget_ep_alloc_request,
1691 .free_request = dwc3_gadget_ep_free_request,
1692 .queue = dwc3_gadget_ep_queue,
1693 .dequeue = dwc3_gadget_ep_dequeue,
1694 .set_halt = dwc3_gadget_ep_set_halt,
1695 .set_wedge = dwc3_gadget_ep_set_wedge,
1696};
1697
1698/* -------------------------------------------------------------------------- */
1699
1700static int dwc3_gadget_get_frame(struct usb_gadget *g)
1701{
1702 struct dwc3 *dwc = gadget_to_dwc(g);
1703
1704 return __dwc3_gadget_get_frame(dwc);
1705}
1706
1707static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1708{
1709 int retries;
1710
1711 int ret;
1712 u32 reg;
1713
1714 u8 link_state;
1715 u8 speed;
1716
1717 /*
1718 * According to the Databook Remote wakeup request should
1719 * be issued only when the device is in early suspend state.
1720 *
1721 * We can check that via USB Link State bits in DSTS register.
1722 */
1723 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1724
1725 speed = reg & DWC3_DSTS_CONNECTSPD;
1726 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1727 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1728 return 0;
1729
1730 link_state = DWC3_DSTS_USBLNKST(reg);
1731
1732 switch (link_state) {
1733 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1734 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1735 break;
1736 default:
1737 return -EINVAL;
1738 }
1739
1740 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1741 if (ret < 0) {
1742 dev_err(dwc->dev, "failed to put link in Recovery\n");
1743 return ret;
1744 }
1745
1746 /* Recent versions do this automatically */
1747 if (dwc->revision < DWC3_REVISION_194A) {
1748 /* write zeroes to Link Change Request */
1749 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1750 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1751 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1752 }
1753
1754 /* poll until Link State changes to ON */
1755 retries = 20000;
1756
1757 while (retries--) {
1758 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1759
1760 /* in HS, means ON */
1761 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1762 break;
1763 }
1764
1765 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1766 dev_err(dwc->dev, "failed to send remote wakeup\n");
1767 return -EINVAL;
1768 }
1769
1770 return 0;
1771}
1772
1773static int dwc3_gadget_wakeup(struct usb_gadget *g)
1774{
1775 struct dwc3 *dwc = gadget_to_dwc(g);
1776 unsigned long flags;
1777 int ret;
1778
1779 spin_lock_irqsave(&dwc->lock, flags);
1780 ret = __dwc3_gadget_wakeup(dwc);
1781 spin_unlock_irqrestore(&dwc->lock, flags);
1782
1783 return ret;
1784}
1785
1786static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1787 int is_selfpowered)
1788{
1789 struct dwc3 *dwc = gadget_to_dwc(g);
1790 unsigned long flags;
1791
1792 spin_lock_irqsave(&dwc->lock, flags);
1793 g->is_selfpowered = !!is_selfpowered;
1794 spin_unlock_irqrestore(&dwc->lock, flags);
1795
1796 return 0;
1797}
1798
1799static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1800{
1801 u32 reg;
1802 u32 timeout = 500;
1803
1804 if (pm_runtime_suspended(dwc->dev))
1805 return 0;
1806
1807 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1808 if (is_on) {
1809 if (dwc->revision <= DWC3_REVISION_187A) {
1810 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1811 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1812 }
1813
1814 if (dwc->revision >= DWC3_REVISION_194A)
1815 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1816 reg |= DWC3_DCTL_RUN_STOP;
1817
1818 if (dwc->has_hibernation)
1819 reg |= DWC3_DCTL_KEEP_CONNECT;
1820
1821 dwc->pullups_connected = true;
1822 } else {
1823 reg &= ~DWC3_DCTL_RUN_STOP;
1824
1825 if (dwc->has_hibernation && !suspend)
1826 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1827
1828 dwc->pullups_connected = false;
1829 }
1830
1831 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1832
1833 do {
1834 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1835 reg &= DWC3_DSTS_DEVCTRLHLT;
1836 } while (--timeout && !(!is_on ^ !reg));
1837
1838 if (!timeout)
1839 return -ETIMEDOUT;
1840
1841 return 0;
1842}
1843
1844static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1845{
1846 struct dwc3 *dwc = gadget_to_dwc(g);
1847 unsigned long flags;
1848 int ret;
1849
1850 is_on = !!is_on;
1851
1852 /*
1853 * Per databook, when we want to stop the gadget, if a control transfer
1854 * is still in process, complete it and get the core into setup phase.
1855 */
1856 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1857 reinit_completion(&dwc->ep0_in_setup);
1858
1859 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1860 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1861 if (ret == 0) {
1862 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1863 return -ETIMEDOUT;
1864 }
1865 }
1866
1867 spin_lock_irqsave(&dwc->lock, flags);
1868 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1869 spin_unlock_irqrestore(&dwc->lock, flags);
1870
1871 return ret;
1872}
1873
1874static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1875{
1876 u32 reg;
1877
1878 /* Enable all but Start and End of Frame IRQs */
1879 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1880 DWC3_DEVTEN_EVNTOVERFLOWEN |
1881 DWC3_DEVTEN_CMDCMPLTEN |
1882 DWC3_DEVTEN_ERRTICERREN |
1883 DWC3_DEVTEN_WKUPEVTEN |
1884 DWC3_DEVTEN_CONNECTDONEEN |
1885 DWC3_DEVTEN_USBRSTEN |
1886 DWC3_DEVTEN_DISCONNEVTEN);
1887
1888 if (dwc->revision < DWC3_REVISION_250A)
1889 reg |= DWC3_DEVTEN_ULSTCNGEN;
1890
1891 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1892}
1893
1894static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1895{
1896 /* mask all interrupts */
1897 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1898}
1899
1900static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1901static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1902
1903/**
1904 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1905 * @dwc: pointer to our context structure
1906 *
1907 * The following looks like complex but it's actually very simple. In order to
1908 * calculate the number of packets we can burst at once on OUT transfers, we're
1909 * gonna use RxFIFO size.
1910 *
1911 * To calculate RxFIFO size we need two numbers:
1912 * MDWIDTH = size, in bits, of the internal memory bus
1913 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1914 *
1915 * Given these two numbers, the formula is simple:
1916 *
1917 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1918 *
1919 * 24 bytes is for 3x SETUP packets
1920 * 16 bytes is a clock domain crossing tolerance
1921 *
1922 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1923 */
1924static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1925{
1926 u32 ram2_depth;
1927 u32 mdwidth;
1928 u32 nump;
1929 u32 reg;
1930
1931 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1932 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1933
1934 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1935 nump = min_t(u32, nump, 16);
1936
1937 /* update NumP */
1938 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1939 reg &= ~DWC3_DCFG_NUMP_MASK;
1940 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1941 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1942}
1943
1944static int __dwc3_gadget_start(struct dwc3 *dwc)
1945{
1946 struct dwc3_ep *dep;
1947 int ret = 0;
1948 u32 reg;
1949
1950 /*
1951 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1952 * the core supports IMOD, disable it.
1953 */
1954 if (dwc->imod_interval) {
1955 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1956 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1957 } else if (dwc3_has_imod(dwc)) {
1958 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1959 }
1960
1961 /*
1962 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1963 * field instead of letting dwc3 itself calculate that automatically.
1964 *
1965 * This way, we maximize the chances that we'll be able to get several
1966 * bursts of data without going through any sort of endpoint throttling.
1967 */
1968 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1969 if (dwc3_is_usb31(dwc))
1970 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1971 else
1972 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1973
1974 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1975
1976 dwc3_gadget_setup_nump(dwc);
1977
1978 /* Start with SuperSpeed Default */
1979 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1980
1981 dep = dwc->eps[0];
1982 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1983 if (ret) {
1984 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1985 goto err0;
1986 }
1987
1988 dep = dwc->eps[1];
1989 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1990 if (ret) {
1991 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1992 goto err1;
1993 }
1994
1995 /* begin to receive SETUP packets */
1996 dwc->ep0state = EP0_SETUP_PHASE;
1997 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1998 dwc3_ep0_out_start(dwc);
1999
2000 dwc3_gadget_enable_irq(dwc);
2001
2002 return 0;
2003
2004err1:
2005 __dwc3_gadget_ep_disable(dwc->eps[0]);
2006
2007err0:
2008 return ret;
2009}
2010
2011static int dwc3_gadget_start(struct usb_gadget *g,
2012 struct usb_gadget_driver *driver)
2013{
2014 struct dwc3 *dwc = gadget_to_dwc(g);
2015 unsigned long flags;
2016 int ret = 0;
2017 int irq;
2018
2019 irq = dwc->irq_gadget;
2020 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2021 IRQF_SHARED, "dwc3", dwc->ev_buf);
2022 if (ret) {
2023 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2024 irq, ret);
2025 goto err0;
2026 }
2027
2028 spin_lock_irqsave(&dwc->lock, flags);
2029 if (dwc->gadget_driver) {
2030 dev_err(dwc->dev, "%s is already bound to %s\n",
2031 dwc->gadget.name,
2032 dwc->gadget_driver->driver.name);
2033 ret = -EBUSY;
2034 goto err1;
2035 }
2036
2037 dwc->gadget_driver = driver;
2038
2039 if (pm_runtime_active(dwc->dev))
2040 __dwc3_gadget_start(dwc);
2041
2042 spin_unlock_irqrestore(&dwc->lock, flags);
2043
2044 return 0;
2045
2046err1:
2047 spin_unlock_irqrestore(&dwc->lock, flags);
2048 free_irq(irq, dwc);
2049
2050err0:
2051 return ret;
2052}
2053
2054static void __dwc3_gadget_stop(struct dwc3 *dwc)
2055{
2056 dwc3_gadget_disable_irq(dwc);
2057 __dwc3_gadget_ep_disable(dwc->eps[0]);
2058 __dwc3_gadget_ep_disable(dwc->eps[1]);
2059}
2060
2061static int dwc3_gadget_stop(struct usb_gadget *g)
2062{
2063 struct dwc3 *dwc = gadget_to_dwc(g);
2064 unsigned long flags;
2065
2066 spin_lock_irqsave(&dwc->lock, flags);
2067
2068 if (pm_runtime_suspended(dwc->dev))
2069 goto out;
2070
2071 __dwc3_gadget_stop(dwc);
2072
2073out:
2074 dwc->gadget_driver = NULL;
2075 spin_unlock_irqrestore(&dwc->lock, flags);
2076
2077 free_irq(dwc->irq_gadget, dwc->ev_buf);
2078
2079 return 0;
2080}
2081
2082static void dwc3_gadget_config_params(struct usb_gadget *g,
2083 struct usb_dcd_config_params *params)
2084{
2085 struct dwc3 *dwc = gadget_to_dwc(g);
2086
2087 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2088 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2089
2090 /* Recommended BESL */
2091 if (!dwc->dis_enblslpm_quirk) {
2092 /*
2093 * If the recommended BESL baseline is 0 or if the BESL deep is
2094 * less than 2, Microsoft's Windows 10 host usb stack will issue
2095 * a usb reset immediately after it receives the extended BOS
2096 * descriptor and the enumeration will fail. To maintain
2097 * compatibility with the Windows' usb stack, let's set the
2098 * recommended BESL baseline to 1 and clamp the BESL deep to be
2099 * within 2 to 15.
2100 */
2101 params->besl_baseline = 1;
2102 if (dwc->is_utmi_l1_suspend)
2103 params->besl_deep =
2104 clamp_t(u8, dwc->hird_threshold, 2, 15);
2105 }
2106
2107 /* U1 Device exit Latency */
2108 if (dwc->dis_u1_entry_quirk)
2109 params->bU1devExitLat = 0;
2110 else
2111 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2112
2113 /* U2 Device exit Latency */
2114 if (dwc->dis_u2_entry_quirk)
2115 params->bU2DevExitLat = 0;
2116 else
2117 params->bU2DevExitLat =
2118 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2119}
2120
2121static void dwc3_gadget_set_speed(struct usb_gadget *g,
2122 enum usb_device_speed speed)
2123{
2124 struct dwc3 *dwc = gadget_to_dwc(g);
2125 unsigned long flags;
2126 u32 reg;
2127
2128 spin_lock_irqsave(&dwc->lock, flags);
2129 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2130 reg &= ~(DWC3_DCFG_SPEED_MASK);
2131
2132 /*
2133 * WORKAROUND: DWC3 revision < 2.20a have an issue
2134 * which would cause metastability state on Run/Stop
2135 * bit if we try to force the IP to USB2-only mode.
2136 *
2137 * Because of that, we cannot configure the IP to any
2138 * speed other than the SuperSpeed
2139 *
2140 * Refers to:
2141 *
2142 * STAR#9000525659: Clock Domain Crossing on DCTL in
2143 * USB 2.0 Mode
2144 */
2145 if (dwc->revision < DWC3_REVISION_220A &&
2146 !dwc->dis_metastability_quirk) {
2147 reg |= DWC3_DCFG_SUPERSPEED;
2148 } else {
2149 switch (speed) {
2150 case USB_SPEED_LOW:
2151 reg |= DWC3_DCFG_LOWSPEED;
2152 break;
2153 case USB_SPEED_FULL:
2154 reg |= DWC3_DCFG_FULLSPEED;
2155 break;
2156 case USB_SPEED_HIGH:
2157 reg |= DWC3_DCFG_HIGHSPEED;
2158 break;
2159 case USB_SPEED_SUPER:
2160 reg |= DWC3_DCFG_SUPERSPEED;
2161 break;
2162 case USB_SPEED_SUPER_PLUS:
2163 if (dwc3_is_usb31(dwc))
2164 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2165 else
2166 reg |= DWC3_DCFG_SUPERSPEED;
2167 break;
2168 default:
2169 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2170
2171 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2172 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2173 else
2174 reg |= DWC3_DCFG_SUPERSPEED;
2175 }
2176 }
2177 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2178
2179 spin_unlock_irqrestore(&dwc->lock, flags);
2180}
2181
2182static const struct usb_gadget_ops dwc3_gadget_ops = {
2183 .get_frame = dwc3_gadget_get_frame,
2184 .wakeup = dwc3_gadget_wakeup,
2185 .set_selfpowered = dwc3_gadget_set_selfpowered,
2186 .pullup = dwc3_gadget_pullup,
2187 .udc_start = dwc3_gadget_start,
2188 .udc_stop = dwc3_gadget_stop,
2189 .udc_set_speed = dwc3_gadget_set_speed,
2190 .get_config_params = dwc3_gadget_config_params,
2191};
2192
2193/* -------------------------------------------------------------------------- */
2194
2195static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2196{
2197 struct dwc3 *dwc = dep->dwc;
2198
2199 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2200 dep->endpoint.maxburst = 1;
2201 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2202 if (!dep->direction)
2203 dwc->gadget.ep0 = &dep->endpoint;
2204
2205 dep->endpoint.caps.type_control = true;
2206
2207 return 0;
2208}
2209
2210static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2211{
2212 struct dwc3 *dwc = dep->dwc;
2213 int mdwidth;
2214 int kbytes;
2215 int size;
2216
2217 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2218 /* MDWIDTH is represented in bits, we need it in bytes */
2219 mdwidth /= 8;
2220
2221 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2222 if (dwc3_is_usb31(dwc))
2223 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2224 else
2225 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2226
2227 /* FIFO Depth is in MDWDITH bytes. Multiply */
2228 size *= mdwidth;
2229
2230 kbytes = size / 1024;
2231 if (kbytes == 0)
2232 kbytes = 1;
2233
2234 /*
2235 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2236 * internal overhead. We don't really know how these are used,
2237 * but documentation say it exists.
2238 */
2239 size -= mdwidth * (kbytes + 1);
2240 size /= kbytes;
2241
2242 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2243
2244 dep->endpoint.max_streams = 15;
2245 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2246 list_add_tail(&dep->endpoint.ep_list,
2247 &dwc->gadget.ep_list);
2248 dep->endpoint.caps.type_iso = true;
2249 dep->endpoint.caps.type_bulk = true;
2250 dep->endpoint.caps.type_int = true;
2251
2252 return dwc3_alloc_trb_pool(dep);
2253}
2254
2255static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2256{
2257 struct dwc3 *dwc = dep->dwc;
2258
2259 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2260 dep->endpoint.max_streams = 15;
2261 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2262 list_add_tail(&dep->endpoint.ep_list,
2263 &dwc->gadget.ep_list);
2264 dep->endpoint.caps.type_iso = true;
2265 dep->endpoint.caps.type_bulk = true;
2266 dep->endpoint.caps.type_int = true;
2267
2268 return dwc3_alloc_trb_pool(dep);
2269}
2270
2271static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2272{
2273 struct dwc3_ep *dep;
2274 bool direction = epnum & 1;
2275 int ret;
2276 u8 num = epnum >> 1;
2277
2278 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2279 if (!dep)
2280 return -ENOMEM;
2281
2282 dep->dwc = dwc;
2283 dep->number = epnum;
2284 dep->direction = direction;
2285 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2286 dwc->eps[epnum] = dep;
2287 dep->combo_num = 0;
2288 dep->start_cmd_status = 0;
2289
2290 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2291 direction ? "in" : "out");
2292
2293 dep->endpoint.name = dep->name;
2294
2295 if (!(dep->number > 1)) {
2296 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2297 dep->endpoint.comp_desc = NULL;
2298 }
2299
2300 if (num == 0)
2301 ret = dwc3_gadget_init_control_endpoint(dep);
2302 else if (direction)
2303 ret = dwc3_gadget_init_in_endpoint(dep);
2304 else
2305 ret = dwc3_gadget_init_out_endpoint(dep);
2306
2307 if (ret)
2308 return ret;
2309
2310 dep->endpoint.caps.dir_in = direction;
2311 dep->endpoint.caps.dir_out = !direction;
2312
2313 INIT_LIST_HEAD(&dep->pending_list);
2314 INIT_LIST_HEAD(&dep->started_list);
2315 INIT_LIST_HEAD(&dep->cancelled_list);
2316
2317 return 0;
2318}
2319
2320static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2321{
2322 u8 epnum;
2323
2324 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2325
2326 for (epnum = 0; epnum < total; epnum++) {
2327 int ret;
2328
2329 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2330 if (ret)
2331 return ret;
2332 }
2333
2334 return 0;
2335}
2336
2337static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2338{
2339 struct dwc3_ep *dep;
2340 u8 epnum;
2341
2342 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2343 dep = dwc->eps[epnum];
2344 if (!dep)
2345 continue;
2346 /*
2347 * Physical endpoints 0 and 1 are special; they form the
2348 * bi-directional USB endpoint 0.
2349 *
2350 * For those two physical endpoints, we don't allocate a TRB
2351 * pool nor do we add them the endpoints list. Due to that, we
2352 * shouldn't do these two operations otherwise we would end up
2353 * with all sorts of bugs when removing dwc3.ko.
2354 */
2355 if (epnum != 0 && epnum != 1) {
2356 dwc3_free_trb_pool(dep);
2357 list_del(&dep->endpoint.ep_list);
2358 }
2359
2360 kfree(dep);
2361 }
2362}
2363
2364/* -------------------------------------------------------------------------- */
2365
2366static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2367 struct dwc3_request *req, struct dwc3_trb *trb,
2368 const struct dwc3_event_depevt *event, int status, int chain)
2369{
2370 unsigned int count;
2371
2372 dwc3_ep_inc_deq(dep);
2373
2374 trace_dwc3_complete_trb(dep, trb);
2375 req->num_trbs--;
2376
2377 /*
2378 * If we're in the middle of series of chained TRBs and we
2379 * receive a short transfer along the way, DWC3 will skip
2380 * through all TRBs including the last TRB in the chain (the
2381 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2382 * bit and SW has to do it manually.
2383 *
2384 * We're going to do that here to avoid problems of HW trying
2385 * to use bogus TRBs for transfers.
2386 */
2387 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2388 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2389
2390 /*
2391 * For isochronous transfers, the first TRB in a service interval must
2392 * have the Isoc-First type. Track and report its interval frame number.
2393 */
2394 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2395 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2396 unsigned int frame_number;
2397
2398 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2399 frame_number &= ~(dep->interval - 1);
2400 req->request.frame_number = frame_number;
2401 }
2402
2403 /*
2404 * If we're dealing with unaligned size OUT transfer, we will be left
2405 * with one TRB pending in the ring. We need to manually clear HWO bit
2406 * from that TRB.
2407 */
2408
2409 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2410 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2411 return 1;
2412 }
2413
2414 count = trb->size & DWC3_TRB_SIZE_MASK;
2415 req->remaining += count;
2416
2417 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2418 return 1;
2419
2420 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2421 return 1;
2422
2423 if (event->status & DEPEVT_STATUS_IOC)
2424 return 1;
2425
2426 return 0;
2427}
2428
2429static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2430 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2431 int status)
2432{
2433 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2434 struct scatterlist *sg = req->sg;
2435 struct scatterlist *s;
2436 unsigned int pending = req->num_pending_sgs;
2437 unsigned int i;
2438 int ret = 0;
2439
2440 for_each_sg(sg, s, pending, i) {
2441 trb = &dep->trb_pool[dep->trb_dequeue];
2442
2443 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2444 break;
2445
2446 req->sg = sg_next(s);
2447 req->num_pending_sgs--;
2448
2449 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2450 trb, event, status, true);
2451 if (ret)
2452 break;
2453 }
2454
2455 return ret;
2456}
2457
2458static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2459 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2460 int status)
2461{
2462 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2463
2464 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2465 event, status, false);
2466}
2467
2468static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2469{
2470 return req->request.actual == req->request.length;
2471}
2472
2473static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2474 const struct dwc3_event_depevt *event,
2475 struct dwc3_request *req, int status)
2476{
2477 int ret;
2478
2479 if (req->num_pending_sgs)
2480 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2481 status);
2482 else
2483 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2484 status);
2485
2486 if (req->needs_extra_trb) {
2487 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2488 status);
2489 req->needs_extra_trb = false;
2490 }
2491
2492 req->request.actual = req->request.length - req->remaining;
2493
2494 if (!dwc3_gadget_ep_request_completed(req) &&
2495 req->num_pending_sgs) {
2496 __dwc3_gadget_kick_transfer(dep);
2497 goto out;
2498 }
2499
2500 dwc3_gadget_giveback(dep, req, status);
2501
2502out:
2503 return ret;
2504}
2505
2506static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2507 const struct dwc3_event_depevt *event, int status)
2508{
2509 struct dwc3_request *req;
2510 struct dwc3_request *tmp;
2511
2512 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2513 int ret;
2514
2515 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2516 req, status);
2517 if (ret)
2518 break;
2519 }
2520}
2521
2522static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2523 const struct dwc3_event_depevt *event)
2524{
2525 dep->frame_number = event->parameters;
2526}
2527
2528static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2529 const struct dwc3_event_depevt *event)
2530{
2531 struct dwc3 *dwc = dep->dwc;
2532 unsigned status = 0;
2533 bool stop = false;
2534
2535 dwc3_gadget_endpoint_frame_from_event(dep, event);
2536
2537 if (event->status & DEPEVT_STATUS_BUSERR)
2538 status = -ECONNRESET;
2539
2540 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2541 status = -EXDEV;
2542
2543 if (list_empty(&dep->started_list))
2544 stop = true;
2545 }
2546
2547 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2548
2549 if (stop) {
2550 dwc3_stop_active_transfer(dep, true, true);
2551 dep->flags = DWC3_EP_ENABLED;
2552 }
2553
2554 /*
2555 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2556 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2557 */
2558 if (dwc->revision < DWC3_REVISION_183A) {
2559 u32 reg;
2560 int i;
2561
2562 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2563 dep = dwc->eps[i];
2564
2565 if (!(dep->flags & DWC3_EP_ENABLED))
2566 continue;
2567
2568 if (!list_empty(&dep->started_list))
2569 return;
2570 }
2571
2572 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2573 reg |= dwc->u1u2;
2574 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2575
2576 dwc->u1u2 = 0;
2577 }
2578}
2579
2580static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2581 const struct dwc3_event_depevt *event)
2582{
2583 dwc3_gadget_endpoint_frame_from_event(dep, event);
2584 (void) __dwc3_gadget_start_isoc(dep);
2585}
2586
2587static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2588 const struct dwc3_event_depevt *event)
2589{
2590 struct dwc3_ep *dep;
2591 u8 epnum = event->endpoint_number;
2592 u8 cmd;
2593
2594 dep = dwc->eps[epnum];
2595
2596 if (!(dep->flags & DWC3_EP_ENABLED)) {
2597 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2598 return;
2599
2600 /* Handle only EPCMDCMPLT when EP disabled */
2601 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2602 return;
2603 }
2604
2605 if (epnum == 0 || epnum == 1) {
2606 dwc3_ep0_interrupt(dwc, event);
2607 return;
2608 }
2609
2610 switch (event->endpoint_event) {
2611 case DWC3_DEPEVT_XFERINPROGRESS:
2612 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2613 break;
2614 case DWC3_DEPEVT_XFERNOTREADY:
2615 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2616 break;
2617 case DWC3_DEPEVT_EPCMDCMPLT:
2618 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2619
2620 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2621 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2622 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2623 }
2624 break;
2625 case DWC3_DEPEVT_STREAMEVT:
2626 case DWC3_DEPEVT_XFERCOMPLETE:
2627 case DWC3_DEPEVT_RXTXFIFOEVT:
2628 break;
2629 }
2630}
2631
2632static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2633{
2634 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2635 spin_unlock(&dwc->lock);
2636 dwc->gadget_driver->disconnect(&dwc->gadget);
2637 spin_lock(&dwc->lock);
2638 }
2639}
2640
2641static void dwc3_suspend_gadget(struct dwc3 *dwc)
2642{
2643 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2644 spin_unlock(&dwc->lock);
2645 dwc->gadget_driver->suspend(&dwc->gadget);
2646 spin_lock(&dwc->lock);
2647 }
2648}
2649
2650static void dwc3_resume_gadget(struct dwc3 *dwc)
2651{
2652 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2653 spin_unlock(&dwc->lock);
2654 dwc->gadget_driver->resume(&dwc->gadget);
2655 spin_lock(&dwc->lock);
2656 }
2657}
2658
2659static void dwc3_reset_gadget(struct dwc3 *dwc)
2660{
2661 if (!dwc->gadget_driver)
2662 return;
2663
2664 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2665 spin_unlock(&dwc->lock);
2666 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2667 spin_lock(&dwc->lock);
2668 }
2669}
2670
2671static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
2672 bool interrupt)
2673{
2674 struct dwc3 *dwc = dep->dwc;
2675 struct dwc3_gadget_ep_cmd_params params;
2676 u32 cmd;
2677 int ret;
2678
2679 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2680 return;
2681
2682 /*
2683 * NOTICE: We are violating what the Databook says about the
2684 * EndTransfer command. Ideally we would _always_ wait for the
2685 * EndTransfer Command Completion IRQ, but that's causing too
2686 * much trouble synchronizing between us and gadget driver.
2687 *
2688 * We have discussed this with the IP Provider and it was
2689 * suggested to giveback all requests here, but give HW some
2690 * extra time to synchronize with the interconnect. We're using
2691 * an arbitrary 100us delay for that.
2692 *
2693 * Note also that a similar handling was tested by Synopsys
2694 * (thanks a lot Paul) and nothing bad has come out of it.
2695 * In short, what we're doing is:
2696 *
2697 * - Issue EndTransfer WITH CMDIOC bit set
2698 * - Wait 100us
2699 *
2700 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2701 * supports a mode to work around the above limitation. The
2702 * software can poll the CMDACT bit in the DEPCMD register
2703 * after issuing a EndTransfer command. This mode is enabled
2704 * by writing GUCTL2[14]. This polling is already done in the
2705 * dwc3_send_gadget_ep_cmd() function so if the mode is
2706 * enabled, the EndTransfer command will have completed upon
2707 * returning from this function and we don't need to delay for
2708 * 100us.
2709 *
2710 * This mode is NOT available on the DWC_usb31 IP.
2711 */
2712
2713 cmd = DWC3_DEPCMD_ENDTRANSFER;
2714 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2715 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
2716 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2717 memset(¶ms, 0, sizeof(params));
2718 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2719 WARN_ON_ONCE(ret);
2720 dep->resource_index = 0;
2721
2722 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A)
2723 udelay(100);
2724}
2725
2726static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2727{
2728 u32 epnum;
2729
2730 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2731 struct dwc3_ep *dep;
2732 int ret;
2733
2734 dep = dwc->eps[epnum];
2735 if (!dep)
2736 continue;
2737
2738 if (!(dep->flags & DWC3_EP_STALL))
2739 continue;
2740
2741 dep->flags &= ~DWC3_EP_STALL;
2742
2743 ret = dwc3_send_clear_stall_ep_cmd(dep);
2744 WARN_ON_ONCE(ret);
2745 }
2746}
2747
2748static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2749{
2750 int reg;
2751
2752 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2753 reg &= ~DWC3_DCTL_INITU1ENA;
2754 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2755
2756 reg &= ~DWC3_DCTL_INITU2ENA;
2757 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2758
2759 dwc3_disconnect_gadget(dwc);
2760
2761 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2762 dwc->setup_packet_pending = false;
2763 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2764
2765 dwc->connected = false;
2766}
2767
2768static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2769{
2770 u32 reg;
2771
2772 dwc->connected = true;
2773
2774 /*
2775 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2776 * would cause a missing Disconnect Event if there's a
2777 * pending Setup Packet in the FIFO.
2778 *
2779 * There's no suggested workaround on the official Bug
2780 * report, which states that "unless the driver/application
2781 * is doing any special handling of a disconnect event,
2782 * there is no functional issue".
2783 *
2784 * Unfortunately, it turns out that we _do_ some special
2785 * handling of a disconnect event, namely complete all
2786 * pending transfers, notify gadget driver of the
2787 * disconnection, and so on.
2788 *
2789 * Our suggested workaround is to follow the Disconnect
2790 * Event steps here, instead, based on a setup_packet_pending
2791 * flag. Such flag gets set whenever we have a SETUP_PENDING
2792 * status for EP0 TRBs and gets cleared on XferComplete for the
2793 * same endpoint.
2794 *
2795 * Refers to:
2796 *
2797 * STAR#9000466709: RTL: Device : Disconnect event not
2798 * generated if setup packet pending in FIFO
2799 */
2800 if (dwc->revision < DWC3_REVISION_188A) {
2801 if (dwc->setup_packet_pending)
2802 dwc3_gadget_disconnect_interrupt(dwc);
2803 }
2804
2805 dwc3_reset_gadget(dwc);
2806
2807 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2808 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2809 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2810 dwc->test_mode = false;
2811 dwc3_clear_stall_all_ep(dwc);
2812
2813 /* Reset device address to zero */
2814 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2815 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2816 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2817}
2818
2819static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2820{
2821 struct dwc3_ep *dep;
2822 int ret;
2823 u32 reg;
2824 u8 speed;
2825
2826 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2827 speed = reg & DWC3_DSTS_CONNECTSPD;
2828 dwc->speed = speed;
2829
2830 /*
2831 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2832 * each time on Connect Done.
2833 *
2834 * Currently we always use the reset value. If any platform
2835 * wants to set this to a different value, we need to add a
2836 * setting and update GCTL.RAMCLKSEL here.
2837 */
2838
2839 switch (speed) {
2840 case DWC3_DSTS_SUPERSPEED_PLUS:
2841 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2842 dwc->gadget.ep0->maxpacket = 512;
2843 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2844 break;
2845 case DWC3_DSTS_SUPERSPEED:
2846 /*
2847 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2848 * would cause a missing USB3 Reset event.
2849 *
2850 * In such situations, we should force a USB3 Reset
2851 * event by calling our dwc3_gadget_reset_interrupt()
2852 * routine.
2853 *
2854 * Refers to:
2855 *
2856 * STAR#9000483510: RTL: SS : USB3 reset event may
2857 * not be generated always when the link enters poll
2858 */
2859 if (dwc->revision < DWC3_REVISION_190A)
2860 dwc3_gadget_reset_interrupt(dwc);
2861
2862 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2863 dwc->gadget.ep0->maxpacket = 512;
2864 dwc->gadget.speed = USB_SPEED_SUPER;
2865 break;
2866 case DWC3_DSTS_HIGHSPEED:
2867 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2868 dwc->gadget.ep0->maxpacket = 64;
2869 dwc->gadget.speed = USB_SPEED_HIGH;
2870 break;
2871 case DWC3_DSTS_FULLSPEED:
2872 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2873 dwc->gadget.ep0->maxpacket = 64;
2874 dwc->gadget.speed = USB_SPEED_FULL;
2875 break;
2876 case DWC3_DSTS_LOWSPEED:
2877 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2878 dwc->gadget.ep0->maxpacket = 8;
2879 dwc->gadget.speed = USB_SPEED_LOW;
2880 break;
2881 }
2882
2883 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2884
2885 /* Enable USB2 LPM Capability */
2886
2887 if ((dwc->revision > DWC3_REVISION_194A) &&
2888 (speed != DWC3_DSTS_SUPERSPEED) &&
2889 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2890 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2891 reg |= DWC3_DCFG_LPM_CAP;
2892 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2893
2894 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2895 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2896
2897 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
2898 (dwc->is_utmi_l1_suspend << 4));
2899
2900 /*
2901 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2902 * DCFG.LPMCap is set, core responses with an ACK and the
2903 * BESL value in the LPM token is less than or equal to LPM
2904 * NYET threshold.
2905 */
2906 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2907 && dwc->has_lpm_erratum,
2908 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2909
2910 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2911 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
2912
2913 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2914 } else {
2915 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2916 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2917 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2918 }
2919
2920 dep = dwc->eps[0];
2921 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2922 if (ret) {
2923 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2924 return;
2925 }
2926
2927 dep = dwc->eps[1];
2928 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2929 if (ret) {
2930 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2931 return;
2932 }
2933
2934 /*
2935 * Configure PHY via GUSB3PIPECTLn if required.
2936 *
2937 * Update GTXFIFOSIZn
2938 *
2939 * In both cases reset values should be sufficient.
2940 */
2941}
2942
2943static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2944{
2945 /*
2946 * TODO take core out of low power mode when that's
2947 * implemented.
2948 */
2949
2950 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2951 spin_unlock(&dwc->lock);
2952 dwc->gadget_driver->resume(&dwc->gadget);
2953 spin_lock(&dwc->lock);
2954 }
2955}
2956
2957static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2958 unsigned int evtinfo)
2959{
2960 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2961 unsigned int pwropt;
2962
2963 /*
2964 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2965 * Hibernation mode enabled which would show up when device detects
2966 * host-initiated U3 exit.
2967 *
2968 * In that case, device will generate a Link State Change Interrupt
2969 * from U3 to RESUME which is only necessary if Hibernation is
2970 * configured in.
2971 *
2972 * There are no functional changes due to such spurious event and we
2973 * just need to ignore it.
2974 *
2975 * Refers to:
2976 *
2977 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2978 * operational mode
2979 */
2980 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2981 if ((dwc->revision < DWC3_REVISION_250A) &&
2982 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2983 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2984 (next == DWC3_LINK_STATE_RESUME)) {
2985 return;
2986 }
2987 }
2988
2989 /*
2990 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2991 * on the link partner, the USB session might do multiple entry/exit
2992 * of low power states before a transfer takes place.
2993 *
2994 * Due to this problem, we might experience lower throughput. The
2995 * suggested workaround is to disable DCTL[12:9] bits if we're
2996 * transitioning from U1/U2 to U0 and enable those bits again
2997 * after a transfer completes and there are no pending transfers
2998 * on any of the enabled endpoints.
2999 *
3000 * This is the first half of that workaround.
3001 *
3002 * Refers to:
3003 *
3004 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3005 * core send LGO_Ux entering U0
3006 */
3007 if (dwc->revision < DWC3_REVISION_183A) {
3008 if (next == DWC3_LINK_STATE_U0) {
3009 u32 u1u2;
3010 u32 reg;
3011
3012 switch (dwc->link_state) {
3013 case DWC3_LINK_STATE_U1:
3014 case DWC3_LINK_STATE_U2:
3015 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3016 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3017 | DWC3_DCTL_ACCEPTU2ENA
3018 | DWC3_DCTL_INITU1ENA
3019 | DWC3_DCTL_ACCEPTU1ENA);
3020
3021 if (!dwc->u1u2)
3022 dwc->u1u2 = reg & u1u2;
3023
3024 reg &= ~u1u2;
3025
3026 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3027 break;
3028 default:
3029 /* do nothing */
3030 break;
3031 }
3032 }
3033 }
3034
3035 switch (next) {
3036 case DWC3_LINK_STATE_U1:
3037 if (dwc->speed == USB_SPEED_SUPER)
3038 dwc3_suspend_gadget(dwc);
3039 break;
3040 case DWC3_LINK_STATE_U2:
3041 case DWC3_LINK_STATE_U3:
3042 dwc3_suspend_gadget(dwc);
3043 break;
3044 case DWC3_LINK_STATE_RESUME:
3045 dwc3_resume_gadget(dwc);
3046 break;
3047 default:
3048 /* do nothing */
3049 break;
3050 }
3051
3052 dwc->link_state = next;
3053}
3054
3055static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3056 unsigned int evtinfo)
3057{
3058 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3059
3060 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3061 dwc3_suspend_gadget(dwc);
3062
3063 dwc->link_state = next;
3064}
3065
3066static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3067 unsigned int evtinfo)
3068{
3069 unsigned int is_ss = evtinfo & BIT(4);
3070
3071 /*
3072 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3073 * have a known issue which can cause USB CV TD.9.23 to fail
3074 * randomly.
3075 *
3076 * Because of this issue, core could generate bogus hibernation
3077 * events which SW needs to ignore.
3078 *
3079 * Refers to:
3080 *
3081 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3082 * Device Fallback from SuperSpeed
3083 */
3084 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3085 return;
3086
3087 /* enter hibernation here */
3088}
3089
3090static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3091 const struct dwc3_event_devt *event)
3092{
3093 switch (event->type) {
3094 case DWC3_DEVICE_EVENT_DISCONNECT:
3095 dwc3_gadget_disconnect_interrupt(dwc);
3096 break;
3097 case DWC3_DEVICE_EVENT_RESET:
3098 dwc3_gadget_reset_interrupt(dwc);
3099 break;
3100 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3101 dwc3_gadget_conndone_interrupt(dwc);
3102 break;
3103 case DWC3_DEVICE_EVENT_WAKEUP:
3104 dwc3_gadget_wakeup_interrupt(dwc);
3105 break;
3106 case DWC3_DEVICE_EVENT_HIBER_REQ:
3107 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3108 "unexpected hibernation event\n"))
3109 break;
3110
3111 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3112 break;
3113 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3114 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3115 break;
3116 case DWC3_DEVICE_EVENT_EOPF:
3117 /* It changed to be suspend event for version 2.30a and above */
3118 if (dwc->revision >= DWC3_REVISION_230A) {
3119 /*
3120 * Ignore suspend event until the gadget enters into
3121 * USB_STATE_CONFIGURED state.
3122 */
3123 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3124 dwc3_gadget_suspend_interrupt(dwc,
3125 event->event_info);
3126 }
3127 break;
3128 case DWC3_DEVICE_EVENT_SOF:
3129 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3130 case DWC3_DEVICE_EVENT_CMD_CMPL:
3131 case DWC3_DEVICE_EVENT_OVERFLOW:
3132 break;
3133 default:
3134 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3135 }
3136}
3137
3138static void dwc3_process_event_entry(struct dwc3 *dwc,
3139 const union dwc3_event *event)
3140{
3141 trace_dwc3_event(event->raw, dwc);
3142
3143 if (!event->type.is_devspec)
3144 dwc3_endpoint_interrupt(dwc, &event->depevt);
3145 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3146 dwc3_gadget_interrupt(dwc, &event->devt);
3147 else
3148 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3149}
3150
3151static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3152{
3153 struct dwc3 *dwc = evt->dwc;
3154 irqreturn_t ret = IRQ_NONE;
3155 int left;
3156 u32 reg;
3157
3158 left = evt->count;
3159
3160 if (!(evt->flags & DWC3_EVENT_PENDING))
3161 return IRQ_NONE;
3162
3163 while (left > 0) {
3164 union dwc3_event event;
3165
3166 event.raw = *(u32 *) (evt->cache + evt->lpos);
3167
3168 dwc3_process_event_entry(dwc, &event);
3169
3170 /*
3171 * FIXME we wrap around correctly to the next entry as
3172 * almost all entries are 4 bytes in size. There is one
3173 * entry which has 12 bytes which is a regular entry
3174 * followed by 8 bytes data. ATM I don't know how
3175 * things are organized if we get next to the a
3176 * boundary so I worry about that once we try to handle
3177 * that.
3178 */
3179 evt->lpos = (evt->lpos + 4) % evt->length;
3180 left -= 4;
3181 }
3182
3183 evt->count = 0;
3184 evt->flags &= ~DWC3_EVENT_PENDING;
3185 ret = IRQ_HANDLED;
3186
3187 /* Unmask interrupt */
3188 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3189 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3190 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3191
3192 if (dwc->imod_interval) {
3193 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3194 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3195 }
3196
3197 return ret;
3198}
3199
3200static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3201{
3202 struct dwc3_event_buffer *evt = _evt;
3203 struct dwc3 *dwc = evt->dwc;
3204 unsigned long flags;
3205 irqreturn_t ret = IRQ_NONE;
3206
3207 spin_lock_irqsave(&dwc->lock, flags);
3208 ret = dwc3_process_event_buf(evt);
3209 spin_unlock_irqrestore(&dwc->lock, flags);
3210
3211 return ret;
3212}
3213
3214static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3215{
3216 struct dwc3 *dwc = evt->dwc;
3217 u32 amount;
3218 u32 count;
3219 u32 reg;
3220
3221 if (pm_runtime_suspended(dwc->dev)) {
3222 pm_runtime_get(dwc->dev);
3223 disable_irq_nosync(dwc->irq_gadget);
3224 dwc->pending_events = true;
3225 return IRQ_HANDLED;
3226 }
3227
3228 /*
3229 * With PCIe legacy interrupt, test shows that top-half irq handler can
3230 * be called again after HW interrupt deassertion. Check if bottom-half
3231 * irq event handler completes before caching new event to prevent
3232 * losing events.
3233 */
3234 if (evt->flags & DWC3_EVENT_PENDING)
3235 return IRQ_HANDLED;
3236
3237 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3238 count &= DWC3_GEVNTCOUNT_MASK;
3239 if (!count)
3240 return IRQ_NONE;
3241
3242 evt->count = count;
3243 evt->flags |= DWC3_EVENT_PENDING;
3244
3245 /* Mask interrupt */
3246 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3247 reg |= DWC3_GEVNTSIZ_INTMASK;
3248 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3249
3250 amount = min(count, evt->length - evt->lpos);
3251 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3252
3253 if (amount < count)
3254 memcpy(evt->cache, evt->buf, count - amount);
3255
3256 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3257
3258 return IRQ_WAKE_THREAD;
3259}
3260
3261static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3262{
3263 struct dwc3_event_buffer *evt = _evt;
3264
3265 return dwc3_check_event_buf(evt);
3266}
3267
3268static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3269{
3270 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3271 int irq;
3272
3273 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3274 if (irq > 0)
3275 goto out;
3276
3277 if (irq == -EPROBE_DEFER)
3278 goto out;
3279
3280 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3281 if (irq > 0)
3282 goto out;
3283
3284 if (irq == -EPROBE_DEFER)
3285 goto out;
3286
3287 irq = platform_get_irq(dwc3_pdev, 0);
3288 if (irq > 0)
3289 goto out;
3290
3291 if (!irq)
3292 irq = -EINVAL;
3293
3294out:
3295 return irq;
3296}
3297
3298/**
3299 * dwc3_gadget_init - initializes gadget related registers
3300 * @dwc: pointer to our controller context structure
3301 *
3302 * Returns 0 on success otherwise negative errno.
3303 */
3304int dwc3_gadget_init(struct dwc3 *dwc)
3305{
3306 int ret;
3307 int irq;
3308
3309 irq = dwc3_gadget_get_irq(dwc);
3310 if (irq < 0) {
3311 ret = irq;
3312 goto err0;
3313 }
3314
3315 dwc->irq_gadget = irq;
3316
3317 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3318 sizeof(*dwc->ep0_trb) * 2,
3319 &dwc->ep0_trb_addr, GFP_KERNEL);
3320 if (!dwc->ep0_trb) {
3321 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3322 ret = -ENOMEM;
3323 goto err0;
3324 }
3325
3326 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3327 if (!dwc->setup_buf) {
3328 ret = -ENOMEM;
3329 goto err1;
3330 }
3331
3332 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3333 &dwc->bounce_addr, GFP_KERNEL);
3334 if (!dwc->bounce) {
3335 ret = -ENOMEM;
3336 goto err2;
3337 }
3338
3339 init_completion(&dwc->ep0_in_setup);
3340
3341 dwc->gadget.ops = &dwc3_gadget_ops;
3342 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3343 dwc->gadget.sg_supported = true;
3344 dwc->gadget.name = "dwc3-gadget";
3345 dwc->gadget.lpm_capable = true;
3346
3347 /*
3348 * FIXME We might be setting max_speed to <SUPER, however versions
3349 * <2.20a of dwc3 have an issue with metastability (documented
3350 * elsewhere in this driver) which tells us we can't set max speed to
3351 * anything lower than SUPER.
3352 *
3353 * Because gadget.max_speed is only used by composite.c and function
3354 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3355 * to happen so we avoid sending SuperSpeed Capability descriptor
3356 * together with our BOS descriptor as that could confuse host into
3357 * thinking we can handle super speed.
3358 *
3359 * Note that, in fact, we won't even support GetBOS requests when speed
3360 * is less than super speed because we don't have means, yet, to tell
3361 * composite.c that we are USB 2.0 + LPM ECN.
3362 */
3363 if (dwc->revision < DWC3_REVISION_220A &&
3364 !dwc->dis_metastability_quirk)
3365 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3366 dwc->revision);
3367
3368 dwc->gadget.max_speed = dwc->maximum_speed;
3369
3370 /*
3371 * REVISIT: Here we should clear all pending IRQs to be
3372 * sure we're starting from a well known location.
3373 */
3374
3375 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3376 if (ret)
3377 goto err3;
3378
3379 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3380 if (ret) {
3381 dev_err(dwc->dev, "failed to register udc\n");
3382 goto err4;
3383 }
3384
3385 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3386
3387 return 0;
3388
3389err4:
3390 dwc3_gadget_free_endpoints(dwc);
3391
3392err3:
3393 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3394 dwc->bounce_addr);
3395
3396err2:
3397 kfree(dwc->setup_buf);
3398
3399err1:
3400 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3401 dwc->ep0_trb, dwc->ep0_trb_addr);
3402
3403err0:
3404 return ret;
3405}
3406
3407/* -------------------------------------------------------------------------- */
3408
3409void dwc3_gadget_exit(struct dwc3 *dwc)
3410{
3411 usb_del_gadget_udc(&dwc->gadget);
3412 dwc3_gadget_free_endpoints(dwc);
3413 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3414 dwc->bounce_addr);
3415 kfree(dwc->setup_buf);
3416 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3417 dwc->ep0_trb, dwc->ep0_trb_addr);
3418}
3419
3420int dwc3_gadget_suspend(struct dwc3 *dwc)
3421{
3422 if (!dwc->gadget_driver)
3423 return 0;
3424
3425 dwc3_gadget_run_stop(dwc, false, false);
3426 dwc3_disconnect_gadget(dwc);
3427 __dwc3_gadget_stop(dwc);
3428
3429 return 0;
3430}
3431
3432int dwc3_gadget_resume(struct dwc3 *dwc)
3433{
3434 int ret;
3435
3436 if (!dwc->gadget_driver)
3437 return 0;
3438
3439 ret = __dwc3_gadget_start(dwc);
3440 if (ret < 0)
3441 goto err0;
3442
3443 ret = dwc3_gadget_run_stop(dwc, true, false);
3444 if (ret < 0)
3445 goto err1;
3446
3447 return 0;
3448
3449err1:
3450 __dwc3_gadget_stop(dwc);
3451
3452err0:
3453 return ret;
3454}
3455
3456void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3457{
3458 if (dwc->pending_events) {
3459 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3460 dwc->pending_events = false;
3461 enable_irq(dwc->irq_gadget);
3462 }
3463}