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1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/prctl.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <linux/sched/idle.h>
12#include <linux/sched/debug.h>
13#include <linux/sched/task.h>
14#include <linux/sched/task_stack.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/pm.h>
18#include <linux/tick.h>
19#include <linux/random.h>
20#include <linux/user-return-notifier.h>
21#include <linux/dmi.h>
22#include <linux/utsname.h>
23#include <linux/stackprotector.h>
24#include <linux/cpuidle.h>
25#include <trace/events/power.h>
26#include <linux/hw_breakpoint.h>
27#include <asm/cpu.h>
28#include <asm/apic.h>
29#include <asm/syscalls.h>
30#include <linux/uaccess.h>
31#include <asm/mwait.h>
32#include <asm/fpu/internal.h>
33#include <asm/debugreg.h>
34#include <asm/nmi.h>
35#include <asm/tlbflush.h>
36#include <asm/mce.h>
37#include <asm/vm86.h>
38#include <asm/switch_to.h>
39#include <asm/desc.h>
40#include <asm/prctl.h>
41#include <asm/spec-ctrl.h>
42
43/*
44 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
45 * no more per-task TSS's. The TSS size is kept cacheline-aligned
46 * so they are allowed to end up in the .data..cacheline_aligned
47 * section. Since TSS's are completely CPU-local, we want them
48 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
49 */
50__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
51 .x86_tss = {
52 /*
53 * .sp0 is only used when entering ring 0 from a lower
54 * privilege level. Since the init task never runs anything
55 * but ring 0 code, there is no need for a valid value here.
56 * Poison it.
57 */
58 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
59
60#ifdef CONFIG_X86_64
61 /*
62 * .sp1 is cpu_current_top_of_stack. The init task never
63 * runs user code, but cpu_current_top_of_stack should still
64 * be well defined before the first context switch.
65 */
66 .sp1 = TOP_OF_INIT_STACK,
67#endif
68
69#ifdef CONFIG_X86_32
70 .ss0 = __KERNEL_DS,
71 .ss1 = __KERNEL_CS,
72 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
73#endif
74 },
75#ifdef CONFIG_X86_32
76 /*
77 * Note that the .io_bitmap member must be extra-big. This is because
78 * the CPU will access an additional byte beyond the end of the IO
79 * permission bitmap. The extra byte must be all 1 bits, and must
80 * be within the limit.
81 */
82 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
83#endif
84};
85EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
86
87DEFINE_PER_CPU(bool, __tss_limit_invalid);
88EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
89
90/*
91 * this gets called so that we can store lazy state into memory and copy the
92 * current task into the new thread.
93 */
94int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
95{
96 memcpy(dst, src, arch_task_struct_size);
97#ifdef CONFIG_VM86
98 dst->thread.vm86 = NULL;
99#endif
100
101 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
102}
103
104/*
105 * Free current thread data structures etc..
106 */
107void exit_thread(struct task_struct *tsk)
108{
109 struct thread_struct *t = &tsk->thread;
110 unsigned long *bp = t->io_bitmap_ptr;
111 struct fpu *fpu = &t->fpu;
112
113 if (bp) {
114 struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
115
116 t->io_bitmap_ptr = NULL;
117 clear_thread_flag(TIF_IO_BITMAP);
118 /*
119 * Careful, clear this in the TSS too:
120 */
121 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
122 t->io_bitmap_max = 0;
123 put_cpu();
124 kfree(bp);
125 }
126
127 free_vm86(t);
128
129 fpu__drop(fpu);
130}
131
132void flush_thread(void)
133{
134 struct task_struct *tsk = current;
135
136 flush_ptrace_hw_breakpoint(tsk);
137 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
138
139 fpu__clear(&tsk->thread.fpu);
140}
141
142void disable_TSC(void)
143{
144 preempt_disable();
145 if (!test_and_set_thread_flag(TIF_NOTSC))
146 /*
147 * Must flip the CPU state synchronously with
148 * TIF_NOTSC in the current running context.
149 */
150 cr4_set_bits(X86_CR4_TSD);
151 preempt_enable();
152}
153
154static void enable_TSC(void)
155{
156 preempt_disable();
157 if (test_and_clear_thread_flag(TIF_NOTSC))
158 /*
159 * Must flip the CPU state synchronously with
160 * TIF_NOTSC in the current running context.
161 */
162 cr4_clear_bits(X86_CR4_TSD);
163 preempt_enable();
164}
165
166int get_tsc_mode(unsigned long adr)
167{
168 unsigned int val;
169
170 if (test_thread_flag(TIF_NOTSC))
171 val = PR_TSC_SIGSEGV;
172 else
173 val = PR_TSC_ENABLE;
174
175 return put_user(val, (unsigned int __user *)adr);
176}
177
178int set_tsc_mode(unsigned int val)
179{
180 if (val == PR_TSC_SIGSEGV)
181 disable_TSC();
182 else if (val == PR_TSC_ENABLE)
183 enable_TSC();
184 else
185 return -EINVAL;
186
187 return 0;
188}
189
190DEFINE_PER_CPU(u64, msr_misc_features_shadow);
191
192static void set_cpuid_faulting(bool on)
193{
194 u64 msrval;
195
196 msrval = this_cpu_read(msr_misc_features_shadow);
197 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
198 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
199 this_cpu_write(msr_misc_features_shadow, msrval);
200 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
201}
202
203static void disable_cpuid(void)
204{
205 preempt_disable();
206 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
207 /*
208 * Must flip the CPU state synchronously with
209 * TIF_NOCPUID in the current running context.
210 */
211 set_cpuid_faulting(true);
212 }
213 preempt_enable();
214}
215
216static void enable_cpuid(void)
217{
218 preempt_disable();
219 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
220 /*
221 * Must flip the CPU state synchronously with
222 * TIF_NOCPUID in the current running context.
223 */
224 set_cpuid_faulting(false);
225 }
226 preempt_enable();
227}
228
229static int get_cpuid_mode(void)
230{
231 return !test_thread_flag(TIF_NOCPUID);
232}
233
234static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
235{
236 if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
237 return -ENODEV;
238
239 if (cpuid_enabled)
240 enable_cpuid();
241 else
242 disable_cpuid();
243
244 return 0;
245}
246
247/*
248 * Called immediately after a successful exec.
249 */
250void arch_setup_new_exec(void)
251{
252 /* If cpuid was previously disabled for this task, re-enable it. */
253 if (test_thread_flag(TIF_NOCPUID))
254 enable_cpuid();
255}
256
257static inline void switch_to_bitmap(struct tss_struct *tss,
258 struct thread_struct *prev,
259 struct thread_struct *next,
260 unsigned long tifp, unsigned long tifn)
261{
262 if (tifn & _TIF_IO_BITMAP) {
263 /*
264 * Copy the relevant range of the IO bitmap.
265 * Normally this is 128 bytes or less:
266 */
267 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
268 max(prev->io_bitmap_max, next->io_bitmap_max));
269 /*
270 * Make sure that the TSS limit is correct for the CPU
271 * to notice the IO bitmap.
272 */
273 refresh_tss_limit();
274 } else if (tifp & _TIF_IO_BITMAP) {
275 /*
276 * Clear any possible leftover bits:
277 */
278 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
279 }
280}
281
282#ifdef CONFIG_SMP
283
284struct ssb_state {
285 struct ssb_state *shared_state;
286 raw_spinlock_t lock;
287 unsigned int disable_state;
288 unsigned long local_state;
289};
290
291#define LSTATE_SSB 0
292
293static DEFINE_PER_CPU(struct ssb_state, ssb_state);
294
295void speculative_store_bypass_ht_init(void)
296{
297 struct ssb_state *st = this_cpu_ptr(&ssb_state);
298 unsigned int this_cpu = smp_processor_id();
299 unsigned int cpu;
300
301 st->local_state = 0;
302
303 /*
304 * Shared state setup happens once on the first bringup
305 * of the CPU. It's not destroyed on CPU hotunplug.
306 */
307 if (st->shared_state)
308 return;
309
310 raw_spin_lock_init(&st->lock);
311
312 /*
313 * Go over HT siblings and check whether one of them has set up the
314 * shared state pointer already.
315 */
316 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
317 if (cpu == this_cpu)
318 continue;
319
320 if (!per_cpu(ssb_state, cpu).shared_state)
321 continue;
322
323 /* Link it to the state of the sibling: */
324 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
325 return;
326 }
327
328 /*
329 * First HT sibling to come up on the core. Link shared state of
330 * the first HT sibling to itself. The siblings on the same core
331 * which come up later will see the shared state pointer and link
332 * themself to the state of this CPU.
333 */
334 st->shared_state = st;
335}
336
337/*
338 * Logic is: First HT sibling enables SSBD for both siblings in the core
339 * and last sibling to disable it, disables it for the whole core. This how
340 * MSR_SPEC_CTRL works in "hardware":
341 *
342 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
343 */
344static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
345{
346 struct ssb_state *st = this_cpu_ptr(&ssb_state);
347 u64 msr = x86_amd_ls_cfg_base;
348
349 if (!static_cpu_has(X86_FEATURE_ZEN)) {
350 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
351 wrmsrl(MSR_AMD64_LS_CFG, msr);
352 return;
353 }
354
355 if (tifn & _TIF_SSBD) {
356 /*
357 * Since this can race with prctl(), block reentry on the
358 * same CPU.
359 */
360 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
361 return;
362
363 msr |= x86_amd_ls_cfg_ssbd_mask;
364
365 raw_spin_lock(&st->shared_state->lock);
366 /* First sibling enables SSBD: */
367 if (!st->shared_state->disable_state)
368 wrmsrl(MSR_AMD64_LS_CFG, msr);
369 st->shared_state->disable_state++;
370 raw_spin_unlock(&st->shared_state->lock);
371 } else {
372 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
373 return;
374
375 raw_spin_lock(&st->shared_state->lock);
376 st->shared_state->disable_state--;
377 if (!st->shared_state->disable_state)
378 wrmsrl(MSR_AMD64_LS_CFG, msr);
379 raw_spin_unlock(&st->shared_state->lock);
380 }
381}
382#else
383static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
384{
385 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
386
387 wrmsrl(MSR_AMD64_LS_CFG, msr);
388}
389#endif
390
391static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
392{
393 /*
394 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
395 * so ssbd_tif_to_spec_ctrl() just works.
396 */
397 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
398}
399
400static __always_inline void intel_set_ssb_state(unsigned long tifn)
401{
402 u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
403
404 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
405}
406
407static __always_inline void __speculative_store_bypass_update(unsigned long tifn)
408{
409 if (static_cpu_has(X86_FEATURE_VIRT_SSBD))
410 amd_set_ssb_virt_state(tifn);
411 else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
412 amd_set_core_ssb_state(tifn);
413 else
414 intel_set_ssb_state(tifn);
415}
416
417void speculative_store_bypass_update(unsigned long tif)
418{
419 preempt_disable();
420 __speculative_store_bypass_update(tif);
421 preempt_enable();
422}
423
424void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
425 struct tss_struct *tss)
426{
427 struct thread_struct *prev, *next;
428 unsigned long tifp, tifn;
429
430 prev = &prev_p->thread;
431 next = &next_p->thread;
432
433 tifn = READ_ONCE(task_thread_info(next_p)->flags);
434 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
435 switch_to_bitmap(tss, prev, next, tifp, tifn);
436
437 propagate_user_return_notify(prev_p, next_p);
438
439 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
440 arch_has_block_step()) {
441 unsigned long debugctl, msk;
442
443 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
444 debugctl &= ~DEBUGCTLMSR_BTF;
445 msk = tifn & _TIF_BLOCKSTEP;
446 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
447 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
448 }
449
450 if ((tifp ^ tifn) & _TIF_NOTSC)
451 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
452
453 if ((tifp ^ tifn) & _TIF_NOCPUID)
454 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
455
456 if ((tifp ^ tifn) & _TIF_SSBD)
457 __speculative_store_bypass_update(tifn);
458}
459
460/*
461 * Idle related variables and functions
462 */
463unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
464EXPORT_SYMBOL(boot_option_idle_override);
465
466static void (*x86_idle)(void);
467
468#ifndef CONFIG_SMP
469static inline void play_dead(void)
470{
471 BUG();
472}
473#endif
474
475void arch_cpu_idle_enter(void)
476{
477 tsc_verify_tsc_adjust(false);
478 local_touch_nmi();
479}
480
481void arch_cpu_idle_dead(void)
482{
483 play_dead();
484}
485
486/*
487 * Called from the generic idle code.
488 */
489void arch_cpu_idle(void)
490{
491 x86_idle();
492}
493
494/*
495 * We use this if we don't have any better idle routine..
496 */
497void __cpuidle default_idle(void)
498{
499 trace_cpu_idle_rcuidle(1, smp_processor_id());
500 safe_halt();
501 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
502}
503#ifdef CONFIG_APM_MODULE
504EXPORT_SYMBOL(default_idle);
505#endif
506
507#ifdef CONFIG_XEN
508bool xen_set_default_idle(void)
509{
510 bool ret = !!x86_idle;
511
512 x86_idle = default_idle;
513
514 return ret;
515}
516#endif
517
518void stop_this_cpu(void *dummy)
519{
520 local_irq_disable();
521 /*
522 * Remove this CPU:
523 */
524 set_cpu_online(smp_processor_id(), false);
525 disable_local_APIC();
526 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
527
528 /*
529 * Use wbinvd on processors that support SME. This provides support
530 * for performing a successful kexec when going from SME inactive
531 * to SME active (or vice-versa). The cache must be cleared so that
532 * if there are entries with the same physical address, both with and
533 * without the encryption bit, they don't race each other when flushed
534 * and potentially end up with the wrong entry being committed to
535 * memory.
536 */
537 if (boot_cpu_has(X86_FEATURE_SME))
538 native_wbinvd();
539 for (;;) {
540 /*
541 * Use native_halt() so that memory contents don't change
542 * (stack usage and variables) after possibly issuing the
543 * native_wbinvd() above.
544 */
545 native_halt();
546 }
547}
548
549/*
550 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
551 * states (local apic timer and TSC stop).
552 */
553static void amd_e400_idle(void)
554{
555 /*
556 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
557 * gets set after static_cpu_has() places have been converted via
558 * alternatives.
559 */
560 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
561 default_idle();
562 return;
563 }
564
565 tick_broadcast_enter();
566
567 default_idle();
568
569 /*
570 * The switch back from broadcast mode needs to be called with
571 * interrupts disabled.
572 */
573 local_irq_disable();
574 tick_broadcast_exit();
575 local_irq_enable();
576}
577
578/*
579 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
580 * We can't rely on cpuidle installing MWAIT, because it will not load
581 * on systems that support only C1 -- so the boot default must be MWAIT.
582 *
583 * Some AMD machines are the opposite, they depend on using HALT.
584 *
585 * So for default C1, which is used during boot until cpuidle loads,
586 * use MWAIT-C1 on Intel HW that has it, else use HALT.
587 */
588static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
589{
590 if (c->x86_vendor != X86_VENDOR_INTEL)
591 return 0;
592
593 if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
594 return 0;
595
596 return 1;
597}
598
599/*
600 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
601 * with interrupts enabled and no flags, which is backwards compatible with the
602 * original MWAIT implementation.
603 */
604static __cpuidle void mwait_idle(void)
605{
606 if (!current_set_polling_and_test()) {
607 trace_cpu_idle_rcuidle(1, smp_processor_id());
608 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
609 mb(); /* quirk */
610 clflush((void *)¤t_thread_info()->flags);
611 mb(); /* quirk */
612 }
613
614 __monitor((void *)¤t_thread_info()->flags, 0, 0);
615 if (!need_resched())
616 __sti_mwait(0, 0);
617 else
618 local_irq_enable();
619 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
620 } else {
621 local_irq_enable();
622 }
623 __current_clr_polling();
624}
625
626void select_idle_routine(const struct cpuinfo_x86 *c)
627{
628#ifdef CONFIG_SMP
629 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
630 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
631#endif
632 if (x86_idle || boot_option_idle_override == IDLE_POLL)
633 return;
634
635 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
636 pr_info("using AMD E400 aware idle routine\n");
637 x86_idle = amd_e400_idle;
638 } else if (prefer_mwait_c1_over_halt(c)) {
639 pr_info("using mwait in idle threads\n");
640 x86_idle = mwait_idle;
641 } else
642 x86_idle = default_idle;
643}
644
645void amd_e400_c1e_apic_setup(void)
646{
647 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
648 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
649 local_irq_disable();
650 tick_broadcast_force();
651 local_irq_enable();
652 }
653}
654
655void __init arch_post_acpi_subsys_init(void)
656{
657 u32 lo, hi;
658
659 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
660 return;
661
662 /*
663 * AMD E400 detection needs to happen after ACPI has been enabled. If
664 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
665 * MSR_K8_INT_PENDING_MSG.
666 */
667 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
668 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
669 return;
670
671 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
672
673 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
674 mark_tsc_unstable("TSC halt in AMD C1E");
675 pr_info("System has AMD C1E enabled\n");
676}
677
678static int __init idle_setup(char *str)
679{
680 if (!str)
681 return -EINVAL;
682
683 if (!strcmp(str, "poll")) {
684 pr_info("using polling idle threads\n");
685 boot_option_idle_override = IDLE_POLL;
686 cpu_idle_poll_ctrl(true);
687 } else if (!strcmp(str, "halt")) {
688 /*
689 * When the boot option of idle=halt is added, halt is
690 * forced to be used for CPU idle. In such case CPU C2/C3
691 * won't be used again.
692 * To continue to load the CPU idle driver, don't touch
693 * the boot_option_idle_override.
694 */
695 x86_idle = default_idle;
696 boot_option_idle_override = IDLE_HALT;
697 } else if (!strcmp(str, "nomwait")) {
698 /*
699 * If the boot option of "idle=nomwait" is added,
700 * it means that mwait will be disabled for CPU C2/C3
701 * states. In such case it won't touch the variable
702 * of boot_option_idle_override.
703 */
704 boot_option_idle_override = IDLE_NOMWAIT;
705 } else
706 return -1;
707
708 return 0;
709}
710early_param("idle", idle_setup);
711
712unsigned long arch_align_stack(unsigned long sp)
713{
714 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
715 sp -= get_random_int() % 8192;
716 return sp & ~0xf;
717}
718
719unsigned long arch_randomize_brk(struct mm_struct *mm)
720{
721 return randomize_page(mm->brk, 0x02000000);
722}
723
724/*
725 * Called from fs/proc with a reference on @p to find the function
726 * which called into schedule(). This needs to be done carefully
727 * because the task might wake up and we might look at a stack
728 * changing under us.
729 */
730unsigned long get_wchan(struct task_struct *p)
731{
732 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
733 int count = 0;
734
735 if (!p || p == current || p->state == TASK_RUNNING)
736 return 0;
737
738 if (!try_get_task_stack(p))
739 return 0;
740
741 start = (unsigned long)task_stack_page(p);
742 if (!start)
743 goto out;
744
745 /*
746 * Layout of the stack page:
747 *
748 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
749 * PADDING
750 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
751 * stack
752 * ----------- bottom = start
753 *
754 * The tasks stack pointer points at the location where the
755 * framepointer is stored. The data on the stack is:
756 * ... IP FP ... IP FP
757 *
758 * We need to read FP and IP, so we need to adjust the upper
759 * bound by another unsigned long.
760 */
761 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
762 top -= 2 * sizeof(unsigned long);
763 bottom = start;
764
765 sp = READ_ONCE(p->thread.sp);
766 if (sp < bottom || sp > top)
767 goto out;
768
769 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
770 do {
771 if (fp < bottom || fp > top)
772 goto out;
773 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
774 if (!in_sched_functions(ip)) {
775 ret = ip;
776 goto out;
777 }
778 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
779 } while (count++ < 16 && p->state != TASK_RUNNING);
780
781out:
782 put_task_stack(p);
783 return ret;
784}
785
786long do_arch_prctl_common(struct task_struct *task, int option,
787 unsigned long cpuid_enabled)
788{
789 switch (option) {
790 case ARCH_GET_CPUID:
791 return get_cpuid_mode();
792 case ARCH_SET_CPUID:
793 return set_cpuid_mode(task, cpuid_enabled);
794 }
795
796 return -EINVAL;
797}
1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/prctl.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <linux/sched/idle.h>
12#include <linux/sched/debug.h>
13#include <linux/sched/task.h>
14#include <linux/sched/task_stack.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/pm.h>
18#include <linux/tick.h>
19#include <linux/random.h>
20#include <linux/user-return-notifier.h>
21#include <linux/dmi.h>
22#include <linux/utsname.h>
23#include <linux/stackprotector.h>
24#include <linux/cpuidle.h>
25#include <linux/acpi.h>
26#include <linux/elf-randomize.h>
27#include <trace/events/power.h>
28#include <linux/hw_breakpoint.h>
29#include <asm/cpu.h>
30#include <asm/apic.h>
31#include <linux/uaccess.h>
32#include <asm/mwait.h>
33#include <asm/fpu/internal.h>
34#include <asm/debugreg.h>
35#include <asm/nmi.h>
36#include <asm/tlbflush.h>
37#include <asm/mce.h>
38#include <asm/vm86.h>
39#include <asm/switch_to.h>
40#include <asm/desc.h>
41#include <asm/prctl.h>
42#include <asm/spec-ctrl.h>
43#include <asm/io_bitmap.h>
44#include <asm/proto.h>
45#include <asm/frame.h>
46
47#include "process.h"
48
49/*
50 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
51 * no more per-task TSS's. The TSS size is kept cacheline-aligned
52 * so they are allowed to end up in the .data..cacheline_aligned
53 * section. Since TSS's are completely CPU-local, we want them
54 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
55 */
56__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
57 .x86_tss = {
58 /*
59 * .sp0 is only used when entering ring 0 from a lower
60 * privilege level. Since the init task never runs anything
61 * but ring 0 code, there is no need for a valid value here.
62 * Poison it.
63 */
64 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
65
66 /*
67 * .sp1 is cpu_current_top_of_stack. The init task never
68 * runs user code, but cpu_current_top_of_stack should still
69 * be well defined before the first context switch.
70 */
71 .sp1 = TOP_OF_INIT_STACK,
72
73#ifdef CONFIG_X86_32
74 .ss0 = __KERNEL_DS,
75 .ss1 = __KERNEL_CS,
76#endif
77 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
78 },
79};
80EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
81
82DEFINE_PER_CPU(bool, __tss_limit_invalid);
83EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
84
85/*
86 * this gets called so that we can store lazy state into memory and copy the
87 * current task into the new thread.
88 */
89int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
90{
91 memcpy(dst, src, arch_task_struct_size);
92#ifdef CONFIG_VM86
93 dst->thread.vm86 = NULL;
94#endif
95
96 return fpu__copy(dst, src);
97}
98
99/*
100 * Free thread data structures etc..
101 */
102void exit_thread(struct task_struct *tsk)
103{
104 struct thread_struct *t = &tsk->thread;
105 struct fpu *fpu = &t->fpu;
106
107 if (test_thread_flag(TIF_IO_BITMAP))
108 io_bitmap_exit(tsk);
109
110 free_vm86(t);
111
112 fpu__drop(fpu);
113}
114
115static int set_new_tls(struct task_struct *p, unsigned long tls)
116{
117 struct user_desc __user *utls = (struct user_desc __user *)tls;
118
119 if (in_ia32_syscall())
120 return do_set_thread_area(p, -1, utls, 0);
121 else
122 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
123}
124
125int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
126 struct task_struct *p, unsigned long tls)
127{
128 struct inactive_task_frame *frame;
129 struct fork_frame *fork_frame;
130 struct pt_regs *childregs;
131 int ret = 0;
132
133 childregs = task_pt_regs(p);
134 fork_frame = container_of(childregs, struct fork_frame, regs);
135 frame = &fork_frame->frame;
136
137 frame->bp = encode_frame_pointer(childregs);
138 frame->ret_addr = (unsigned long) ret_from_fork;
139 p->thread.sp = (unsigned long) fork_frame;
140 p->thread.io_bitmap = NULL;
141 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
142
143#ifdef CONFIG_X86_64
144 current_save_fsgs();
145 p->thread.fsindex = current->thread.fsindex;
146 p->thread.fsbase = current->thread.fsbase;
147 p->thread.gsindex = current->thread.gsindex;
148 p->thread.gsbase = current->thread.gsbase;
149
150 savesegment(es, p->thread.es);
151 savesegment(ds, p->thread.ds);
152#else
153 p->thread.sp0 = (unsigned long) (childregs + 1);
154 /*
155 * Clear all status flags including IF and set fixed bit. 64bit
156 * does not have this initialization as the frame does not contain
157 * flags. The flags consistency (especially vs. AC) is there
158 * ensured via objtool, which lacks 32bit support.
159 */
160 frame->flags = X86_EFLAGS_FIXED;
161#endif
162
163 /* Kernel thread ? */
164 if (unlikely(p->flags & PF_KTHREAD)) {
165 memset(childregs, 0, sizeof(struct pt_regs));
166 kthread_frame_init(frame, sp, arg);
167 return 0;
168 }
169
170 frame->bx = 0;
171 *childregs = *current_pt_regs();
172 childregs->ax = 0;
173 if (sp)
174 childregs->sp = sp;
175
176#ifdef CONFIG_X86_32
177 task_user_gs(p) = get_user_gs(current_pt_regs());
178#endif
179
180 /* Set a new TLS for the child thread? */
181 if (clone_flags & CLONE_SETTLS)
182 ret = set_new_tls(p, tls);
183
184 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
185 io_bitmap_share(p);
186
187 return ret;
188}
189
190void flush_thread(void)
191{
192 struct task_struct *tsk = current;
193
194 flush_ptrace_hw_breakpoint(tsk);
195 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
196
197 fpu__clear_all(&tsk->thread.fpu);
198}
199
200void disable_TSC(void)
201{
202 preempt_disable();
203 if (!test_and_set_thread_flag(TIF_NOTSC))
204 /*
205 * Must flip the CPU state synchronously with
206 * TIF_NOTSC in the current running context.
207 */
208 cr4_set_bits(X86_CR4_TSD);
209 preempt_enable();
210}
211
212static void enable_TSC(void)
213{
214 preempt_disable();
215 if (test_and_clear_thread_flag(TIF_NOTSC))
216 /*
217 * Must flip the CPU state synchronously with
218 * TIF_NOTSC in the current running context.
219 */
220 cr4_clear_bits(X86_CR4_TSD);
221 preempt_enable();
222}
223
224int get_tsc_mode(unsigned long adr)
225{
226 unsigned int val;
227
228 if (test_thread_flag(TIF_NOTSC))
229 val = PR_TSC_SIGSEGV;
230 else
231 val = PR_TSC_ENABLE;
232
233 return put_user(val, (unsigned int __user *)adr);
234}
235
236int set_tsc_mode(unsigned int val)
237{
238 if (val == PR_TSC_SIGSEGV)
239 disable_TSC();
240 else if (val == PR_TSC_ENABLE)
241 enable_TSC();
242 else
243 return -EINVAL;
244
245 return 0;
246}
247
248DEFINE_PER_CPU(u64, msr_misc_features_shadow);
249
250static void set_cpuid_faulting(bool on)
251{
252 u64 msrval;
253
254 msrval = this_cpu_read(msr_misc_features_shadow);
255 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
256 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
257 this_cpu_write(msr_misc_features_shadow, msrval);
258 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
259}
260
261static void disable_cpuid(void)
262{
263 preempt_disable();
264 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
265 /*
266 * Must flip the CPU state synchronously with
267 * TIF_NOCPUID in the current running context.
268 */
269 set_cpuid_faulting(true);
270 }
271 preempt_enable();
272}
273
274static void enable_cpuid(void)
275{
276 preempt_disable();
277 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
278 /*
279 * Must flip the CPU state synchronously with
280 * TIF_NOCPUID in the current running context.
281 */
282 set_cpuid_faulting(false);
283 }
284 preempt_enable();
285}
286
287static int get_cpuid_mode(void)
288{
289 return !test_thread_flag(TIF_NOCPUID);
290}
291
292static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
293{
294 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
295 return -ENODEV;
296
297 if (cpuid_enabled)
298 enable_cpuid();
299 else
300 disable_cpuid();
301
302 return 0;
303}
304
305/*
306 * Called immediately after a successful exec.
307 */
308void arch_setup_new_exec(void)
309{
310 /* If cpuid was previously disabled for this task, re-enable it. */
311 if (test_thread_flag(TIF_NOCPUID))
312 enable_cpuid();
313
314 /*
315 * Don't inherit TIF_SSBD across exec boundary when
316 * PR_SPEC_DISABLE_NOEXEC is used.
317 */
318 if (test_thread_flag(TIF_SSBD) &&
319 task_spec_ssb_noexec(current)) {
320 clear_thread_flag(TIF_SSBD);
321 task_clear_spec_ssb_disable(current);
322 task_clear_spec_ssb_noexec(current);
323 speculation_ctrl_update(task_thread_info(current)->flags);
324 }
325}
326
327#ifdef CONFIG_X86_IOPL_IOPERM
328static inline void switch_to_bitmap(unsigned long tifp)
329{
330 /*
331 * Invalidate I/O bitmap if the previous task used it. This prevents
332 * any possible leakage of an active I/O bitmap.
333 *
334 * If the next task has an I/O bitmap it will handle it on exit to
335 * user mode.
336 */
337 if (tifp & _TIF_IO_BITMAP)
338 tss_invalidate_io_bitmap();
339}
340
341static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
342{
343 /*
344 * Copy at least the byte range of the incoming tasks bitmap which
345 * covers the permitted I/O ports.
346 *
347 * If the previous task which used an I/O bitmap had more bits
348 * permitted, then the copy needs to cover those as well so they
349 * get turned off.
350 */
351 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
352 max(tss->io_bitmap.prev_max, iobm->max));
353
354 /*
355 * Store the new max and the sequence number of this bitmap
356 * and a pointer to the bitmap itself.
357 */
358 tss->io_bitmap.prev_max = iobm->max;
359 tss->io_bitmap.prev_sequence = iobm->sequence;
360}
361
362/**
363 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
364 */
365void native_tss_update_io_bitmap(void)
366{
367 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
368 struct thread_struct *t = ¤t->thread;
369 u16 *base = &tss->x86_tss.io_bitmap_base;
370
371 if (!test_thread_flag(TIF_IO_BITMAP)) {
372 native_tss_invalidate_io_bitmap();
373 return;
374 }
375
376 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
377 *base = IO_BITMAP_OFFSET_VALID_ALL;
378 } else {
379 struct io_bitmap *iobm = t->io_bitmap;
380
381 /*
382 * Only copy bitmap data when the sequence number differs. The
383 * update time is accounted to the incoming task.
384 */
385 if (tss->io_bitmap.prev_sequence != iobm->sequence)
386 tss_copy_io_bitmap(tss, iobm);
387
388 /* Enable the bitmap */
389 *base = IO_BITMAP_OFFSET_VALID_MAP;
390 }
391
392 /*
393 * Make sure that the TSS limit is covering the IO bitmap. It might have
394 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
395 * access from user space to trigger a #GP because tbe bitmap is outside
396 * the TSS limit.
397 */
398 refresh_tss_limit();
399}
400#else /* CONFIG_X86_IOPL_IOPERM */
401static inline void switch_to_bitmap(unsigned long tifp) { }
402#endif
403
404#ifdef CONFIG_SMP
405
406struct ssb_state {
407 struct ssb_state *shared_state;
408 raw_spinlock_t lock;
409 unsigned int disable_state;
410 unsigned long local_state;
411};
412
413#define LSTATE_SSB 0
414
415static DEFINE_PER_CPU(struct ssb_state, ssb_state);
416
417void speculative_store_bypass_ht_init(void)
418{
419 struct ssb_state *st = this_cpu_ptr(&ssb_state);
420 unsigned int this_cpu = smp_processor_id();
421 unsigned int cpu;
422
423 st->local_state = 0;
424
425 /*
426 * Shared state setup happens once on the first bringup
427 * of the CPU. It's not destroyed on CPU hotunplug.
428 */
429 if (st->shared_state)
430 return;
431
432 raw_spin_lock_init(&st->lock);
433
434 /*
435 * Go over HT siblings and check whether one of them has set up the
436 * shared state pointer already.
437 */
438 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
439 if (cpu == this_cpu)
440 continue;
441
442 if (!per_cpu(ssb_state, cpu).shared_state)
443 continue;
444
445 /* Link it to the state of the sibling: */
446 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
447 return;
448 }
449
450 /*
451 * First HT sibling to come up on the core. Link shared state of
452 * the first HT sibling to itself. The siblings on the same core
453 * which come up later will see the shared state pointer and link
454 * themself to the state of this CPU.
455 */
456 st->shared_state = st;
457}
458
459/*
460 * Logic is: First HT sibling enables SSBD for both siblings in the core
461 * and last sibling to disable it, disables it for the whole core. This how
462 * MSR_SPEC_CTRL works in "hardware":
463 *
464 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
465 */
466static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
467{
468 struct ssb_state *st = this_cpu_ptr(&ssb_state);
469 u64 msr = x86_amd_ls_cfg_base;
470
471 if (!static_cpu_has(X86_FEATURE_ZEN)) {
472 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
473 wrmsrl(MSR_AMD64_LS_CFG, msr);
474 return;
475 }
476
477 if (tifn & _TIF_SSBD) {
478 /*
479 * Since this can race with prctl(), block reentry on the
480 * same CPU.
481 */
482 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
483 return;
484
485 msr |= x86_amd_ls_cfg_ssbd_mask;
486
487 raw_spin_lock(&st->shared_state->lock);
488 /* First sibling enables SSBD: */
489 if (!st->shared_state->disable_state)
490 wrmsrl(MSR_AMD64_LS_CFG, msr);
491 st->shared_state->disable_state++;
492 raw_spin_unlock(&st->shared_state->lock);
493 } else {
494 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
495 return;
496
497 raw_spin_lock(&st->shared_state->lock);
498 st->shared_state->disable_state--;
499 if (!st->shared_state->disable_state)
500 wrmsrl(MSR_AMD64_LS_CFG, msr);
501 raw_spin_unlock(&st->shared_state->lock);
502 }
503}
504#else
505static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
506{
507 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
508
509 wrmsrl(MSR_AMD64_LS_CFG, msr);
510}
511#endif
512
513static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
514{
515 /*
516 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
517 * so ssbd_tif_to_spec_ctrl() just works.
518 */
519 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
520}
521
522/*
523 * Update the MSRs managing speculation control, during context switch.
524 *
525 * tifp: Previous task's thread flags
526 * tifn: Next task's thread flags
527 */
528static __always_inline void __speculation_ctrl_update(unsigned long tifp,
529 unsigned long tifn)
530{
531 unsigned long tif_diff = tifp ^ tifn;
532 u64 msr = x86_spec_ctrl_base;
533 bool updmsr = false;
534
535 lockdep_assert_irqs_disabled();
536
537 /* Handle change of TIF_SSBD depending on the mitigation method. */
538 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
539 if (tif_diff & _TIF_SSBD)
540 amd_set_ssb_virt_state(tifn);
541 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
542 if (tif_diff & _TIF_SSBD)
543 amd_set_core_ssb_state(tifn);
544 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
545 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
546 updmsr |= !!(tif_diff & _TIF_SSBD);
547 msr |= ssbd_tif_to_spec_ctrl(tifn);
548 }
549
550 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
551 if (IS_ENABLED(CONFIG_SMP) &&
552 static_branch_unlikely(&switch_to_cond_stibp)) {
553 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
554 msr |= stibp_tif_to_spec_ctrl(tifn);
555 }
556
557 if (updmsr)
558 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
559}
560
561static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
562{
563 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
564 if (task_spec_ssb_disable(tsk))
565 set_tsk_thread_flag(tsk, TIF_SSBD);
566 else
567 clear_tsk_thread_flag(tsk, TIF_SSBD);
568
569 if (task_spec_ib_disable(tsk))
570 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
571 else
572 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
573 }
574 /* Return the updated threadinfo flags*/
575 return task_thread_info(tsk)->flags;
576}
577
578void speculation_ctrl_update(unsigned long tif)
579{
580 unsigned long flags;
581
582 /* Forced update. Make sure all relevant TIF flags are different */
583 local_irq_save(flags);
584 __speculation_ctrl_update(~tif, tif);
585 local_irq_restore(flags);
586}
587
588/* Called from seccomp/prctl update */
589void speculation_ctrl_update_current(void)
590{
591 preempt_disable();
592 speculation_ctrl_update(speculation_ctrl_update_tif(current));
593 preempt_enable();
594}
595
596static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
597{
598 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
599
600 newval = cr4 ^ mask;
601 if (newval != cr4) {
602 this_cpu_write(cpu_tlbstate.cr4, newval);
603 __write_cr4(newval);
604 }
605}
606
607void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
608{
609 unsigned long tifp, tifn;
610
611 tifn = READ_ONCE(task_thread_info(next_p)->flags);
612 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
613
614 switch_to_bitmap(tifp);
615
616 propagate_user_return_notify(prev_p, next_p);
617
618 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
619 arch_has_block_step()) {
620 unsigned long debugctl, msk;
621
622 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
623 debugctl &= ~DEBUGCTLMSR_BTF;
624 msk = tifn & _TIF_BLOCKSTEP;
625 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
626 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
627 }
628
629 if ((tifp ^ tifn) & _TIF_NOTSC)
630 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
631
632 if ((tifp ^ tifn) & _TIF_NOCPUID)
633 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
634
635 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
636 __speculation_ctrl_update(tifp, tifn);
637 } else {
638 speculation_ctrl_update_tif(prev_p);
639 tifn = speculation_ctrl_update_tif(next_p);
640
641 /* Enforce MSR update to ensure consistent state */
642 __speculation_ctrl_update(~tifn, tifn);
643 }
644
645 if ((tifp ^ tifn) & _TIF_SLD)
646 switch_to_sld(tifn);
647}
648
649/*
650 * Idle related variables and functions
651 */
652unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
653EXPORT_SYMBOL(boot_option_idle_override);
654
655static void (*x86_idle)(void);
656
657#ifndef CONFIG_SMP
658static inline void play_dead(void)
659{
660 BUG();
661}
662#endif
663
664void arch_cpu_idle_enter(void)
665{
666 tsc_verify_tsc_adjust(false);
667 local_touch_nmi();
668}
669
670void arch_cpu_idle_dead(void)
671{
672 play_dead();
673}
674
675/*
676 * Called from the generic idle code.
677 */
678void arch_cpu_idle(void)
679{
680 x86_idle();
681}
682
683/*
684 * We use this if we don't have any better idle routine..
685 */
686void __cpuidle default_idle(void)
687{
688 safe_halt();
689}
690#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
691EXPORT_SYMBOL(default_idle);
692#endif
693
694#ifdef CONFIG_XEN
695bool xen_set_default_idle(void)
696{
697 bool ret = !!x86_idle;
698
699 x86_idle = default_idle;
700
701 return ret;
702}
703#endif
704
705void stop_this_cpu(void *dummy)
706{
707 local_irq_disable();
708 /*
709 * Remove this CPU:
710 */
711 set_cpu_online(smp_processor_id(), false);
712 disable_local_APIC();
713 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
714
715 /*
716 * Use wbinvd on processors that support SME. This provides support
717 * for performing a successful kexec when going from SME inactive
718 * to SME active (or vice-versa). The cache must be cleared so that
719 * if there are entries with the same physical address, both with and
720 * without the encryption bit, they don't race each other when flushed
721 * and potentially end up with the wrong entry being committed to
722 * memory.
723 */
724 if (boot_cpu_has(X86_FEATURE_SME))
725 native_wbinvd();
726 for (;;) {
727 /*
728 * Use native_halt() so that memory contents don't change
729 * (stack usage and variables) after possibly issuing the
730 * native_wbinvd() above.
731 */
732 native_halt();
733 }
734}
735
736/*
737 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
738 * states (local apic timer and TSC stop).
739 */
740static void amd_e400_idle(void)
741{
742 /*
743 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
744 * gets set after static_cpu_has() places have been converted via
745 * alternatives.
746 */
747 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
748 default_idle();
749 return;
750 }
751
752 tick_broadcast_enter();
753
754 default_idle();
755
756 /*
757 * The switch back from broadcast mode needs to be called with
758 * interrupts disabled.
759 */
760 local_irq_disable();
761 tick_broadcast_exit();
762 local_irq_enable();
763}
764
765/*
766 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
767 * We can't rely on cpuidle installing MWAIT, because it will not load
768 * on systems that support only C1 -- so the boot default must be MWAIT.
769 *
770 * Some AMD machines are the opposite, they depend on using HALT.
771 *
772 * So for default C1, which is used during boot until cpuidle loads,
773 * use MWAIT-C1 on Intel HW that has it, else use HALT.
774 */
775static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
776{
777 if (c->x86_vendor != X86_VENDOR_INTEL)
778 return 0;
779
780 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
781 return 0;
782
783 return 1;
784}
785
786/*
787 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
788 * with interrupts enabled and no flags, which is backwards compatible with the
789 * original MWAIT implementation.
790 */
791static __cpuidle void mwait_idle(void)
792{
793 if (!current_set_polling_and_test()) {
794 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
795 mb(); /* quirk */
796 clflush((void *)¤t_thread_info()->flags);
797 mb(); /* quirk */
798 }
799
800 __monitor((void *)¤t_thread_info()->flags, 0, 0);
801 if (!need_resched())
802 __sti_mwait(0, 0);
803 else
804 local_irq_enable();
805 } else {
806 local_irq_enable();
807 }
808 __current_clr_polling();
809}
810
811void select_idle_routine(const struct cpuinfo_x86 *c)
812{
813#ifdef CONFIG_SMP
814 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
815 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
816#endif
817 if (x86_idle || boot_option_idle_override == IDLE_POLL)
818 return;
819
820 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
821 pr_info("using AMD E400 aware idle routine\n");
822 x86_idle = amd_e400_idle;
823 } else if (prefer_mwait_c1_over_halt(c)) {
824 pr_info("using mwait in idle threads\n");
825 x86_idle = mwait_idle;
826 } else
827 x86_idle = default_idle;
828}
829
830void amd_e400_c1e_apic_setup(void)
831{
832 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
833 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
834 local_irq_disable();
835 tick_broadcast_force();
836 local_irq_enable();
837 }
838}
839
840void __init arch_post_acpi_subsys_init(void)
841{
842 u32 lo, hi;
843
844 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
845 return;
846
847 /*
848 * AMD E400 detection needs to happen after ACPI has been enabled. If
849 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
850 * MSR_K8_INT_PENDING_MSG.
851 */
852 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
853 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
854 return;
855
856 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
857
858 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
859 mark_tsc_unstable("TSC halt in AMD C1E");
860 pr_info("System has AMD C1E enabled\n");
861}
862
863static int __init idle_setup(char *str)
864{
865 if (!str)
866 return -EINVAL;
867
868 if (!strcmp(str, "poll")) {
869 pr_info("using polling idle threads\n");
870 boot_option_idle_override = IDLE_POLL;
871 cpu_idle_poll_ctrl(true);
872 } else if (!strcmp(str, "halt")) {
873 /*
874 * When the boot option of idle=halt is added, halt is
875 * forced to be used for CPU idle. In such case CPU C2/C3
876 * won't be used again.
877 * To continue to load the CPU idle driver, don't touch
878 * the boot_option_idle_override.
879 */
880 x86_idle = default_idle;
881 boot_option_idle_override = IDLE_HALT;
882 } else if (!strcmp(str, "nomwait")) {
883 /*
884 * If the boot option of "idle=nomwait" is added,
885 * it means that mwait will be disabled for CPU C2/C3
886 * states. In such case it won't touch the variable
887 * of boot_option_idle_override.
888 */
889 boot_option_idle_override = IDLE_NOMWAIT;
890 } else
891 return -1;
892
893 return 0;
894}
895early_param("idle", idle_setup);
896
897unsigned long arch_align_stack(unsigned long sp)
898{
899 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
900 sp -= get_random_int() % 8192;
901 return sp & ~0xf;
902}
903
904unsigned long arch_randomize_brk(struct mm_struct *mm)
905{
906 return randomize_page(mm->brk, 0x02000000);
907}
908
909/*
910 * Called from fs/proc with a reference on @p to find the function
911 * which called into schedule(). This needs to be done carefully
912 * because the task might wake up and we might look at a stack
913 * changing under us.
914 */
915unsigned long get_wchan(struct task_struct *p)
916{
917 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
918 int count = 0;
919
920 if (p == current || p->state == TASK_RUNNING)
921 return 0;
922
923 if (!try_get_task_stack(p))
924 return 0;
925
926 start = (unsigned long)task_stack_page(p);
927 if (!start)
928 goto out;
929
930 /*
931 * Layout of the stack page:
932 *
933 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
934 * PADDING
935 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
936 * stack
937 * ----------- bottom = start
938 *
939 * The tasks stack pointer points at the location where the
940 * framepointer is stored. The data on the stack is:
941 * ... IP FP ... IP FP
942 *
943 * We need to read FP and IP, so we need to adjust the upper
944 * bound by another unsigned long.
945 */
946 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
947 top -= 2 * sizeof(unsigned long);
948 bottom = start;
949
950 sp = READ_ONCE(p->thread.sp);
951 if (sp < bottom || sp > top)
952 goto out;
953
954 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
955 do {
956 if (fp < bottom || fp > top)
957 goto out;
958 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
959 if (!in_sched_functions(ip)) {
960 ret = ip;
961 goto out;
962 }
963 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
964 } while (count++ < 16 && p->state != TASK_RUNNING);
965
966out:
967 put_task_stack(p);
968 return ret;
969}
970
971long do_arch_prctl_common(struct task_struct *task, int option,
972 unsigned long cpuid_enabled)
973{
974 switch (option) {
975 case ARCH_GET_CPUID:
976 return get_cpuid_mode();
977 case ARCH_SET_CPUID:
978 return set_cpuid_mode(task, cpuid_enabled);
979 }
980
981 return -EINVAL;
982}