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1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/prctl.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <linux/sched/idle.h>
12#include <linux/sched/debug.h>
13#include <linux/sched/task.h>
14#include <linux/sched/task_stack.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/pm.h>
18#include <linux/tick.h>
19#include <linux/random.h>
20#include <linux/user-return-notifier.h>
21#include <linux/dmi.h>
22#include <linux/utsname.h>
23#include <linux/stackprotector.h>
24#include <linux/cpuidle.h>
25#include <trace/events/power.h>
26#include <linux/hw_breakpoint.h>
27#include <asm/cpu.h>
28#include <asm/apic.h>
29#include <asm/syscalls.h>
30#include <linux/uaccess.h>
31#include <asm/mwait.h>
32#include <asm/fpu/internal.h>
33#include <asm/debugreg.h>
34#include <asm/nmi.h>
35#include <asm/tlbflush.h>
36#include <asm/mce.h>
37#include <asm/vm86.h>
38#include <asm/switch_to.h>
39#include <asm/desc.h>
40#include <asm/prctl.h>
41#include <asm/spec-ctrl.h>
42
43/*
44 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
45 * no more per-task TSS's. The TSS size is kept cacheline-aligned
46 * so they are allowed to end up in the .data..cacheline_aligned
47 * section. Since TSS's are completely CPU-local, we want them
48 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
49 */
50__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
51 .x86_tss = {
52 /*
53 * .sp0 is only used when entering ring 0 from a lower
54 * privilege level. Since the init task never runs anything
55 * but ring 0 code, there is no need for a valid value here.
56 * Poison it.
57 */
58 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
59
60#ifdef CONFIG_X86_64
61 /*
62 * .sp1 is cpu_current_top_of_stack. The init task never
63 * runs user code, but cpu_current_top_of_stack should still
64 * be well defined before the first context switch.
65 */
66 .sp1 = TOP_OF_INIT_STACK,
67#endif
68
69#ifdef CONFIG_X86_32
70 .ss0 = __KERNEL_DS,
71 .ss1 = __KERNEL_CS,
72 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
73#endif
74 },
75#ifdef CONFIG_X86_32
76 /*
77 * Note that the .io_bitmap member must be extra-big. This is because
78 * the CPU will access an additional byte beyond the end of the IO
79 * permission bitmap. The extra byte must be all 1 bits, and must
80 * be within the limit.
81 */
82 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
83#endif
84};
85EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
86
87DEFINE_PER_CPU(bool, __tss_limit_invalid);
88EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
89
90/*
91 * this gets called so that we can store lazy state into memory and copy the
92 * current task into the new thread.
93 */
94int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
95{
96 memcpy(dst, src, arch_task_struct_size);
97#ifdef CONFIG_VM86
98 dst->thread.vm86 = NULL;
99#endif
100
101 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
102}
103
104/*
105 * Free current thread data structures etc..
106 */
107void exit_thread(struct task_struct *tsk)
108{
109 struct thread_struct *t = &tsk->thread;
110 unsigned long *bp = t->io_bitmap_ptr;
111 struct fpu *fpu = &t->fpu;
112
113 if (bp) {
114 struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
115
116 t->io_bitmap_ptr = NULL;
117 clear_thread_flag(TIF_IO_BITMAP);
118 /*
119 * Careful, clear this in the TSS too:
120 */
121 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
122 t->io_bitmap_max = 0;
123 put_cpu();
124 kfree(bp);
125 }
126
127 free_vm86(t);
128
129 fpu__drop(fpu);
130}
131
132void flush_thread(void)
133{
134 struct task_struct *tsk = current;
135
136 flush_ptrace_hw_breakpoint(tsk);
137 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
138
139 fpu__clear(&tsk->thread.fpu);
140}
141
142void disable_TSC(void)
143{
144 preempt_disable();
145 if (!test_and_set_thread_flag(TIF_NOTSC))
146 /*
147 * Must flip the CPU state synchronously with
148 * TIF_NOTSC in the current running context.
149 */
150 cr4_set_bits(X86_CR4_TSD);
151 preempt_enable();
152}
153
154static void enable_TSC(void)
155{
156 preempt_disable();
157 if (test_and_clear_thread_flag(TIF_NOTSC))
158 /*
159 * Must flip the CPU state synchronously with
160 * TIF_NOTSC in the current running context.
161 */
162 cr4_clear_bits(X86_CR4_TSD);
163 preempt_enable();
164}
165
166int get_tsc_mode(unsigned long adr)
167{
168 unsigned int val;
169
170 if (test_thread_flag(TIF_NOTSC))
171 val = PR_TSC_SIGSEGV;
172 else
173 val = PR_TSC_ENABLE;
174
175 return put_user(val, (unsigned int __user *)adr);
176}
177
178int set_tsc_mode(unsigned int val)
179{
180 if (val == PR_TSC_SIGSEGV)
181 disable_TSC();
182 else if (val == PR_TSC_ENABLE)
183 enable_TSC();
184 else
185 return -EINVAL;
186
187 return 0;
188}
189
190DEFINE_PER_CPU(u64, msr_misc_features_shadow);
191
192static void set_cpuid_faulting(bool on)
193{
194 u64 msrval;
195
196 msrval = this_cpu_read(msr_misc_features_shadow);
197 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
198 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
199 this_cpu_write(msr_misc_features_shadow, msrval);
200 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
201}
202
203static void disable_cpuid(void)
204{
205 preempt_disable();
206 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
207 /*
208 * Must flip the CPU state synchronously with
209 * TIF_NOCPUID in the current running context.
210 */
211 set_cpuid_faulting(true);
212 }
213 preempt_enable();
214}
215
216static void enable_cpuid(void)
217{
218 preempt_disable();
219 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
220 /*
221 * Must flip the CPU state synchronously with
222 * TIF_NOCPUID in the current running context.
223 */
224 set_cpuid_faulting(false);
225 }
226 preempt_enable();
227}
228
229static int get_cpuid_mode(void)
230{
231 return !test_thread_flag(TIF_NOCPUID);
232}
233
234static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
235{
236 if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
237 return -ENODEV;
238
239 if (cpuid_enabled)
240 enable_cpuid();
241 else
242 disable_cpuid();
243
244 return 0;
245}
246
247/*
248 * Called immediately after a successful exec.
249 */
250void arch_setup_new_exec(void)
251{
252 /* If cpuid was previously disabled for this task, re-enable it. */
253 if (test_thread_flag(TIF_NOCPUID))
254 enable_cpuid();
255}
256
257static inline void switch_to_bitmap(struct tss_struct *tss,
258 struct thread_struct *prev,
259 struct thread_struct *next,
260 unsigned long tifp, unsigned long tifn)
261{
262 if (tifn & _TIF_IO_BITMAP) {
263 /*
264 * Copy the relevant range of the IO bitmap.
265 * Normally this is 128 bytes or less:
266 */
267 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
268 max(prev->io_bitmap_max, next->io_bitmap_max));
269 /*
270 * Make sure that the TSS limit is correct for the CPU
271 * to notice the IO bitmap.
272 */
273 refresh_tss_limit();
274 } else if (tifp & _TIF_IO_BITMAP) {
275 /*
276 * Clear any possible leftover bits:
277 */
278 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
279 }
280}
281
282#ifdef CONFIG_SMP
283
284struct ssb_state {
285 struct ssb_state *shared_state;
286 raw_spinlock_t lock;
287 unsigned int disable_state;
288 unsigned long local_state;
289};
290
291#define LSTATE_SSB 0
292
293static DEFINE_PER_CPU(struct ssb_state, ssb_state);
294
295void speculative_store_bypass_ht_init(void)
296{
297 struct ssb_state *st = this_cpu_ptr(&ssb_state);
298 unsigned int this_cpu = smp_processor_id();
299 unsigned int cpu;
300
301 st->local_state = 0;
302
303 /*
304 * Shared state setup happens once on the first bringup
305 * of the CPU. It's not destroyed on CPU hotunplug.
306 */
307 if (st->shared_state)
308 return;
309
310 raw_spin_lock_init(&st->lock);
311
312 /*
313 * Go over HT siblings and check whether one of them has set up the
314 * shared state pointer already.
315 */
316 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
317 if (cpu == this_cpu)
318 continue;
319
320 if (!per_cpu(ssb_state, cpu).shared_state)
321 continue;
322
323 /* Link it to the state of the sibling: */
324 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
325 return;
326 }
327
328 /*
329 * First HT sibling to come up on the core. Link shared state of
330 * the first HT sibling to itself. The siblings on the same core
331 * which come up later will see the shared state pointer and link
332 * themself to the state of this CPU.
333 */
334 st->shared_state = st;
335}
336
337/*
338 * Logic is: First HT sibling enables SSBD for both siblings in the core
339 * and last sibling to disable it, disables it for the whole core. This how
340 * MSR_SPEC_CTRL works in "hardware":
341 *
342 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
343 */
344static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
345{
346 struct ssb_state *st = this_cpu_ptr(&ssb_state);
347 u64 msr = x86_amd_ls_cfg_base;
348
349 if (!static_cpu_has(X86_FEATURE_ZEN)) {
350 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
351 wrmsrl(MSR_AMD64_LS_CFG, msr);
352 return;
353 }
354
355 if (tifn & _TIF_SSBD) {
356 /*
357 * Since this can race with prctl(), block reentry on the
358 * same CPU.
359 */
360 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
361 return;
362
363 msr |= x86_amd_ls_cfg_ssbd_mask;
364
365 raw_spin_lock(&st->shared_state->lock);
366 /* First sibling enables SSBD: */
367 if (!st->shared_state->disable_state)
368 wrmsrl(MSR_AMD64_LS_CFG, msr);
369 st->shared_state->disable_state++;
370 raw_spin_unlock(&st->shared_state->lock);
371 } else {
372 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
373 return;
374
375 raw_spin_lock(&st->shared_state->lock);
376 st->shared_state->disable_state--;
377 if (!st->shared_state->disable_state)
378 wrmsrl(MSR_AMD64_LS_CFG, msr);
379 raw_spin_unlock(&st->shared_state->lock);
380 }
381}
382#else
383static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
384{
385 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
386
387 wrmsrl(MSR_AMD64_LS_CFG, msr);
388}
389#endif
390
391static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
392{
393 /*
394 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
395 * so ssbd_tif_to_spec_ctrl() just works.
396 */
397 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
398}
399
400static __always_inline void intel_set_ssb_state(unsigned long tifn)
401{
402 u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
403
404 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
405}
406
407static __always_inline void __speculative_store_bypass_update(unsigned long tifn)
408{
409 if (static_cpu_has(X86_FEATURE_VIRT_SSBD))
410 amd_set_ssb_virt_state(tifn);
411 else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
412 amd_set_core_ssb_state(tifn);
413 else
414 intel_set_ssb_state(tifn);
415}
416
417void speculative_store_bypass_update(unsigned long tif)
418{
419 preempt_disable();
420 __speculative_store_bypass_update(tif);
421 preempt_enable();
422}
423
424void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
425 struct tss_struct *tss)
426{
427 struct thread_struct *prev, *next;
428 unsigned long tifp, tifn;
429
430 prev = &prev_p->thread;
431 next = &next_p->thread;
432
433 tifn = READ_ONCE(task_thread_info(next_p)->flags);
434 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
435 switch_to_bitmap(tss, prev, next, tifp, tifn);
436
437 propagate_user_return_notify(prev_p, next_p);
438
439 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
440 arch_has_block_step()) {
441 unsigned long debugctl, msk;
442
443 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
444 debugctl &= ~DEBUGCTLMSR_BTF;
445 msk = tifn & _TIF_BLOCKSTEP;
446 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
447 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
448 }
449
450 if ((tifp ^ tifn) & _TIF_NOTSC)
451 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
452
453 if ((tifp ^ tifn) & _TIF_NOCPUID)
454 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
455
456 if ((tifp ^ tifn) & _TIF_SSBD)
457 __speculative_store_bypass_update(tifn);
458}
459
460/*
461 * Idle related variables and functions
462 */
463unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
464EXPORT_SYMBOL(boot_option_idle_override);
465
466static void (*x86_idle)(void);
467
468#ifndef CONFIG_SMP
469static inline void play_dead(void)
470{
471 BUG();
472}
473#endif
474
475void arch_cpu_idle_enter(void)
476{
477 tsc_verify_tsc_adjust(false);
478 local_touch_nmi();
479}
480
481void arch_cpu_idle_dead(void)
482{
483 play_dead();
484}
485
486/*
487 * Called from the generic idle code.
488 */
489void arch_cpu_idle(void)
490{
491 x86_idle();
492}
493
494/*
495 * We use this if we don't have any better idle routine..
496 */
497void __cpuidle default_idle(void)
498{
499 trace_cpu_idle_rcuidle(1, smp_processor_id());
500 safe_halt();
501 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
502}
503#ifdef CONFIG_APM_MODULE
504EXPORT_SYMBOL(default_idle);
505#endif
506
507#ifdef CONFIG_XEN
508bool xen_set_default_idle(void)
509{
510 bool ret = !!x86_idle;
511
512 x86_idle = default_idle;
513
514 return ret;
515}
516#endif
517
518void stop_this_cpu(void *dummy)
519{
520 local_irq_disable();
521 /*
522 * Remove this CPU:
523 */
524 set_cpu_online(smp_processor_id(), false);
525 disable_local_APIC();
526 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
527
528 /*
529 * Use wbinvd on processors that support SME. This provides support
530 * for performing a successful kexec when going from SME inactive
531 * to SME active (or vice-versa). The cache must be cleared so that
532 * if there are entries with the same physical address, both with and
533 * without the encryption bit, they don't race each other when flushed
534 * and potentially end up with the wrong entry being committed to
535 * memory.
536 */
537 if (boot_cpu_has(X86_FEATURE_SME))
538 native_wbinvd();
539 for (;;) {
540 /*
541 * Use native_halt() so that memory contents don't change
542 * (stack usage and variables) after possibly issuing the
543 * native_wbinvd() above.
544 */
545 native_halt();
546 }
547}
548
549/*
550 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
551 * states (local apic timer and TSC stop).
552 */
553static void amd_e400_idle(void)
554{
555 /*
556 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
557 * gets set after static_cpu_has() places have been converted via
558 * alternatives.
559 */
560 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
561 default_idle();
562 return;
563 }
564
565 tick_broadcast_enter();
566
567 default_idle();
568
569 /*
570 * The switch back from broadcast mode needs to be called with
571 * interrupts disabled.
572 */
573 local_irq_disable();
574 tick_broadcast_exit();
575 local_irq_enable();
576}
577
578/*
579 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
580 * We can't rely on cpuidle installing MWAIT, because it will not load
581 * on systems that support only C1 -- so the boot default must be MWAIT.
582 *
583 * Some AMD machines are the opposite, they depend on using HALT.
584 *
585 * So for default C1, which is used during boot until cpuidle loads,
586 * use MWAIT-C1 on Intel HW that has it, else use HALT.
587 */
588static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
589{
590 if (c->x86_vendor != X86_VENDOR_INTEL)
591 return 0;
592
593 if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
594 return 0;
595
596 return 1;
597}
598
599/*
600 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
601 * with interrupts enabled and no flags, which is backwards compatible with the
602 * original MWAIT implementation.
603 */
604static __cpuidle void mwait_idle(void)
605{
606 if (!current_set_polling_and_test()) {
607 trace_cpu_idle_rcuidle(1, smp_processor_id());
608 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
609 mb(); /* quirk */
610 clflush((void *)¤t_thread_info()->flags);
611 mb(); /* quirk */
612 }
613
614 __monitor((void *)¤t_thread_info()->flags, 0, 0);
615 if (!need_resched())
616 __sti_mwait(0, 0);
617 else
618 local_irq_enable();
619 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
620 } else {
621 local_irq_enable();
622 }
623 __current_clr_polling();
624}
625
626void select_idle_routine(const struct cpuinfo_x86 *c)
627{
628#ifdef CONFIG_SMP
629 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
630 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
631#endif
632 if (x86_idle || boot_option_idle_override == IDLE_POLL)
633 return;
634
635 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
636 pr_info("using AMD E400 aware idle routine\n");
637 x86_idle = amd_e400_idle;
638 } else if (prefer_mwait_c1_over_halt(c)) {
639 pr_info("using mwait in idle threads\n");
640 x86_idle = mwait_idle;
641 } else
642 x86_idle = default_idle;
643}
644
645void amd_e400_c1e_apic_setup(void)
646{
647 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
648 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
649 local_irq_disable();
650 tick_broadcast_force();
651 local_irq_enable();
652 }
653}
654
655void __init arch_post_acpi_subsys_init(void)
656{
657 u32 lo, hi;
658
659 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
660 return;
661
662 /*
663 * AMD E400 detection needs to happen after ACPI has been enabled. If
664 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
665 * MSR_K8_INT_PENDING_MSG.
666 */
667 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
668 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
669 return;
670
671 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
672
673 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
674 mark_tsc_unstable("TSC halt in AMD C1E");
675 pr_info("System has AMD C1E enabled\n");
676}
677
678static int __init idle_setup(char *str)
679{
680 if (!str)
681 return -EINVAL;
682
683 if (!strcmp(str, "poll")) {
684 pr_info("using polling idle threads\n");
685 boot_option_idle_override = IDLE_POLL;
686 cpu_idle_poll_ctrl(true);
687 } else if (!strcmp(str, "halt")) {
688 /*
689 * When the boot option of idle=halt is added, halt is
690 * forced to be used for CPU idle. In such case CPU C2/C3
691 * won't be used again.
692 * To continue to load the CPU idle driver, don't touch
693 * the boot_option_idle_override.
694 */
695 x86_idle = default_idle;
696 boot_option_idle_override = IDLE_HALT;
697 } else if (!strcmp(str, "nomwait")) {
698 /*
699 * If the boot option of "idle=nomwait" is added,
700 * it means that mwait will be disabled for CPU C2/C3
701 * states. In such case it won't touch the variable
702 * of boot_option_idle_override.
703 */
704 boot_option_idle_override = IDLE_NOMWAIT;
705 } else
706 return -1;
707
708 return 0;
709}
710early_param("idle", idle_setup);
711
712unsigned long arch_align_stack(unsigned long sp)
713{
714 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
715 sp -= get_random_int() % 8192;
716 return sp & ~0xf;
717}
718
719unsigned long arch_randomize_brk(struct mm_struct *mm)
720{
721 return randomize_page(mm->brk, 0x02000000);
722}
723
724/*
725 * Called from fs/proc with a reference on @p to find the function
726 * which called into schedule(). This needs to be done carefully
727 * because the task might wake up and we might look at a stack
728 * changing under us.
729 */
730unsigned long get_wchan(struct task_struct *p)
731{
732 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
733 int count = 0;
734
735 if (!p || p == current || p->state == TASK_RUNNING)
736 return 0;
737
738 if (!try_get_task_stack(p))
739 return 0;
740
741 start = (unsigned long)task_stack_page(p);
742 if (!start)
743 goto out;
744
745 /*
746 * Layout of the stack page:
747 *
748 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
749 * PADDING
750 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
751 * stack
752 * ----------- bottom = start
753 *
754 * The tasks stack pointer points at the location where the
755 * framepointer is stored. The data on the stack is:
756 * ... IP FP ... IP FP
757 *
758 * We need to read FP and IP, so we need to adjust the upper
759 * bound by another unsigned long.
760 */
761 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
762 top -= 2 * sizeof(unsigned long);
763 bottom = start;
764
765 sp = READ_ONCE(p->thread.sp);
766 if (sp < bottom || sp > top)
767 goto out;
768
769 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
770 do {
771 if (fp < bottom || fp > top)
772 goto out;
773 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
774 if (!in_sched_functions(ip)) {
775 ret = ip;
776 goto out;
777 }
778 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
779 } while (count++ < 16 && p->state != TASK_RUNNING);
780
781out:
782 put_task_stack(p);
783 return ret;
784}
785
786long do_arch_prctl_common(struct task_struct *task, int option,
787 unsigned long cpuid_enabled)
788{
789 switch (option) {
790 case ARCH_GET_CPUID:
791 return get_cpuid_mode();
792 case ARCH_SET_CPUID:
793 return set_cpuid_mode(task, cpuid_enabled);
794 }
795
796 return -EINVAL;
797}
1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/prctl.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <linux/sched/idle.h>
12#include <linux/sched/debug.h>
13#include <linux/sched/task.h>
14#include <linux/sched/task_stack.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/pm.h>
18#include <linux/tick.h>
19#include <linux/random.h>
20#include <linux/user-return-notifier.h>
21#include <linux/dmi.h>
22#include <linux/utsname.h>
23#include <linux/stackprotector.h>
24#include <linux/cpuidle.h>
25#include <linux/acpi.h>
26#include <linux/elf-randomize.h>
27#include <trace/events/power.h>
28#include <linux/hw_breakpoint.h>
29#include <asm/cpu.h>
30#include <asm/apic.h>
31#include <linux/uaccess.h>
32#include <asm/mwait.h>
33#include <asm/fpu/api.h>
34#include <asm/fpu/sched.h>
35#include <asm/fpu/xstate.h>
36#include <asm/debugreg.h>
37#include <asm/nmi.h>
38#include <asm/tlbflush.h>
39#include <asm/mce.h>
40#include <asm/vm86.h>
41#include <asm/switch_to.h>
42#include <asm/desc.h>
43#include <asm/prctl.h>
44#include <asm/spec-ctrl.h>
45#include <asm/io_bitmap.h>
46#include <asm/proto.h>
47#include <asm/frame.h>
48#include <asm/unwind.h>
49#include <asm/tdx.h>
50
51#include "process.h"
52
53/*
54 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
55 * no more per-task TSS's. The TSS size is kept cacheline-aligned
56 * so they are allowed to end up in the .data..cacheline_aligned
57 * section. Since TSS's are completely CPU-local, we want them
58 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
59 */
60__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
61 .x86_tss = {
62 /*
63 * .sp0 is only used when entering ring 0 from a lower
64 * privilege level. Since the init task never runs anything
65 * but ring 0 code, there is no need for a valid value here.
66 * Poison it.
67 */
68 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
69
70#ifdef CONFIG_X86_32
71 .sp1 = TOP_OF_INIT_STACK,
72
73 .ss0 = __KERNEL_DS,
74 .ss1 = __KERNEL_CS,
75#endif
76 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
77 },
78};
79EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
80
81DEFINE_PER_CPU(bool, __tss_limit_invalid);
82EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
83
84/*
85 * this gets called so that we can store lazy state into memory and copy the
86 * current task into the new thread.
87 */
88int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
89{
90 memcpy(dst, src, arch_task_struct_size);
91#ifdef CONFIG_VM86
92 dst->thread.vm86 = NULL;
93#endif
94 /* Drop the copied pointer to current's fpstate */
95 dst->thread.fpu.fpstate = NULL;
96
97 return 0;
98}
99
100#ifdef CONFIG_X86_64
101void arch_release_task_struct(struct task_struct *tsk)
102{
103 if (fpu_state_size_dynamic())
104 fpstate_free(&tsk->thread.fpu);
105}
106#endif
107
108/*
109 * Free thread data structures etc..
110 */
111void exit_thread(struct task_struct *tsk)
112{
113 struct thread_struct *t = &tsk->thread;
114 struct fpu *fpu = &t->fpu;
115
116 if (test_thread_flag(TIF_IO_BITMAP))
117 io_bitmap_exit(tsk);
118
119 free_vm86(t);
120
121 fpu__drop(fpu);
122}
123
124static int set_new_tls(struct task_struct *p, unsigned long tls)
125{
126 struct user_desc __user *utls = (struct user_desc __user *)tls;
127
128 if (in_ia32_syscall())
129 return do_set_thread_area(p, -1, utls, 0);
130 else
131 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
132}
133
134int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
135{
136 unsigned long clone_flags = args->flags;
137 unsigned long sp = args->stack;
138 unsigned long tls = args->tls;
139 struct inactive_task_frame *frame;
140 struct fork_frame *fork_frame;
141 struct pt_regs *childregs;
142 int ret = 0;
143
144 childregs = task_pt_regs(p);
145 fork_frame = container_of(childregs, struct fork_frame, regs);
146 frame = &fork_frame->frame;
147
148 frame->bp = encode_frame_pointer(childregs);
149 frame->ret_addr = (unsigned long) ret_from_fork;
150 p->thread.sp = (unsigned long) fork_frame;
151 p->thread.io_bitmap = NULL;
152 p->thread.iopl_warn = 0;
153 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
154
155#ifdef CONFIG_X86_64
156 current_save_fsgs();
157 p->thread.fsindex = current->thread.fsindex;
158 p->thread.fsbase = current->thread.fsbase;
159 p->thread.gsindex = current->thread.gsindex;
160 p->thread.gsbase = current->thread.gsbase;
161
162 savesegment(es, p->thread.es);
163 savesegment(ds, p->thread.ds);
164#else
165 p->thread.sp0 = (unsigned long) (childregs + 1);
166 savesegment(gs, p->thread.gs);
167 /*
168 * Clear all status flags including IF and set fixed bit. 64bit
169 * does not have this initialization as the frame does not contain
170 * flags. The flags consistency (especially vs. AC) is there
171 * ensured via objtool, which lacks 32bit support.
172 */
173 frame->flags = X86_EFLAGS_FIXED;
174#endif
175
176 fpu_clone(p, clone_flags, args->fn);
177
178 /* Kernel thread ? */
179 if (unlikely(p->flags & PF_KTHREAD)) {
180 p->thread.pkru = pkru_get_init_value();
181 memset(childregs, 0, sizeof(struct pt_regs));
182 kthread_frame_init(frame, args->fn, args->fn_arg);
183 return 0;
184 }
185
186 /*
187 * Clone current's PKRU value from hardware. tsk->thread.pkru
188 * is only valid when scheduled out.
189 */
190 p->thread.pkru = read_pkru();
191
192 frame->bx = 0;
193 *childregs = *current_pt_regs();
194 childregs->ax = 0;
195 if (sp)
196 childregs->sp = sp;
197
198 if (unlikely(args->fn)) {
199 /*
200 * A user space thread, but it doesn't return to
201 * ret_after_fork().
202 *
203 * In order to indicate that to tools like gdb,
204 * we reset the stack and instruction pointers.
205 *
206 * It does the same kernel frame setup to return to a kernel
207 * function that a kernel thread does.
208 */
209 childregs->sp = 0;
210 childregs->ip = 0;
211 kthread_frame_init(frame, args->fn, args->fn_arg);
212 return 0;
213 }
214
215 /* Set a new TLS for the child thread? */
216 if (clone_flags & CLONE_SETTLS)
217 ret = set_new_tls(p, tls);
218
219 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
220 io_bitmap_share(p);
221
222 return ret;
223}
224
225static void pkru_flush_thread(void)
226{
227 /*
228 * If PKRU is enabled the default PKRU value has to be loaded into
229 * the hardware right here (similar to context switch).
230 */
231 pkru_write_default();
232}
233
234void flush_thread(void)
235{
236 struct task_struct *tsk = current;
237
238 flush_ptrace_hw_breakpoint(tsk);
239 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
240
241 fpu_flush_thread();
242 pkru_flush_thread();
243}
244
245void disable_TSC(void)
246{
247 preempt_disable();
248 if (!test_and_set_thread_flag(TIF_NOTSC))
249 /*
250 * Must flip the CPU state synchronously with
251 * TIF_NOTSC in the current running context.
252 */
253 cr4_set_bits(X86_CR4_TSD);
254 preempt_enable();
255}
256
257static void enable_TSC(void)
258{
259 preempt_disable();
260 if (test_and_clear_thread_flag(TIF_NOTSC))
261 /*
262 * Must flip the CPU state synchronously with
263 * TIF_NOTSC in the current running context.
264 */
265 cr4_clear_bits(X86_CR4_TSD);
266 preempt_enable();
267}
268
269int get_tsc_mode(unsigned long adr)
270{
271 unsigned int val;
272
273 if (test_thread_flag(TIF_NOTSC))
274 val = PR_TSC_SIGSEGV;
275 else
276 val = PR_TSC_ENABLE;
277
278 return put_user(val, (unsigned int __user *)adr);
279}
280
281int set_tsc_mode(unsigned int val)
282{
283 if (val == PR_TSC_SIGSEGV)
284 disable_TSC();
285 else if (val == PR_TSC_ENABLE)
286 enable_TSC();
287 else
288 return -EINVAL;
289
290 return 0;
291}
292
293DEFINE_PER_CPU(u64, msr_misc_features_shadow);
294
295static void set_cpuid_faulting(bool on)
296{
297 u64 msrval;
298
299 msrval = this_cpu_read(msr_misc_features_shadow);
300 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
301 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
302 this_cpu_write(msr_misc_features_shadow, msrval);
303 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
304}
305
306static void disable_cpuid(void)
307{
308 preempt_disable();
309 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
310 /*
311 * Must flip the CPU state synchronously with
312 * TIF_NOCPUID in the current running context.
313 */
314 set_cpuid_faulting(true);
315 }
316 preempt_enable();
317}
318
319static void enable_cpuid(void)
320{
321 preempt_disable();
322 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
323 /*
324 * Must flip the CPU state synchronously with
325 * TIF_NOCPUID in the current running context.
326 */
327 set_cpuid_faulting(false);
328 }
329 preempt_enable();
330}
331
332static int get_cpuid_mode(void)
333{
334 return !test_thread_flag(TIF_NOCPUID);
335}
336
337static int set_cpuid_mode(unsigned long cpuid_enabled)
338{
339 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
340 return -ENODEV;
341
342 if (cpuid_enabled)
343 enable_cpuid();
344 else
345 disable_cpuid();
346
347 return 0;
348}
349
350/*
351 * Called immediately after a successful exec.
352 */
353void arch_setup_new_exec(void)
354{
355 /* If cpuid was previously disabled for this task, re-enable it. */
356 if (test_thread_flag(TIF_NOCPUID))
357 enable_cpuid();
358
359 /*
360 * Don't inherit TIF_SSBD across exec boundary when
361 * PR_SPEC_DISABLE_NOEXEC is used.
362 */
363 if (test_thread_flag(TIF_SSBD) &&
364 task_spec_ssb_noexec(current)) {
365 clear_thread_flag(TIF_SSBD);
366 task_clear_spec_ssb_disable(current);
367 task_clear_spec_ssb_noexec(current);
368 speculation_ctrl_update(read_thread_flags());
369 }
370}
371
372#ifdef CONFIG_X86_IOPL_IOPERM
373static inline void switch_to_bitmap(unsigned long tifp)
374{
375 /*
376 * Invalidate I/O bitmap if the previous task used it. This prevents
377 * any possible leakage of an active I/O bitmap.
378 *
379 * If the next task has an I/O bitmap it will handle it on exit to
380 * user mode.
381 */
382 if (tifp & _TIF_IO_BITMAP)
383 tss_invalidate_io_bitmap();
384}
385
386static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
387{
388 /*
389 * Copy at least the byte range of the incoming tasks bitmap which
390 * covers the permitted I/O ports.
391 *
392 * If the previous task which used an I/O bitmap had more bits
393 * permitted, then the copy needs to cover those as well so they
394 * get turned off.
395 */
396 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
397 max(tss->io_bitmap.prev_max, iobm->max));
398
399 /*
400 * Store the new max and the sequence number of this bitmap
401 * and a pointer to the bitmap itself.
402 */
403 tss->io_bitmap.prev_max = iobm->max;
404 tss->io_bitmap.prev_sequence = iobm->sequence;
405}
406
407/**
408 * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode
409 */
410void native_tss_update_io_bitmap(void)
411{
412 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
413 struct thread_struct *t = ¤t->thread;
414 u16 *base = &tss->x86_tss.io_bitmap_base;
415
416 if (!test_thread_flag(TIF_IO_BITMAP)) {
417 native_tss_invalidate_io_bitmap();
418 return;
419 }
420
421 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
422 *base = IO_BITMAP_OFFSET_VALID_ALL;
423 } else {
424 struct io_bitmap *iobm = t->io_bitmap;
425
426 /*
427 * Only copy bitmap data when the sequence number differs. The
428 * update time is accounted to the incoming task.
429 */
430 if (tss->io_bitmap.prev_sequence != iobm->sequence)
431 tss_copy_io_bitmap(tss, iobm);
432
433 /* Enable the bitmap */
434 *base = IO_BITMAP_OFFSET_VALID_MAP;
435 }
436
437 /*
438 * Make sure that the TSS limit is covering the IO bitmap. It might have
439 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
440 * access from user space to trigger a #GP because tbe bitmap is outside
441 * the TSS limit.
442 */
443 refresh_tss_limit();
444}
445#else /* CONFIG_X86_IOPL_IOPERM */
446static inline void switch_to_bitmap(unsigned long tifp) { }
447#endif
448
449#ifdef CONFIG_SMP
450
451struct ssb_state {
452 struct ssb_state *shared_state;
453 raw_spinlock_t lock;
454 unsigned int disable_state;
455 unsigned long local_state;
456};
457
458#define LSTATE_SSB 0
459
460static DEFINE_PER_CPU(struct ssb_state, ssb_state);
461
462void speculative_store_bypass_ht_init(void)
463{
464 struct ssb_state *st = this_cpu_ptr(&ssb_state);
465 unsigned int this_cpu = smp_processor_id();
466 unsigned int cpu;
467
468 st->local_state = 0;
469
470 /*
471 * Shared state setup happens once on the first bringup
472 * of the CPU. It's not destroyed on CPU hotunplug.
473 */
474 if (st->shared_state)
475 return;
476
477 raw_spin_lock_init(&st->lock);
478
479 /*
480 * Go over HT siblings and check whether one of them has set up the
481 * shared state pointer already.
482 */
483 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
484 if (cpu == this_cpu)
485 continue;
486
487 if (!per_cpu(ssb_state, cpu).shared_state)
488 continue;
489
490 /* Link it to the state of the sibling: */
491 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
492 return;
493 }
494
495 /*
496 * First HT sibling to come up on the core. Link shared state of
497 * the first HT sibling to itself. The siblings on the same core
498 * which come up later will see the shared state pointer and link
499 * themselves to the state of this CPU.
500 */
501 st->shared_state = st;
502}
503
504/*
505 * Logic is: First HT sibling enables SSBD for both siblings in the core
506 * and last sibling to disable it, disables it for the whole core. This how
507 * MSR_SPEC_CTRL works in "hardware":
508 *
509 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
510 */
511static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
512{
513 struct ssb_state *st = this_cpu_ptr(&ssb_state);
514 u64 msr = x86_amd_ls_cfg_base;
515
516 if (!static_cpu_has(X86_FEATURE_ZEN)) {
517 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
518 wrmsrl(MSR_AMD64_LS_CFG, msr);
519 return;
520 }
521
522 if (tifn & _TIF_SSBD) {
523 /*
524 * Since this can race with prctl(), block reentry on the
525 * same CPU.
526 */
527 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
528 return;
529
530 msr |= x86_amd_ls_cfg_ssbd_mask;
531
532 raw_spin_lock(&st->shared_state->lock);
533 /* First sibling enables SSBD: */
534 if (!st->shared_state->disable_state)
535 wrmsrl(MSR_AMD64_LS_CFG, msr);
536 st->shared_state->disable_state++;
537 raw_spin_unlock(&st->shared_state->lock);
538 } else {
539 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
540 return;
541
542 raw_spin_lock(&st->shared_state->lock);
543 st->shared_state->disable_state--;
544 if (!st->shared_state->disable_state)
545 wrmsrl(MSR_AMD64_LS_CFG, msr);
546 raw_spin_unlock(&st->shared_state->lock);
547 }
548}
549#else
550static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
551{
552 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
553
554 wrmsrl(MSR_AMD64_LS_CFG, msr);
555}
556#endif
557
558static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
559{
560 /*
561 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
562 * so ssbd_tif_to_spec_ctrl() just works.
563 */
564 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
565}
566
567/*
568 * Update the MSRs managing speculation control, during context switch.
569 *
570 * tifp: Previous task's thread flags
571 * tifn: Next task's thread flags
572 */
573static __always_inline void __speculation_ctrl_update(unsigned long tifp,
574 unsigned long tifn)
575{
576 unsigned long tif_diff = tifp ^ tifn;
577 u64 msr = x86_spec_ctrl_base;
578 bool updmsr = false;
579
580 lockdep_assert_irqs_disabled();
581
582 /* Handle change of TIF_SSBD depending on the mitigation method. */
583 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
584 if (tif_diff & _TIF_SSBD)
585 amd_set_ssb_virt_state(tifn);
586 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
587 if (tif_diff & _TIF_SSBD)
588 amd_set_core_ssb_state(tifn);
589 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
590 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
591 updmsr |= !!(tif_diff & _TIF_SSBD);
592 msr |= ssbd_tif_to_spec_ctrl(tifn);
593 }
594
595 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
596 if (IS_ENABLED(CONFIG_SMP) &&
597 static_branch_unlikely(&switch_to_cond_stibp)) {
598 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
599 msr |= stibp_tif_to_spec_ctrl(tifn);
600 }
601
602 if (updmsr)
603 update_spec_ctrl_cond(msr);
604}
605
606static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
607{
608 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
609 if (task_spec_ssb_disable(tsk))
610 set_tsk_thread_flag(tsk, TIF_SSBD);
611 else
612 clear_tsk_thread_flag(tsk, TIF_SSBD);
613
614 if (task_spec_ib_disable(tsk))
615 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
616 else
617 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
618 }
619 /* Return the updated threadinfo flags*/
620 return read_task_thread_flags(tsk);
621}
622
623void speculation_ctrl_update(unsigned long tif)
624{
625 unsigned long flags;
626
627 /* Forced update. Make sure all relevant TIF flags are different */
628 local_irq_save(flags);
629 __speculation_ctrl_update(~tif, tif);
630 local_irq_restore(flags);
631}
632
633/* Called from seccomp/prctl update */
634void speculation_ctrl_update_current(void)
635{
636 preempt_disable();
637 speculation_ctrl_update(speculation_ctrl_update_tif(current));
638 preempt_enable();
639}
640
641static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
642{
643 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
644
645 newval = cr4 ^ mask;
646 if (newval != cr4) {
647 this_cpu_write(cpu_tlbstate.cr4, newval);
648 __write_cr4(newval);
649 }
650}
651
652void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
653{
654 unsigned long tifp, tifn;
655
656 tifn = read_task_thread_flags(next_p);
657 tifp = read_task_thread_flags(prev_p);
658
659 switch_to_bitmap(tifp);
660
661 propagate_user_return_notify(prev_p, next_p);
662
663 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
664 arch_has_block_step()) {
665 unsigned long debugctl, msk;
666
667 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
668 debugctl &= ~DEBUGCTLMSR_BTF;
669 msk = tifn & _TIF_BLOCKSTEP;
670 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
671 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
672 }
673
674 if ((tifp ^ tifn) & _TIF_NOTSC)
675 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
676
677 if ((tifp ^ tifn) & _TIF_NOCPUID)
678 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
679
680 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
681 __speculation_ctrl_update(tifp, tifn);
682 } else {
683 speculation_ctrl_update_tif(prev_p);
684 tifn = speculation_ctrl_update_tif(next_p);
685
686 /* Enforce MSR update to ensure consistent state */
687 __speculation_ctrl_update(~tifn, tifn);
688 }
689}
690
691/*
692 * Idle related variables and functions
693 */
694unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
695EXPORT_SYMBOL(boot_option_idle_override);
696
697static void (*x86_idle)(void);
698
699#ifndef CONFIG_SMP
700static inline void play_dead(void)
701{
702 BUG();
703}
704#endif
705
706void arch_cpu_idle_enter(void)
707{
708 tsc_verify_tsc_adjust(false);
709 local_touch_nmi();
710}
711
712void arch_cpu_idle_dead(void)
713{
714 play_dead();
715}
716
717/*
718 * Called from the generic idle code.
719 */
720void arch_cpu_idle(void)
721{
722 x86_idle();
723}
724
725/*
726 * We use this if we don't have any better idle routine..
727 */
728void __cpuidle default_idle(void)
729{
730 raw_safe_halt();
731}
732#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
733EXPORT_SYMBOL(default_idle);
734#endif
735
736#ifdef CONFIG_XEN
737bool xen_set_default_idle(void)
738{
739 bool ret = !!x86_idle;
740
741 x86_idle = default_idle;
742
743 return ret;
744}
745#endif
746
747void __noreturn stop_this_cpu(void *dummy)
748{
749 local_irq_disable();
750 /*
751 * Remove this CPU:
752 */
753 set_cpu_online(smp_processor_id(), false);
754 disable_local_APIC();
755 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
756
757 /*
758 * Use wbinvd on processors that support SME. This provides support
759 * for performing a successful kexec when going from SME inactive
760 * to SME active (or vice-versa). The cache must be cleared so that
761 * if there are entries with the same physical address, both with and
762 * without the encryption bit, they don't race each other when flushed
763 * and potentially end up with the wrong entry being committed to
764 * memory.
765 *
766 * Test the CPUID bit directly because the machine might've cleared
767 * X86_FEATURE_SME due to cmdline options.
768 */
769 if (cpuid_eax(0x8000001f) & BIT(0))
770 native_wbinvd();
771 for (;;) {
772 /*
773 * Use native_halt() so that memory contents don't change
774 * (stack usage and variables) after possibly issuing the
775 * native_wbinvd() above.
776 */
777 native_halt();
778 }
779}
780
781/*
782 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
783 * states (local apic timer and TSC stop).
784 *
785 * XXX this function is completely buggered vs RCU and tracing.
786 */
787static void amd_e400_idle(void)
788{
789 /*
790 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
791 * gets set after static_cpu_has() places have been converted via
792 * alternatives.
793 */
794 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
795 default_idle();
796 return;
797 }
798
799 tick_broadcast_enter();
800
801 default_idle();
802
803 /*
804 * The switch back from broadcast mode needs to be called with
805 * interrupts disabled.
806 */
807 raw_local_irq_disable();
808 tick_broadcast_exit();
809 raw_local_irq_enable();
810}
811
812/*
813 * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf
814 * exists and whenever MONITOR/MWAIT extensions are present there is at
815 * least one C1 substate.
816 *
817 * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait
818 * is passed to kernel commandline parameter.
819 */
820static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
821{
822 u32 eax, ebx, ecx, edx;
823
824 /* User has disallowed the use of MWAIT. Fallback to HALT */
825 if (boot_option_idle_override == IDLE_NOMWAIT)
826 return 0;
827
828 /* MWAIT is not supported on this platform. Fallback to HALT */
829 if (!cpu_has(c, X86_FEATURE_MWAIT))
830 return 0;
831
832 /* Monitor has a bug. Fallback to HALT */
833 if (boot_cpu_has_bug(X86_BUG_MONITOR))
834 return 0;
835
836 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
837
838 /*
839 * If MWAIT extensions are not available, it is safe to use MWAIT
840 * with EAX=0, ECX=0.
841 */
842 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED))
843 return 1;
844
845 /*
846 * If MWAIT extensions are available, there should be at least one
847 * MWAIT C1 substate present.
848 */
849 return (edx & MWAIT_C1_SUBSTATE_MASK);
850}
851
852/*
853 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
854 * with interrupts enabled and no flags, which is backwards compatible with the
855 * original MWAIT implementation.
856 */
857static __cpuidle void mwait_idle(void)
858{
859 if (!current_set_polling_and_test()) {
860 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
861 mb(); /* quirk */
862 clflush((void *)¤t_thread_info()->flags);
863 mb(); /* quirk */
864 }
865
866 __monitor((void *)¤t_thread_info()->flags, 0, 0);
867 if (!need_resched())
868 __sti_mwait(0, 0);
869 else
870 raw_local_irq_enable();
871 } else {
872 raw_local_irq_enable();
873 }
874 __current_clr_polling();
875}
876
877void select_idle_routine(const struct cpuinfo_x86 *c)
878{
879#ifdef CONFIG_SMP
880 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
881 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
882#endif
883 if (x86_idle || boot_option_idle_override == IDLE_POLL)
884 return;
885
886 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
887 pr_info("using AMD E400 aware idle routine\n");
888 x86_idle = amd_e400_idle;
889 } else if (prefer_mwait_c1_over_halt(c)) {
890 pr_info("using mwait in idle threads\n");
891 x86_idle = mwait_idle;
892 } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
893 pr_info("using TDX aware idle routine\n");
894 x86_idle = tdx_safe_halt;
895 } else
896 x86_idle = default_idle;
897}
898
899void amd_e400_c1e_apic_setup(void)
900{
901 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
902 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
903 local_irq_disable();
904 tick_broadcast_force();
905 local_irq_enable();
906 }
907}
908
909void __init arch_post_acpi_subsys_init(void)
910{
911 u32 lo, hi;
912
913 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
914 return;
915
916 /*
917 * AMD E400 detection needs to happen after ACPI has been enabled. If
918 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
919 * MSR_K8_INT_PENDING_MSG.
920 */
921 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
922 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
923 return;
924
925 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
926
927 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
928 mark_tsc_unstable("TSC halt in AMD C1E");
929 pr_info("System has AMD C1E enabled\n");
930}
931
932static int __init idle_setup(char *str)
933{
934 if (!str)
935 return -EINVAL;
936
937 if (!strcmp(str, "poll")) {
938 pr_info("using polling idle threads\n");
939 boot_option_idle_override = IDLE_POLL;
940 cpu_idle_poll_ctrl(true);
941 } else if (!strcmp(str, "halt")) {
942 /*
943 * When the boot option of idle=halt is added, halt is
944 * forced to be used for CPU idle. In such case CPU C2/C3
945 * won't be used again.
946 * To continue to load the CPU idle driver, don't touch
947 * the boot_option_idle_override.
948 */
949 x86_idle = default_idle;
950 boot_option_idle_override = IDLE_HALT;
951 } else if (!strcmp(str, "nomwait")) {
952 /*
953 * If the boot option of "idle=nomwait" is added,
954 * it means that mwait will be disabled for CPU C1/C2/C3
955 * states.
956 */
957 boot_option_idle_override = IDLE_NOMWAIT;
958 } else
959 return -1;
960
961 return 0;
962}
963early_param("idle", idle_setup);
964
965unsigned long arch_align_stack(unsigned long sp)
966{
967 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
968 sp -= get_random_u32_below(8192);
969 return sp & ~0xf;
970}
971
972unsigned long arch_randomize_brk(struct mm_struct *mm)
973{
974 return randomize_page(mm->brk, 0x02000000);
975}
976
977/*
978 * Called from fs/proc with a reference on @p to find the function
979 * which called into schedule(). This needs to be done carefully
980 * because the task might wake up and we might look at a stack
981 * changing under us.
982 */
983unsigned long __get_wchan(struct task_struct *p)
984{
985 struct unwind_state state;
986 unsigned long addr = 0;
987
988 if (!try_get_task_stack(p))
989 return 0;
990
991 for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state);
992 unwind_next_frame(&state)) {
993 addr = unwind_get_return_address(&state);
994 if (!addr)
995 break;
996 if (in_sched_functions(addr))
997 continue;
998 break;
999 }
1000
1001 put_task_stack(p);
1002
1003 return addr;
1004}
1005
1006long do_arch_prctl_common(int option, unsigned long arg2)
1007{
1008 switch (option) {
1009 case ARCH_GET_CPUID:
1010 return get_cpuid_mode();
1011 case ARCH_SET_CPUID:
1012 return set_cpuid_mode(arg2);
1013 case ARCH_GET_XCOMP_SUPP:
1014 case ARCH_GET_XCOMP_PERM:
1015 case ARCH_REQ_XCOMP_PERM:
1016 case ARCH_GET_XCOMP_GUEST_PERM:
1017 case ARCH_REQ_XCOMP_GUEST_PERM:
1018 return fpu_xstate_prctl(option, arg2);
1019 }
1020
1021 return -EINVAL;
1022}