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1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/prctl.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <linux/sched/idle.h>
12#include <linux/sched/debug.h>
13#include <linux/sched/task.h>
14#include <linux/sched/task_stack.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/pm.h>
18#include <linux/tick.h>
19#include <linux/random.h>
20#include <linux/user-return-notifier.h>
21#include <linux/dmi.h>
22#include <linux/utsname.h>
23#include <linux/stackprotector.h>
24#include <linux/cpuidle.h>
25#include <trace/events/power.h>
26#include <linux/hw_breakpoint.h>
27#include <asm/cpu.h>
28#include <asm/apic.h>
29#include <asm/syscalls.h>
30#include <linux/uaccess.h>
31#include <asm/mwait.h>
32#include <asm/fpu/internal.h>
33#include <asm/debugreg.h>
34#include <asm/nmi.h>
35#include <asm/tlbflush.h>
36#include <asm/mce.h>
37#include <asm/vm86.h>
38#include <asm/switch_to.h>
39#include <asm/desc.h>
40#include <asm/prctl.h>
41#include <asm/spec-ctrl.h>
42
43/*
44 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
45 * no more per-task TSS's. The TSS size is kept cacheline-aligned
46 * so they are allowed to end up in the .data..cacheline_aligned
47 * section. Since TSS's are completely CPU-local, we want them
48 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
49 */
50__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
51 .x86_tss = {
52 /*
53 * .sp0 is only used when entering ring 0 from a lower
54 * privilege level. Since the init task never runs anything
55 * but ring 0 code, there is no need for a valid value here.
56 * Poison it.
57 */
58 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
59
60#ifdef CONFIG_X86_64
61 /*
62 * .sp1 is cpu_current_top_of_stack. The init task never
63 * runs user code, but cpu_current_top_of_stack should still
64 * be well defined before the first context switch.
65 */
66 .sp1 = TOP_OF_INIT_STACK,
67#endif
68
69#ifdef CONFIG_X86_32
70 .ss0 = __KERNEL_DS,
71 .ss1 = __KERNEL_CS,
72 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
73#endif
74 },
75#ifdef CONFIG_X86_32
76 /*
77 * Note that the .io_bitmap member must be extra-big. This is because
78 * the CPU will access an additional byte beyond the end of the IO
79 * permission bitmap. The extra byte must be all 1 bits, and must
80 * be within the limit.
81 */
82 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
83#endif
84};
85EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
86
87DEFINE_PER_CPU(bool, __tss_limit_invalid);
88EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
89
90/*
91 * this gets called so that we can store lazy state into memory and copy the
92 * current task into the new thread.
93 */
94int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
95{
96 memcpy(dst, src, arch_task_struct_size);
97#ifdef CONFIG_VM86
98 dst->thread.vm86 = NULL;
99#endif
100
101 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
102}
103
104/*
105 * Free current thread data structures etc..
106 */
107void exit_thread(struct task_struct *tsk)
108{
109 struct thread_struct *t = &tsk->thread;
110 unsigned long *bp = t->io_bitmap_ptr;
111 struct fpu *fpu = &t->fpu;
112
113 if (bp) {
114 struct tss_struct *tss = &per_cpu(cpu_tss_rw, get_cpu());
115
116 t->io_bitmap_ptr = NULL;
117 clear_thread_flag(TIF_IO_BITMAP);
118 /*
119 * Careful, clear this in the TSS too:
120 */
121 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
122 t->io_bitmap_max = 0;
123 put_cpu();
124 kfree(bp);
125 }
126
127 free_vm86(t);
128
129 fpu__drop(fpu);
130}
131
132void flush_thread(void)
133{
134 struct task_struct *tsk = current;
135
136 flush_ptrace_hw_breakpoint(tsk);
137 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
138
139 fpu__clear(&tsk->thread.fpu);
140}
141
142void disable_TSC(void)
143{
144 preempt_disable();
145 if (!test_and_set_thread_flag(TIF_NOTSC))
146 /*
147 * Must flip the CPU state synchronously with
148 * TIF_NOTSC in the current running context.
149 */
150 cr4_set_bits(X86_CR4_TSD);
151 preempt_enable();
152}
153
154static void enable_TSC(void)
155{
156 preempt_disable();
157 if (test_and_clear_thread_flag(TIF_NOTSC))
158 /*
159 * Must flip the CPU state synchronously with
160 * TIF_NOTSC in the current running context.
161 */
162 cr4_clear_bits(X86_CR4_TSD);
163 preempt_enable();
164}
165
166int get_tsc_mode(unsigned long adr)
167{
168 unsigned int val;
169
170 if (test_thread_flag(TIF_NOTSC))
171 val = PR_TSC_SIGSEGV;
172 else
173 val = PR_TSC_ENABLE;
174
175 return put_user(val, (unsigned int __user *)adr);
176}
177
178int set_tsc_mode(unsigned int val)
179{
180 if (val == PR_TSC_SIGSEGV)
181 disable_TSC();
182 else if (val == PR_TSC_ENABLE)
183 enable_TSC();
184 else
185 return -EINVAL;
186
187 return 0;
188}
189
190DEFINE_PER_CPU(u64, msr_misc_features_shadow);
191
192static void set_cpuid_faulting(bool on)
193{
194 u64 msrval;
195
196 msrval = this_cpu_read(msr_misc_features_shadow);
197 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
198 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
199 this_cpu_write(msr_misc_features_shadow, msrval);
200 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
201}
202
203static void disable_cpuid(void)
204{
205 preempt_disable();
206 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
207 /*
208 * Must flip the CPU state synchronously with
209 * TIF_NOCPUID in the current running context.
210 */
211 set_cpuid_faulting(true);
212 }
213 preempt_enable();
214}
215
216static void enable_cpuid(void)
217{
218 preempt_disable();
219 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
220 /*
221 * Must flip the CPU state synchronously with
222 * TIF_NOCPUID in the current running context.
223 */
224 set_cpuid_faulting(false);
225 }
226 preempt_enable();
227}
228
229static int get_cpuid_mode(void)
230{
231 return !test_thread_flag(TIF_NOCPUID);
232}
233
234static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
235{
236 if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
237 return -ENODEV;
238
239 if (cpuid_enabled)
240 enable_cpuid();
241 else
242 disable_cpuid();
243
244 return 0;
245}
246
247/*
248 * Called immediately after a successful exec.
249 */
250void arch_setup_new_exec(void)
251{
252 /* If cpuid was previously disabled for this task, re-enable it. */
253 if (test_thread_flag(TIF_NOCPUID))
254 enable_cpuid();
255}
256
257static inline void switch_to_bitmap(struct tss_struct *tss,
258 struct thread_struct *prev,
259 struct thread_struct *next,
260 unsigned long tifp, unsigned long tifn)
261{
262 if (tifn & _TIF_IO_BITMAP) {
263 /*
264 * Copy the relevant range of the IO bitmap.
265 * Normally this is 128 bytes or less:
266 */
267 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
268 max(prev->io_bitmap_max, next->io_bitmap_max));
269 /*
270 * Make sure that the TSS limit is correct for the CPU
271 * to notice the IO bitmap.
272 */
273 refresh_tss_limit();
274 } else if (tifp & _TIF_IO_BITMAP) {
275 /*
276 * Clear any possible leftover bits:
277 */
278 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
279 }
280}
281
282#ifdef CONFIG_SMP
283
284struct ssb_state {
285 struct ssb_state *shared_state;
286 raw_spinlock_t lock;
287 unsigned int disable_state;
288 unsigned long local_state;
289};
290
291#define LSTATE_SSB 0
292
293static DEFINE_PER_CPU(struct ssb_state, ssb_state);
294
295void speculative_store_bypass_ht_init(void)
296{
297 struct ssb_state *st = this_cpu_ptr(&ssb_state);
298 unsigned int this_cpu = smp_processor_id();
299 unsigned int cpu;
300
301 st->local_state = 0;
302
303 /*
304 * Shared state setup happens once on the first bringup
305 * of the CPU. It's not destroyed on CPU hotunplug.
306 */
307 if (st->shared_state)
308 return;
309
310 raw_spin_lock_init(&st->lock);
311
312 /*
313 * Go over HT siblings and check whether one of them has set up the
314 * shared state pointer already.
315 */
316 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
317 if (cpu == this_cpu)
318 continue;
319
320 if (!per_cpu(ssb_state, cpu).shared_state)
321 continue;
322
323 /* Link it to the state of the sibling: */
324 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
325 return;
326 }
327
328 /*
329 * First HT sibling to come up on the core. Link shared state of
330 * the first HT sibling to itself. The siblings on the same core
331 * which come up later will see the shared state pointer and link
332 * themself to the state of this CPU.
333 */
334 st->shared_state = st;
335}
336
337/*
338 * Logic is: First HT sibling enables SSBD for both siblings in the core
339 * and last sibling to disable it, disables it for the whole core. This how
340 * MSR_SPEC_CTRL works in "hardware":
341 *
342 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
343 */
344static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
345{
346 struct ssb_state *st = this_cpu_ptr(&ssb_state);
347 u64 msr = x86_amd_ls_cfg_base;
348
349 if (!static_cpu_has(X86_FEATURE_ZEN)) {
350 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
351 wrmsrl(MSR_AMD64_LS_CFG, msr);
352 return;
353 }
354
355 if (tifn & _TIF_SSBD) {
356 /*
357 * Since this can race with prctl(), block reentry on the
358 * same CPU.
359 */
360 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
361 return;
362
363 msr |= x86_amd_ls_cfg_ssbd_mask;
364
365 raw_spin_lock(&st->shared_state->lock);
366 /* First sibling enables SSBD: */
367 if (!st->shared_state->disable_state)
368 wrmsrl(MSR_AMD64_LS_CFG, msr);
369 st->shared_state->disable_state++;
370 raw_spin_unlock(&st->shared_state->lock);
371 } else {
372 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
373 return;
374
375 raw_spin_lock(&st->shared_state->lock);
376 st->shared_state->disable_state--;
377 if (!st->shared_state->disable_state)
378 wrmsrl(MSR_AMD64_LS_CFG, msr);
379 raw_spin_unlock(&st->shared_state->lock);
380 }
381}
382#else
383static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
384{
385 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
386
387 wrmsrl(MSR_AMD64_LS_CFG, msr);
388}
389#endif
390
391static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
392{
393 /*
394 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
395 * so ssbd_tif_to_spec_ctrl() just works.
396 */
397 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
398}
399
400static __always_inline void intel_set_ssb_state(unsigned long tifn)
401{
402 u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
403
404 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
405}
406
407static __always_inline void __speculative_store_bypass_update(unsigned long tifn)
408{
409 if (static_cpu_has(X86_FEATURE_VIRT_SSBD))
410 amd_set_ssb_virt_state(tifn);
411 else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
412 amd_set_core_ssb_state(tifn);
413 else
414 intel_set_ssb_state(tifn);
415}
416
417void speculative_store_bypass_update(unsigned long tif)
418{
419 preempt_disable();
420 __speculative_store_bypass_update(tif);
421 preempt_enable();
422}
423
424void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
425 struct tss_struct *tss)
426{
427 struct thread_struct *prev, *next;
428 unsigned long tifp, tifn;
429
430 prev = &prev_p->thread;
431 next = &next_p->thread;
432
433 tifn = READ_ONCE(task_thread_info(next_p)->flags);
434 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
435 switch_to_bitmap(tss, prev, next, tifp, tifn);
436
437 propagate_user_return_notify(prev_p, next_p);
438
439 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
440 arch_has_block_step()) {
441 unsigned long debugctl, msk;
442
443 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
444 debugctl &= ~DEBUGCTLMSR_BTF;
445 msk = tifn & _TIF_BLOCKSTEP;
446 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
447 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
448 }
449
450 if ((tifp ^ tifn) & _TIF_NOTSC)
451 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
452
453 if ((tifp ^ tifn) & _TIF_NOCPUID)
454 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
455
456 if ((tifp ^ tifn) & _TIF_SSBD)
457 __speculative_store_bypass_update(tifn);
458}
459
460/*
461 * Idle related variables and functions
462 */
463unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
464EXPORT_SYMBOL(boot_option_idle_override);
465
466static void (*x86_idle)(void);
467
468#ifndef CONFIG_SMP
469static inline void play_dead(void)
470{
471 BUG();
472}
473#endif
474
475void arch_cpu_idle_enter(void)
476{
477 tsc_verify_tsc_adjust(false);
478 local_touch_nmi();
479}
480
481void arch_cpu_idle_dead(void)
482{
483 play_dead();
484}
485
486/*
487 * Called from the generic idle code.
488 */
489void arch_cpu_idle(void)
490{
491 x86_idle();
492}
493
494/*
495 * We use this if we don't have any better idle routine..
496 */
497void __cpuidle default_idle(void)
498{
499 trace_cpu_idle_rcuidle(1, smp_processor_id());
500 safe_halt();
501 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
502}
503#ifdef CONFIG_APM_MODULE
504EXPORT_SYMBOL(default_idle);
505#endif
506
507#ifdef CONFIG_XEN
508bool xen_set_default_idle(void)
509{
510 bool ret = !!x86_idle;
511
512 x86_idle = default_idle;
513
514 return ret;
515}
516#endif
517
518void stop_this_cpu(void *dummy)
519{
520 local_irq_disable();
521 /*
522 * Remove this CPU:
523 */
524 set_cpu_online(smp_processor_id(), false);
525 disable_local_APIC();
526 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
527
528 /*
529 * Use wbinvd on processors that support SME. This provides support
530 * for performing a successful kexec when going from SME inactive
531 * to SME active (or vice-versa). The cache must be cleared so that
532 * if there are entries with the same physical address, both with and
533 * without the encryption bit, they don't race each other when flushed
534 * and potentially end up with the wrong entry being committed to
535 * memory.
536 */
537 if (boot_cpu_has(X86_FEATURE_SME))
538 native_wbinvd();
539 for (;;) {
540 /*
541 * Use native_halt() so that memory contents don't change
542 * (stack usage and variables) after possibly issuing the
543 * native_wbinvd() above.
544 */
545 native_halt();
546 }
547}
548
549/*
550 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
551 * states (local apic timer and TSC stop).
552 */
553static void amd_e400_idle(void)
554{
555 /*
556 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
557 * gets set after static_cpu_has() places have been converted via
558 * alternatives.
559 */
560 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
561 default_idle();
562 return;
563 }
564
565 tick_broadcast_enter();
566
567 default_idle();
568
569 /*
570 * The switch back from broadcast mode needs to be called with
571 * interrupts disabled.
572 */
573 local_irq_disable();
574 tick_broadcast_exit();
575 local_irq_enable();
576}
577
578/*
579 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
580 * We can't rely on cpuidle installing MWAIT, because it will not load
581 * on systems that support only C1 -- so the boot default must be MWAIT.
582 *
583 * Some AMD machines are the opposite, they depend on using HALT.
584 *
585 * So for default C1, which is used during boot until cpuidle loads,
586 * use MWAIT-C1 on Intel HW that has it, else use HALT.
587 */
588static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
589{
590 if (c->x86_vendor != X86_VENDOR_INTEL)
591 return 0;
592
593 if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
594 return 0;
595
596 return 1;
597}
598
599/*
600 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
601 * with interrupts enabled and no flags, which is backwards compatible with the
602 * original MWAIT implementation.
603 */
604static __cpuidle void mwait_idle(void)
605{
606 if (!current_set_polling_and_test()) {
607 trace_cpu_idle_rcuidle(1, smp_processor_id());
608 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
609 mb(); /* quirk */
610 clflush((void *)¤t_thread_info()->flags);
611 mb(); /* quirk */
612 }
613
614 __monitor((void *)¤t_thread_info()->flags, 0, 0);
615 if (!need_resched())
616 __sti_mwait(0, 0);
617 else
618 local_irq_enable();
619 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
620 } else {
621 local_irq_enable();
622 }
623 __current_clr_polling();
624}
625
626void select_idle_routine(const struct cpuinfo_x86 *c)
627{
628#ifdef CONFIG_SMP
629 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
630 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
631#endif
632 if (x86_idle || boot_option_idle_override == IDLE_POLL)
633 return;
634
635 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
636 pr_info("using AMD E400 aware idle routine\n");
637 x86_idle = amd_e400_idle;
638 } else if (prefer_mwait_c1_over_halt(c)) {
639 pr_info("using mwait in idle threads\n");
640 x86_idle = mwait_idle;
641 } else
642 x86_idle = default_idle;
643}
644
645void amd_e400_c1e_apic_setup(void)
646{
647 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
648 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
649 local_irq_disable();
650 tick_broadcast_force();
651 local_irq_enable();
652 }
653}
654
655void __init arch_post_acpi_subsys_init(void)
656{
657 u32 lo, hi;
658
659 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
660 return;
661
662 /*
663 * AMD E400 detection needs to happen after ACPI has been enabled. If
664 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
665 * MSR_K8_INT_PENDING_MSG.
666 */
667 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
668 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
669 return;
670
671 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
672
673 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
674 mark_tsc_unstable("TSC halt in AMD C1E");
675 pr_info("System has AMD C1E enabled\n");
676}
677
678static int __init idle_setup(char *str)
679{
680 if (!str)
681 return -EINVAL;
682
683 if (!strcmp(str, "poll")) {
684 pr_info("using polling idle threads\n");
685 boot_option_idle_override = IDLE_POLL;
686 cpu_idle_poll_ctrl(true);
687 } else if (!strcmp(str, "halt")) {
688 /*
689 * When the boot option of idle=halt is added, halt is
690 * forced to be used for CPU idle. In such case CPU C2/C3
691 * won't be used again.
692 * To continue to load the CPU idle driver, don't touch
693 * the boot_option_idle_override.
694 */
695 x86_idle = default_idle;
696 boot_option_idle_override = IDLE_HALT;
697 } else if (!strcmp(str, "nomwait")) {
698 /*
699 * If the boot option of "idle=nomwait" is added,
700 * it means that mwait will be disabled for CPU C2/C3
701 * states. In such case it won't touch the variable
702 * of boot_option_idle_override.
703 */
704 boot_option_idle_override = IDLE_NOMWAIT;
705 } else
706 return -1;
707
708 return 0;
709}
710early_param("idle", idle_setup);
711
712unsigned long arch_align_stack(unsigned long sp)
713{
714 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
715 sp -= get_random_int() % 8192;
716 return sp & ~0xf;
717}
718
719unsigned long arch_randomize_brk(struct mm_struct *mm)
720{
721 return randomize_page(mm->brk, 0x02000000);
722}
723
724/*
725 * Called from fs/proc with a reference on @p to find the function
726 * which called into schedule(). This needs to be done carefully
727 * because the task might wake up and we might look at a stack
728 * changing under us.
729 */
730unsigned long get_wchan(struct task_struct *p)
731{
732 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
733 int count = 0;
734
735 if (!p || p == current || p->state == TASK_RUNNING)
736 return 0;
737
738 if (!try_get_task_stack(p))
739 return 0;
740
741 start = (unsigned long)task_stack_page(p);
742 if (!start)
743 goto out;
744
745 /*
746 * Layout of the stack page:
747 *
748 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
749 * PADDING
750 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
751 * stack
752 * ----------- bottom = start
753 *
754 * The tasks stack pointer points at the location where the
755 * framepointer is stored. The data on the stack is:
756 * ... IP FP ... IP FP
757 *
758 * We need to read FP and IP, so we need to adjust the upper
759 * bound by another unsigned long.
760 */
761 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
762 top -= 2 * sizeof(unsigned long);
763 bottom = start;
764
765 sp = READ_ONCE(p->thread.sp);
766 if (sp < bottom || sp > top)
767 goto out;
768
769 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
770 do {
771 if (fp < bottom || fp > top)
772 goto out;
773 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
774 if (!in_sched_functions(ip)) {
775 ret = ip;
776 goto out;
777 }
778 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
779 } while (count++ < 16 && p->state != TASK_RUNNING);
780
781out:
782 put_task_stack(p);
783 return ret;
784}
785
786long do_arch_prctl_common(struct task_struct *task, int option,
787 unsigned long cpuid_enabled)
788{
789 switch (option) {
790 case ARCH_GET_CPUID:
791 return get_cpuid_mode();
792 case ARCH_SET_CPUID:
793 return set_cpuid_mode(task, cpuid_enabled);
794 }
795
796 return -EINVAL;
797}
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/errno.h>
4#include <linux/kernel.h>
5#include <linux/mm.h>
6#include <linux/smp.h>
7#include <linux/prctl.h>
8#include <linux/slab.h>
9#include <linux/sched.h>
10#include <linux/module.h>
11#include <linux/pm.h>
12#include <linux/tick.h>
13#include <linux/random.h>
14#include <linux/user-return-notifier.h>
15#include <linux/dmi.h>
16#include <linux/utsname.h>
17#include <linux/stackprotector.h>
18#include <linux/tick.h>
19#include <linux/cpuidle.h>
20#include <trace/events/power.h>
21#include <linux/hw_breakpoint.h>
22#include <asm/cpu.h>
23#include <asm/apic.h>
24#include <asm/syscalls.h>
25#include <asm/idle.h>
26#include <asm/uaccess.h>
27#include <asm/mwait.h>
28#include <asm/fpu/internal.h>
29#include <asm/debugreg.h>
30#include <asm/nmi.h>
31#include <asm/tlbflush.h>
32#include <asm/mce.h>
33#include <asm/vm86.h>
34
35/*
36 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
37 * no more per-task TSS's. The TSS size is kept cacheline-aligned
38 * so they are allowed to end up in the .data..cacheline_aligned
39 * section. Since TSS's are completely CPU-local, we want them
40 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
41 */
42__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
43 .x86_tss = {
44 .sp0 = TOP_OF_INIT_STACK,
45#ifdef CONFIG_X86_32
46 .ss0 = __KERNEL_DS,
47 .ss1 = __KERNEL_CS,
48 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
49#endif
50 },
51#ifdef CONFIG_X86_32
52 /*
53 * Note that the .io_bitmap member must be extra-big. This is because
54 * the CPU will access an additional byte beyond the end of the IO
55 * permission bitmap. The extra byte must be all 1 bits, and must
56 * be within the limit.
57 */
58 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
59#endif
60#ifdef CONFIG_X86_32
61 .SYSENTER_stack_canary = STACK_END_MAGIC,
62#endif
63};
64EXPORT_PER_CPU_SYMBOL(cpu_tss);
65
66#ifdef CONFIG_X86_64
67static DEFINE_PER_CPU(unsigned char, is_idle);
68static ATOMIC_NOTIFIER_HEAD(idle_notifier);
69
70void idle_notifier_register(struct notifier_block *n)
71{
72 atomic_notifier_chain_register(&idle_notifier, n);
73}
74EXPORT_SYMBOL_GPL(idle_notifier_register);
75
76void idle_notifier_unregister(struct notifier_block *n)
77{
78 atomic_notifier_chain_unregister(&idle_notifier, n);
79}
80EXPORT_SYMBOL_GPL(idle_notifier_unregister);
81#endif
82
83/*
84 * this gets called so that we can store lazy state into memory and copy the
85 * current task into the new thread.
86 */
87int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
88{
89 memcpy(dst, src, arch_task_struct_size);
90#ifdef CONFIG_VM86
91 dst->thread.vm86 = NULL;
92#endif
93
94 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
95}
96
97/*
98 * Free current thread data structures etc..
99 */
100void exit_thread(void)
101{
102 struct task_struct *me = current;
103 struct thread_struct *t = &me->thread;
104 unsigned long *bp = t->io_bitmap_ptr;
105 struct fpu *fpu = &t->fpu;
106
107 if (bp) {
108 struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
109
110 t->io_bitmap_ptr = NULL;
111 clear_thread_flag(TIF_IO_BITMAP);
112 /*
113 * Careful, clear this in the TSS too:
114 */
115 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
116 t->io_bitmap_max = 0;
117 put_cpu();
118 kfree(bp);
119 }
120
121 free_vm86(t);
122
123 fpu__drop(fpu);
124}
125
126void flush_thread(void)
127{
128 struct task_struct *tsk = current;
129
130 flush_ptrace_hw_breakpoint(tsk);
131 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
132
133 fpu__clear(&tsk->thread.fpu);
134}
135
136static void hard_disable_TSC(void)
137{
138 cr4_set_bits(X86_CR4_TSD);
139}
140
141void disable_TSC(void)
142{
143 preempt_disable();
144 if (!test_and_set_thread_flag(TIF_NOTSC))
145 /*
146 * Must flip the CPU state synchronously with
147 * TIF_NOTSC in the current running context.
148 */
149 hard_disable_TSC();
150 preempt_enable();
151}
152
153static void hard_enable_TSC(void)
154{
155 cr4_clear_bits(X86_CR4_TSD);
156}
157
158static void enable_TSC(void)
159{
160 preempt_disable();
161 if (test_and_clear_thread_flag(TIF_NOTSC))
162 /*
163 * Must flip the CPU state synchronously with
164 * TIF_NOTSC in the current running context.
165 */
166 hard_enable_TSC();
167 preempt_enable();
168}
169
170int get_tsc_mode(unsigned long adr)
171{
172 unsigned int val;
173
174 if (test_thread_flag(TIF_NOTSC))
175 val = PR_TSC_SIGSEGV;
176 else
177 val = PR_TSC_ENABLE;
178
179 return put_user(val, (unsigned int __user *)adr);
180}
181
182int set_tsc_mode(unsigned int val)
183{
184 if (val == PR_TSC_SIGSEGV)
185 disable_TSC();
186 else if (val == PR_TSC_ENABLE)
187 enable_TSC();
188 else
189 return -EINVAL;
190
191 return 0;
192}
193
194void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
195 struct tss_struct *tss)
196{
197 struct thread_struct *prev, *next;
198
199 prev = &prev_p->thread;
200 next = &next_p->thread;
201
202 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
203 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
204 unsigned long debugctl = get_debugctlmsr();
205
206 debugctl &= ~DEBUGCTLMSR_BTF;
207 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
208 debugctl |= DEBUGCTLMSR_BTF;
209
210 update_debugctlmsr(debugctl);
211 }
212
213 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
214 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
215 /* prev and next are different */
216 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
217 hard_disable_TSC();
218 else
219 hard_enable_TSC();
220 }
221
222 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
223 /*
224 * Copy the relevant range of the IO bitmap.
225 * Normally this is 128 bytes or less:
226 */
227 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
228 max(prev->io_bitmap_max, next->io_bitmap_max));
229 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
230 /*
231 * Clear any possible leftover bits:
232 */
233 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
234 }
235 propagate_user_return_notify(prev_p, next_p);
236}
237
238/*
239 * Idle related variables and functions
240 */
241unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
242EXPORT_SYMBOL(boot_option_idle_override);
243
244static void (*x86_idle)(void);
245
246#ifndef CONFIG_SMP
247static inline void play_dead(void)
248{
249 BUG();
250}
251#endif
252
253#ifdef CONFIG_X86_64
254void enter_idle(void)
255{
256 this_cpu_write(is_idle, 1);
257 atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
258}
259
260static void __exit_idle(void)
261{
262 if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
263 return;
264 atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
265}
266
267/* Called from interrupts to signify idle end */
268void exit_idle(void)
269{
270 /* idle loop has pid 0 */
271 if (current->pid)
272 return;
273 __exit_idle();
274}
275#endif
276
277void arch_cpu_idle_enter(void)
278{
279 local_touch_nmi();
280 enter_idle();
281}
282
283void arch_cpu_idle_exit(void)
284{
285 __exit_idle();
286}
287
288void arch_cpu_idle_dead(void)
289{
290 play_dead();
291}
292
293/*
294 * Called from the generic idle code.
295 */
296void arch_cpu_idle(void)
297{
298 x86_idle();
299}
300
301/*
302 * We use this if we don't have any better idle routine..
303 */
304void default_idle(void)
305{
306 trace_cpu_idle_rcuidle(1, smp_processor_id());
307 safe_halt();
308 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
309}
310#ifdef CONFIG_APM_MODULE
311EXPORT_SYMBOL(default_idle);
312#endif
313
314#ifdef CONFIG_XEN
315bool xen_set_default_idle(void)
316{
317 bool ret = !!x86_idle;
318
319 x86_idle = default_idle;
320
321 return ret;
322}
323#endif
324void stop_this_cpu(void *dummy)
325{
326 local_irq_disable();
327 /*
328 * Remove this CPU:
329 */
330 set_cpu_online(smp_processor_id(), false);
331 disable_local_APIC();
332 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
333
334 for (;;)
335 halt();
336}
337
338bool amd_e400_c1e_detected;
339EXPORT_SYMBOL(amd_e400_c1e_detected);
340
341static cpumask_var_t amd_e400_c1e_mask;
342
343void amd_e400_remove_cpu(int cpu)
344{
345 if (amd_e400_c1e_mask != NULL)
346 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
347}
348
349/*
350 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
351 * pending message MSR. If we detect C1E, then we handle it the same
352 * way as C3 power states (local apic timer and TSC stop)
353 */
354static void amd_e400_idle(void)
355{
356 if (!amd_e400_c1e_detected) {
357 u32 lo, hi;
358
359 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
360
361 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
362 amd_e400_c1e_detected = true;
363 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
364 mark_tsc_unstable("TSC halt in AMD C1E");
365 pr_info("System has AMD C1E enabled\n");
366 }
367 }
368
369 if (amd_e400_c1e_detected) {
370 int cpu = smp_processor_id();
371
372 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
373 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
374 /* Force broadcast so ACPI can not interfere. */
375 tick_broadcast_force();
376 pr_info("Switch to broadcast mode on CPU%d\n", cpu);
377 }
378 tick_broadcast_enter();
379
380 default_idle();
381
382 /*
383 * The switch back from broadcast mode needs to be
384 * called with interrupts disabled.
385 */
386 local_irq_disable();
387 tick_broadcast_exit();
388 local_irq_enable();
389 } else
390 default_idle();
391}
392
393/*
394 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
395 * We can't rely on cpuidle installing MWAIT, because it will not load
396 * on systems that support only C1 -- so the boot default must be MWAIT.
397 *
398 * Some AMD machines are the opposite, they depend on using HALT.
399 *
400 * So for default C1, which is used during boot until cpuidle loads,
401 * use MWAIT-C1 on Intel HW that has it, else use HALT.
402 */
403static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
404{
405 if (c->x86_vendor != X86_VENDOR_INTEL)
406 return 0;
407
408 if (!cpu_has(c, X86_FEATURE_MWAIT))
409 return 0;
410
411 return 1;
412}
413
414/*
415 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
416 * with interrupts enabled and no flags, which is backwards compatible with the
417 * original MWAIT implementation.
418 */
419static void mwait_idle(void)
420{
421 if (!current_set_polling_and_test()) {
422 trace_cpu_idle_rcuidle(1, smp_processor_id());
423 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
424 mb(); /* quirk */
425 clflush((void *)¤t_thread_info()->flags);
426 mb(); /* quirk */
427 }
428
429 __monitor((void *)¤t_thread_info()->flags, 0, 0);
430 if (!need_resched())
431 __sti_mwait(0, 0);
432 else
433 local_irq_enable();
434 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
435 } else {
436 local_irq_enable();
437 }
438 __current_clr_polling();
439}
440
441void select_idle_routine(const struct cpuinfo_x86 *c)
442{
443#ifdef CONFIG_SMP
444 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
445 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
446#endif
447 if (x86_idle || boot_option_idle_override == IDLE_POLL)
448 return;
449
450 if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
451 /* E400: APIC timer interrupt does not wake up CPU from C1e */
452 pr_info("using AMD E400 aware idle routine\n");
453 x86_idle = amd_e400_idle;
454 } else if (prefer_mwait_c1_over_halt(c)) {
455 pr_info("using mwait in idle threads\n");
456 x86_idle = mwait_idle;
457 } else
458 x86_idle = default_idle;
459}
460
461void __init init_amd_e400_c1e_mask(void)
462{
463 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
464 if (x86_idle == amd_e400_idle)
465 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
466}
467
468static int __init idle_setup(char *str)
469{
470 if (!str)
471 return -EINVAL;
472
473 if (!strcmp(str, "poll")) {
474 pr_info("using polling idle threads\n");
475 boot_option_idle_override = IDLE_POLL;
476 cpu_idle_poll_ctrl(true);
477 } else if (!strcmp(str, "halt")) {
478 /*
479 * When the boot option of idle=halt is added, halt is
480 * forced to be used for CPU idle. In such case CPU C2/C3
481 * won't be used again.
482 * To continue to load the CPU idle driver, don't touch
483 * the boot_option_idle_override.
484 */
485 x86_idle = default_idle;
486 boot_option_idle_override = IDLE_HALT;
487 } else if (!strcmp(str, "nomwait")) {
488 /*
489 * If the boot option of "idle=nomwait" is added,
490 * it means that mwait will be disabled for CPU C2/C3
491 * states. In such case it won't touch the variable
492 * of boot_option_idle_override.
493 */
494 boot_option_idle_override = IDLE_NOMWAIT;
495 } else
496 return -1;
497
498 return 0;
499}
500early_param("idle", idle_setup);
501
502unsigned long arch_align_stack(unsigned long sp)
503{
504 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
505 sp -= get_random_int() % 8192;
506 return sp & ~0xf;
507}
508
509unsigned long arch_randomize_brk(struct mm_struct *mm)
510{
511 unsigned long range_end = mm->brk + 0x02000000;
512 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
513}
514
515/*
516 * Called from fs/proc with a reference on @p to find the function
517 * which called into schedule(). This needs to be done carefully
518 * because the task might wake up and we might look at a stack
519 * changing under us.
520 */
521unsigned long get_wchan(struct task_struct *p)
522{
523 unsigned long start, bottom, top, sp, fp, ip;
524 int count = 0;
525
526 if (!p || p == current || p->state == TASK_RUNNING)
527 return 0;
528
529 start = (unsigned long)task_stack_page(p);
530 if (!start)
531 return 0;
532
533 /*
534 * Layout of the stack page:
535 *
536 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
537 * PADDING
538 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
539 * stack
540 * ----------- bottom = start + sizeof(thread_info)
541 * thread_info
542 * ----------- start
543 *
544 * The tasks stack pointer points at the location where the
545 * framepointer is stored. The data on the stack is:
546 * ... IP FP ... IP FP
547 *
548 * We need to read FP and IP, so we need to adjust the upper
549 * bound by another unsigned long.
550 */
551 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
552 top -= 2 * sizeof(unsigned long);
553 bottom = start + sizeof(struct thread_info);
554
555 sp = READ_ONCE(p->thread.sp);
556 if (sp < bottom || sp > top)
557 return 0;
558
559 fp = READ_ONCE_NOCHECK(*(unsigned long *)sp);
560 do {
561 if (fp < bottom || fp > top)
562 return 0;
563 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
564 if (!in_sched_functions(ip))
565 return ip;
566 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
567 } while (count++ < 16 && p->state != TASK_RUNNING);
568 return 0;
569}