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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SAMSUNG EXYNOS5250 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
9 * EXYNOS5250 based board files can include this file and provide
10 * values for board specfic bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
14 * additional nodes can be added to this file.
15 */
16
17#include <dt-bindings/clock/exynos5250.h>
18#include "exynos5.dtsi"
19#include "exynos4-cpu-thermal.dtsi"
20#include <dt-bindings/clock/exynos-audss-clk.h>
21
22/ {
23 compatible = "samsung,exynos5250", "samsung,exynos5";
24
25 aliases {
26 spi0 = &spi_0;
27 spi1 = &spi_1;
28 spi2 = &spi_2;
29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3;
33 mshc0 = &mmc_0;
34 mshc1 = &mmc_1;
35 mshc2 = &mmc_2;
36 mshc3 = &mmc_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 i2c9 = &i2c_9;
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a15";
56 reg = <0>;
57 clock-frequency = <1700000000>;
58 clocks = <&clock CLK_ARM_CLK>;
59 clock-names = "cpu";
60 clock-latency = <140000>;
61
62 operating-points = <
63 1700000 1300000
64 1600000 1250000
65 1500000 1225000
66 1400000 1200000
67 1300000 1150000
68 1200000 1125000
69 1100000 1100000
70 1000000 1075000
71 900000 1050000
72 800000 1025000
73 700000 1012500
74 600000 1000000
75 500000 975000
76 400000 950000
77 300000 937500
78 200000 925000
79 >;
80 #cooling-cells = <2>; /* min followed by max */
81 };
82 cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <1>;
86 clock-frequency = <1700000000>;
87 };
88 };
89
90 soc: soc {
91 sysram@2020000 {
92 compatible = "mmio-sram";
93 reg = <0x02020000 0x30000>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges = <0 0x02020000 0x30000>;
97
98 smp-sysram@0 {
99 compatible = "samsung,exynos4210-sysram";
100 reg = <0x0 0x1000>;
101 };
102
103 smp-sysram@2f000 {
104 compatible = "samsung,exynos4210-sysram-ns";
105 reg = <0x2f000 0x1000>;
106 };
107 };
108
109 pd_gsc: power-domain@10044000 {
110 compatible = "samsung,exynos4210-pd";
111 reg = <0x10044000 0x20>;
112 #power-domain-cells = <0>;
113 label = "GSC";
114 };
115
116 pd_mfc: power-domain@10044040 {
117 compatible = "samsung,exynos4210-pd";
118 reg = <0x10044040 0x20>;
119 #power-domain-cells = <0>;
120 label = "MFC";
121 };
122
123 pd_g3d: power-domain@10044060 {
124 compatible = "samsung,exynos4210-pd";
125 reg = <0x10044060 0x20>;
126 #power-domain-cells = <0>;
127 label = "G3D";
128 };
129
130 pd_disp1: power-domain@100440a0 {
131 compatible = "samsung,exynos4210-pd";
132 reg = <0x100440A0 0x20>;
133 #power-domain-cells = <0>;
134 label = "DISP1";
135 clocks = <&clock CLK_FIN_PLL>,
136 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
137 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
138 clock-names = "oscclk", "clk0", "clk1";
139 };
140
141 pd_mau: power-domain@100440c0 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x100440C0 0x20>;
144 #power-domain-cells = <0>;
145 label = "MAU";
146 };
147
148 clock: clock-controller@10010000 {
149 compatible = "samsung,exynos5250-clock";
150 reg = <0x10010000 0x30000>;
151 #clock-cells = <1>;
152 };
153
154 clock_audss: audss-clock-controller@3810000 {
155 compatible = "samsung,exynos5250-audss-clock";
156 reg = <0x03810000 0x0C>;
157 #clock-cells = <1>;
158 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
159 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
160 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
161 power-domains = <&pd_mau>;
162 };
163
164 timer {
165 compatible = "arm,armv7-timer";
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
170 /*
171 * Unfortunately we need this since some versions
172 * of U-Boot on Exynos don't set the CNTFRQ register,
173 * so we need the value from DT.
174 */
175 clock-frequency = <24000000>;
176 };
177
178 mct@101c0000 {
179 compatible = "samsung,exynos4210-mct";
180 reg = <0x101C0000 0x800>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
183 interrupt-parent = <&mct_map>;
184 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
185 <4 0>, <5 0>;
186 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
187 clock-names = "fin_pll", "mct";
188
189 mct_map: mct-map {
190 #interrupt-cells = <2>;
191 #address-cells = <0>;
192 #size-cells = <0>;
193 interrupt-map = <0x0 0 &combiner 23 3>,
194 <0x1 0 &combiner 23 4>,
195 <0x2 0 &combiner 25 2>,
196 <0x3 0 &combiner 25 3>,
197 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
198 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
199 };
200 };
201
202 pmu {
203 compatible = "arm,cortex-a15-pmu";
204 interrupt-parent = <&combiner>;
205 interrupts = <1 2>, <22 4>;
206 };
207
208 pinctrl_0: pinctrl@11400000 {
209 compatible = "samsung,exynos5250-pinctrl";
210 reg = <0x11400000 0x1000>;
211 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
212
213 wakup_eint: wakeup-interrupt-controller {
214 compatible = "samsung,exynos4210-wakeup-eint";
215 interrupt-parent = <&gic>;
216 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
217 };
218 };
219
220 pinctrl_1: pinctrl@13400000 {
221 compatible = "samsung,exynos5250-pinctrl";
222 reg = <0x13400000 0x1000>;
223 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
224 };
225
226 pinctrl_2: pinctrl@10d10000 {
227 compatible = "samsung,exynos5250-pinctrl";
228 reg = <0x10d10000 0x1000>;
229 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
230 };
231
232 pinctrl_3: pinctrl@3860000 {
233 compatible = "samsung,exynos5250-pinctrl";
234 reg = <0x03860000 0x1000>;
235 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
236 power-domains = <&pd_mau>;
237 };
238
239 pmu_system_controller: system-controller@10040000 {
240 compatible = "samsung,exynos5250-pmu", "syscon";
241 reg = <0x10040000 0x5000>;
242 clock-names = "clkout16";
243 clocks = <&clock CLK_FIN_PLL>;
244 #clock-cells = <1>;
245 interrupt-controller;
246 #interrupt-cells = <3>;
247 interrupt-parent = <&gic>;
248 };
249
250 watchdog@101d0000 {
251 compatible = "samsung,exynos5250-wdt";
252 reg = <0x101D0000 0x100>;
253 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clock CLK_WDT>;
255 clock-names = "watchdog";
256 samsung,syscon-phandle = <&pmu_system_controller>;
257 };
258
259 mfc: codec@11000000 {
260 compatible = "samsung,mfc-v6";
261 reg = <0x11000000 0x10000>;
262 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
263 power-domains = <&pd_mfc>;
264 clocks = <&clock CLK_MFC>;
265 clock-names = "mfc";
266 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
267 iommu-names = "left", "right";
268 };
269
270 rotator: rotator@11c00000 {
271 compatible = "samsung,exynos5250-rotator";
272 reg = <0x11C00000 0x64>;
273 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clock CLK_ROTATOR>;
275 clock-names = "rotator";
276 iommus = <&sysmmu_rotator>;
277 };
278
279 tmu: tmu@10060000 {
280 compatible = "samsung,exynos5250-tmu";
281 reg = <0x10060000 0x100>;
282 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clock CLK_TMU>;
284 clock-names = "tmu_apbif";
285 #include "exynos4412-tmu-sensor-conf.dtsi"
286 };
287
288 sata: sata@122f0000 {
289 compatible = "snps,dwc-ahci";
290 samsung,sata-freq = <66>;
291 reg = <0x122F0000 0x1ff>;
292 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
294 clock-names = "sata", "sclk_sata";
295 phys = <&sata_phy>;
296 phy-names = "sata-phy";
297 status = "disabled";
298 };
299
300 sata_phy: sata-phy@12170000 {
301 compatible = "samsung,exynos5250-sata-phy";
302 reg = <0x12170000 0x1ff>;
303 clocks = <&clock CLK_SATA_PHYCTRL>;
304 clock-names = "sata_phyctrl";
305 #phy-cells = <0>;
306 samsung,syscon-phandle = <&pmu_system_controller>;
307 status = "disabled";
308 };
309
310 /* i2c_0-3 are defined in exynos5.dtsi */
311 i2c_4: i2c@12ca0000 {
312 compatible = "samsung,s3c2440-i2c";
313 reg = <0x12CA0000 0x100>;
314 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 clocks = <&clock CLK_I2C4>;
318 clock-names = "i2c";
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c4_bus>;
321 status = "disabled";
322 };
323
324 i2c_5: i2c@12cb0000 {
325 compatible = "samsung,s3c2440-i2c";
326 reg = <0x12CB0000 0x100>;
327 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
328 #address-cells = <1>;
329 #size-cells = <0>;
330 clocks = <&clock CLK_I2C5>;
331 clock-names = "i2c";
332 pinctrl-names = "default";
333 pinctrl-0 = <&i2c5_bus>;
334 status = "disabled";
335 };
336
337 i2c_6: i2c@12cc0000 {
338 compatible = "samsung,s3c2440-i2c";
339 reg = <0x12CC0000 0x100>;
340 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 clocks = <&clock CLK_I2C6>;
344 clock-names = "i2c";
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c6_bus>;
347 status = "disabled";
348 };
349
350 i2c_7: i2c@12cd0000 {
351 compatible = "samsung,s3c2440-i2c";
352 reg = <0x12CD0000 0x100>;
353 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 clocks = <&clock CLK_I2C7>;
357 clock-names = "i2c";
358 pinctrl-names = "default";
359 pinctrl-0 = <&i2c7_bus>;
360 status = "disabled";
361 };
362
363 i2c_8: i2c@12ce0000 {
364 compatible = "samsung,s3c2440-hdmiphy-i2c";
365 reg = <0x12CE0000 0x1000>;
366 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 clocks = <&clock CLK_I2C_HDMI>;
370 clock-names = "i2c";
371 status = "disabled";
372
373 hdmiphy: hdmiphy@38 {
374 compatible = "samsung,exynos4212-hdmiphy";
375 reg = <0x38>;
376 };
377 };
378
379 i2c_9: i2c@121d0000 {
380 compatible = "samsung,exynos5-sata-phy-i2c";
381 reg = <0x121D0000 0x100>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 clocks = <&clock CLK_SATA_PHYI2C>;
385 clock-names = "i2c";
386 status = "disabled";
387 };
388
389 spi_0: spi@12d20000 {
390 compatible = "samsung,exynos4210-spi";
391 status = "disabled";
392 reg = <0x12d20000 0x100>;
393 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
394 dmas = <&pdma0 5
395 &pdma0 4>;
396 dma-names = "tx", "rx";
397 #address-cells = <1>;
398 #size-cells = <0>;
399 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
400 clock-names = "spi", "spi_busclk0";
401 pinctrl-names = "default";
402 pinctrl-0 = <&spi0_bus>;
403 };
404
405 spi_1: spi@12d30000 {
406 compatible = "samsung,exynos4210-spi";
407 status = "disabled";
408 reg = <0x12d30000 0x100>;
409 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
410 dmas = <&pdma1 5
411 &pdma1 4>;
412 dma-names = "tx", "rx";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
416 clock-names = "spi", "spi_busclk0";
417 pinctrl-names = "default";
418 pinctrl-0 = <&spi1_bus>;
419 };
420
421 spi_2: spi@12d40000 {
422 compatible = "samsung,exynos4210-spi";
423 status = "disabled";
424 reg = <0x12d40000 0x100>;
425 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
426 dmas = <&pdma0 7
427 &pdma0 6>;
428 dma-names = "tx", "rx";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
432 clock-names = "spi", "spi_busclk0";
433 pinctrl-names = "default";
434 pinctrl-0 = <&spi2_bus>;
435 };
436
437 mmc_0: mmc@12200000 {
438 compatible = "samsung,exynos5250-dw-mshc";
439 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>;
441 #size-cells = <0>;
442 reg = <0x12200000 0x1000>;
443 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
444 clock-names = "biu", "ciu";
445 fifo-depth = <0x80>;
446 status = "disabled";
447 };
448
449 mmc_1: mmc@12210000 {
450 compatible = "samsung,exynos5250-dw-mshc";
451 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 reg = <0x12210000 0x1000>;
455 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
456 clock-names = "biu", "ciu";
457 fifo-depth = <0x80>;
458 status = "disabled";
459 };
460
461 mmc_2: mmc@12220000 {
462 compatible = "samsung,exynos5250-dw-mshc";
463 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 reg = <0x12220000 0x1000>;
467 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
468 clock-names = "biu", "ciu";
469 fifo-depth = <0x80>;
470 status = "disabled";
471 };
472
473 mmc_3: mmc@12230000 {
474 compatible = "samsung,exynos5250-dw-mshc";
475 reg = <0x12230000 0x1000>;
476 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
480 clock-names = "biu", "ciu";
481 fifo-depth = <0x80>;
482 status = "disabled";
483 };
484
485 i2s0: i2s@3830000 {
486 compatible = "samsung,s5pv210-i2s";
487 status = "disabled";
488 reg = <0x03830000 0x100>;
489 dmas = <&pdma0 10
490 &pdma0 9
491 &pdma0 8>;
492 dma-names = "tx", "rx", "tx-sec";
493 clocks = <&clock_audss EXYNOS_I2S_BUS>,
494 <&clock_audss EXYNOS_I2S_BUS>,
495 <&clock_audss EXYNOS_SCLK_I2S>;
496 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
497 samsung,idma-addr = <0x03000000>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&i2s0_bus>;
500 power-domains = <&pd_mau>;
501 #clock-cells = <1>;
502 #sound-dai-cells = <1>;
503 };
504
505 i2s1: i2s@12d60000 {
506 compatible = "samsung,s3c6410-i2s";
507 status = "disabled";
508 reg = <0x12D60000 0x100>;
509 dmas = <&pdma1 12
510 &pdma1 11>;
511 dma-names = "tx", "rx";
512 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
513 clock-names = "iis", "i2s_opclk0";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2s1_bus>;
516 power-domains = <&pd_mau>;
517 #sound-dai-cells = <1>;
518 };
519
520 i2s2: i2s@12d70000 {
521 compatible = "samsung,s3c6410-i2s";
522 status = "disabled";
523 reg = <0x12D70000 0x100>;
524 dmas = <&pdma0 12
525 &pdma0 11>;
526 dma-names = "tx", "rx";
527 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
528 clock-names = "iis", "i2s_opclk0";
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2s2_bus>;
531 power-domains = <&pd_mau>;
532 #sound-dai-cells = <1>;
533 };
534
535 usb_dwc3 {
536 compatible = "samsung,exynos5250-dwusb3";
537 clocks = <&clock CLK_USB3>;
538 clock-names = "usbdrd30";
539 #address-cells = <1>;
540 #size-cells = <1>;
541 ranges;
542
543 usbdrd_dwc3: dwc3@12000000 {
544 compatible = "synopsys,dwc3";
545 reg = <0x12000000 0x10000>;
546 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
547 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
548 phy-names = "usb2-phy", "usb3-phy";
549 };
550 };
551
552 usbdrd_phy: phy@12100000 {
553 compatible = "samsung,exynos5250-usbdrd-phy";
554 reg = <0x12100000 0x100>;
555 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
556 clock-names = "phy", "ref";
557 samsung,pmu-syscon = <&pmu_system_controller>;
558 #phy-cells = <1>;
559 };
560
561 ehci: usb@12110000 {
562 compatible = "samsung,exynos4210-ehci";
563 reg = <0x12110000 0x100>;
564 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
565
566 clocks = <&clock CLK_USB2>;
567 clock-names = "usbhost";
568 #address-cells = <1>;
569 #size-cells = <0>;
570 port@0 {
571 reg = <0>;
572 phys = <&usb2_phy_gen 1>;
573 };
574 };
575
576 ohci: usb@12120000 {
577 compatible = "samsung,exynos4210-ohci";
578 reg = <0x12120000 0x100>;
579 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
580
581 clocks = <&clock CLK_USB2>;
582 clock-names = "usbhost";
583 #address-cells = <1>;
584 #size-cells = <0>;
585 port@0 {
586 reg = <0>;
587 phys = <&usb2_phy_gen 1>;
588 };
589 };
590
591 usb2_phy_gen: phy@12130000 {
592 compatible = "samsung,exynos5250-usb2-phy";
593 reg = <0x12130000 0x100>;
594 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
595 clock-names = "phy", "ref";
596 #phy-cells = <1>;
597 samsung,sysreg-phandle = <&sysreg_system_controller>;
598 samsung,pmureg-phandle = <&pmu_system_controller>;
599 };
600
601 amba {
602 #address-cells = <1>;
603 #size-cells = <1>;
604 compatible = "simple-bus";
605 interrupt-parent = <&gic>;
606 ranges;
607
608 pdma0: pdma@121a0000 {
609 compatible = "arm,pl330", "arm,primecell";
610 reg = <0x121A0000 0x1000>;
611 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clock CLK_PDMA0>;
613 clock-names = "apb_pclk";
614 #dma-cells = <1>;
615 #dma-channels = <8>;
616 #dma-requests = <32>;
617 };
618
619 pdma1: pdma@121b0000 {
620 compatible = "arm,pl330", "arm,primecell";
621 reg = <0x121B0000 0x1000>;
622 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clock CLK_PDMA1>;
624 clock-names = "apb_pclk";
625 #dma-cells = <1>;
626 #dma-channels = <8>;
627 #dma-requests = <32>;
628 };
629
630 mdma0: mdma@10800000 {
631 compatible = "arm,pl330", "arm,primecell";
632 reg = <0x10800000 0x1000>;
633 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&clock CLK_MDMA0>;
635 clock-names = "apb_pclk";
636 #dma-cells = <1>;
637 #dma-channels = <8>;
638 #dma-requests = <1>;
639 };
640
641 mdma1: mdma@11c10000 {
642 compatible = "arm,pl330", "arm,primecell";
643 reg = <0x11C10000 0x1000>;
644 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clock CLK_MDMA1>;
646 clock-names = "apb_pclk";
647 #dma-cells = <1>;
648 #dma-channels = <8>;
649 #dma-requests = <1>;
650 };
651 };
652
653 gsc_0: gsc@13e00000 {
654 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
655 reg = <0x13e00000 0x1000>;
656 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
657 power-domains = <&pd_gsc>;
658 clocks = <&clock CLK_GSCL0>;
659 clock-names = "gscl";
660 iommus = <&sysmmu_gsc0>;
661 };
662
663 gsc_1: gsc@13e10000 {
664 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
665 reg = <0x13e10000 0x1000>;
666 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
667 power-domains = <&pd_gsc>;
668 clocks = <&clock CLK_GSCL1>;
669 clock-names = "gscl";
670 iommus = <&sysmmu_gsc1>;
671 };
672
673 gsc_2: gsc@13e20000 {
674 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
675 reg = <0x13e20000 0x1000>;
676 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
677 power-domains = <&pd_gsc>;
678 clocks = <&clock CLK_GSCL2>;
679 clock-names = "gscl";
680 iommus = <&sysmmu_gsc2>;
681 };
682
683 gsc_3: gsc@13e30000 {
684 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
685 reg = <0x13e30000 0x1000>;
686 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
687 power-domains = <&pd_gsc>;
688 clocks = <&clock CLK_GSCL3>;
689 clock-names = "gscl";
690 iommus = <&sysmmu_gsc3>;
691 };
692
693 hdmi: hdmi@14530000 {
694 compatible = "samsung,exynos4212-hdmi";
695 reg = <0x14530000 0x70000>;
696 power-domains = <&pd_disp1>;
697 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
699 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
700 <&clock CLK_MOUT_HDMI>;
701 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
702 "sclk_hdmiphy", "mout_hdmi";
703 samsung,syscon-phandle = <&pmu_system_controller>;
704 phy = <&hdmiphy>;
705 #sound-dai-cells = <0>;
706 status = "disabled";
707 };
708
709 hdmicec: cec@101b0000 {
710 compatible = "samsung,s5p-cec";
711 reg = <0x101B0000 0x200>;
712 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clock CLK_HDMI_CEC>;
714 clock-names = "hdmicec";
715 samsung,syscon-phandle = <&pmu_system_controller>;
716 hdmi-phandle = <&hdmi>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&hdmi_cec>;
719 status = "disabled";
720 };
721
722 mixer: mixer@14450000 {
723 compatible = "samsung,exynos5250-mixer";
724 reg = <0x14450000 0x10000>;
725 power-domains = <&pd_disp1>;
726 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
728 <&clock CLK_SCLK_HDMI>;
729 clock-names = "mixer", "hdmi", "sclk_hdmi";
730 iommus = <&sysmmu_tv>;
731 status = "disabled";
732 };
733
734 dp_phy: video-phy {
735 compatible = "samsung,exynos5250-dp-video-phy";
736 samsung,pmu-syscon = <&pmu_system_controller>;
737 #phy-cells = <0>;
738 };
739
740 adc: adc@12d10000 {
741 compatible = "samsung,exynos-adc-v1";
742 reg = <0x12D10000 0x100>;
743 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clock CLK_ADC>;
745 clock-names = "adc";
746 #io-channel-cells = <1>;
747 io-channel-ranges;
748 samsung,syscon-phandle = <&pmu_system_controller>;
749 status = "disabled";
750 };
751
752 sysmmu_g2d: sysmmu@10a60000 {
753 compatible = "samsung,exynos-sysmmu";
754 reg = <0x10A60000 0x1000>;
755 interrupt-parent = <&combiner>;
756 interrupts = <24 5>;
757 clock-names = "sysmmu", "master";
758 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
759 #iommu-cells = <0>;
760 };
761
762 sysmmu_mfc_r: sysmmu@11200000 {
763 compatible = "samsung,exynos-sysmmu";
764 reg = <0x11200000 0x1000>;
765 interrupt-parent = <&combiner>;
766 interrupts = <6 2>;
767 power-domains = <&pd_mfc>;
768 clock-names = "sysmmu", "master";
769 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
770 #iommu-cells = <0>;
771 };
772
773 sysmmu_mfc_l: sysmmu@11210000 {
774 compatible = "samsung,exynos-sysmmu";
775 reg = <0x11210000 0x1000>;
776 interrupt-parent = <&combiner>;
777 interrupts = <8 5>;
778 power-domains = <&pd_mfc>;
779 clock-names = "sysmmu", "master";
780 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
781 #iommu-cells = <0>;
782 };
783
784 sysmmu_rotator: sysmmu@11d40000 {
785 compatible = "samsung,exynos-sysmmu";
786 reg = <0x11D40000 0x1000>;
787 interrupt-parent = <&combiner>;
788 interrupts = <4 0>;
789 clock-names = "sysmmu", "master";
790 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
791 #iommu-cells = <0>;
792 };
793
794 sysmmu_jpeg: sysmmu@11f20000 {
795 compatible = "samsung,exynos-sysmmu";
796 reg = <0x11F20000 0x1000>;
797 interrupt-parent = <&combiner>;
798 interrupts = <4 2>;
799 power-domains = <&pd_gsc>;
800 clock-names = "sysmmu", "master";
801 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
802 #iommu-cells = <0>;
803 };
804
805 sysmmu_fimc_isp: sysmmu@13260000 {
806 compatible = "samsung,exynos-sysmmu";
807 reg = <0x13260000 0x1000>;
808 interrupt-parent = <&combiner>;
809 interrupts = <10 6>;
810 clock-names = "sysmmu";
811 clocks = <&clock CLK_SMMU_FIMC_ISP>;
812 #iommu-cells = <0>;
813 };
814
815 sysmmu_fimc_drc: sysmmu@13270000 {
816 compatible = "samsung,exynos-sysmmu";
817 reg = <0x13270000 0x1000>;
818 interrupt-parent = <&combiner>;
819 interrupts = <11 6>;
820 clock-names = "sysmmu";
821 clocks = <&clock CLK_SMMU_FIMC_DRC>;
822 #iommu-cells = <0>;
823 };
824
825 sysmmu_fimc_fd: sysmmu@132a0000 {
826 compatible = "samsung,exynos-sysmmu";
827 reg = <0x132A0000 0x1000>;
828 interrupt-parent = <&combiner>;
829 interrupts = <5 0>;
830 clock-names = "sysmmu";
831 clocks = <&clock CLK_SMMU_FIMC_FD>;
832 #iommu-cells = <0>;
833 };
834
835 sysmmu_fimc_scc: sysmmu@13280000 {
836 compatible = "samsung,exynos-sysmmu";
837 reg = <0x13280000 0x1000>;
838 interrupt-parent = <&combiner>;
839 interrupts = <5 2>;
840 clock-names = "sysmmu";
841 clocks = <&clock CLK_SMMU_FIMC_SCC>;
842 #iommu-cells = <0>;
843 };
844
845 sysmmu_fimc_scp: sysmmu@13290000 {
846 compatible = "samsung,exynos-sysmmu";
847 reg = <0x13290000 0x1000>;
848 interrupt-parent = <&combiner>;
849 interrupts = <3 6>;
850 clock-names = "sysmmu";
851 clocks = <&clock CLK_SMMU_FIMC_SCP>;
852 #iommu-cells = <0>;
853 };
854
855 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
856 compatible = "samsung,exynos-sysmmu";
857 reg = <0x132B0000 0x1000>;
858 interrupt-parent = <&combiner>;
859 interrupts = <5 4>;
860 clock-names = "sysmmu";
861 clocks = <&clock CLK_SMMU_FIMC_MCU>;
862 #iommu-cells = <0>;
863 };
864
865 sysmmu_fimc_odc: sysmmu@132c0000 {
866 compatible = "samsung,exynos-sysmmu";
867 reg = <0x132C0000 0x1000>;
868 interrupt-parent = <&combiner>;
869 interrupts = <11 0>;
870 clock-names = "sysmmu";
871 clocks = <&clock CLK_SMMU_FIMC_ODC>;
872 #iommu-cells = <0>;
873 };
874
875 sysmmu_fimc_dis0: sysmmu@132d0000 {
876 compatible = "samsung,exynos-sysmmu";
877 reg = <0x132D0000 0x1000>;
878 interrupt-parent = <&combiner>;
879 interrupts = <10 4>;
880 clock-names = "sysmmu";
881 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
882 #iommu-cells = <0>;
883 };
884
885 sysmmu_fimc_dis1: sysmmu@132E0000{
886 compatible = "samsung,exynos-sysmmu";
887 reg = <0x132E0000 0x1000>;
888 interrupt-parent = <&combiner>;
889 interrupts = <9 4>;
890 clock-names = "sysmmu";
891 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
892 #iommu-cells = <0>;
893 };
894
895 sysmmu_fimc_3dnr: sysmmu@132f0000 {
896 compatible = "samsung,exynos-sysmmu";
897 reg = <0x132F0000 0x1000>;
898 interrupt-parent = <&combiner>;
899 interrupts = <5 6>;
900 clock-names = "sysmmu";
901 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
902 #iommu-cells = <0>;
903 };
904
905 sysmmu_fimc_lite0: sysmmu@13c40000 {
906 compatible = "samsung,exynos-sysmmu";
907 reg = <0x13C40000 0x1000>;
908 interrupt-parent = <&combiner>;
909 interrupts = <3 4>;
910 power-domains = <&pd_gsc>;
911 clock-names = "sysmmu", "master";
912 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
913 #iommu-cells = <0>;
914 };
915
916 sysmmu_fimc_lite1: sysmmu@13c50000 {
917 compatible = "samsung,exynos-sysmmu";
918 reg = <0x13C50000 0x1000>;
919 interrupt-parent = <&combiner>;
920 interrupts = <24 1>;
921 power-domains = <&pd_gsc>;
922 clock-names = "sysmmu", "master";
923 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
924 #iommu-cells = <0>;
925 };
926
927 sysmmu_gsc0: sysmmu@13e80000 {
928 compatible = "samsung,exynos-sysmmu";
929 reg = <0x13E80000 0x1000>;
930 interrupt-parent = <&combiner>;
931 interrupts = <2 0>;
932 power-domains = <&pd_gsc>;
933 clock-names = "sysmmu", "master";
934 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
935 #iommu-cells = <0>;
936 };
937
938 sysmmu_gsc1: sysmmu@13e90000 {
939 compatible = "samsung,exynos-sysmmu";
940 reg = <0x13E90000 0x1000>;
941 interrupt-parent = <&combiner>;
942 interrupts = <2 2>;
943 power-domains = <&pd_gsc>;
944 clock-names = "sysmmu", "master";
945 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
946 #iommu-cells = <0>;
947 };
948
949 sysmmu_gsc2: sysmmu@13ea0000 {
950 compatible = "samsung,exynos-sysmmu";
951 reg = <0x13EA0000 0x1000>;
952 interrupt-parent = <&combiner>;
953 interrupts = <2 4>;
954 power-domains = <&pd_gsc>;
955 clock-names = "sysmmu", "master";
956 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
957 #iommu-cells = <0>;
958 };
959
960 sysmmu_gsc3: sysmmu@13eb0000 {
961 compatible = "samsung,exynos-sysmmu";
962 reg = <0x13EB0000 0x1000>;
963 interrupt-parent = <&combiner>;
964 interrupts = <2 6>;
965 power-domains = <&pd_gsc>;
966 clock-names = "sysmmu", "master";
967 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
968 #iommu-cells = <0>;
969 };
970
971 sysmmu_fimd1: sysmmu@14640000 {
972 compatible = "samsung,exynos-sysmmu";
973 reg = <0x14640000 0x1000>;
974 interrupt-parent = <&combiner>;
975 interrupts = <3 2>;
976 power-domains = <&pd_disp1>;
977 clock-names = "sysmmu", "master";
978 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
979 #iommu-cells = <0>;
980 };
981
982 sysmmu_tv: sysmmu@14650000 {
983 compatible = "samsung,exynos-sysmmu";
984 reg = <0x14650000 0x1000>;
985 interrupt-parent = <&combiner>;
986 interrupts = <7 4>;
987 power-domains = <&pd_disp1>;
988 clock-names = "sysmmu", "master";
989 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
990 #iommu-cells = <0>;
991 };
992 };
993
994 thermal-zones {
995 cpu_thermal: cpu-thermal {
996 polling-delay-passive = <0>;
997 polling-delay = <0>;
998 thermal-sensors = <&tmu 0>;
999
1000 cooling-maps {
1001 map0 {
1002 /* Corresponds to 800MHz at freq_table */
1003 cooling-device = <&cpu0 9 9>;
1004 };
1005 map1 {
1006 /* Corresponds to 200MHz at freq_table */
1007 cooling-device = <&cpu0 15 15>;
1008 };
1009 };
1010 };
1011 };
1012};
1013
1014&dp {
1015 power-domains = <&pd_disp1>;
1016 clocks = <&clock CLK_DP>;
1017 clock-names = "dp";
1018 phys = <&dp_phy>;
1019 phy-names = "dp";
1020};
1021
1022&fimd {
1023 power-domains = <&pd_disp1>;
1024 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1025 clock-names = "sclk_fimd", "fimd";
1026 iommus = <&sysmmu_fimd1>;
1027};
1028
1029&g2d {
1030 iommus = <&sysmmu_g2d>;
1031 clocks = <&clock CLK_G2D>;
1032 clock-names = "fimg2d";
1033 status = "okay";
1034};
1035
1036&i2c_0 {
1037 clocks = <&clock CLK_I2C0>;
1038 clock-names = "i2c";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&i2c0_bus>;
1041};
1042
1043&i2c_1 {
1044 clocks = <&clock CLK_I2C1>;
1045 clock-names = "i2c";
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&i2c1_bus>;
1048};
1049
1050&i2c_2 {
1051 clocks = <&clock CLK_I2C2>;
1052 clock-names = "i2c";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&i2c2_bus>;
1055};
1056
1057&i2c_3 {
1058 clocks = <&clock CLK_I2C3>;
1059 clock-names = "i2c";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&i2c3_bus>;
1062};
1063
1064&prng {
1065 clocks = <&clock CLK_SSS>;
1066 clock-names = "secss";
1067};
1068
1069&pwm {
1070 clocks = <&clock CLK_PWM>;
1071 clock-names = "timers";
1072};
1073
1074&rtc {
1075 clocks = <&clock CLK_RTC>;
1076 clock-names = "rtc";
1077 interrupt-parent = <&pmu_system_controller>;
1078 status = "disabled";
1079};
1080
1081&serial_0 {
1082 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1083 clock-names = "uart", "clk_uart_baud0";
1084 dmas = <&pdma0 13>, <&pdma0 14>;
1085 dma-names = "rx", "tx";
1086};
1087
1088&serial_1 {
1089 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1090 clock-names = "uart", "clk_uart_baud0";
1091 dmas = <&pdma1 15>, <&pdma1 16>;
1092 dma-names = "rx", "tx";
1093};
1094
1095&serial_2 {
1096 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1097 clock-names = "uart", "clk_uart_baud0";
1098 dmas = <&pdma0 15>, <&pdma0 16>;
1099 dma-names = "rx", "tx";
1100};
1101
1102&serial_3 {
1103 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1104 clock-names = "uart", "clk_uart_baud0";
1105 dmas = <&pdma1 17>, <&pdma1 18>;
1106 dma-names = "rx", "tx";
1107};
1108
1109&sss {
1110 clocks = <&clock CLK_SSS>;
1111 clock-names = "secss";
1112};
1113
1114&trng {
1115 clocks = <&clock CLK_SSS>;
1116 clock-names = "secss";
1117};
1118
1119#include "exynos5250-pinctrl.dtsi"
1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#include <dt-bindings/clock/exynos5250.h>
21#include "exynos5.dtsi"
22#include "exynos4-cpu-thermal.dtsi"
23#include <dt-bindings/clock/exynos-audss-clk.h>
24
25/ {
26 compatible = "samsung,exynos5250", "samsung,exynos5";
27
28 aliases {
29 spi0 = &spi_0;
30 spi1 = &spi_1;
31 spi2 = &spi_2;
32 gsc0 = &gsc_0;
33 gsc1 = &gsc_1;
34 gsc2 = &gsc_2;
35 gsc3 = &gsc_3;
36 mshc0 = &mmc_0;
37 mshc1 = &mmc_1;
38 mshc2 = &mmc_2;
39 mshc3 = &mmc_3;
40 i2c0 = &i2c_0;
41 i2c1 = &i2c_1;
42 i2c2 = &i2c_2;
43 i2c3 = &i2c_3;
44 i2c4 = &i2c_4;
45 i2c5 = &i2c_5;
46 i2c6 = &i2c_6;
47 i2c7 = &i2c_7;
48 i2c8 = &i2c_8;
49 i2c9 = &i2c_9;
50 pinctrl0 = &pinctrl_0;
51 pinctrl1 = &pinctrl_1;
52 pinctrl2 = &pinctrl_2;
53 pinctrl3 = &pinctrl_3;
54 };
55
56 cpus {
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 cpu0: cpu@0 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <0>;
64 clock-frequency = <1700000000>;
65 clocks = <&clock CLK_ARM_CLK>;
66 clock-names = "cpu";
67 clock-latency = <140000>;
68
69 operating-points = <
70 1700000 1300000
71 1600000 1250000
72 1500000 1225000
73 1400000 1200000
74 1300000 1150000
75 1200000 1125000
76 1100000 1100000
77 1000000 1075000
78 900000 1050000
79 800000 1025000
80 700000 1012500
81 600000 1000000
82 500000 975000
83 400000 950000
84 300000 937500
85 200000 925000
86 >;
87 cooling-min-level = <15>;
88 cooling-max-level = <9>;
89 #cooling-cells = <2>; /* min followed by max */
90 };
91 cpu@1 {
92 device_type = "cpu";
93 compatible = "arm,cortex-a15";
94 reg = <1>;
95 clock-frequency = <1700000000>;
96 };
97 };
98
99 sysram@02020000 {
100 compatible = "mmio-sram";
101 reg = <0x02020000 0x30000>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x02020000 0x30000>;
105
106 smp-sysram@0 {
107 compatible = "samsung,exynos4210-sysram";
108 reg = <0x0 0x1000>;
109 };
110
111 smp-sysram@2f000 {
112 compatible = "samsung,exynos4210-sysram-ns";
113 reg = <0x2f000 0x1000>;
114 };
115 };
116
117 pd_gsc: gsc-power-domain@10044000 {
118 compatible = "samsung,exynos4210-pd";
119 reg = <0x10044000 0x20>;
120 #power-domain-cells = <0>;
121 };
122
123 pd_mfc: mfc-power-domain@10044040 {
124 compatible = "samsung,exynos4210-pd";
125 reg = <0x10044040 0x20>;
126 #power-domain-cells = <0>;
127 };
128
129 pd_disp1: disp1-power-domain@100440A0 {
130 compatible = "samsung,exynos4210-pd";
131 reg = <0x100440A0 0x20>;
132 #power-domain-cells = <0>;
133 clocks = <&clock CLK_FIN_PLL>,
134 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
135 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
136 clock-names = "oscclk", "clk0", "clk1";
137 };
138
139 clock: clock-controller@10010000 {
140 compatible = "samsung,exynos5250-clock";
141 reg = <0x10010000 0x30000>;
142 #clock-cells = <1>;
143 };
144
145 clock_audss: audss-clock-controller@3810000 {
146 compatible = "samsung,exynos5250-audss-clock";
147 reg = <0x03810000 0x0C>;
148 #clock-cells = <1>;
149 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
150 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
151 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
152 };
153
154 timer {
155 compatible = "arm,armv7-timer";
156 interrupts = <1 13 0xf08>,
157 <1 14 0xf08>,
158 <1 11 0xf08>,
159 <1 10 0xf08>;
160 /* Unfortunately we need this since some versions of U-Boot
161 * on Exynos don't set the CNTFRQ register, so we need the
162 * value from DT.
163 */
164 clock-frequency = <24000000>;
165 };
166
167 mct@101C0000 {
168 compatible = "samsung,exynos4210-mct";
169 reg = <0x101C0000 0x800>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 interrupt-parent = <&mct_map>;
173 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
174 <4 0>, <5 0>;
175 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
176 clock-names = "fin_pll", "mct";
177
178 mct_map: mct-map {
179 #interrupt-cells = <2>;
180 #address-cells = <0>;
181 #size-cells = <0>;
182 interrupt-map = <0x0 0 &combiner 23 3>,
183 <0x1 0 &combiner 23 4>,
184 <0x2 0 &combiner 25 2>,
185 <0x3 0 &combiner 25 3>,
186 <0x4 0 &gic 0 120 0>,
187 <0x5 0 &gic 0 121 0>;
188 };
189 };
190
191 pmu {
192 compatible = "arm,cortex-a15-pmu";
193 interrupt-parent = <&combiner>;
194 interrupts = <1 2>, <22 4>;
195 };
196
197 pinctrl_0: pinctrl@11400000 {
198 compatible = "samsung,exynos5250-pinctrl";
199 reg = <0x11400000 0x1000>;
200 interrupts = <0 46 0>;
201
202 wakup_eint: wakeup-interrupt-controller {
203 compatible = "samsung,exynos4210-wakeup-eint";
204 interrupt-parent = <&gic>;
205 interrupts = <0 32 0>;
206 };
207 };
208
209 pinctrl_1: pinctrl@13400000 {
210 compatible = "samsung,exynos5250-pinctrl";
211 reg = <0x13400000 0x1000>;
212 interrupts = <0 45 0>;
213 };
214
215 pinctrl_2: pinctrl@10d10000 {
216 compatible = "samsung,exynos5250-pinctrl";
217 reg = <0x10d10000 0x1000>;
218 interrupts = <0 50 0>;
219 };
220
221 pinctrl_3: pinctrl@03860000 {
222 compatible = "samsung,exynos5250-pinctrl";
223 reg = <0x03860000 0x1000>;
224 interrupts = <0 47 0>;
225 };
226
227 pmu_system_controller: system-controller@10040000 {
228 compatible = "samsung,exynos5250-pmu", "syscon";
229 reg = <0x10040000 0x5000>;
230 clock-names = "clkout16";
231 clocks = <&clock CLK_FIN_PLL>;
232 #clock-cells = <1>;
233 interrupt-controller;
234 #interrupt-cells = <3>;
235 interrupt-parent = <&gic>;
236 };
237
238 sysreg_system_controller: syscon@10050000 {
239 compatible = "samsung,exynos5-sysreg", "syscon";
240 reg = <0x10050000 0x5000>;
241 };
242
243 watchdog@101D0000 {
244 compatible = "samsung,exynos5250-wdt";
245 reg = <0x101D0000 0x100>;
246 interrupts = <0 42 0>;
247 clocks = <&clock CLK_WDT>;
248 clock-names = "watchdog";
249 samsung,syscon-phandle = <&pmu_system_controller>;
250 };
251
252 g2d@10850000 {
253 compatible = "samsung,exynos5250-g2d";
254 reg = <0x10850000 0x1000>;
255 interrupts = <0 91 0>;
256 clocks = <&clock CLK_G2D>;
257 clock-names = "fimg2d";
258 iommus = <&sysmmu_g2d>;
259 };
260
261 mfc: codec@11000000 {
262 compatible = "samsung,mfc-v6";
263 reg = <0x11000000 0x10000>;
264 interrupts = <0 96 0>;
265 power-domains = <&pd_mfc>;
266 clocks = <&clock CLK_MFC>;
267 clock-names = "mfc";
268 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
269 iommu-names = "left", "right";
270 };
271
272 rotator: rotator@11C00000 {
273 compatible = "samsung,exynos5250-rotator";
274 reg = <0x11C00000 0x64>;
275 interrupts = <0 84 0>;
276 clocks = <&clock CLK_ROTATOR>;
277 clock-names = "rotator";
278 iommus = <&sysmmu_rotator>;
279 };
280
281 tmu: tmu@10060000 {
282 compatible = "samsung,exynos5250-tmu";
283 reg = <0x10060000 0x100>;
284 interrupts = <0 65 0>;
285 clocks = <&clock CLK_TMU>;
286 clock-names = "tmu_apbif";
287 #include "exynos4412-tmu-sensor-conf.dtsi"
288 };
289
290 thermal-zones {
291 cpu_thermal: cpu-thermal {
292 polling-delay-passive = <0>;
293 polling-delay = <0>;
294 thermal-sensors = <&tmu 0>;
295
296 cooling-maps {
297 map0 {
298 /* Corresponds to 800MHz at freq_table */
299 cooling-device = <&cpu0 9 9>;
300 };
301 map1 {
302 /* Corresponds to 200MHz at freq_table */
303 cooling-device = <&cpu0 15 15>;
304 };
305 };
306 };
307 };
308
309 sata: sata@122F0000 {
310 compatible = "snps,dwc-ahci";
311 samsung,sata-freq = <66>;
312 reg = <0x122F0000 0x1ff>;
313 interrupts = <0 115 0>;
314 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
315 clock-names = "sata", "sclk_sata";
316 phys = <&sata_phy>;
317 phy-names = "sata-phy";
318 status = "disabled";
319 };
320
321 sata_phy: sata-phy@12170000 {
322 compatible = "samsung,exynos5250-sata-phy";
323 reg = <0x12170000 0x1ff>;
324 clocks = <&clock CLK_SATA_PHYCTRL>;
325 clock-names = "sata_phyctrl";
326 #phy-cells = <0>;
327 samsung,syscon-phandle = <&pmu_system_controller>;
328 status = "disabled";
329 };
330
331 i2c_0: i2c@12C60000 {
332 compatible = "samsung,s3c2440-i2c";
333 reg = <0x12C60000 0x100>;
334 interrupts = <0 56 0>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 clocks = <&clock CLK_I2C0>;
338 clock-names = "i2c";
339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c0_bus>;
341 samsung,sysreg-phandle = <&sysreg_system_controller>;
342 status = "disabled";
343 };
344
345 i2c_1: i2c@12C70000 {
346 compatible = "samsung,s3c2440-i2c";
347 reg = <0x12C70000 0x100>;
348 interrupts = <0 57 0>;
349 #address-cells = <1>;
350 #size-cells = <0>;
351 clocks = <&clock CLK_I2C1>;
352 clock-names = "i2c";
353 pinctrl-names = "default";
354 pinctrl-0 = <&i2c1_bus>;
355 samsung,sysreg-phandle = <&sysreg_system_controller>;
356 status = "disabled";
357 };
358
359 i2c_2: i2c@12C80000 {
360 compatible = "samsung,s3c2440-i2c";
361 reg = <0x12C80000 0x100>;
362 interrupts = <0 58 0>;
363 #address-cells = <1>;
364 #size-cells = <0>;
365 clocks = <&clock CLK_I2C2>;
366 clock-names = "i2c";
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c2_bus>;
369 samsung,sysreg-phandle = <&sysreg_system_controller>;
370 status = "disabled";
371 };
372
373 i2c_3: i2c@12C90000 {
374 compatible = "samsung,s3c2440-i2c";
375 reg = <0x12C90000 0x100>;
376 interrupts = <0 59 0>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 clocks = <&clock CLK_I2C3>;
380 clock-names = "i2c";
381 pinctrl-names = "default";
382 pinctrl-0 = <&i2c3_bus>;
383 samsung,sysreg-phandle = <&sysreg_system_controller>;
384 status = "disabled";
385 };
386
387 i2c_4: i2c@12CA0000 {
388 compatible = "samsung,s3c2440-i2c";
389 reg = <0x12CA0000 0x100>;
390 interrupts = <0 60 0>;
391 #address-cells = <1>;
392 #size-cells = <0>;
393 clocks = <&clock CLK_I2C4>;
394 clock-names = "i2c";
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c4_bus>;
397 status = "disabled";
398 };
399
400 i2c_5: i2c@12CB0000 {
401 compatible = "samsung,s3c2440-i2c";
402 reg = <0x12CB0000 0x100>;
403 interrupts = <0 61 0>;
404 #address-cells = <1>;
405 #size-cells = <0>;
406 clocks = <&clock CLK_I2C5>;
407 clock-names = "i2c";
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c5_bus>;
410 status = "disabled";
411 };
412
413 i2c_6: i2c@12CC0000 {
414 compatible = "samsung,s3c2440-i2c";
415 reg = <0x12CC0000 0x100>;
416 interrupts = <0 62 0>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 clocks = <&clock CLK_I2C6>;
420 clock-names = "i2c";
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c6_bus>;
423 status = "disabled";
424 };
425
426 i2c_7: i2c@12CD0000 {
427 compatible = "samsung,s3c2440-i2c";
428 reg = <0x12CD0000 0x100>;
429 interrupts = <0 63 0>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 clocks = <&clock CLK_I2C7>;
433 clock-names = "i2c";
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c7_bus>;
436 status = "disabled";
437 };
438
439 i2c_8: i2c@12CE0000 {
440 compatible = "samsung,s3c2440-hdmiphy-i2c";
441 reg = <0x12CE0000 0x1000>;
442 interrupts = <0 64 0>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 clocks = <&clock CLK_I2C_HDMI>;
446 clock-names = "i2c";
447 status = "disabled";
448 };
449
450 i2c_9: i2c@121D0000 {
451 compatible = "samsung,exynos5-sata-phy-i2c";
452 reg = <0x121D0000 0x100>;
453 #address-cells = <1>;
454 #size-cells = <0>;
455 clocks = <&clock CLK_SATA_PHYI2C>;
456 clock-names = "i2c";
457 status = "disabled";
458 };
459
460 spi_0: spi@12d20000 {
461 compatible = "samsung,exynos4210-spi";
462 status = "disabled";
463 reg = <0x12d20000 0x100>;
464 interrupts = <0 66 0>;
465 dmas = <&pdma0 5
466 &pdma0 4>;
467 dma-names = "tx", "rx";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
471 clock-names = "spi", "spi_busclk0";
472 pinctrl-names = "default";
473 pinctrl-0 = <&spi0_bus>;
474 };
475
476 spi_1: spi@12d30000 {
477 compatible = "samsung,exynos4210-spi";
478 status = "disabled";
479 reg = <0x12d30000 0x100>;
480 interrupts = <0 67 0>;
481 dmas = <&pdma1 5
482 &pdma1 4>;
483 dma-names = "tx", "rx";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
487 clock-names = "spi", "spi_busclk0";
488 pinctrl-names = "default";
489 pinctrl-0 = <&spi1_bus>;
490 };
491
492 spi_2: spi@12d40000 {
493 compatible = "samsung,exynos4210-spi";
494 status = "disabled";
495 reg = <0x12d40000 0x100>;
496 interrupts = <0 68 0>;
497 dmas = <&pdma0 7
498 &pdma0 6>;
499 dma-names = "tx", "rx";
500 #address-cells = <1>;
501 #size-cells = <0>;
502 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
503 clock-names = "spi", "spi_busclk0";
504 pinctrl-names = "default";
505 pinctrl-0 = <&spi2_bus>;
506 };
507
508 mmc_0: mmc@12200000 {
509 compatible = "samsung,exynos5250-dw-mshc";
510 interrupts = <0 75 0>;
511 #address-cells = <1>;
512 #size-cells = <0>;
513 reg = <0x12200000 0x1000>;
514 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
515 clock-names = "biu", "ciu";
516 fifo-depth = <0x80>;
517 status = "disabled";
518 };
519
520 mmc_1: mmc@12210000 {
521 compatible = "samsung,exynos5250-dw-mshc";
522 interrupts = <0 76 0>;
523 #address-cells = <1>;
524 #size-cells = <0>;
525 reg = <0x12210000 0x1000>;
526 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
527 clock-names = "biu", "ciu";
528 fifo-depth = <0x80>;
529 status = "disabled";
530 };
531
532 mmc_2: mmc@12220000 {
533 compatible = "samsung,exynos5250-dw-mshc";
534 interrupts = <0 77 0>;
535 #address-cells = <1>;
536 #size-cells = <0>;
537 reg = <0x12220000 0x1000>;
538 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
539 clock-names = "biu", "ciu";
540 fifo-depth = <0x80>;
541 status = "disabled";
542 };
543
544 mmc_3: mmc@12230000 {
545 compatible = "samsung,exynos5250-dw-mshc";
546 reg = <0x12230000 0x1000>;
547 interrupts = <0 78 0>;
548 #address-cells = <1>;
549 #size-cells = <0>;
550 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
551 clock-names = "biu", "ciu";
552 fifo-depth = <0x80>;
553 status = "disabled";
554 };
555
556 i2s0: i2s@03830000 {
557 compatible = "samsung,s5pv210-i2s";
558 status = "disabled";
559 reg = <0x03830000 0x100>;
560 dmas = <&pdma0 10
561 &pdma0 9
562 &pdma0 8>;
563 dma-names = "tx", "rx", "tx-sec";
564 clocks = <&clock_audss EXYNOS_I2S_BUS>,
565 <&clock_audss EXYNOS_I2S_BUS>,
566 <&clock_audss EXYNOS_SCLK_I2S>;
567 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
568 samsung,idma-addr = <0x03000000>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2s0_bus>;
571 };
572
573 i2s1: i2s@12D60000 {
574 compatible = "samsung,s3c6410-i2s";
575 status = "disabled";
576 reg = <0x12D60000 0x100>;
577 dmas = <&pdma1 12
578 &pdma1 11>;
579 dma-names = "tx", "rx";
580 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
581 clock-names = "iis", "i2s_opclk0";
582 pinctrl-names = "default";
583 pinctrl-0 = <&i2s1_bus>;
584 };
585
586 i2s2: i2s@12D70000 {
587 compatible = "samsung,s3c6410-i2s";
588 status = "disabled";
589 reg = <0x12D70000 0x100>;
590 dmas = <&pdma0 12
591 &pdma0 11>;
592 dma-names = "tx", "rx";
593 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
594 clock-names = "iis", "i2s_opclk0";
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2s2_bus>;
597 };
598
599 usb@12000000 {
600 compatible = "samsung,exynos5250-dwusb3";
601 clocks = <&clock CLK_USB3>;
602 clock-names = "usbdrd30";
603 #address-cells = <1>;
604 #size-cells = <1>;
605 ranges;
606
607 usbdrd_dwc3: dwc3 {
608 compatible = "synopsys,dwc3";
609 reg = <0x12000000 0x10000>;
610 interrupts = <0 72 0>;
611 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
612 phy-names = "usb2-phy", "usb3-phy";
613 };
614 };
615
616 usbdrd_phy: phy@12100000 {
617 compatible = "samsung,exynos5250-usbdrd-phy";
618 reg = <0x12100000 0x100>;
619 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
620 clock-names = "phy", "ref";
621 samsung,pmu-syscon = <&pmu_system_controller>;
622 #phy-cells = <1>;
623 };
624
625 ehci: usb@12110000 {
626 compatible = "samsung,exynos4210-ehci";
627 reg = <0x12110000 0x100>;
628 interrupts = <0 71 0>;
629
630 clocks = <&clock CLK_USB2>;
631 clock-names = "usbhost";
632 #address-cells = <1>;
633 #size-cells = <0>;
634 port@0 {
635 reg = <0>;
636 phys = <&usb2_phy_gen 1>;
637 };
638 };
639
640 ohci: usb@12120000 {
641 compatible = "samsung,exynos4210-ohci";
642 reg = <0x12120000 0x100>;
643 interrupts = <0 71 0>;
644
645 clocks = <&clock CLK_USB2>;
646 clock-names = "usbhost";
647 #address-cells = <1>;
648 #size-cells = <0>;
649 port@0 {
650 reg = <0>;
651 phys = <&usb2_phy_gen 1>;
652 };
653 };
654
655 usb2_phy_gen: phy@12130000 {
656 compatible = "samsung,exynos5250-usb2-phy";
657 reg = <0x12130000 0x100>;
658 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
659 clock-names = "phy", "ref";
660 #phy-cells = <1>;
661 samsung,sysreg-phandle = <&sysreg_system_controller>;
662 samsung,pmureg-phandle = <&pmu_system_controller>;
663 };
664
665 pwm: pwm@12dd0000 {
666 compatible = "samsung,exynos4210-pwm";
667 reg = <0x12dd0000 0x100>;
668 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
669 #pwm-cells = <3>;
670 clocks = <&clock CLK_PWM>;
671 clock-names = "timers";
672 };
673
674 amba {
675 #address-cells = <1>;
676 #size-cells = <1>;
677 compatible = "simple-bus";
678 interrupt-parent = <&gic>;
679 ranges;
680
681 pdma0: pdma@121A0000 {
682 compatible = "arm,pl330", "arm,primecell";
683 reg = <0x121A0000 0x1000>;
684 interrupts = <0 34 0>;
685 clocks = <&clock CLK_PDMA0>;
686 clock-names = "apb_pclk";
687 #dma-cells = <1>;
688 #dma-channels = <8>;
689 #dma-requests = <32>;
690 };
691
692 pdma1: pdma@121B0000 {
693 compatible = "arm,pl330", "arm,primecell";
694 reg = <0x121B0000 0x1000>;
695 interrupts = <0 35 0>;
696 clocks = <&clock CLK_PDMA1>;
697 clock-names = "apb_pclk";
698 #dma-cells = <1>;
699 #dma-channels = <8>;
700 #dma-requests = <32>;
701 };
702
703 mdma0: mdma@10800000 {
704 compatible = "arm,pl330", "arm,primecell";
705 reg = <0x10800000 0x1000>;
706 interrupts = <0 33 0>;
707 clocks = <&clock CLK_MDMA0>;
708 clock-names = "apb_pclk";
709 #dma-cells = <1>;
710 #dma-channels = <8>;
711 #dma-requests = <1>;
712 };
713
714 mdma1: mdma@11C10000 {
715 compatible = "arm,pl330", "arm,primecell";
716 reg = <0x11C10000 0x1000>;
717 interrupts = <0 124 0>;
718 clocks = <&clock CLK_MDMA1>;
719 clock-names = "apb_pclk";
720 #dma-cells = <1>;
721 #dma-channels = <8>;
722 #dma-requests = <1>;
723 };
724 };
725
726 gsc_0: gsc@13e00000 {
727 compatible = "samsung,exynos5-gsc";
728 reg = <0x13e00000 0x1000>;
729 interrupts = <0 85 0>;
730 power-domains = <&pd_gsc>;
731 clocks = <&clock CLK_GSCL0>;
732 clock-names = "gscl";
733 iommu = <&sysmmu_gsc0>;
734 };
735
736 gsc_1: gsc@13e10000 {
737 compatible = "samsung,exynos5-gsc";
738 reg = <0x13e10000 0x1000>;
739 interrupts = <0 86 0>;
740 power-domains = <&pd_gsc>;
741 clocks = <&clock CLK_GSCL1>;
742 clock-names = "gscl";
743 iommu = <&sysmmu_gsc1>;
744 };
745
746 gsc_2: gsc@13e20000 {
747 compatible = "samsung,exynos5-gsc";
748 reg = <0x13e20000 0x1000>;
749 interrupts = <0 87 0>;
750 power-domains = <&pd_gsc>;
751 clocks = <&clock CLK_GSCL2>;
752 clock-names = "gscl";
753 iommu = <&sysmmu_gsc2>;
754 };
755
756 gsc_3: gsc@13e30000 {
757 compatible = "samsung,exynos5-gsc";
758 reg = <0x13e30000 0x1000>;
759 interrupts = <0 88 0>;
760 power-domains = <&pd_gsc>;
761 clocks = <&clock CLK_GSCL3>;
762 clock-names = "gscl";
763 iommu = <&sysmmu_gsc3>;
764 };
765
766 hdmi: hdmi {
767 compatible = "samsung,exynos4212-hdmi";
768 reg = <0x14530000 0x70000>;
769 power-domains = <&pd_disp1>;
770 interrupts = <0 95 0>;
771 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
772 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
773 <&clock CLK_MOUT_HDMI>;
774 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
775 "sclk_hdmiphy", "mout_hdmi";
776 samsung,syscon-phandle = <&pmu_system_controller>;
777 };
778
779 mixer {
780 compatible = "samsung,exynos5250-mixer";
781 reg = <0x14450000 0x10000>;
782 power-domains = <&pd_disp1>;
783 interrupts = <0 94 0>;
784 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
785 <&clock CLK_SCLK_HDMI>;
786 clock-names = "mixer", "hdmi", "sclk_hdmi";
787 iommus = <&sysmmu_tv>;
788 };
789
790 dp_phy: video-phy@10040720 {
791 compatible = "samsung,exynos5250-dp-video-phy";
792 samsung,pmu-syscon = <&pmu_system_controller>;
793 #phy-cells = <0>;
794 };
795
796 adc: adc@12D10000 {
797 compatible = "samsung,exynos-adc-v1";
798 reg = <0x12D10000 0x100>;
799 interrupts = <0 106 0>;
800 clocks = <&clock CLK_ADC>;
801 clock-names = "adc";
802 #io-channel-cells = <1>;
803 io-channel-ranges;
804 samsung,syscon-phandle = <&pmu_system_controller>;
805 status = "disabled";
806 };
807
808 sss@10830000 {
809 compatible = "samsung,exynos4210-secss";
810 reg = <0x10830000 0x300>;
811 interrupts = <0 112 0>;
812 clocks = <&clock CLK_SSS>;
813 clock-names = "secss";
814 };
815
816 sysmmu_g2d: sysmmu@10A60000 {
817 compatible = "samsung,exynos-sysmmu";
818 reg = <0x10A60000 0x1000>;
819 interrupt-parent = <&combiner>;
820 interrupts = <24 5>;
821 clock-names = "sysmmu", "master";
822 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
823 #iommu-cells = <0>;
824 };
825
826 sysmmu_mfc_r: sysmmu@11200000 {
827 compatible = "samsung,exynos-sysmmu";
828 reg = <0x11200000 0x1000>;
829 interrupt-parent = <&combiner>;
830 interrupts = <6 2>;
831 power-domains = <&pd_mfc>;
832 clock-names = "sysmmu", "master";
833 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
834 #iommu-cells = <0>;
835 };
836
837 sysmmu_mfc_l: sysmmu@11210000 {
838 compatible = "samsung,exynos-sysmmu";
839 reg = <0x11210000 0x1000>;
840 interrupt-parent = <&combiner>;
841 interrupts = <8 5>;
842 power-domains = <&pd_mfc>;
843 clock-names = "sysmmu", "master";
844 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
845 #iommu-cells = <0>;
846 };
847
848 sysmmu_rotator: sysmmu@11D40000 {
849 compatible = "samsung,exynos-sysmmu";
850 reg = <0x11D40000 0x1000>;
851 interrupt-parent = <&combiner>;
852 interrupts = <4 0>;
853 clock-names = "sysmmu", "master";
854 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
855 #iommu-cells = <0>;
856 };
857
858 sysmmu_jpeg: sysmmu@11F20000 {
859 compatible = "samsung,exynos-sysmmu";
860 reg = <0x11F20000 0x1000>;
861 interrupt-parent = <&combiner>;
862 interrupts = <4 2>;
863 power-domains = <&pd_gsc>;
864 clock-names = "sysmmu", "master";
865 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
866 #iommu-cells = <0>;
867 };
868
869 sysmmu_fimc_isp: sysmmu@13260000 {
870 compatible = "samsung,exynos-sysmmu";
871 reg = <0x13260000 0x1000>;
872 interrupt-parent = <&combiner>;
873 interrupts = <10 6>;
874 clock-names = "sysmmu";
875 clocks = <&clock CLK_SMMU_FIMC_ISP>;
876 #iommu-cells = <0>;
877 };
878
879 sysmmu_fimc_drc: sysmmu@13270000 {
880 compatible = "samsung,exynos-sysmmu";
881 reg = <0x13270000 0x1000>;
882 interrupt-parent = <&combiner>;
883 interrupts = <11 6>;
884 clock-names = "sysmmu";
885 clocks = <&clock CLK_SMMU_FIMC_DRC>;
886 #iommu-cells = <0>;
887 };
888
889 sysmmu_fimc_fd: sysmmu@132A0000 {
890 compatible = "samsung,exynos-sysmmu";
891 reg = <0x132A0000 0x1000>;
892 interrupt-parent = <&combiner>;
893 interrupts = <5 0>;
894 clock-names = "sysmmu";
895 clocks = <&clock CLK_SMMU_FIMC_FD>;
896 #iommu-cells = <0>;
897 };
898
899 sysmmu_fimc_scc: sysmmu@13280000 {
900 compatible = "samsung,exynos-sysmmu";
901 reg = <0x13280000 0x1000>;
902 interrupt-parent = <&combiner>;
903 interrupts = <5 2>;
904 clock-names = "sysmmu";
905 clocks = <&clock CLK_SMMU_FIMC_SCC>;
906 #iommu-cells = <0>;
907 };
908
909 sysmmu_fimc_scp: sysmmu@13290000 {
910 compatible = "samsung,exynos-sysmmu";
911 reg = <0x13290000 0x1000>;
912 interrupt-parent = <&combiner>;
913 interrupts = <3 6>;
914 clock-names = "sysmmu";
915 clocks = <&clock CLK_SMMU_FIMC_SCP>;
916 #iommu-cells = <0>;
917 };
918
919 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
920 compatible = "samsung,exynos-sysmmu";
921 reg = <0x132B0000 0x1000>;
922 interrupt-parent = <&combiner>;
923 interrupts = <5 4>;
924 clock-names = "sysmmu";
925 clocks = <&clock CLK_SMMU_FIMC_MCU>;
926 #iommu-cells = <0>;
927 };
928
929 sysmmu_fimc_odc: sysmmu@132C0000 {
930 compatible = "samsung,exynos-sysmmu";
931 reg = <0x132C0000 0x1000>;
932 interrupt-parent = <&combiner>;
933 interrupts = <11 0>;
934 clock-names = "sysmmu";
935 clocks = <&clock CLK_SMMU_FIMC_ODC>;
936 #iommu-cells = <0>;
937 };
938
939 sysmmu_fimc_dis0: sysmmu@132D0000 {
940 compatible = "samsung,exynos-sysmmu";
941 reg = <0x132D0000 0x1000>;
942 interrupt-parent = <&combiner>;
943 interrupts = <10 4>;
944 clock-names = "sysmmu";
945 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
946 #iommu-cells = <0>;
947 };
948
949 sysmmu_fimc_dis1: sysmmu@132E0000{
950 compatible = "samsung,exynos-sysmmu";
951 reg = <0x132E0000 0x1000>;
952 interrupt-parent = <&combiner>;
953 interrupts = <9 4>;
954 clock-names = "sysmmu";
955 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
956 #iommu-cells = <0>;
957 };
958
959 sysmmu_fimc_3dnr: sysmmu@132F0000 {
960 compatible = "samsung,exynos-sysmmu";
961 reg = <0x132F0000 0x1000>;
962 interrupt-parent = <&combiner>;
963 interrupts = <5 6>;
964 clock-names = "sysmmu";
965 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
966 #iommu-cells = <0>;
967 };
968
969 sysmmu_fimc_lite0: sysmmu@13C40000 {
970 compatible = "samsung,exynos-sysmmu";
971 reg = <0x13C40000 0x1000>;
972 interrupt-parent = <&combiner>;
973 interrupts = <3 4>;
974 power-domains = <&pd_gsc>;
975 clock-names = "sysmmu", "master";
976 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
977 #iommu-cells = <0>;
978 };
979
980 sysmmu_fimc_lite1: sysmmu@13C50000 {
981 compatible = "samsung,exynos-sysmmu";
982 reg = <0x13C50000 0x1000>;
983 interrupt-parent = <&combiner>;
984 interrupts = <24 1>;
985 power-domains = <&pd_gsc>;
986 clock-names = "sysmmu", "master";
987 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
988 #iommu-cells = <0>;
989 };
990
991 sysmmu_gsc0: sysmmu@13E80000 {
992 compatible = "samsung,exynos-sysmmu";
993 reg = <0x13E80000 0x1000>;
994 interrupt-parent = <&combiner>;
995 interrupts = <2 0>;
996 power-domains = <&pd_gsc>;
997 clock-names = "sysmmu", "master";
998 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
999 #iommu-cells = <0>;
1000 };
1001
1002 sysmmu_gsc1: sysmmu@13E90000 {
1003 compatible = "samsung,exynos-sysmmu";
1004 reg = <0x13E90000 0x1000>;
1005 interrupt-parent = <&combiner>;
1006 interrupts = <2 2>;
1007 power-domains = <&pd_gsc>;
1008 clock-names = "sysmmu", "master";
1009 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1010 #iommu-cells = <0>;
1011 };
1012
1013 sysmmu_gsc2: sysmmu@13EA0000 {
1014 compatible = "samsung,exynos-sysmmu";
1015 reg = <0x13EA0000 0x1000>;
1016 interrupt-parent = <&combiner>;
1017 interrupts = <2 4>;
1018 power-domains = <&pd_gsc>;
1019 clock-names = "sysmmu", "master";
1020 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1021 #iommu-cells = <0>;
1022 };
1023
1024 sysmmu_gsc3: sysmmu@13EB0000 {
1025 compatible = "samsung,exynos-sysmmu";
1026 reg = <0x13EB0000 0x1000>;
1027 interrupt-parent = <&combiner>;
1028 interrupts = <2 6>;
1029 power-domains = <&pd_gsc>;
1030 clock-names = "sysmmu", "master";
1031 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1032 #iommu-cells = <0>;
1033 };
1034
1035 sysmmu_fimd1: sysmmu@14640000 {
1036 compatible = "samsung,exynos-sysmmu";
1037 reg = <0x14640000 0x1000>;
1038 interrupt-parent = <&combiner>;
1039 interrupts = <3 2>;
1040 power-domains = <&pd_disp1>;
1041 clock-names = "sysmmu", "master";
1042 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1043 #iommu-cells = <0>;
1044 };
1045
1046 sysmmu_tv: sysmmu@14650000 {
1047 compatible = "samsung,exynos-sysmmu";
1048 reg = <0x14650000 0x1000>;
1049 interrupt-parent = <&combiner>;
1050 interrupts = <7 4>;
1051 power-domains = <&pd_disp1>;
1052 clock-names = "sysmmu", "master";
1053 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1054 #iommu-cells = <0>;
1055 };
1056};
1057
1058&dp {
1059 power-domains = <&pd_disp1>;
1060 clocks = <&clock CLK_DP>;
1061 clock-names = "dp";
1062 phys = <&dp_phy>;
1063 phy-names = "dp";
1064};
1065
1066&fimd {
1067 power-domains = <&pd_disp1>;
1068 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1069 clock-names = "sclk_fimd", "fimd";
1070 iommus = <&sysmmu_fimd1>;
1071};
1072
1073&rtc {
1074 clocks = <&clock CLK_RTC>;
1075 clock-names = "rtc";
1076 interrupt-parent = <&pmu_system_controller>;
1077 status = "disabled";
1078};
1079
1080&serial_0 {
1081 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1082 clock-names = "uart", "clk_uart_baud0";
1083};
1084
1085&serial_1 {
1086 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1087 clock-names = "uart", "clk_uart_baud0";
1088};
1089
1090&serial_2 {
1091 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1092 clock-names = "uart", "clk_uart_baud0";
1093};
1094
1095&serial_3 {
1096 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1097 clock-names = "uart", "clk_uart_baud0";
1098};
1099
1100#include "exynos5250-pinctrl.dtsi"