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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SAMSUNG EXYNOS5250 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
9 * EXYNOS5250 based board files can include this file and provide
10 * values for board specfic bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
14 * additional nodes can be added to this file.
15 */
16
17#include <dt-bindings/clock/exynos5250.h>
18#include "exynos5.dtsi"
19#include "exynos4-cpu-thermal.dtsi"
20#include <dt-bindings/clock/exynos-audss-clk.h>
21
22/ {
23 compatible = "samsung,exynos5250", "samsung,exynos5";
24
25 aliases {
26 spi0 = &spi_0;
27 spi1 = &spi_1;
28 spi2 = &spi_2;
29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3;
33 mshc0 = &mmc_0;
34 mshc1 = &mmc_1;
35 mshc2 = &mmc_2;
36 mshc3 = &mmc_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 i2c9 = &i2c_9;
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a15";
56 reg = <0>;
57 clock-frequency = <1700000000>;
58 clocks = <&clock CLK_ARM_CLK>;
59 clock-names = "cpu";
60 clock-latency = <140000>;
61
62 operating-points = <
63 1700000 1300000
64 1600000 1250000
65 1500000 1225000
66 1400000 1200000
67 1300000 1150000
68 1200000 1125000
69 1100000 1100000
70 1000000 1075000
71 900000 1050000
72 800000 1025000
73 700000 1012500
74 600000 1000000
75 500000 975000
76 400000 950000
77 300000 937500
78 200000 925000
79 >;
80 #cooling-cells = <2>; /* min followed by max */
81 };
82 cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <1>;
86 clock-frequency = <1700000000>;
87 };
88 };
89
90 soc: soc {
91 sysram@2020000 {
92 compatible = "mmio-sram";
93 reg = <0x02020000 0x30000>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges = <0 0x02020000 0x30000>;
97
98 smp-sysram@0 {
99 compatible = "samsung,exynos4210-sysram";
100 reg = <0x0 0x1000>;
101 };
102
103 smp-sysram@2f000 {
104 compatible = "samsung,exynos4210-sysram-ns";
105 reg = <0x2f000 0x1000>;
106 };
107 };
108
109 pd_gsc: power-domain@10044000 {
110 compatible = "samsung,exynos4210-pd";
111 reg = <0x10044000 0x20>;
112 #power-domain-cells = <0>;
113 label = "GSC";
114 };
115
116 pd_mfc: power-domain@10044040 {
117 compatible = "samsung,exynos4210-pd";
118 reg = <0x10044040 0x20>;
119 #power-domain-cells = <0>;
120 label = "MFC";
121 };
122
123 pd_g3d: power-domain@10044060 {
124 compatible = "samsung,exynos4210-pd";
125 reg = <0x10044060 0x20>;
126 #power-domain-cells = <0>;
127 label = "G3D";
128 };
129
130 pd_disp1: power-domain@100440a0 {
131 compatible = "samsung,exynos4210-pd";
132 reg = <0x100440A0 0x20>;
133 #power-domain-cells = <0>;
134 label = "DISP1";
135 clocks = <&clock CLK_FIN_PLL>,
136 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
137 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
138 clock-names = "oscclk", "clk0", "clk1";
139 };
140
141 pd_mau: power-domain@100440c0 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x100440C0 0x20>;
144 #power-domain-cells = <0>;
145 label = "MAU";
146 };
147
148 clock: clock-controller@10010000 {
149 compatible = "samsung,exynos5250-clock";
150 reg = <0x10010000 0x30000>;
151 #clock-cells = <1>;
152 };
153
154 clock_audss: audss-clock-controller@3810000 {
155 compatible = "samsung,exynos5250-audss-clock";
156 reg = <0x03810000 0x0C>;
157 #clock-cells = <1>;
158 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
159 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
160 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
161 power-domains = <&pd_mau>;
162 };
163
164 timer {
165 compatible = "arm,armv7-timer";
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
170 /*
171 * Unfortunately we need this since some versions
172 * of U-Boot on Exynos don't set the CNTFRQ register,
173 * so we need the value from DT.
174 */
175 clock-frequency = <24000000>;
176 };
177
178 mct@101c0000 {
179 compatible = "samsung,exynos4210-mct";
180 reg = <0x101C0000 0x800>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
183 interrupt-parent = <&mct_map>;
184 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
185 <4 0>, <5 0>;
186 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
187 clock-names = "fin_pll", "mct";
188
189 mct_map: mct-map {
190 #interrupt-cells = <2>;
191 #address-cells = <0>;
192 #size-cells = <0>;
193 interrupt-map = <0x0 0 &combiner 23 3>,
194 <0x1 0 &combiner 23 4>,
195 <0x2 0 &combiner 25 2>,
196 <0x3 0 &combiner 25 3>,
197 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
198 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
199 };
200 };
201
202 pmu {
203 compatible = "arm,cortex-a15-pmu";
204 interrupt-parent = <&combiner>;
205 interrupts = <1 2>, <22 4>;
206 };
207
208 pinctrl_0: pinctrl@11400000 {
209 compatible = "samsung,exynos5250-pinctrl";
210 reg = <0x11400000 0x1000>;
211 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
212
213 wakup_eint: wakeup-interrupt-controller {
214 compatible = "samsung,exynos4210-wakeup-eint";
215 interrupt-parent = <&gic>;
216 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
217 };
218 };
219
220 pinctrl_1: pinctrl@13400000 {
221 compatible = "samsung,exynos5250-pinctrl";
222 reg = <0x13400000 0x1000>;
223 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
224 };
225
226 pinctrl_2: pinctrl@10d10000 {
227 compatible = "samsung,exynos5250-pinctrl";
228 reg = <0x10d10000 0x1000>;
229 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
230 };
231
232 pinctrl_3: pinctrl@3860000 {
233 compatible = "samsung,exynos5250-pinctrl";
234 reg = <0x03860000 0x1000>;
235 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
236 power-domains = <&pd_mau>;
237 };
238
239 pmu_system_controller: system-controller@10040000 {
240 compatible = "samsung,exynos5250-pmu", "syscon";
241 reg = <0x10040000 0x5000>;
242 clock-names = "clkout16";
243 clocks = <&clock CLK_FIN_PLL>;
244 #clock-cells = <1>;
245 interrupt-controller;
246 #interrupt-cells = <3>;
247 interrupt-parent = <&gic>;
248 };
249
250 watchdog@101d0000 {
251 compatible = "samsung,exynos5250-wdt";
252 reg = <0x101D0000 0x100>;
253 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clock CLK_WDT>;
255 clock-names = "watchdog";
256 samsung,syscon-phandle = <&pmu_system_controller>;
257 };
258
259 mfc: codec@11000000 {
260 compatible = "samsung,mfc-v6";
261 reg = <0x11000000 0x10000>;
262 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
263 power-domains = <&pd_mfc>;
264 clocks = <&clock CLK_MFC>;
265 clock-names = "mfc";
266 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
267 iommu-names = "left", "right";
268 };
269
270 rotator: rotator@11c00000 {
271 compatible = "samsung,exynos5250-rotator";
272 reg = <0x11C00000 0x64>;
273 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clock CLK_ROTATOR>;
275 clock-names = "rotator";
276 iommus = <&sysmmu_rotator>;
277 };
278
279 tmu: tmu@10060000 {
280 compatible = "samsung,exynos5250-tmu";
281 reg = <0x10060000 0x100>;
282 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clock CLK_TMU>;
284 clock-names = "tmu_apbif";
285 #include "exynos4412-tmu-sensor-conf.dtsi"
286 };
287
288 sata: sata@122f0000 {
289 compatible = "snps,dwc-ahci";
290 samsung,sata-freq = <66>;
291 reg = <0x122F0000 0x1ff>;
292 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
294 clock-names = "sata", "sclk_sata";
295 phys = <&sata_phy>;
296 phy-names = "sata-phy";
297 status = "disabled";
298 };
299
300 sata_phy: sata-phy@12170000 {
301 compatible = "samsung,exynos5250-sata-phy";
302 reg = <0x12170000 0x1ff>;
303 clocks = <&clock CLK_SATA_PHYCTRL>;
304 clock-names = "sata_phyctrl";
305 #phy-cells = <0>;
306 samsung,syscon-phandle = <&pmu_system_controller>;
307 status = "disabled";
308 };
309
310 /* i2c_0-3 are defined in exynos5.dtsi */
311 i2c_4: i2c@12ca0000 {
312 compatible = "samsung,s3c2440-i2c";
313 reg = <0x12CA0000 0x100>;
314 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 clocks = <&clock CLK_I2C4>;
318 clock-names = "i2c";
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c4_bus>;
321 status = "disabled";
322 };
323
324 i2c_5: i2c@12cb0000 {
325 compatible = "samsung,s3c2440-i2c";
326 reg = <0x12CB0000 0x100>;
327 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
328 #address-cells = <1>;
329 #size-cells = <0>;
330 clocks = <&clock CLK_I2C5>;
331 clock-names = "i2c";
332 pinctrl-names = "default";
333 pinctrl-0 = <&i2c5_bus>;
334 status = "disabled";
335 };
336
337 i2c_6: i2c@12cc0000 {
338 compatible = "samsung,s3c2440-i2c";
339 reg = <0x12CC0000 0x100>;
340 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 clocks = <&clock CLK_I2C6>;
344 clock-names = "i2c";
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c6_bus>;
347 status = "disabled";
348 };
349
350 i2c_7: i2c@12cd0000 {
351 compatible = "samsung,s3c2440-i2c";
352 reg = <0x12CD0000 0x100>;
353 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 clocks = <&clock CLK_I2C7>;
357 clock-names = "i2c";
358 pinctrl-names = "default";
359 pinctrl-0 = <&i2c7_bus>;
360 status = "disabled";
361 };
362
363 i2c_8: i2c@12ce0000 {
364 compatible = "samsung,s3c2440-hdmiphy-i2c";
365 reg = <0x12CE0000 0x1000>;
366 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 clocks = <&clock CLK_I2C_HDMI>;
370 clock-names = "i2c";
371 status = "disabled";
372
373 hdmiphy: hdmiphy@38 {
374 compatible = "samsung,exynos4212-hdmiphy";
375 reg = <0x38>;
376 };
377 };
378
379 i2c_9: i2c@121d0000 {
380 compatible = "samsung,exynos5-sata-phy-i2c";
381 reg = <0x121D0000 0x100>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 clocks = <&clock CLK_SATA_PHYI2C>;
385 clock-names = "i2c";
386 status = "disabled";
387 };
388
389 spi_0: spi@12d20000 {
390 compatible = "samsung,exynos4210-spi";
391 status = "disabled";
392 reg = <0x12d20000 0x100>;
393 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
394 dmas = <&pdma0 5
395 &pdma0 4>;
396 dma-names = "tx", "rx";
397 #address-cells = <1>;
398 #size-cells = <0>;
399 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
400 clock-names = "spi", "spi_busclk0";
401 pinctrl-names = "default";
402 pinctrl-0 = <&spi0_bus>;
403 };
404
405 spi_1: spi@12d30000 {
406 compatible = "samsung,exynos4210-spi";
407 status = "disabled";
408 reg = <0x12d30000 0x100>;
409 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
410 dmas = <&pdma1 5
411 &pdma1 4>;
412 dma-names = "tx", "rx";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
416 clock-names = "spi", "spi_busclk0";
417 pinctrl-names = "default";
418 pinctrl-0 = <&spi1_bus>;
419 };
420
421 spi_2: spi@12d40000 {
422 compatible = "samsung,exynos4210-spi";
423 status = "disabled";
424 reg = <0x12d40000 0x100>;
425 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
426 dmas = <&pdma0 7
427 &pdma0 6>;
428 dma-names = "tx", "rx";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
432 clock-names = "spi", "spi_busclk0";
433 pinctrl-names = "default";
434 pinctrl-0 = <&spi2_bus>;
435 };
436
437 mmc_0: mmc@12200000 {
438 compatible = "samsung,exynos5250-dw-mshc";
439 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>;
441 #size-cells = <0>;
442 reg = <0x12200000 0x1000>;
443 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
444 clock-names = "biu", "ciu";
445 fifo-depth = <0x80>;
446 status = "disabled";
447 };
448
449 mmc_1: mmc@12210000 {
450 compatible = "samsung,exynos5250-dw-mshc";
451 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 reg = <0x12210000 0x1000>;
455 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
456 clock-names = "biu", "ciu";
457 fifo-depth = <0x80>;
458 status = "disabled";
459 };
460
461 mmc_2: mmc@12220000 {
462 compatible = "samsung,exynos5250-dw-mshc";
463 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 reg = <0x12220000 0x1000>;
467 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
468 clock-names = "biu", "ciu";
469 fifo-depth = <0x80>;
470 status = "disabled";
471 };
472
473 mmc_3: mmc@12230000 {
474 compatible = "samsung,exynos5250-dw-mshc";
475 reg = <0x12230000 0x1000>;
476 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
480 clock-names = "biu", "ciu";
481 fifo-depth = <0x80>;
482 status = "disabled";
483 };
484
485 i2s0: i2s@3830000 {
486 compatible = "samsung,s5pv210-i2s";
487 status = "disabled";
488 reg = <0x03830000 0x100>;
489 dmas = <&pdma0 10
490 &pdma0 9
491 &pdma0 8>;
492 dma-names = "tx", "rx", "tx-sec";
493 clocks = <&clock_audss EXYNOS_I2S_BUS>,
494 <&clock_audss EXYNOS_I2S_BUS>,
495 <&clock_audss EXYNOS_SCLK_I2S>;
496 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
497 samsung,idma-addr = <0x03000000>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&i2s0_bus>;
500 power-domains = <&pd_mau>;
501 #clock-cells = <1>;
502 #sound-dai-cells = <1>;
503 };
504
505 i2s1: i2s@12d60000 {
506 compatible = "samsung,s3c6410-i2s";
507 status = "disabled";
508 reg = <0x12D60000 0x100>;
509 dmas = <&pdma1 12
510 &pdma1 11>;
511 dma-names = "tx", "rx";
512 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
513 clock-names = "iis", "i2s_opclk0";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2s1_bus>;
516 power-domains = <&pd_mau>;
517 #sound-dai-cells = <1>;
518 };
519
520 i2s2: i2s@12d70000 {
521 compatible = "samsung,s3c6410-i2s";
522 status = "disabled";
523 reg = <0x12D70000 0x100>;
524 dmas = <&pdma0 12
525 &pdma0 11>;
526 dma-names = "tx", "rx";
527 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
528 clock-names = "iis", "i2s_opclk0";
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2s2_bus>;
531 power-domains = <&pd_mau>;
532 #sound-dai-cells = <1>;
533 };
534
535 usb_dwc3 {
536 compatible = "samsung,exynos5250-dwusb3";
537 clocks = <&clock CLK_USB3>;
538 clock-names = "usbdrd30";
539 #address-cells = <1>;
540 #size-cells = <1>;
541 ranges;
542
543 usbdrd_dwc3: dwc3@12000000 {
544 compatible = "synopsys,dwc3";
545 reg = <0x12000000 0x10000>;
546 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
547 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
548 phy-names = "usb2-phy", "usb3-phy";
549 };
550 };
551
552 usbdrd_phy: phy@12100000 {
553 compatible = "samsung,exynos5250-usbdrd-phy";
554 reg = <0x12100000 0x100>;
555 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
556 clock-names = "phy", "ref";
557 samsung,pmu-syscon = <&pmu_system_controller>;
558 #phy-cells = <1>;
559 };
560
561 ehci: usb@12110000 {
562 compatible = "samsung,exynos4210-ehci";
563 reg = <0x12110000 0x100>;
564 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
565
566 clocks = <&clock CLK_USB2>;
567 clock-names = "usbhost";
568 #address-cells = <1>;
569 #size-cells = <0>;
570 port@0 {
571 reg = <0>;
572 phys = <&usb2_phy_gen 1>;
573 };
574 };
575
576 ohci: usb@12120000 {
577 compatible = "samsung,exynos4210-ohci";
578 reg = <0x12120000 0x100>;
579 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
580
581 clocks = <&clock CLK_USB2>;
582 clock-names = "usbhost";
583 #address-cells = <1>;
584 #size-cells = <0>;
585 port@0 {
586 reg = <0>;
587 phys = <&usb2_phy_gen 1>;
588 };
589 };
590
591 usb2_phy_gen: phy@12130000 {
592 compatible = "samsung,exynos5250-usb2-phy";
593 reg = <0x12130000 0x100>;
594 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
595 clock-names = "phy", "ref";
596 #phy-cells = <1>;
597 samsung,sysreg-phandle = <&sysreg_system_controller>;
598 samsung,pmureg-phandle = <&pmu_system_controller>;
599 };
600
601 amba {
602 #address-cells = <1>;
603 #size-cells = <1>;
604 compatible = "simple-bus";
605 interrupt-parent = <&gic>;
606 ranges;
607
608 pdma0: pdma@121a0000 {
609 compatible = "arm,pl330", "arm,primecell";
610 reg = <0x121A0000 0x1000>;
611 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clock CLK_PDMA0>;
613 clock-names = "apb_pclk";
614 #dma-cells = <1>;
615 #dma-channels = <8>;
616 #dma-requests = <32>;
617 };
618
619 pdma1: pdma@121b0000 {
620 compatible = "arm,pl330", "arm,primecell";
621 reg = <0x121B0000 0x1000>;
622 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clock CLK_PDMA1>;
624 clock-names = "apb_pclk";
625 #dma-cells = <1>;
626 #dma-channels = <8>;
627 #dma-requests = <32>;
628 };
629
630 mdma0: mdma@10800000 {
631 compatible = "arm,pl330", "arm,primecell";
632 reg = <0x10800000 0x1000>;
633 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&clock CLK_MDMA0>;
635 clock-names = "apb_pclk";
636 #dma-cells = <1>;
637 #dma-channels = <8>;
638 #dma-requests = <1>;
639 };
640
641 mdma1: mdma@11c10000 {
642 compatible = "arm,pl330", "arm,primecell";
643 reg = <0x11C10000 0x1000>;
644 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clock CLK_MDMA1>;
646 clock-names = "apb_pclk";
647 #dma-cells = <1>;
648 #dma-channels = <8>;
649 #dma-requests = <1>;
650 };
651 };
652
653 gsc_0: gsc@13e00000 {
654 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
655 reg = <0x13e00000 0x1000>;
656 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
657 power-domains = <&pd_gsc>;
658 clocks = <&clock CLK_GSCL0>;
659 clock-names = "gscl";
660 iommus = <&sysmmu_gsc0>;
661 };
662
663 gsc_1: gsc@13e10000 {
664 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
665 reg = <0x13e10000 0x1000>;
666 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
667 power-domains = <&pd_gsc>;
668 clocks = <&clock CLK_GSCL1>;
669 clock-names = "gscl";
670 iommus = <&sysmmu_gsc1>;
671 };
672
673 gsc_2: gsc@13e20000 {
674 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
675 reg = <0x13e20000 0x1000>;
676 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
677 power-domains = <&pd_gsc>;
678 clocks = <&clock CLK_GSCL2>;
679 clock-names = "gscl";
680 iommus = <&sysmmu_gsc2>;
681 };
682
683 gsc_3: gsc@13e30000 {
684 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
685 reg = <0x13e30000 0x1000>;
686 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
687 power-domains = <&pd_gsc>;
688 clocks = <&clock CLK_GSCL3>;
689 clock-names = "gscl";
690 iommus = <&sysmmu_gsc3>;
691 };
692
693 hdmi: hdmi@14530000 {
694 compatible = "samsung,exynos4212-hdmi";
695 reg = <0x14530000 0x70000>;
696 power-domains = <&pd_disp1>;
697 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
699 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
700 <&clock CLK_MOUT_HDMI>;
701 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
702 "sclk_hdmiphy", "mout_hdmi";
703 samsung,syscon-phandle = <&pmu_system_controller>;
704 phy = <&hdmiphy>;
705 #sound-dai-cells = <0>;
706 status = "disabled";
707 };
708
709 hdmicec: cec@101b0000 {
710 compatible = "samsung,s5p-cec";
711 reg = <0x101B0000 0x200>;
712 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clock CLK_HDMI_CEC>;
714 clock-names = "hdmicec";
715 samsung,syscon-phandle = <&pmu_system_controller>;
716 hdmi-phandle = <&hdmi>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&hdmi_cec>;
719 status = "disabled";
720 };
721
722 mixer: mixer@14450000 {
723 compatible = "samsung,exynos5250-mixer";
724 reg = <0x14450000 0x10000>;
725 power-domains = <&pd_disp1>;
726 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
728 <&clock CLK_SCLK_HDMI>;
729 clock-names = "mixer", "hdmi", "sclk_hdmi";
730 iommus = <&sysmmu_tv>;
731 status = "disabled";
732 };
733
734 dp_phy: video-phy {
735 compatible = "samsung,exynos5250-dp-video-phy";
736 samsung,pmu-syscon = <&pmu_system_controller>;
737 #phy-cells = <0>;
738 };
739
740 adc: adc@12d10000 {
741 compatible = "samsung,exynos-adc-v1";
742 reg = <0x12D10000 0x100>;
743 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clock CLK_ADC>;
745 clock-names = "adc";
746 #io-channel-cells = <1>;
747 io-channel-ranges;
748 samsung,syscon-phandle = <&pmu_system_controller>;
749 status = "disabled";
750 };
751
752 sysmmu_g2d: sysmmu@10a60000 {
753 compatible = "samsung,exynos-sysmmu";
754 reg = <0x10A60000 0x1000>;
755 interrupt-parent = <&combiner>;
756 interrupts = <24 5>;
757 clock-names = "sysmmu", "master";
758 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
759 #iommu-cells = <0>;
760 };
761
762 sysmmu_mfc_r: sysmmu@11200000 {
763 compatible = "samsung,exynos-sysmmu";
764 reg = <0x11200000 0x1000>;
765 interrupt-parent = <&combiner>;
766 interrupts = <6 2>;
767 power-domains = <&pd_mfc>;
768 clock-names = "sysmmu", "master";
769 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
770 #iommu-cells = <0>;
771 };
772
773 sysmmu_mfc_l: sysmmu@11210000 {
774 compatible = "samsung,exynos-sysmmu";
775 reg = <0x11210000 0x1000>;
776 interrupt-parent = <&combiner>;
777 interrupts = <8 5>;
778 power-domains = <&pd_mfc>;
779 clock-names = "sysmmu", "master";
780 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
781 #iommu-cells = <0>;
782 };
783
784 sysmmu_rotator: sysmmu@11d40000 {
785 compatible = "samsung,exynos-sysmmu";
786 reg = <0x11D40000 0x1000>;
787 interrupt-parent = <&combiner>;
788 interrupts = <4 0>;
789 clock-names = "sysmmu", "master";
790 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
791 #iommu-cells = <0>;
792 };
793
794 sysmmu_jpeg: sysmmu@11f20000 {
795 compatible = "samsung,exynos-sysmmu";
796 reg = <0x11F20000 0x1000>;
797 interrupt-parent = <&combiner>;
798 interrupts = <4 2>;
799 power-domains = <&pd_gsc>;
800 clock-names = "sysmmu", "master";
801 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
802 #iommu-cells = <0>;
803 };
804
805 sysmmu_fimc_isp: sysmmu@13260000 {
806 compatible = "samsung,exynos-sysmmu";
807 reg = <0x13260000 0x1000>;
808 interrupt-parent = <&combiner>;
809 interrupts = <10 6>;
810 clock-names = "sysmmu";
811 clocks = <&clock CLK_SMMU_FIMC_ISP>;
812 #iommu-cells = <0>;
813 };
814
815 sysmmu_fimc_drc: sysmmu@13270000 {
816 compatible = "samsung,exynos-sysmmu";
817 reg = <0x13270000 0x1000>;
818 interrupt-parent = <&combiner>;
819 interrupts = <11 6>;
820 clock-names = "sysmmu";
821 clocks = <&clock CLK_SMMU_FIMC_DRC>;
822 #iommu-cells = <0>;
823 };
824
825 sysmmu_fimc_fd: sysmmu@132a0000 {
826 compatible = "samsung,exynos-sysmmu";
827 reg = <0x132A0000 0x1000>;
828 interrupt-parent = <&combiner>;
829 interrupts = <5 0>;
830 clock-names = "sysmmu";
831 clocks = <&clock CLK_SMMU_FIMC_FD>;
832 #iommu-cells = <0>;
833 };
834
835 sysmmu_fimc_scc: sysmmu@13280000 {
836 compatible = "samsung,exynos-sysmmu";
837 reg = <0x13280000 0x1000>;
838 interrupt-parent = <&combiner>;
839 interrupts = <5 2>;
840 clock-names = "sysmmu";
841 clocks = <&clock CLK_SMMU_FIMC_SCC>;
842 #iommu-cells = <0>;
843 };
844
845 sysmmu_fimc_scp: sysmmu@13290000 {
846 compatible = "samsung,exynos-sysmmu";
847 reg = <0x13290000 0x1000>;
848 interrupt-parent = <&combiner>;
849 interrupts = <3 6>;
850 clock-names = "sysmmu";
851 clocks = <&clock CLK_SMMU_FIMC_SCP>;
852 #iommu-cells = <0>;
853 };
854
855 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
856 compatible = "samsung,exynos-sysmmu";
857 reg = <0x132B0000 0x1000>;
858 interrupt-parent = <&combiner>;
859 interrupts = <5 4>;
860 clock-names = "sysmmu";
861 clocks = <&clock CLK_SMMU_FIMC_MCU>;
862 #iommu-cells = <0>;
863 };
864
865 sysmmu_fimc_odc: sysmmu@132c0000 {
866 compatible = "samsung,exynos-sysmmu";
867 reg = <0x132C0000 0x1000>;
868 interrupt-parent = <&combiner>;
869 interrupts = <11 0>;
870 clock-names = "sysmmu";
871 clocks = <&clock CLK_SMMU_FIMC_ODC>;
872 #iommu-cells = <0>;
873 };
874
875 sysmmu_fimc_dis0: sysmmu@132d0000 {
876 compatible = "samsung,exynos-sysmmu";
877 reg = <0x132D0000 0x1000>;
878 interrupt-parent = <&combiner>;
879 interrupts = <10 4>;
880 clock-names = "sysmmu";
881 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
882 #iommu-cells = <0>;
883 };
884
885 sysmmu_fimc_dis1: sysmmu@132E0000{
886 compatible = "samsung,exynos-sysmmu";
887 reg = <0x132E0000 0x1000>;
888 interrupt-parent = <&combiner>;
889 interrupts = <9 4>;
890 clock-names = "sysmmu";
891 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
892 #iommu-cells = <0>;
893 };
894
895 sysmmu_fimc_3dnr: sysmmu@132f0000 {
896 compatible = "samsung,exynos-sysmmu";
897 reg = <0x132F0000 0x1000>;
898 interrupt-parent = <&combiner>;
899 interrupts = <5 6>;
900 clock-names = "sysmmu";
901 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
902 #iommu-cells = <0>;
903 };
904
905 sysmmu_fimc_lite0: sysmmu@13c40000 {
906 compatible = "samsung,exynos-sysmmu";
907 reg = <0x13C40000 0x1000>;
908 interrupt-parent = <&combiner>;
909 interrupts = <3 4>;
910 power-domains = <&pd_gsc>;
911 clock-names = "sysmmu", "master";
912 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
913 #iommu-cells = <0>;
914 };
915
916 sysmmu_fimc_lite1: sysmmu@13c50000 {
917 compatible = "samsung,exynos-sysmmu";
918 reg = <0x13C50000 0x1000>;
919 interrupt-parent = <&combiner>;
920 interrupts = <24 1>;
921 power-domains = <&pd_gsc>;
922 clock-names = "sysmmu", "master";
923 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
924 #iommu-cells = <0>;
925 };
926
927 sysmmu_gsc0: sysmmu@13e80000 {
928 compatible = "samsung,exynos-sysmmu";
929 reg = <0x13E80000 0x1000>;
930 interrupt-parent = <&combiner>;
931 interrupts = <2 0>;
932 power-domains = <&pd_gsc>;
933 clock-names = "sysmmu", "master";
934 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
935 #iommu-cells = <0>;
936 };
937
938 sysmmu_gsc1: sysmmu@13e90000 {
939 compatible = "samsung,exynos-sysmmu";
940 reg = <0x13E90000 0x1000>;
941 interrupt-parent = <&combiner>;
942 interrupts = <2 2>;
943 power-domains = <&pd_gsc>;
944 clock-names = "sysmmu", "master";
945 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
946 #iommu-cells = <0>;
947 };
948
949 sysmmu_gsc2: sysmmu@13ea0000 {
950 compatible = "samsung,exynos-sysmmu";
951 reg = <0x13EA0000 0x1000>;
952 interrupt-parent = <&combiner>;
953 interrupts = <2 4>;
954 power-domains = <&pd_gsc>;
955 clock-names = "sysmmu", "master";
956 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
957 #iommu-cells = <0>;
958 };
959
960 sysmmu_gsc3: sysmmu@13eb0000 {
961 compatible = "samsung,exynos-sysmmu";
962 reg = <0x13EB0000 0x1000>;
963 interrupt-parent = <&combiner>;
964 interrupts = <2 6>;
965 power-domains = <&pd_gsc>;
966 clock-names = "sysmmu", "master";
967 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
968 #iommu-cells = <0>;
969 };
970
971 sysmmu_fimd1: sysmmu@14640000 {
972 compatible = "samsung,exynos-sysmmu";
973 reg = <0x14640000 0x1000>;
974 interrupt-parent = <&combiner>;
975 interrupts = <3 2>;
976 power-domains = <&pd_disp1>;
977 clock-names = "sysmmu", "master";
978 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
979 #iommu-cells = <0>;
980 };
981
982 sysmmu_tv: sysmmu@14650000 {
983 compatible = "samsung,exynos-sysmmu";
984 reg = <0x14650000 0x1000>;
985 interrupt-parent = <&combiner>;
986 interrupts = <7 4>;
987 power-domains = <&pd_disp1>;
988 clock-names = "sysmmu", "master";
989 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
990 #iommu-cells = <0>;
991 };
992 };
993
994 thermal-zones {
995 cpu_thermal: cpu-thermal {
996 polling-delay-passive = <0>;
997 polling-delay = <0>;
998 thermal-sensors = <&tmu 0>;
999
1000 cooling-maps {
1001 map0 {
1002 /* Corresponds to 800MHz at freq_table */
1003 cooling-device = <&cpu0 9 9>;
1004 };
1005 map1 {
1006 /* Corresponds to 200MHz at freq_table */
1007 cooling-device = <&cpu0 15 15>;
1008 };
1009 };
1010 };
1011 };
1012};
1013
1014&dp {
1015 power-domains = <&pd_disp1>;
1016 clocks = <&clock CLK_DP>;
1017 clock-names = "dp";
1018 phys = <&dp_phy>;
1019 phy-names = "dp";
1020};
1021
1022&fimd {
1023 power-domains = <&pd_disp1>;
1024 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1025 clock-names = "sclk_fimd", "fimd";
1026 iommus = <&sysmmu_fimd1>;
1027};
1028
1029&g2d {
1030 iommus = <&sysmmu_g2d>;
1031 clocks = <&clock CLK_G2D>;
1032 clock-names = "fimg2d";
1033 status = "okay";
1034};
1035
1036&i2c_0 {
1037 clocks = <&clock CLK_I2C0>;
1038 clock-names = "i2c";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&i2c0_bus>;
1041};
1042
1043&i2c_1 {
1044 clocks = <&clock CLK_I2C1>;
1045 clock-names = "i2c";
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&i2c1_bus>;
1048};
1049
1050&i2c_2 {
1051 clocks = <&clock CLK_I2C2>;
1052 clock-names = "i2c";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&i2c2_bus>;
1055};
1056
1057&i2c_3 {
1058 clocks = <&clock CLK_I2C3>;
1059 clock-names = "i2c";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&i2c3_bus>;
1062};
1063
1064&prng {
1065 clocks = <&clock CLK_SSS>;
1066 clock-names = "secss";
1067};
1068
1069&pwm {
1070 clocks = <&clock CLK_PWM>;
1071 clock-names = "timers";
1072};
1073
1074&rtc {
1075 clocks = <&clock CLK_RTC>;
1076 clock-names = "rtc";
1077 interrupt-parent = <&pmu_system_controller>;
1078 status = "disabled";
1079};
1080
1081&serial_0 {
1082 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1083 clock-names = "uart", "clk_uart_baud0";
1084 dmas = <&pdma0 13>, <&pdma0 14>;
1085 dma-names = "rx", "tx";
1086};
1087
1088&serial_1 {
1089 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1090 clock-names = "uart", "clk_uart_baud0";
1091 dmas = <&pdma1 15>, <&pdma1 16>;
1092 dma-names = "rx", "tx";
1093};
1094
1095&serial_2 {
1096 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1097 clock-names = "uart", "clk_uart_baud0";
1098 dmas = <&pdma0 15>, <&pdma0 16>;
1099 dma-names = "rx", "tx";
1100};
1101
1102&serial_3 {
1103 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1104 clock-names = "uart", "clk_uart_baud0";
1105 dmas = <&pdma1 17>, <&pdma1 18>;
1106 dma-names = "rx", "tx";
1107};
1108
1109&sss {
1110 clocks = <&clock CLK_SSS>;
1111 clock-names = "secss";
1112};
1113
1114&trng {
1115 clocks = <&clock CLK_SSS>;
1116 clock-names = "secss";
1117};
1118
1119#include "exynos5250-pinctrl.dtsi"
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos5250 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include this file and provide
10 * values for board specfic bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
14 * additional nodes can be added to this file.
15 */
16
17#include <dt-bindings/clock/exynos5250.h>
18#include "exynos5.dtsi"
19#include "exynos4-cpu-thermal.dtsi"
20#include <dt-bindings/clock/exynos-audss-clk.h>
21
22/ {
23 compatible = "samsung,exynos5250", "samsung,exynos5";
24
25 aliases {
26 spi0 = &spi_0;
27 spi1 = &spi_1;
28 spi2 = &spi_2;
29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3;
33 mshc0 = &mmc_0;
34 mshc1 = &mmc_1;
35 mshc2 = &mmc_2;
36 mshc3 = &mmc_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 i2c9 = &i2c_9;
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a15";
56 reg = <0>;
57 clocks = <&clock CLK_ARM_CLK>;
58 clock-names = "cpu";
59 operating-points-v2 = <&cpu0_opp_table>;
60 #cooling-cells = <2>; /* min followed by max */
61 };
62 cpu1: cpu@1 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a15";
65 reg = <1>;
66 clocks = <&clock CLK_ARM_CLK>;
67 clock-names = "cpu";
68 operating-points-v2 = <&cpu0_opp_table>;
69 #cooling-cells = <2>; /* min followed by max */
70 };
71 };
72
73 cpu0_opp_table: opp_table0 {
74 compatible = "operating-points-v2";
75 opp-shared;
76
77 opp-200000000 {
78 opp-hz = /bits/ 64 <200000000>;
79 opp-microvolt = <925000>;
80 clock-latency-ns = <140000>;
81 };
82 opp-300000000 {
83 opp-hz = /bits/ 64 <300000000>;
84 opp-microvolt = <937500>;
85 clock-latency-ns = <140000>;
86 };
87 opp-400000000 {
88 opp-hz = /bits/ 64 <400000000>;
89 opp-microvolt = <950000>;
90 clock-latency-ns = <140000>;
91 };
92 opp-500000000 {
93 opp-hz = /bits/ 64 <500000000>;
94 opp-microvolt = <975000>;
95 clock-latency-ns = <140000>;
96 };
97 opp-600000000 {
98 opp-hz = /bits/ 64 <600000000>;
99 opp-microvolt = <1000000>;
100 clock-latency-ns = <140000>;
101 };
102 opp-700000000 {
103 opp-hz = /bits/ 64 <700000000>;
104 opp-microvolt = <1012500>;
105 clock-latency-ns = <140000>;
106 };
107 opp-800000000 {
108 opp-hz = /bits/ 64 <800000000>;
109 opp-microvolt = <1025000>;
110 clock-latency-ns = <140000>;
111 };
112 opp-900000000 {
113 opp-hz = /bits/ 64 <900000000>;
114 opp-microvolt = <1050000>;
115 clock-latency-ns = <140000>;
116 };
117 opp-1000000000 {
118 opp-hz = /bits/ 64 <1000000000>;
119 opp-microvolt = <1075000>;
120 clock-latency-ns = <140000>;
121 opp-suspend;
122 };
123 opp-1100000000 {
124 opp-hz = /bits/ 64 <1100000000>;
125 opp-microvolt = <1100000>;
126 clock-latency-ns = <140000>;
127 };
128 opp-1200000000 {
129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <1125000>;
131 clock-latency-ns = <140000>;
132 };
133 opp-1300000000 {
134 opp-hz = /bits/ 64 <1300000000>;
135 opp-microvolt = <1150000>;
136 clock-latency-ns = <140000>;
137 };
138 opp-1400000000 {
139 opp-hz = /bits/ 64 <1400000000>;
140 opp-microvolt = <1200000>;
141 clock-latency-ns = <140000>;
142 };
143 opp-1500000000 {
144 opp-hz = /bits/ 64 <1500000000>;
145 opp-microvolt = <1225000>;
146 clock-latency-ns = <140000>;
147 };
148 opp-1600000000 {
149 opp-hz = /bits/ 64 <1600000000>;
150 opp-microvolt = <1250000>;
151 clock-latency-ns = <140000>;
152 };
153 opp-1700000000 {
154 opp-hz = /bits/ 64 <1700000000>;
155 opp-microvolt = <1300000>;
156 clock-latency-ns = <140000>;
157 };
158 };
159
160 pmu {
161 compatible = "arm,cortex-a15-pmu";
162 interrupt-parent = <&combiner>;
163 interrupts = <1 2>, <22 4>;
164 };
165
166 soc: soc {
167 sram@2020000 {
168 compatible = "mmio-sram";
169 reg = <0x02020000 0x30000>;
170 #address-cells = <1>;
171 #size-cells = <1>;
172 ranges = <0 0x02020000 0x30000>;
173
174 smp-sram@0 {
175 compatible = "samsung,exynos4210-sysram";
176 reg = <0x0 0x1000>;
177 };
178
179 smp-sram@2f000 {
180 compatible = "samsung,exynos4210-sysram-ns";
181 reg = <0x2f000 0x1000>;
182 };
183 };
184
185 pd_gsc: power-domain@10044000 {
186 compatible = "samsung,exynos4210-pd";
187 reg = <0x10044000 0x20>;
188 #power-domain-cells = <0>;
189 label = "GSC";
190 };
191
192 pd_mfc: power-domain@10044040 {
193 compatible = "samsung,exynos4210-pd";
194 reg = <0x10044040 0x20>;
195 #power-domain-cells = <0>;
196 label = "MFC";
197 };
198
199 pd_g3d: power-domain@10044060 {
200 compatible = "samsung,exynos4210-pd";
201 reg = <0x10044060 0x20>;
202 #power-domain-cells = <0>;
203 label = "G3D";
204 };
205
206 pd_disp1: power-domain@100440a0 {
207 compatible = "samsung,exynos4210-pd";
208 reg = <0x100440A0 0x20>;
209 #power-domain-cells = <0>;
210 label = "DISP1";
211 };
212
213 pd_mau: power-domain@100440c0 {
214 compatible = "samsung,exynos4210-pd";
215 reg = <0x100440C0 0x20>;
216 #power-domain-cells = <0>;
217 label = "MAU";
218 };
219
220 clock: clock-controller@10010000 {
221 compatible = "samsung,exynos5250-clock";
222 reg = <0x10010000 0x30000>;
223 #clock-cells = <1>;
224 };
225
226 clock_audss: audss-clock-controller@3810000 {
227 compatible = "samsung,exynos5250-audss-clock";
228 reg = <0x03810000 0x0C>;
229 #clock-cells = <1>;
230 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
231 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
232 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
233 power-domains = <&pd_mau>;
234 };
235
236 timer@101c0000 {
237 compatible = "samsung,exynos4210-mct";
238 reg = <0x101C0000 0x800>;
239 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
240 clock-names = "fin_pll", "mct";
241 interrupts-extended = <&combiner 23 3>,
242 <&combiner 23 4>,
243 <&combiner 25 2>,
244 <&combiner 25 3>,
245 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
246 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
247 };
248
249 pinctrl_0: pinctrl@11400000 {
250 compatible = "samsung,exynos5250-pinctrl";
251 reg = <0x11400000 0x1000>;
252 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
253
254 wakup_eint: wakeup-interrupt-controller {
255 compatible = "samsung,exynos4210-wakeup-eint";
256 interrupt-parent = <&gic>;
257 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
258 };
259 };
260
261 pinctrl_1: pinctrl@13400000 {
262 compatible = "samsung,exynos5250-pinctrl";
263 reg = <0x13400000 0x1000>;
264 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
265 };
266
267 pinctrl_2: pinctrl@10d10000 {
268 compatible = "samsung,exynos5250-pinctrl";
269 reg = <0x10d10000 0x1000>;
270 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
271 };
272
273 pinctrl_3: pinctrl@3860000 {
274 compatible = "samsung,exynos5250-pinctrl";
275 reg = <0x03860000 0x1000>;
276 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
277 power-domains = <&pd_mau>;
278 };
279
280 pmu_system_controller: system-controller@10040000 {
281 compatible = "samsung,exynos5250-pmu", "syscon";
282 reg = <0x10040000 0x5000>;
283 clock-names = "clkout16";
284 clocks = <&clock CLK_FIN_PLL>;
285 #clock-cells = <1>;
286 interrupt-controller;
287 #interrupt-cells = <3>;
288 interrupt-parent = <&gic>;
289 };
290
291 watchdog@101d0000 {
292 compatible = "samsung,exynos5250-wdt";
293 reg = <0x101D0000 0x100>;
294 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clock CLK_WDT>;
296 clock-names = "watchdog";
297 samsung,syscon-phandle = <&pmu_system_controller>;
298 };
299
300 mfc: codec@11000000 {
301 compatible = "samsung,mfc-v6";
302 reg = <0x11000000 0x10000>;
303 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
304 power-domains = <&pd_mfc>;
305 clocks = <&clock CLK_MFC>;
306 clock-names = "mfc";
307 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
308 iommu-names = "left", "right";
309 };
310
311 rotator: rotator@11c00000 {
312 compatible = "samsung,exynos5250-rotator";
313 reg = <0x11C00000 0x64>;
314 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clock CLK_ROTATOR>;
316 clock-names = "rotator";
317 iommus = <&sysmmu_rotator>;
318 };
319
320 mali: gpu@11800000 {
321 compatible = "samsung,exynos5250-mali", "arm,mali-t604";
322 reg = <0x11800000 0x5000>;
323 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
326 interrupt-names = "job", "mmu", "gpu";
327 clocks = <&clock CLK_G3D>;
328 clock-names = "core";
329 operating-points-v2 = <&gpu_opp_table>;
330 power-domains = <&pd_g3d>;
331 status = "disabled";
332
333 gpu_opp_table: gpu-opp-table {
334 compatible = "operating-points-v2";
335
336 opp-100000000 {
337 opp-hz = /bits/ 64 <100000000>;
338 opp-microvolt = <925000>;
339 };
340 opp-160000000 {
341 opp-hz = /bits/ 64 <160000000>;
342 opp-microvolt = <925000>;
343 };
344 opp-266000000 {
345 opp-hz = /bits/ 64 <266000000>;
346 opp-microvolt = <1025000>;
347 };
348 opp-350000000 {
349 opp-hz = /bits/ 64 <350000000>;
350 opp-microvolt = <1075000>;
351 };
352 opp-400000000 {
353 opp-hz = /bits/ 64 <400000000>;
354 opp-microvolt = <1125000>;
355 };
356 opp-450000000 {
357 opp-hz = /bits/ 64 <450000000>;
358 opp-microvolt = <1150000>;
359 };
360 opp-533000000 {
361 opp-hz = /bits/ 64 <533000000>;
362 opp-microvolt = <1250000>;
363 };
364 };
365 };
366
367 tmu: tmu@10060000 {
368 compatible = "samsung,exynos5250-tmu";
369 reg = <0x10060000 0x100>;
370 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clock CLK_TMU>;
372 clock-names = "tmu_apbif";
373 #thermal-sensor-cells = <0>;
374 };
375
376 sata: sata@122f0000 {
377 compatible = "snps,dwc-ahci";
378 samsung,sata-freq = <66>;
379 reg = <0x122F0000 0x1ff>;
380 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
382 clock-names = "sata", "sclk_sata";
383 phys = <&sata_phy>;
384 phy-names = "sata-phy";
385 ports-implemented = <0x1>;
386 status = "disabled";
387 };
388
389 sata_phy: sata-phy@12170000 {
390 compatible = "samsung,exynos5250-sata-phy";
391 reg = <0x12170000 0x1ff>;
392 clocks = <&clock CLK_SATA_PHYCTRL>;
393 clock-names = "sata_phyctrl";
394 #phy-cells = <0>;
395 samsung,syscon-phandle = <&pmu_system_controller>;
396 status = "disabled";
397 };
398
399 /* i2c_0-3 are defined in exynos5.dtsi */
400 i2c_4: i2c@12ca0000 {
401 compatible = "samsung,s3c2440-i2c";
402 reg = <0x12CA0000 0x100>;
403 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
405 #size-cells = <0>;
406 clocks = <&clock CLK_I2C4>;
407 clock-names = "i2c";
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c4_bus>;
410 status = "disabled";
411 };
412
413 i2c_5: i2c@12cb0000 {
414 compatible = "samsung,s3c2440-i2c";
415 reg = <0x12CB0000 0x100>;
416 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 clocks = <&clock CLK_I2C5>;
420 clock-names = "i2c";
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c5_bus>;
423 status = "disabled";
424 };
425
426 i2c_6: i2c@12cc0000 {
427 compatible = "samsung,s3c2440-i2c";
428 reg = <0x12CC0000 0x100>;
429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 clocks = <&clock CLK_I2C6>;
433 clock-names = "i2c";
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c6_bus>;
436 status = "disabled";
437 };
438
439 i2c_7: i2c@12cd0000 {
440 compatible = "samsung,s3c2440-i2c";
441 reg = <0x12CD0000 0x100>;
442 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 clocks = <&clock CLK_I2C7>;
446 clock-names = "i2c";
447 pinctrl-names = "default";
448 pinctrl-0 = <&i2c7_bus>;
449 status = "disabled";
450 };
451
452 i2c_8: i2c@12ce0000 {
453 compatible = "samsung,s3c2440-hdmiphy-i2c";
454 reg = <0x12CE0000 0x1000>;
455 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 clocks = <&clock CLK_I2C_HDMI>;
459 clock-names = "i2c";
460 status = "disabled";
461
462 hdmiphy: hdmiphy@38 {
463 compatible = "samsung,exynos4212-hdmiphy";
464 reg = <0x38>;
465 };
466 };
467
468 i2c_9: i2c@121d0000 {
469 compatible = "samsung,exynos5-sata-phy-i2c";
470 reg = <0x121D0000 0x100>;
471 #address-cells = <1>;
472 #size-cells = <0>;
473 clocks = <&clock CLK_SATA_PHYI2C>;
474 clock-names = "i2c";
475 status = "disabled";
476 };
477
478 spi_0: spi@12d20000 {
479 compatible = "samsung,exynos4210-spi";
480 status = "disabled";
481 reg = <0x12d20000 0x100>;
482 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
483 dmas = <&pdma0 5
484 &pdma0 4>;
485 dma-names = "tx", "rx";
486 #address-cells = <1>;
487 #size-cells = <0>;
488 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
489 clock-names = "spi", "spi_busclk0";
490 pinctrl-names = "default";
491 pinctrl-0 = <&spi0_bus>;
492 };
493
494 spi_1: spi@12d30000 {
495 compatible = "samsung,exynos4210-spi";
496 status = "disabled";
497 reg = <0x12d30000 0x100>;
498 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
499 dmas = <&pdma1 5
500 &pdma1 4>;
501 dma-names = "tx", "rx";
502 #address-cells = <1>;
503 #size-cells = <0>;
504 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
505 clock-names = "spi", "spi_busclk0";
506 pinctrl-names = "default";
507 pinctrl-0 = <&spi1_bus>;
508 };
509
510 spi_2: spi@12d40000 {
511 compatible = "samsung,exynos4210-spi";
512 status = "disabled";
513 reg = <0x12d40000 0x100>;
514 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
515 dmas = <&pdma0 7
516 &pdma0 6>;
517 dma-names = "tx", "rx";
518 #address-cells = <1>;
519 #size-cells = <0>;
520 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
521 clock-names = "spi", "spi_busclk0";
522 pinctrl-names = "default";
523 pinctrl-0 = <&spi2_bus>;
524 };
525
526 mmc_0: mmc@12200000 {
527 compatible = "samsung,exynos5250-dw-mshc";
528 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
529 #address-cells = <1>;
530 #size-cells = <0>;
531 reg = <0x12200000 0x1000>;
532 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
533 clock-names = "biu", "ciu";
534 fifo-depth = <0x80>;
535 status = "disabled";
536 };
537
538 mmc_1: mmc@12210000 {
539 compatible = "samsung,exynos5250-dw-mshc";
540 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 reg = <0x12210000 0x1000>;
544 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
545 clock-names = "biu", "ciu";
546 fifo-depth = <0x80>;
547 status = "disabled";
548 };
549
550 mmc_2: mmc@12220000 {
551 compatible = "samsung,exynos5250-dw-mshc";
552 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 reg = <0x12220000 0x1000>;
556 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
557 clock-names = "biu", "ciu";
558 fifo-depth = <0x80>;
559 status = "disabled";
560 };
561
562 mmc_3: mmc@12230000 {
563 compatible = "samsung,exynos5250-dw-mshc";
564 reg = <0x12230000 0x1000>;
565 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
569 clock-names = "biu", "ciu";
570 fifo-depth = <0x80>;
571 status = "disabled";
572 };
573
574 i2s0: i2s@3830000 {
575 compatible = "samsung,s5pv210-i2s";
576 status = "disabled";
577 reg = <0x03830000 0x100>;
578 dmas = <&pdma0 10>,
579 <&pdma0 9>,
580 <&pdma0 8>;
581 dma-names = "tx", "rx", "tx-sec";
582 clocks = <&clock_audss EXYNOS_I2S_BUS>,
583 <&clock_audss EXYNOS_I2S_BUS>,
584 <&clock_audss EXYNOS_SCLK_I2S>;
585 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
586 samsung,idma-addr = <0x03000000>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&i2s0_bus>;
589 power-domains = <&pd_mau>;
590 #clock-cells = <1>;
591 #sound-dai-cells = <1>;
592 };
593
594 i2s1: i2s@12d60000 {
595 compatible = "samsung,s3c6410-i2s";
596 status = "disabled";
597 reg = <0x12D60000 0x100>;
598 dmas = <&pdma1 12>,
599 <&pdma1 11>;
600 dma-names = "tx", "rx";
601 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
602 clock-names = "iis", "i2s_opclk0";
603 pinctrl-names = "default";
604 pinctrl-0 = <&i2s1_bus>;
605 power-domains = <&pd_mau>;
606 #sound-dai-cells = <1>;
607 };
608
609 i2s2: i2s@12d70000 {
610 compatible = "samsung,s3c6410-i2s";
611 status = "disabled";
612 reg = <0x12D70000 0x100>;
613 dmas = <&pdma0 12>,
614 <&pdma0 11>;
615 dma-names = "tx", "rx";
616 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
617 clock-names = "iis", "i2s_opclk0";
618 pinctrl-names = "default";
619 pinctrl-0 = <&i2s2_bus>;
620 power-domains = <&pd_mau>;
621 #sound-dai-cells = <1>;
622 };
623
624 usb_dwc3 {
625 compatible = "samsung,exynos5250-dwusb3";
626 clocks = <&clock CLK_USB3>;
627 clock-names = "usbdrd30";
628 #address-cells = <1>;
629 #size-cells = <1>;
630 ranges;
631
632 usbdrd_dwc3: dwc3@12000000 {
633 compatible = "synopsys,dwc3";
634 reg = <0x12000000 0x10000>;
635 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
636 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
637 phy-names = "usb2-phy", "usb3-phy";
638 };
639 };
640
641 usbdrd_phy: phy@12100000 {
642 compatible = "samsung,exynos5250-usbdrd-phy";
643 reg = <0x12100000 0x100>;
644 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
645 clock-names = "phy", "ref";
646 samsung,pmu-syscon = <&pmu_system_controller>;
647 #phy-cells = <1>;
648 };
649
650 ehci: usb@12110000 {
651 compatible = "samsung,exynos4210-ehci";
652 reg = <0x12110000 0x100>;
653 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
654
655 clocks = <&clock CLK_USB2>;
656 clock-names = "usbhost";
657 phys = <&usb2_phy_gen 1>;
658 phy-names = "host";
659 };
660
661 ohci: usb@12120000 {
662 compatible = "samsung,exynos4210-ohci";
663 reg = <0x12120000 0x100>;
664 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
665
666 clocks = <&clock CLK_USB2>;
667 clock-names = "usbhost";
668 phys = <&usb2_phy_gen 1>;
669 phy-names = "host";
670 };
671
672 usb2_phy_gen: phy@12130000 {
673 compatible = "samsung,exynos5250-usb2-phy";
674 reg = <0x12130000 0x100>;
675 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
676 clock-names = "phy", "ref";
677 #phy-cells = <1>;
678 samsung,sysreg-phandle = <&sysreg_system_controller>;
679 samsung,pmureg-phandle = <&pmu_system_controller>;
680 };
681
682 pdma0: pdma@121a0000 {
683 compatible = "arm,pl330", "arm,primecell";
684 reg = <0x121A0000 0x1000>;
685 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&clock CLK_PDMA0>;
687 clock-names = "apb_pclk";
688 #dma-cells = <1>;
689 #dma-channels = <8>;
690 #dma-requests = <32>;
691 };
692
693 pdma1: pdma@121b0000 {
694 compatible = "arm,pl330", "arm,primecell";
695 reg = <0x121B0000 0x1000>;
696 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&clock CLK_PDMA1>;
698 clock-names = "apb_pclk";
699 #dma-cells = <1>;
700 #dma-channels = <8>;
701 #dma-requests = <32>;
702 };
703
704 mdma0: mdma@10800000 {
705 compatible = "arm,pl330", "arm,primecell";
706 reg = <0x10800000 0x1000>;
707 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&clock CLK_MDMA0>;
709 clock-names = "apb_pclk";
710 #dma-cells = <1>;
711 #dma-channels = <8>;
712 #dma-requests = <1>;
713 };
714
715 mdma1: mdma@11c10000 {
716 compatible = "arm,pl330", "arm,primecell";
717 reg = <0x11C10000 0x1000>;
718 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&clock CLK_MDMA1>;
720 clock-names = "apb_pclk";
721 #dma-cells = <1>;
722 #dma-channels = <8>;
723 #dma-requests = <1>;
724 };
725
726 gsc_0: gsc@13e00000 {
727 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
728 reg = <0x13e00000 0x1000>;
729 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
730 power-domains = <&pd_gsc>;
731 clocks = <&clock CLK_GSCL0>;
732 clock-names = "gscl";
733 iommus = <&sysmmu_gsc0>;
734 };
735
736 gsc_1: gsc@13e10000 {
737 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
738 reg = <0x13e10000 0x1000>;
739 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
740 power-domains = <&pd_gsc>;
741 clocks = <&clock CLK_GSCL1>;
742 clock-names = "gscl";
743 iommus = <&sysmmu_gsc1>;
744 };
745
746 gsc_2: gsc@13e20000 {
747 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
748 reg = <0x13e20000 0x1000>;
749 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
750 power-domains = <&pd_gsc>;
751 clocks = <&clock CLK_GSCL2>;
752 clock-names = "gscl";
753 iommus = <&sysmmu_gsc2>;
754 };
755
756 gsc_3: gsc@13e30000 {
757 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
758 reg = <0x13e30000 0x1000>;
759 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
760 power-domains = <&pd_gsc>;
761 clocks = <&clock CLK_GSCL3>;
762 clock-names = "gscl";
763 iommus = <&sysmmu_gsc3>;
764 };
765
766 hdmi: hdmi@14530000 {
767 compatible = "samsung,exynos4212-hdmi";
768 reg = <0x14530000 0x70000>;
769 power-domains = <&pd_disp1>;
770 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
771 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
772 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
773 <&clock CLK_MOUT_HDMI>;
774 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
775 "sclk_hdmiphy", "mout_hdmi";
776 samsung,syscon-phandle = <&pmu_system_controller>;
777 phy = <&hdmiphy>;
778 #sound-dai-cells = <0>;
779 status = "disabled";
780 };
781
782 hdmicec: cec@101b0000 {
783 compatible = "samsung,s5p-cec";
784 reg = <0x101B0000 0x200>;
785 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clock CLK_HDMI_CEC>;
787 clock-names = "hdmicec";
788 samsung,syscon-phandle = <&pmu_system_controller>;
789 hdmi-phandle = <&hdmi>;
790 pinctrl-names = "default";
791 pinctrl-0 = <&hdmi_cec>;
792 status = "disabled";
793 };
794
795 mixer: mixer@14450000 {
796 compatible = "samsung,exynos5250-mixer";
797 reg = <0x14450000 0x10000>;
798 power-domains = <&pd_disp1>;
799 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
801 <&clock CLK_SCLK_HDMI>;
802 clock-names = "mixer", "hdmi", "sclk_hdmi";
803 iommus = <&sysmmu_tv>;
804 status = "disabled";
805 };
806
807 dp_phy: video-phy {
808 compatible = "samsung,exynos5250-dp-video-phy";
809 samsung,pmu-syscon = <&pmu_system_controller>;
810 #phy-cells = <0>;
811 };
812
813 mipi_phy: video-phy@10040710 {
814 compatible = "samsung,s5pv210-mipi-video-phy";
815 reg = <0x10040710 0x100>;
816 #phy-cells = <1>;
817 syscon = <&pmu_system_controller>;
818 };
819
820 dsi_0: dsi@14500000 {
821 compatible = "samsung,exynos4210-mipi-dsi";
822 reg = <0x14500000 0x10000>;
823 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
824 samsung,power-domain = <&pd_disp1>;
825 phys = <&mipi_phy 3>;
826 phy-names = "dsim";
827 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
828 clock-names = "bus_clk", "sclk_mipi";
829 status = "disabled";
830 #address-cells = <1>;
831 #size-cells = <0>;
832 };
833
834 adc: adc@12d10000 {
835 compatible = "samsung,exynos-adc-v1";
836 reg = <0x12D10000 0x100>;
837 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&clock CLK_ADC>;
839 clock-names = "adc";
840 #io-channel-cells = <1>;
841 io-channel-ranges;
842 samsung,syscon-phandle = <&pmu_system_controller>;
843 status = "disabled";
844 };
845
846 sysmmu_g2d: sysmmu@10a60000 {
847 compatible = "samsung,exynos-sysmmu";
848 reg = <0x10A60000 0x1000>;
849 interrupt-parent = <&combiner>;
850 interrupts = <24 5>;
851 clock-names = "sysmmu", "master";
852 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
853 #iommu-cells = <0>;
854 };
855
856 sysmmu_mfc_r: sysmmu@11200000 {
857 compatible = "samsung,exynos-sysmmu";
858 reg = <0x11200000 0x1000>;
859 interrupt-parent = <&combiner>;
860 interrupts = <6 2>;
861 power-domains = <&pd_mfc>;
862 clock-names = "sysmmu", "master";
863 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
864 #iommu-cells = <0>;
865 };
866
867 sysmmu_mfc_l: sysmmu@11210000 {
868 compatible = "samsung,exynos-sysmmu";
869 reg = <0x11210000 0x1000>;
870 interrupt-parent = <&combiner>;
871 interrupts = <8 5>;
872 power-domains = <&pd_mfc>;
873 clock-names = "sysmmu", "master";
874 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
875 #iommu-cells = <0>;
876 };
877
878 sysmmu_rotator: sysmmu@11d40000 {
879 compatible = "samsung,exynos-sysmmu";
880 reg = <0x11D40000 0x1000>;
881 interrupt-parent = <&combiner>;
882 interrupts = <4 0>;
883 clock-names = "sysmmu", "master";
884 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
885 #iommu-cells = <0>;
886 };
887
888 sysmmu_jpeg: sysmmu@11f20000 {
889 compatible = "samsung,exynos-sysmmu";
890 reg = <0x11F20000 0x1000>;
891 interrupt-parent = <&combiner>;
892 interrupts = <4 2>;
893 power-domains = <&pd_gsc>;
894 clock-names = "sysmmu", "master";
895 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
896 #iommu-cells = <0>;
897 };
898
899 sysmmu_fimc_isp: sysmmu@13260000 {
900 compatible = "samsung,exynos-sysmmu";
901 reg = <0x13260000 0x1000>;
902 interrupt-parent = <&combiner>;
903 interrupts = <10 6>;
904 clock-names = "sysmmu";
905 clocks = <&clock CLK_SMMU_FIMC_ISP>;
906 #iommu-cells = <0>;
907 };
908
909 sysmmu_fimc_drc: sysmmu@13270000 {
910 compatible = "samsung,exynos-sysmmu";
911 reg = <0x13270000 0x1000>;
912 interrupt-parent = <&combiner>;
913 interrupts = <11 6>;
914 clock-names = "sysmmu";
915 clocks = <&clock CLK_SMMU_FIMC_DRC>;
916 #iommu-cells = <0>;
917 };
918
919 sysmmu_fimc_fd: sysmmu@132a0000 {
920 compatible = "samsung,exynos-sysmmu";
921 reg = <0x132A0000 0x1000>;
922 interrupt-parent = <&combiner>;
923 interrupts = <5 0>;
924 clock-names = "sysmmu";
925 clocks = <&clock CLK_SMMU_FIMC_FD>;
926 #iommu-cells = <0>;
927 };
928
929 sysmmu_fimc_scc: sysmmu@13280000 {
930 compatible = "samsung,exynos-sysmmu";
931 reg = <0x13280000 0x1000>;
932 interrupt-parent = <&combiner>;
933 interrupts = <5 2>;
934 clock-names = "sysmmu";
935 clocks = <&clock CLK_SMMU_FIMC_SCC>;
936 #iommu-cells = <0>;
937 };
938
939 sysmmu_fimc_scp: sysmmu@13290000 {
940 compatible = "samsung,exynos-sysmmu";
941 reg = <0x13290000 0x1000>;
942 interrupt-parent = <&combiner>;
943 interrupts = <3 6>;
944 clock-names = "sysmmu";
945 clocks = <&clock CLK_SMMU_FIMC_SCP>;
946 #iommu-cells = <0>;
947 };
948
949 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
950 compatible = "samsung,exynos-sysmmu";
951 reg = <0x132B0000 0x1000>;
952 interrupt-parent = <&combiner>;
953 interrupts = <5 4>;
954 clock-names = "sysmmu";
955 clocks = <&clock CLK_SMMU_FIMC_MCU>;
956 #iommu-cells = <0>;
957 };
958
959 sysmmu_fimc_odc: sysmmu@132c0000 {
960 compatible = "samsung,exynos-sysmmu";
961 reg = <0x132C0000 0x1000>;
962 interrupt-parent = <&combiner>;
963 interrupts = <11 0>;
964 clock-names = "sysmmu";
965 clocks = <&clock CLK_SMMU_FIMC_ODC>;
966 #iommu-cells = <0>;
967 };
968
969 sysmmu_fimc_dis0: sysmmu@132d0000 {
970 compatible = "samsung,exynos-sysmmu";
971 reg = <0x132D0000 0x1000>;
972 interrupt-parent = <&combiner>;
973 interrupts = <10 4>;
974 clock-names = "sysmmu";
975 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
976 #iommu-cells = <0>;
977 };
978
979 sysmmu_fimc_dis1: sysmmu@132e0000 {
980 compatible = "samsung,exynos-sysmmu";
981 reg = <0x132E0000 0x1000>;
982 interrupt-parent = <&combiner>;
983 interrupts = <9 4>;
984 clock-names = "sysmmu";
985 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
986 #iommu-cells = <0>;
987 };
988
989 sysmmu_fimc_3dnr: sysmmu@132f0000 {
990 compatible = "samsung,exynos-sysmmu";
991 reg = <0x132F0000 0x1000>;
992 interrupt-parent = <&combiner>;
993 interrupts = <5 6>;
994 clock-names = "sysmmu";
995 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
996 #iommu-cells = <0>;
997 };
998
999 sysmmu_fimc_lite0: sysmmu@13c40000 {
1000 compatible = "samsung,exynos-sysmmu";
1001 reg = <0x13C40000 0x1000>;
1002 interrupt-parent = <&combiner>;
1003 interrupts = <3 4>;
1004 power-domains = <&pd_gsc>;
1005 clock-names = "sysmmu", "master";
1006 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1007 #iommu-cells = <0>;
1008 };
1009
1010 sysmmu_fimc_lite1: sysmmu@13c50000 {
1011 compatible = "samsung,exynos-sysmmu";
1012 reg = <0x13C50000 0x1000>;
1013 interrupt-parent = <&combiner>;
1014 interrupts = <24 1>;
1015 power-domains = <&pd_gsc>;
1016 clock-names = "sysmmu", "master";
1017 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1018 #iommu-cells = <0>;
1019 };
1020
1021 sysmmu_gsc0: sysmmu@13e80000 {
1022 compatible = "samsung,exynos-sysmmu";
1023 reg = <0x13E80000 0x1000>;
1024 interrupt-parent = <&combiner>;
1025 interrupts = <2 0>;
1026 power-domains = <&pd_gsc>;
1027 clock-names = "sysmmu", "master";
1028 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1029 #iommu-cells = <0>;
1030 };
1031
1032 sysmmu_gsc1: sysmmu@13e90000 {
1033 compatible = "samsung,exynos-sysmmu";
1034 reg = <0x13E90000 0x1000>;
1035 interrupt-parent = <&combiner>;
1036 interrupts = <2 2>;
1037 power-domains = <&pd_gsc>;
1038 clock-names = "sysmmu", "master";
1039 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1040 #iommu-cells = <0>;
1041 };
1042
1043 sysmmu_gsc2: sysmmu@13ea0000 {
1044 compatible = "samsung,exynos-sysmmu";
1045 reg = <0x13EA0000 0x1000>;
1046 interrupt-parent = <&combiner>;
1047 interrupts = <2 4>;
1048 power-domains = <&pd_gsc>;
1049 clock-names = "sysmmu", "master";
1050 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1051 #iommu-cells = <0>;
1052 };
1053
1054 sysmmu_gsc3: sysmmu@13eb0000 {
1055 compatible = "samsung,exynos-sysmmu";
1056 reg = <0x13EB0000 0x1000>;
1057 interrupt-parent = <&combiner>;
1058 interrupts = <2 6>;
1059 power-domains = <&pd_gsc>;
1060 clock-names = "sysmmu", "master";
1061 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1062 #iommu-cells = <0>;
1063 };
1064
1065 sysmmu_fimd1: sysmmu@14640000 {
1066 compatible = "samsung,exynos-sysmmu";
1067 reg = <0x14640000 0x1000>;
1068 interrupt-parent = <&combiner>;
1069 interrupts = <3 2>;
1070 power-domains = <&pd_disp1>;
1071 clock-names = "sysmmu", "master";
1072 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1073 #iommu-cells = <0>;
1074 };
1075
1076 sysmmu_tv: sysmmu@14650000 {
1077 compatible = "samsung,exynos-sysmmu";
1078 reg = <0x14650000 0x1000>;
1079 interrupt-parent = <&combiner>;
1080 interrupts = <7 4>;
1081 power-domains = <&pd_disp1>;
1082 clock-names = "sysmmu", "master";
1083 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1084 #iommu-cells = <0>;
1085 };
1086 };
1087
1088 thermal-zones {
1089 cpu_thermal: cpu-thermal {
1090 polling-delay-passive = <0>;
1091 polling-delay = <0>;
1092 thermal-sensors = <&tmu 0>;
1093
1094 cooling-maps {
1095 map0 {
1096 /* Corresponds to 800MHz at freq_table */
1097 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1098 };
1099 map1 {
1100 /* Corresponds to 200MHz at freq_table */
1101 cooling-device = <&cpu0 15 15>,
1102 <&cpu1 15 15>;
1103 };
1104 };
1105 };
1106 };
1107
1108 timer {
1109 compatible = "arm,armv7-timer";
1110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1112 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1114 /*
1115 * Unfortunately we need this since some versions
1116 * of U-Boot on Exynos don't set the CNTFRQ register,
1117 * so we need the value from DT.
1118 */
1119 clock-frequency = <24000000>;
1120 };
1121};
1122
1123&dp {
1124 power-domains = <&pd_disp1>;
1125 clocks = <&clock CLK_DP>;
1126 clock-names = "dp";
1127 phys = <&dp_phy>;
1128 phy-names = "dp";
1129};
1130
1131&fimd {
1132 power-domains = <&pd_disp1>;
1133 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1134 clock-names = "sclk_fimd", "fimd";
1135 iommus = <&sysmmu_fimd1>;
1136};
1137
1138&g2d {
1139 iommus = <&sysmmu_g2d>;
1140 clocks = <&clock CLK_G2D>;
1141 clock-names = "fimg2d";
1142 status = "okay";
1143};
1144
1145&i2c_0 {
1146 clocks = <&clock CLK_I2C0>;
1147 clock-names = "i2c";
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&i2c0_bus>;
1150};
1151
1152&i2c_1 {
1153 clocks = <&clock CLK_I2C1>;
1154 clock-names = "i2c";
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&i2c1_bus>;
1157};
1158
1159&i2c_2 {
1160 clocks = <&clock CLK_I2C2>;
1161 clock-names = "i2c";
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&i2c2_bus>;
1164};
1165
1166&i2c_3 {
1167 clocks = <&clock CLK_I2C3>;
1168 clock-names = "i2c";
1169 pinctrl-names = "default";
1170 pinctrl-0 = <&i2c3_bus>;
1171};
1172
1173&prng {
1174 clocks = <&clock CLK_SSS>;
1175 clock-names = "secss";
1176};
1177
1178&pwm {
1179 clocks = <&clock CLK_PWM>;
1180 clock-names = "timers";
1181};
1182
1183&rtc {
1184 clocks = <&clock CLK_RTC>;
1185 clock-names = "rtc";
1186 interrupt-parent = <&pmu_system_controller>;
1187 status = "disabled";
1188};
1189
1190&serial_0 {
1191 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1192 clock-names = "uart", "clk_uart_baud0";
1193 dmas = <&pdma0 13>, <&pdma0 14>;
1194 dma-names = "rx", "tx";
1195};
1196
1197&serial_1 {
1198 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1199 clock-names = "uart", "clk_uart_baud0";
1200 dmas = <&pdma1 15>, <&pdma1 16>;
1201 dma-names = "rx", "tx";
1202};
1203
1204&serial_2 {
1205 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1206 clock-names = "uart", "clk_uart_baud0";
1207 dmas = <&pdma0 15>, <&pdma0 16>;
1208 dma-names = "rx", "tx";
1209};
1210
1211&serial_3 {
1212 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1213 clock-names = "uart", "clk_uart_baud0";
1214 dmas = <&pdma1 17>, <&pdma1 18>;
1215 dma-names = "rx", "tx";
1216};
1217
1218&sss {
1219 clocks = <&clock CLK_SSS>;
1220 clock-names = "secss";
1221};
1222
1223&trng {
1224 clocks = <&clock CLK_SSS>;
1225 clock-names = "secss";
1226};
1227
1228#include "exynos5250-pinctrl.dtsi"
1229#include "exynos-syscon-restart.dtsi"