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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SAMSUNG EXYNOS5250 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
9 * EXYNOS5250 based board files can include this file and provide
10 * values for board specfic bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
14 * additional nodes can be added to this file.
15 */
16
17#include <dt-bindings/clock/exynos5250.h>
18#include "exynos5.dtsi"
19#include "exynos4-cpu-thermal.dtsi"
20#include <dt-bindings/clock/exynos-audss-clk.h>
21
22/ {
23 compatible = "samsung,exynos5250", "samsung,exynos5";
24
25 aliases {
26 spi0 = &spi_0;
27 spi1 = &spi_1;
28 spi2 = &spi_2;
29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3;
33 mshc0 = &mmc_0;
34 mshc1 = &mmc_1;
35 mshc2 = &mmc_2;
36 mshc3 = &mmc_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 i2c9 = &i2c_9;
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a15";
56 reg = <0>;
57 clock-frequency = <1700000000>;
58 clocks = <&clock CLK_ARM_CLK>;
59 clock-names = "cpu";
60 clock-latency = <140000>;
61
62 operating-points = <
63 1700000 1300000
64 1600000 1250000
65 1500000 1225000
66 1400000 1200000
67 1300000 1150000
68 1200000 1125000
69 1100000 1100000
70 1000000 1075000
71 900000 1050000
72 800000 1025000
73 700000 1012500
74 600000 1000000
75 500000 975000
76 400000 950000
77 300000 937500
78 200000 925000
79 >;
80 #cooling-cells = <2>; /* min followed by max */
81 };
82 cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <1>;
86 clock-frequency = <1700000000>;
87 };
88 };
89
90 soc: soc {
91 sysram@2020000 {
92 compatible = "mmio-sram";
93 reg = <0x02020000 0x30000>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges = <0 0x02020000 0x30000>;
97
98 smp-sysram@0 {
99 compatible = "samsung,exynos4210-sysram";
100 reg = <0x0 0x1000>;
101 };
102
103 smp-sysram@2f000 {
104 compatible = "samsung,exynos4210-sysram-ns";
105 reg = <0x2f000 0x1000>;
106 };
107 };
108
109 pd_gsc: power-domain@10044000 {
110 compatible = "samsung,exynos4210-pd";
111 reg = <0x10044000 0x20>;
112 #power-domain-cells = <0>;
113 label = "GSC";
114 };
115
116 pd_mfc: power-domain@10044040 {
117 compatible = "samsung,exynos4210-pd";
118 reg = <0x10044040 0x20>;
119 #power-domain-cells = <0>;
120 label = "MFC";
121 };
122
123 pd_g3d: power-domain@10044060 {
124 compatible = "samsung,exynos4210-pd";
125 reg = <0x10044060 0x20>;
126 #power-domain-cells = <0>;
127 label = "G3D";
128 };
129
130 pd_disp1: power-domain@100440a0 {
131 compatible = "samsung,exynos4210-pd";
132 reg = <0x100440A0 0x20>;
133 #power-domain-cells = <0>;
134 label = "DISP1";
135 clocks = <&clock CLK_FIN_PLL>,
136 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
137 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
138 clock-names = "oscclk", "clk0", "clk1";
139 };
140
141 pd_mau: power-domain@100440c0 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x100440C0 0x20>;
144 #power-domain-cells = <0>;
145 label = "MAU";
146 };
147
148 clock: clock-controller@10010000 {
149 compatible = "samsung,exynos5250-clock";
150 reg = <0x10010000 0x30000>;
151 #clock-cells = <1>;
152 };
153
154 clock_audss: audss-clock-controller@3810000 {
155 compatible = "samsung,exynos5250-audss-clock";
156 reg = <0x03810000 0x0C>;
157 #clock-cells = <1>;
158 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
159 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
160 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
161 power-domains = <&pd_mau>;
162 };
163
164 timer {
165 compatible = "arm,armv7-timer";
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
170 /*
171 * Unfortunately we need this since some versions
172 * of U-Boot on Exynos don't set the CNTFRQ register,
173 * so we need the value from DT.
174 */
175 clock-frequency = <24000000>;
176 };
177
178 mct@101c0000 {
179 compatible = "samsung,exynos4210-mct";
180 reg = <0x101C0000 0x800>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
183 interrupt-parent = <&mct_map>;
184 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
185 <4 0>, <5 0>;
186 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
187 clock-names = "fin_pll", "mct";
188
189 mct_map: mct-map {
190 #interrupt-cells = <2>;
191 #address-cells = <0>;
192 #size-cells = <0>;
193 interrupt-map = <0x0 0 &combiner 23 3>,
194 <0x1 0 &combiner 23 4>,
195 <0x2 0 &combiner 25 2>,
196 <0x3 0 &combiner 25 3>,
197 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
198 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
199 };
200 };
201
202 pmu {
203 compatible = "arm,cortex-a15-pmu";
204 interrupt-parent = <&combiner>;
205 interrupts = <1 2>, <22 4>;
206 };
207
208 pinctrl_0: pinctrl@11400000 {
209 compatible = "samsung,exynos5250-pinctrl";
210 reg = <0x11400000 0x1000>;
211 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
212
213 wakup_eint: wakeup-interrupt-controller {
214 compatible = "samsung,exynos4210-wakeup-eint";
215 interrupt-parent = <&gic>;
216 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
217 };
218 };
219
220 pinctrl_1: pinctrl@13400000 {
221 compatible = "samsung,exynos5250-pinctrl";
222 reg = <0x13400000 0x1000>;
223 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
224 };
225
226 pinctrl_2: pinctrl@10d10000 {
227 compatible = "samsung,exynos5250-pinctrl";
228 reg = <0x10d10000 0x1000>;
229 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
230 };
231
232 pinctrl_3: pinctrl@3860000 {
233 compatible = "samsung,exynos5250-pinctrl";
234 reg = <0x03860000 0x1000>;
235 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
236 power-domains = <&pd_mau>;
237 };
238
239 pmu_system_controller: system-controller@10040000 {
240 compatible = "samsung,exynos5250-pmu", "syscon";
241 reg = <0x10040000 0x5000>;
242 clock-names = "clkout16";
243 clocks = <&clock CLK_FIN_PLL>;
244 #clock-cells = <1>;
245 interrupt-controller;
246 #interrupt-cells = <3>;
247 interrupt-parent = <&gic>;
248 };
249
250 watchdog@101d0000 {
251 compatible = "samsung,exynos5250-wdt";
252 reg = <0x101D0000 0x100>;
253 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clock CLK_WDT>;
255 clock-names = "watchdog";
256 samsung,syscon-phandle = <&pmu_system_controller>;
257 };
258
259 mfc: codec@11000000 {
260 compatible = "samsung,mfc-v6";
261 reg = <0x11000000 0x10000>;
262 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
263 power-domains = <&pd_mfc>;
264 clocks = <&clock CLK_MFC>;
265 clock-names = "mfc";
266 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
267 iommu-names = "left", "right";
268 };
269
270 rotator: rotator@11c00000 {
271 compatible = "samsung,exynos5250-rotator";
272 reg = <0x11C00000 0x64>;
273 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clock CLK_ROTATOR>;
275 clock-names = "rotator";
276 iommus = <&sysmmu_rotator>;
277 };
278
279 tmu: tmu@10060000 {
280 compatible = "samsung,exynos5250-tmu";
281 reg = <0x10060000 0x100>;
282 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clock CLK_TMU>;
284 clock-names = "tmu_apbif";
285 #include "exynos4412-tmu-sensor-conf.dtsi"
286 };
287
288 sata: sata@122f0000 {
289 compatible = "snps,dwc-ahci";
290 samsung,sata-freq = <66>;
291 reg = <0x122F0000 0x1ff>;
292 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
294 clock-names = "sata", "sclk_sata";
295 phys = <&sata_phy>;
296 phy-names = "sata-phy";
297 status = "disabled";
298 };
299
300 sata_phy: sata-phy@12170000 {
301 compatible = "samsung,exynos5250-sata-phy";
302 reg = <0x12170000 0x1ff>;
303 clocks = <&clock CLK_SATA_PHYCTRL>;
304 clock-names = "sata_phyctrl";
305 #phy-cells = <0>;
306 samsung,syscon-phandle = <&pmu_system_controller>;
307 status = "disabled";
308 };
309
310 /* i2c_0-3 are defined in exynos5.dtsi */
311 i2c_4: i2c@12ca0000 {
312 compatible = "samsung,s3c2440-i2c";
313 reg = <0x12CA0000 0x100>;
314 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 clocks = <&clock CLK_I2C4>;
318 clock-names = "i2c";
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c4_bus>;
321 status = "disabled";
322 };
323
324 i2c_5: i2c@12cb0000 {
325 compatible = "samsung,s3c2440-i2c";
326 reg = <0x12CB0000 0x100>;
327 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
328 #address-cells = <1>;
329 #size-cells = <0>;
330 clocks = <&clock CLK_I2C5>;
331 clock-names = "i2c";
332 pinctrl-names = "default";
333 pinctrl-0 = <&i2c5_bus>;
334 status = "disabled";
335 };
336
337 i2c_6: i2c@12cc0000 {
338 compatible = "samsung,s3c2440-i2c";
339 reg = <0x12CC0000 0x100>;
340 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 clocks = <&clock CLK_I2C6>;
344 clock-names = "i2c";
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c6_bus>;
347 status = "disabled";
348 };
349
350 i2c_7: i2c@12cd0000 {
351 compatible = "samsung,s3c2440-i2c";
352 reg = <0x12CD0000 0x100>;
353 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 clocks = <&clock CLK_I2C7>;
357 clock-names = "i2c";
358 pinctrl-names = "default";
359 pinctrl-0 = <&i2c7_bus>;
360 status = "disabled";
361 };
362
363 i2c_8: i2c@12ce0000 {
364 compatible = "samsung,s3c2440-hdmiphy-i2c";
365 reg = <0x12CE0000 0x1000>;
366 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 clocks = <&clock CLK_I2C_HDMI>;
370 clock-names = "i2c";
371 status = "disabled";
372
373 hdmiphy: hdmiphy@38 {
374 compatible = "samsung,exynos4212-hdmiphy";
375 reg = <0x38>;
376 };
377 };
378
379 i2c_9: i2c@121d0000 {
380 compatible = "samsung,exynos5-sata-phy-i2c";
381 reg = <0x121D0000 0x100>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 clocks = <&clock CLK_SATA_PHYI2C>;
385 clock-names = "i2c";
386 status = "disabled";
387 };
388
389 spi_0: spi@12d20000 {
390 compatible = "samsung,exynos4210-spi";
391 status = "disabled";
392 reg = <0x12d20000 0x100>;
393 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
394 dmas = <&pdma0 5
395 &pdma0 4>;
396 dma-names = "tx", "rx";
397 #address-cells = <1>;
398 #size-cells = <0>;
399 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
400 clock-names = "spi", "spi_busclk0";
401 pinctrl-names = "default";
402 pinctrl-0 = <&spi0_bus>;
403 };
404
405 spi_1: spi@12d30000 {
406 compatible = "samsung,exynos4210-spi";
407 status = "disabled";
408 reg = <0x12d30000 0x100>;
409 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
410 dmas = <&pdma1 5
411 &pdma1 4>;
412 dma-names = "tx", "rx";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
416 clock-names = "spi", "spi_busclk0";
417 pinctrl-names = "default";
418 pinctrl-0 = <&spi1_bus>;
419 };
420
421 spi_2: spi@12d40000 {
422 compatible = "samsung,exynos4210-spi";
423 status = "disabled";
424 reg = <0x12d40000 0x100>;
425 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
426 dmas = <&pdma0 7
427 &pdma0 6>;
428 dma-names = "tx", "rx";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
432 clock-names = "spi", "spi_busclk0";
433 pinctrl-names = "default";
434 pinctrl-0 = <&spi2_bus>;
435 };
436
437 mmc_0: mmc@12200000 {
438 compatible = "samsung,exynos5250-dw-mshc";
439 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>;
441 #size-cells = <0>;
442 reg = <0x12200000 0x1000>;
443 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
444 clock-names = "biu", "ciu";
445 fifo-depth = <0x80>;
446 status = "disabled";
447 };
448
449 mmc_1: mmc@12210000 {
450 compatible = "samsung,exynos5250-dw-mshc";
451 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 reg = <0x12210000 0x1000>;
455 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
456 clock-names = "biu", "ciu";
457 fifo-depth = <0x80>;
458 status = "disabled";
459 };
460
461 mmc_2: mmc@12220000 {
462 compatible = "samsung,exynos5250-dw-mshc";
463 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 reg = <0x12220000 0x1000>;
467 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
468 clock-names = "biu", "ciu";
469 fifo-depth = <0x80>;
470 status = "disabled";
471 };
472
473 mmc_3: mmc@12230000 {
474 compatible = "samsung,exynos5250-dw-mshc";
475 reg = <0x12230000 0x1000>;
476 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
480 clock-names = "biu", "ciu";
481 fifo-depth = <0x80>;
482 status = "disabled";
483 };
484
485 i2s0: i2s@3830000 {
486 compatible = "samsung,s5pv210-i2s";
487 status = "disabled";
488 reg = <0x03830000 0x100>;
489 dmas = <&pdma0 10
490 &pdma0 9
491 &pdma0 8>;
492 dma-names = "tx", "rx", "tx-sec";
493 clocks = <&clock_audss EXYNOS_I2S_BUS>,
494 <&clock_audss EXYNOS_I2S_BUS>,
495 <&clock_audss EXYNOS_SCLK_I2S>;
496 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
497 samsung,idma-addr = <0x03000000>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&i2s0_bus>;
500 power-domains = <&pd_mau>;
501 #clock-cells = <1>;
502 #sound-dai-cells = <1>;
503 };
504
505 i2s1: i2s@12d60000 {
506 compatible = "samsung,s3c6410-i2s";
507 status = "disabled";
508 reg = <0x12D60000 0x100>;
509 dmas = <&pdma1 12
510 &pdma1 11>;
511 dma-names = "tx", "rx";
512 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
513 clock-names = "iis", "i2s_opclk0";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2s1_bus>;
516 power-domains = <&pd_mau>;
517 #sound-dai-cells = <1>;
518 };
519
520 i2s2: i2s@12d70000 {
521 compatible = "samsung,s3c6410-i2s";
522 status = "disabled";
523 reg = <0x12D70000 0x100>;
524 dmas = <&pdma0 12
525 &pdma0 11>;
526 dma-names = "tx", "rx";
527 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
528 clock-names = "iis", "i2s_opclk0";
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2s2_bus>;
531 power-domains = <&pd_mau>;
532 #sound-dai-cells = <1>;
533 };
534
535 usb_dwc3 {
536 compatible = "samsung,exynos5250-dwusb3";
537 clocks = <&clock CLK_USB3>;
538 clock-names = "usbdrd30";
539 #address-cells = <1>;
540 #size-cells = <1>;
541 ranges;
542
543 usbdrd_dwc3: dwc3@12000000 {
544 compatible = "synopsys,dwc3";
545 reg = <0x12000000 0x10000>;
546 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
547 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
548 phy-names = "usb2-phy", "usb3-phy";
549 };
550 };
551
552 usbdrd_phy: phy@12100000 {
553 compatible = "samsung,exynos5250-usbdrd-phy";
554 reg = <0x12100000 0x100>;
555 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
556 clock-names = "phy", "ref";
557 samsung,pmu-syscon = <&pmu_system_controller>;
558 #phy-cells = <1>;
559 };
560
561 ehci: usb@12110000 {
562 compatible = "samsung,exynos4210-ehci";
563 reg = <0x12110000 0x100>;
564 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
565
566 clocks = <&clock CLK_USB2>;
567 clock-names = "usbhost";
568 #address-cells = <1>;
569 #size-cells = <0>;
570 port@0 {
571 reg = <0>;
572 phys = <&usb2_phy_gen 1>;
573 };
574 };
575
576 ohci: usb@12120000 {
577 compatible = "samsung,exynos4210-ohci";
578 reg = <0x12120000 0x100>;
579 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
580
581 clocks = <&clock CLK_USB2>;
582 clock-names = "usbhost";
583 #address-cells = <1>;
584 #size-cells = <0>;
585 port@0 {
586 reg = <0>;
587 phys = <&usb2_phy_gen 1>;
588 };
589 };
590
591 usb2_phy_gen: phy@12130000 {
592 compatible = "samsung,exynos5250-usb2-phy";
593 reg = <0x12130000 0x100>;
594 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
595 clock-names = "phy", "ref";
596 #phy-cells = <1>;
597 samsung,sysreg-phandle = <&sysreg_system_controller>;
598 samsung,pmureg-phandle = <&pmu_system_controller>;
599 };
600
601 amba {
602 #address-cells = <1>;
603 #size-cells = <1>;
604 compatible = "simple-bus";
605 interrupt-parent = <&gic>;
606 ranges;
607
608 pdma0: pdma@121a0000 {
609 compatible = "arm,pl330", "arm,primecell";
610 reg = <0x121A0000 0x1000>;
611 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clock CLK_PDMA0>;
613 clock-names = "apb_pclk";
614 #dma-cells = <1>;
615 #dma-channels = <8>;
616 #dma-requests = <32>;
617 };
618
619 pdma1: pdma@121b0000 {
620 compatible = "arm,pl330", "arm,primecell";
621 reg = <0x121B0000 0x1000>;
622 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clock CLK_PDMA1>;
624 clock-names = "apb_pclk";
625 #dma-cells = <1>;
626 #dma-channels = <8>;
627 #dma-requests = <32>;
628 };
629
630 mdma0: mdma@10800000 {
631 compatible = "arm,pl330", "arm,primecell";
632 reg = <0x10800000 0x1000>;
633 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&clock CLK_MDMA0>;
635 clock-names = "apb_pclk";
636 #dma-cells = <1>;
637 #dma-channels = <8>;
638 #dma-requests = <1>;
639 };
640
641 mdma1: mdma@11c10000 {
642 compatible = "arm,pl330", "arm,primecell";
643 reg = <0x11C10000 0x1000>;
644 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clock CLK_MDMA1>;
646 clock-names = "apb_pclk";
647 #dma-cells = <1>;
648 #dma-channels = <8>;
649 #dma-requests = <1>;
650 };
651 };
652
653 gsc_0: gsc@13e00000 {
654 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
655 reg = <0x13e00000 0x1000>;
656 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
657 power-domains = <&pd_gsc>;
658 clocks = <&clock CLK_GSCL0>;
659 clock-names = "gscl";
660 iommus = <&sysmmu_gsc0>;
661 };
662
663 gsc_1: gsc@13e10000 {
664 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
665 reg = <0x13e10000 0x1000>;
666 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
667 power-domains = <&pd_gsc>;
668 clocks = <&clock CLK_GSCL1>;
669 clock-names = "gscl";
670 iommus = <&sysmmu_gsc1>;
671 };
672
673 gsc_2: gsc@13e20000 {
674 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
675 reg = <0x13e20000 0x1000>;
676 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
677 power-domains = <&pd_gsc>;
678 clocks = <&clock CLK_GSCL2>;
679 clock-names = "gscl";
680 iommus = <&sysmmu_gsc2>;
681 };
682
683 gsc_3: gsc@13e30000 {
684 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
685 reg = <0x13e30000 0x1000>;
686 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
687 power-domains = <&pd_gsc>;
688 clocks = <&clock CLK_GSCL3>;
689 clock-names = "gscl";
690 iommus = <&sysmmu_gsc3>;
691 };
692
693 hdmi: hdmi@14530000 {
694 compatible = "samsung,exynos4212-hdmi";
695 reg = <0x14530000 0x70000>;
696 power-domains = <&pd_disp1>;
697 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
699 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
700 <&clock CLK_MOUT_HDMI>;
701 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
702 "sclk_hdmiphy", "mout_hdmi";
703 samsung,syscon-phandle = <&pmu_system_controller>;
704 phy = <&hdmiphy>;
705 #sound-dai-cells = <0>;
706 status = "disabled";
707 };
708
709 hdmicec: cec@101b0000 {
710 compatible = "samsung,s5p-cec";
711 reg = <0x101B0000 0x200>;
712 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clock CLK_HDMI_CEC>;
714 clock-names = "hdmicec";
715 samsung,syscon-phandle = <&pmu_system_controller>;
716 hdmi-phandle = <&hdmi>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&hdmi_cec>;
719 status = "disabled";
720 };
721
722 mixer: mixer@14450000 {
723 compatible = "samsung,exynos5250-mixer";
724 reg = <0x14450000 0x10000>;
725 power-domains = <&pd_disp1>;
726 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
728 <&clock CLK_SCLK_HDMI>;
729 clock-names = "mixer", "hdmi", "sclk_hdmi";
730 iommus = <&sysmmu_tv>;
731 status = "disabled";
732 };
733
734 dp_phy: video-phy {
735 compatible = "samsung,exynos5250-dp-video-phy";
736 samsung,pmu-syscon = <&pmu_system_controller>;
737 #phy-cells = <0>;
738 };
739
740 adc: adc@12d10000 {
741 compatible = "samsung,exynos-adc-v1";
742 reg = <0x12D10000 0x100>;
743 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clock CLK_ADC>;
745 clock-names = "adc";
746 #io-channel-cells = <1>;
747 io-channel-ranges;
748 samsung,syscon-phandle = <&pmu_system_controller>;
749 status = "disabled";
750 };
751
752 sysmmu_g2d: sysmmu@10a60000 {
753 compatible = "samsung,exynos-sysmmu";
754 reg = <0x10A60000 0x1000>;
755 interrupt-parent = <&combiner>;
756 interrupts = <24 5>;
757 clock-names = "sysmmu", "master";
758 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
759 #iommu-cells = <0>;
760 };
761
762 sysmmu_mfc_r: sysmmu@11200000 {
763 compatible = "samsung,exynos-sysmmu";
764 reg = <0x11200000 0x1000>;
765 interrupt-parent = <&combiner>;
766 interrupts = <6 2>;
767 power-domains = <&pd_mfc>;
768 clock-names = "sysmmu", "master";
769 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
770 #iommu-cells = <0>;
771 };
772
773 sysmmu_mfc_l: sysmmu@11210000 {
774 compatible = "samsung,exynos-sysmmu";
775 reg = <0x11210000 0x1000>;
776 interrupt-parent = <&combiner>;
777 interrupts = <8 5>;
778 power-domains = <&pd_mfc>;
779 clock-names = "sysmmu", "master";
780 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
781 #iommu-cells = <0>;
782 };
783
784 sysmmu_rotator: sysmmu@11d40000 {
785 compatible = "samsung,exynos-sysmmu";
786 reg = <0x11D40000 0x1000>;
787 interrupt-parent = <&combiner>;
788 interrupts = <4 0>;
789 clock-names = "sysmmu", "master";
790 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
791 #iommu-cells = <0>;
792 };
793
794 sysmmu_jpeg: sysmmu@11f20000 {
795 compatible = "samsung,exynos-sysmmu";
796 reg = <0x11F20000 0x1000>;
797 interrupt-parent = <&combiner>;
798 interrupts = <4 2>;
799 power-domains = <&pd_gsc>;
800 clock-names = "sysmmu", "master";
801 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
802 #iommu-cells = <0>;
803 };
804
805 sysmmu_fimc_isp: sysmmu@13260000 {
806 compatible = "samsung,exynos-sysmmu";
807 reg = <0x13260000 0x1000>;
808 interrupt-parent = <&combiner>;
809 interrupts = <10 6>;
810 clock-names = "sysmmu";
811 clocks = <&clock CLK_SMMU_FIMC_ISP>;
812 #iommu-cells = <0>;
813 };
814
815 sysmmu_fimc_drc: sysmmu@13270000 {
816 compatible = "samsung,exynos-sysmmu";
817 reg = <0x13270000 0x1000>;
818 interrupt-parent = <&combiner>;
819 interrupts = <11 6>;
820 clock-names = "sysmmu";
821 clocks = <&clock CLK_SMMU_FIMC_DRC>;
822 #iommu-cells = <0>;
823 };
824
825 sysmmu_fimc_fd: sysmmu@132a0000 {
826 compatible = "samsung,exynos-sysmmu";
827 reg = <0x132A0000 0x1000>;
828 interrupt-parent = <&combiner>;
829 interrupts = <5 0>;
830 clock-names = "sysmmu";
831 clocks = <&clock CLK_SMMU_FIMC_FD>;
832 #iommu-cells = <0>;
833 };
834
835 sysmmu_fimc_scc: sysmmu@13280000 {
836 compatible = "samsung,exynos-sysmmu";
837 reg = <0x13280000 0x1000>;
838 interrupt-parent = <&combiner>;
839 interrupts = <5 2>;
840 clock-names = "sysmmu";
841 clocks = <&clock CLK_SMMU_FIMC_SCC>;
842 #iommu-cells = <0>;
843 };
844
845 sysmmu_fimc_scp: sysmmu@13290000 {
846 compatible = "samsung,exynos-sysmmu";
847 reg = <0x13290000 0x1000>;
848 interrupt-parent = <&combiner>;
849 interrupts = <3 6>;
850 clock-names = "sysmmu";
851 clocks = <&clock CLK_SMMU_FIMC_SCP>;
852 #iommu-cells = <0>;
853 };
854
855 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
856 compatible = "samsung,exynos-sysmmu";
857 reg = <0x132B0000 0x1000>;
858 interrupt-parent = <&combiner>;
859 interrupts = <5 4>;
860 clock-names = "sysmmu";
861 clocks = <&clock CLK_SMMU_FIMC_MCU>;
862 #iommu-cells = <0>;
863 };
864
865 sysmmu_fimc_odc: sysmmu@132c0000 {
866 compatible = "samsung,exynos-sysmmu";
867 reg = <0x132C0000 0x1000>;
868 interrupt-parent = <&combiner>;
869 interrupts = <11 0>;
870 clock-names = "sysmmu";
871 clocks = <&clock CLK_SMMU_FIMC_ODC>;
872 #iommu-cells = <0>;
873 };
874
875 sysmmu_fimc_dis0: sysmmu@132d0000 {
876 compatible = "samsung,exynos-sysmmu";
877 reg = <0x132D0000 0x1000>;
878 interrupt-parent = <&combiner>;
879 interrupts = <10 4>;
880 clock-names = "sysmmu";
881 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
882 #iommu-cells = <0>;
883 };
884
885 sysmmu_fimc_dis1: sysmmu@132E0000{
886 compatible = "samsung,exynos-sysmmu";
887 reg = <0x132E0000 0x1000>;
888 interrupt-parent = <&combiner>;
889 interrupts = <9 4>;
890 clock-names = "sysmmu";
891 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
892 #iommu-cells = <0>;
893 };
894
895 sysmmu_fimc_3dnr: sysmmu@132f0000 {
896 compatible = "samsung,exynos-sysmmu";
897 reg = <0x132F0000 0x1000>;
898 interrupt-parent = <&combiner>;
899 interrupts = <5 6>;
900 clock-names = "sysmmu";
901 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
902 #iommu-cells = <0>;
903 };
904
905 sysmmu_fimc_lite0: sysmmu@13c40000 {
906 compatible = "samsung,exynos-sysmmu";
907 reg = <0x13C40000 0x1000>;
908 interrupt-parent = <&combiner>;
909 interrupts = <3 4>;
910 power-domains = <&pd_gsc>;
911 clock-names = "sysmmu", "master";
912 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
913 #iommu-cells = <0>;
914 };
915
916 sysmmu_fimc_lite1: sysmmu@13c50000 {
917 compatible = "samsung,exynos-sysmmu";
918 reg = <0x13C50000 0x1000>;
919 interrupt-parent = <&combiner>;
920 interrupts = <24 1>;
921 power-domains = <&pd_gsc>;
922 clock-names = "sysmmu", "master";
923 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
924 #iommu-cells = <0>;
925 };
926
927 sysmmu_gsc0: sysmmu@13e80000 {
928 compatible = "samsung,exynos-sysmmu";
929 reg = <0x13E80000 0x1000>;
930 interrupt-parent = <&combiner>;
931 interrupts = <2 0>;
932 power-domains = <&pd_gsc>;
933 clock-names = "sysmmu", "master";
934 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
935 #iommu-cells = <0>;
936 };
937
938 sysmmu_gsc1: sysmmu@13e90000 {
939 compatible = "samsung,exynos-sysmmu";
940 reg = <0x13E90000 0x1000>;
941 interrupt-parent = <&combiner>;
942 interrupts = <2 2>;
943 power-domains = <&pd_gsc>;
944 clock-names = "sysmmu", "master";
945 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
946 #iommu-cells = <0>;
947 };
948
949 sysmmu_gsc2: sysmmu@13ea0000 {
950 compatible = "samsung,exynos-sysmmu";
951 reg = <0x13EA0000 0x1000>;
952 interrupt-parent = <&combiner>;
953 interrupts = <2 4>;
954 power-domains = <&pd_gsc>;
955 clock-names = "sysmmu", "master";
956 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
957 #iommu-cells = <0>;
958 };
959
960 sysmmu_gsc3: sysmmu@13eb0000 {
961 compatible = "samsung,exynos-sysmmu";
962 reg = <0x13EB0000 0x1000>;
963 interrupt-parent = <&combiner>;
964 interrupts = <2 6>;
965 power-domains = <&pd_gsc>;
966 clock-names = "sysmmu", "master";
967 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
968 #iommu-cells = <0>;
969 };
970
971 sysmmu_fimd1: sysmmu@14640000 {
972 compatible = "samsung,exynos-sysmmu";
973 reg = <0x14640000 0x1000>;
974 interrupt-parent = <&combiner>;
975 interrupts = <3 2>;
976 power-domains = <&pd_disp1>;
977 clock-names = "sysmmu", "master";
978 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
979 #iommu-cells = <0>;
980 };
981
982 sysmmu_tv: sysmmu@14650000 {
983 compatible = "samsung,exynos-sysmmu";
984 reg = <0x14650000 0x1000>;
985 interrupt-parent = <&combiner>;
986 interrupts = <7 4>;
987 power-domains = <&pd_disp1>;
988 clock-names = "sysmmu", "master";
989 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
990 #iommu-cells = <0>;
991 };
992 };
993
994 thermal-zones {
995 cpu_thermal: cpu-thermal {
996 polling-delay-passive = <0>;
997 polling-delay = <0>;
998 thermal-sensors = <&tmu 0>;
999
1000 cooling-maps {
1001 map0 {
1002 /* Corresponds to 800MHz at freq_table */
1003 cooling-device = <&cpu0 9 9>;
1004 };
1005 map1 {
1006 /* Corresponds to 200MHz at freq_table */
1007 cooling-device = <&cpu0 15 15>;
1008 };
1009 };
1010 };
1011 };
1012};
1013
1014&dp {
1015 power-domains = <&pd_disp1>;
1016 clocks = <&clock CLK_DP>;
1017 clock-names = "dp";
1018 phys = <&dp_phy>;
1019 phy-names = "dp";
1020};
1021
1022&fimd {
1023 power-domains = <&pd_disp1>;
1024 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1025 clock-names = "sclk_fimd", "fimd";
1026 iommus = <&sysmmu_fimd1>;
1027};
1028
1029&g2d {
1030 iommus = <&sysmmu_g2d>;
1031 clocks = <&clock CLK_G2D>;
1032 clock-names = "fimg2d";
1033 status = "okay";
1034};
1035
1036&i2c_0 {
1037 clocks = <&clock CLK_I2C0>;
1038 clock-names = "i2c";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&i2c0_bus>;
1041};
1042
1043&i2c_1 {
1044 clocks = <&clock CLK_I2C1>;
1045 clock-names = "i2c";
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&i2c1_bus>;
1048};
1049
1050&i2c_2 {
1051 clocks = <&clock CLK_I2C2>;
1052 clock-names = "i2c";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&i2c2_bus>;
1055};
1056
1057&i2c_3 {
1058 clocks = <&clock CLK_I2C3>;
1059 clock-names = "i2c";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&i2c3_bus>;
1062};
1063
1064&prng {
1065 clocks = <&clock CLK_SSS>;
1066 clock-names = "secss";
1067};
1068
1069&pwm {
1070 clocks = <&clock CLK_PWM>;
1071 clock-names = "timers";
1072};
1073
1074&rtc {
1075 clocks = <&clock CLK_RTC>;
1076 clock-names = "rtc";
1077 interrupt-parent = <&pmu_system_controller>;
1078 status = "disabled";
1079};
1080
1081&serial_0 {
1082 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1083 clock-names = "uart", "clk_uart_baud0";
1084 dmas = <&pdma0 13>, <&pdma0 14>;
1085 dma-names = "rx", "tx";
1086};
1087
1088&serial_1 {
1089 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1090 clock-names = "uart", "clk_uart_baud0";
1091 dmas = <&pdma1 15>, <&pdma1 16>;
1092 dma-names = "rx", "tx";
1093};
1094
1095&serial_2 {
1096 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1097 clock-names = "uart", "clk_uart_baud0";
1098 dmas = <&pdma0 15>, <&pdma0 16>;
1099 dma-names = "rx", "tx";
1100};
1101
1102&serial_3 {
1103 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1104 clock-names = "uart", "clk_uart_baud0";
1105 dmas = <&pdma1 17>, <&pdma1 18>;
1106 dma-names = "rx", "tx";
1107};
1108
1109&sss {
1110 clocks = <&clock CLK_SSS>;
1111 clock-names = "secss";
1112};
1113
1114&trng {
1115 clocks = <&clock CLK_SSS>;
1116 clock-names = "secss";
1117};
1118
1119#include "exynos5250-pinctrl.dtsi"
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos5250 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include this file and provide
10 * values for board specfic bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
14 * additional nodes can be added to this file.
15 */
16
17#include <dt-bindings/clock/exynos5250.h>
18#include "exynos5.dtsi"
19#include "exynos4-cpu-thermal.dtsi"
20#include <dt-bindings/clock/exynos-audss-clk.h>
21
22/ {
23 compatible = "samsung,exynos5250", "samsung,exynos5";
24
25 aliases {
26 spi0 = &spi_0;
27 spi1 = &spi_1;
28 spi2 = &spi_2;
29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3;
33 mshc0 = &mmc_0;
34 mshc1 = &mmc_1;
35 mshc2 = &mmc_2;
36 mshc3 = &mmc_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 i2c9 = &i2c_9;
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu-map {
54 cluster0 {
55 core0 {
56 cpu = <&cpu0>;
57 };
58 core1 {
59 cpu = <&cpu1>;
60 };
61 };
62 };
63
64 cpu0: cpu@0 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <0>;
68 clocks = <&clock CLK_ARM_CLK>;
69 clock-names = "cpu";
70 operating-points-v2 = <&cpu0_opp_table>;
71 #cooling-cells = <2>; /* min followed by max */
72 };
73 cpu1: cpu@1 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a15";
76 reg = <1>;
77 clocks = <&clock CLK_ARM_CLK>;
78 clock-names = "cpu";
79 operating-points-v2 = <&cpu0_opp_table>;
80 #cooling-cells = <2>; /* min followed by max */
81 };
82 };
83
84 cpu0_opp_table: opp-table0 {
85 compatible = "operating-points-v2";
86 opp-shared;
87
88 opp-200000000 {
89 opp-hz = /bits/ 64 <200000000>;
90 opp-microvolt = <925000>;
91 clock-latency-ns = <140000>;
92 };
93 opp-300000000 {
94 opp-hz = /bits/ 64 <300000000>;
95 opp-microvolt = <937500>;
96 clock-latency-ns = <140000>;
97 };
98 opp-400000000 {
99 opp-hz = /bits/ 64 <400000000>;
100 opp-microvolt = <950000>;
101 clock-latency-ns = <140000>;
102 };
103 opp-500000000 {
104 opp-hz = /bits/ 64 <500000000>;
105 opp-microvolt = <975000>;
106 clock-latency-ns = <140000>;
107 };
108 opp-600000000 {
109 opp-hz = /bits/ 64 <600000000>;
110 opp-microvolt = <1000000>;
111 clock-latency-ns = <140000>;
112 };
113 opp-700000000 {
114 opp-hz = /bits/ 64 <700000000>;
115 opp-microvolt = <1012500>;
116 clock-latency-ns = <140000>;
117 };
118 opp-800000000 {
119 opp-hz = /bits/ 64 <800000000>;
120 opp-microvolt = <1025000>;
121 clock-latency-ns = <140000>;
122 };
123 opp-900000000 {
124 opp-hz = /bits/ 64 <900000000>;
125 opp-microvolt = <1050000>;
126 clock-latency-ns = <140000>;
127 };
128 opp-1000000000 {
129 opp-hz = /bits/ 64 <1000000000>;
130 opp-microvolt = <1075000>;
131 clock-latency-ns = <140000>;
132 opp-suspend;
133 };
134 opp-1100000000 {
135 opp-hz = /bits/ 64 <1100000000>;
136 opp-microvolt = <1100000>;
137 clock-latency-ns = <140000>;
138 };
139 opp-1200000000 {
140 opp-hz = /bits/ 64 <1200000000>;
141 opp-microvolt = <1125000>;
142 clock-latency-ns = <140000>;
143 };
144 opp-1300000000 {
145 opp-hz = /bits/ 64 <1300000000>;
146 opp-microvolt = <1150000>;
147 clock-latency-ns = <140000>;
148 };
149 opp-1400000000 {
150 opp-hz = /bits/ 64 <1400000000>;
151 opp-microvolt = <1200000>;
152 clock-latency-ns = <140000>;
153 };
154 opp-1500000000 {
155 opp-hz = /bits/ 64 <1500000000>;
156 opp-microvolt = <1225000>;
157 clock-latency-ns = <140000>;
158 };
159 opp-1600000000 {
160 opp-hz = /bits/ 64 <1600000000>;
161 opp-microvolt = <1250000>;
162 clock-latency-ns = <140000>;
163 };
164 opp-1700000000 {
165 opp-hz = /bits/ 64 <1700000000>;
166 opp-microvolt = <1300000>;
167 clock-latency-ns = <140000>;
168 };
169 };
170
171 pmu {
172 compatible = "arm,cortex-a15-pmu";
173 interrupt-parent = <&combiner>;
174 interrupts = <1 2>, <22 4>;
175 };
176
177 soc: soc {
178 sram@2020000 {
179 compatible = "mmio-sram";
180 reg = <0x02020000 0x30000>;
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges = <0 0x02020000 0x30000>;
184
185 smp-sram@0 {
186 compatible = "samsung,exynos4210-sysram";
187 reg = <0x0 0x1000>;
188 };
189
190 smp-sram@2f000 {
191 compatible = "samsung,exynos4210-sysram-ns";
192 reg = <0x2f000 0x1000>;
193 };
194 };
195
196 pd_gsc: power-domain@10044000 {
197 compatible = "samsung,exynos4210-pd";
198 reg = <0x10044000 0x20>;
199 #power-domain-cells = <0>;
200 label = "GSC";
201 };
202
203 pd_mfc: power-domain@10044040 {
204 compatible = "samsung,exynos4210-pd";
205 reg = <0x10044040 0x20>;
206 #power-domain-cells = <0>;
207 label = "MFC";
208 };
209
210 pd_g3d: power-domain@10044060 {
211 compatible = "samsung,exynos4210-pd";
212 reg = <0x10044060 0x20>;
213 #power-domain-cells = <0>;
214 label = "G3D";
215 };
216
217 pd_disp1: power-domain@100440a0 {
218 compatible = "samsung,exynos4210-pd";
219 reg = <0x100440A0 0x20>;
220 #power-domain-cells = <0>;
221 label = "DISP1";
222 };
223
224 pd_mau: power-domain@100440c0 {
225 compatible = "samsung,exynos4210-pd";
226 reg = <0x100440C0 0x20>;
227 #power-domain-cells = <0>;
228 label = "MAU";
229 };
230
231 clock: clock-controller@10010000 {
232 compatible = "samsung,exynos5250-clock";
233 reg = <0x10010000 0x30000>;
234 #clock-cells = <1>;
235 };
236
237 clock_audss: audss-clock-controller@3810000 {
238 compatible = "samsung,exynos5250-audss-clock";
239 reg = <0x03810000 0x0C>;
240 #clock-cells = <1>;
241 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
242 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
243 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
244 power-domains = <&pd_mau>;
245 };
246
247 timer@101c0000 {
248 compatible = "samsung,exynos5250-mct",
249 "samsung,exynos4210-mct";
250 reg = <0x101C0000 0x800>;
251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
252 clock-names = "fin_pll", "mct";
253 interrupts-extended = <&combiner 23 3>,
254 <&combiner 23 4>,
255 <&combiner 25 2>,
256 <&combiner 25 3>,
257 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
258 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
259 };
260
261 pinctrl_0: pinctrl@11400000 {
262 compatible = "samsung,exynos5250-pinctrl";
263 reg = <0x11400000 0x1000>;
264 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
265
266 wakup_eint: wakeup-interrupt-controller {
267 compatible = "samsung,exynos4210-wakeup-eint";
268 interrupt-parent = <&gic>;
269 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
270 };
271 };
272
273 pinctrl_1: pinctrl@13400000 {
274 compatible = "samsung,exynos5250-pinctrl";
275 reg = <0x13400000 0x1000>;
276 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
277 };
278
279 pinctrl_2: pinctrl@10d10000 {
280 compatible = "samsung,exynos5250-pinctrl";
281 reg = <0x10d10000 0x1000>;
282 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
283 };
284
285 pinctrl_3: pinctrl@3860000 {
286 compatible = "samsung,exynos5250-pinctrl";
287 reg = <0x03860000 0x1000>;
288 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
289 power-domains = <&pd_mau>;
290 };
291
292 pmu_system_controller: system-controller@10040000 {
293 compatible = "samsung,exynos5250-pmu", "syscon";
294 reg = <0x10040000 0x5000>;
295 clock-names = "clkout16";
296 clocks = <&clock CLK_FIN_PLL>;
297 #clock-cells = <1>;
298 interrupt-controller;
299 #interrupt-cells = <3>;
300 interrupt-parent = <&gic>;
301 };
302
303 watchdog@101d0000 {
304 compatible = "samsung,exynos5250-wdt";
305 reg = <0x101D0000 0x100>;
306 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&clock CLK_WDT>;
308 clock-names = "watchdog";
309 samsung,syscon-phandle = <&pmu_system_controller>;
310 };
311
312 mfc: codec@11000000 {
313 compatible = "samsung,mfc-v6";
314 reg = <0x11000000 0x10000>;
315 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
316 power-domains = <&pd_mfc>;
317 clocks = <&clock CLK_MFC>;
318 clock-names = "mfc";
319 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
320 iommu-names = "left", "right";
321 };
322
323 rotator: rotator@11c00000 {
324 compatible = "samsung,exynos5250-rotator";
325 reg = <0x11C00000 0x64>;
326 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clock CLK_ROTATOR>;
328 clock-names = "rotator";
329 iommus = <&sysmmu_rotator>;
330 };
331
332 mali: gpu@11800000 {
333 compatible = "samsung,exynos5250-mali", "arm,mali-t604";
334 reg = <0x11800000 0x5000>;
335 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-names = "job", "mmu", "gpu";
339 clocks = <&clock CLK_G3D>;
340 clock-names = "core";
341 operating-points-v2 = <&gpu_opp_table>;
342 power-domains = <&pd_g3d>;
343 status = "disabled";
344
345 gpu_opp_table: opp-table {
346 compatible = "operating-points-v2";
347
348 opp-100000000 {
349 opp-hz = /bits/ 64 <100000000>;
350 opp-microvolt = <925000>;
351 };
352 opp-160000000 {
353 opp-hz = /bits/ 64 <160000000>;
354 opp-microvolt = <925000>;
355 };
356 opp-266000000 {
357 opp-hz = /bits/ 64 <266000000>;
358 opp-microvolt = <1025000>;
359 };
360 opp-350000000 {
361 opp-hz = /bits/ 64 <350000000>;
362 opp-microvolt = <1075000>;
363 };
364 opp-400000000 {
365 opp-hz = /bits/ 64 <400000000>;
366 opp-microvolt = <1125000>;
367 };
368 opp-450000000 {
369 opp-hz = /bits/ 64 <450000000>;
370 opp-microvolt = <1150000>;
371 };
372 opp-533000000 {
373 opp-hz = /bits/ 64 <533000000>;
374 opp-microvolt = <1250000>;
375 };
376 };
377 };
378
379 tmu: tmu@10060000 {
380 compatible = "samsung,exynos5250-tmu";
381 reg = <0x10060000 0x100>;
382 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&clock CLK_TMU>;
384 clock-names = "tmu_apbif";
385 #thermal-sensor-cells = <0>;
386 };
387
388 sata: sata@122f0000 {
389 compatible = "snps,dwc-ahci";
390 reg = <0x122F0000 0x1ff>;
391 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
393 clock-names = "sata", "sclk_sata";
394 phys = <&sata_phy>;
395 phy-names = "sata-phy";
396 ports-implemented = <0x1>;
397 status = "disabled";
398 };
399
400 sata_phy: sata-phy@12170000 {
401 compatible = "samsung,exynos5250-sata-phy";
402 reg = <0x12170000 0x1ff>;
403 clocks = <&clock CLK_SATA_PHYCTRL>;
404 clock-names = "sata_phyctrl";
405 #phy-cells = <0>;
406 samsung,syscon-phandle = <&pmu_system_controller>;
407 status = "disabled";
408 };
409
410 /* i2c_0-3 are defined in exynos5.dtsi */
411 i2c_4: i2c@12ca0000 {
412 compatible = "samsung,s3c2440-i2c";
413 reg = <0x12CA0000 0x100>;
414 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
416 #size-cells = <0>;
417 clocks = <&clock CLK_I2C4>;
418 clock-names = "i2c";
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2c4_bus>;
421 status = "disabled";
422 };
423
424 i2c_5: i2c@12cb0000 {
425 compatible = "samsung,s3c2440-i2c";
426 reg = <0x12CB0000 0x100>;
427 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
428 #address-cells = <1>;
429 #size-cells = <0>;
430 clocks = <&clock CLK_I2C5>;
431 clock-names = "i2c";
432 pinctrl-names = "default";
433 pinctrl-0 = <&i2c5_bus>;
434 status = "disabled";
435 };
436
437 i2c_6: i2c@12cc0000 {
438 compatible = "samsung,s3c2440-i2c";
439 reg = <0x12CC0000 0x100>;
440 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 clocks = <&clock CLK_I2C6>;
444 clock-names = "i2c";
445 pinctrl-names = "default";
446 pinctrl-0 = <&i2c6_bus>;
447 status = "disabled";
448 };
449
450 i2c_7: i2c@12cd0000 {
451 compatible = "samsung,s3c2440-i2c";
452 reg = <0x12CD0000 0x100>;
453 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 clocks = <&clock CLK_I2C7>;
457 clock-names = "i2c";
458 pinctrl-names = "default";
459 pinctrl-0 = <&i2c7_bus>;
460 status = "disabled";
461 };
462
463 i2c_8: i2c@12ce0000 {
464 compatible = "samsung,s3c2440-hdmiphy-i2c";
465 reg = <0x12CE0000 0x1000>;
466 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 clocks = <&clock CLK_I2C_HDMI>;
470 clock-names = "i2c";
471 status = "disabled";
472
473 hdmiphy: hdmiphy@38 {
474 compatible = "samsung,exynos4212-hdmiphy";
475 reg = <0x38>;
476 };
477 };
478
479 i2c_9: i2c@121d0000 {
480 compatible = "samsung,exynos5-sata-phy-i2c";
481 reg = <0x121D0000 0x100>;
482 #address-cells = <1>;
483 #size-cells = <0>;
484 clocks = <&clock CLK_SATA_PHYI2C>;
485 clock-names = "i2c";
486 status = "disabled";
487
488 sata_phy_i2c: sata-phy-i2c@38 {
489 compatible = "samsung,exynos-sataphy-i2c";
490 reg = <0x38>;
491 status = "disabled";
492 };
493 };
494
495 spi_0: spi@12d20000 {
496 compatible = "samsung,exynos4210-spi";
497 status = "disabled";
498 reg = <0x12d20000 0x100>;
499 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
500 dmas = <&pdma0 5>, <&pdma0 4>;
501 dma-names = "tx", "rx";
502 #address-cells = <1>;
503 #size-cells = <0>;
504 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
505 clock-names = "spi", "spi_busclk0";
506 pinctrl-names = "default";
507 pinctrl-0 = <&spi0_bus>;
508 };
509
510 spi_1: spi@12d30000 {
511 compatible = "samsung,exynos4210-spi";
512 status = "disabled";
513 reg = <0x12d30000 0x100>;
514 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
515 dmas = <&pdma1 5>, <&pdma1 4>;
516 dma-names = "tx", "rx";
517 #address-cells = <1>;
518 #size-cells = <0>;
519 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
520 clock-names = "spi", "spi_busclk0";
521 pinctrl-names = "default";
522 pinctrl-0 = <&spi1_bus>;
523 };
524
525 spi_2: spi@12d40000 {
526 compatible = "samsung,exynos4210-spi";
527 status = "disabled";
528 reg = <0x12d40000 0x100>;
529 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
530 dmas = <&pdma0 7>, <&pdma0 6>;
531 dma-names = "tx", "rx";
532 #address-cells = <1>;
533 #size-cells = <0>;
534 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
535 clock-names = "spi", "spi_busclk0";
536 pinctrl-names = "default";
537 pinctrl-0 = <&spi2_bus>;
538 };
539
540 mmc_0: mmc@12200000 {
541 compatible = "samsung,exynos5250-dw-mshc";
542 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
543 #address-cells = <1>;
544 #size-cells = <0>;
545 reg = <0x12200000 0x1000>;
546 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
547 clock-names = "biu", "ciu";
548 fifo-depth = <0x80>;
549 status = "disabled";
550 };
551
552 mmc_1: mmc@12210000 {
553 compatible = "samsung,exynos5250-dw-mshc";
554 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
555 #address-cells = <1>;
556 #size-cells = <0>;
557 reg = <0x12210000 0x1000>;
558 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
559 clock-names = "biu", "ciu";
560 fifo-depth = <0x80>;
561 status = "disabled";
562 };
563
564 mmc_2: mmc@12220000 {
565 compatible = "samsung,exynos5250-dw-mshc";
566 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
567 #address-cells = <1>;
568 #size-cells = <0>;
569 reg = <0x12220000 0x1000>;
570 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
571 clock-names = "biu", "ciu";
572 fifo-depth = <0x80>;
573 status = "disabled";
574 };
575
576 mmc_3: mmc@12230000 {
577 compatible = "samsung,exynos5250-dw-mshc";
578 reg = <0x12230000 0x1000>;
579 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
580 #address-cells = <1>;
581 #size-cells = <0>;
582 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
583 clock-names = "biu", "ciu";
584 fifo-depth = <0x80>;
585 status = "disabled";
586 };
587
588 i2s0: i2s@3830000 {
589 compatible = "samsung,s5pv210-i2s";
590 status = "disabled";
591 reg = <0x03830000 0x100>;
592 dmas = <&pdma0 10>,
593 <&pdma0 9>,
594 <&pdma0 8>;
595 dma-names = "tx", "rx", "tx-sec";
596 clocks = <&clock_audss EXYNOS_I2S_BUS>,
597 <&clock_audss EXYNOS_I2S_BUS>,
598 <&clock_audss EXYNOS_SCLK_I2S>;
599 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
600 samsung,idma-addr = <0x03000000>;
601 pinctrl-names = "default";
602 pinctrl-0 = <&i2s0_bus>;
603 power-domains = <&pd_mau>;
604 #clock-cells = <1>;
605 #sound-dai-cells = <1>;
606 };
607
608 i2s1: i2s@12d60000 {
609 compatible = "samsung,s3c6410-i2s";
610 status = "disabled";
611 reg = <0x12D60000 0x100>;
612 dmas = <&pdma1 12>,
613 <&pdma1 11>;
614 dma-names = "tx", "rx";
615 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
616 clock-names = "iis", "i2s_opclk0";
617 pinctrl-names = "default";
618 pinctrl-0 = <&i2s1_bus>;
619 power-domains = <&pd_mau>;
620 #sound-dai-cells = <1>;
621 };
622
623 i2s2: i2s@12d70000 {
624 compatible = "samsung,s3c6410-i2s";
625 status = "disabled";
626 reg = <0x12D70000 0x100>;
627 dmas = <&pdma0 12>,
628 <&pdma0 11>;
629 dma-names = "tx", "rx";
630 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
631 clock-names = "iis", "i2s_opclk0";
632 pinctrl-names = "default";
633 pinctrl-0 = <&i2s2_bus>;
634 power-domains = <&pd_mau>;
635 #sound-dai-cells = <1>;
636 };
637
638 usbdrd: usb3 {
639 compatible = "samsung,exynos5250-dwusb3";
640 clocks = <&clock CLK_USB3>;
641 clock-names = "usbdrd30";
642 #address-cells = <1>;
643 #size-cells = <1>;
644 ranges;
645
646 usbdrd_dwc3: usb@12000000 {
647 compatible = "snps,dwc3";
648 reg = <0x12000000 0x10000>;
649 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
650 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
651 phy-names = "usb2-phy", "usb3-phy";
652 };
653 };
654
655 usbdrd_phy: phy@12100000 {
656 compatible = "samsung,exynos5250-usbdrd-phy";
657 reg = <0x12100000 0x100>;
658 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
659 clock-names = "phy", "ref";
660 samsung,pmu-syscon = <&pmu_system_controller>;
661 #phy-cells = <1>;
662 };
663
664 ehci: usb@12110000 {
665 compatible = "samsung,exynos4210-ehci";
666 reg = <0x12110000 0x100>;
667 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
668
669 clocks = <&clock CLK_USB2>;
670 clock-names = "usbhost";
671 phys = <&usb2_phy_gen 1>;
672 phy-names = "host";
673 };
674
675 ohci: usb@12120000 {
676 compatible = "samsung,exynos4210-ohci";
677 reg = <0x12120000 0x100>;
678 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
679
680 clocks = <&clock CLK_USB2>;
681 clock-names = "usbhost";
682 phys = <&usb2_phy_gen 1>;
683 phy-names = "host";
684 };
685
686 usb2_phy_gen: phy@12130000 {
687 compatible = "samsung,exynos5250-usb2-phy";
688 reg = <0x12130000 0x100>;
689 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
690 clock-names = "phy", "ref";
691 #phy-cells = <1>;
692 samsung,sysreg-phandle = <&sysreg_system_controller>;
693 samsung,pmureg-phandle = <&pmu_system_controller>;
694 };
695
696 pdma0: dma-controller@121a0000 {
697 compatible = "arm,pl330", "arm,primecell";
698 reg = <0x121A0000 0x1000>;
699 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&clock CLK_PDMA0>;
701 clock-names = "apb_pclk";
702 #dma-cells = <1>;
703 };
704
705 pdma1: dma-controller@121b0000 {
706 compatible = "arm,pl330", "arm,primecell";
707 reg = <0x121B0000 0x1000>;
708 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&clock CLK_PDMA1>;
710 clock-names = "apb_pclk";
711 #dma-cells = <1>;
712 };
713
714 mdma0: dma-controller@10800000 {
715 compatible = "arm,pl330", "arm,primecell";
716 reg = <0x10800000 0x1000>;
717 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clock CLK_MDMA0>;
719 clock-names = "apb_pclk";
720 #dma-cells = <1>;
721 };
722
723 mdma1: dma-controller@11c10000 {
724 compatible = "arm,pl330", "arm,primecell";
725 reg = <0x11C10000 0x1000>;
726 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clock CLK_MDMA1>;
728 clock-names = "apb_pclk";
729 #dma-cells = <1>;
730 };
731
732 gsc_0: gsc@13e00000 {
733 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
734 reg = <0x13e00000 0x1000>;
735 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
736 power-domains = <&pd_gsc>;
737 clocks = <&clock CLK_GSCL0>;
738 clock-names = "gscl";
739 iommus = <&sysmmu_gsc0>;
740 };
741
742 gsc_1: gsc@13e10000 {
743 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
744 reg = <0x13e10000 0x1000>;
745 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
746 power-domains = <&pd_gsc>;
747 clocks = <&clock CLK_GSCL1>;
748 clock-names = "gscl";
749 iommus = <&sysmmu_gsc1>;
750 };
751
752 gsc_2: gsc@13e20000 {
753 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
754 reg = <0x13e20000 0x1000>;
755 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
756 power-domains = <&pd_gsc>;
757 clocks = <&clock CLK_GSCL2>;
758 clock-names = "gscl";
759 iommus = <&sysmmu_gsc2>;
760 };
761
762 gsc_3: gsc@13e30000 {
763 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
764 reg = <0x13e30000 0x1000>;
765 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
766 power-domains = <&pd_gsc>;
767 clocks = <&clock CLK_GSCL3>;
768 clock-names = "gscl";
769 iommus = <&sysmmu_gsc3>;
770 };
771
772 hdmi: hdmi@14530000 {
773 compatible = "samsung,exynos4212-hdmi";
774 reg = <0x14530000 0x70000>;
775 power-domains = <&pd_disp1>;
776 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
778 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
779 <&clock CLK_MOUT_HDMI>;
780 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
781 "sclk_hdmiphy", "mout_hdmi";
782 samsung,syscon-phandle = <&pmu_system_controller>;
783 phy = <&hdmiphy>;
784 #sound-dai-cells = <0>;
785 status = "disabled";
786 };
787
788 hdmicec: cec@101b0000 {
789 compatible = "samsung,s5p-cec";
790 reg = <0x101B0000 0x200>;
791 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clock CLK_HDMI_CEC>;
793 clock-names = "hdmicec";
794 samsung,syscon-phandle = <&pmu_system_controller>;
795 hdmi-phandle = <&hdmi>;
796 pinctrl-names = "default";
797 pinctrl-0 = <&hdmi_cec>;
798 status = "disabled";
799 };
800
801 mixer: mixer@14450000 {
802 compatible = "samsung,exynos5250-mixer";
803 reg = <0x14450000 0x10000>;
804 power-domains = <&pd_disp1>;
805 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
807 <&clock CLK_SCLK_HDMI>;
808 clock-names = "mixer", "hdmi", "sclk_hdmi";
809 iommus = <&sysmmu_tv>;
810 status = "disabled";
811 };
812
813 dp_phy: video-phy-0 {
814 compatible = "samsung,exynos5250-dp-video-phy";
815 samsung,pmu-syscon = <&pmu_system_controller>;
816 #phy-cells = <0>;
817 };
818
819 mipi_phy: video-phy-1 {
820 compatible = "samsung,s5pv210-mipi-video-phy";
821 #phy-cells = <1>;
822 syscon = <&pmu_system_controller>;
823 };
824
825 dsi_0: dsi@14500000 {
826 compatible = "samsung,exynos4210-mipi-dsi";
827 reg = <0x14500000 0x10000>;
828 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
829 samsung,power-domain = <&pd_disp1>;
830 phys = <&mipi_phy 3>;
831 phy-names = "dsim";
832 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
833 clock-names = "bus_clk", "sclk_mipi";
834 status = "disabled";
835 #address-cells = <1>;
836 #size-cells = <0>;
837 };
838
839 adc: adc@12d10000 {
840 compatible = "samsung,exynos-adc-v1";
841 reg = <0x12D10000 0x100>;
842 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&clock CLK_ADC>;
844 clock-names = "adc";
845 #io-channel-cells = <1>;
846 samsung,syscon-phandle = <&pmu_system_controller>;
847 status = "disabled";
848 };
849
850 sysmmu_g2d: sysmmu@10a60000 {
851 compatible = "samsung,exynos-sysmmu";
852 reg = <0x10A60000 0x1000>;
853 interrupt-parent = <&combiner>;
854 interrupts = <24 5>;
855 clock-names = "sysmmu", "master";
856 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
857 #iommu-cells = <0>;
858 };
859
860 sysmmu_mfc_r: sysmmu@11200000 {
861 compatible = "samsung,exynos-sysmmu";
862 reg = <0x11200000 0x1000>;
863 interrupt-parent = <&combiner>;
864 interrupts = <6 2>;
865 power-domains = <&pd_mfc>;
866 clock-names = "sysmmu", "master";
867 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
868 #iommu-cells = <0>;
869 };
870
871 sysmmu_mfc_l: sysmmu@11210000 {
872 compatible = "samsung,exynos-sysmmu";
873 reg = <0x11210000 0x1000>;
874 interrupt-parent = <&combiner>;
875 interrupts = <8 5>;
876 power-domains = <&pd_mfc>;
877 clock-names = "sysmmu", "master";
878 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
879 #iommu-cells = <0>;
880 };
881
882 sysmmu_rotator: sysmmu@11d40000 {
883 compatible = "samsung,exynos-sysmmu";
884 reg = <0x11D40000 0x1000>;
885 interrupt-parent = <&combiner>;
886 interrupts = <4 0>;
887 clock-names = "sysmmu", "master";
888 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
889 #iommu-cells = <0>;
890 };
891
892 sysmmu_jpeg: sysmmu@11f20000 {
893 compatible = "samsung,exynos-sysmmu";
894 reg = <0x11F20000 0x1000>;
895 interrupt-parent = <&combiner>;
896 interrupts = <4 2>;
897 power-domains = <&pd_gsc>;
898 clock-names = "sysmmu", "master";
899 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
900 #iommu-cells = <0>;
901 };
902
903 sysmmu_fimc_isp: sysmmu@13260000 {
904 compatible = "samsung,exynos-sysmmu";
905 reg = <0x13260000 0x1000>;
906 interrupt-parent = <&combiner>;
907 interrupts = <10 6>;
908 clock-names = "sysmmu";
909 clocks = <&clock CLK_SMMU_FIMC_ISP>;
910 #iommu-cells = <0>;
911 };
912
913 sysmmu_fimc_drc: sysmmu@13270000 {
914 compatible = "samsung,exynos-sysmmu";
915 reg = <0x13270000 0x1000>;
916 interrupt-parent = <&combiner>;
917 interrupts = <11 6>;
918 clock-names = "sysmmu";
919 clocks = <&clock CLK_SMMU_FIMC_DRC>;
920 #iommu-cells = <0>;
921 };
922
923 sysmmu_fimc_fd: sysmmu@132a0000 {
924 compatible = "samsung,exynos-sysmmu";
925 reg = <0x132A0000 0x1000>;
926 interrupt-parent = <&combiner>;
927 interrupts = <5 0>;
928 clock-names = "sysmmu";
929 clocks = <&clock CLK_SMMU_FIMC_FD>;
930 #iommu-cells = <0>;
931 };
932
933 sysmmu_fimc_scc: sysmmu@13280000 {
934 compatible = "samsung,exynos-sysmmu";
935 reg = <0x13280000 0x1000>;
936 interrupt-parent = <&combiner>;
937 interrupts = <5 2>;
938 clock-names = "sysmmu";
939 clocks = <&clock CLK_SMMU_FIMC_SCC>;
940 #iommu-cells = <0>;
941 };
942
943 sysmmu_fimc_scp: sysmmu@13290000 {
944 compatible = "samsung,exynos-sysmmu";
945 reg = <0x13290000 0x1000>;
946 interrupt-parent = <&combiner>;
947 interrupts = <3 6>;
948 clock-names = "sysmmu";
949 clocks = <&clock CLK_SMMU_FIMC_SCP>;
950 #iommu-cells = <0>;
951 };
952
953 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
954 compatible = "samsung,exynos-sysmmu";
955 reg = <0x132B0000 0x1000>;
956 interrupt-parent = <&combiner>;
957 interrupts = <5 4>;
958 clock-names = "sysmmu";
959 clocks = <&clock CLK_SMMU_FIMC_MCU>;
960 #iommu-cells = <0>;
961 };
962
963 sysmmu_fimc_odc: sysmmu@132c0000 {
964 compatible = "samsung,exynos-sysmmu";
965 reg = <0x132C0000 0x1000>;
966 interrupt-parent = <&combiner>;
967 interrupts = <11 0>;
968 clock-names = "sysmmu";
969 clocks = <&clock CLK_SMMU_FIMC_ODC>;
970 #iommu-cells = <0>;
971 };
972
973 sysmmu_fimc_dis0: sysmmu@132d0000 {
974 compatible = "samsung,exynos-sysmmu";
975 reg = <0x132D0000 0x1000>;
976 interrupt-parent = <&combiner>;
977 interrupts = <10 4>;
978 clock-names = "sysmmu";
979 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
980 #iommu-cells = <0>;
981 };
982
983 sysmmu_fimc_dis1: sysmmu@132e0000 {
984 compatible = "samsung,exynos-sysmmu";
985 reg = <0x132E0000 0x1000>;
986 interrupt-parent = <&combiner>;
987 interrupts = <9 4>;
988 clock-names = "sysmmu";
989 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
990 #iommu-cells = <0>;
991 };
992
993 sysmmu_fimc_3dnr: sysmmu@132f0000 {
994 compatible = "samsung,exynos-sysmmu";
995 reg = <0x132F0000 0x1000>;
996 interrupt-parent = <&combiner>;
997 interrupts = <5 6>;
998 clock-names = "sysmmu";
999 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
1000 #iommu-cells = <0>;
1001 };
1002
1003 sysmmu_fimc_lite0: sysmmu@13c40000 {
1004 compatible = "samsung,exynos-sysmmu";
1005 reg = <0x13C40000 0x1000>;
1006 interrupt-parent = <&combiner>;
1007 interrupts = <3 4>;
1008 power-domains = <&pd_gsc>;
1009 clock-names = "sysmmu", "master";
1010 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1011 #iommu-cells = <0>;
1012 };
1013
1014 sysmmu_fimc_lite1: sysmmu@13c50000 {
1015 compatible = "samsung,exynos-sysmmu";
1016 reg = <0x13C50000 0x1000>;
1017 interrupt-parent = <&combiner>;
1018 interrupts = <24 1>;
1019 power-domains = <&pd_gsc>;
1020 clock-names = "sysmmu", "master";
1021 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1022 #iommu-cells = <0>;
1023 };
1024
1025 sysmmu_gsc0: sysmmu@13e80000 {
1026 compatible = "samsung,exynos-sysmmu";
1027 reg = <0x13E80000 0x1000>;
1028 interrupt-parent = <&combiner>;
1029 interrupts = <2 0>;
1030 power-domains = <&pd_gsc>;
1031 clock-names = "sysmmu", "master";
1032 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1033 #iommu-cells = <0>;
1034 };
1035
1036 sysmmu_gsc1: sysmmu@13e90000 {
1037 compatible = "samsung,exynos-sysmmu";
1038 reg = <0x13E90000 0x1000>;
1039 interrupt-parent = <&combiner>;
1040 interrupts = <2 2>;
1041 power-domains = <&pd_gsc>;
1042 clock-names = "sysmmu", "master";
1043 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1044 #iommu-cells = <0>;
1045 };
1046
1047 sysmmu_gsc2: sysmmu@13ea0000 {
1048 compatible = "samsung,exynos-sysmmu";
1049 reg = <0x13EA0000 0x1000>;
1050 interrupt-parent = <&combiner>;
1051 interrupts = <2 4>;
1052 power-domains = <&pd_gsc>;
1053 clock-names = "sysmmu", "master";
1054 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1055 #iommu-cells = <0>;
1056 };
1057
1058 sysmmu_gsc3: sysmmu@13eb0000 {
1059 compatible = "samsung,exynos-sysmmu";
1060 reg = <0x13EB0000 0x1000>;
1061 interrupt-parent = <&combiner>;
1062 interrupts = <2 6>;
1063 power-domains = <&pd_gsc>;
1064 clock-names = "sysmmu", "master";
1065 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1066 #iommu-cells = <0>;
1067 };
1068
1069 sysmmu_fimd1: sysmmu@14640000 {
1070 compatible = "samsung,exynos-sysmmu";
1071 reg = <0x14640000 0x1000>;
1072 interrupt-parent = <&combiner>;
1073 interrupts = <3 2>;
1074 power-domains = <&pd_disp1>;
1075 clock-names = "sysmmu", "master";
1076 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1077 #iommu-cells = <0>;
1078 };
1079
1080 sysmmu_tv: sysmmu@14650000 {
1081 compatible = "samsung,exynos-sysmmu";
1082 reg = <0x14650000 0x1000>;
1083 interrupt-parent = <&combiner>;
1084 interrupts = <7 4>;
1085 power-domains = <&pd_disp1>;
1086 clock-names = "sysmmu", "master";
1087 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1088 #iommu-cells = <0>;
1089 };
1090 };
1091
1092 timer {
1093 compatible = "arm,armv7-timer";
1094 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1095 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1096 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1097 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1098 /*
1099 * Unfortunately we need this since some versions
1100 * of U-Boot on Exynos don't set the CNTFRQ register,
1101 * so we need the value from DT.
1102 */
1103 clock-frequency = <24000000>;
1104 };
1105};
1106
1107&cpu_thermal {
1108 polling-delay-passive = <0>;
1109 polling-delay = <0>;
1110 thermal-sensors = <&tmu 0>;
1111
1112 cooling-maps {
1113 map0 {
1114 /* Corresponds to 800MHz at freq_table */
1115 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1116 };
1117 map1 {
1118 /* Corresponds to 200MHz at freq_table */
1119 cooling-device = <&cpu0 15 15>,
1120 <&cpu1 15 15>;
1121 };
1122 };
1123};
1124
1125&dp {
1126 power-domains = <&pd_disp1>;
1127 clocks = <&clock CLK_DP>;
1128 clock-names = "dp";
1129 phys = <&dp_phy>;
1130 phy-names = "dp";
1131};
1132
1133&fimd {
1134 power-domains = <&pd_disp1>;
1135 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1136 clock-names = "sclk_fimd", "fimd";
1137 iommus = <&sysmmu_fimd1>;
1138};
1139
1140&g2d {
1141 iommus = <&sysmmu_g2d>;
1142 clocks = <&clock CLK_G2D>;
1143 clock-names = "fimg2d";
1144 status = "okay";
1145};
1146
1147&i2c_0 {
1148 clocks = <&clock CLK_I2C0>;
1149 clock-names = "i2c";
1150 pinctrl-names = "default";
1151 pinctrl-0 = <&i2c0_bus>;
1152};
1153
1154&i2c_1 {
1155 clocks = <&clock CLK_I2C1>;
1156 clock-names = "i2c";
1157 pinctrl-names = "default";
1158 pinctrl-0 = <&i2c1_bus>;
1159};
1160
1161&i2c_2 {
1162 clocks = <&clock CLK_I2C2>;
1163 clock-names = "i2c";
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&i2c2_bus>;
1166};
1167
1168&i2c_3 {
1169 clocks = <&clock CLK_I2C3>;
1170 clock-names = "i2c";
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&i2c3_bus>;
1173};
1174
1175&prng {
1176 clocks = <&clock CLK_SSS>;
1177 clock-names = "secss";
1178};
1179
1180&pwm {
1181 clocks = <&clock CLK_PWM>;
1182 clock-names = "timers";
1183};
1184
1185&rtc {
1186 clocks = <&clock CLK_RTC>;
1187 clock-names = "rtc";
1188 interrupt-parent = <&pmu_system_controller>;
1189 status = "disabled";
1190};
1191
1192&serial_0 {
1193 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1194 clock-names = "uart", "clk_uart_baud0";
1195 dmas = <&pdma0 13>, <&pdma0 14>;
1196 dma-names = "rx", "tx";
1197};
1198
1199&serial_1 {
1200 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1201 clock-names = "uart", "clk_uart_baud0";
1202 dmas = <&pdma1 15>, <&pdma1 16>;
1203 dma-names = "rx", "tx";
1204};
1205
1206&serial_2 {
1207 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1208 clock-names = "uart", "clk_uart_baud0";
1209 dmas = <&pdma0 15>, <&pdma0 16>;
1210 dma-names = "rx", "tx";
1211};
1212
1213&serial_3 {
1214 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1215 clock-names = "uart", "clk_uart_baud0";
1216 dmas = <&pdma1 17>, <&pdma1 18>;
1217 dma-names = "rx", "tx";
1218};
1219
1220&sss {
1221 clocks = <&clock CLK_SSS>;
1222 clock-names = "secss";
1223};
1224
1225&trng {
1226 clocks = <&clock CLK_SSS>;
1227 clock-names = "secss";
1228};
1229
1230#include "exynos5250-pinctrl.dtsi"
1231#include "exynos-syscon-restart.dtsi"