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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SAMSUNG EXYNOS5250 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
9 * EXYNOS5250 based board files can include this file and provide
10 * values for board specfic bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
14 * additional nodes can be added to this file.
15 */
16
17#include <dt-bindings/clock/exynos5250.h>
18#include "exynos5.dtsi"
19#include "exynos4-cpu-thermal.dtsi"
20#include <dt-bindings/clock/exynos-audss-clk.h>
21
22/ {
23 compatible = "samsung,exynos5250", "samsung,exynos5";
24
25 aliases {
26 spi0 = &spi_0;
27 spi1 = &spi_1;
28 spi2 = &spi_2;
29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3;
33 mshc0 = &mmc_0;
34 mshc1 = &mmc_1;
35 mshc2 = &mmc_2;
36 mshc3 = &mmc_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 i2c9 = &i2c_9;
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a15";
56 reg = <0>;
57 clock-frequency = <1700000000>;
58 clocks = <&clock CLK_ARM_CLK>;
59 clock-names = "cpu";
60 clock-latency = <140000>;
61
62 operating-points = <
63 1700000 1300000
64 1600000 1250000
65 1500000 1225000
66 1400000 1200000
67 1300000 1150000
68 1200000 1125000
69 1100000 1100000
70 1000000 1075000
71 900000 1050000
72 800000 1025000
73 700000 1012500
74 600000 1000000
75 500000 975000
76 400000 950000
77 300000 937500
78 200000 925000
79 >;
80 #cooling-cells = <2>; /* min followed by max */
81 };
82 cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <1>;
86 clock-frequency = <1700000000>;
87 };
88 };
89
90 soc: soc {
91 sysram@2020000 {
92 compatible = "mmio-sram";
93 reg = <0x02020000 0x30000>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges = <0 0x02020000 0x30000>;
97
98 smp-sysram@0 {
99 compatible = "samsung,exynos4210-sysram";
100 reg = <0x0 0x1000>;
101 };
102
103 smp-sysram@2f000 {
104 compatible = "samsung,exynos4210-sysram-ns";
105 reg = <0x2f000 0x1000>;
106 };
107 };
108
109 pd_gsc: power-domain@10044000 {
110 compatible = "samsung,exynos4210-pd";
111 reg = <0x10044000 0x20>;
112 #power-domain-cells = <0>;
113 label = "GSC";
114 };
115
116 pd_mfc: power-domain@10044040 {
117 compatible = "samsung,exynos4210-pd";
118 reg = <0x10044040 0x20>;
119 #power-domain-cells = <0>;
120 label = "MFC";
121 };
122
123 pd_g3d: power-domain@10044060 {
124 compatible = "samsung,exynos4210-pd";
125 reg = <0x10044060 0x20>;
126 #power-domain-cells = <0>;
127 label = "G3D";
128 };
129
130 pd_disp1: power-domain@100440a0 {
131 compatible = "samsung,exynos4210-pd";
132 reg = <0x100440A0 0x20>;
133 #power-domain-cells = <0>;
134 label = "DISP1";
135 clocks = <&clock CLK_FIN_PLL>,
136 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
137 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
138 clock-names = "oscclk", "clk0", "clk1";
139 };
140
141 pd_mau: power-domain@100440c0 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x100440C0 0x20>;
144 #power-domain-cells = <0>;
145 label = "MAU";
146 };
147
148 clock: clock-controller@10010000 {
149 compatible = "samsung,exynos5250-clock";
150 reg = <0x10010000 0x30000>;
151 #clock-cells = <1>;
152 };
153
154 clock_audss: audss-clock-controller@3810000 {
155 compatible = "samsung,exynos5250-audss-clock";
156 reg = <0x03810000 0x0C>;
157 #clock-cells = <1>;
158 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
159 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
160 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
161 power-domains = <&pd_mau>;
162 };
163
164 timer {
165 compatible = "arm,armv7-timer";
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
170 /*
171 * Unfortunately we need this since some versions
172 * of U-Boot on Exynos don't set the CNTFRQ register,
173 * so we need the value from DT.
174 */
175 clock-frequency = <24000000>;
176 };
177
178 mct@101c0000 {
179 compatible = "samsung,exynos4210-mct";
180 reg = <0x101C0000 0x800>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
183 interrupt-parent = <&mct_map>;
184 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
185 <4 0>, <5 0>;
186 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
187 clock-names = "fin_pll", "mct";
188
189 mct_map: mct-map {
190 #interrupt-cells = <2>;
191 #address-cells = <0>;
192 #size-cells = <0>;
193 interrupt-map = <0x0 0 &combiner 23 3>,
194 <0x1 0 &combiner 23 4>,
195 <0x2 0 &combiner 25 2>,
196 <0x3 0 &combiner 25 3>,
197 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
198 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
199 };
200 };
201
202 pmu {
203 compatible = "arm,cortex-a15-pmu";
204 interrupt-parent = <&combiner>;
205 interrupts = <1 2>, <22 4>;
206 };
207
208 pinctrl_0: pinctrl@11400000 {
209 compatible = "samsung,exynos5250-pinctrl";
210 reg = <0x11400000 0x1000>;
211 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
212
213 wakup_eint: wakeup-interrupt-controller {
214 compatible = "samsung,exynos4210-wakeup-eint";
215 interrupt-parent = <&gic>;
216 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
217 };
218 };
219
220 pinctrl_1: pinctrl@13400000 {
221 compatible = "samsung,exynos5250-pinctrl";
222 reg = <0x13400000 0x1000>;
223 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
224 };
225
226 pinctrl_2: pinctrl@10d10000 {
227 compatible = "samsung,exynos5250-pinctrl";
228 reg = <0x10d10000 0x1000>;
229 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
230 };
231
232 pinctrl_3: pinctrl@3860000 {
233 compatible = "samsung,exynos5250-pinctrl";
234 reg = <0x03860000 0x1000>;
235 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
236 power-domains = <&pd_mau>;
237 };
238
239 pmu_system_controller: system-controller@10040000 {
240 compatible = "samsung,exynos5250-pmu", "syscon";
241 reg = <0x10040000 0x5000>;
242 clock-names = "clkout16";
243 clocks = <&clock CLK_FIN_PLL>;
244 #clock-cells = <1>;
245 interrupt-controller;
246 #interrupt-cells = <3>;
247 interrupt-parent = <&gic>;
248 };
249
250 watchdog@101d0000 {
251 compatible = "samsung,exynos5250-wdt";
252 reg = <0x101D0000 0x100>;
253 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clock CLK_WDT>;
255 clock-names = "watchdog";
256 samsung,syscon-phandle = <&pmu_system_controller>;
257 };
258
259 mfc: codec@11000000 {
260 compatible = "samsung,mfc-v6";
261 reg = <0x11000000 0x10000>;
262 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
263 power-domains = <&pd_mfc>;
264 clocks = <&clock CLK_MFC>;
265 clock-names = "mfc";
266 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
267 iommu-names = "left", "right";
268 };
269
270 rotator: rotator@11c00000 {
271 compatible = "samsung,exynos5250-rotator";
272 reg = <0x11C00000 0x64>;
273 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clock CLK_ROTATOR>;
275 clock-names = "rotator";
276 iommus = <&sysmmu_rotator>;
277 };
278
279 tmu: tmu@10060000 {
280 compatible = "samsung,exynos5250-tmu";
281 reg = <0x10060000 0x100>;
282 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clock CLK_TMU>;
284 clock-names = "tmu_apbif";
285 #include "exynos4412-tmu-sensor-conf.dtsi"
286 };
287
288 sata: sata@122f0000 {
289 compatible = "snps,dwc-ahci";
290 samsung,sata-freq = <66>;
291 reg = <0x122F0000 0x1ff>;
292 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
294 clock-names = "sata", "sclk_sata";
295 phys = <&sata_phy>;
296 phy-names = "sata-phy";
297 status = "disabled";
298 };
299
300 sata_phy: sata-phy@12170000 {
301 compatible = "samsung,exynos5250-sata-phy";
302 reg = <0x12170000 0x1ff>;
303 clocks = <&clock CLK_SATA_PHYCTRL>;
304 clock-names = "sata_phyctrl";
305 #phy-cells = <0>;
306 samsung,syscon-phandle = <&pmu_system_controller>;
307 status = "disabled";
308 };
309
310 /* i2c_0-3 are defined in exynos5.dtsi */
311 i2c_4: i2c@12ca0000 {
312 compatible = "samsung,s3c2440-i2c";
313 reg = <0x12CA0000 0x100>;
314 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 clocks = <&clock CLK_I2C4>;
318 clock-names = "i2c";
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c4_bus>;
321 status = "disabled";
322 };
323
324 i2c_5: i2c@12cb0000 {
325 compatible = "samsung,s3c2440-i2c";
326 reg = <0x12CB0000 0x100>;
327 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
328 #address-cells = <1>;
329 #size-cells = <0>;
330 clocks = <&clock CLK_I2C5>;
331 clock-names = "i2c";
332 pinctrl-names = "default";
333 pinctrl-0 = <&i2c5_bus>;
334 status = "disabled";
335 };
336
337 i2c_6: i2c@12cc0000 {
338 compatible = "samsung,s3c2440-i2c";
339 reg = <0x12CC0000 0x100>;
340 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 clocks = <&clock CLK_I2C6>;
344 clock-names = "i2c";
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c6_bus>;
347 status = "disabled";
348 };
349
350 i2c_7: i2c@12cd0000 {
351 compatible = "samsung,s3c2440-i2c";
352 reg = <0x12CD0000 0x100>;
353 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 clocks = <&clock CLK_I2C7>;
357 clock-names = "i2c";
358 pinctrl-names = "default";
359 pinctrl-0 = <&i2c7_bus>;
360 status = "disabled";
361 };
362
363 i2c_8: i2c@12ce0000 {
364 compatible = "samsung,s3c2440-hdmiphy-i2c";
365 reg = <0x12CE0000 0x1000>;
366 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 clocks = <&clock CLK_I2C_HDMI>;
370 clock-names = "i2c";
371 status = "disabled";
372
373 hdmiphy: hdmiphy@38 {
374 compatible = "samsung,exynos4212-hdmiphy";
375 reg = <0x38>;
376 };
377 };
378
379 i2c_9: i2c@121d0000 {
380 compatible = "samsung,exynos5-sata-phy-i2c";
381 reg = <0x121D0000 0x100>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 clocks = <&clock CLK_SATA_PHYI2C>;
385 clock-names = "i2c";
386 status = "disabled";
387 };
388
389 spi_0: spi@12d20000 {
390 compatible = "samsung,exynos4210-spi";
391 status = "disabled";
392 reg = <0x12d20000 0x100>;
393 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
394 dmas = <&pdma0 5
395 &pdma0 4>;
396 dma-names = "tx", "rx";
397 #address-cells = <1>;
398 #size-cells = <0>;
399 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
400 clock-names = "spi", "spi_busclk0";
401 pinctrl-names = "default";
402 pinctrl-0 = <&spi0_bus>;
403 };
404
405 spi_1: spi@12d30000 {
406 compatible = "samsung,exynos4210-spi";
407 status = "disabled";
408 reg = <0x12d30000 0x100>;
409 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
410 dmas = <&pdma1 5
411 &pdma1 4>;
412 dma-names = "tx", "rx";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
416 clock-names = "spi", "spi_busclk0";
417 pinctrl-names = "default";
418 pinctrl-0 = <&spi1_bus>;
419 };
420
421 spi_2: spi@12d40000 {
422 compatible = "samsung,exynos4210-spi";
423 status = "disabled";
424 reg = <0x12d40000 0x100>;
425 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
426 dmas = <&pdma0 7
427 &pdma0 6>;
428 dma-names = "tx", "rx";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
432 clock-names = "spi", "spi_busclk0";
433 pinctrl-names = "default";
434 pinctrl-0 = <&spi2_bus>;
435 };
436
437 mmc_0: mmc@12200000 {
438 compatible = "samsung,exynos5250-dw-mshc";
439 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>;
441 #size-cells = <0>;
442 reg = <0x12200000 0x1000>;
443 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
444 clock-names = "biu", "ciu";
445 fifo-depth = <0x80>;
446 status = "disabled";
447 };
448
449 mmc_1: mmc@12210000 {
450 compatible = "samsung,exynos5250-dw-mshc";
451 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 reg = <0x12210000 0x1000>;
455 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
456 clock-names = "biu", "ciu";
457 fifo-depth = <0x80>;
458 status = "disabled";
459 };
460
461 mmc_2: mmc@12220000 {
462 compatible = "samsung,exynos5250-dw-mshc";
463 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 reg = <0x12220000 0x1000>;
467 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
468 clock-names = "biu", "ciu";
469 fifo-depth = <0x80>;
470 status = "disabled";
471 };
472
473 mmc_3: mmc@12230000 {
474 compatible = "samsung,exynos5250-dw-mshc";
475 reg = <0x12230000 0x1000>;
476 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
480 clock-names = "biu", "ciu";
481 fifo-depth = <0x80>;
482 status = "disabled";
483 };
484
485 i2s0: i2s@3830000 {
486 compatible = "samsung,s5pv210-i2s";
487 status = "disabled";
488 reg = <0x03830000 0x100>;
489 dmas = <&pdma0 10
490 &pdma0 9
491 &pdma0 8>;
492 dma-names = "tx", "rx", "tx-sec";
493 clocks = <&clock_audss EXYNOS_I2S_BUS>,
494 <&clock_audss EXYNOS_I2S_BUS>,
495 <&clock_audss EXYNOS_SCLK_I2S>;
496 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
497 samsung,idma-addr = <0x03000000>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&i2s0_bus>;
500 power-domains = <&pd_mau>;
501 #clock-cells = <1>;
502 #sound-dai-cells = <1>;
503 };
504
505 i2s1: i2s@12d60000 {
506 compatible = "samsung,s3c6410-i2s";
507 status = "disabled";
508 reg = <0x12D60000 0x100>;
509 dmas = <&pdma1 12
510 &pdma1 11>;
511 dma-names = "tx", "rx";
512 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
513 clock-names = "iis", "i2s_opclk0";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2s1_bus>;
516 power-domains = <&pd_mau>;
517 #sound-dai-cells = <1>;
518 };
519
520 i2s2: i2s@12d70000 {
521 compatible = "samsung,s3c6410-i2s";
522 status = "disabled";
523 reg = <0x12D70000 0x100>;
524 dmas = <&pdma0 12
525 &pdma0 11>;
526 dma-names = "tx", "rx";
527 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
528 clock-names = "iis", "i2s_opclk0";
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2s2_bus>;
531 power-domains = <&pd_mau>;
532 #sound-dai-cells = <1>;
533 };
534
535 usb_dwc3 {
536 compatible = "samsung,exynos5250-dwusb3";
537 clocks = <&clock CLK_USB3>;
538 clock-names = "usbdrd30";
539 #address-cells = <1>;
540 #size-cells = <1>;
541 ranges;
542
543 usbdrd_dwc3: dwc3@12000000 {
544 compatible = "synopsys,dwc3";
545 reg = <0x12000000 0x10000>;
546 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
547 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
548 phy-names = "usb2-phy", "usb3-phy";
549 };
550 };
551
552 usbdrd_phy: phy@12100000 {
553 compatible = "samsung,exynos5250-usbdrd-phy";
554 reg = <0x12100000 0x100>;
555 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
556 clock-names = "phy", "ref";
557 samsung,pmu-syscon = <&pmu_system_controller>;
558 #phy-cells = <1>;
559 };
560
561 ehci: usb@12110000 {
562 compatible = "samsung,exynos4210-ehci";
563 reg = <0x12110000 0x100>;
564 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
565
566 clocks = <&clock CLK_USB2>;
567 clock-names = "usbhost";
568 #address-cells = <1>;
569 #size-cells = <0>;
570 port@0 {
571 reg = <0>;
572 phys = <&usb2_phy_gen 1>;
573 };
574 };
575
576 ohci: usb@12120000 {
577 compatible = "samsung,exynos4210-ohci";
578 reg = <0x12120000 0x100>;
579 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
580
581 clocks = <&clock CLK_USB2>;
582 clock-names = "usbhost";
583 #address-cells = <1>;
584 #size-cells = <0>;
585 port@0 {
586 reg = <0>;
587 phys = <&usb2_phy_gen 1>;
588 };
589 };
590
591 usb2_phy_gen: phy@12130000 {
592 compatible = "samsung,exynos5250-usb2-phy";
593 reg = <0x12130000 0x100>;
594 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
595 clock-names = "phy", "ref";
596 #phy-cells = <1>;
597 samsung,sysreg-phandle = <&sysreg_system_controller>;
598 samsung,pmureg-phandle = <&pmu_system_controller>;
599 };
600
601 amba {
602 #address-cells = <1>;
603 #size-cells = <1>;
604 compatible = "simple-bus";
605 interrupt-parent = <&gic>;
606 ranges;
607
608 pdma0: pdma@121a0000 {
609 compatible = "arm,pl330", "arm,primecell";
610 reg = <0x121A0000 0x1000>;
611 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clock CLK_PDMA0>;
613 clock-names = "apb_pclk";
614 #dma-cells = <1>;
615 #dma-channels = <8>;
616 #dma-requests = <32>;
617 };
618
619 pdma1: pdma@121b0000 {
620 compatible = "arm,pl330", "arm,primecell";
621 reg = <0x121B0000 0x1000>;
622 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clock CLK_PDMA1>;
624 clock-names = "apb_pclk";
625 #dma-cells = <1>;
626 #dma-channels = <8>;
627 #dma-requests = <32>;
628 };
629
630 mdma0: mdma@10800000 {
631 compatible = "arm,pl330", "arm,primecell";
632 reg = <0x10800000 0x1000>;
633 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&clock CLK_MDMA0>;
635 clock-names = "apb_pclk";
636 #dma-cells = <1>;
637 #dma-channels = <8>;
638 #dma-requests = <1>;
639 };
640
641 mdma1: mdma@11c10000 {
642 compatible = "arm,pl330", "arm,primecell";
643 reg = <0x11C10000 0x1000>;
644 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clock CLK_MDMA1>;
646 clock-names = "apb_pclk";
647 #dma-cells = <1>;
648 #dma-channels = <8>;
649 #dma-requests = <1>;
650 };
651 };
652
653 gsc_0: gsc@13e00000 {
654 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
655 reg = <0x13e00000 0x1000>;
656 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
657 power-domains = <&pd_gsc>;
658 clocks = <&clock CLK_GSCL0>;
659 clock-names = "gscl";
660 iommus = <&sysmmu_gsc0>;
661 };
662
663 gsc_1: gsc@13e10000 {
664 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
665 reg = <0x13e10000 0x1000>;
666 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
667 power-domains = <&pd_gsc>;
668 clocks = <&clock CLK_GSCL1>;
669 clock-names = "gscl";
670 iommus = <&sysmmu_gsc1>;
671 };
672
673 gsc_2: gsc@13e20000 {
674 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
675 reg = <0x13e20000 0x1000>;
676 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
677 power-domains = <&pd_gsc>;
678 clocks = <&clock CLK_GSCL2>;
679 clock-names = "gscl";
680 iommus = <&sysmmu_gsc2>;
681 };
682
683 gsc_3: gsc@13e30000 {
684 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
685 reg = <0x13e30000 0x1000>;
686 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
687 power-domains = <&pd_gsc>;
688 clocks = <&clock CLK_GSCL3>;
689 clock-names = "gscl";
690 iommus = <&sysmmu_gsc3>;
691 };
692
693 hdmi: hdmi@14530000 {
694 compatible = "samsung,exynos4212-hdmi";
695 reg = <0x14530000 0x70000>;
696 power-domains = <&pd_disp1>;
697 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
699 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
700 <&clock CLK_MOUT_HDMI>;
701 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
702 "sclk_hdmiphy", "mout_hdmi";
703 samsung,syscon-phandle = <&pmu_system_controller>;
704 phy = <&hdmiphy>;
705 #sound-dai-cells = <0>;
706 status = "disabled";
707 };
708
709 hdmicec: cec@101b0000 {
710 compatible = "samsung,s5p-cec";
711 reg = <0x101B0000 0x200>;
712 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clock CLK_HDMI_CEC>;
714 clock-names = "hdmicec";
715 samsung,syscon-phandle = <&pmu_system_controller>;
716 hdmi-phandle = <&hdmi>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&hdmi_cec>;
719 status = "disabled";
720 };
721
722 mixer: mixer@14450000 {
723 compatible = "samsung,exynos5250-mixer";
724 reg = <0x14450000 0x10000>;
725 power-domains = <&pd_disp1>;
726 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
728 <&clock CLK_SCLK_HDMI>;
729 clock-names = "mixer", "hdmi", "sclk_hdmi";
730 iommus = <&sysmmu_tv>;
731 status = "disabled";
732 };
733
734 dp_phy: video-phy {
735 compatible = "samsung,exynos5250-dp-video-phy";
736 samsung,pmu-syscon = <&pmu_system_controller>;
737 #phy-cells = <0>;
738 };
739
740 adc: adc@12d10000 {
741 compatible = "samsung,exynos-adc-v1";
742 reg = <0x12D10000 0x100>;
743 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clock CLK_ADC>;
745 clock-names = "adc";
746 #io-channel-cells = <1>;
747 io-channel-ranges;
748 samsung,syscon-phandle = <&pmu_system_controller>;
749 status = "disabled";
750 };
751
752 sysmmu_g2d: sysmmu@10a60000 {
753 compatible = "samsung,exynos-sysmmu";
754 reg = <0x10A60000 0x1000>;
755 interrupt-parent = <&combiner>;
756 interrupts = <24 5>;
757 clock-names = "sysmmu", "master";
758 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
759 #iommu-cells = <0>;
760 };
761
762 sysmmu_mfc_r: sysmmu@11200000 {
763 compatible = "samsung,exynos-sysmmu";
764 reg = <0x11200000 0x1000>;
765 interrupt-parent = <&combiner>;
766 interrupts = <6 2>;
767 power-domains = <&pd_mfc>;
768 clock-names = "sysmmu", "master";
769 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
770 #iommu-cells = <0>;
771 };
772
773 sysmmu_mfc_l: sysmmu@11210000 {
774 compatible = "samsung,exynos-sysmmu";
775 reg = <0x11210000 0x1000>;
776 interrupt-parent = <&combiner>;
777 interrupts = <8 5>;
778 power-domains = <&pd_mfc>;
779 clock-names = "sysmmu", "master";
780 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
781 #iommu-cells = <0>;
782 };
783
784 sysmmu_rotator: sysmmu@11d40000 {
785 compatible = "samsung,exynos-sysmmu";
786 reg = <0x11D40000 0x1000>;
787 interrupt-parent = <&combiner>;
788 interrupts = <4 0>;
789 clock-names = "sysmmu", "master";
790 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
791 #iommu-cells = <0>;
792 };
793
794 sysmmu_jpeg: sysmmu@11f20000 {
795 compatible = "samsung,exynos-sysmmu";
796 reg = <0x11F20000 0x1000>;
797 interrupt-parent = <&combiner>;
798 interrupts = <4 2>;
799 power-domains = <&pd_gsc>;
800 clock-names = "sysmmu", "master";
801 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
802 #iommu-cells = <0>;
803 };
804
805 sysmmu_fimc_isp: sysmmu@13260000 {
806 compatible = "samsung,exynos-sysmmu";
807 reg = <0x13260000 0x1000>;
808 interrupt-parent = <&combiner>;
809 interrupts = <10 6>;
810 clock-names = "sysmmu";
811 clocks = <&clock CLK_SMMU_FIMC_ISP>;
812 #iommu-cells = <0>;
813 };
814
815 sysmmu_fimc_drc: sysmmu@13270000 {
816 compatible = "samsung,exynos-sysmmu";
817 reg = <0x13270000 0x1000>;
818 interrupt-parent = <&combiner>;
819 interrupts = <11 6>;
820 clock-names = "sysmmu";
821 clocks = <&clock CLK_SMMU_FIMC_DRC>;
822 #iommu-cells = <0>;
823 };
824
825 sysmmu_fimc_fd: sysmmu@132a0000 {
826 compatible = "samsung,exynos-sysmmu";
827 reg = <0x132A0000 0x1000>;
828 interrupt-parent = <&combiner>;
829 interrupts = <5 0>;
830 clock-names = "sysmmu";
831 clocks = <&clock CLK_SMMU_FIMC_FD>;
832 #iommu-cells = <0>;
833 };
834
835 sysmmu_fimc_scc: sysmmu@13280000 {
836 compatible = "samsung,exynos-sysmmu";
837 reg = <0x13280000 0x1000>;
838 interrupt-parent = <&combiner>;
839 interrupts = <5 2>;
840 clock-names = "sysmmu";
841 clocks = <&clock CLK_SMMU_FIMC_SCC>;
842 #iommu-cells = <0>;
843 };
844
845 sysmmu_fimc_scp: sysmmu@13290000 {
846 compatible = "samsung,exynos-sysmmu";
847 reg = <0x13290000 0x1000>;
848 interrupt-parent = <&combiner>;
849 interrupts = <3 6>;
850 clock-names = "sysmmu";
851 clocks = <&clock CLK_SMMU_FIMC_SCP>;
852 #iommu-cells = <0>;
853 };
854
855 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
856 compatible = "samsung,exynos-sysmmu";
857 reg = <0x132B0000 0x1000>;
858 interrupt-parent = <&combiner>;
859 interrupts = <5 4>;
860 clock-names = "sysmmu";
861 clocks = <&clock CLK_SMMU_FIMC_MCU>;
862 #iommu-cells = <0>;
863 };
864
865 sysmmu_fimc_odc: sysmmu@132c0000 {
866 compatible = "samsung,exynos-sysmmu";
867 reg = <0x132C0000 0x1000>;
868 interrupt-parent = <&combiner>;
869 interrupts = <11 0>;
870 clock-names = "sysmmu";
871 clocks = <&clock CLK_SMMU_FIMC_ODC>;
872 #iommu-cells = <0>;
873 };
874
875 sysmmu_fimc_dis0: sysmmu@132d0000 {
876 compatible = "samsung,exynos-sysmmu";
877 reg = <0x132D0000 0x1000>;
878 interrupt-parent = <&combiner>;
879 interrupts = <10 4>;
880 clock-names = "sysmmu";
881 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
882 #iommu-cells = <0>;
883 };
884
885 sysmmu_fimc_dis1: sysmmu@132E0000{
886 compatible = "samsung,exynos-sysmmu";
887 reg = <0x132E0000 0x1000>;
888 interrupt-parent = <&combiner>;
889 interrupts = <9 4>;
890 clock-names = "sysmmu";
891 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
892 #iommu-cells = <0>;
893 };
894
895 sysmmu_fimc_3dnr: sysmmu@132f0000 {
896 compatible = "samsung,exynos-sysmmu";
897 reg = <0x132F0000 0x1000>;
898 interrupt-parent = <&combiner>;
899 interrupts = <5 6>;
900 clock-names = "sysmmu";
901 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
902 #iommu-cells = <0>;
903 };
904
905 sysmmu_fimc_lite0: sysmmu@13c40000 {
906 compatible = "samsung,exynos-sysmmu";
907 reg = <0x13C40000 0x1000>;
908 interrupt-parent = <&combiner>;
909 interrupts = <3 4>;
910 power-domains = <&pd_gsc>;
911 clock-names = "sysmmu", "master";
912 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
913 #iommu-cells = <0>;
914 };
915
916 sysmmu_fimc_lite1: sysmmu@13c50000 {
917 compatible = "samsung,exynos-sysmmu";
918 reg = <0x13C50000 0x1000>;
919 interrupt-parent = <&combiner>;
920 interrupts = <24 1>;
921 power-domains = <&pd_gsc>;
922 clock-names = "sysmmu", "master";
923 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
924 #iommu-cells = <0>;
925 };
926
927 sysmmu_gsc0: sysmmu@13e80000 {
928 compatible = "samsung,exynos-sysmmu";
929 reg = <0x13E80000 0x1000>;
930 interrupt-parent = <&combiner>;
931 interrupts = <2 0>;
932 power-domains = <&pd_gsc>;
933 clock-names = "sysmmu", "master";
934 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
935 #iommu-cells = <0>;
936 };
937
938 sysmmu_gsc1: sysmmu@13e90000 {
939 compatible = "samsung,exynos-sysmmu";
940 reg = <0x13E90000 0x1000>;
941 interrupt-parent = <&combiner>;
942 interrupts = <2 2>;
943 power-domains = <&pd_gsc>;
944 clock-names = "sysmmu", "master";
945 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
946 #iommu-cells = <0>;
947 };
948
949 sysmmu_gsc2: sysmmu@13ea0000 {
950 compatible = "samsung,exynos-sysmmu";
951 reg = <0x13EA0000 0x1000>;
952 interrupt-parent = <&combiner>;
953 interrupts = <2 4>;
954 power-domains = <&pd_gsc>;
955 clock-names = "sysmmu", "master";
956 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
957 #iommu-cells = <0>;
958 };
959
960 sysmmu_gsc3: sysmmu@13eb0000 {
961 compatible = "samsung,exynos-sysmmu";
962 reg = <0x13EB0000 0x1000>;
963 interrupt-parent = <&combiner>;
964 interrupts = <2 6>;
965 power-domains = <&pd_gsc>;
966 clock-names = "sysmmu", "master";
967 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
968 #iommu-cells = <0>;
969 };
970
971 sysmmu_fimd1: sysmmu@14640000 {
972 compatible = "samsung,exynos-sysmmu";
973 reg = <0x14640000 0x1000>;
974 interrupt-parent = <&combiner>;
975 interrupts = <3 2>;
976 power-domains = <&pd_disp1>;
977 clock-names = "sysmmu", "master";
978 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
979 #iommu-cells = <0>;
980 };
981
982 sysmmu_tv: sysmmu@14650000 {
983 compatible = "samsung,exynos-sysmmu";
984 reg = <0x14650000 0x1000>;
985 interrupt-parent = <&combiner>;
986 interrupts = <7 4>;
987 power-domains = <&pd_disp1>;
988 clock-names = "sysmmu", "master";
989 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
990 #iommu-cells = <0>;
991 };
992 };
993
994 thermal-zones {
995 cpu_thermal: cpu-thermal {
996 polling-delay-passive = <0>;
997 polling-delay = <0>;
998 thermal-sensors = <&tmu 0>;
999
1000 cooling-maps {
1001 map0 {
1002 /* Corresponds to 800MHz at freq_table */
1003 cooling-device = <&cpu0 9 9>;
1004 };
1005 map1 {
1006 /* Corresponds to 200MHz at freq_table */
1007 cooling-device = <&cpu0 15 15>;
1008 };
1009 };
1010 };
1011 };
1012};
1013
1014&dp {
1015 power-domains = <&pd_disp1>;
1016 clocks = <&clock CLK_DP>;
1017 clock-names = "dp";
1018 phys = <&dp_phy>;
1019 phy-names = "dp";
1020};
1021
1022&fimd {
1023 power-domains = <&pd_disp1>;
1024 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1025 clock-names = "sclk_fimd", "fimd";
1026 iommus = <&sysmmu_fimd1>;
1027};
1028
1029&g2d {
1030 iommus = <&sysmmu_g2d>;
1031 clocks = <&clock CLK_G2D>;
1032 clock-names = "fimg2d";
1033 status = "okay";
1034};
1035
1036&i2c_0 {
1037 clocks = <&clock CLK_I2C0>;
1038 clock-names = "i2c";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&i2c0_bus>;
1041};
1042
1043&i2c_1 {
1044 clocks = <&clock CLK_I2C1>;
1045 clock-names = "i2c";
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&i2c1_bus>;
1048};
1049
1050&i2c_2 {
1051 clocks = <&clock CLK_I2C2>;
1052 clock-names = "i2c";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&i2c2_bus>;
1055};
1056
1057&i2c_3 {
1058 clocks = <&clock CLK_I2C3>;
1059 clock-names = "i2c";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&i2c3_bus>;
1062};
1063
1064&prng {
1065 clocks = <&clock CLK_SSS>;
1066 clock-names = "secss";
1067};
1068
1069&pwm {
1070 clocks = <&clock CLK_PWM>;
1071 clock-names = "timers";
1072};
1073
1074&rtc {
1075 clocks = <&clock CLK_RTC>;
1076 clock-names = "rtc";
1077 interrupt-parent = <&pmu_system_controller>;
1078 status = "disabled";
1079};
1080
1081&serial_0 {
1082 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1083 clock-names = "uart", "clk_uart_baud0";
1084 dmas = <&pdma0 13>, <&pdma0 14>;
1085 dma-names = "rx", "tx";
1086};
1087
1088&serial_1 {
1089 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1090 clock-names = "uart", "clk_uart_baud0";
1091 dmas = <&pdma1 15>, <&pdma1 16>;
1092 dma-names = "rx", "tx";
1093};
1094
1095&serial_2 {
1096 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1097 clock-names = "uart", "clk_uart_baud0";
1098 dmas = <&pdma0 15>, <&pdma0 16>;
1099 dma-names = "rx", "tx";
1100};
1101
1102&serial_3 {
1103 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1104 clock-names = "uart", "clk_uart_baud0";
1105 dmas = <&pdma1 17>, <&pdma1 18>;
1106 dma-names = "rx", "tx";
1107};
1108
1109&sss {
1110 clocks = <&clock CLK_SSS>;
1111 clock-names = "secss";
1112};
1113
1114&trng {
1115 clocks = <&clock CLK_SSS>;
1116 clock-names = "secss";
1117};
1118
1119#include "exynos5250-pinctrl.dtsi"
1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#include <dt-bindings/clock/exynos5250.h>
21#include "exynos5.dtsi"
22#include "exynos5250-pinctrl.dtsi"
23
24#include <dt-bindings/clock/exynos-audss-clk.h>
25
26/ {
27 compatible = "samsung,exynos5250", "samsung,exynos5";
28
29 aliases {
30 spi0 = &spi_0;
31 spi1 = &spi_1;
32 spi2 = &spi_2;
33 gsc0 = &gsc_0;
34 gsc1 = &gsc_1;
35 gsc2 = &gsc_2;
36 gsc3 = &gsc_3;
37 mshc0 = &mmc_0;
38 mshc1 = &mmc_1;
39 mshc2 = &mmc_2;
40 mshc3 = &mmc_3;
41 i2c0 = &i2c_0;
42 i2c1 = &i2c_1;
43 i2c2 = &i2c_2;
44 i2c3 = &i2c_3;
45 i2c4 = &i2c_4;
46 i2c5 = &i2c_5;
47 i2c6 = &i2c_6;
48 i2c7 = &i2c_7;
49 i2c8 = &i2c_8;
50 i2c9 = &i2c_9;
51 pinctrl0 = &pinctrl_0;
52 pinctrl1 = &pinctrl_1;
53 pinctrl2 = &pinctrl_2;
54 pinctrl3 = &pinctrl_3;
55 };
56
57 cpus {
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 cpu@0 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a15";
64 reg = <0>;
65 clock-frequency = <1700000000>;
66 };
67 cpu@1 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a15";
70 reg = <1>;
71 clock-frequency = <1700000000>;
72 };
73 };
74
75 pd_gsc: gsc-power-domain@10044000 {
76 compatible = "samsung,exynos4210-pd";
77 reg = <0x10044000 0x20>;
78 };
79
80 pd_mfc: mfc-power-domain@10044040 {
81 compatible = "samsung,exynos4210-pd";
82 reg = <0x10044040 0x20>;
83 };
84
85 clock: clock-controller@10010000 {
86 compatible = "samsung,exynos5250-clock";
87 reg = <0x10010000 0x30000>;
88 #clock-cells = <1>;
89 };
90
91 clock_audss: audss-clock-controller@3810000 {
92 compatible = "samsung,exynos5250-audss-clock";
93 reg = <0x03810000 0x0C>;
94 #clock-cells = <1>;
95 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
96 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
97 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
98 };
99
100 timer {
101 compatible = "arm,armv7-timer";
102 interrupts = <1 13 0xf08>,
103 <1 14 0xf08>,
104 <1 11 0xf08>,
105 <1 10 0xf08>;
106 /* Unfortunately we need this since some versions of U-Boot
107 * on Exynos don't set the CNTFRQ register, so we need the
108 * value from DT.
109 */
110 clock-frequency = <24000000>;
111 };
112
113 mct@101C0000 {
114 compatible = "samsung,exynos4210-mct";
115 reg = <0x101C0000 0x800>;
116 interrupt-controller;
117 #interrups-cells = <2>;
118 interrupt-parent = <&mct_map>;
119 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
120 <4 0>, <5 0>;
121 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
122 clock-names = "fin_pll", "mct";
123
124 mct_map: mct-map {
125 #interrupt-cells = <2>;
126 #address-cells = <0>;
127 #size-cells = <0>;
128 interrupt-map = <0x0 0 &combiner 23 3>,
129 <0x1 0 &combiner 23 4>,
130 <0x2 0 &combiner 25 2>,
131 <0x3 0 &combiner 25 3>,
132 <0x4 0 &gic 0 120 0>,
133 <0x5 0 &gic 0 121 0>;
134 };
135 };
136
137 pmu {
138 compatible = "arm,cortex-a15-pmu";
139 interrupt-parent = <&combiner>;
140 interrupts = <1 2>, <22 4>;
141 };
142
143 pinctrl_0: pinctrl@11400000 {
144 compatible = "samsung,exynos5250-pinctrl";
145 reg = <0x11400000 0x1000>;
146 interrupts = <0 46 0>;
147
148 wakup_eint: wakeup-interrupt-controller {
149 compatible = "samsung,exynos4210-wakeup-eint";
150 interrupt-parent = <&gic>;
151 interrupts = <0 32 0>;
152 };
153 };
154
155 pinctrl_1: pinctrl@13400000 {
156 compatible = "samsung,exynos5250-pinctrl";
157 reg = <0x13400000 0x1000>;
158 interrupts = <0 45 0>;
159 };
160
161 pinctrl_2: pinctrl@10d10000 {
162 compatible = "samsung,exynos5250-pinctrl";
163 reg = <0x10d10000 0x1000>;
164 interrupts = <0 50 0>;
165 };
166
167 pinctrl_3: pinctrl@03860000 {
168 compatible = "samsung,exynos5250-pinctrl";
169 reg = <0x03860000 0x1000>;
170 interrupts = <0 47 0>;
171 };
172
173 pmu_system_controller: system-controller@10040000 {
174 compatible = "samsung,exynos5250-pmu", "syscon";
175 reg = <0x10040000 0x5000>;
176 };
177
178 watchdog@101D0000 {
179 compatible = "samsung,exynos5250-wdt";
180 reg = <0x101D0000 0x100>;
181 interrupts = <0 42 0>;
182 clocks = <&clock CLK_WDT>;
183 clock-names = "watchdog";
184 samsung,syscon-phandle = <&pmu_system_controller>;
185 };
186
187 g2d@10850000 {
188 compatible = "samsung,exynos5250-g2d";
189 reg = <0x10850000 0x1000>;
190 interrupts = <0 91 0>;
191 clocks = <&clock CLK_G2D>;
192 clock-names = "fimg2d";
193 };
194
195 codec@11000000 {
196 compatible = "samsung,mfc-v6";
197 reg = <0x11000000 0x10000>;
198 interrupts = <0 96 0>;
199 samsung,power-domain = <&pd_mfc>;
200 clocks = <&clock CLK_MFC>;
201 clock-names = "mfc";
202 };
203
204 rtc@101E0000 {
205 clocks = <&clock CLK_RTC>;
206 clock-names = "rtc";
207 status = "disabled";
208 };
209
210 tmu@10060000 {
211 compatible = "samsung,exynos5250-tmu";
212 reg = <0x10060000 0x100>;
213 interrupts = <0 65 0>;
214 clocks = <&clock CLK_TMU>;
215 clock-names = "tmu_apbif";
216 };
217
218 serial@12C00000 {
219 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
220 clock-names = "uart", "clk_uart_baud0";
221 };
222
223 serial@12C10000 {
224 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
225 clock-names = "uart", "clk_uart_baud0";
226 };
227
228 serial@12C20000 {
229 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
230 clock-names = "uart", "clk_uart_baud0";
231 };
232
233 serial@12C30000 {
234 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
235 clock-names = "uart", "clk_uart_baud0";
236 };
237
238 sata@122F0000 {
239 compatible = "snps,dwc-ahci";
240 samsung,sata-freq = <66>;
241 reg = <0x122F0000 0x1ff>;
242 interrupts = <0 115 0>;
243 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
244 clock-names = "sata", "sclk_sata";
245 phys = <&sata_phy>;
246 phy-names = "sata-phy";
247 status = "disabled";
248 };
249
250 sata_phy: sata-phy@12170000 {
251 compatible = "samsung,exynos5250-sata-phy";
252 reg = <0x12170000 0x1ff>;
253 clocks = <&clock 287>;
254 clock-names = "sata_phyctrl";
255 #phy-cells = <0>;
256 samsung,syscon-phandle = <&pmu_system_controller>;
257 status = "disabled";
258 };
259
260 i2c_0: i2c@12C60000 {
261 compatible = "samsung,s3c2440-i2c";
262 reg = <0x12C60000 0x100>;
263 interrupts = <0 56 0>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 clocks = <&clock CLK_I2C0>;
267 clock-names = "i2c";
268 pinctrl-names = "default";
269 pinctrl-0 = <&i2c0_bus>;
270 status = "disabled";
271 };
272
273 i2c_1: i2c@12C70000 {
274 compatible = "samsung,s3c2440-i2c";
275 reg = <0x12C70000 0x100>;
276 interrupts = <0 57 0>;
277 #address-cells = <1>;
278 #size-cells = <0>;
279 clocks = <&clock CLK_I2C1>;
280 clock-names = "i2c";
281 pinctrl-names = "default";
282 pinctrl-0 = <&i2c1_bus>;
283 status = "disabled";
284 };
285
286 i2c_2: i2c@12C80000 {
287 compatible = "samsung,s3c2440-i2c";
288 reg = <0x12C80000 0x100>;
289 interrupts = <0 58 0>;
290 #address-cells = <1>;
291 #size-cells = <0>;
292 clocks = <&clock CLK_I2C2>;
293 clock-names = "i2c";
294 pinctrl-names = "default";
295 pinctrl-0 = <&i2c2_bus>;
296 status = "disabled";
297 };
298
299 i2c_3: i2c@12C90000 {
300 compatible = "samsung,s3c2440-i2c";
301 reg = <0x12C90000 0x100>;
302 interrupts = <0 59 0>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 clocks = <&clock CLK_I2C3>;
306 clock-names = "i2c";
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2c3_bus>;
309 status = "disabled";
310 };
311
312 i2c_4: i2c@12CA0000 {
313 compatible = "samsung,s3c2440-i2c";
314 reg = <0x12CA0000 0x100>;
315 interrupts = <0 60 0>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318 clocks = <&clock CLK_I2C4>;
319 clock-names = "i2c";
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c4_bus>;
322 status = "disabled";
323 };
324
325 i2c_5: i2c@12CB0000 {
326 compatible = "samsung,s3c2440-i2c";
327 reg = <0x12CB0000 0x100>;
328 interrupts = <0 61 0>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 clocks = <&clock CLK_I2C5>;
332 clock-names = "i2c";
333 pinctrl-names = "default";
334 pinctrl-0 = <&i2c5_bus>;
335 status = "disabled";
336 };
337
338 i2c_6: i2c@12CC0000 {
339 compatible = "samsung,s3c2440-i2c";
340 reg = <0x12CC0000 0x100>;
341 interrupts = <0 62 0>;
342 #address-cells = <1>;
343 #size-cells = <0>;
344 clocks = <&clock CLK_I2C6>;
345 clock-names = "i2c";
346 pinctrl-names = "default";
347 pinctrl-0 = <&i2c6_bus>;
348 status = "disabled";
349 };
350
351 i2c_7: i2c@12CD0000 {
352 compatible = "samsung,s3c2440-i2c";
353 reg = <0x12CD0000 0x100>;
354 interrupts = <0 63 0>;
355 #address-cells = <1>;
356 #size-cells = <0>;
357 clocks = <&clock CLK_I2C7>;
358 clock-names = "i2c";
359 pinctrl-names = "default";
360 pinctrl-0 = <&i2c7_bus>;
361 status = "disabled";
362 };
363
364 i2c_8: i2c@12CE0000 {
365 compatible = "samsung,s3c2440-hdmiphy-i2c";
366 reg = <0x12CE0000 0x1000>;
367 interrupts = <0 64 0>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370 clocks = <&clock CLK_I2C_HDMI>;
371 clock-names = "i2c";
372 status = "disabled";
373 };
374
375 i2c_9: i2c@121D0000 {
376 compatible = "samsung,exynos5-sata-phy-i2c";
377 reg = <0x121D0000 0x100>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 clocks = <&clock CLK_SATA_PHYI2C>;
381 clock-names = "i2c";
382 status = "disabled";
383 };
384
385 spi_0: spi@12d20000 {
386 compatible = "samsung,exynos4210-spi";
387 status = "disabled";
388 reg = <0x12d20000 0x100>;
389 interrupts = <0 66 0>;
390 dmas = <&pdma0 5
391 &pdma0 4>;
392 dma-names = "tx", "rx";
393 #address-cells = <1>;
394 #size-cells = <0>;
395 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
396 clock-names = "spi", "spi_busclk0";
397 pinctrl-names = "default";
398 pinctrl-0 = <&spi0_bus>;
399 };
400
401 spi_1: spi@12d30000 {
402 compatible = "samsung,exynos4210-spi";
403 status = "disabled";
404 reg = <0x12d30000 0x100>;
405 interrupts = <0 67 0>;
406 dmas = <&pdma1 5
407 &pdma1 4>;
408 dma-names = "tx", "rx";
409 #address-cells = <1>;
410 #size-cells = <0>;
411 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
412 clock-names = "spi", "spi_busclk0";
413 pinctrl-names = "default";
414 pinctrl-0 = <&spi1_bus>;
415 };
416
417 spi_2: spi@12d40000 {
418 compatible = "samsung,exynos4210-spi";
419 status = "disabled";
420 reg = <0x12d40000 0x100>;
421 interrupts = <0 68 0>;
422 dmas = <&pdma0 7
423 &pdma0 6>;
424 dma-names = "tx", "rx";
425 #address-cells = <1>;
426 #size-cells = <0>;
427 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
428 clock-names = "spi", "spi_busclk0";
429 pinctrl-names = "default";
430 pinctrl-0 = <&spi2_bus>;
431 };
432
433 mmc_0: mmc@12200000 {
434 compatible = "samsung,exynos5250-dw-mshc";
435 interrupts = <0 75 0>;
436 #address-cells = <1>;
437 #size-cells = <0>;
438 reg = <0x12200000 0x1000>;
439 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
440 clock-names = "biu", "ciu";
441 fifo-depth = <0x80>;
442 status = "disabled";
443 };
444
445 mmc_1: mmc@12210000 {
446 compatible = "samsung,exynos5250-dw-mshc";
447 interrupts = <0 76 0>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450 reg = <0x12210000 0x1000>;
451 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
452 clock-names = "biu", "ciu";
453 fifo-depth = <0x80>;
454 status = "disabled";
455 };
456
457 mmc_2: mmc@12220000 {
458 compatible = "samsung,exynos5250-dw-mshc";
459 interrupts = <0 77 0>;
460 #address-cells = <1>;
461 #size-cells = <0>;
462 reg = <0x12220000 0x1000>;
463 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
464 clock-names = "biu", "ciu";
465 fifo-depth = <0x80>;
466 status = "disabled";
467 };
468
469 mmc_3: mmc@12230000 {
470 compatible = "samsung,exynos5250-dw-mshc";
471 reg = <0x12230000 0x1000>;
472 interrupts = <0 78 0>;
473 #address-cells = <1>;
474 #size-cells = <0>;
475 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
476 clock-names = "biu", "ciu";
477 fifo-depth = <0x80>;
478 status = "disabled";
479 };
480
481 i2s0: i2s@03830000 {
482 compatible = "samsung,s5pv210-i2s";
483 status = "disabled";
484 reg = <0x03830000 0x100>;
485 dmas = <&pdma0 10
486 &pdma0 9
487 &pdma0 8>;
488 dma-names = "tx", "rx", "tx-sec";
489 clocks = <&clock_audss EXYNOS_I2S_BUS>,
490 <&clock_audss EXYNOS_I2S_BUS>,
491 <&clock_audss EXYNOS_SCLK_I2S>;
492 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
493 samsung,idma-addr = <0x03000000>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2s0_bus>;
496 };
497
498 i2s1: i2s@12D60000 {
499 compatible = "samsung,s3c6410-i2s";
500 status = "disabled";
501 reg = <0x12D60000 0x100>;
502 dmas = <&pdma1 12
503 &pdma1 11>;
504 dma-names = "tx", "rx";
505 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
506 clock-names = "iis", "i2s_opclk0";
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2s1_bus>;
509 };
510
511 i2s2: i2s@12D70000 {
512 compatible = "samsung,s3c6410-i2s";
513 status = "disabled";
514 reg = <0x12D70000 0x100>;
515 dmas = <&pdma0 12
516 &pdma0 11>;
517 dma-names = "tx", "rx";
518 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
519 clock-names = "iis", "i2s_opclk0";
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2s2_bus>;
522 };
523
524 usb@12000000 {
525 compatible = "samsung,exynos5250-dwusb3";
526 clocks = <&clock CLK_USB3>;
527 clock-names = "usbdrd30";
528 #address-cells = <1>;
529 #size-cells = <1>;
530 ranges;
531
532 dwc3 {
533 compatible = "synopsys,dwc3";
534 reg = <0x12000000 0x10000>;
535 interrupts = <0 72 0>;
536 usb-phy = <&usb2_phy &usb3_phy>;
537 };
538 };
539
540 usb3_phy: usbphy@12100000 {
541 compatible = "samsung,exynos5250-usb3phy";
542 reg = <0x12100000 0x100>;
543 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>;
544 clock-names = "ext_xtal", "usbdrd30";
545 #address-cells = <1>;
546 #size-cells = <1>;
547 ranges;
548
549 usbphy-sys {
550 reg = <0x10040704 0x8>;
551 };
552 };
553
554 usb@12110000 {
555 compatible = "samsung,exynos4210-ehci";
556 reg = <0x12110000 0x100>;
557 interrupts = <0 71 0>;
558
559 clocks = <&clock CLK_USB2>;
560 clock-names = "usbhost";
561 };
562
563 usb@12120000 {
564 compatible = "samsung,exynos4210-ohci";
565 reg = <0x12120000 0x100>;
566 interrupts = <0 71 0>;
567
568 clocks = <&clock CLK_USB2>;
569 clock-names = "usbhost";
570 };
571
572 usb2_phy: usbphy@12130000 {
573 compatible = "samsung,exynos5250-usb2phy";
574 reg = <0x12130000 0x100>;
575 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>;
576 clock-names = "ext_xtal", "usbhost";
577 #address-cells = <1>;
578 #size-cells = <1>;
579 ranges;
580
581 usbphy-sys {
582 reg = <0x10040704 0x8>,
583 <0x10050230 0x4>;
584 };
585 };
586
587 pwm: pwm@12dd0000 {
588 compatible = "samsung,exynos4210-pwm";
589 reg = <0x12dd0000 0x100>;
590 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
591 #pwm-cells = <3>;
592 clocks = <&clock CLK_PWM>;
593 clock-names = "timers";
594 };
595
596 amba {
597 #address-cells = <1>;
598 #size-cells = <1>;
599 compatible = "arm,amba-bus";
600 interrupt-parent = <&gic>;
601 ranges;
602
603 pdma0: pdma@121A0000 {
604 compatible = "arm,pl330", "arm,primecell";
605 reg = <0x121A0000 0x1000>;
606 interrupts = <0 34 0>;
607 clocks = <&clock CLK_PDMA0>;
608 clock-names = "apb_pclk";
609 #dma-cells = <1>;
610 #dma-channels = <8>;
611 #dma-requests = <32>;
612 };
613
614 pdma1: pdma@121B0000 {
615 compatible = "arm,pl330", "arm,primecell";
616 reg = <0x121B0000 0x1000>;
617 interrupts = <0 35 0>;
618 clocks = <&clock CLK_PDMA1>;
619 clock-names = "apb_pclk";
620 #dma-cells = <1>;
621 #dma-channels = <8>;
622 #dma-requests = <32>;
623 };
624
625 mdma0: mdma@10800000 {
626 compatible = "arm,pl330", "arm,primecell";
627 reg = <0x10800000 0x1000>;
628 interrupts = <0 33 0>;
629 clocks = <&clock CLK_MDMA0>;
630 clock-names = "apb_pclk";
631 #dma-cells = <1>;
632 #dma-channels = <8>;
633 #dma-requests = <1>;
634 };
635
636 mdma1: mdma@11C10000 {
637 compatible = "arm,pl330", "arm,primecell";
638 reg = <0x11C10000 0x1000>;
639 interrupts = <0 124 0>;
640 clocks = <&clock CLK_MDMA1>;
641 clock-names = "apb_pclk";
642 #dma-cells = <1>;
643 #dma-channels = <8>;
644 #dma-requests = <1>;
645 };
646 };
647
648 gsc_0: gsc@13e00000 {
649 compatible = "samsung,exynos5-gsc";
650 reg = <0x13e00000 0x1000>;
651 interrupts = <0 85 0>;
652 samsung,power-domain = <&pd_gsc>;
653 clocks = <&clock CLK_GSCL0>;
654 clock-names = "gscl";
655 };
656
657 gsc_1: gsc@13e10000 {
658 compatible = "samsung,exynos5-gsc";
659 reg = <0x13e10000 0x1000>;
660 interrupts = <0 86 0>;
661 samsung,power-domain = <&pd_gsc>;
662 clocks = <&clock CLK_GSCL1>;
663 clock-names = "gscl";
664 };
665
666 gsc_2: gsc@13e20000 {
667 compatible = "samsung,exynos5-gsc";
668 reg = <0x13e20000 0x1000>;
669 interrupts = <0 87 0>;
670 samsung,power-domain = <&pd_gsc>;
671 clocks = <&clock CLK_GSCL2>;
672 clock-names = "gscl";
673 };
674
675 gsc_3: gsc@13e30000 {
676 compatible = "samsung,exynos5-gsc";
677 reg = <0x13e30000 0x1000>;
678 interrupts = <0 88 0>;
679 samsung,power-domain = <&pd_gsc>;
680 clocks = <&clock CLK_GSCL3>;
681 clock-names = "gscl";
682 };
683
684 hdmi {
685 compatible = "samsung,exynos4212-hdmi";
686 reg = <0x14530000 0x70000>;
687 interrupts = <0 95 0>;
688 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
689 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
690 <&clock CLK_MOUT_HDMI>;
691 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
692 "sclk_hdmiphy", "mout_hdmi";
693 };
694
695 mixer {
696 compatible = "samsung,exynos5250-mixer";
697 reg = <0x14450000 0x10000>;
698 interrupts = <0 94 0>;
699 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
700 clock-names = "mixer", "sclk_hdmi";
701 };
702
703 dp_phy: video-phy@10040720 {
704 compatible = "samsung,exynos5250-dp-video-phy";
705 reg = <0x10040720 4>;
706 #phy-cells = <0>;
707 };
708
709 dp-controller@145B0000 {
710 clocks = <&clock CLK_DP>;
711 clock-names = "dp";
712 phys = <&dp_phy>;
713 phy-names = "dp";
714 };
715
716 fimd@14400000 {
717 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
718 clock-names = "sclk_fimd", "fimd";
719 };
720
721 adc: adc@12D10000 {
722 compatible = "samsung,exynos-adc-v1";
723 reg = <0x12D10000 0x100>, <0x10040718 0x4>;
724 interrupts = <0 106 0>;
725 clocks = <&clock CLK_ADC>;
726 clock-names = "adc";
727 #io-channel-cells = <1>;
728 io-channel-ranges;
729 status = "disabled";
730 };
731
732 sss@10830000 {
733 compatible = "samsung,exynos4210-secss";
734 reg = <0x10830000 0x10000>;
735 interrupts = <0 112 0>;
736 clocks = <&clock 348>;
737 clock-names = "secss";
738 };
739};