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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SAMSUNG EXYNOS5250 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
9 * EXYNOS5250 based board files can include this file and provide
10 * values for board specfic bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
14 * additional nodes can be added to this file.
15 */
16
17#include <dt-bindings/clock/exynos5250.h>
18#include "exynos5.dtsi"
19#include "exynos4-cpu-thermal.dtsi"
20#include <dt-bindings/clock/exynos-audss-clk.h>
21
22/ {
23 compatible = "samsung,exynos5250", "samsung,exynos5";
24
25 aliases {
26 spi0 = &spi_0;
27 spi1 = &spi_1;
28 spi2 = &spi_2;
29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3;
33 mshc0 = &mmc_0;
34 mshc1 = &mmc_1;
35 mshc2 = &mmc_2;
36 mshc3 = &mmc_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
42 i2c9 = &i2c_9;
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a15";
56 reg = <0>;
57 clock-frequency = <1700000000>;
58 clocks = <&clock CLK_ARM_CLK>;
59 clock-names = "cpu";
60 clock-latency = <140000>;
61
62 operating-points = <
63 1700000 1300000
64 1600000 1250000
65 1500000 1225000
66 1400000 1200000
67 1300000 1150000
68 1200000 1125000
69 1100000 1100000
70 1000000 1075000
71 900000 1050000
72 800000 1025000
73 700000 1012500
74 600000 1000000
75 500000 975000
76 400000 950000
77 300000 937500
78 200000 925000
79 >;
80 #cooling-cells = <2>; /* min followed by max */
81 };
82 cpu@1 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <1>;
86 clock-frequency = <1700000000>;
87 };
88 };
89
90 soc: soc {
91 sysram@2020000 {
92 compatible = "mmio-sram";
93 reg = <0x02020000 0x30000>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges = <0 0x02020000 0x30000>;
97
98 smp-sysram@0 {
99 compatible = "samsung,exynos4210-sysram";
100 reg = <0x0 0x1000>;
101 };
102
103 smp-sysram@2f000 {
104 compatible = "samsung,exynos4210-sysram-ns";
105 reg = <0x2f000 0x1000>;
106 };
107 };
108
109 pd_gsc: power-domain@10044000 {
110 compatible = "samsung,exynos4210-pd";
111 reg = <0x10044000 0x20>;
112 #power-domain-cells = <0>;
113 label = "GSC";
114 };
115
116 pd_mfc: power-domain@10044040 {
117 compatible = "samsung,exynos4210-pd";
118 reg = <0x10044040 0x20>;
119 #power-domain-cells = <0>;
120 label = "MFC";
121 };
122
123 pd_g3d: power-domain@10044060 {
124 compatible = "samsung,exynos4210-pd";
125 reg = <0x10044060 0x20>;
126 #power-domain-cells = <0>;
127 label = "G3D";
128 };
129
130 pd_disp1: power-domain@100440a0 {
131 compatible = "samsung,exynos4210-pd";
132 reg = <0x100440A0 0x20>;
133 #power-domain-cells = <0>;
134 label = "DISP1";
135 clocks = <&clock CLK_FIN_PLL>,
136 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
137 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
138 clock-names = "oscclk", "clk0", "clk1";
139 };
140
141 pd_mau: power-domain@100440c0 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x100440C0 0x20>;
144 #power-domain-cells = <0>;
145 label = "MAU";
146 };
147
148 clock: clock-controller@10010000 {
149 compatible = "samsung,exynos5250-clock";
150 reg = <0x10010000 0x30000>;
151 #clock-cells = <1>;
152 };
153
154 clock_audss: audss-clock-controller@3810000 {
155 compatible = "samsung,exynos5250-audss-clock";
156 reg = <0x03810000 0x0C>;
157 #clock-cells = <1>;
158 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
159 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
160 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
161 power-domains = <&pd_mau>;
162 };
163
164 timer {
165 compatible = "arm,armv7-timer";
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
170 /*
171 * Unfortunately we need this since some versions
172 * of U-Boot on Exynos don't set the CNTFRQ register,
173 * so we need the value from DT.
174 */
175 clock-frequency = <24000000>;
176 };
177
178 mct@101c0000 {
179 compatible = "samsung,exynos4210-mct";
180 reg = <0x101C0000 0x800>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
183 interrupt-parent = <&mct_map>;
184 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
185 <4 0>, <5 0>;
186 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
187 clock-names = "fin_pll", "mct";
188
189 mct_map: mct-map {
190 #interrupt-cells = <2>;
191 #address-cells = <0>;
192 #size-cells = <0>;
193 interrupt-map = <0x0 0 &combiner 23 3>,
194 <0x1 0 &combiner 23 4>,
195 <0x2 0 &combiner 25 2>,
196 <0x3 0 &combiner 25 3>,
197 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
198 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
199 };
200 };
201
202 pmu {
203 compatible = "arm,cortex-a15-pmu";
204 interrupt-parent = <&combiner>;
205 interrupts = <1 2>, <22 4>;
206 };
207
208 pinctrl_0: pinctrl@11400000 {
209 compatible = "samsung,exynos5250-pinctrl";
210 reg = <0x11400000 0x1000>;
211 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
212
213 wakup_eint: wakeup-interrupt-controller {
214 compatible = "samsung,exynos4210-wakeup-eint";
215 interrupt-parent = <&gic>;
216 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
217 };
218 };
219
220 pinctrl_1: pinctrl@13400000 {
221 compatible = "samsung,exynos5250-pinctrl";
222 reg = <0x13400000 0x1000>;
223 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
224 };
225
226 pinctrl_2: pinctrl@10d10000 {
227 compatible = "samsung,exynos5250-pinctrl";
228 reg = <0x10d10000 0x1000>;
229 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
230 };
231
232 pinctrl_3: pinctrl@3860000 {
233 compatible = "samsung,exynos5250-pinctrl";
234 reg = <0x03860000 0x1000>;
235 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
236 power-domains = <&pd_mau>;
237 };
238
239 pmu_system_controller: system-controller@10040000 {
240 compatible = "samsung,exynos5250-pmu", "syscon";
241 reg = <0x10040000 0x5000>;
242 clock-names = "clkout16";
243 clocks = <&clock CLK_FIN_PLL>;
244 #clock-cells = <1>;
245 interrupt-controller;
246 #interrupt-cells = <3>;
247 interrupt-parent = <&gic>;
248 };
249
250 watchdog@101d0000 {
251 compatible = "samsung,exynos5250-wdt";
252 reg = <0x101D0000 0x100>;
253 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clock CLK_WDT>;
255 clock-names = "watchdog";
256 samsung,syscon-phandle = <&pmu_system_controller>;
257 };
258
259 mfc: codec@11000000 {
260 compatible = "samsung,mfc-v6";
261 reg = <0x11000000 0x10000>;
262 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
263 power-domains = <&pd_mfc>;
264 clocks = <&clock CLK_MFC>;
265 clock-names = "mfc";
266 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
267 iommu-names = "left", "right";
268 };
269
270 rotator: rotator@11c00000 {
271 compatible = "samsung,exynos5250-rotator";
272 reg = <0x11C00000 0x64>;
273 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&clock CLK_ROTATOR>;
275 clock-names = "rotator";
276 iommus = <&sysmmu_rotator>;
277 };
278
279 tmu: tmu@10060000 {
280 compatible = "samsung,exynos5250-tmu";
281 reg = <0x10060000 0x100>;
282 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clock CLK_TMU>;
284 clock-names = "tmu_apbif";
285 #include "exynos4412-tmu-sensor-conf.dtsi"
286 };
287
288 sata: sata@122f0000 {
289 compatible = "snps,dwc-ahci";
290 samsung,sata-freq = <66>;
291 reg = <0x122F0000 0x1ff>;
292 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
294 clock-names = "sata", "sclk_sata";
295 phys = <&sata_phy>;
296 phy-names = "sata-phy";
297 status = "disabled";
298 };
299
300 sata_phy: sata-phy@12170000 {
301 compatible = "samsung,exynos5250-sata-phy";
302 reg = <0x12170000 0x1ff>;
303 clocks = <&clock CLK_SATA_PHYCTRL>;
304 clock-names = "sata_phyctrl";
305 #phy-cells = <0>;
306 samsung,syscon-phandle = <&pmu_system_controller>;
307 status = "disabled";
308 };
309
310 /* i2c_0-3 are defined in exynos5.dtsi */
311 i2c_4: i2c@12ca0000 {
312 compatible = "samsung,s3c2440-i2c";
313 reg = <0x12CA0000 0x100>;
314 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 clocks = <&clock CLK_I2C4>;
318 clock-names = "i2c";
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c4_bus>;
321 status = "disabled";
322 };
323
324 i2c_5: i2c@12cb0000 {
325 compatible = "samsung,s3c2440-i2c";
326 reg = <0x12CB0000 0x100>;
327 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
328 #address-cells = <1>;
329 #size-cells = <0>;
330 clocks = <&clock CLK_I2C5>;
331 clock-names = "i2c";
332 pinctrl-names = "default";
333 pinctrl-0 = <&i2c5_bus>;
334 status = "disabled";
335 };
336
337 i2c_6: i2c@12cc0000 {
338 compatible = "samsung,s3c2440-i2c";
339 reg = <0x12CC0000 0x100>;
340 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 clocks = <&clock CLK_I2C6>;
344 clock-names = "i2c";
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c6_bus>;
347 status = "disabled";
348 };
349
350 i2c_7: i2c@12cd0000 {
351 compatible = "samsung,s3c2440-i2c";
352 reg = <0x12CD0000 0x100>;
353 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 clocks = <&clock CLK_I2C7>;
357 clock-names = "i2c";
358 pinctrl-names = "default";
359 pinctrl-0 = <&i2c7_bus>;
360 status = "disabled";
361 };
362
363 i2c_8: i2c@12ce0000 {
364 compatible = "samsung,s3c2440-hdmiphy-i2c";
365 reg = <0x12CE0000 0x1000>;
366 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 clocks = <&clock CLK_I2C_HDMI>;
370 clock-names = "i2c";
371 status = "disabled";
372
373 hdmiphy: hdmiphy@38 {
374 compatible = "samsung,exynos4212-hdmiphy";
375 reg = <0x38>;
376 };
377 };
378
379 i2c_9: i2c@121d0000 {
380 compatible = "samsung,exynos5-sata-phy-i2c";
381 reg = <0x121D0000 0x100>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 clocks = <&clock CLK_SATA_PHYI2C>;
385 clock-names = "i2c";
386 status = "disabled";
387 };
388
389 spi_0: spi@12d20000 {
390 compatible = "samsung,exynos4210-spi";
391 status = "disabled";
392 reg = <0x12d20000 0x100>;
393 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
394 dmas = <&pdma0 5
395 &pdma0 4>;
396 dma-names = "tx", "rx";
397 #address-cells = <1>;
398 #size-cells = <0>;
399 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
400 clock-names = "spi", "spi_busclk0";
401 pinctrl-names = "default";
402 pinctrl-0 = <&spi0_bus>;
403 };
404
405 spi_1: spi@12d30000 {
406 compatible = "samsung,exynos4210-spi";
407 status = "disabled";
408 reg = <0x12d30000 0x100>;
409 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
410 dmas = <&pdma1 5
411 &pdma1 4>;
412 dma-names = "tx", "rx";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
416 clock-names = "spi", "spi_busclk0";
417 pinctrl-names = "default";
418 pinctrl-0 = <&spi1_bus>;
419 };
420
421 spi_2: spi@12d40000 {
422 compatible = "samsung,exynos4210-spi";
423 status = "disabled";
424 reg = <0x12d40000 0x100>;
425 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
426 dmas = <&pdma0 7
427 &pdma0 6>;
428 dma-names = "tx", "rx";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
432 clock-names = "spi", "spi_busclk0";
433 pinctrl-names = "default";
434 pinctrl-0 = <&spi2_bus>;
435 };
436
437 mmc_0: mmc@12200000 {
438 compatible = "samsung,exynos5250-dw-mshc";
439 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>;
441 #size-cells = <0>;
442 reg = <0x12200000 0x1000>;
443 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
444 clock-names = "biu", "ciu";
445 fifo-depth = <0x80>;
446 status = "disabled";
447 };
448
449 mmc_1: mmc@12210000 {
450 compatible = "samsung,exynos5250-dw-mshc";
451 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 reg = <0x12210000 0x1000>;
455 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
456 clock-names = "biu", "ciu";
457 fifo-depth = <0x80>;
458 status = "disabled";
459 };
460
461 mmc_2: mmc@12220000 {
462 compatible = "samsung,exynos5250-dw-mshc";
463 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 reg = <0x12220000 0x1000>;
467 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
468 clock-names = "biu", "ciu";
469 fifo-depth = <0x80>;
470 status = "disabled";
471 };
472
473 mmc_3: mmc@12230000 {
474 compatible = "samsung,exynos5250-dw-mshc";
475 reg = <0x12230000 0x1000>;
476 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
480 clock-names = "biu", "ciu";
481 fifo-depth = <0x80>;
482 status = "disabled";
483 };
484
485 i2s0: i2s@3830000 {
486 compatible = "samsung,s5pv210-i2s";
487 status = "disabled";
488 reg = <0x03830000 0x100>;
489 dmas = <&pdma0 10
490 &pdma0 9
491 &pdma0 8>;
492 dma-names = "tx", "rx", "tx-sec";
493 clocks = <&clock_audss EXYNOS_I2S_BUS>,
494 <&clock_audss EXYNOS_I2S_BUS>,
495 <&clock_audss EXYNOS_SCLK_I2S>;
496 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
497 samsung,idma-addr = <0x03000000>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&i2s0_bus>;
500 power-domains = <&pd_mau>;
501 #clock-cells = <1>;
502 #sound-dai-cells = <1>;
503 };
504
505 i2s1: i2s@12d60000 {
506 compatible = "samsung,s3c6410-i2s";
507 status = "disabled";
508 reg = <0x12D60000 0x100>;
509 dmas = <&pdma1 12
510 &pdma1 11>;
511 dma-names = "tx", "rx";
512 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
513 clock-names = "iis", "i2s_opclk0";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2s1_bus>;
516 power-domains = <&pd_mau>;
517 #sound-dai-cells = <1>;
518 };
519
520 i2s2: i2s@12d70000 {
521 compatible = "samsung,s3c6410-i2s";
522 status = "disabled";
523 reg = <0x12D70000 0x100>;
524 dmas = <&pdma0 12
525 &pdma0 11>;
526 dma-names = "tx", "rx";
527 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
528 clock-names = "iis", "i2s_opclk0";
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2s2_bus>;
531 power-domains = <&pd_mau>;
532 #sound-dai-cells = <1>;
533 };
534
535 usb_dwc3 {
536 compatible = "samsung,exynos5250-dwusb3";
537 clocks = <&clock CLK_USB3>;
538 clock-names = "usbdrd30";
539 #address-cells = <1>;
540 #size-cells = <1>;
541 ranges;
542
543 usbdrd_dwc3: dwc3@12000000 {
544 compatible = "synopsys,dwc3";
545 reg = <0x12000000 0x10000>;
546 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
547 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
548 phy-names = "usb2-phy", "usb3-phy";
549 };
550 };
551
552 usbdrd_phy: phy@12100000 {
553 compatible = "samsung,exynos5250-usbdrd-phy";
554 reg = <0x12100000 0x100>;
555 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
556 clock-names = "phy", "ref";
557 samsung,pmu-syscon = <&pmu_system_controller>;
558 #phy-cells = <1>;
559 };
560
561 ehci: usb@12110000 {
562 compatible = "samsung,exynos4210-ehci";
563 reg = <0x12110000 0x100>;
564 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
565
566 clocks = <&clock CLK_USB2>;
567 clock-names = "usbhost";
568 #address-cells = <1>;
569 #size-cells = <0>;
570 port@0 {
571 reg = <0>;
572 phys = <&usb2_phy_gen 1>;
573 };
574 };
575
576 ohci: usb@12120000 {
577 compatible = "samsung,exynos4210-ohci";
578 reg = <0x12120000 0x100>;
579 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
580
581 clocks = <&clock CLK_USB2>;
582 clock-names = "usbhost";
583 #address-cells = <1>;
584 #size-cells = <0>;
585 port@0 {
586 reg = <0>;
587 phys = <&usb2_phy_gen 1>;
588 };
589 };
590
591 usb2_phy_gen: phy@12130000 {
592 compatible = "samsung,exynos5250-usb2-phy";
593 reg = <0x12130000 0x100>;
594 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
595 clock-names = "phy", "ref";
596 #phy-cells = <1>;
597 samsung,sysreg-phandle = <&sysreg_system_controller>;
598 samsung,pmureg-phandle = <&pmu_system_controller>;
599 };
600
601 amba {
602 #address-cells = <1>;
603 #size-cells = <1>;
604 compatible = "simple-bus";
605 interrupt-parent = <&gic>;
606 ranges;
607
608 pdma0: pdma@121a0000 {
609 compatible = "arm,pl330", "arm,primecell";
610 reg = <0x121A0000 0x1000>;
611 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clock CLK_PDMA0>;
613 clock-names = "apb_pclk";
614 #dma-cells = <1>;
615 #dma-channels = <8>;
616 #dma-requests = <32>;
617 };
618
619 pdma1: pdma@121b0000 {
620 compatible = "arm,pl330", "arm,primecell";
621 reg = <0x121B0000 0x1000>;
622 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clock CLK_PDMA1>;
624 clock-names = "apb_pclk";
625 #dma-cells = <1>;
626 #dma-channels = <8>;
627 #dma-requests = <32>;
628 };
629
630 mdma0: mdma@10800000 {
631 compatible = "arm,pl330", "arm,primecell";
632 reg = <0x10800000 0x1000>;
633 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&clock CLK_MDMA0>;
635 clock-names = "apb_pclk";
636 #dma-cells = <1>;
637 #dma-channels = <8>;
638 #dma-requests = <1>;
639 };
640
641 mdma1: mdma@11c10000 {
642 compatible = "arm,pl330", "arm,primecell";
643 reg = <0x11C10000 0x1000>;
644 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clock CLK_MDMA1>;
646 clock-names = "apb_pclk";
647 #dma-cells = <1>;
648 #dma-channels = <8>;
649 #dma-requests = <1>;
650 };
651 };
652
653 gsc_0: gsc@13e00000 {
654 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
655 reg = <0x13e00000 0x1000>;
656 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
657 power-domains = <&pd_gsc>;
658 clocks = <&clock CLK_GSCL0>;
659 clock-names = "gscl";
660 iommus = <&sysmmu_gsc0>;
661 };
662
663 gsc_1: gsc@13e10000 {
664 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
665 reg = <0x13e10000 0x1000>;
666 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
667 power-domains = <&pd_gsc>;
668 clocks = <&clock CLK_GSCL1>;
669 clock-names = "gscl";
670 iommus = <&sysmmu_gsc1>;
671 };
672
673 gsc_2: gsc@13e20000 {
674 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
675 reg = <0x13e20000 0x1000>;
676 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
677 power-domains = <&pd_gsc>;
678 clocks = <&clock CLK_GSCL2>;
679 clock-names = "gscl";
680 iommus = <&sysmmu_gsc2>;
681 };
682
683 gsc_3: gsc@13e30000 {
684 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
685 reg = <0x13e30000 0x1000>;
686 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
687 power-domains = <&pd_gsc>;
688 clocks = <&clock CLK_GSCL3>;
689 clock-names = "gscl";
690 iommus = <&sysmmu_gsc3>;
691 };
692
693 hdmi: hdmi@14530000 {
694 compatible = "samsung,exynos4212-hdmi";
695 reg = <0x14530000 0x70000>;
696 power-domains = <&pd_disp1>;
697 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
699 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
700 <&clock CLK_MOUT_HDMI>;
701 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
702 "sclk_hdmiphy", "mout_hdmi";
703 samsung,syscon-phandle = <&pmu_system_controller>;
704 phy = <&hdmiphy>;
705 #sound-dai-cells = <0>;
706 status = "disabled";
707 };
708
709 hdmicec: cec@101b0000 {
710 compatible = "samsung,s5p-cec";
711 reg = <0x101B0000 0x200>;
712 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clock CLK_HDMI_CEC>;
714 clock-names = "hdmicec";
715 samsung,syscon-phandle = <&pmu_system_controller>;
716 hdmi-phandle = <&hdmi>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&hdmi_cec>;
719 status = "disabled";
720 };
721
722 mixer: mixer@14450000 {
723 compatible = "samsung,exynos5250-mixer";
724 reg = <0x14450000 0x10000>;
725 power-domains = <&pd_disp1>;
726 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
728 <&clock CLK_SCLK_HDMI>;
729 clock-names = "mixer", "hdmi", "sclk_hdmi";
730 iommus = <&sysmmu_tv>;
731 status = "disabled";
732 };
733
734 dp_phy: video-phy {
735 compatible = "samsung,exynos5250-dp-video-phy";
736 samsung,pmu-syscon = <&pmu_system_controller>;
737 #phy-cells = <0>;
738 };
739
740 adc: adc@12d10000 {
741 compatible = "samsung,exynos-adc-v1";
742 reg = <0x12D10000 0x100>;
743 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clock CLK_ADC>;
745 clock-names = "adc";
746 #io-channel-cells = <1>;
747 io-channel-ranges;
748 samsung,syscon-phandle = <&pmu_system_controller>;
749 status = "disabled";
750 };
751
752 sysmmu_g2d: sysmmu@10a60000 {
753 compatible = "samsung,exynos-sysmmu";
754 reg = <0x10A60000 0x1000>;
755 interrupt-parent = <&combiner>;
756 interrupts = <24 5>;
757 clock-names = "sysmmu", "master";
758 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
759 #iommu-cells = <0>;
760 };
761
762 sysmmu_mfc_r: sysmmu@11200000 {
763 compatible = "samsung,exynos-sysmmu";
764 reg = <0x11200000 0x1000>;
765 interrupt-parent = <&combiner>;
766 interrupts = <6 2>;
767 power-domains = <&pd_mfc>;
768 clock-names = "sysmmu", "master";
769 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
770 #iommu-cells = <0>;
771 };
772
773 sysmmu_mfc_l: sysmmu@11210000 {
774 compatible = "samsung,exynos-sysmmu";
775 reg = <0x11210000 0x1000>;
776 interrupt-parent = <&combiner>;
777 interrupts = <8 5>;
778 power-domains = <&pd_mfc>;
779 clock-names = "sysmmu", "master";
780 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
781 #iommu-cells = <0>;
782 };
783
784 sysmmu_rotator: sysmmu@11d40000 {
785 compatible = "samsung,exynos-sysmmu";
786 reg = <0x11D40000 0x1000>;
787 interrupt-parent = <&combiner>;
788 interrupts = <4 0>;
789 clock-names = "sysmmu", "master";
790 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
791 #iommu-cells = <0>;
792 };
793
794 sysmmu_jpeg: sysmmu@11f20000 {
795 compatible = "samsung,exynos-sysmmu";
796 reg = <0x11F20000 0x1000>;
797 interrupt-parent = <&combiner>;
798 interrupts = <4 2>;
799 power-domains = <&pd_gsc>;
800 clock-names = "sysmmu", "master";
801 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
802 #iommu-cells = <0>;
803 };
804
805 sysmmu_fimc_isp: sysmmu@13260000 {
806 compatible = "samsung,exynos-sysmmu";
807 reg = <0x13260000 0x1000>;
808 interrupt-parent = <&combiner>;
809 interrupts = <10 6>;
810 clock-names = "sysmmu";
811 clocks = <&clock CLK_SMMU_FIMC_ISP>;
812 #iommu-cells = <0>;
813 };
814
815 sysmmu_fimc_drc: sysmmu@13270000 {
816 compatible = "samsung,exynos-sysmmu";
817 reg = <0x13270000 0x1000>;
818 interrupt-parent = <&combiner>;
819 interrupts = <11 6>;
820 clock-names = "sysmmu";
821 clocks = <&clock CLK_SMMU_FIMC_DRC>;
822 #iommu-cells = <0>;
823 };
824
825 sysmmu_fimc_fd: sysmmu@132a0000 {
826 compatible = "samsung,exynos-sysmmu";
827 reg = <0x132A0000 0x1000>;
828 interrupt-parent = <&combiner>;
829 interrupts = <5 0>;
830 clock-names = "sysmmu";
831 clocks = <&clock CLK_SMMU_FIMC_FD>;
832 #iommu-cells = <0>;
833 };
834
835 sysmmu_fimc_scc: sysmmu@13280000 {
836 compatible = "samsung,exynos-sysmmu";
837 reg = <0x13280000 0x1000>;
838 interrupt-parent = <&combiner>;
839 interrupts = <5 2>;
840 clock-names = "sysmmu";
841 clocks = <&clock CLK_SMMU_FIMC_SCC>;
842 #iommu-cells = <0>;
843 };
844
845 sysmmu_fimc_scp: sysmmu@13290000 {
846 compatible = "samsung,exynos-sysmmu";
847 reg = <0x13290000 0x1000>;
848 interrupt-parent = <&combiner>;
849 interrupts = <3 6>;
850 clock-names = "sysmmu";
851 clocks = <&clock CLK_SMMU_FIMC_SCP>;
852 #iommu-cells = <0>;
853 };
854
855 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
856 compatible = "samsung,exynos-sysmmu";
857 reg = <0x132B0000 0x1000>;
858 interrupt-parent = <&combiner>;
859 interrupts = <5 4>;
860 clock-names = "sysmmu";
861 clocks = <&clock CLK_SMMU_FIMC_MCU>;
862 #iommu-cells = <0>;
863 };
864
865 sysmmu_fimc_odc: sysmmu@132c0000 {
866 compatible = "samsung,exynos-sysmmu";
867 reg = <0x132C0000 0x1000>;
868 interrupt-parent = <&combiner>;
869 interrupts = <11 0>;
870 clock-names = "sysmmu";
871 clocks = <&clock CLK_SMMU_FIMC_ODC>;
872 #iommu-cells = <0>;
873 };
874
875 sysmmu_fimc_dis0: sysmmu@132d0000 {
876 compatible = "samsung,exynos-sysmmu";
877 reg = <0x132D0000 0x1000>;
878 interrupt-parent = <&combiner>;
879 interrupts = <10 4>;
880 clock-names = "sysmmu";
881 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
882 #iommu-cells = <0>;
883 };
884
885 sysmmu_fimc_dis1: sysmmu@132E0000{
886 compatible = "samsung,exynos-sysmmu";
887 reg = <0x132E0000 0x1000>;
888 interrupt-parent = <&combiner>;
889 interrupts = <9 4>;
890 clock-names = "sysmmu";
891 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
892 #iommu-cells = <0>;
893 };
894
895 sysmmu_fimc_3dnr: sysmmu@132f0000 {
896 compatible = "samsung,exynos-sysmmu";
897 reg = <0x132F0000 0x1000>;
898 interrupt-parent = <&combiner>;
899 interrupts = <5 6>;
900 clock-names = "sysmmu";
901 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
902 #iommu-cells = <0>;
903 };
904
905 sysmmu_fimc_lite0: sysmmu@13c40000 {
906 compatible = "samsung,exynos-sysmmu";
907 reg = <0x13C40000 0x1000>;
908 interrupt-parent = <&combiner>;
909 interrupts = <3 4>;
910 power-domains = <&pd_gsc>;
911 clock-names = "sysmmu", "master";
912 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
913 #iommu-cells = <0>;
914 };
915
916 sysmmu_fimc_lite1: sysmmu@13c50000 {
917 compatible = "samsung,exynos-sysmmu";
918 reg = <0x13C50000 0x1000>;
919 interrupt-parent = <&combiner>;
920 interrupts = <24 1>;
921 power-domains = <&pd_gsc>;
922 clock-names = "sysmmu", "master";
923 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
924 #iommu-cells = <0>;
925 };
926
927 sysmmu_gsc0: sysmmu@13e80000 {
928 compatible = "samsung,exynos-sysmmu";
929 reg = <0x13E80000 0x1000>;
930 interrupt-parent = <&combiner>;
931 interrupts = <2 0>;
932 power-domains = <&pd_gsc>;
933 clock-names = "sysmmu", "master";
934 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
935 #iommu-cells = <0>;
936 };
937
938 sysmmu_gsc1: sysmmu@13e90000 {
939 compatible = "samsung,exynos-sysmmu";
940 reg = <0x13E90000 0x1000>;
941 interrupt-parent = <&combiner>;
942 interrupts = <2 2>;
943 power-domains = <&pd_gsc>;
944 clock-names = "sysmmu", "master";
945 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
946 #iommu-cells = <0>;
947 };
948
949 sysmmu_gsc2: sysmmu@13ea0000 {
950 compatible = "samsung,exynos-sysmmu";
951 reg = <0x13EA0000 0x1000>;
952 interrupt-parent = <&combiner>;
953 interrupts = <2 4>;
954 power-domains = <&pd_gsc>;
955 clock-names = "sysmmu", "master";
956 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
957 #iommu-cells = <0>;
958 };
959
960 sysmmu_gsc3: sysmmu@13eb0000 {
961 compatible = "samsung,exynos-sysmmu";
962 reg = <0x13EB0000 0x1000>;
963 interrupt-parent = <&combiner>;
964 interrupts = <2 6>;
965 power-domains = <&pd_gsc>;
966 clock-names = "sysmmu", "master";
967 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
968 #iommu-cells = <0>;
969 };
970
971 sysmmu_fimd1: sysmmu@14640000 {
972 compatible = "samsung,exynos-sysmmu";
973 reg = <0x14640000 0x1000>;
974 interrupt-parent = <&combiner>;
975 interrupts = <3 2>;
976 power-domains = <&pd_disp1>;
977 clock-names = "sysmmu", "master";
978 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
979 #iommu-cells = <0>;
980 };
981
982 sysmmu_tv: sysmmu@14650000 {
983 compatible = "samsung,exynos-sysmmu";
984 reg = <0x14650000 0x1000>;
985 interrupt-parent = <&combiner>;
986 interrupts = <7 4>;
987 power-domains = <&pd_disp1>;
988 clock-names = "sysmmu", "master";
989 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
990 #iommu-cells = <0>;
991 };
992 };
993
994 thermal-zones {
995 cpu_thermal: cpu-thermal {
996 polling-delay-passive = <0>;
997 polling-delay = <0>;
998 thermal-sensors = <&tmu 0>;
999
1000 cooling-maps {
1001 map0 {
1002 /* Corresponds to 800MHz at freq_table */
1003 cooling-device = <&cpu0 9 9>;
1004 };
1005 map1 {
1006 /* Corresponds to 200MHz at freq_table */
1007 cooling-device = <&cpu0 15 15>;
1008 };
1009 };
1010 };
1011 };
1012};
1013
1014&dp {
1015 power-domains = <&pd_disp1>;
1016 clocks = <&clock CLK_DP>;
1017 clock-names = "dp";
1018 phys = <&dp_phy>;
1019 phy-names = "dp";
1020};
1021
1022&fimd {
1023 power-domains = <&pd_disp1>;
1024 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1025 clock-names = "sclk_fimd", "fimd";
1026 iommus = <&sysmmu_fimd1>;
1027};
1028
1029&g2d {
1030 iommus = <&sysmmu_g2d>;
1031 clocks = <&clock CLK_G2D>;
1032 clock-names = "fimg2d";
1033 status = "okay";
1034};
1035
1036&i2c_0 {
1037 clocks = <&clock CLK_I2C0>;
1038 clock-names = "i2c";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&i2c0_bus>;
1041};
1042
1043&i2c_1 {
1044 clocks = <&clock CLK_I2C1>;
1045 clock-names = "i2c";
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&i2c1_bus>;
1048};
1049
1050&i2c_2 {
1051 clocks = <&clock CLK_I2C2>;
1052 clock-names = "i2c";
1053 pinctrl-names = "default";
1054 pinctrl-0 = <&i2c2_bus>;
1055};
1056
1057&i2c_3 {
1058 clocks = <&clock CLK_I2C3>;
1059 clock-names = "i2c";
1060 pinctrl-names = "default";
1061 pinctrl-0 = <&i2c3_bus>;
1062};
1063
1064&prng {
1065 clocks = <&clock CLK_SSS>;
1066 clock-names = "secss";
1067};
1068
1069&pwm {
1070 clocks = <&clock CLK_PWM>;
1071 clock-names = "timers";
1072};
1073
1074&rtc {
1075 clocks = <&clock CLK_RTC>;
1076 clock-names = "rtc";
1077 interrupt-parent = <&pmu_system_controller>;
1078 status = "disabled";
1079};
1080
1081&serial_0 {
1082 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1083 clock-names = "uart", "clk_uart_baud0";
1084 dmas = <&pdma0 13>, <&pdma0 14>;
1085 dma-names = "rx", "tx";
1086};
1087
1088&serial_1 {
1089 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1090 clock-names = "uart", "clk_uart_baud0";
1091 dmas = <&pdma1 15>, <&pdma1 16>;
1092 dma-names = "rx", "tx";
1093};
1094
1095&serial_2 {
1096 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1097 clock-names = "uart", "clk_uart_baud0";
1098 dmas = <&pdma0 15>, <&pdma0 16>;
1099 dma-names = "rx", "tx";
1100};
1101
1102&serial_3 {
1103 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1104 clock-names = "uart", "clk_uart_baud0";
1105 dmas = <&pdma1 17>, <&pdma1 18>;
1106 dma-names = "rx", "tx";
1107};
1108
1109&sss {
1110 clocks = <&clock CLK_SSS>;
1111 clock-names = "secss";
1112};
1113
1114&trng {
1115 clocks = <&clock CLK_SSS>;
1116 clock-names = "secss";
1117};
1118
1119#include "exynos5250-pinctrl.dtsi"
1/*
2 * SAMSUNG EXYNOS5250 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#include <dt-bindings/clock/exynos5250.h>
21#include "exynos5.dtsi"
22#include "exynos4-cpu-thermal.dtsi"
23#include <dt-bindings/clock/exynos-audss-clk.h>
24
25/ {
26 compatible = "samsung,exynos5250", "samsung,exynos5";
27
28 aliases {
29 spi0 = &spi_0;
30 spi1 = &spi_1;
31 spi2 = &spi_2;
32 gsc0 = &gsc_0;
33 gsc1 = &gsc_1;
34 gsc2 = &gsc_2;
35 gsc3 = &gsc_3;
36 mshc0 = &mmc_0;
37 mshc1 = &mmc_1;
38 mshc2 = &mmc_2;
39 mshc3 = &mmc_3;
40 i2c4 = &i2c_4;
41 i2c5 = &i2c_5;
42 i2c6 = &i2c_6;
43 i2c7 = &i2c_7;
44 i2c8 = &i2c_8;
45 i2c9 = &i2c_9;
46 pinctrl0 = &pinctrl_0;
47 pinctrl1 = &pinctrl_1;
48 pinctrl2 = &pinctrl_2;
49 pinctrl3 = &pinctrl_3;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 cpu0: cpu@0 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a15";
59 reg = <0>;
60 clock-frequency = <1700000000>;
61 clocks = <&clock CLK_ARM_CLK>;
62 clock-names = "cpu";
63 clock-latency = <140000>;
64
65 operating-points = <
66 1700000 1300000
67 1600000 1250000
68 1500000 1225000
69 1400000 1200000
70 1300000 1150000
71 1200000 1125000
72 1100000 1100000
73 1000000 1075000
74 900000 1050000
75 800000 1025000
76 700000 1012500
77 600000 1000000
78 500000 975000
79 400000 950000
80 300000 937500
81 200000 925000
82 >;
83 cooling-min-level = <15>;
84 cooling-max-level = <9>;
85 #cooling-cells = <2>; /* min followed by max */
86 };
87 cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a15";
90 reg = <1>;
91 clock-frequency = <1700000000>;
92 };
93 };
94
95 soc: soc {
96 sysram@02020000 {
97 compatible = "mmio-sram";
98 reg = <0x02020000 0x30000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 0x02020000 0x30000>;
102
103 smp-sysram@0 {
104 compatible = "samsung,exynos4210-sysram";
105 reg = <0x0 0x1000>;
106 };
107
108 smp-sysram@2f000 {
109 compatible = "samsung,exynos4210-sysram-ns";
110 reg = <0x2f000 0x1000>;
111 };
112 };
113
114 pd_gsc: gsc-power-domain@10044000 {
115 compatible = "samsung,exynos4210-pd";
116 reg = <0x10044000 0x20>;
117 #power-domain-cells = <0>;
118 };
119
120 pd_mfc: mfc-power-domain@10044040 {
121 compatible = "samsung,exynos4210-pd";
122 reg = <0x10044040 0x20>;
123 #power-domain-cells = <0>;
124 };
125
126 pd_disp1: disp1-power-domain@100440A0 {
127 compatible = "samsung,exynos4210-pd";
128 reg = <0x100440A0 0x20>;
129 #power-domain-cells = <0>;
130 clocks = <&clock CLK_FIN_PLL>,
131 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
132 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
133 clock-names = "oscclk", "clk0", "clk1";
134 };
135
136 clock: clock-controller@10010000 {
137 compatible = "samsung,exynos5250-clock";
138 reg = <0x10010000 0x30000>;
139 #clock-cells = <1>;
140 };
141
142 clock_audss: audss-clock-controller@3810000 {
143 compatible = "samsung,exynos5250-audss-clock";
144 reg = <0x03810000 0x0C>;
145 #clock-cells = <1>;
146 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
147 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
148 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
149 };
150
151 timer {
152 compatible = "arm,armv7-timer";
153 interrupts = <1 13 0xf08>,
154 <1 14 0xf08>,
155 <1 11 0xf08>,
156 <1 10 0xf08>;
157 /*
158 * Unfortunately we need this since some versions
159 * of U-Boot on Exynos don't set the CNTFRQ register,
160 * so we need the value from DT.
161 */
162 clock-frequency = <24000000>;
163 };
164
165 mct@101C0000 {
166 compatible = "samsung,exynos4210-mct";
167 reg = <0x101C0000 0x800>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 interrupt-parent = <&mct_map>;
171 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
172 <4 0>, <5 0>;
173 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
174 clock-names = "fin_pll", "mct";
175
176 mct_map: mct-map {
177 #interrupt-cells = <2>;
178 #address-cells = <0>;
179 #size-cells = <0>;
180 interrupt-map = <0x0 0 &combiner 23 3>,
181 <0x1 0 &combiner 23 4>,
182 <0x2 0 &combiner 25 2>,
183 <0x3 0 &combiner 25 3>,
184 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
185 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
186 };
187 };
188
189 pmu {
190 compatible = "arm,cortex-a15-pmu";
191 interrupt-parent = <&combiner>;
192 interrupts = <1 2>, <22 4>;
193 };
194
195 pinctrl_0: pinctrl@11400000 {
196 compatible = "samsung,exynos5250-pinctrl";
197 reg = <0x11400000 0x1000>;
198 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
199
200 wakup_eint: wakeup-interrupt-controller {
201 compatible = "samsung,exynos4210-wakeup-eint";
202 interrupt-parent = <&gic>;
203 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
204 };
205 };
206
207 pinctrl_1: pinctrl@13400000 {
208 compatible = "samsung,exynos5250-pinctrl";
209 reg = <0x13400000 0x1000>;
210 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
211 };
212
213 pinctrl_2: pinctrl@10d10000 {
214 compatible = "samsung,exynos5250-pinctrl";
215 reg = <0x10d10000 0x1000>;
216 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
217 };
218
219 pinctrl_3: pinctrl@03860000 {
220 compatible = "samsung,exynos5250-pinctrl";
221 reg = <0x03860000 0x1000>;
222 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
223 };
224
225 pmu_system_controller: system-controller@10040000 {
226 compatible = "samsung,exynos5250-pmu", "syscon";
227 reg = <0x10040000 0x5000>;
228 clock-names = "clkout16";
229 clocks = <&clock CLK_FIN_PLL>;
230 #clock-cells = <1>;
231 interrupt-controller;
232 #interrupt-cells = <3>;
233 interrupt-parent = <&gic>;
234 };
235
236 watchdog@101D0000 {
237 compatible = "samsung,exynos5250-wdt";
238 reg = <0x101D0000 0x100>;
239 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&clock CLK_WDT>;
241 clock-names = "watchdog";
242 samsung,syscon-phandle = <&pmu_system_controller>;
243 };
244
245 g2d@10850000 {
246 compatible = "samsung,exynos5250-g2d";
247 reg = <0x10850000 0x1000>;
248 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&clock CLK_G2D>;
250 clock-names = "fimg2d";
251 iommus = <&sysmmu_g2d>;
252 };
253
254 mfc: codec@11000000 {
255 compatible = "samsung,mfc-v6";
256 reg = <0x11000000 0x10000>;
257 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
258 power-domains = <&pd_mfc>;
259 clocks = <&clock CLK_MFC>;
260 clock-names = "mfc";
261 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
262 iommu-names = "left", "right";
263 };
264
265 rotator: rotator@11C00000 {
266 compatible = "samsung,exynos5250-rotator";
267 reg = <0x11C00000 0x64>;
268 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clock CLK_ROTATOR>;
270 clock-names = "rotator";
271 iommus = <&sysmmu_rotator>;
272 };
273
274 tmu: tmu@10060000 {
275 compatible = "samsung,exynos5250-tmu";
276 reg = <0x10060000 0x100>;
277 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&clock CLK_TMU>;
279 clock-names = "tmu_apbif";
280 #include "exynos4412-tmu-sensor-conf.dtsi"
281 };
282
283 sata: sata@122F0000 {
284 compatible = "snps,dwc-ahci";
285 samsung,sata-freq = <66>;
286 reg = <0x122F0000 0x1ff>;
287 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
289 clock-names = "sata", "sclk_sata";
290 phys = <&sata_phy>;
291 phy-names = "sata-phy";
292 status = "disabled";
293 };
294
295 sata_phy: sata-phy@12170000 {
296 compatible = "samsung,exynos5250-sata-phy";
297 reg = <0x12170000 0x1ff>;
298 clocks = <&clock CLK_SATA_PHYCTRL>;
299 clock-names = "sata_phyctrl";
300 #phy-cells = <0>;
301 samsung,syscon-phandle = <&pmu_system_controller>;
302 status = "disabled";
303 };
304
305 /* i2c_0-3 are defined in exynos5.dtsi */
306 i2c_4: i2c@12CA0000 {
307 compatible = "samsung,s3c2440-i2c";
308 reg = <0x12CA0000 0x100>;
309 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 clocks = <&clock CLK_I2C4>;
313 clock-names = "i2c";
314 pinctrl-names = "default";
315 pinctrl-0 = <&i2c4_bus>;
316 status = "disabled";
317 };
318
319 i2c_5: i2c@12CB0000 {
320 compatible = "samsung,s3c2440-i2c";
321 reg = <0x12CB0000 0x100>;
322 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
323 #address-cells = <1>;
324 #size-cells = <0>;
325 clocks = <&clock CLK_I2C5>;
326 clock-names = "i2c";
327 pinctrl-names = "default";
328 pinctrl-0 = <&i2c5_bus>;
329 status = "disabled";
330 };
331
332 i2c_6: i2c@12CC0000 {
333 compatible = "samsung,s3c2440-i2c";
334 reg = <0x12CC0000 0x100>;
335 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 clocks = <&clock CLK_I2C6>;
339 clock-names = "i2c";
340 pinctrl-names = "default";
341 pinctrl-0 = <&i2c6_bus>;
342 status = "disabled";
343 };
344
345 i2c_7: i2c@12CD0000 {
346 compatible = "samsung,s3c2440-i2c";
347 reg = <0x12CD0000 0x100>;
348 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
349 #address-cells = <1>;
350 #size-cells = <0>;
351 clocks = <&clock CLK_I2C7>;
352 clock-names = "i2c";
353 pinctrl-names = "default";
354 pinctrl-0 = <&i2c7_bus>;
355 status = "disabled";
356 };
357
358 i2c_8: i2c@12CE0000 {
359 compatible = "samsung,s3c2440-hdmiphy-i2c";
360 reg = <0x12CE0000 0x1000>;
361 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 clocks = <&clock CLK_I2C_HDMI>;
365 clock-names = "i2c";
366 status = "disabled";
367 };
368
369 i2c_9: i2c@121D0000 {
370 compatible = "samsung,exynos5-sata-phy-i2c";
371 reg = <0x121D0000 0x100>;
372 #address-cells = <1>;
373 #size-cells = <0>;
374 clocks = <&clock CLK_SATA_PHYI2C>;
375 clock-names = "i2c";
376 status = "disabled";
377 };
378
379 spi_0: spi@12d20000 {
380 compatible = "samsung,exynos4210-spi";
381 status = "disabled";
382 reg = <0x12d20000 0x100>;
383 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
384 dmas = <&pdma0 5
385 &pdma0 4>;
386 dma-names = "tx", "rx";
387 #address-cells = <1>;
388 #size-cells = <0>;
389 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
390 clock-names = "spi", "spi_busclk0";
391 pinctrl-names = "default";
392 pinctrl-0 = <&spi0_bus>;
393 };
394
395 spi_1: spi@12d30000 {
396 compatible = "samsung,exynos4210-spi";
397 status = "disabled";
398 reg = <0x12d30000 0x100>;
399 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
400 dmas = <&pdma1 5
401 &pdma1 4>;
402 dma-names = "tx", "rx";
403 #address-cells = <1>;
404 #size-cells = <0>;
405 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
406 clock-names = "spi", "spi_busclk0";
407 pinctrl-names = "default";
408 pinctrl-0 = <&spi1_bus>;
409 };
410
411 spi_2: spi@12d40000 {
412 compatible = "samsung,exynos4210-spi";
413 status = "disabled";
414 reg = <0x12d40000 0x100>;
415 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
416 dmas = <&pdma0 7
417 &pdma0 6>;
418 dma-names = "tx", "rx";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
422 clock-names = "spi", "spi_busclk0";
423 pinctrl-names = "default";
424 pinctrl-0 = <&spi2_bus>;
425 };
426
427 mmc_0: mmc@12200000 {
428 compatible = "samsung,exynos5250-dw-mshc";
429 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 reg = <0x12200000 0x1000>;
433 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
434 clock-names = "biu", "ciu";
435 fifo-depth = <0x80>;
436 status = "disabled";
437 };
438
439 mmc_1: mmc@12210000 {
440 compatible = "samsung,exynos5250-dw-mshc";
441 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
442 #address-cells = <1>;
443 #size-cells = <0>;
444 reg = <0x12210000 0x1000>;
445 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
446 clock-names = "biu", "ciu";
447 fifo-depth = <0x80>;
448 status = "disabled";
449 };
450
451 mmc_2: mmc@12220000 {
452 compatible = "samsung,exynos5250-dw-mshc";
453 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 reg = <0x12220000 0x1000>;
457 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
458 clock-names = "biu", "ciu";
459 fifo-depth = <0x80>;
460 status = "disabled";
461 };
462
463 mmc_3: mmc@12230000 {
464 compatible = "samsung,exynos5250-dw-mshc";
465 reg = <0x12230000 0x1000>;
466 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
470 clock-names = "biu", "ciu";
471 fifo-depth = <0x80>;
472 status = "disabled";
473 };
474
475 i2s0: i2s@03830000 {
476 compatible = "samsung,s5pv210-i2s";
477 status = "disabled";
478 reg = <0x03830000 0x100>;
479 dmas = <&pdma0 10
480 &pdma0 9
481 &pdma0 8>;
482 dma-names = "tx", "rx", "tx-sec";
483 clocks = <&clock_audss EXYNOS_I2S_BUS>,
484 <&clock_audss EXYNOS_I2S_BUS>,
485 <&clock_audss EXYNOS_SCLK_I2S>;
486 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
487 samsung,idma-addr = <0x03000000>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&i2s0_bus>;
490 };
491
492 i2s1: i2s@12D60000 {
493 compatible = "samsung,s3c6410-i2s";
494 status = "disabled";
495 reg = <0x12D60000 0x100>;
496 dmas = <&pdma1 12
497 &pdma1 11>;
498 dma-names = "tx", "rx";
499 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
500 clock-names = "iis", "i2s_opclk0";
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2s1_bus>;
503 };
504
505 i2s2: i2s@12D70000 {
506 compatible = "samsung,s3c6410-i2s";
507 status = "disabled";
508 reg = <0x12D70000 0x100>;
509 dmas = <&pdma0 12
510 &pdma0 11>;
511 dma-names = "tx", "rx";
512 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
513 clock-names = "iis", "i2s_opclk0";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2s2_bus>;
516 };
517
518 usb_dwc3 {
519 compatible = "samsung,exynos5250-dwusb3";
520 clocks = <&clock CLK_USB3>;
521 clock-names = "usbdrd30";
522 #address-cells = <1>;
523 #size-cells = <1>;
524 ranges;
525
526 usbdrd_dwc3: dwc3@12000000 {
527 compatible = "synopsys,dwc3";
528 reg = <0x12000000 0x10000>;
529 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
530 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
531 phy-names = "usb2-phy", "usb3-phy";
532 };
533 };
534
535 usbdrd_phy: phy@12100000 {
536 compatible = "samsung,exynos5250-usbdrd-phy";
537 reg = <0x12100000 0x100>;
538 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
539 clock-names = "phy", "ref";
540 samsung,pmu-syscon = <&pmu_system_controller>;
541 #phy-cells = <1>;
542 };
543
544 ehci: usb@12110000 {
545 compatible = "samsung,exynos4210-ehci";
546 reg = <0x12110000 0x100>;
547 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
548
549 clocks = <&clock CLK_USB2>;
550 clock-names = "usbhost";
551 #address-cells = <1>;
552 #size-cells = <0>;
553 port@0 {
554 reg = <0>;
555 phys = <&usb2_phy_gen 1>;
556 };
557 };
558
559 ohci: usb@12120000 {
560 compatible = "samsung,exynos4210-ohci";
561 reg = <0x12120000 0x100>;
562 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
563
564 clocks = <&clock CLK_USB2>;
565 clock-names = "usbhost";
566 #address-cells = <1>;
567 #size-cells = <0>;
568 port@0 {
569 reg = <0>;
570 phys = <&usb2_phy_gen 1>;
571 };
572 };
573
574 usb2_phy_gen: phy@12130000 {
575 compatible = "samsung,exynos5250-usb2-phy";
576 reg = <0x12130000 0x100>;
577 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
578 clock-names = "phy", "ref";
579 #phy-cells = <1>;
580 samsung,sysreg-phandle = <&sysreg_system_controller>;
581 samsung,pmureg-phandle = <&pmu_system_controller>;
582 };
583
584 amba {
585 #address-cells = <1>;
586 #size-cells = <1>;
587 compatible = "simple-bus";
588 interrupt-parent = <&gic>;
589 ranges;
590
591 pdma0: pdma@121A0000 {
592 compatible = "arm,pl330", "arm,primecell";
593 reg = <0x121A0000 0x1000>;
594 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&clock CLK_PDMA0>;
596 clock-names = "apb_pclk";
597 #dma-cells = <1>;
598 #dma-channels = <8>;
599 #dma-requests = <32>;
600 };
601
602 pdma1: pdma@121B0000 {
603 compatible = "arm,pl330", "arm,primecell";
604 reg = <0x121B0000 0x1000>;
605 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&clock CLK_PDMA1>;
607 clock-names = "apb_pclk";
608 #dma-cells = <1>;
609 #dma-channels = <8>;
610 #dma-requests = <32>;
611 };
612
613 mdma0: mdma@10800000 {
614 compatible = "arm,pl330", "arm,primecell";
615 reg = <0x10800000 0x1000>;
616 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&clock CLK_MDMA0>;
618 clock-names = "apb_pclk";
619 #dma-cells = <1>;
620 #dma-channels = <8>;
621 #dma-requests = <1>;
622 };
623
624 mdma1: mdma@11C10000 {
625 compatible = "arm,pl330", "arm,primecell";
626 reg = <0x11C10000 0x1000>;
627 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&clock CLK_MDMA1>;
629 clock-names = "apb_pclk";
630 #dma-cells = <1>;
631 #dma-channels = <8>;
632 #dma-requests = <1>;
633 };
634 };
635
636 gsc_0: gsc@13e00000 {
637 compatible = "samsung,exynos5-gsc";
638 reg = <0x13e00000 0x1000>;
639 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
640 power-domains = <&pd_gsc>;
641 clocks = <&clock CLK_GSCL0>;
642 clock-names = "gscl";
643 iommu = <&sysmmu_gsc0>;
644 };
645
646 gsc_1: gsc@13e10000 {
647 compatible = "samsung,exynos5-gsc";
648 reg = <0x13e10000 0x1000>;
649 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
650 power-domains = <&pd_gsc>;
651 clocks = <&clock CLK_GSCL1>;
652 clock-names = "gscl";
653 iommu = <&sysmmu_gsc1>;
654 };
655
656 gsc_2: gsc@13e20000 {
657 compatible = "samsung,exynos5-gsc";
658 reg = <0x13e20000 0x1000>;
659 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
660 power-domains = <&pd_gsc>;
661 clocks = <&clock CLK_GSCL2>;
662 clock-names = "gscl";
663 iommu = <&sysmmu_gsc2>;
664 };
665
666 gsc_3: gsc@13e30000 {
667 compatible = "samsung,exynos5-gsc";
668 reg = <0x13e30000 0x1000>;
669 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
670 power-domains = <&pd_gsc>;
671 clocks = <&clock CLK_GSCL3>;
672 clock-names = "gscl";
673 iommu = <&sysmmu_gsc3>;
674 };
675
676 hdmi: hdmi@14530000 {
677 compatible = "samsung,exynos4212-hdmi";
678 reg = <0x14530000 0x70000>;
679 power-domains = <&pd_disp1>;
680 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
682 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
683 <&clock CLK_MOUT_HDMI>;
684 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
685 "sclk_hdmiphy", "mout_hdmi";
686 samsung,syscon-phandle = <&pmu_system_controller>;
687 };
688
689 mixer@14450000 {
690 compatible = "samsung,exynos5250-mixer";
691 reg = <0x14450000 0x10000>;
692 power-domains = <&pd_disp1>;
693 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
695 <&clock CLK_SCLK_HDMI>;
696 clock-names = "mixer", "hdmi", "sclk_hdmi";
697 iommus = <&sysmmu_tv>;
698 };
699
700 dp_phy: video-phy {
701 compatible = "samsung,exynos5250-dp-video-phy";
702 samsung,pmu-syscon = <&pmu_system_controller>;
703 #phy-cells = <0>;
704 };
705
706 adc: adc@12D10000 {
707 compatible = "samsung,exynos-adc-v1";
708 reg = <0x12D10000 0x100>;
709 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&clock CLK_ADC>;
711 clock-names = "adc";
712 #io-channel-cells = <1>;
713 io-channel-ranges;
714 samsung,syscon-phandle = <&pmu_system_controller>;
715 status = "disabled";
716 };
717
718 sss@10830000 {
719 compatible = "samsung,exynos4210-secss";
720 reg = <0x10830000 0x300>;
721 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&clock CLK_SSS>;
723 clock-names = "secss";
724 };
725
726 sysmmu_g2d: sysmmu@10A60000 {
727 compatible = "samsung,exynos-sysmmu";
728 reg = <0x10A60000 0x1000>;
729 interrupt-parent = <&combiner>;
730 interrupts = <24 5>;
731 clock-names = "sysmmu", "master";
732 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
733 #iommu-cells = <0>;
734 };
735
736 sysmmu_mfc_r: sysmmu@11200000 {
737 compatible = "samsung,exynos-sysmmu";
738 reg = <0x11200000 0x1000>;
739 interrupt-parent = <&combiner>;
740 interrupts = <6 2>;
741 power-domains = <&pd_mfc>;
742 clock-names = "sysmmu", "master";
743 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
744 #iommu-cells = <0>;
745 };
746
747 sysmmu_mfc_l: sysmmu@11210000 {
748 compatible = "samsung,exynos-sysmmu";
749 reg = <0x11210000 0x1000>;
750 interrupt-parent = <&combiner>;
751 interrupts = <8 5>;
752 power-domains = <&pd_mfc>;
753 clock-names = "sysmmu", "master";
754 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
755 #iommu-cells = <0>;
756 };
757
758 sysmmu_rotator: sysmmu@11D40000 {
759 compatible = "samsung,exynos-sysmmu";
760 reg = <0x11D40000 0x1000>;
761 interrupt-parent = <&combiner>;
762 interrupts = <4 0>;
763 clock-names = "sysmmu", "master";
764 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
765 #iommu-cells = <0>;
766 };
767
768 sysmmu_jpeg: sysmmu@11F20000 {
769 compatible = "samsung,exynos-sysmmu";
770 reg = <0x11F20000 0x1000>;
771 interrupt-parent = <&combiner>;
772 interrupts = <4 2>;
773 power-domains = <&pd_gsc>;
774 clock-names = "sysmmu", "master";
775 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
776 #iommu-cells = <0>;
777 };
778
779 sysmmu_fimc_isp: sysmmu@13260000 {
780 compatible = "samsung,exynos-sysmmu";
781 reg = <0x13260000 0x1000>;
782 interrupt-parent = <&combiner>;
783 interrupts = <10 6>;
784 clock-names = "sysmmu";
785 clocks = <&clock CLK_SMMU_FIMC_ISP>;
786 #iommu-cells = <0>;
787 };
788
789 sysmmu_fimc_drc: sysmmu@13270000 {
790 compatible = "samsung,exynos-sysmmu";
791 reg = <0x13270000 0x1000>;
792 interrupt-parent = <&combiner>;
793 interrupts = <11 6>;
794 clock-names = "sysmmu";
795 clocks = <&clock CLK_SMMU_FIMC_DRC>;
796 #iommu-cells = <0>;
797 };
798
799 sysmmu_fimc_fd: sysmmu@132A0000 {
800 compatible = "samsung,exynos-sysmmu";
801 reg = <0x132A0000 0x1000>;
802 interrupt-parent = <&combiner>;
803 interrupts = <5 0>;
804 clock-names = "sysmmu";
805 clocks = <&clock CLK_SMMU_FIMC_FD>;
806 #iommu-cells = <0>;
807 };
808
809 sysmmu_fimc_scc: sysmmu@13280000 {
810 compatible = "samsung,exynos-sysmmu";
811 reg = <0x13280000 0x1000>;
812 interrupt-parent = <&combiner>;
813 interrupts = <5 2>;
814 clock-names = "sysmmu";
815 clocks = <&clock CLK_SMMU_FIMC_SCC>;
816 #iommu-cells = <0>;
817 };
818
819 sysmmu_fimc_scp: sysmmu@13290000 {
820 compatible = "samsung,exynos-sysmmu";
821 reg = <0x13290000 0x1000>;
822 interrupt-parent = <&combiner>;
823 interrupts = <3 6>;
824 clock-names = "sysmmu";
825 clocks = <&clock CLK_SMMU_FIMC_SCP>;
826 #iommu-cells = <0>;
827 };
828
829 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
830 compatible = "samsung,exynos-sysmmu";
831 reg = <0x132B0000 0x1000>;
832 interrupt-parent = <&combiner>;
833 interrupts = <5 4>;
834 clock-names = "sysmmu";
835 clocks = <&clock CLK_SMMU_FIMC_MCU>;
836 #iommu-cells = <0>;
837 };
838
839 sysmmu_fimc_odc: sysmmu@132C0000 {
840 compatible = "samsung,exynos-sysmmu";
841 reg = <0x132C0000 0x1000>;
842 interrupt-parent = <&combiner>;
843 interrupts = <11 0>;
844 clock-names = "sysmmu";
845 clocks = <&clock CLK_SMMU_FIMC_ODC>;
846 #iommu-cells = <0>;
847 };
848
849 sysmmu_fimc_dis0: sysmmu@132D0000 {
850 compatible = "samsung,exynos-sysmmu";
851 reg = <0x132D0000 0x1000>;
852 interrupt-parent = <&combiner>;
853 interrupts = <10 4>;
854 clock-names = "sysmmu";
855 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
856 #iommu-cells = <0>;
857 };
858
859 sysmmu_fimc_dis1: sysmmu@132E0000{
860 compatible = "samsung,exynos-sysmmu";
861 reg = <0x132E0000 0x1000>;
862 interrupt-parent = <&combiner>;
863 interrupts = <9 4>;
864 clock-names = "sysmmu";
865 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
866 #iommu-cells = <0>;
867 };
868
869 sysmmu_fimc_3dnr: sysmmu@132F0000 {
870 compatible = "samsung,exynos-sysmmu";
871 reg = <0x132F0000 0x1000>;
872 interrupt-parent = <&combiner>;
873 interrupts = <5 6>;
874 clock-names = "sysmmu";
875 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
876 #iommu-cells = <0>;
877 };
878
879 sysmmu_fimc_lite0: sysmmu@13C40000 {
880 compatible = "samsung,exynos-sysmmu";
881 reg = <0x13C40000 0x1000>;
882 interrupt-parent = <&combiner>;
883 interrupts = <3 4>;
884 power-domains = <&pd_gsc>;
885 clock-names = "sysmmu", "master";
886 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
887 #iommu-cells = <0>;
888 };
889
890 sysmmu_fimc_lite1: sysmmu@13C50000 {
891 compatible = "samsung,exynos-sysmmu";
892 reg = <0x13C50000 0x1000>;
893 interrupt-parent = <&combiner>;
894 interrupts = <24 1>;
895 power-domains = <&pd_gsc>;
896 clock-names = "sysmmu", "master";
897 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
898 #iommu-cells = <0>;
899 };
900
901 sysmmu_gsc0: sysmmu@13E80000 {
902 compatible = "samsung,exynos-sysmmu";
903 reg = <0x13E80000 0x1000>;
904 interrupt-parent = <&combiner>;
905 interrupts = <2 0>;
906 power-domains = <&pd_gsc>;
907 clock-names = "sysmmu", "master";
908 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
909 #iommu-cells = <0>;
910 };
911
912 sysmmu_gsc1: sysmmu@13E90000 {
913 compatible = "samsung,exynos-sysmmu";
914 reg = <0x13E90000 0x1000>;
915 interrupt-parent = <&combiner>;
916 interrupts = <2 2>;
917 power-domains = <&pd_gsc>;
918 clock-names = "sysmmu", "master";
919 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
920 #iommu-cells = <0>;
921 };
922
923 sysmmu_gsc2: sysmmu@13EA0000 {
924 compatible = "samsung,exynos-sysmmu";
925 reg = <0x13EA0000 0x1000>;
926 interrupt-parent = <&combiner>;
927 interrupts = <2 4>;
928 power-domains = <&pd_gsc>;
929 clock-names = "sysmmu", "master";
930 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
931 #iommu-cells = <0>;
932 };
933
934 sysmmu_gsc3: sysmmu@13EB0000 {
935 compatible = "samsung,exynos-sysmmu";
936 reg = <0x13EB0000 0x1000>;
937 interrupt-parent = <&combiner>;
938 interrupts = <2 6>;
939 power-domains = <&pd_gsc>;
940 clock-names = "sysmmu", "master";
941 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
942 #iommu-cells = <0>;
943 };
944
945 sysmmu_fimd1: sysmmu@14640000 {
946 compatible = "samsung,exynos-sysmmu";
947 reg = <0x14640000 0x1000>;
948 interrupt-parent = <&combiner>;
949 interrupts = <3 2>;
950 power-domains = <&pd_disp1>;
951 clock-names = "sysmmu", "master";
952 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
953 #iommu-cells = <0>;
954 };
955
956 sysmmu_tv: sysmmu@14650000 {
957 compatible = "samsung,exynos-sysmmu";
958 reg = <0x14650000 0x1000>;
959 interrupt-parent = <&combiner>;
960 interrupts = <7 4>;
961 power-domains = <&pd_disp1>;
962 clock-names = "sysmmu", "master";
963 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
964 #iommu-cells = <0>;
965 };
966 };
967
968 thermal-zones {
969 cpu_thermal: cpu-thermal {
970 polling-delay-passive = <0>;
971 polling-delay = <0>;
972 thermal-sensors = <&tmu 0>;
973
974 cooling-maps {
975 map0 {
976 /* Corresponds to 800MHz at freq_table */
977 cooling-device = <&cpu0 9 9>;
978 };
979 map1 {
980 /* Corresponds to 200MHz at freq_table */
981 cooling-device = <&cpu0 15 15>;
982 };
983 };
984 };
985 };
986};
987
988&dp {
989 power-domains = <&pd_disp1>;
990 clocks = <&clock CLK_DP>;
991 clock-names = "dp";
992 phys = <&dp_phy>;
993 phy-names = "dp";
994};
995
996&fimd {
997 power-domains = <&pd_disp1>;
998 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
999 clock-names = "sclk_fimd", "fimd";
1000 iommus = <&sysmmu_fimd1>;
1001};
1002
1003&i2c_0 {
1004 clocks = <&clock CLK_I2C0>;
1005 clock-names = "i2c";
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&i2c0_bus>;
1008};
1009
1010&i2c_1 {
1011 clocks = <&clock CLK_I2C1>;
1012 clock-names = "i2c";
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&i2c1_bus>;
1015};
1016
1017&i2c_2 {
1018 clocks = <&clock CLK_I2C2>;
1019 clock-names = "i2c";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&i2c2_bus>;
1022};
1023
1024&i2c_3 {
1025 clocks = <&clock CLK_I2C3>;
1026 clock-names = "i2c";
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&i2c3_bus>;
1029};
1030
1031&pwm {
1032 clocks = <&clock CLK_PWM>;
1033 clock-names = "timers";
1034};
1035
1036&rtc {
1037 clocks = <&clock CLK_RTC>;
1038 clock-names = "rtc";
1039 interrupt-parent = <&pmu_system_controller>;
1040 status = "disabled";
1041};
1042
1043&serial_0 {
1044 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1045 clock-names = "uart", "clk_uart_baud0";
1046};
1047
1048&serial_1 {
1049 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1050 clock-names = "uart", "clk_uart_baud0";
1051};
1052
1053&serial_2 {
1054 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1055 clock-names = "uart", "clk_uart_baud0";
1056};
1057
1058&serial_3 {
1059 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1060 clock-names = "uart", "clk_uart_baud0";
1061};
1062
1063#include "exynos5250-pinctrl.dtsi"