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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
5 */
6#include <linux/etherdevice.h>
7#include <linux/if_bridge.h>
8#include <linux/iopoll.h>
9#include <linux/mdio.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
13#include <linux/of_mdio.h>
14#include <linux/of_net.h>
15#include <linux/of_platform.h>
16#include <linux/phylink.h>
17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19#include <linux/reset.h>
20#include <linux/gpio/consumer.h>
21#include <net/dsa.h>
22
23#include "mt7530.h"
24
25/* String, offset, and register size in bytes if different from 4 bytes */
26static const struct mt7530_mib_desc mt7530_mib[] = {
27 MIB_DESC(1, 0x00, "TxDrop"),
28 MIB_DESC(1, 0x04, "TxCrcErr"),
29 MIB_DESC(1, 0x08, "TxUnicast"),
30 MIB_DESC(1, 0x0c, "TxMulticast"),
31 MIB_DESC(1, 0x10, "TxBroadcast"),
32 MIB_DESC(1, 0x14, "TxCollision"),
33 MIB_DESC(1, 0x18, "TxSingleCollision"),
34 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
35 MIB_DESC(1, 0x20, "TxDeferred"),
36 MIB_DESC(1, 0x24, "TxLateCollision"),
37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
38 MIB_DESC(1, 0x2c, "TxPause"),
39 MIB_DESC(1, 0x30, "TxPktSz64"),
40 MIB_DESC(1, 0x34, "TxPktSz65To127"),
41 MIB_DESC(1, 0x38, "TxPktSz128To255"),
42 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
43 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
44 MIB_DESC(1, 0x44, "Tx1024ToMax"),
45 MIB_DESC(2, 0x48, "TxBytes"),
46 MIB_DESC(1, 0x60, "RxDrop"),
47 MIB_DESC(1, 0x64, "RxFiltering"),
48 MIB_DESC(1, 0x6c, "RxMulticast"),
49 MIB_DESC(1, 0x70, "RxBroadcast"),
50 MIB_DESC(1, 0x74, "RxAlignErr"),
51 MIB_DESC(1, 0x78, "RxCrcErr"),
52 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
53 MIB_DESC(1, 0x80, "RxFragErr"),
54 MIB_DESC(1, 0x84, "RxOverSzErr"),
55 MIB_DESC(1, 0x88, "RxJabberErr"),
56 MIB_DESC(1, 0x8c, "RxPause"),
57 MIB_DESC(1, 0x90, "RxPktSz64"),
58 MIB_DESC(1, 0x94, "RxPktSz65To127"),
59 MIB_DESC(1, 0x98, "RxPktSz128To255"),
60 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
61 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
62 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
63 MIB_DESC(2, 0xa8, "RxBytes"),
64 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
65 MIB_DESC(1, 0xb4, "RxIngressDrop"),
66 MIB_DESC(1, 0xb8, "RxArlDrop"),
67};
68
69static int
70core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
71{
72 struct mii_bus *bus = priv->bus;
73 int value, ret;
74
75 /* Write the desired MMD Devad */
76 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
77 if (ret < 0)
78 goto err;
79
80 /* Write the desired MMD register address */
81 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
82 if (ret < 0)
83 goto err;
84
85 /* Select the Function : DATA with no post increment */
86 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
87 if (ret < 0)
88 goto err;
89
90 /* Read the content of the MMD's selected register */
91 value = bus->read(bus, 0, MII_MMD_DATA);
92
93 return value;
94err:
95 dev_err(&bus->dev, "failed to read mmd register\n");
96
97 return ret;
98}
99
100static int
101core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
102 int devad, u32 data)
103{
104 struct mii_bus *bus = priv->bus;
105 int ret;
106
107 /* Write the desired MMD Devad */
108 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
109 if (ret < 0)
110 goto err;
111
112 /* Write the desired MMD register address */
113 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
114 if (ret < 0)
115 goto err;
116
117 /* Select the Function : DATA with no post increment */
118 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
119 if (ret < 0)
120 goto err;
121
122 /* Write the data into MMD's selected register */
123 ret = bus->write(bus, 0, MII_MMD_DATA, data);
124err:
125 if (ret < 0)
126 dev_err(&bus->dev,
127 "failed to write mmd register\n");
128 return ret;
129}
130
131static void
132core_write(struct mt7530_priv *priv, u32 reg, u32 val)
133{
134 struct mii_bus *bus = priv->bus;
135
136 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
137
138 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
139
140 mutex_unlock(&bus->mdio_lock);
141}
142
143static void
144core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
145{
146 struct mii_bus *bus = priv->bus;
147 u32 val;
148
149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
150
151 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
152 val &= ~mask;
153 val |= set;
154 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
155
156 mutex_unlock(&bus->mdio_lock);
157}
158
159static void
160core_set(struct mt7530_priv *priv, u32 reg, u32 val)
161{
162 core_rmw(priv, reg, 0, val);
163}
164
165static void
166core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
167{
168 core_rmw(priv, reg, val, 0);
169}
170
171static int
172mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
173{
174 struct mii_bus *bus = priv->bus;
175 u16 page, r, lo, hi;
176 int ret;
177
178 page = (reg >> 6) & 0x3ff;
179 r = (reg >> 2) & 0xf;
180 lo = val & 0xffff;
181 hi = val >> 16;
182
183 /* MT7530 uses 31 as the pseudo port */
184 ret = bus->write(bus, 0x1f, 0x1f, page);
185 if (ret < 0)
186 goto err;
187
188 ret = bus->write(bus, 0x1f, r, lo);
189 if (ret < 0)
190 goto err;
191
192 ret = bus->write(bus, 0x1f, 0x10, hi);
193err:
194 if (ret < 0)
195 dev_err(&bus->dev,
196 "failed to write mt7530 register\n");
197 return ret;
198}
199
200static u32
201mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
202{
203 struct mii_bus *bus = priv->bus;
204 u16 page, r, lo, hi;
205 int ret;
206
207 page = (reg >> 6) & 0x3ff;
208 r = (reg >> 2) & 0xf;
209
210 /* MT7530 uses 31 as the pseudo port */
211 ret = bus->write(bus, 0x1f, 0x1f, page);
212 if (ret < 0) {
213 dev_err(&bus->dev,
214 "failed to read mt7530 register\n");
215 return ret;
216 }
217
218 lo = bus->read(bus, 0x1f, r);
219 hi = bus->read(bus, 0x1f, 0x10);
220
221 return (hi << 16) | (lo & 0xffff);
222}
223
224static void
225mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
226{
227 struct mii_bus *bus = priv->bus;
228
229 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
230
231 mt7530_mii_write(priv, reg, val);
232
233 mutex_unlock(&bus->mdio_lock);
234}
235
236static u32
237_mt7530_read(struct mt7530_dummy_poll *p)
238{
239 struct mii_bus *bus = p->priv->bus;
240 u32 val;
241
242 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
243
244 val = mt7530_mii_read(p->priv, p->reg);
245
246 mutex_unlock(&bus->mdio_lock);
247
248 return val;
249}
250
251static u32
252mt7530_read(struct mt7530_priv *priv, u32 reg)
253{
254 struct mt7530_dummy_poll p;
255
256 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
257 return _mt7530_read(&p);
258}
259
260static void
261mt7530_rmw(struct mt7530_priv *priv, u32 reg,
262 u32 mask, u32 set)
263{
264 struct mii_bus *bus = priv->bus;
265 u32 val;
266
267 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
268
269 val = mt7530_mii_read(priv, reg);
270 val &= ~mask;
271 val |= set;
272 mt7530_mii_write(priv, reg, val);
273
274 mutex_unlock(&bus->mdio_lock);
275}
276
277static void
278mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
279{
280 mt7530_rmw(priv, reg, 0, val);
281}
282
283static void
284mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
285{
286 mt7530_rmw(priv, reg, val, 0);
287}
288
289static int
290mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
291{
292 u32 val;
293 int ret;
294 struct mt7530_dummy_poll p;
295
296 /* Set the command operating upon the MAC address entries */
297 val = ATC_BUSY | ATC_MAT(0) | cmd;
298 mt7530_write(priv, MT7530_ATC, val);
299
300 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
301 ret = readx_poll_timeout(_mt7530_read, &p, val,
302 !(val & ATC_BUSY), 20, 20000);
303 if (ret < 0) {
304 dev_err(priv->dev, "reset timeout\n");
305 return ret;
306 }
307
308 /* Additional sanity for read command if the specified
309 * entry is invalid
310 */
311 val = mt7530_read(priv, MT7530_ATC);
312 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
313 return -EINVAL;
314
315 if (rsp)
316 *rsp = val;
317
318 return 0;
319}
320
321static void
322mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
323{
324 u32 reg[3];
325 int i;
326
327 /* Read from ARL table into an array */
328 for (i = 0; i < 3; i++) {
329 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
330
331 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
332 __func__, __LINE__, i, reg[i]);
333 }
334
335 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
336 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
337 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
338 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
339 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
340 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
341 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
342 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
343 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
344 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
345}
346
347static void
348mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
349 u8 port_mask, const u8 *mac,
350 u8 aging, u8 type)
351{
352 u32 reg[3] = { 0 };
353 int i;
354
355 reg[1] |= vid & CVID_MASK;
356 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
357 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
358 /* STATIC_ENT indicate that entry is static wouldn't
359 * be aged out and STATIC_EMP specified as erasing an
360 * entry
361 */
362 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
363 reg[1] |= mac[5] << MAC_BYTE_5;
364 reg[1] |= mac[4] << MAC_BYTE_4;
365 reg[0] |= mac[3] << MAC_BYTE_3;
366 reg[0] |= mac[2] << MAC_BYTE_2;
367 reg[0] |= mac[1] << MAC_BYTE_1;
368 reg[0] |= mac[0] << MAC_BYTE_0;
369
370 /* Write array into the ARL table */
371 for (i = 0; i < 3; i++)
372 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
373}
374
375static int
376mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
377{
378 struct mt7530_priv *priv = ds->priv;
379 u32 ncpo1, ssc_delta, trgint, i, xtal;
380
381 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
382
383 if (xtal == HWTRAP_XTAL_20MHZ) {
384 dev_err(priv->dev,
385 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
386 __func__);
387 return -EINVAL;
388 }
389
390 switch (mode) {
391 case PHY_INTERFACE_MODE_RGMII:
392 trgint = 0;
393 /* PLL frequency: 125MHz */
394 ncpo1 = 0x0c80;
395 break;
396 case PHY_INTERFACE_MODE_TRGMII:
397 trgint = 1;
398 if (priv->id == ID_MT7621) {
399 /* PLL frequency: 150MHz: 1.2GBit */
400 if (xtal == HWTRAP_XTAL_40MHZ)
401 ncpo1 = 0x0780;
402 if (xtal == HWTRAP_XTAL_25MHZ)
403 ncpo1 = 0x0a00;
404 } else { /* PLL frequency: 250MHz: 2.0Gbit */
405 if (xtal == HWTRAP_XTAL_40MHZ)
406 ncpo1 = 0x0c80;
407 if (xtal == HWTRAP_XTAL_25MHZ)
408 ncpo1 = 0x1400;
409 }
410 break;
411 default:
412 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
413 return -EINVAL;
414 }
415
416 if (xtal == HWTRAP_XTAL_25MHZ)
417 ssc_delta = 0x57;
418 else
419 ssc_delta = 0x87;
420
421 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
422 P6_INTF_MODE(trgint));
423
424 /* Lower Tx Driving for TRGMII path */
425 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
426 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
427 TD_DM_DRVP(8) | TD_DM_DRVN(8));
428
429 /* Setup core clock for MT7530 */
430 if (!trgint) {
431 /* Disable MT7530 core clock */
432 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
433
434 /* Disable PLL, since phy_device has not yet been created
435 * provided for phy_[read,write]_mmd_indirect is called, we
436 * provide our own core_write_mmd_indirect to complete this
437 * function.
438 */
439 core_write_mmd_indirect(priv,
440 CORE_GSWPLL_GRP1,
441 MDIO_MMD_VEND2,
442 0);
443
444 /* Set core clock into 500Mhz */
445 core_write(priv, CORE_GSWPLL_GRP2,
446 RG_GSWPLL_POSDIV_500M(1) |
447 RG_GSWPLL_FBKDIV_500M(25));
448
449 /* Enable PLL */
450 core_write(priv, CORE_GSWPLL_GRP1,
451 RG_GSWPLL_EN_PRE |
452 RG_GSWPLL_POSDIV_200M(2) |
453 RG_GSWPLL_FBKDIV_200M(32));
454
455 /* Enable MT7530 core clock */
456 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
457 }
458
459 /* Setup the MT7530 TRGMII Tx Clock */
460 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
461 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
462 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
463 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
464 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
465 core_write(priv, CORE_PLL_GROUP4,
466 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
467 RG_SYSPLL_BIAS_LPF_EN);
468 core_write(priv, CORE_PLL_GROUP2,
469 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
470 RG_SYSPLL_POSDIV(1));
471 core_write(priv, CORE_PLL_GROUP7,
472 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
473 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
474 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
475 REG_GSWCK_EN | REG_TRGMIICK_EN);
476
477 if (!trgint)
478 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
479 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
480 RD_TAP_MASK, RD_TAP(16));
481 return 0;
482}
483
484static void
485mt7530_mib_reset(struct dsa_switch *ds)
486{
487 struct mt7530_priv *priv = ds->priv;
488
489 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
490 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
491}
492
493static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
494{
495 struct mt7530_priv *priv = ds->priv;
496
497 return mdiobus_read_nested(priv->bus, port, regnum);
498}
499
500static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
501 u16 val)
502{
503 struct mt7530_priv *priv = ds->priv;
504
505 return mdiobus_write_nested(priv->bus, port, regnum, val);
506}
507
508static void
509mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
510 uint8_t *data)
511{
512 int i;
513
514 if (stringset != ETH_SS_STATS)
515 return;
516
517 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
518 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
519 ETH_GSTRING_LEN);
520}
521
522static void
523mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
524 uint64_t *data)
525{
526 struct mt7530_priv *priv = ds->priv;
527 const struct mt7530_mib_desc *mib;
528 u32 reg, i;
529 u64 hi;
530
531 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
532 mib = &mt7530_mib[i];
533 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
534
535 data[i] = mt7530_read(priv, reg);
536 if (mib->size == 2) {
537 hi = mt7530_read(priv, reg + 4);
538 data[i] |= hi << 32;
539 }
540 }
541}
542
543static int
544mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
545{
546 if (sset != ETH_SS_STATS)
547 return 0;
548
549 return ARRAY_SIZE(mt7530_mib);
550}
551
552static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
553{
554 struct mt7530_priv *priv = ds->priv;
555 u8 tx_delay = 0;
556 int val;
557
558 mutex_lock(&priv->reg_mutex);
559
560 val = mt7530_read(priv, MT7530_MHWTRAP);
561
562 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
563 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
564
565 switch (priv->p5_intf_sel) {
566 case P5_INTF_SEL_PHY_P0:
567 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
568 val |= MHWTRAP_PHY0_SEL;
569 fallthrough;
570 case P5_INTF_SEL_PHY_P4:
571 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
572 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
573
574 /* Setup the MAC by default for the cpu port */
575 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
576 break;
577 case P5_INTF_SEL_GMAC5:
578 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
579 val &= ~MHWTRAP_P5_DIS;
580 break;
581 case P5_DISABLED:
582 interface = PHY_INTERFACE_MODE_NA;
583 break;
584 default:
585 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
586 priv->p5_intf_sel);
587 goto unlock_exit;
588 }
589
590 /* Setup RGMII settings */
591 if (phy_interface_mode_is_rgmii(interface)) {
592 val |= MHWTRAP_P5_RGMII_MODE;
593
594 /* P5 RGMII RX Clock Control: delay setting for 1000M */
595 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
596
597 /* Don't set delay in DSA mode */
598 if (!dsa_is_dsa_port(priv->ds, 5) &&
599 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
600 interface == PHY_INTERFACE_MODE_RGMII_ID))
601 tx_delay = 4; /* n * 0.5 ns */
602
603 /* P5 RGMII TX Clock Control: delay x */
604 mt7530_write(priv, MT7530_P5RGMIITXCR,
605 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
606
607 /* reduce P5 RGMII Tx driving, 8mA */
608 mt7530_write(priv, MT7530_IO_DRV_CR,
609 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
610 }
611
612 mt7530_write(priv, MT7530_MHWTRAP, val);
613
614 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
615 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
616
617 priv->p5_interface = interface;
618
619unlock_exit:
620 mutex_unlock(&priv->reg_mutex);
621}
622
623static int
624mt7530_cpu_port_enable(struct mt7530_priv *priv,
625 int port)
626{
627 /* Enable Mediatek header mode on the cpu port */
628 mt7530_write(priv, MT7530_PVC_P(port),
629 PORT_SPEC_TAG);
630
631 /* Unknown multicast frame forwarding to the cpu port */
632 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
633
634 /* Set CPU port number */
635 if (priv->id == ID_MT7621)
636 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
637
638 /* CPU port gets connected to all user ports of
639 * the switch
640 */
641 mt7530_write(priv, MT7530_PCR_P(port),
642 PCR_MATRIX(dsa_user_ports(priv->ds)));
643
644 return 0;
645}
646
647static int
648mt7530_port_enable(struct dsa_switch *ds, int port,
649 struct phy_device *phy)
650{
651 struct mt7530_priv *priv = ds->priv;
652
653 if (!dsa_is_user_port(ds, port))
654 return 0;
655
656 mutex_lock(&priv->reg_mutex);
657
658 /* Allow the user port gets connected to the cpu port and also
659 * restore the port matrix if the port is the member of a certain
660 * bridge.
661 */
662 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
663 priv->ports[port].enable = true;
664 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
665 priv->ports[port].pm);
666 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
667
668 mutex_unlock(&priv->reg_mutex);
669
670 return 0;
671}
672
673static void
674mt7530_port_disable(struct dsa_switch *ds, int port)
675{
676 struct mt7530_priv *priv = ds->priv;
677
678 if (!dsa_is_user_port(ds, port))
679 return;
680
681 mutex_lock(&priv->reg_mutex);
682
683 /* Clear up all port matrix which could be restored in the next
684 * enablement for the port.
685 */
686 priv->ports[port].enable = false;
687 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
688 PCR_MATRIX_CLR);
689 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
690
691 mutex_unlock(&priv->reg_mutex);
692}
693
694static void
695mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
696{
697 struct mt7530_priv *priv = ds->priv;
698 u32 stp_state;
699
700 switch (state) {
701 case BR_STATE_DISABLED:
702 stp_state = MT7530_STP_DISABLED;
703 break;
704 case BR_STATE_BLOCKING:
705 stp_state = MT7530_STP_BLOCKING;
706 break;
707 case BR_STATE_LISTENING:
708 stp_state = MT7530_STP_LISTENING;
709 break;
710 case BR_STATE_LEARNING:
711 stp_state = MT7530_STP_LEARNING;
712 break;
713 case BR_STATE_FORWARDING:
714 default:
715 stp_state = MT7530_STP_FORWARDING;
716 break;
717 }
718
719 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
720}
721
722static int
723mt7530_port_bridge_join(struct dsa_switch *ds, int port,
724 struct net_device *bridge)
725{
726 struct mt7530_priv *priv = ds->priv;
727 u32 port_bitmap = BIT(MT7530_CPU_PORT);
728 int i;
729
730 mutex_lock(&priv->reg_mutex);
731
732 for (i = 0; i < MT7530_NUM_PORTS; i++) {
733 /* Add this port to the port matrix of the other ports in the
734 * same bridge. If the port is disabled, port matrix is kept
735 * and not being setup until the port becomes enabled.
736 */
737 if (dsa_is_user_port(ds, i) && i != port) {
738 if (dsa_to_port(ds, i)->bridge_dev != bridge)
739 continue;
740 if (priv->ports[i].enable)
741 mt7530_set(priv, MT7530_PCR_P(i),
742 PCR_MATRIX(BIT(port)));
743 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
744
745 port_bitmap |= BIT(i);
746 }
747 }
748
749 /* Add the all other ports to this port matrix. */
750 if (priv->ports[port].enable)
751 mt7530_rmw(priv, MT7530_PCR_P(port),
752 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
753 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
754
755 mutex_unlock(&priv->reg_mutex);
756
757 return 0;
758}
759
760static void
761mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
762{
763 struct mt7530_priv *priv = ds->priv;
764 bool all_user_ports_removed = true;
765 int i;
766
767 /* When a port is removed from the bridge, the port would be set up
768 * back to the default as is at initial boot which is a VLAN-unaware
769 * port.
770 */
771 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
772 MT7530_PORT_MATRIX_MODE);
773 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
774 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
775 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
776
777 for (i = 0; i < MT7530_NUM_PORTS; i++) {
778 if (dsa_is_user_port(ds, i) &&
779 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
780 all_user_ports_removed = false;
781 break;
782 }
783 }
784
785 /* CPU port also does the same thing until all user ports belonging to
786 * the CPU port get out of VLAN filtering mode.
787 */
788 if (all_user_ports_removed) {
789 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
790 PCR_MATRIX(dsa_user_ports(priv->ds)));
791 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
792 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
793 }
794}
795
796static void
797mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
798{
799 struct mt7530_priv *priv = ds->priv;
800
801 /* The real fabric path would be decided on the membership in the
802 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
803 * means potential VLAN can be consisting of certain subset of all
804 * ports.
805 */
806 mt7530_rmw(priv, MT7530_PCR_P(port),
807 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
808
809 /* Trapped into security mode allows packet forwarding through VLAN
810 * table lookup. CPU port is set to fallback mode to let untagged
811 * frames pass through.
812 */
813 if (dsa_is_cpu_port(ds, port))
814 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
815 MT7530_PORT_FALLBACK_MODE);
816 else
817 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
818 MT7530_PORT_SECURITY_MODE);
819
820 /* Set the port as a user port which is to be able to recognize VID
821 * from incoming packets before fetching entry within the VLAN table.
822 */
823 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
824 VLAN_ATTR(MT7530_VLAN_USER) |
825 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
826}
827
828static void
829mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
830 struct net_device *bridge)
831{
832 struct mt7530_priv *priv = ds->priv;
833 int i;
834
835 mutex_lock(&priv->reg_mutex);
836
837 for (i = 0; i < MT7530_NUM_PORTS; i++) {
838 /* Remove this port from the port matrix of the other ports
839 * in the same bridge. If the port is disabled, port matrix
840 * is kept and not being setup until the port becomes enabled.
841 * And the other port's port matrix cannot be broken when the
842 * other port is still a VLAN-aware port.
843 */
844 if (dsa_is_user_port(ds, i) && i != port &&
845 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
846 if (dsa_to_port(ds, i)->bridge_dev != bridge)
847 continue;
848 if (priv->ports[i].enable)
849 mt7530_clear(priv, MT7530_PCR_P(i),
850 PCR_MATRIX(BIT(port)));
851 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
852 }
853 }
854
855 /* Set the cpu port to be the only one in the port matrix of
856 * this port.
857 */
858 if (priv->ports[port].enable)
859 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
860 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
861 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
862
863 mutex_unlock(&priv->reg_mutex);
864}
865
866static int
867mt7530_port_fdb_add(struct dsa_switch *ds, int port,
868 const unsigned char *addr, u16 vid)
869{
870 struct mt7530_priv *priv = ds->priv;
871 int ret;
872 u8 port_mask = BIT(port);
873
874 mutex_lock(&priv->reg_mutex);
875 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
876 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
877 mutex_unlock(&priv->reg_mutex);
878
879 return ret;
880}
881
882static int
883mt7530_port_fdb_del(struct dsa_switch *ds, int port,
884 const unsigned char *addr, u16 vid)
885{
886 struct mt7530_priv *priv = ds->priv;
887 int ret;
888 u8 port_mask = BIT(port);
889
890 mutex_lock(&priv->reg_mutex);
891 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
892 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
893 mutex_unlock(&priv->reg_mutex);
894
895 return ret;
896}
897
898static int
899mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
900 dsa_fdb_dump_cb_t *cb, void *data)
901{
902 struct mt7530_priv *priv = ds->priv;
903 struct mt7530_fdb _fdb = { 0 };
904 int cnt = MT7530_NUM_FDB_RECORDS;
905 int ret = 0;
906 u32 rsp = 0;
907
908 mutex_lock(&priv->reg_mutex);
909
910 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
911 if (ret < 0)
912 goto err;
913
914 do {
915 if (rsp & ATC_SRCH_HIT) {
916 mt7530_fdb_read(priv, &_fdb);
917 if (_fdb.port_mask & BIT(port)) {
918 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
919 data);
920 if (ret < 0)
921 break;
922 }
923 }
924 } while (--cnt &&
925 !(rsp & ATC_SRCH_END) &&
926 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
927err:
928 mutex_unlock(&priv->reg_mutex);
929
930 return 0;
931}
932
933static int
934mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
935{
936 struct mt7530_dummy_poll p;
937 u32 val;
938 int ret;
939
940 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
941 mt7530_write(priv, MT7530_VTCR, val);
942
943 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
944 ret = readx_poll_timeout(_mt7530_read, &p, val,
945 !(val & VTCR_BUSY), 20, 20000);
946 if (ret < 0) {
947 dev_err(priv->dev, "poll timeout\n");
948 return ret;
949 }
950
951 val = mt7530_read(priv, MT7530_VTCR);
952 if (val & VTCR_INVALID) {
953 dev_err(priv->dev, "read VTCR invalid\n");
954 return -EINVAL;
955 }
956
957 return 0;
958}
959
960static int
961mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
962 bool vlan_filtering)
963{
964 if (vlan_filtering) {
965 /* The port is being kept as VLAN-unaware port when bridge is
966 * set up with vlan_filtering not being set, Otherwise, the
967 * port and the corresponding CPU port is required the setup
968 * for becoming a VLAN-aware port.
969 */
970 mt7530_port_set_vlan_aware(ds, port);
971 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
972 } else {
973 mt7530_port_set_vlan_unaware(ds, port);
974 }
975
976 return 0;
977}
978
979static int
980mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
981 const struct switchdev_obj_port_vlan *vlan)
982{
983 /* nothing needed */
984
985 return 0;
986}
987
988static void
989mt7530_hw_vlan_add(struct mt7530_priv *priv,
990 struct mt7530_hw_vlan_entry *entry)
991{
992 u8 new_members;
993 u32 val;
994
995 new_members = entry->old_members | BIT(entry->port) |
996 BIT(MT7530_CPU_PORT);
997
998 /* Validate the entry with independent learning, create egress tag per
999 * VLAN and joining the port as one of the port members.
1000 */
1001 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1002 mt7530_write(priv, MT7530_VAWD1, val);
1003
1004 /* Decide whether adding tag or not for those outgoing packets from the
1005 * port inside the VLAN.
1006 */
1007 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1008 MT7530_VLAN_EGRESS_TAG;
1009 mt7530_rmw(priv, MT7530_VAWD2,
1010 ETAG_CTRL_P_MASK(entry->port),
1011 ETAG_CTRL_P(entry->port, val));
1012
1013 /* CPU port is always taken as a tagged port for serving more than one
1014 * VLANs across and also being applied with egress type stack mode for
1015 * that VLAN tags would be appended after hardware special tag used as
1016 * DSA tag.
1017 */
1018 mt7530_rmw(priv, MT7530_VAWD2,
1019 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1020 ETAG_CTRL_P(MT7530_CPU_PORT,
1021 MT7530_VLAN_EGRESS_STACK));
1022}
1023
1024static void
1025mt7530_hw_vlan_del(struct mt7530_priv *priv,
1026 struct mt7530_hw_vlan_entry *entry)
1027{
1028 u8 new_members;
1029 u32 val;
1030
1031 new_members = entry->old_members & ~BIT(entry->port);
1032
1033 val = mt7530_read(priv, MT7530_VAWD1);
1034 if (!(val & VLAN_VALID)) {
1035 dev_err(priv->dev,
1036 "Cannot be deleted due to invalid entry\n");
1037 return;
1038 }
1039
1040 /* If certain member apart from CPU port is still alive in the VLAN,
1041 * the entry would be kept valid. Otherwise, the entry is got to be
1042 * disabled.
1043 */
1044 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1045 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1046 VLAN_VALID;
1047 mt7530_write(priv, MT7530_VAWD1, val);
1048 } else {
1049 mt7530_write(priv, MT7530_VAWD1, 0);
1050 mt7530_write(priv, MT7530_VAWD2, 0);
1051 }
1052}
1053
1054static void
1055mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1056 struct mt7530_hw_vlan_entry *entry,
1057 mt7530_vlan_op vlan_op)
1058{
1059 u32 val;
1060
1061 /* Fetch entry */
1062 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1063
1064 val = mt7530_read(priv, MT7530_VAWD1);
1065
1066 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1067
1068 /* Manipulate entry */
1069 vlan_op(priv, entry);
1070
1071 /* Flush result to hardware */
1072 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1073}
1074
1075static void
1076mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1077 const struct switchdev_obj_port_vlan *vlan)
1078{
1079 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1080 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1081 struct mt7530_hw_vlan_entry new_entry;
1082 struct mt7530_priv *priv = ds->priv;
1083 u16 vid;
1084
1085 mutex_lock(&priv->reg_mutex);
1086
1087 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1088 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1089 mt7530_hw_vlan_update(priv, vid, &new_entry,
1090 mt7530_hw_vlan_add);
1091 }
1092
1093 if (pvid) {
1094 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1095 G0_PORT_VID(vlan->vid_end));
1096 priv->ports[port].pvid = vlan->vid_end;
1097 }
1098
1099 mutex_unlock(&priv->reg_mutex);
1100}
1101
1102static int
1103mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1104 const struct switchdev_obj_port_vlan *vlan)
1105{
1106 struct mt7530_hw_vlan_entry target_entry;
1107 struct mt7530_priv *priv = ds->priv;
1108 u16 vid, pvid;
1109
1110 mutex_lock(&priv->reg_mutex);
1111
1112 pvid = priv->ports[port].pvid;
1113 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1114 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1115 mt7530_hw_vlan_update(priv, vid, &target_entry,
1116 mt7530_hw_vlan_del);
1117
1118 /* PVID is being restored to the default whenever the PVID port
1119 * is being removed from the VLAN.
1120 */
1121 if (pvid == vid)
1122 pvid = G0_PORT_VID_DEF;
1123 }
1124
1125 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1126 priv->ports[port].pvid = pvid;
1127
1128 mutex_unlock(&priv->reg_mutex);
1129
1130 return 0;
1131}
1132
1133static int mt7530_port_mirror_add(struct dsa_switch *ds, int port,
1134 struct dsa_mall_mirror_tc_entry *mirror,
1135 bool ingress)
1136{
1137 struct mt7530_priv *priv = ds->priv;
1138 u32 val;
1139
1140 /* Check for existent entry */
1141 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1142 return -EEXIST;
1143
1144 val = mt7530_read(priv, MT7530_MFC);
1145
1146 /* MT7530 only supports one monitor port */
1147 if (val & MIRROR_EN && MIRROR_PORT(val) != mirror->to_local_port)
1148 return -EEXIST;
1149
1150 val |= MIRROR_EN;
1151 val &= ~MIRROR_MASK;
1152 val |= mirror->to_local_port;
1153 mt7530_write(priv, MT7530_MFC, val);
1154
1155 val = mt7530_read(priv, MT7530_PCR_P(port));
1156 if (ingress) {
1157 val |= PORT_RX_MIR;
1158 priv->mirror_rx |= BIT(port);
1159 } else {
1160 val |= PORT_TX_MIR;
1161 priv->mirror_tx |= BIT(port);
1162 }
1163 mt7530_write(priv, MT7530_PCR_P(port), val);
1164
1165 return 0;
1166}
1167
1168static void mt7530_port_mirror_del(struct dsa_switch *ds, int port,
1169 struct dsa_mall_mirror_tc_entry *mirror)
1170{
1171 struct mt7530_priv *priv = ds->priv;
1172 u32 val;
1173
1174 val = mt7530_read(priv, MT7530_PCR_P(port));
1175 if (mirror->ingress) {
1176 val &= ~PORT_RX_MIR;
1177 priv->mirror_rx &= ~BIT(port);
1178 } else {
1179 val &= ~PORT_TX_MIR;
1180 priv->mirror_tx &= ~BIT(port);
1181 }
1182 mt7530_write(priv, MT7530_PCR_P(port), val);
1183
1184 if (!priv->mirror_rx && !priv->mirror_tx) {
1185 val = mt7530_read(priv, MT7530_MFC);
1186 val &= ~MIRROR_EN;
1187 mt7530_write(priv, MT7530_MFC, val);
1188 }
1189}
1190
1191static enum dsa_tag_protocol
1192mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1193 enum dsa_tag_protocol mp)
1194{
1195 struct mt7530_priv *priv = ds->priv;
1196
1197 if (port != MT7530_CPU_PORT) {
1198 dev_warn(priv->dev,
1199 "port not matched with tagging CPU port\n");
1200 return DSA_TAG_PROTO_NONE;
1201 } else {
1202 return DSA_TAG_PROTO_MTK;
1203 }
1204}
1205
1206static int
1207mt7530_setup(struct dsa_switch *ds)
1208{
1209 struct mt7530_priv *priv = ds->priv;
1210 struct device_node *phy_node;
1211 struct device_node *mac_np;
1212 struct mt7530_dummy_poll p;
1213 phy_interface_t interface;
1214 struct device_node *dn;
1215 u32 id, val;
1216 int ret, i;
1217
1218 /* The parent node of master netdev which holds the common system
1219 * controller also is the container for two GMACs nodes representing
1220 * as two netdev instances.
1221 */
1222 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
1223 ds->configure_vlan_while_not_filtering = true;
1224
1225 if (priv->id == ID_MT7530) {
1226 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1227 ret = regulator_enable(priv->core_pwr);
1228 if (ret < 0) {
1229 dev_err(priv->dev,
1230 "Failed to enable core power: %d\n", ret);
1231 return ret;
1232 }
1233
1234 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1235 ret = regulator_enable(priv->io_pwr);
1236 if (ret < 0) {
1237 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1238 ret);
1239 return ret;
1240 }
1241 }
1242
1243 /* Reset whole chip through gpio pin or memory-mapped registers for
1244 * different type of hardware
1245 */
1246 if (priv->mcm) {
1247 reset_control_assert(priv->rstc);
1248 usleep_range(1000, 1100);
1249 reset_control_deassert(priv->rstc);
1250 } else {
1251 gpiod_set_value_cansleep(priv->reset, 0);
1252 usleep_range(1000, 1100);
1253 gpiod_set_value_cansleep(priv->reset, 1);
1254 }
1255
1256 /* Waiting for MT7530 got to stable */
1257 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1258 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1259 20, 1000000);
1260 if (ret < 0) {
1261 dev_err(priv->dev, "reset timeout\n");
1262 return ret;
1263 }
1264
1265 id = mt7530_read(priv, MT7530_CREV);
1266 id >>= CHIP_NAME_SHIFT;
1267 if (id != MT7530_ID) {
1268 dev_err(priv->dev, "chip %x can't be supported\n", id);
1269 return -ENODEV;
1270 }
1271
1272 /* Reset the switch through internal reset */
1273 mt7530_write(priv, MT7530_SYS_CTRL,
1274 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1275 SYS_CTRL_REG_RST);
1276
1277 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1278 val = mt7530_read(priv, MT7530_MHWTRAP);
1279 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1280 val |= MHWTRAP_MANUAL;
1281 mt7530_write(priv, MT7530_MHWTRAP, val);
1282
1283 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1284
1285 /* Enable and reset MIB counters */
1286 mt7530_mib_reset(ds);
1287
1288 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1289 /* Disable forwarding by default on all ports */
1290 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1291 PCR_MATRIX_CLR);
1292
1293 if (dsa_is_cpu_port(ds, i))
1294 mt7530_cpu_port_enable(priv, i);
1295 else
1296 mt7530_port_disable(ds, i);
1297
1298 /* Enable consistent egress tag */
1299 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1300 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1301 }
1302
1303 /* Setup port 5 */
1304 priv->p5_intf_sel = P5_DISABLED;
1305 interface = PHY_INTERFACE_MODE_NA;
1306
1307 if (!dsa_is_unused_port(ds, 5)) {
1308 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1309 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
1310 if (ret && ret != -ENODEV)
1311 return ret;
1312 } else {
1313 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1314 for_each_child_of_node(dn, mac_np) {
1315 if (!of_device_is_compatible(mac_np,
1316 "mediatek,eth-mac"))
1317 continue;
1318
1319 ret = of_property_read_u32(mac_np, "reg", &id);
1320 if (ret < 0 || id != 1)
1321 continue;
1322
1323 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
1324 if (!phy_node)
1325 continue;
1326
1327 if (phy_node->parent == priv->dev->of_node->parent) {
1328 ret = of_get_phy_mode(mac_np, &interface);
1329 if (ret && ret != -ENODEV) {
1330 of_node_put(mac_np);
1331 return ret;
1332 }
1333 id = of_mdio_parse_addr(ds->dev, phy_node);
1334 if (id == 0)
1335 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1336 if (id == 4)
1337 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1338 }
1339 of_node_put(mac_np);
1340 of_node_put(phy_node);
1341 break;
1342 }
1343 }
1344
1345 mt7530_setup_port5(ds, interface);
1346
1347 /* Flush the FDB table */
1348 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1349 if (ret < 0)
1350 return ret;
1351
1352 return 0;
1353}
1354
1355static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
1356 unsigned int mode,
1357 const struct phylink_link_state *state)
1358{
1359 struct mt7530_priv *priv = ds->priv;
1360 u32 mcr_cur, mcr_new;
1361
1362 switch (port) {
1363 case 0: /* Internal phy */
1364 case 1:
1365 case 2:
1366 case 3:
1367 case 4:
1368 if (state->interface != PHY_INTERFACE_MODE_GMII)
1369 return;
1370 break;
1371 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1372 if (priv->p5_interface == state->interface)
1373 break;
1374 if (!phy_interface_mode_is_rgmii(state->interface) &&
1375 state->interface != PHY_INTERFACE_MODE_MII &&
1376 state->interface != PHY_INTERFACE_MODE_GMII)
1377 return;
1378
1379 mt7530_setup_port5(ds, state->interface);
1380 break;
1381 case 6: /* 1st cpu port */
1382 if (priv->p6_interface == state->interface)
1383 break;
1384
1385 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1386 state->interface != PHY_INTERFACE_MODE_TRGMII)
1387 return;
1388
1389 /* Setup TX circuit incluing relevant PAD and driving */
1390 mt7530_pad_clk_setup(ds, state->interface);
1391
1392 priv->p6_interface = state->interface;
1393 break;
1394 default:
1395 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1396 return;
1397 }
1398
1399 if (phylink_autoneg_inband(mode)) {
1400 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1401 __func__);
1402 return;
1403 }
1404
1405 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
1406 mcr_new = mcr_cur;
1407 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
1408 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
1409 PMCR_BACKPR_EN | PMCR_FORCE_MODE;
1410
1411 /* Are we connected to external phy */
1412 if (port == 5 && dsa_is_user_port(ds, 5))
1413 mcr_new |= PMCR_EXT_PHY;
1414
1415 if (mcr_new != mcr_cur)
1416 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
1417}
1418
1419static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port,
1420 unsigned int mode,
1421 phy_interface_t interface)
1422{
1423 struct mt7530_priv *priv = ds->priv;
1424
1425 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1426}
1427
1428static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port,
1429 unsigned int mode,
1430 phy_interface_t interface,
1431 struct phy_device *phydev,
1432 int speed, int duplex,
1433 bool tx_pause, bool rx_pause)
1434{
1435 struct mt7530_priv *priv = ds->priv;
1436 u32 mcr;
1437
1438 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
1439
1440 switch (speed) {
1441 case SPEED_1000:
1442 mcr |= PMCR_FORCE_SPEED_1000;
1443 break;
1444 case SPEED_100:
1445 mcr |= PMCR_FORCE_SPEED_100;
1446 break;
1447 }
1448 if (duplex == DUPLEX_FULL) {
1449 mcr |= PMCR_FORCE_FDX;
1450 if (tx_pause)
1451 mcr |= PMCR_TX_FC_EN;
1452 if (rx_pause)
1453 mcr |= PMCR_RX_FC_EN;
1454 }
1455
1456 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
1457}
1458
1459static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
1460 unsigned long *supported,
1461 struct phylink_link_state *state)
1462{
1463 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1464
1465 switch (port) {
1466 case 0: /* Internal phy */
1467 case 1:
1468 case 2:
1469 case 3:
1470 case 4:
1471 if (state->interface != PHY_INTERFACE_MODE_NA &&
1472 state->interface != PHY_INTERFACE_MODE_GMII)
1473 goto unsupported;
1474 break;
1475 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
1476 if (state->interface != PHY_INTERFACE_MODE_NA &&
1477 !phy_interface_mode_is_rgmii(state->interface) &&
1478 state->interface != PHY_INTERFACE_MODE_MII &&
1479 state->interface != PHY_INTERFACE_MODE_GMII)
1480 goto unsupported;
1481 break;
1482 case 6: /* 1st cpu port */
1483 if (state->interface != PHY_INTERFACE_MODE_NA &&
1484 state->interface != PHY_INTERFACE_MODE_RGMII &&
1485 state->interface != PHY_INTERFACE_MODE_TRGMII)
1486 goto unsupported;
1487 break;
1488 default:
1489 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1490unsupported:
1491 linkmode_zero(supported);
1492 return;
1493 }
1494
1495 phylink_set_port_modes(mask);
1496 phylink_set(mask, Autoneg);
1497
1498 if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
1499 phylink_set(mask, 1000baseT_Full);
1500 } else {
1501 phylink_set(mask, 10baseT_Half);
1502 phylink_set(mask, 10baseT_Full);
1503 phylink_set(mask, 100baseT_Half);
1504 phylink_set(mask, 100baseT_Full);
1505
1506 if (state->interface != PHY_INTERFACE_MODE_MII) {
1507 /* This switch only supports 1G full-duplex. */
1508 phylink_set(mask, 1000baseT_Full);
1509 if (port == 5)
1510 phylink_set(mask, 1000baseX_Full);
1511 }
1512 }
1513
1514 phylink_set(mask, Pause);
1515 phylink_set(mask, Asym_Pause);
1516
1517 linkmode_and(supported, supported, mask);
1518 linkmode_and(state->advertising, state->advertising, mask);
1519}
1520
1521static int
1522mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
1523 struct phylink_link_state *state)
1524{
1525 struct mt7530_priv *priv = ds->priv;
1526 u32 pmsr;
1527
1528 if (port < 0 || port >= MT7530_NUM_PORTS)
1529 return -EINVAL;
1530
1531 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
1532
1533 state->link = (pmsr & PMSR_LINK);
1534 state->an_complete = state->link;
1535 state->duplex = !!(pmsr & PMSR_DPX);
1536
1537 switch (pmsr & PMSR_SPEED_MASK) {
1538 case PMSR_SPEED_10:
1539 state->speed = SPEED_10;
1540 break;
1541 case PMSR_SPEED_100:
1542 state->speed = SPEED_100;
1543 break;
1544 case PMSR_SPEED_1000:
1545 state->speed = SPEED_1000;
1546 break;
1547 default:
1548 state->speed = SPEED_UNKNOWN;
1549 break;
1550 }
1551
1552 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
1553 if (pmsr & PMSR_RX_FC)
1554 state->pause |= MLO_PAUSE_RX;
1555 if (pmsr & PMSR_TX_FC)
1556 state->pause |= MLO_PAUSE_TX;
1557
1558 return 1;
1559}
1560
1561static const struct dsa_switch_ops mt7530_switch_ops = {
1562 .get_tag_protocol = mtk_get_tag_protocol,
1563 .setup = mt7530_setup,
1564 .get_strings = mt7530_get_strings,
1565 .phy_read = mt7530_phy_read,
1566 .phy_write = mt7530_phy_write,
1567 .get_ethtool_stats = mt7530_get_ethtool_stats,
1568 .get_sset_count = mt7530_get_sset_count,
1569 .port_enable = mt7530_port_enable,
1570 .port_disable = mt7530_port_disable,
1571 .port_stp_state_set = mt7530_stp_state_set,
1572 .port_bridge_join = mt7530_port_bridge_join,
1573 .port_bridge_leave = mt7530_port_bridge_leave,
1574 .port_fdb_add = mt7530_port_fdb_add,
1575 .port_fdb_del = mt7530_port_fdb_del,
1576 .port_fdb_dump = mt7530_port_fdb_dump,
1577 .port_vlan_filtering = mt7530_port_vlan_filtering,
1578 .port_vlan_prepare = mt7530_port_vlan_prepare,
1579 .port_vlan_add = mt7530_port_vlan_add,
1580 .port_vlan_del = mt7530_port_vlan_del,
1581 .port_mirror_add = mt7530_port_mirror_add,
1582 .port_mirror_del = mt7530_port_mirror_del,
1583 .phylink_validate = mt7530_phylink_validate,
1584 .phylink_mac_link_state = mt7530_phylink_mac_link_state,
1585 .phylink_mac_config = mt7530_phylink_mac_config,
1586 .phylink_mac_link_down = mt7530_phylink_mac_link_down,
1587 .phylink_mac_link_up = mt7530_phylink_mac_link_up,
1588};
1589
1590static const struct of_device_id mt7530_of_match[] = {
1591 { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, },
1592 { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, },
1593 { /* sentinel */ },
1594};
1595MODULE_DEVICE_TABLE(of, mt7530_of_match);
1596
1597static int
1598mt7530_probe(struct mdio_device *mdiodev)
1599{
1600 struct mt7530_priv *priv;
1601 struct device_node *dn;
1602
1603 dn = mdiodev->dev.of_node;
1604
1605 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1606 if (!priv)
1607 return -ENOMEM;
1608
1609 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
1610 if (!priv->ds)
1611 return -ENOMEM;
1612
1613 priv->ds->dev = &mdiodev->dev;
1614 priv->ds->num_ports = DSA_MAX_PORTS;
1615
1616 /* Use medatek,mcm property to distinguish hardware type that would
1617 * casues a little bit differences on power-on sequence.
1618 */
1619 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1620 if (priv->mcm) {
1621 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1622
1623 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1624 if (IS_ERR(priv->rstc)) {
1625 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1626 return PTR_ERR(priv->rstc);
1627 }
1628 }
1629
1630 /* Get the hardware identifier from the devicetree node.
1631 * We will need it for some of the clock and regulator setup.
1632 */
1633 priv->id = (unsigned int)(unsigned long)
1634 of_device_get_match_data(&mdiodev->dev);
1635
1636 if (priv->id == ID_MT7530) {
1637 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1638 if (IS_ERR(priv->core_pwr))
1639 return PTR_ERR(priv->core_pwr);
1640
1641 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1642 if (IS_ERR(priv->io_pwr))
1643 return PTR_ERR(priv->io_pwr);
1644 }
1645
1646 /* Not MCM that indicates switch works as the remote standalone
1647 * integrated circuit so the GPIO pin would be used to complete
1648 * the reset, otherwise memory-mapped register accessing used
1649 * through syscon provides in the case of MCM.
1650 */
1651 if (!priv->mcm) {
1652 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1653 GPIOD_OUT_LOW);
1654 if (IS_ERR(priv->reset)) {
1655 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1656 return PTR_ERR(priv->reset);
1657 }
1658 }
1659
1660 priv->bus = mdiodev->bus;
1661 priv->dev = &mdiodev->dev;
1662 priv->ds->priv = priv;
1663 priv->ds->ops = &mt7530_switch_ops;
1664 mutex_init(&priv->reg_mutex);
1665 dev_set_drvdata(&mdiodev->dev, priv);
1666
1667 return dsa_register_switch(priv->ds);
1668}
1669
1670static void
1671mt7530_remove(struct mdio_device *mdiodev)
1672{
1673 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1674 int ret = 0;
1675
1676 ret = regulator_disable(priv->core_pwr);
1677 if (ret < 0)
1678 dev_err(priv->dev,
1679 "Failed to disable core power: %d\n", ret);
1680
1681 ret = regulator_disable(priv->io_pwr);
1682 if (ret < 0)
1683 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1684 ret);
1685
1686 dsa_unregister_switch(priv->ds);
1687 mutex_destroy(&priv->reg_mutex);
1688}
1689
1690static struct mdio_driver mt7530_mdio_driver = {
1691 .probe = mt7530_probe,
1692 .remove = mt7530_remove,
1693 .mdiodrv.driver = {
1694 .name = "mt7530",
1695 .of_match_table = mt7530_of_match,
1696 },
1697};
1698
1699mdio_module_driver(mt7530_mdio_driver);
1700
1701MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1702MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1703MODULE_LICENSE("GPL");