1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Mediatek MT7530 DSA Switch driver
   4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
   5 */
   6#include <linux/etherdevice.h>
   7#include <linux/if_bridge.h>
   8#include <linux/iopoll.h>
   9#include <linux/mdio.h>
  10#include <linux/mfd/syscon.h>
  11#include <linux/module.h>
  12#include <linux/netdevice.h>
  13#include <linux/of_irq.h>
  14#include <linux/of_mdio.h>
  15#include <linux/of_net.h>
  16#include <linux/of_platform.h>
  17#include <linux/phylink.h>
  18#include <linux/regmap.h>
  19#include <linux/regulator/consumer.h>
  20#include <linux/reset.h>
  21#include <linux/gpio/consumer.h>
  22#include <linux/gpio/driver.h>
  23#include <net/dsa.h>
  24
  25#include "mt7530.h"
  26
  27/* String, offset, and register size in bytes if different from 4 bytes */
  28static const struct mt7530_mib_desc mt7530_mib[] = {
  29	MIB_DESC(1, 0x00, "TxDrop"),
  30	MIB_DESC(1, 0x04, "TxCrcErr"),
  31	MIB_DESC(1, 0x08, "TxUnicast"),
  32	MIB_DESC(1, 0x0c, "TxMulticast"),
  33	MIB_DESC(1, 0x10, "TxBroadcast"),
  34	MIB_DESC(1, 0x14, "TxCollision"),
  35	MIB_DESC(1, 0x18, "TxSingleCollision"),
  36	MIB_DESC(1, 0x1c, "TxMultipleCollision"),
  37	MIB_DESC(1, 0x20, "TxDeferred"),
  38	MIB_DESC(1, 0x24, "TxLateCollision"),
  39	MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
  40	MIB_DESC(1, 0x2c, "TxPause"),
  41	MIB_DESC(1, 0x30, "TxPktSz64"),
  42	MIB_DESC(1, 0x34, "TxPktSz65To127"),
  43	MIB_DESC(1, 0x38, "TxPktSz128To255"),
  44	MIB_DESC(1, 0x3c, "TxPktSz256To511"),
  45	MIB_DESC(1, 0x40, "TxPktSz512To1023"),
  46	MIB_DESC(1, 0x44, "Tx1024ToMax"),
  47	MIB_DESC(2, 0x48, "TxBytes"),
  48	MIB_DESC(1, 0x60, "RxDrop"),
  49	MIB_DESC(1, 0x64, "RxFiltering"),
  50	MIB_DESC(1, 0x68, "RxUnicast"),
  51	MIB_DESC(1, 0x6c, "RxMulticast"),
  52	MIB_DESC(1, 0x70, "RxBroadcast"),
  53	MIB_DESC(1, 0x74, "RxAlignErr"),
  54	MIB_DESC(1, 0x78, "RxCrcErr"),
  55	MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
  56	MIB_DESC(1, 0x80, "RxFragErr"),
  57	MIB_DESC(1, 0x84, "RxOverSzErr"),
  58	MIB_DESC(1, 0x88, "RxJabberErr"),
  59	MIB_DESC(1, 0x8c, "RxPause"),
  60	MIB_DESC(1, 0x90, "RxPktSz64"),
  61	MIB_DESC(1, 0x94, "RxPktSz65To127"),
  62	MIB_DESC(1, 0x98, "RxPktSz128To255"),
  63	MIB_DESC(1, 0x9c, "RxPktSz256To511"),
  64	MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
  65	MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
  66	MIB_DESC(2, 0xa8, "RxBytes"),
  67	MIB_DESC(1, 0xb0, "RxCtrlDrop"),
  68	MIB_DESC(1, 0xb4, "RxIngressDrop"),
  69	MIB_DESC(1, 0xb8, "RxArlDrop"),
  70};
  71
  72/* Since phy_device has not yet been created and
  73 * phy_{read,write}_mmd_indirect is not available, we provide our own
  74 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
  75 * to complete this function.
  76 */
  77static int
  78core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
  79{
  80	struct mii_bus *bus = priv->bus;
  81	int value, ret;
  82
  83	/* Write the desired MMD Devad */
  84	ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
  85	if (ret < 0)
  86		goto err;
  87
  88	/* Write the desired MMD register address */
  89	ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
  90	if (ret < 0)
  91		goto err;
  92
  93	/* Select the Function : DATA with no post increment */
  94	ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
  95	if (ret < 0)
  96		goto err;
  97
  98	/* Read the content of the MMD's selected register */
  99	value = bus->read(bus, 0, MII_MMD_DATA);
 100
 101	return value;
 102err:
 103	dev_err(&bus->dev,  "failed to read mmd register\n");
 104
 105	return ret;
 106}
 107
 108static int
 109core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
 110			int devad, u32 data)
 111{
 112	struct mii_bus *bus = priv->bus;
 113	int ret;
 114
 115	/* Write the desired MMD Devad */
 116	ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
 117	if (ret < 0)
 118		goto err;
 119
 120	/* Write the desired MMD register address */
 121	ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
 122	if (ret < 0)
 123		goto err;
 124
 125	/* Select the Function : DATA with no post increment */
 126	ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
 127	if (ret < 0)
 128		goto err;
 129
 130	/* Write the data into MMD's selected register */
 131	ret = bus->write(bus, 0, MII_MMD_DATA, data);
 132err:
 133	if (ret < 0)
 134		dev_err(&bus->dev,
 135			"failed to write mmd register\n");
 136	return ret;
 137}
 138
 139static void
 140core_write(struct mt7530_priv *priv, u32 reg, u32 val)
 141{
 142	struct mii_bus *bus = priv->bus;
 143
 144	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 145
 146	core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
 147
 148	mutex_unlock(&bus->mdio_lock);
 149}
 150
 151static void
 152core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
 153{
 154	struct mii_bus *bus = priv->bus;
 155	u32 val;
 156
 157	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 158
 159	val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
 160	val &= ~mask;
 161	val |= set;
 162	core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
 163
 164	mutex_unlock(&bus->mdio_lock);
 165}
 166
 167static void
 168core_set(struct mt7530_priv *priv, u32 reg, u32 val)
 169{
 170	core_rmw(priv, reg, 0, val);
 171}
 172
 173static void
 174core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
 175{
 176	core_rmw(priv, reg, val, 0);
 177}
 178
 179static int
 180mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
 181{
 182	struct mii_bus *bus = priv->bus;
 183	u16 page, r, lo, hi;
 184	int ret;
 185
 186	page = (reg >> 6) & 0x3ff;
 187	r  = (reg >> 2) & 0xf;
 188	lo = val & 0xffff;
 189	hi = val >> 16;
 190
 191	/* MT7530 uses 31 as the pseudo port */
 192	ret = bus->write(bus, 0x1f, 0x1f, page);
 193	if (ret < 0)
 194		goto err;
 195
 196	ret = bus->write(bus, 0x1f, r,  lo);
 197	if (ret < 0)
 198		goto err;
 199
 200	ret = bus->write(bus, 0x1f, 0x10, hi);
 201err:
 202	if (ret < 0)
 203		dev_err(&bus->dev,
 204			"failed to write mt7530 register\n");
 205	return ret;
 206}
 207
 208static u32
 209mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
 210{
 211	struct mii_bus *bus = priv->bus;
 212	u16 page, r, lo, hi;
 213	int ret;
 214
 215	page = (reg >> 6) & 0x3ff;
 216	r = (reg >> 2) & 0xf;
 217
 218	/* MT7530 uses 31 as the pseudo port */
 219	ret = bus->write(bus, 0x1f, 0x1f, page);
 220	if (ret < 0) {
 221		dev_err(&bus->dev,
 222			"failed to read mt7530 register\n");
 223		return ret;
 224	}
 225
 226	lo = bus->read(bus, 0x1f, r);
 227	hi = bus->read(bus, 0x1f, 0x10);
 228
 229	return (hi << 16) | (lo & 0xffff);
 230}
 231
 232static void
 233mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
 234{
 235	struct mii_bus *bus = priv->bus;
 236
 237	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 238
 239	mt7530_mii_write(priv, reg, val);
 240
 241	mutex_unlock(&bus->mdio_lock);
 242}
 243
 244static u32
 245_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
 246{
 247	return mt7530_mii_read(p->priv, p->reg);
 248}
 249
 250static u32
 251_mt7530_read(struct mt7530_dummy_poll *p)
 252{
 253	struct mii_bus		*bus = p->priv->bus;
 254	u32 val;
 255
 256	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 257
 258	val = mt7530_mii_read(p->priv, p->reg);
 259
 260	mutex_unlock(&bus->mdio_lock);
 261
 262	return val;
 263}
 264
 265static u32
 266mt7530_read(struct mt7530_priv *priv, u32 reg)
 267{
 268	struct mt7530_dummy_poll p;
 269
 270	INIT_MT7530_DUMMY_POLL(&p, priv, reg);
 271	return _mt7530_read(&p);
 272}
 273
 274static void
 275mt7530_rmw(struct mt7530_priv *priv, u32 reg,
 276	   u32 mask, u32 set)
 277{
 278	struct mii_bus *bus = priv->bus;
 279	u32 val;
 280
 281	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 282
 283	val = mt7530_mii_read(priv, reg);
 284	val &= ~mask;
 285	val |= set;
 286	mt7530_mii_write(priv, reg, val);
 287
 288	mutex_unlock(&bus->mdio_lock);
 289}
 290
 291static void
 292mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
 293{
 294	mt7530_rmw(priv, reg, 0, val);
 295}
 296
 297static void
 298mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
 299{
 300	mt7530_rmw(priv, reg, val, 0);
 301}
 302
 303static int
 304mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
 305{
 306	u32 val;
 307	int ret;
 308	struct mt7530_dummy_poll p;
 309
 310	/* Set the command operating upon the MAC address entries */
 311	val = ATC_BUSY | ATC_MAT(0) | cmd;
 312	mt7530_write(priv, MT7530_ATC, val);
 313
 314	INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
 315	ret = readx_poll_timeout(_mt7530_read, &p, val,
 316				 !(val & ATC_BUSY), 20, 20000);
 317	if (ret < 0) {
 318		dev_err(priv->dev, "reset timeout\n");
 319		return ret;
 320	}
 321
 322	/* Additional sanity for read command if the specified
 323	 * entry is invalid
 324	 */
 325	val = mt7530_read(priv, MT7530_ATC);
 326	if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
 327		return -EINVAL;
 328
 329	if (rsp)
 330		*rsp = val;
 331
 332	return 0;
 333}
 334
 335static void
 336mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
 337{
 338	u32 reg[3];
 339	int i;
 340
 341	/* Read from ARL table into an array */
 342	for (i = 0; i < 3; i++) {
 343		reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
 344
 345		dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
 346			__func__, __LINE__, i, reg[i]);
 347	}
 348
 349	fdb->vid = (reg[1] >> CVID) & CVID_MASK;
 350	fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
 351	fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
 352	fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
 353	fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
 354	fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
 355	fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
 356	fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
 357	fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
 358	fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
 359}
 360
 361static void
 362mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
 363		 u8 port_mask, const u8 *mac,
 364		 u8 aging, u8 type)
 365{
 366	u32 reg[3] = { 0 };
 367	int i;
 368
 369	reg[1] |= vid & CVID_MASK;
 370	if (vid > 1)
 371		reg[1] |= ATA2_IVL;
 372	reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
 373	reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
 374	/* STATIC_ENT indicate that entry is static wouldn't
 375	 * be aged out and STATIC_EMP specified as erasing an
 376	 * entry
 377	 */
 378	reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
 379	reg[1] |= mac[5] << MAC_BYTE_5;
 380	reg[1] |= mac[4] << MAC_BYTE_4;
 381	reg[0] |= mac[3] << MAC_BYTE_3;
 382	reg[0] |= mac[2] << MAC_BYTE_2;
 383	reg[0] |= mac[1] << MAC_BYTE_1;
 384	reg[0] |= mac[0] << MAC_BYTE_0;
 385
 386	/* Write array into the ARL table */
 387	for (i = 0; i < 3; i++)
 388		mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
 389}
 390
 391/* Setup TX circuit including relevant PAD and driving */
 392static int
 393mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
 394{
 395	struct mt7530_priv *priv = ds->priv;
 396	u32 ncpo1, ssc_delta, trgint, i, xtal;
 397
 398	xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
 399
 400	if (xtal == HWTRAP_XTAL_20MHZ) {
 401		dev_err(priv->dev,
 402			"%s: MT7530 with a 20MHz XTAL is not supported!\n",
 403			__func__);
 404		return -EINVAL;
 405	}
 406
 407	switch (interface) {
 408	case PHY_INTERFACE_MODE_RGMII:
 409		trgint = 0;
 410		/* PLL frequency: 125MHz */
 411		ncpo1 = 0x0c80;
 412		break;
 413	case PHY_INTERFACE_MODE_TRGMII:
 414		trgint = 1;
 415		if (priv->id == ID_MT7621) {
 416			/* PLL frequency: 150MHz: 1.2GBit */
 417			if (xtal == HWTRAP_XTAL_40MHZ)
 418				ncpo1 = 0x0780;
 419			if (xtal == HWTRAP_XTAL_25MHZ)
 420				ncpo1 = 0x0a00;
 421		} else { /* PLL frequency: 250MHz: 2.0Gbit */
 422			if (xtal == HWTRAP_XTAL_40MHZ)
 423				ncpo1 = 0x0c80;
 424			if (xtal == HWTRAP_XTAL_25MHZ)
 425				ncpo1 = 0x1400;
 426		}
 427		break;
 428	default:
 429		dev_err(priv->dev, "xMII interface %d not supported\n",
 430			interface);
 431		return -EINVAL;
 432	}
 433
 434	if (xtal == HWTRAP_XTAL_25MHZ)
 435		ssc_delta = 0x57;
 436	else
 437		ssc_delta = 0x87;
 438
 439	mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
 440		   P6_INTF_MODE(trgint));
 441
 442	/* Lower Tx Driving for TRGMII path */
 443	for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
 444		mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
 445			     TD_DM_DRVP(8) | TD_DM_DRVN(8));
 446
 447	/* Disable MT7530 core and TRGMII Tx clocks */
 448	core_clear(priv, CORE_TRGMII_GSW_CLK_CG,
 449		   REG_GSWCK_EN | REG_TRGMIICK_EN);
 450
 451	/* Setup core clock for MT7530 */
 452	/* Disable PLL */
 453	core_write(priv, CORE_GSWPLL_GRP1, 0);
 454
 455	/* Set core clock into 500Mhz */
 456	core_write(priv, CORE_GSWPLL_GRP2,
 457		   RG_GSWPLL_POSDIV_500M(1) |
 458		   RG_GSWPLL_FBKDIV_500M(25));
 459
 460	/* Enable PLL */
 461	core_write(priv, CORE_GSWPLL_GRP1,
 462		   RG_GSWPLL_EN_PRE |
 463		   RG_GSWPLL_POSDIV_200M(2) |
 464		   RG_GSWPLL_FBKDIV_200M(32));
 465
 466	/* Setup the MT7530 TRGMII Tx Clock */
 467	core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
 468	core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
 469	core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
 470	core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
 471	core_write(priv, CORE_PLL_GROUP4,
 472		   RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
 473		   RG_SYSPLL_BIAS_LPF_EN);
 474	core_write(priv, CORE_PLL_GROUP2,
 475		   RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
 476		   RG_SYSPLL_POSDIV(1));
 477	core_write(priv, CORE_PLL_GROUP7,
 478		   RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
 479		   RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
 480
 481	/* Enable MT7530 core and TRGMII Tx clocks */
 482	core_set(priv, CORE_TRGMII_GSW_CLK_CG,
 483		 REG_GSWCK_EN | REG_TRGMIICK_EN);
 484
 485	if (!trgint)
 486		for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
 487			mt7530_rmw(priv, MT7530_TRGMII_RD(i),
 488				   RD_TAP_MASK, RD_TAP(16));
 489	return 0;
 490}
 491
 492static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
 493{
 494	u32 val;
 495
 496	val = mt7530_read(priv, MT7531_TOP_SIG_SR);
 497
 498	return (val & PAD_DUAL_SGMII_EN) != 0;
 499}
 500
 501static int
 502mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
 503{
 504	struct mt7530_priv *priv = ds->priv;
 505	u32 top_sig;
 506	u32 hwstrap;
 507	u32 xtal;
 508	u32 val;
 509
 510	if (mt7531_dual_sgmii_supported(priv))
 511		return 0;
 512
 513	val = mt7530_read(priv, MT7531_CREV);
 514	top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
 515	hwstrap = mt7530_read(priv, MT7531_HWTRAP);
 516	if ((val & CHIP_REV_M) > 0)
 517		xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
 518						    HWTRAP_XTAL_FSEL_25MHZ;
 519	else
 520		xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
 521
 522	/* Step 1 : Disable MT7531 COREPLL */
 523	val = mt7530_read(priv, MT7531_PLLGP_EN);
 524	val &= ~EN_COREPLL;
 525	mt7530_write(priv, MT7531_PLLGP_EN, val);
 526
 527	/* Step 2: switch to XTAL output */
 528	val = mt7530_read(priv, MT7531_PLLGP_EN);
 529	val |= SW_CLKSW;
 530	mt7530_write(priv, MT7531_PLLGP_EN, val);
 531
 532	val = mt7530_read(priv, MT7531_PLLGP_CR0);
 533	val &= ~RG_COREPLL_EN;
 534	mt7530_write(priv, MT7531_PLLGP_CR0, val);
 535
 536	/* Step 3: disable PLLGP and enable program PLLGP */
 537	val = mt7530_read(priv, MT7531_PLLGP_EN);
 538	val |= SW_PLLGP;
 539	mt7530_write(priv, MT7531_PLLGP_EN, val);
 540
 541	/* Step 4: program COREPLL output frequency to 500MHz */
 542	val = mt7530_read(priv, MT7531_PLLGP_CR0);
 543	val &= ~RG_COREPLL_POSDIV_M;
 544	val |= 2 << RG_COREPLL_POSDIV_S;
 545	mt7530_write(priv, MT7531_PLLGP_CR0, val);
 546	usleep_range(25, 35);
 547
 548	switch (xtal) {
 549	case HWTRAP_XTAL_FSEL_25MHZ:
 550		val = mt7530_read(priv, MT7531_PLLGP_CR0);
 551		val &= ~RG_COREPLL_SDM_PCW_M;
 552		val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
 553		mt7530_write(priv, MT7531_PLLGP_CR0, val);
 554		break;
 555	case HWTRAP_XTAL_FSEL_40MHZ:
 556		val = mt7530_read(priv, MT7531_PLLGP_CR0);
 557		val &= ~RG_COREPLL_SDM_PCW_M;
 558		val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
 559		mt7530_write(priv, MT7531_PLLGP_CR0, val);
 560		break;
 561	}
 562
 563	/* Set feedback divide ratio update signal to high */
 564	val = mt7530_read(priv, MT7531_PLLGP_CR0);
 565	val |= RG_COREPLL_SDM_PCW_CHG;
 566	mt7530_write(priv, MT7531_PLLGP_CR0, val);
 567	/* Wait for at least 16 XTAL clocks */
 568	usleep_range(10, 20);
 569
 570	/* Step 5: set feedback divide ratio update signal to low */
 571	val = mt7530_read(priv, MT7531_PLLGP_CR0);
 572	val &= ~RG_COREPLL_SDM_PCW_CHG;
 573	mt7530_write(priv, MT7531_PLLGP_CR0, val);
 574
 575	/* Enable 325M clock for SGMII */
 576	mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
 577
 578	/* Enable 250SSC clock for RGMII */
 579	mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
 580
 581	/* Step 6: Enable MT7531 PLL */
 582	val = mt7530_read(priv, MT7531_PLLGP_CR0);
 583	val |= RG_COREPLL_EN;
 584	mt7530_write(priv, MT7531_PLLGP_CR0, val);
 585
 586	val = mt7530_read(priv, MT7531_PLLGP_EN);
 587	val |= EN_COREPLL;
 588	mt7530_write(priv, MT7531_PLLGP_EN, val);
 589	usleep_range(25, 35);
 590
 591	return 0;
 592}
 593
 594static void
 595mt7530_mib_reset(struct dsa_switch *ds)
 596{
 597	struct mt7530_priv *priv = ds->priv;
 598
 599	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
 600	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
 601}
 602
 603static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum)
 604{
 605	return mdiobus_read_nested(priv->bus, port, regnum);
 606}
 607
 608static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum,
 609			    u16 val)
 610{
 611	return mdiobus_write_nested(priv->bus, port, regnum, val);
 612}
 613
 614static int
 615mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
 616			int regnum)
 617{
 618	struct mii_bus *bus = priv->bus;
 619	struct mt7530_dummy_poll p;
 620	u32 reg, val;
 621	int ret;
 622
 623	INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
 624
 625	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 626
 627	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 628				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
 629	if (ret < 0) {
 630		dev_err(priv->dev, "poll timeout\n");
 631		goto out;
 632	}
 633
 634	reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
 635	      MT7531_MDIO_DEV_ADDR(devad) | regnum;
 636	mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
 637
 638	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 639				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
 640	if (ret < 0) {
 641		dev_err(priv->dev, "poll timeout\n");
 642		goto out;
 643	}
 644
 645	reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
 646	      MT7531_MDIO_DEV_ADDR(devad);
 647	mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
 648
 649	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 650				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
 651	if (ret < 0) {
 652		dev_err(priv->dev, "poll timeout\n");
 653		goto out;
 654	}
 655
 656	ret = val & MT7531_MDIO_RW_DATA_MASK;
 657out:
 658	mutex_unlock(&bus->mdio_lock);
 659
 660	return ret;
 661}
 662
 663static int
 664mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
 665			 int regnum, u32 data)
 666{
 667	struct mii_bus *bus = priv->bus;
 668	struct mt7530_dummy_poll p;
 669	u32 val, reg;
 670	int ret;
 671
 672	INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
 673
 674	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 675
 676	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 677				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
 678	if (ret < 0) {
 679		dev_err(priv->dev, "poll timeout\n");
 680		goto out;
 681	}
 682
 683	reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
 684	      MT7531_MDIO_DEV_ADDR(devad) | regnum;
 685	mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
 686
 687	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 688				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
 689	if (ret < 0) {
 690		dev_err(priv->dev, "poll timeout\n");
 691		goto out;
 692	}
 693
 694	reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
 695	      MT7531_MDIO_DEV_ADDR(devad) | data;
 696	mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
 697
 698	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 699				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
 700	if (ret < 0) {
 701		dev_err(priv->dev, "poll timeout\n");
 702		goto out;
 703	}
 704
 705out:
 706	mutex_unlock(&bus->mdio_lock);
 707
 708	return ret;
 709}
 710
 711static int
 712mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
 713{
 714	struct mii_bus *bus = priv->bus;
 715	struct mt7530_dummy_poll p;
 716	int ret;
 717	u32 val;
 718
 719	INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
 720
 721	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 722
 723	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 724				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
 725	if (ret < 0) {
 726		dev_err(priv->dev, "poll timeout\n");
 727		goto out;
 728	}
 729
 730	val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
 731	      MT7531_MDIO_REG_ADDR(regnum);
 732
 733	mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
 734
 735	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
 736				 !(val & MT7531_PHY_ACS_ST), 20, 100000);
 737	if (ret < 0) {
 738		dev_err(priv->dev, "poll timeout\n");
 739		goto out;
 740	}
 741
 742	ret = val & MT7531_MDIO_RW_DATA_MASK;
 743out:
 744	mutex_unlock(&bus->mdio_lock);
 745
 746	return ret;
 747}
 748
 749static int
 750mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
 751			 u16 data)
 752{
 753	struct mii_bus *bus = priv->bus;
 754	struct mt7530_dummy_poll p;
 755	int ret;
 756	u32 reg;
 757
 758	INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
 759
 760	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 761
 762	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
 763				 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
 764	if (ret < 0) {
 765		dev_err(priv->dev, "poll timeout\n");
 766		goto out;
 767	}
 768
 769	reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
 770	      MT7531_MDIO_REG_ADDR(regnum) | data;
 771
 772	mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
 773
 774	ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
 775				 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
 776	if (ret < 0) {
 777		dev_err(priv->dev, "poll timeout\n");
 778		goto out;
 779	}
 780
 781out:
 782	mutex_unlock(&bus->mdio_lock);
 783
 784	return ret;
 785}
 786
 787static int
 788mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum)
 789{
 790	int devad;
 791	int ret;
 792
 793	if (regnum & MII_ADDR_C45) {
 794		devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
 795		ret = mt7531_ind_c45_phy_read(priv, port, devad,
 796					      regnum & MII_REGADDR_C45_MASK);
 797	} else {
 798		ret = mt7531_ind_c22_phy_read(priv, port, regnum);
 799	}
 800
 801	return ret;
 802}
 803
 804static int
 805mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum,
 806		     u16 data)
 807{
 808	int devad;
 809	int ret;
 810
 811	if (regnum & MII_ADDR_C45) {
 812		devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
 813		ret = mt7531_ind_c45_phy_write(priv, port, devad,
 814					       regnum & MII_REGADDR_C45_MASK,
 815					       data);
 816	} else {
 817		ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
 818	}
 819
 820	return ret;
 821}
 822
 823static int
 824mt753x_phy_read(struct mii_bus *bus, int port, int regnum)
 825{
 826	struct mt7530_priv *priv = bus->priv;
 827
 828	return priv->info->phy_read(priv, port, regnum);
 829}
 830
 831static int
 832mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val)
 833{
 834	struct mt7530_priv *priv = bus->priv;
 835
 836	return priv->info->phy_write(priv, port, regnum, val);
 837}
 838
 839static void
 840mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
 841		   uint8_t *data)
 842{
 843	int i;
 844
 845	if (stringset != ETH_SS_STATS)
 846		return;
 847
 848	for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
 849		strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
 850			ETH_GSTRING_LEN);
 851}
 852
 853static void
 854mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
 855			 uint64_t *data)
 856{
 857	struct mt7530_priv *priv = ds->priv;
 858	const struct mt7530_mib_desc *mib;
 859	u32 reg, i;
 860	u64 hi;
 861
 862	for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
 863		mib = &mt7530_mib[i];
 864		reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
 865
 866		data[i] = mt7530_read(priv, reg);
 867		if (mib->size == 2) {
 868			hi = mt7530_read(priv, reg + 4);
 869			data[i] |= hi << 32;
 870		}
 871	}
 872}
 873
 874static int
 875mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
 876{
 877	if (sset != ETH_SS_STATS)
 878		return 0;
 879
 880	return ARRAY_SIZE(mt7530_mib);
 881}
 882
 883static int
 884mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
 885{
 886	struct mt7530_priv *priv = ds->priv;
 887	unsigned int secs = msecs / 1000;
 888	unsigned int tmp_age_count;
 889	unsigned int error = -1;
 890	unsigned int age_count;
 891	unsigned int age_unit;
 892
 893	/* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
 894	if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
 895		return -ERANGE;
 896
 897	/* iterate through all possible age_count to find the closest pair */
 898	for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
 899		unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
 900
 901		if (tmp_age_unit <= AGE_UNIT_MAX) {
 902			unsigned int tmp_error = secs -
 903				(tmp_age_count + 1) * (tmp_age_unit + 1);
 904
 905			/* found a closer pair */
 906			if (error > tmp_error) {
 907				error = tmp_error;
 908				age_count = tmp_age_count;
 909				age_unit = tmp_age_unit;
 910			}
 911
 912			/* found the exact match, so break the loop */
 913			if (!error)
 914				break;
 915		}
 916	}
 917
 918	mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
 919
 920	return 0;
 921}
 922
 923static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
 924{
 925	struct mt7530_priv *priv = ds->priv;
 926	u8 tx_delay = 0;
 927	int val;
 928
 929	mutex_lock(&priv->reg_mutex);
 930
 931	val = mt7530_read(priv, MT7530_MHWTRAP);
 932
 933	val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
 934	val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
 935
 936	switch (priv->p5_intf_sel) {
 937	case P5_INTF_SEL_PHY_P0:
 938		/* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
 939		val |= MHWTRAP_PHY0_SEL;
 940		fallthrough;
 941	case P5_INTF_SEL_PHY_P4:
 942		/* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
 943		val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
 944
 945		/* Setup the MAC by default for the cpu port */
 946		mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
 947		break;
 948	case P5_INTF_SEL_GMAC5:
 949		/* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
 950		val &= ~MHWTRAP_P5_DIS;
 951		break;
 952	case P5_DISABLED:
 953		interface = PHY_INTERFACE_MODE_NA;
 954		break;
 955	default:
 956		dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
 957			priv->p5_intf_sel);
 958		goto unlock_exit;
 959	}
 960
 961	/* Setup RGMII settings */
 962	if (phy_interface_mode_is_rgmii(interface)) {
 963		val |= MHWTRAP_P5_RGMII_MODE;
 964
 965		/* P5 RGMII RX Clock Control: delay setting for 1000M */
 966		mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
 967
 968		/* Don't set delay in DSA mode */
 969		if (!dsa_is_dsa_port(priv->ds, 5) &&
 970		    (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
 971		     interface == PHY_INTERFACE_MODE_RGMII_ID))
 972			tx_delay = 4; /* n * 0.5 ns */
 973
 974		/* P5 RGMII TX Clock Control: delay x */
 975		mt7530_write(priv, MT7530_P5RGMIITXCR,
 976			     CSR_RGMII_TXC_CFG(0x10 + tx_delay));
 977
 978		/* reduce P5 RGMII Tx driving, 8mA */
 979		mt7530_write(priv, MT7530_IO_DRV_CR,
 980			     P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
 981	}
 982
 983	mt7530_write(priv, MT7530_MHWTRAP, val);
 984
 985	dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
 986		val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
 987
 988	priv->p5_interface = interface;
 989
 990unlock_exit:
 991	mutex_unlock(&priv->reg_mutex);
 992}
 993
 994static int
 995mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
 996{
 997	struct mt7530_priv *priv = ds->priv;
 998	int ret;
 999
1000	/* Setup max capability of CPU port at first */
1001	if (priv->info->cpu_port_config) {
1002		ret = priv->info->cpu_port_config(ds, port);
1003		if (ret)
1004			return ret;
1005	}
1006
1007	/* Enable Mediatek header mode on the cpu port */
1008	mt7530_write(priv, MT7530_PVC_P(port),
1009		     PORT_SPEC_TAG);
1010
1011	/* Disable flooding by default */
1012	mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK,
1013		   BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port)));
1014
1015	/* Set CPU port number */
1016	if (priv->id == ID_MT7621)
1017		mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1018
1019	/* CPU port gets connected to all user ports of
1020	 * the switch.
1021	 */
1022	mt7530_write(priv, MT7530_PCR_P(port),
1023		     PCR_MATRIX(dsa_user_ports(priv->ds)));
1024
1025	return 0;
1026}
1027
1028static int
1029mt7530_port_enable(struct dsa_switch *ds, int port,
1030		   struct phy_device *phy)
1031{
1032	struct mt7530_priv *priv = ds->priv;
1033
1034	mutex_lock(&priv->reg_mutex);
1035
1036	/* Allow the user port gets connected to the cpu port and also
1037	 * restore the port matrix if the port is the member of a certain
1038	 * bridge.
1039	 */
1040	priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
1041	priv->ports[port].enable = true;
1042	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1043		   priv->ports[port].pm);
1044	mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1045
1046	mutex_unlock(&priv->reg_mutex);
1047
1048	return 0;
1049}
1050
1051static void
1052mt7530_port_disable(struct dsa_switch *ds, int port)
1053{
1054	struct mt7530_priv *priv = ds->priv;
1055
1056	mutex_lock(&priv->reg_mutex);
1057
1058	/* Clear up all port matrix which could be restored in the next
1059	 * enablement for the port.
1060	 */
1061	priv->ports[port].enable = false;
1062	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1063		   PCR_MATRIX_CLR);
1064	mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
1065
1066	mutex_unlock(&priv->reg_mutex);
1067}
1068
1069static int
1070mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1071{
1072	struct mt7530_priv *priv = ds->priv;
1073	struct mii_bus *bus = priv->bus;
1074	int length;
1075	u32 val;
1076
1077	/* When a new MTU is set, DSA always set the CPU port's MTU to the
1078	 * largest MTU of the slave ports. Because the switch only has a global
1079	 * RX length register, only allowing CPU port here is enough.
1080	 */
1081	if (!dsa_is_cpu_port(ds, port))
1082		return 0;
1083
1084	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1085
1086	val = mt7530_mii_read(priv, MT7530_GMACCR);
1087	val &= ~MAX_RX_PKT_LEN_MASK;
1088
1089	/* RX length also includes Ethernet header, MTK tag, and FCS length */
1090	length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1091	if (length <= 1522) {
1092		val |= MAX_RX_PKT_LEN_1522;
1093	} else if (length <= 1536) {
1094		val |= MAX_RX_PKT_LEN_1536;
1095	} else if (length <= 1552) {
1096		val |= MAX_RX_PKT_LEN_1552;
1097	} else {
1098		val &= ~MAX_RX_JUMBO_MASK;
1099		val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1100		val |= MAX_RX_PKT_LEN_JUMBO;
1101	}
1102
1103	mt7530_mii_write(priv, MT7530_GMACCR, val);
1104
1105	mutex_unlock(&bus->mdio_lock);
1106
1107	return 0;
1108}
1109
1110static int
1111mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1112{
1113	return MT7530_MAX_MTU;
1114}
1115
1116static void
1117mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1118{
1119	struct mt7530_priv *priv = ds->priv;
1120	u32 stp_state;
1121
1122	switch (state) {
1123	case BR_STATE_DISABLED:
1124		stp_state = MT7530_STP_DISABLED;
1125		break;
1126	case BR_STATE_BLOCKING:
1127		stp_state = MT7530_STP_BLOCKING;
1128		break;
1129	case BR_STATE_LISTENING:
1130		stp_state = MT7530_STP_LISTENING;
1131		break;
1132	case BR_STATE_LEARNING:
1133		stp_state = MT7530_STP_LEARNING;
1134		break;
1135	case BR_STATE_FORWARDING:
1136	default:
1137		stp_state = MT7530_STP_FORWARDING;
1138		break;
1139	}
1140
1141	mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
1142}
1143
1144static int
1145mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1146			     struct switchdev_brport_flags flags,
1147			     struct netlink_ext_ack *extack)
1148{
1149	if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1150			   BR_BCAST_FLOOD))
1151		return -EINVAL;
1152
1153	return 0;
1154}
1155
1156static int
1157mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
1158			 struct switchdev_brport_flags flags,
1159			 struct netlink_ext_ack *extack)
1160{
1161	struct mt7530_priv *priv = ds->priv;
1162
1163	if (flags.mask & BR_LEARNING)
1164		mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
1165			   flags.val & BR_LEARNING ? 0 : SA_DIS);
1166
1167	if (flags.mask & BR_FLOOD)
1168		mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
1169			   flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1170
1171	if (flags.mask & BR_MCAST_FLOOD)
1172		mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1173			   flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1174
1175	if (flags.mask & BR_BCAST_FLOOD)
1176		mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
1177			   flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1178
1179	return 0;
1180}
1181
1182static int
1183mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1184			struct net_device *bridge)
1185{
1186	struct mt7530_priv *priv = ds->priv;
1187	u32 port_bitmap = BIT(MT7530_CPU_PORT);
1188	int i;
1189
1190	mutex_lock(&priv->reg_mutex);
1191
1192	for (i = 0; i < MT7530_NUM_PORTS; i++) {
1193		/* Add this port to the port matrix of the other ports in the
1194		 * same bridge. If the port is disabled, port matrix is kept
1195		 * and not being setup until the port becomes enabled.
1196		 */
1197		if (dsa_is_user_port(ds, i) && i != port) {
1198			if (dsa_to_port(ds, i)->bridge_dev != bridge)
1199				continue;
1200			if (priv->ports[i].enable)
1201				mt7530_set(priv, MT7530_PCR_P(i),
1202					   PCR_MATRIX(BIT(port)));
1203			priv->ports[i].pm |= PCR_MATRIX(BIT(port));
1204
1205			port_bitmap |= BIT(i);
1206		}
1207	}
1208
1209	/* Add the all other ports to this port matrix. */
1210	if (priv->ports[port].enable)
1211		mt7530_rmw(priv, MT7530_PCR_P(port),
1212			   PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1213	priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1214
1215	mutex_unlock(&priv->reg_mutex);
1216
1217	return 0;
1218}
1219
1220static void
1221mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1222{
1223	struct mt7530_priv *priv = ds->priv;
1224	bool all_user_ports_removed = true;
1225	int i;
1226
1227	/* When a port is removed from the bridge, the port would be set up
1228	 * back to the default as is at initial boot which is a VLAN-unaware
1229	 * port.
1230	 */
1231	mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1232		   MT7530_PORT_MATRIX_MODE);
1233	mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1234		   VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
1235		   PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1236
1237	for (i = 0; i < MT7530_NUM_PORTS; i++) {
1238		if (dsa_is_user_port(ds, i) &&
1239		    dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
1240			all_user_ports_removed = false;
1241			break;
1242		}
1243	}
1244
1245	/* CPU port also does the same thing until all user ports belonging to
1246	 * the CPU port get out of VLAN filtering mode.
1247	 */
1248	if (all_user_ports_removed) {
1249		mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
1250			     PCR_MATRIX(dsa_user_ports(priv->ds)));
1251		mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
1252			     | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1253	}
1254}
1255
1256static void
1257mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1258{
1259	struct mt7530_priv *priv = ds->priv;
1260
1261	/* Trapped into security mode allows packet forwarding through VLAN
1262	 * table lookup. CPU port is set to fallback mode to let untagged
1263	 * frames pass through.
1264	 */
1265	if (dsa_is_cpu_port(ds, port))
1266		mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1267			   MT7530_PORT_FALLBACK_MODE);
1268	else
1269		mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1270			   MT7530_PORT_SECURITY_MODE);
1271
1272	/* Set the port as a user port which is to be able to recognize VID
1273	 * from incoming packets before fetching entry within the VLAN table.
1274	 */
1275	mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1276		   VLAN_ATTR(MT7530_VLAN_USER) |
1277		   PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
1278}
1279
1280static void
1281mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1282			 struct net_device *bridge)
1283{
1284	struct mt7530_priv *priv = ds->priv;
1285	int i;
1286
1287	mutex_lock(&priv->reg_mutex);
1288
1289	for (i = 0; i < MT7530_NUM_PORTS; i++) {
1290		/* Remove this port from the port matrix of the other ports
1291		 * in the same bridge. If the port is disabled, port matrix
1292		 * is kept and not being setup until the port becomes enabled.
1293		 */
1294		if (dsa_is_user_port(ds, i) && i != port) {
1295			if (dsa_to_port(ds, i)->bridge_dev != bridge)
1296				continue;
1297			if (priv->ports[i].enable)
1298				mt7530_clear(priv, MT7530_PCR_P(i),
1299					     PCR_MATRIX(BIT(port)));
1300			priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
1301		}
1302	}
1303
1304	/* Set the cpu port to be the only one in the port matrix of
1305	 * this port.
1306	 */
1307	if (priv->ports[port].enable)
1308		mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1309			   PCR_MATRIX(BIT(MT7530_CPU_PORT)));
1310	priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
1311
1312	mutex_unlock(&priv->reg_mutex);
1313}
1314
1315static int
1316mt7530_port_fdb_add(struct dsa_switch *ds, int port,
1317		    const unsigned char *addr, u16 vid)
1318{
1319	struct mt7530_priv *priv = ds->priv;
1320	int ret;
1321	u8 port_mask = BIT(port);
1322
1323	mutex_lock(&priv->reg_mutex);
1324	mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1325	ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1326	mutex_unlock(&priv->reg_mutex);
1327
1328	return ret;
1329}
1330
1331static int
1332mt7530_port_fdb_del(struct dsa_switch *ds, int port,
1333		    const unsigned char *addr, u16 vid)
1334{
1335	struct mt7530_priv *priv = ds->priv;
1336	int ret;
1337	u8 port_mask = BIT(port);
1338
1339	mutex_lock(&priv->reg_mutex);
1340	mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
1341	ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1342	mutex_unlock(&priv->reg_mutex);
1343
1344	return ret;
1345}
1346
1347static int
1348mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
1349		     dsa_fdb_dump_cb_t *cb, void *data)
1350{
1351	struct mt7530_priv *priv = ds->priv;
1352	struct mt7530_fdb _fdb = { 0 };
1353	int cnt = MT7530_NUM_FDB_RECORDS;
1354	int ret = 0;
1355	u32 rsp = 0;
1356
1357	mutex_lock(&priv->reg_mutex);
1358
1359	ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1360	if (ret < 0)
1361		goto err;
1362
1363	do {
1364		if (rsp & ATC_SRCH_HIT) {
1365			mt7530_fdb_read(priv, &_fdb);
1366			if (_fdb.port_mask & BIT(port)) {
1367				ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1368					 data);
1369				if (ret < 0)
1370					break;
1371			}
1372		}
1373	} while (--cnt &&
1374		 !(rsp & ATC_SRCH_END) &&
1375		 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1376err:
1377	mutex_unlock(&priv->reg_mutex);
1378
1379	return 0;
1380}
1381
1382static int
1383mt7530_port_mdb_add(struct dsa_switch *ds, int port,
1384		    const struct switchdev_obj_port_mdb *mdb)
1385{
1386	struct mt7530_priv *priv = ds->priv;
1387	const u8 *addr = mdb->addr;
1388	u16 vid = mdb->vid;
1389	u8 port_mask = 0;
1390	int ret;
1391
1392	mutex_lock(&priv->reg_mutex);
1393
1394	mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1395	if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1396		port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1397			    & PORT_MAP_MASK;
1398
1399	port_mask |= BIT(port);
1400	mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1401	ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1402
1403	mutex_unlock(&priv->reg_mutex);
1404
1405	return ret;
1406}
1407
1408static int
1409mt7530_port_mdb_del(struct dsa_switch *ds, int port,
1410		    const struct switchdev_obj_port_mdb *mdb)
1411{
1412	struct mt7530_priv *priv = ds->priv;
1413	const u8 *addr = mdb->addr;
1414	u16 vid = mdb->vid;
1415	u8 port_mask = 0;
1416	int ret;
1417
1418	mutex_lock(&priv->reg_mutex);
1419
1420	mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1421	if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1422		port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1423			    & PORT_MAP_MASK;
1424
1425	port_mask &= ~BIT(port);
1426	mt7530_fdb_write(priv, vid, port_mask, addr, -1,
1427			 port_mask ? STATIC_ENT : STATIC_EMP);
1428	ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1429
1430	mutex_unlock(&priv->reg_mutex);
1431
1432	return ret;
1433}
1434
1435static int
1436mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1437{
1438	struct mt7530_dummy_poll p;
1439	u32 val;
1440	int ret;
1441
1442	val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1443	mt7530_write(priv, MT7530_VTCR, val);
1444
1445	INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1446	ret = readx_poll_timeout(_mt7530_read, &p, val,
1447				 !(val & VTCR_BUSY), 20, 20000);
1448	if (ret < 0) {
1449		dev_err(priv->dev, "poll timeout\n");
1450		return ret;
1451	}
1452
1453	val = mt7530_read(priv, MT7530_VTCR);
1454	if (val & VTCR_INVALID) {
1455		dev_err(priv->dev, "read VTCR invalid\n");
1456		return -EINVAL;
1457	}
1458
1459	return 0;
1460}
1461
1462static int
1463mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1464			   struct netlink_ext_ack *extack)
1465{
1466	if (vlan_filtering) {
1467		/* The port is being kept as VLAN-unaware port when bridge is
1468		 * set up with vlan_filtering not being set, Otherwise, the
1469		 * port and the corresponding CPU port is required the setup
1470		 * for becoming a VLAN-aware port.
1471		 */
1472		mt7530_port_set_vlan_aware(ds, port);
1473		mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
1474	} else {
1475		mt7530_port_set_vlan_unaware(ds, port);
1476	}
1477
1478	return 0;
1479}
1480
1481static void
1482mt7530_hw_vlan_add(struct mt7530_priv *priv,
1483		   struct mt7530_hw_vlan_entry *entry)
1484{
1485	u8 new_members;
1486	u32 val;
1487
1488	new_members = entry->old_members | BIT(entry->port) |
1489		      BIT(MT7530_CPU_PORT);
1490
1491	/* Validate the entry with independent learning, create egress tag per
1492	 * VLAN and joining the port as one of the port members.
1493	 */
1494	val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1495	mt7530_write(priv, MT7530_VAWD1, val);
1496
1497	/* Decide whether adding tag or not for those outgoing packets from the
1498	 * port inside the VLAN.
1499	 */
1500	val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1501				MT7530_VLAN_EGRESS_TAG;
1502	mt7530_rmw(priv, MT7530_VAWD2,
1503		   ETAG_CTRL_P_MASK(entry->port),
1504		   ETAG_CTRL_P(entry->port, val));
1505
1506	/* CPU port is always taken as a tagged port for serving more than one
1507	 * VLANs across and also being applied with egress type stack mode for
1508	 * that VLAN tags would be appended after hardware special tag used as
1509	 * DSA tag.
1510	 */
1511	mt7530_rmw(priv, MT7530_VAWD2,
1512		   ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1513		   ETAG_CTRL_P(MT7530_CPU_PORT,
1514			       MT7530_VLAN_EGRESS_STACK));
1515}
1516
1517static void
1518mt7530_hw_vlan_del(struct mt7530_priv *priv,
1519		   struct mt7530_hw_vlan_entry *entry)
1520{
1521	u8 new_members;
1522	u32 val;
1523
1524	new_members = entry->old_members & ~BIT(entry->port);
1525
1526	val = mt7530_read(priv, MT7530_VAWD1);
1527	if (!(val & VLAN_VALID)) {
1528		dev_err(priv->dev,
1529			"Cannot be deleted due to invalid entry\n");
1530		return;
1531	}
1532
1533	/* If certain member apart from CPU port is still alive in the VLAN,
1534	 * the entry would be kept valid. Otherwise, the entry is got to be
1535	 * disabled.
1536	 */
1537	if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1538		val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1539		      VLAN_VALID;
1540		mt7530_write(priv, MT7530_VAWD1, val);
1541	} else {
1542		mt7530_write(priv, MT7530_VAWD1, 0);
1543		mt7530_write(priv, MT7530_VAWD2, 0);
1544	}
1545}
1546
1547static void
1548mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1549		      struct mt7530_hw_vlan_entry *entry,
1550		      mt7530_vlan_op vlan_op)
1551{
1552	u32 val;
1553
1554	/* Fetch entry */
1555	mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1556
1557	val = mt7530_read(priv, MT7530_VAWD1);
1558
1559	entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1560
1561	/* Manipulate entry */
1562	vlan_op(priv, entry);
1563
1564	/* Flush result to hardware */
1565	mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1566}
1567
1568static int
1569mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1570		     const struct switchdev_obj_port_vlan *vlan,
1571		     struct netlink_ext_ack *extack)
1572{
1573	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1574	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1575	struct mt7530_hw_vlan_entry new_entry;
1576	struct mt7530_priv *priv = ds->priv;
1577
1578	mutex_lock(&priv->reg_mutex);
1579
1580	mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1581	mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
1582
1583	if (pvid) {
1584		mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1585			   G0_PORT_VID(vlan->vid));
1586		priv->ports[port].pvid = vlan->vid;
1587	}
1588
1589	mutex_unlock(&priv->reg_mutex);
1590
1591	return 0;
1592}
1593
1594static int
1595mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1596		     const struct switchdev_obj_port_vlan *vlan)
1597{
1598	struct mt7530_hw_vlan_entry target_entry;
1599	struct mt7530_priv *priv = ds->priv;
1600	u16 pvid;
1601
1602	mutex_lock(&priv->reg_mutex);
1603
1604	pvid = priv->ports[port].pvid;
1605	mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1606	mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1607			      mt7530_hw_vlan_del);
1608
1609	/* PVID is being restored to the default whenever the PVID port
1610	 * is being removed from the VLAN.
1611	 */
1612	if (pvid == vlan->vid)
1613		pvid = G0_PORT_VID_DEF;
1614
1615	mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1616	priv->ports[port].pvid = pvid;
1617
1618	mutex_unlock(&priv->reg_mutex);
1619
1620	return 0;
1621}
1622
1623static int mt753x_mirror_port_get(unsigned int id, u32 val)
1624{
1625	return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1626				   MIRROR_PORT(val);
1627}
1628
1629static int mt753x_mirror_port_set(unsigned int id, u32 val)
1630{
1631	return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1632				   MIRROR_PORT(val);
1633}
1634
1635static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
1636				  struct dsa_mall_mirror_tc_entry *mirror,
1637				  bool ingress)
1638{
1639	struct mt7530_priv *priv = ds->priv;
1640	int monitor_port;
1641	u32 val;
1642
1643	/* Check for existent entry */
1644	if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1645		return -EEXIST;
1646
1647	val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1648
1649	/* MT7530 only supports one monitor port */
1650	monitor_port = mt753x_mirror_port_get(priv->id, val);
1651	if (val & MT753X_MIRROR_EN(priv->id) &&
1652	    monitor_port != mirror->to_local_port)
1653		return -EEXIST;
1654
1655	val |= MT753X_MIRROR_EN(priv->id);
1656	val &= ~MT753X_MIRROR_MASK(priv->id);
1657	val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1658	mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1659
1660	val = mt7530_read(priv, MT7530_PCR_P(port));
1661	if (ingress) {
1662		val |= PORT_RX_MIR;
1663		priv->mirror_rx |= BIT(port);
1664	} else {
1665		val |= PORT_TX_MIR;
1666		priv->mirror_tx |= BIT(port);
1667	}
1668	mt7530_write(priv, MT7530_PCR_P(port), val);
1669
1670	return 0;
1671}
1672
1673static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
1674				   struct dsa_mall_mirror_tc_entry *mirror)
1675{
1676	struct mt7530_priv *priv = ds->priv;
1677	u32 val;
1678
1679	val = mt7530_read(priv, MT7530_PCR_P(port));
1680	if (mirror->ingress) {
1681		val &= ~PORT_RX_MIR;
1682		priv->mirror_rx &= ~BIT(port);
1683	} else {
1684		val &= ~PORT_TX_MIR;
1685		priv->mirror_tx &= ~BIT(port);
1686	}
1687	mt7530_write(priv, MT7530_PCR_P(port), val);
1688
1689	if (!priv->mirror_rx && !priv->mirror_tx) {
1690		val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1691		val &= ~MT753X_MIRROR_EN(priv->id);
1692		mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
1693	}
1694}
1695
1696static enum dsa_tag_protocol
1697mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1698		     enum dsa_tag_protocol mp)
1699{
1700	struct mt7530_priv *priv = ds->priv;
1701
1702	if (port != MT7530_CPU_PORT) {
1703		dev_warn(priv->dev,
1704			 "port not matched with tagging CPU port\n");
1705		return DSA_TAG_PROTO_NONE;
1706	} else {
1707		return DSA_TAG_PROTO_MTK;
1708	}
1709}
1710
1711#ifdef CONFIG_GPIOLIB
1712static inline u32
1713mt7530_gpio_to_bit(unsigned int offset)
1714{
1715	/* Map GPIO offset to register bit
1716	 * [ 2: 0]  port 0 LED 0..2 as GPIO 0..2
1717	 * [ 6: 4]  port 1 LED 0..2 as GPIO 3..5
1718	 * [10: 8]  port 2 LED 0..2 as GPIO 6..8
1719	 * [14:12]  port 3 LED 0..2 as GPIO 9..11
1720	 * [18:16]  port 4 LED 0..2 as GPIO 12..14
1721	 */
1722	return BIT(offset + offset / 3);
1723}
1724
1725static int
1726mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1727{
1728	struct mt7530_priv *priv = gpiochip_get_data(gc);
1729	u32 bit = mt7530_gpio_to_bit(offset);
1730
1731	return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1732}
1733
1734static void
1735mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1736{
1737	struct mt7530_priv *priv = gpiochip_get_data(gc);
1738	u32 bit = mt7530_gpio_to_bit(offset);
1739
1740	if (value)
1741		mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1742	else
1743		mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1744}
1745
1746static int
1747mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1748{
1749	struct mt7530_priv *priv = gpiochip_get_data(gc);
1750	u32 bit = mt7530_gpio_to_bit(offset);
1751
1752	return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1753		GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1754}
1755
1756static int
1757mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1758{
1759	struct mt7530_priv *priv = gpiochip_get_data(gc);
1760	u32 bit = mt7530_gpio_to_bit(offset);
1761
1762	mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1763	mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1764
1765	return 0;
1766}
1767
1768static int
1769mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1770{
1771	struct mt7530_priv *priv = gpiochip_get_data(gc);
1772	u32 bit = mt7530_gpio_to_bit(offset);
1773
1774	mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1775
1776	if (value)
1777		mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1778	else
1779		mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1780
1781	mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1782
1783	return 0;
1784}
1785
1786static int
1787mt7530_setup_gpio(struct mt7530_priv *priv)
1788{
1789	struct device *dev = priv->dev;
1790	struct gpio_chip *gc;
1791
1792	gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1793	if (!gc)
1794		return -ENOMEM;
1795
1796	mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1797	mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1798	mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1799
1800	gc->label = "mt7530";
1801	gc->parent = dev;
1802	gc->owner = THIS_MODULE;
1803	gc->get_direction = mt7530_gpio_get_direction;
1804	gc->direction_input = mt7530_gpio_direction_input;
1805	gc->direction_output = mt7530_gpio_direction_output;
1806	gc->get = mt7530_gpio_get;
1807	gc->set = mt7530_gpio_set;
1808	gc->base = -1;
1809	gc->ngpio = 15;
1810	gc->can_sleep = true;
1811
1812	return devm_gpiochip_add_data(dev, gc, priv);
1813}
1814#endif /* CONFIG_GPIOLIB */
1815
1816static irqreturn_t
1817mt7530_irq_thread_fn(int irq, void *dev_id)
1818{
1819	struct mt7530_priv *priv = dev_id;
1820	bool handled = false;
1821	u32 val;
1822	int p;
1823
1824	mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1825	val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
1826	mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
1827	mutex_unlock(&priv->bus->mdio_lock);
1828
1829	for (p = 0; p < MT7530_NUM_PHYS; p++) {
1830		if (BIT(p) & val) {
1831			unsigned int irq;
1832
1833			irq = irq_find_mapping(priv->irq_domain, p);
1834			handle_nested_irq(irq);
1835			handled = true;
1836		}
1837	}
1838
1839	return IRQ_RETVAL(handled);
1840}
1841
1842static void
1843mt7530_irq_mask(struct irq_data *d)
1844{
1845	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1846
1847	priv->irq_enable &= ~BIT(d->hwirq);
1848}
1849
1850static void
1851mt7530_irq_unmask(struct irq_data *d)
1852{
1853	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1854
1855	priv->irq_enable |= BIT(d->hwirq);
1856}
1857
1858static void
1859mt7530_irq_bus_lock(struct irq_data *d)
1860{
1861	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1862
1863	mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1864}
1865
1866static void
1867mt7530_irq_bus_sync_unlock(struct irq_data *d)
1868{
1869	struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1870
1871	mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1872	mutex_unlock(&priv->bus->mdio_lock);
1873}
1874
1875static struct irq_chip mt7530_irq_chip = {
1876	.name = KBUILD_MODNAME,
1877	.irq_mask = mt7530_irq_mask,
1878	.irq_unmask = mt7530_irq_unmask,
1879	.irq_bus_lock = mt7530_irq_bus_lock,
1880	.irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock,
1881};
1882
1883static int
1884mt7530_irq_map(struct irq_domain *domain, unsigned int irq,
1885	       irq_hw_number_t hwirq)
1886{
1887	irq_set_chip_data(irq, domain->host_data);
1888	irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq);
1889	irq_set_nested_thread(irq, true);
1890	irq_set_noprobe(irq);
1891
1892	return 0;
1893}
1894
1895static const struct irq_domain_ops mt7530_irq_domain_ops = {
1896	.map = mt7530_irq_map,
1897	.xlate = irq_domain_xlate_onecell,
1898};
1899
1900static void
1901mt7530_setup_mdio_irq(struct mt7530_priv *priv)
1902{
1903	struct dsa_switch *ds = priv->ds;
1904	int p;
1905
1906	for (p = 0; p < MT7530_NUM_PHYS; p++) {
1907		if (BIT(p) & ds->phys_mii_mask) {
1908			unsigned int irq;
1909
1910			irq = irq_create_mapping(priv->irq_domain, p);
1911			ds->slave_mii_bus->irq[p] = irq;
1912		}
1913	}
1914}
1915
1916static int
1917mt7530_setup_irq(struct mt7530_priv *priv)
1918{
1919	struct device *dev = priv->dev;
1920	struct device_node *np = dev->of_node;
1921	int ret;
1922
1923	if (!of_property_read_bool(np, "interrupt-controller")) {
1924		dev_info(dev, "no interrupt support\n");
1925		return 0;
1926	}
1927
1928	priv->irq = of_irq_get(np, 0);
1929	if (priv->irq <= 0) {
1930		dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq);
1931		return priv->irq ? : -EINVAL;
1932	}
1933
1934	priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
1935						 &mt7530_irq_domain_ops, priv);
1936	if (!priv->irq_domain) {
1937		dev_err(dev, "failed to create IRQ domain\n");
1938		return -ENOMEM;
1939	}
1940
1941	/* This register must be set for MT7530 to properly fire interrupts */
1942	if (priv->id != ID_MT7531)
1943		mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
1944
1945	ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
1946				   IRQF_ONESHOT, KBUILD_MODNAME, priv);
1947	if (ret) {
1948		irq_domain_remove(priv->irq_domain);
1949		dev_err(dev, "failed to request IRQ: %d\n", ret);
1950		return ret;
1951	}
1952
1953	return 0;
1954}
1955
1956static void
1957mt7530_free_mdio_irq(struct mt7530_priv *priv)
1958{
1959	int p;
1960
1961	for (p = 0; p < MT7530_NUM_PHYS; p++) {
1962		if (BIT(p) & priv->ds->phys_mii_mask) {
1963			unsigned int irq;
1964
1965			irq = irq_find_mapping(priv->irq_domain, p);
1966			irq_dispose_mapping(irq);
1967		}
1968	}
1969}
1970
1971static void
1972mt7530_free_irq_common(struct mt7530_priv *priv)
1973{
1974	free_irq(priv->irq, priv);
1975	irq_domain_remove(priv->irq_domain);
1976}
1977
1978static void
1979mt7530_free_irq(struct mt7530_priv *priv)
1980{
1981	mt7530_free_mdio_irq(priv);
1982	mt7530_free_irq_common(priv);
1983}
1984
1985static int
1986mt7530_setup_mdio(struct mt7530_priv *priv)
1987{
1988	struct dsa_switch *ds = priv->ds;
1989	struct device *dev = priv->dev;
1990	struct mii_bus *bus;
1991	static int idx;
1992	int ret;
1993
1994	bus = devm_mdiobus_alloc(dev);
1995	if (!bus)
1996		return -ENOMEM;
1997
1998	ds->slave_mii_bus = bus;
1999	bus->priv = priv;
2000	bus->name = KBUILD_MODNAME "-mii";
2001	snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
2002	bus->read = mt753x_phy_read;
2003	bus->write = mt753x_phy_write;
2004	bus->parent = dev;
2005	bus->phy_mask = ~ds->phys_mii_mask;
2006
2007	if (priv->irq)
2008		mt7530_setup_mdio_irq(priv);
2009
2010	ret = mdiobus_register(bus);
2011	if (ret) {
2012		dev_err(dev, "failed to register MDIO bus: %d\n", ret);
2013		if (priv->irq)
2014			mt7530_free_mdio_irq(priv);
2015	}
2016
2017	return ret;
2018}
2019
2020static int
2021mt7530_setup(struct dsa_switch *ds)
2022{
2023	struct mt7530_priv *priv = ds->priv;
2024	struct device_node *phy_node;
2025	struct device_node *mac_np;
2026	struct mt7530_dummy_poll p;
2027	phy_interface_t interface;
2028	struct device_node *dn;
2029	u32 id, val;
2030	int ret, i;
2031
2032	/* The parent node of master netdev which holds the common system
2033	 * controller also is the container for two GMACs nodes representing
2034	 * as two netdev instances.
2035	 */
2036	dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
2037	ds->mtu_enforcement_ingress = true;
2038
2039	if (priv->id == ID_MT7530) {
2040		regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
2041		ret = regulator_enable(priv->core_pwr);
2042		if (ret < 0) {
2043			dev_err(priv->dev,
2044				"Failed to enable core power: %d\n", ret);
2045			return ret;
2046		}
2047
2048		regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
2049		ret = regulator_enable(priv->io_pwr);
2050		if (ret < 0) {
2051			dev_err(priv->dev, "Failed to enable io pwr: %d\n",
2052				ret);
2053			return ret;
2054		}
2055	}
2056
2057	/* Reset whole chip through gpio pin or memory-mapped registers for
2058	 * different type of hardware
2059	 */
2060	if (priv->mcm) {
2061		reset_control_assert(priv->rstc);
2062		usleep_range(1000, 1100);
2063		reset_control_deassert(priv->rstc);
2064	} else {
2065		gpiod_set_value_cansleep(priv->reset, 0);
2066		usleep_range(1000, 1100);
2067		gpiod_set_value_cansleep(priv->reset, 1);
2068	}
2069
2070	/* Waiting for MT7530 got to stable */
2071	INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2072	ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2073				 20, 1000000);
2074	if (ret < 0) {
2075		dev_err(priv->dev, "reset timeout\n");
2076		return ret;
2077	}
2078
2079	id = mt7530_read(priv, MT7530_CREV);
2080	id >>= CHIP_NAME_SHIFT;
2081	if (id != MT7530_ID) {
2082		dev_err(priv->dev, "chip %x can't be supported\n", id);
2083		return -ENODEV;
2084	}
2085
2086	/* Reset the switch through internal reset */
2087	mt7530_write(priv, MT7530_SYS_CTRL,
2088		     SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2089		     SYS_CTRL_REG_RST);
2090
2091	/* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
2092	val = mt7530_read(priv, MT7530_MHWTRAP);
2093	val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
2094	val |= MHWTRAP_MANUAL;
2095	mt7530_write(priv, MT7530_MHWTRAP, val);
2096
2097	priv->p6_interface = PHY_INTERFACE_MODE_NA;
2098
2099	/* Enable and reset MIB counters */
2100	mt7530_mib_reset(ds);
2101
2102	for (i = 0; i < MT7530_NUM_PORTS; i++) {
2103		/* Disable forwarding by default on all ports */
2104		mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2105			   PCR_MATRIX_CLR);
2106
2107		if (dsa_is_cpu_port(ds, i)) {
2108			ret = mt753x_cpu_port_enable(ds, i);
2109			if (ret)
2110				return ret;
2111		} else {
2112			mt7530_port_disable(ds, i);
2113
2114			/* Disable learning by default on all user ports */
2115			mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2116		}
2117		/* Enable consistent egress tag */
2118		mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2119			   PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2120	}
2121
2122	/* Setup port 5 */
2123	priv->p5_intf_sel = P5_DISABLED;
2124	interface = PHY_INTERFACE_MODE_NA;
2125
2126	if (!dsa_is_unused_port(ds, 5)) {
2127		priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2128		ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
2129		if (ret && ret != -ENODEV)
2130			return ret;
2131	} else {
2132		/* Scan the ethernet nodes. look for GMAC1, lookup used phy */
2133		for_each_child_of_node(dn, mac_np) {
2134			if (!of_device_is_compatible(mac_np,
2135						     "mediatek,eth-mac"))
2136				continue;
2137
2138			ret = of_property_read_u32(mac_np, "reg", &id);
2139			if (ret < 0 || id != 1)
2140				continue;
2141
2142			phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
2143			if (!phy_node)
2144				continue;
2145
2146			if (phy_node->parent == priv->dev->of_node->parent) {
2147				ret = of_get_phy_mode(mac_np, &interface);
2148				if (ret && ret != -ENODEV) {
2149					of_node_put(mac_np);
2150					return ret;
2151				}
2152				id = of_mdio_parse_addr(ds->dev, phy_node);
2153				if (id == 0)
2154					priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
2155				if (id == 4)
2156					priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
2157			}
2158			of_node_put(mac_np);
2159			of_node_put(phy_node);
2160			break;
2161		}
2162	}
2163
2164#ifdef CONFIG_GPIOLIB
2165	if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
2166		ret = mt7530_setup_gpio(priv);
2167		if (ret)
2168			return ret;
2169	}
2170#endif /* CONFIG_GPIOLIB */
2171
2172	mt7530_setup_port5(ds, interface);
2173
2174	/* Flush the FDB table */
2175	ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2176	if (ret < 0)
2177		return ret;
2178
2179	return 0;
2180}
2181
2182static int
2183mt7531_setup(struct dsa_switch *ds)
2184{
2185	struct mt7530_priv *priv = ds->priv;
2186	struct mt7530_dummy_poll p;
2187	u32 val, id;
2188	int ret, i;
2189
2190	/* Reset whole chip through gpio pin or memory-mapped registers for
2191	 * different type of hardware
2192	 */
2193	if (priv->mcm) {
2194		reset_control_assert(priv->rstc);
2195		usleep_range(1000, 1100);
2196		reset_control_deassert(priv->rstc);
2197	} else {
2198		gpiod_set_value_cansleep(priv->reset, 0);
2199		usleep_range(1000, 1100);
2200		gpiod_set_value_cansleep(priv->reset, 1);
2201	}
2202
2203	/* Waiting for MT7530 got to stable */
2204	INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2205	ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2206				 20, 1000000);
2207	if (ret < 0) {
2208		dev_err(priv->dev, "reset timeout\n");
2209		return ret;
2210	}
2211
2212	id = mt7530_read(priv, MT7531_CREV);
2213	id >>= CHIP_NAME_SHIFT;
2214
2215	if (id != MT7531_ID) {
2216		dev_err(priv->dev, "chip %x can't be supported\n", id);
2217		return -ENODEV;
2218	}
2219
2220	/* Reset the switch through internal reset */
2221	mt7530_write(priv, MT7530_SYS_CTRL,
2222		     SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2223		     SYS_CTRL_REG_RST);
2224
2225	if (mt7531_dual_sgmii_supported(priv)) {
2226		priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
2227
2228		/* Let ds->slave_mii_bus be able to access external phy. */
2229		mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
2230			   MT7531_EXT_P_MDC_11);
2231		mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
2232			   MT7531_EXT_P_MDIO_12);
2233	} else {
2234		priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2235	}
2236	dev_dbg(ds->dev, "P5 support %s interface\n",
2237		p5_intf_modes(priv->p5_intf_sel));
2238
2239	mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
2240		   MT7531_GPIO0_INTERRUPT);
2241
2242	/* Let phylink decide the interface later. */
2243	priv->p5_interface = PHY_INTERFACE_MODE_NA;
2244	priv->p6_interface = PHY_INTERFACE_MODE_NA;
2245
2246	/* Enable PHY core PLL, since phy_device has not yet been created
2247	 * provided for phy_[read,write]_mmd_indirect is called, we provide
2248	 * our own mt7531_ind_mmd_phy_[read,write] to complete this
2249	 * function.
2250	 */
2251	val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
2252				      MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2253	val |= MT7531_PHY_PLL_BYPASS_MODE;
2254	val &= ~MT7531_PHY_PLL_OFF;
2255	mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
2256				 CORE_PLL_GROUP4, val);
2257
2258	/* BPDU to CPU port */
2259	mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
2260		   BIT(MT7530_CPU_PORT));
2261	mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
2262		   MT753X_BPDU_CPU_ONLY);
2263
2264	/* Enable and reset MIB counters */
2265	mt7530_mib_reset(ds);
2266
2267	for (i = 0; i < MT7530_NUM_PORTS; i++) {
2268		/* Disable forwarding by default on all ports */
2269		mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2270			   PCR_MATRIX_CLR);
2271
2272		mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
2273
2274		if (dsa_is_cpu_port(ds, i)) {
2275			ret = mt753x_cpu_port_enable(ds, i);
2276			if (ret)
2277				return ret;
2278		} else {
2279			mt7530_port_disable(ds, i);
2280
2281			/* Disable learning by default on all user ports */
2282			mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2283		}
2284
2285		/* Enable consistent egress tag */
2286		mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2287			   PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2288	}
2289
2290	ds->mtu_enforcement_ingress = true;
2291
2292	/* Flush the FDB table */
2293	ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2294	if (ret < 0)
2295		return ret;
2296
2297	return 0;
2298}
2299
2300static bool
2301mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
2302			  const struct phylink_link_state *state)
2303{
2304	struct mt7530_priv *priv = ds->priv;
2305
2306	switch (port) {
2307	case 0 ... 4: /* Internal phy */
2308		if (state->interface != PHY_INTERFACE_MODE_GMII)
2309			return false;
2310		break;
2311	case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2312		if (!phy_interface_mode_is_rgmii(state->interface) &&
2313		    state->interface != PHY_INTERFACE_MODE_MII &&
2314		    state->interface != PHY_INTERFACE_MODE_GMII)
2315			return false;
2316		break;
2317	case 6: /* 1st cpu port */
2318		if (state->interface != PHY_INTERFACE_MODE_RGMII &&
2319		    state->interface != PHY_INTERFACE_MODE_TRGMII)
2320			return false;
2321		break;
2322	default:
2323		dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2324			port);
2325		return false;
2326	}
2327
2328	return true;
2329}
2330
2331static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
2332{
2333	return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
2334}
2335
2336static bool
2337mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
2338			  const struct phylink_link_state *state)
2339{
2340	struct mt7530_priv *priv = ds->priv;
2341
2342	switch (port) {
2343	case 0 ... 4: /* Internal phy */
2344		if (state->interface != PHY_INTERFACE_MODE_GMII)
2345			return false;
2346		break;
2347	case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
2348		if (mt7531_is_rgmii_port(priv, port))
2349			return phy_interface_mode_is_rgmii(state->interface);
2350		fallthrough;
2351	case 6: /* 1st cpu port supports sgmii/8023z only */
2352		if (state->interface != PHY_INTERFACE_MODE_SGMII &&
2353		    !phy_interface_mode_is_8023z(state->interface))
2354			return false;
2355		break;
2356	default:
2357		dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2358			port);
2359		return false;
2360	}
2361
2362	return true;
2363}
2364
2365static bool
2366mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
2367			  const struct phylink_link_state *state)
2368{
2369	struct mt7530_priv *priv = ds->priv;
2370
2371	return priv->info->phy_mode_supported(ds, port, state);
2372}
2373
2374static int
2375mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2376{
2377	struct mt7530_priv *priv = ds->priv;
2378
2379	return priv->info->pad_setup(ds, state->interface);
2380}
2381
2382static int
2383mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2384		  phy_interface_t interface)
2385{
2386	struct mt7530_priv *priv = ds->priv;
2387
2388	/* Only need to setup port5. */
2389	if (port != 5)
2390		return 0;
2391
2392	mt7530_setup_port5(priv->ds, interface);
2393
2394	return 0;
2395}
2396
2397static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2398			      phy_interface_t interface,
2399			      struct phy_device *phydev)
2400{
2401	u32 val;
2402
2403	if (!mt7531_is_rgmii_port(priv, port)) {
2404		dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2405			port);
2406		return -EINVAL;
2407	}
2408
2409	val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2410	val |= GP_CLK_EN;
2411	val &= ~GP_MODE_MASK;
2412	val |= GP_MODE(MT7531_GP_MODE_RGMII);
2413	val &= ~CLK_SKEW_IN_MASK;
2414	val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2415	val &= ~CLK_SKEW_OUT_MASK;
2416	val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2417	val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2418
2419	/* Do not adjust rgmii delay when vendor phy driver presents. */
2420	if (!phydev || phy_driver_is_genphy(phydev)) {
2421		val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2422		switch (interface) {
2423		case PHY_INTERFACE_MODE_RGMII:
2424			val |= TXCLK_NO_REVERSE;
2425			val |= RXCLK_NO_DELAY;
2426			break;
2427		case PHY_INTERFACE_MODE_RGMII_RXID:
2428			val |= TXCLK_NO_REVERSE;
2429			break;
2430		case PHY_INTERFACE_MODE_RGMII_TXID:
2431			val |= RXCLK_NO_DELAY;
2432			break;
2433		case PHY_INTERFACE_MODE_RGMII_ID:
2434			break;
2435		default:
2436			return -EINVAL;
2437		}
2438	}
2439	mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2440
2441	return 0;
2442}
2443
2444static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
2445				  unsigned long *supported)
2446{
2447	/* Port5 supports ethier RGMII or SGMII.
2448	 * Port6 supports SGMII only.
2449	 */
2450	switch (port) {
2451	case 5:
2452		if (mt7531_is_rgmii_port(priv, port))
2453			break;
2454		fallthrough;
2455	case 6:
2456		phylink_set(supported, 1000baseX_Full);
2457		phylink_set(supported, 2500baseX_Full);
2458		phylink_set(supported, 2500baseT_Full);
2459	}
2460}
2461
2462static void
2463mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
2464			   unsigned int mode, phy_interface_t interface,
2465			   int speed, int duplex)
2466{
2467	struct mt7530_priv *priv = ds->priv;
2468	unsigned int val;
2469
2470	/* For adjusting speed and duplex of SGMII force mode. */
2471	if (interface != PHY_INTERFACE_MODE_SGMII ||
2472	    phylink_autoneg_inband(mode))
2473		return;
2474
2475	/* SGMII force mode setting */
2476	val = mt7530_read(priv, MT7531_SGMII_MODE(port));
2477	val &= ~MT7531_SGMII_IF_MODE_MASK;
2478
2479	switch (speed) {
2480	case SPEED_10:
2481		val |= MT7531_SGMII_FORCE_SPEED_10;
2482		break;
2483	case SPEED_100:
2484		val |= MT7531_SGMII_FORCE_SPEED_100;
2485		break;
2486	case SPEED_1000:
2487		val |= MT7531_SGMII_FORCE_SPEED_1000;
2488		break;
2489	}
2490
2491	/* MT7531 SGMII 1G force mode can only work in full duplex mode,
2492	 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2493	 */
2494	if ((speed == SPEED_10 || speed == SPEED_100) &&
2495	    duplex != DUPLEX_FULL)
2496		val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2497
2498	mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2499}
2500
2501static bool mt753x_is_mac_port(u32 port)
2502{
2503	return (port == 5 || port == 6);
2504}
2505
2506static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2507					 phy_interface_t interface)
2508{
2509	u32 val;
2510
2511	if (!mt753x_is_mac_port(port))
2512		return -EINVAL;
2513
2514	mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2515		   MT7531_SGMII_PHYA_PWD);
2516
2517	val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2518	val &= ~MT7531_RG_TPHY_SPEED_MASK;
2519	/* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2520	 * encoding.
2521	 */
2522	val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2523		MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2524	mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2525
2526	mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2527
2528	/* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2529	 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2530	 */
2531	mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2532		   MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2533		   MT7531_SGMII_FORCE_SPEED_1000);
2534
2535	mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2536
2537	return 0;
2538}
2539
2540static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2541				      phy_interface_t interface)
2542{
2543	if (!mt753x_is_mac_port(port))
2544		return -EINVAL;
2545
2546	mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2547		   MT7531_SGMII_PHYA_PWD);
2548
2549	mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2550		   MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2551
2552	mt7530_set(priv, MT7531_SGMII_MODE(port),
2553		   MT7531_SGMII_REMOTE_FAULT_DIS |
2554		   MT7531_SGMII_SPEED_DUPLEX_AN);
2555
2556	mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2557		   MT7531_SGMII_TX_CONFIG_MASK, 1);
2558
2559	mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2560
2561	mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2562
2563	mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2564
2565	return 0;
2566}
2567
2568static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
2569{
2570	struct mt7530_priv *priv = ds->priv;
2571	u32 val;
2572
2573	/* Only restart AN when AN is enabled */
2574	val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2575	if (val & MT7531_SGMII_AN_ENABLE) {
2576		val |= MT7531_SGMII_AN_RESTART;
2577		mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2578	}
2579}
2580
2581static int
2582mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2583		  phy_interface_t interface)
2584{
2585	struct mt7530_priv *priv = ds->priv;
2586	struct phy_device *phydev;
2587	struct dsa_port *dp;
2588
2589	if (!mt753x_is_mac_port(port)) {
2590		dev_err(priv->dev, "port %d is not a MAC port\n", port);
2591		return -EINVAL;
2592	}
2593
2594	switch (interface) {
2595	case PHY_INTERFACE_MODE_RGMII:
2596	case PHY_INTERFACE_MODE_RGMII_ID:
2597	case PHY_INTERFACE_MODE_RGMII_RXID:
2598	case PHY_INTERFACE_MODE_RGMII_TXID:
2599		dp = dsa_to_port(ds, port);
2600		phydev = dp->slave->phydev;
2601		return mt7531_rgmii_setup(priv, port, interface, phydev);
2602	case PHY_INTERFACE_MODE_SGMII:
2603		return mt7531_sgmii_setup_mode_an(priv, port, interface);
2604	case PHY_INTERFACE_MODE_NA:
2605	case PHY_INTERFACE_MODE_1000BASEX:
2606	case PHY_INTERFACE_MODE_2500BASEX:
2607		if (phylink_autoneg_inband(mode))
2608			return -EINVAL;
2609
2610		return mt7531_sgmii_setup_mode_force(priv, port, interface);
2611	default:
2612		return -EINVAL;
2613	}
2614
2615	return -EINVAL;
2616}
2617
2618static int
2619mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2620		  const struct phylink_link_state *state)
2621{
2622	struct mt7530_priv *priv = ds->priv;
2623
2624	return priv->info->mac_port_config(ds, port, mode, state->interface);
2625}
2626
2627static void
2628mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2629			  const struct phylink_link_state *state)
2630{
2631	struct mt7530_priv *priv = ds->priv;
2632	u32 mcr_cur, mcr_new;
2633
2634	if (!mt753x_phy_mode_supported(ds, port, state))
2635		goto unsupported;
2636
2637	switch (port) {
2638	case 0 ... 4: /* Internal phy */
2639		if (state->interface != PHY_INTERFACE_MODE_GMII)
2640			goto unsupported;
2641		break;
2642	case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2643		if (priv->p5_interface == state->interface)
2644			break;
2645
2646		if (mt753x_mac_config(ds, port, mode, state) < 0)
2647			goto unsupported;
2648
2649		if (priv->p5_intf_sel != P5_DISABLED)
2650			priv->p5_interface = state->interface;
2651		break;
2652	case 6: /* 1st cpu port */
2653		if (priv->p6_interface == state->interface)
2654			break;
2655
2656		mt753x_pad_setup(ds, state);
2657
2658		if (mt753x_mac_config(ds, port, mode, state) < 0)
2659			goto unsupported;
2660
2661		priv->p6_interface = state->interface;
2662		break;
2663	default:
2664unsupported:
2665		dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2666			__func__, phy_modes(state->interface), port);
2667		return;
2668	}
2669
2670	if (phylink_autoneg_inband(mode) &&
2671	    state->interface != PHY_INTERFACE_MODE_SGMII) {
2672		dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
2673			__func__);
2674		return;
2675	}
2676
2677	mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2678	mcr_new = mcr_cur;
2679	mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
2680	mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
2681		   PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
2682
2683	/* Are we connected to external phy */
2684	if (port == 5 && dsa_is_user_port(ds, 5))
2685		mcr_new |= PMCR_EXT_PHY;
2686
2687	if (mcr_new != mcr_cur)
2688		mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2689}
2690
2691static void
2692mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
2693{
2694	struct mt7530_priv *priv = ds->priv;
2695
2696	if (!priv->info->mac_pcs_an_restart)
2697		return;
2698
2699	priv->info->mac_pcs_an_restart(ds, port);
2700}
2701
2702static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
2703					 unsigned int mode,
2704					 phy_interface_t interface)
2705{
2706	struct mt7530_priv *priv = ds->priv;
2707
2708	mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
2709}
2710
2711static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
2712				   unsigned int mode, phy_interface_t interface,
2713				   int speed, int duplex)
2714{
2715	struct mt7530_priv *priv = ds->priv;
2716
2717	if (!priv->info->mac_pcs_link_up)
2718		return;
2719
2720	priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2721}
2722
2723static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
2724				       unsigned int mode,
2725				       phy_interface_t interface,
2726				       struct phy_device *phydev,
2727				       int speed, int duplex,
2728				       bool tx_pause, bool rx_pause)
2729{
2730	struct mt7530_priv *priv = ds->priv;
2731	u32 mcr;
2732
2733	mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2734
2735	mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2736
2737	/* MT753x MAC works in 1G full duplex mode for all up-clocked
2738	 * variants.
2739	 */
2740	if (interface == PHY_INTERFACE_MODE_TRGMII ||
2741	    (phy_interface_mode_is_8023z(interface))) {
2742		speed = SPEED_1000;
2743		duplex = DUPLEX_FULL;
2744	}
2745
2746	switch (speed) {
2747	case SPEED_1000:
2748		mcr |= PMCR_FORCE_SPEED_1000;
2749		break;
2750	case SPEED_100:
2751		mcr |= PMCR_FORCE_SPEED_100;
2752		break;
2753	}
2754	if (duplex == DUPLEX_FULL) {
2755		mcr |= PMCR_FORCE_FDX;
2756		if (tx_pause)
2757			mcr |= PMCR_TX_FC_EN;
2758		if (rx_pause)
2759			mcr |= PMCR_RX_FC_EN;
2760	}
2761
2762	if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) {
2763		switch (speed) {
2764		case SPEED_1000:
2765			mcr |= PMCR_FORCE_EEE1G;
2766			break;
2767		case SPEED_100:
2768			mcr |= PMCR_FORCE_EEE100;
2769			break;
2770		}
2771	}
2772
2773	mt7530_set(priv, MT7530_PMCR_P(port), mcr);
2774}
2775
2776static int
2777mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2778{
2779	struct mt7530_priv *priv = ds->priv;
2780	phy_interface_t interface;
2781	int speed;
2782	int ret;
2783
2784	switch (port) {
2785	case 5:
2786		if (mt7531_is_rgmii_port(priv, port))
2787			interface = PHY_INTERFACE_MODE_RGMII;
2788		else
2789			interface = PHY_INTERFACE_MODE_2500BASEX;
2790
2791		priv->p5_interface = interface;
2792		break;
2793	case 6:
2794		interface = PHY_INTERFACE_MODE_2500BASEX;
2795
2796		mt7531_pad_setup(ds, interface);
2797
2798		priv->p6_interface = interface;
2799		break;
2800	default:
2801		return -EINVAL;
2802	}
2803
2804	if (interface == PHY_INTERFACE_MODE_2500BASEX)
2805		speed = SPEED_2500;
2806	else
2807		speed = SPEED_1000;
2808
2809	ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2810	if (ret)
2811		return ret;
2812	mt7530_write(priv, MT7530_PMCR_P(port),
2813		     PMCR_CPU_PORT_SETTING(priv->id));
2814	mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2815				   speed, DUPLEX_FULL, true, true);
2816
2817	return 0;
2818}
2819
2820static void
2821mt7530_mac_port_validate(struct dsa_switch *ds, int port,
2822			 unsigned long *supported)
2823{
2824	if (port == 5)
2825		phylink_set(supported, 1000baseX_Full);
2826}
2827
2828static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
2829				     unsigned long *supported)
2830{
2831	struct mt7530_priv *priv = ds->priv;
2832
2833	mt7531_sgmii_validate(priv, port, supported);
2834}
2835
2836static void
2837mt753x_phylink_validate(struct dsa_switch *ds, int port,
2838			unsigned long *supported,
2839			struct phylink_link_state *state)
2840{
2841	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
2842	struct mt7530_priv *priv = ds->priv;
2843
2844	if (state->interface != PHY_INTERFACE_MODE_NA &&
2845	    !mt753x_phy_mode_supported(ds, port, state)) {
2846		linkmode_zero(supported);
2847		return;
2848	}
2849
2850	phylink_set_port_modes(mask);
2851
2852	if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
2853	    !phy_interface_mode_is_8023z(state->interface)) {
2854		phylink_set(mask, 10baseT_Half);
2855		phylink_set(mask, 10baseT_Full);
2856		phylink_set(mask, 100baseT_Half);
2857		phylink_set(mask, 100baseT_Full);
2858		phylink_set(mask, Autoneg);
2859	}
2860
2861	/* This switch only supports 1G full-duplex. */
2862	if (state->interface != PHY_INTERFACE_MODE_MII)
2863		phylink_set(mask, 1000baseT_Full);
2864
2865	priv->info->mac_port_validate(ds, port, mask);
2866
2867	phylink_set(mask, Pause);
2868	phylink_set(mask, Asym_Pause);
2869
2870	linkmode_and(supported, supported, mask);
2871	linkmode_and(state->advertising, state->advertising, mask);
2872
2873	/* We can only operate at 2500BaseX or 1000BaseX.  If requested
2874	 * to advertise both, only report advertising at 2500BaseX.
2875	 */
2876	phylink_helper_basex_speed(state);
2877}
2878
2879static int
2880mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
2881			      struct phylink_link_state *state)
2882{
2883	struct mt7530_priv *priv = ds->priv;
2884	u32 pmsr;
2885
2886	if (port < 0 || port >= MT7530_NUM_PORTS)
2887		return -EINVAL;
2888
2889	pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2890
2891	state->link = (pmsr & PMSR_LINK);
2892	state->an_complete = state->link;
2893	state->duplex = !!(pmsr & PMSR_DPX);
2894
2895	switch (pmsr & PMSR_SPEED_MASK) {
2896	case PMSR_SPEED_10:
2897		state->speed = SPEED_10;
2898		break;
2899	case PMSR_SPEED_100:
2900		state->speed = SPEED_100;
2901		break;
2902	case PMSR_SPEED_1000:
2903		state->speed = SPEED_1000;
2904		break;
2905	default:
2906		state->speed = SPEED_UNKNOWN;
2907		break;
2908	}
2909
2910	state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2911	if (pmsr & PMSR_RX_FC)
2912		state->pause |= MLO_PAUSE_RX;
2913	if (pmsr & PMSR_TX_FC)
2914		state->pause |= MLO_PAUSE_TX;
2915
2916	return 1;
2917}
2918
2919static int
2920mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
2921			      struct phylink_link_state *state)
2922{
2923	u32 status, val;
2924	u16 config_reg;
2925
2926	status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2927	state->link = !!(status & MT7531_SGMII_LINK_STATUS);
2928	if (state->interface == PHY_INTERFACE_MODE_SGMII &&
2929	    (status & MT7531_SGMII_AN_ENABLE)) {
2930		val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
2931		config_reg = val >> 16;
2932
2933		switch (config_reg & LPA_SGMII_SPD_MASK) {
2934		case LPA_SGMII_1000:
2935			state->speed = SPEED_1000;
2936			break;
2937		case LPA_SGMII_100:
2938			state->speed = SPEED_100;
2939			break;
2940		case LPA_SGMII_10:
2941			state->speed = SPEED_10;
2942			break;
2943		default:
2944			dev_err(priv->dev, "invalid sgmii PHY speed\n");
2945			state->link = false;
2946			return -EINVAL;
2947		}
2948
2949		if (config_reg & LPA_SGMII_FULL_DUPLEX)
2950			state->duplex = DUPLEX_FULL;
2951		else
2952			state->duplex = DUPLEX_HALF;
2953	}
2954
2955	return 0;
2956}
2957
2958static int
2959mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
2960			      struct phylink_link_state *state)
2961{
2962	struct mt7530_priv *priv = ds->priv;
2963
2964	if (state->interface == PHY_INTERFACE_MODE_SGMII)
2965		return mt7531_sgmii_pcs_get_state_an(priv, port, state);
2966
2967	return -EOPNOTSUPP;
2968}
2969
2970static int
2971mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
2972			      struct phylink_link_state *state)
2973{
2974	struct mt7530_priv *priv = ds->priv;
2975
2976	return priv->info->mac_port_get_state(ds, port, state);
2977}
2978
2979static int
2980mt753x_setup(struct dsa_switch *ds)
2981{
2982	struct mt7530_priv *priv = ds->priv;
2983	int ret = priv->info->sw_setup(ds);
2984
2985	if (ret)
2986		return ret;
2987
2988	ret = mt7530_setup_irq(priv);
2989	if (ret)
2990		return ret;
2991
2992	ret = mt7530_setup_mdio(priv);
2993	if (ret && priv->irq)
2994		mt7530_free_irq_common(priv);
2995
2996	return ret;
2997}
2998
2999static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,
3000			      struct ethtool_eee *e)
3001{
3002	struct mt7530_priv *priv = ds->priv;
3003	u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
3004
3005	e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
3006	e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
3007
3008	return 0;
3009}
3010
3011static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
3012			      struct ethtool_eee *e)
3013{
3014	struct mt7530_priv *priv = ds->priv;
3015	u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;
3016
3017	if (e->tx_lpi_timer > 0xFFF)
3018		return -EINVAL;
3019
3020	set = SET_LPI_THRESH(e->tx_lpi_timer);
3021	if (!e->tx_lpi_enabled)
3022		/* Force LPI Mode without a delay */
3023		set |= LPI_MODE_EN;
3024	mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
3025
3026	return 0;
3027}
3028
3029static const struct dsa_switch_ops mt7530_switch_ops = {
3030	.get_tag_protocol	= mtk_get_tag_protocol,
3031	.setup			= mt753x_setup,
3032	.get_strings		= mt7530_get_strings,
3033	.get_ethtool_stats	= mt7530_get_ethtool_stats,
3034	.get_sset_count		= mt7530_get_sset_count,
3035	.set_ageing_time	= mt7530_set_ageing_time,
3036	.port_enable		= mt7530_port_enable,
3037	.port_disable		= mt7530_port_disable,
3038	.port_change_mtu	= mt7530_port_change_mtu,
3039	.port_max_mtu		= mt7530_port_max_mtu,
3040	.port_stp_state_set	= mt7530_stp_state_set,
3041	.port_pre_bridge_flags	= mt7530_port_pre_bridge_flags,
3042	.port_bridge_flags	= mt7530_port_bridge_flags,
3043	.port_bridge_join	= mt7530_port_bridge_join,
3044	.port_bridge_leave	= mt7530_port_bridge_leave,
3045	.port_fdb_add		= mt7530_port_fdb_add,
3046	.port_fdb_del		= mt7530_port_fdb_del,
3047	.port_fdb_dump		= mt7530_port_fdb_dump,
3048	.port_mdb_add		= mt7530_port_mdb_add,
3049	.port_mdb_del		= mt7530_port_mdb_del,
3050	.port_vlan_filtering	= mt7530_port_vlan_filtering,
3051	.port_vlan_add		= mt7530_port_vlan_add,
3052	.port_vlan_del		= mt7530_port_vlan_del,
3053	.port_mirror_add	= mt753x_port_mirror_add,
3054	.port_mirror_del	= mt753x_port_mirror_del,
3055	.phylink_validate	= mt753x_phylink_validate,
3056	.phylink_mac_link_state	= mt753x_phylink_mac_link_state,
3057	.phylink_mac_config	= mt753x_phylink_mac_config,
3058	.phylink_mac_an_restart	= mt753x_phylink_mac_an_restart,
3059	.phylink_mac_link_down	= mt753x_phylink_mac_link_down,
3060	.phylink_mac_link_up	= mt753x_phylink_mac_link_up,
3061	.get_mac_eee		= mt753x_get_mac_eee,
3062	.set_mac_eee		= mt753x_set_mac_eee,
3063};
3064
3065static const struct mt753x_info mt753x_table[] = {
3066	[ID_MT7621] = {
3067		.id = ID_MT7621,
3068		.sw_setup = mt7530_setup,
3069		.phy_read = mt7530_phy_read,
3070		.phy_write = mt7530_phy_write,
3071		.pad_setup = mt7530_pad_clk_setup,
3072		.phy_mode_supported = mt7530_phy_mode_supported,
3073		.mac_port_validate = mt7530_mac_port_validate,
3074		.mac_port_get_state = mt7530_phylink_mac_link_state,
3075		.mac_port_config = mt7530_mac_config,
3076	},
3077	[ID_MT7530] = {
3078		.id = ID_MT7530,
3079		.sw_setup = mt7530_setup,
3080		.phy_read = mt7530_phy_read,
3081		.phy_write = mt7530_phy_write,
3082		.pad_setup = mt7530_pad_clk_setup,
3083		.phy_mode_supported = mt7530_phy_mode_supported,
3084		.mac_port_validate = mt7530_mac_port_validate,
3085		.mac_port_get_state = mt7530_phylink_mac_link_state,
3086		.mac_port_config = mt7530_mac_config,
3087	},
3088	[ID_MT7531] = {
3089		.id = ID_MT7531,
3090		.sw_setup = mt7531_setup,
3091		.phy_read = mt7531_ind_phy_read,
3092		.phy_write = mt7531_ind_phy_write,
3093		.pad_setup = mt7531_pad_setup,
3094		.cpu_port_config = mt7531_cpu_port_config,
3095		.phy_mode_supported = mt7531_phy_mode_supported,
3096		.mac_port_validate = mt7531_mac_port_validate,
3097		.mac_port_get_state = mt7531_phylink_mac_link_state,
3098		.mac_port_config = mt7531_mac_config,
3099		.mac_pcs_an_restart = mt7531_sgmii_restart_an,
3100		.mac_pcs_link_up = mt7531_sgmii_link_up_force,
3101	},
3102};
3103
3104static const struct of_device_id mt7530_of_match[] = {
3105	{ .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
3106	{ .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
3107	{ .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
3108	{ /* sentinel */ },
3109};
3110MODULE_DEVICE_TABLE(of, mt7530_of_match);
3111
3112static int
3113mt7530_probe(struct mdio_device *mdiodev)
3114{
3115	struct mt7530_priv *priv;
3116	struct device_node *dn;
3117
3118	dn = mdiodev->dev.of_node;
3119
3120	priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
3121	if (!priv)
3122		return -ENOMEM;
3123
3124	priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
3125	if (!priv->ds)
3126		return -ENOMEM;
3127
3128	priv->ds->dev = &mdiodev->dev;
3129	priv->ds->num_ports = MT7530_NUM_PORTS;
3130
3131	/* Use medatek,mcm property to distinguish hardware type that would
3132	 * casues a little bit differences on power-on sequence.
3133	 */
3134	priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
3135	if (priv->mcm) {
3136		dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
3137
3138		priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
3139		if (IS_ERR(priv->rstc)) {
3140			dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3141			return PTR_ERR(priv->rstc);
3142		}
3143	}
3144
3145	/* Get the hardware identifier from the devicetree node.
3146	 * We will need it for some of the clock and regulator setup.
3147	 */
3148	priv->info = of_device_get_match_data(&mdiodev->dev);
3149	if (!priv->info)
3150		return -EINVAL;
3151
3152	/* Sanity check if these required device operations are filled
3153	 * properly.
3154	 */
3155	if (!priv->info->sw_setup || !priv->info->pad_setup ||
3156	    !priv->info->phy_read || !priv->info->phy_write ||
3157	    !priv->info->phy_mode_supported ||
3158	    !priv->info->mac_port_validate ||
3159	    !priv->info->mac_port_get_state || !priv->info->mac_port_config)
3160		return -EINVAL;
3161
3162	priv->id = priv->info->id;
3163
3164	if (priv->id == ID_MT7530) {
3165		priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
3166		if (IS_ERR(priv->core_pwr))
3167			return PTR_ERR(priv->core_pwr);
3168
3169		priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
3170		if (IS_ERR(priv->io_pwr))
3171			return PTR_ERR(priv->io_pwr);
3172	}
3173
3174	/* Not MCM that indicates switch works as the remote standalone
3175	 * integrated circuit so the GPIO pin would be used to complete
3176	 * the reset, otherwise memory-mapped register accessing used
3177	 * through syscon provides in the case of MCM.
3178	 */
3179	if (!priv->mcm) {
3180		priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
3181						      GPIOD_OUT_LOW);
3182		if (IS_ERR(priv->reset)) {
3183			dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3184			return PTR_ERR(priv->reset);
3185		}
3186	}
3187
3188	priv->bus = mdiodev->bus;
3189	priv->dev = &mdiodev->dev;
3190	priv->ds->priv = priv;
3191	priv->ds->ops = &mt7530_switch_ops;
3192	mutex_init(&priv->reg_mutex);
3193	dev_set_drvdata(&mdiodev->dev, priv);
3194
3195	return dsa_register_switch(priv->ds);
3196}
3197
3198static void
3199mt7530_remove(struct mdio_device *mdiodev)
3200{
3201	struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3202	int ret = 0;
3203
3204	ret = regulator_disable(priv->core_pwr);
3205	if (ret < 0)
3206		dev_err(priv->dev,
3207			"Failed to disable core power: %d\n", ret);
3208
3209	ret = regulator_disable(priv->io_pwr);
3210	if (ret < 0)
3211		dev_err(priv->dev, "Failed to disable io pwr: %d\n",
3212			ret);
3213
3214	if (priv->irq)
3215		mt7530_free_irq(priv);
3216
3217	dsa_unregister_switch(priv->ds);
3218	mutex_destroy(&priv->reg_mutex);
3219}
3220
3221static struct mdio_driver mt7530_mdio_driver = {
3222	.probe  = mt7530_probe,
3223	.remove = mt7530_remove,
3224	.mdiodrv.driver = {
3225		.name = "mt7530",
3226		.of_match_table = mt7530_of_match,
3227	},
3228};
3229
3230mdio_module_driver(mt7530_mdio_driver);
3231
3232MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
3233MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
3234MODULE_LICENSE("GPL");