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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/irq.h>
25#include <linux/log2.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/slab.h>
29
30#include "xhci.h"
31
32#define DRIVER_AUTHOR "Sarah Sharp"
33#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
34
35/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
36static int link_quirk;
37module_param(link_quirk, int, S_IRUGO | S_IWUSR);
38MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
39
40/* TODO: copied from ehci-hcd.c - can this be refactored? */
41/*
42 * handshake - spin reading hc until handshake completes or fails
43 * @ptr: address of hc register to be read
44 * @mask: bits to look at in result of read
45 * @done: value of those bits when handshake succeeds
46 * @usec: timeout in microseconds
47 *
48 * Returns negative errno, or zero on success
49 *
50 * Success happens when the "mask" bits have the specified value (hardware
51 * handshake done). There are two failure modes: "usec" have passed (major
52 * hardware flakeout), or the register reads as all-ones (hardware removed).
53 */
54static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
55 u32 mask, u32 done, int usec)
56{
57 u32 result;
58
59 do {
60 result = xhci_readl(xhci, ptr);
61 if (result == ~(u32)0) /* card removed */
62 return -ENODEV;
63 result &= mask;
64 if (result == done)
65 return 0;
66 udelay(1);
67 usec--;
68 } while (usec > 0);
69 return -ETIMEDOUT;
70}
71
72/*
73 * Disable interrupts and begin the xHCI halting process.
74 */
75void xhci_quiesce(struct xhci_hcd *xhci)
76{
77 u32 halted;
78 u32 cmd;
79 u32 mask;
80
81 mask = ~(XHCI_IRQS);
82 halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
83 if (!halted)
84 mask &= ~CMD_RUN;
85
86 cmd = xhci_readl(xhci, &xhci->op_regs->command);
87 cmd &= mask;
88 xhci_writel(xhci, cmd, &xhci->op_regs->command);
89}
90
91/*
92 * Force HC into halt state.
93 *
94 * Disable any IRQs and clear the run/stop bit.
95 * HC will complete any current and actively pipelined transactions, and
96 * should halt within 16 ms of the run/stop bit being cleared.
97 * Read HC Halted bit in the status register to see when the HC is finished.
98 */
99int xhci_halt(struct xhci_hcd *xhci)
100{
101 int ret;
102 xhci_dbg(xhci, "// Halt the HC\n");
103 xhci_quiesce(xhci);
104
105 ret = handshake(xhci, &xhci->op_regs->status,
106 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
107 if (!ret)
108 xhci->xhc_state |= XHCI_STATE_HALTED;
109 return ret;
110}
111
112/*
113 * Set the run bit and wait for the host to be running.
114 */
115static int xhci_start(struct xhci_hcd *xhci)
116{
117 u32 temp;
118 int ret;
119
120 temp = xhci_readl(xhci, &xhci->op_regs->command);
121 temp |= (CMD_RUN);
122 xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
123 temp);
124 xhci_writel(xhci, temp, &xhci->op_regs->command);
125
126 /*
127 * Wait for the HCHalted Status bit to be 0 to indicate the host is
128 * running.
129 */
130 ret = handshake(xhci, &xhci->op_regs->status,
131 STS_HALT, 0, XHCI_MAX_HALT_USEC);
132 if (ret == -ETIMEDOUT)
133 xhci_err(xhci, "Host took too long to start, "
134 "waited %u microseconds.\n",
135 XHCI_MAX_HALT_USEC);
136 if (!ret)
137 xhci->xhc_state &= ~XHCI_STATE_HALTED;
138 return ret;
139}
140
141/*
142 * Reset a halted HC.
143 *
144 * This resets pipelines, timers, counters, state machines, etc.
145 * Transactions will be terminated immediately, and operational registers
146 * will be set to their defaults.
147 */
148int xhci_reset(struct xhci_hcd *xhci)
149{
150 u32 command;
151 u32 state;
152 int ret;
153
154 state = xhci_readl(xhci, &xhci->op_regs->status);
155 if ((state & STS_HALT) == 0) {
156 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
157 return 0;
158 }
159
160 xhci_dbg(xhci, "// Reset the HC\n");
161 command = xhci_readl(xhci, &xhci->op_regs->command);
162 command |= CMD_RESET;
163 xhci_writel(xhci, command, &xhci->op_regs->command);
164
165 ret = handshake(xhci, &xhci->op_regs->command,
166 CMD_RESET, 0, 250 * 1000);
167 if (ret)
168 return ret;
169
170 xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
171 /*
172 * xHCI cannot write to any doorbells or operational registers other
173 * than status until the "Controller Not Ready" flag is cleared.
174 */
175 return handshake(xhci, &xhci->op_regs->status, STS_CNR, 0, 250 * 1000);
176}
177
178/*
179 * Free IRQs
180 * free all IRQs request
181 */
182static void xhci_free_irq(struct xhci_hcd *xhci)
183{
184 int i;
185 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
186
187 /* return if using legacy interrupt */
188 if (xhci_to_hcd(xhci)->irq >= 0)
189 return;
190
191 if (xhci->msix_entries) {
192 for (i = 0; i < xhci->msix_count; i++)
193 if (xhci->msix_entries[i].vector)
194 free_irq(xhci->msix_entries[i].vector,
195 xhci_to_hcd(xhci));
196 } else if (pdev->irq >= 0)
197 free_irq(pdev->irq, xhci_to_hcd(xhci));
198
199 return;
200}
201
202/*
203 * Set up MSI
204 */
205static int xhci_setup_msi(struct xhci_hcd *xhci)
206{
207 int ret;
208 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
209
210 ret = pci_enable_msi(pdev);
211 if (ret) {
212 xhci_err(xhci, "failed to allocate MSI entry\n");
213 return ret;
214 }
215
216 ret = request_irq(pdev->irq, (irq_handler_t)xhci_msi_irq,
217 0, "xhci_hcd", xhci_to_hcd(xhci));
218 if (ret) {
219 xhci_err(xhci, "disable MSI interrupt\n");
220 pci_disable_msi(pdev);
221 }
222
223 return ret;
224}
225
226/*
227 * Set up MSI-X
228 */
229static int xhci_setup_msix(struct xhci_hcd *xhci)
230{
231 int i, ret = 0;
232 struct usb_hcd *hcd = xhci_to_hcd(xhci);
233 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
234
235 /*
236 * calculate number of msi-x vectors supported.
237 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
238 * with max number of interrupters based on the xhci HCSPARAMS1.
239 * - num_online_cpus: maximum msi-x vectors per CPUs core.
240 * Add additional 1 vector to ensure always available interrupt.
241 */
242 xhci->msix_count = min(num_online_cpus() + 1,
243 HCS_MAX_INTRS(xhci->hcs_params1));
244
245 xhci->msix_entries =
246 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
247 GFP_KERNEL);
248 if (!xhci->msix_entries) {
249 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
250 return -ENOMEM;
251 }
252
253 for (i = 0; i < xhci->msix_count; i++) {
254 xhci->msix_entries[i].entry = i;
255 xhci->msix_entries[i].vector = 0;
256 }
257
258 ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
259 if (ret) {
260 xhci_err(xhci, "Failed to enable MSI-X\n");
261 goto free_entries;
262 }
263
264 for (i = 0; i < xhci->msix_count; i++) {
265 ret = request_irq(xhci->msix_entries[i].vector,
266 (irq_handler_t)xhci_msi_irq,
267 0, "xhci_hcd", xhci_to_hcd(xhci));
268 if (ret)
269 goto disable_msix;
270 }
271
272 hcd->msix_enabled = 1;
273 return ret;
274
275disable_msix:
276 xhci_err(xhci, "disable MSI-X interrupt\n");
277 xhci_free_irq(xhci);
278 pci_disable_msix(pdev);
279free_entries:
280 kfree(xhci->msix_entries);
281 xhci->msix_entries = NULL;
282 return ret;
283}
284
285/* Free any IRQs and disable MSI-X */
286static void xhci_cleanup_msix(struct xhci_hcd *xhci)
287{
288 struct usb_hcd *hcd = xhci_to_hcd(xhci);
289 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
290
291 xhci_free_irq(xhci);
292
293 if (xhci->msix_entries) {
294 pci_disable_msix(pdev);
295 kfree(xhci->msix_entries);
296 xhci->msix_entries = NULL;
297 } else {
298 pci_disable_msi(pdev);
299 }
300
301 hcd->msix_enabled = 0;
302 return;
303}
304
305/*
306 * Initialize memory for HCD and xHC (one-time init).
307 *
308 * Program the PAGESIZE register, initialize the device context array, create
309 * device contexts (?), set up a command ring segment (or two?), create event
310 * ring (one for now).
311 */
312int xhci_init(struct usb_hcd *hcd)
313{
314 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
315 int retval = 0;
316
317 xhci_dbg(xhci, "xhci_init\n");
318 spin_lock_init(&xhci->lock);
319 if (link_quirk) {
320 xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
321 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
322 } else {
323 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
324 }
325 retval = xhci_mem_init(xhci, GFP_KERNEL);
326 xhci_dbg(xhci, "Finished xhci_init\n");
327
328 return retval;
329}
330
331/*-------------------------------------------------------------------------*/
332
333
334#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
335static void xhci_event_ring_work(unsigned long arg)
336{
337 unsigned long flags;
338 int temp;
339 u64 temp_64;
340 struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
341 int i, j;
342
343 xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
344
345 spin_lock_irqsave(&xhci->lock, flags);
346 temp = xhci_readl(xhci, &xhci->op_regs->status);
347 xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
348 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
349 (xhci->xhc_state & XHCI_STATE_HALTED)) {
350 xhci_dbg(xhci, "HW died, polling stopped.\n");
351 spin_unlock_irqrestore(&xhci->lock, flags);
352 return;
353 }
354
355 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
356 xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
357 xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
358 xhci->error_bitmask = 0;
359 xhci_dbg(xhci, "Event ring:\n");
360 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
361 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
362 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
363 temp_64 &= ~ERST_PTR_MASK;
364 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
365 xhci_dbg(xhci, "Command ring:\n");
366 xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
367 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
368 xhci_dbg_cmd_ptrs(xhci);
369 for (i = 0; i < MAX_HC_SLOTS; ++i) {
370 if (!xhci->devs[i])
371 continue;
372 for (j = 0; j < 31; ++j) {
373 xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
374 }
375 }
376 spin_unlock_irqrestore(&xhci->lock, flags);
377
378 if (!xhci->zombie)
379 mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
380 else
381 xhci_dbg(xhci, "Quit polling the event ring.\n");
382}
383#endif
384
385static int xhci_run_finished(struct xhci_hcd *xhci)
386{
387 if (xhci_start(xhci)) {
388 xhci_halt(xhci);
389 return -ENODEV;
390 }
391 xhci->shared_hcd->state = HC_STATE_RUNNING;
392
393 if (xhci->quirks & XHCI_NEC_HOST)
394 xhci_ring_cmd_db(xhci);
395
396 xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
397 return 0;
398}
399
400/*
401 * Start the HC after it was halted.
402 *
403 * This function is called by the USB core when the HC driver is added.
404 * Its opposite is xhci_stop().
405 *
406 * xhci_init() must be called once before this function can be called.
407 * Reset the HC, enable device slot contexts, program DCBAAP, and
408 * set command ring pointer and event ring pointer.
409 *
410 * Setup MSI-X vectors and enable interrupts.
411 */
412int xhci_run(struct usb_hcd *hcd)
413{
414 u32 temp;
415 u64 temp_64;
416 u32 ret;
417 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
418 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
419
420 /* Start the xHCI host controller running only after the USB 2.0 roothub
421 * is setup.
422 */
423
424 hcd->uses_new_polling = 1;
425 if (!usb_hcd_is_primary_hcd(hcd))
426 return xhci_run_finished(xhci);
427
428 xhci_dbg(xhci, "xhci_run\n");
429 /* unregister the legacy interrupt */
430 if (hcd->irq)
431 free_irq(hcd->irq, hcd);
432 hcd->irq = -1;
433
434 /* Some Fresco Logic host controllers advertise MSI, but fail to
435 * generate interrupts. Don't even try to enable MSI.
436 */
437 if (xhci->quirks & XHCI_BROKEN_MSI)
438 goto legacy_irq;
439
440 ret = xhci_setup_msix(xhci);
441 if (ret)
442 /* fall back to msi*/
443 ret = xhci_setup_msi(xhci);
444
445 if (ret) {
446legacy_irq:
447 /* fall back to legacy interrupt*/
448 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
449 hcd->irq_descr, hcd);
450 if (ret) {
451 xhci_err(xhci, "request interrupt %d failed\n",
452 pdev->irq);
453 return ret;
454 }
455 hcd->irq = pdev->irq;
456 }
457
458#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
459 init_timer(&xhci->event_ring_timer);
460 xhci->event_ring_timer.data = (unsigned long) xhci;
461 xhci->event_ring_timer.function = xhci_event_ring_work;
462 /* Poll the event ring */
463 xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
464 xhci->zombie = 0;
465 xhci_dbg(xhci, "Setting event ring polling timer\n");
466 add_timer(&xhci->event_ring_timer);
467#endif
468
469 xhci_dbg(xhci, "Command ring memory map follows:\n");
470 xhci_debug_ring(xhci, xhci->cmd_ring);
471 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
472 xhci_dbg_cmd_ptrs(xhci);
473
474 xhci_dbg(xhci, "ERST memory map follows:\n");
475 xhci_dbg_erst(xhci, &xhci->erst);
476 xhci_dbg(xhci, "Event ring:\n");
477 xhci_debug_ring(xhci, xhci->event_ring);
478 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
479 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
480 temp_64 &= ~ERST_PTR_MASK;
481 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
482
483 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
484 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
485 temp &= ~ER_IRQ_INTERVAL_MASK;
486 temp |= (u32) 160;
487 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
488
489 /* Set the HCD state before we enable the irqs */
490 temp = xhci_readl(xhci, &xhci->op_regs->command);
491 temp |= (CMD_EIE);
492 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
493 temp);
494 xhci_writel(xhci, temp, &xhci->op_regs->command);
495
496 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
497 xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
498 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
499 xhci_writel(xhci, ER_IRQ_ENABLE(temp),
500 &xhci->ir_set->irq_pending);
501 xhci_print_ir_set(xhci, 0);
502
503 if (xhci->quirks & XHCI_NEC_HOST)
504 xhci_queue_vendor_command(xhci, 0, 0, 0,
505 TRB_TYPE(TRB_NEC_GET_FW));
506
507 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
508 return 0;
509}
510
511static void xhci_only_stop_hcd(struct usb_hcd *hcd)
512{
513 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
514
515 spin_lock_irq(&xhci->lock);
516 xhci_halt(xhci);
517
518 /* The shared_hcd is going to be deallocated shortly (the USB core only
519 * calls this function when allocation fails in usb_add_hcd(), or
520 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
521 */
522 xhci->shared_hcd = NULL;
523 spin_unlock_irq(&xhci->lock);
524}
525
526/*
527 * Stop xHCI driver.
528 *
529 * This function is called by the USB core when the HC driver is removed.
530 * Its opposite is xhci_run().
531 *
532 * Disable device contexts, disable IRQs, and quiesce the HC.
533 * Reset the HC, finish any completed transactions, and cleanup memory.
534 */
535void xhci_stop(struct usb_hcd *hcd)
536{
537 u32 temp;
538 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
539
540 if (!usb_hcd_is_primary_hcd(hcd)) {
541 xhci_only_stop_hcd(xhci->shared_hcd);
542 return;
543 }
544
545 spin_lock_irq(&xhci->lock);
546 /* Make sure the xHC is halted for a USB3 roothub
547 * (xhci_stop() could be called as part of failed init).
548 */
549 xhci_halt(xhci);
550 xhci_reset(xhci);
551 spin_unlock_irq(&xhci->lock);
552
553 xhci_cleanup_msix(xhci);
554
555#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
556 /* Tell the event ring poll function not to reschedule */
557 xhci->zombie = 1;
558 del_timer_sync(&xhci->event_ring_timer);
559#endif
560
561 if (xhci->quirks & XHCI_AMD_PLL_FIX)
562 usb_amd_dev_put();
563
564 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
565 temp = xhci_readl(xhci, &xhci->op_regs->status);
566 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
567 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
568 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
569 &xhci->ir_set->irq_pending);
570 xhci_print_ir_set(xhci, 0);
571
572 xhci_dbg(xhci, "cleaning up memory\n");
573 xhci_mem_cleanup(xhci);
574 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
575 xhci_readl(xhci, &xhci->op_regs->status));
576}
577
578/*
579 * Shutdown HC (not bus-specific)
580 *
581 * This is called when the machine is rebooting or halting. We assume that the
582 * machine will be powered off, and the HC's internal state will be reset.
583 * Don't bother to free memory.
584 *
585 * This will only ever be called with the main usb_hcd (the USB3 roothub).
586 */
587void xhci_shutdown(struct usb_hcd *hcd)
588{
589 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
590
591 spin_lock_irq(&xhci->lock);
592 xhci_halt(xhci);
593 spin_unlock_irq(&xhci->lock);
594
595 xhci_cleanup_msix(xhci);
596
597 xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
598 xhci_readl(xhci, &xhci->op_regs->status));
599}
600
601#ifdef CONFIG_PM
602static void xhci_save_registers(struct xhci_hcd *xhci)
603{
604 xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
605 xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
606 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
607 xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
608 xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
609 xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
610 xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
611 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
612 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
613}
614
615static void xhci_restore_registers(struct xhci_hcd *xhci)
616{
617 xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
618 xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
619 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
620 xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
621 xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
622 xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
623 xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
624 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
625}
626
627static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
628{
629 u64 val_64;
630
631 /* step 2: initialize command ring buffer */
632 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
633 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
634 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
635 xhci->cmd_ring->dequeue) &
636 (u64) ~CMD_RING_RSVD_BITS) |
637 xhci->cmd_ring->cycle_state;
638 xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
639 (long unsigned long) val_64);
640 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
641}
642
643/*
644 * The whole command ring must be cleared to zero when we suspend the host.
645 *
646 * The host doesn't save the command ring pointer in the suspend well, so we
647 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
648 * aligned, because of the reserved bits in the command ring dequeue pointer
649 * register. Therefore, we can't just set the dequeue pointer back in the
650 * middle of the ring (TRBs are 16-byte aligned).
651 */
652static void xhci_clear_command_ring(struct xhci_hcd *xhci)
653{
654 struct xhci_ring *ring;
655 struct xhci_segment *seg;
656
657 ring = xhci->cmd_ring;
658 seg = ring->deq_seg;
659 do {
660 memset(seg->trbs, 0, SEGMENT_SIZE);
661 seg = seg->next;
662 } while (seg != ring->deq_seg);
663
664 /* Reset the software enqueue and dequeue pointers */
665 ring->deq_seg = ring->first_seg;
666 ring->dequeue = ring->first_seg->trbs;
667 ring->enq_seg = ring->deq_seg;
668 ring->enqueue = ring->dequeue;
669
670 /*
671 * Ring is now zeroed, so the HW should look for change of ownership
672 * when the cycle bit is set to 1.
673 */
674 ring->cycle_state = 1;
675
676 /*
677 * Reset the hardware dequeue pointer.
678 * Yes, this will need to be re-written after resume, but we're paranoid
679 * and want to make sure the hardware doesn't access bogus memory
680 * because, say, the BIOS or an SMI started the host without changing
681 * the command ring pointers.
682 */
683 xhci_set_cmd_ring_deq(xhci);
684}
685
686/*
687 * Stop HC (not bus-specific)
688 *
689 * This is called when the machine transition into S3/S4 mode.
690 *
691 */
692int xhci_suspend(struct xhci_hcd *xhci)
693{
694 int rc = 0;
695 struct usb_hcd *hcd = xhci_to_hcd(xhci);
696 u32 command;
697 int i;
698
699 spin_lock_irq(&xhci->lock);
700 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
701 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
702 /* step 1: stop endpoint */
703 /* skipped assuming that port suspend has done */
704
705 /* step 2: clear Run/Stop bit */
706 command = xhci_readl(xhci, &xhci->op_regs->command);
707 command &= ~CMD_RUN;
708 xhci_writel(xhci, command, &xhci->op_regs->command);
709 if (handshake(xhci, &xhci->op_regs->status,
710 STS_HALT, STS_HALT, 100*100)) {
711 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
712 spin_unlock_irq(&xhci->lock);
713 return -ETIMEDOUT;
714 }
715 xhci_clear_command_ring(xhci);
716
717 /* step 3: save registers */
718 xhci_save_registers(xhci);
719
720 /* step 4: set CSS flag */
721 command = xhci_readl(xhci, &xhci->op_regs->command);
722 command |= CMD_CSS;
723 xhci_writel(xhci, command, &xhci->op_regs->command);
724 if (handshake(xhci, &xhci->op_regs->status, STS_SAVE, 0, 10*100)) {
725 xhci_warn(xhci, "WARN: xHC CMD_CSS timeout\n");
726 spin_unlock_irq(&xhci->lock);
727 return -ETIMEDOUT;
728 }
729 spin_unlock_irq(&xhci->lock);
730
731 /* step 5: remove core well power */
732 /* synchronize irq when using MSI-X */
733 if (xhci->msix_entries) {
734 for (i = 0; i < xhci->msix_count; i++)
735 synchronize_irq(xhci->msix_entries[i].vector);
736 }
737
738 return rc;
739}
740
741/*
742 * start xHC (not bus-specific)
743 *
744 * This is called when the machine transition from S3/S4 mode.
745 *
746 */
747int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
748{
749 u32 command, temp = 0;
750 struct usb_hcd *hcd = xhci_to_hcd(xhci);
751 struct usb_hcd *secondary_hcd;
752 int retval;
753
754 /* Wait a bit if either of the roothubs need to settle from the
755 * transition into bus suspend.
756 */
757 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
758 time_before(jiffies,
759 xhci->bus_state[1].next_statechange))
760 msleep(100);
761
762 spin_lock_irq(&xhci->lock);
763 if (xhci->quirks & XHCI_RESET_ON_RESUME)
764 hibernated = true;
765
766 if (!hibernated) {
767 /* step 1: restore register */
768 xhci_restore_registers(xhci);
769 /* step 2: initialize command ring buffer */
770 xhci_set_cmd_ring_deq(xhci);
771 /* step 3: restore state and start state*/
772 /* step 3: set CRS flag */
773 command = xhci_readl(xhci, &xhci->op_regs->command);
774 command |= CMD_CRS;
775 xhci_writel(xhci, command, &xhci->op_regs->command);
776 if (handshake(xhci, &xhci->op_regs->status,
777 STS_RESTORE, 0, 10*100)) {
778 xhci_dbg(xhci, "WARN: xHC CMD_CSS timeout\n");
779 spin_unlock_irq(&xhci->lock);
780 return -ETIMEDOUT;
781 }
782 temp = xhci_readl(xhci, &xhci->op_regs->status);
783 }
784
785 /* If restore operation fails, re-initialize the HC during resume */
786 if ((temp & STS_SRE) || hibernated) {
787 /* Let the USB core know _both_ roothubs lost power. */
788 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
789 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
790
791 xhci_dbg(xhci, "Stop HCD\n");
792 xhci_halt(xhci);
793 xhci_reset(xhci);
794 spin_unlock_irq(&xhci->lock);
795 xhci_cleanup_msix(xhci);
796
797#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
798 /* Tell the event ring poll function not to reschedule */
799 xhci->zombie = 1;
800 del_timer_sync(&xhci->event_ring_timer);
801#endif
802
803 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
804 temp = xhci_readl(xhci, &xhci->op_regs->status);
805 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
806 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
807 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
808 &xhci->ir_set->irq_pending);
809 xhci_print_ir_set(xhci, 0);
810
811 xhci_dbg(xhci, "cleaning up memory\n");
812 xhci_mem_cleanup(xhci);
813 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
814 xhci_readl(xhci, &xhci->op_regs->status));
815
816 /* USB core calls the PCI reinit and start functions twice:
817 * first with the primary HCD, and then with the secondary HCD.
818 * If we don't do the same, the host will never be started.
819 */
820 if (!usb_hcd_is_primary_hcd(hcd))
821 secondary_hcd = hcd;
822 else
823 secondary_hcd = xhci->shared_hcd;
824
825 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
826 retval = xhci_init(hcd->primary_hcd);
827 if (retval)
828 return retval;
829 xhci_dbg(xhci, "Start the primary HCD\n");
830 retval = xhci_run(hcd->primary_hcd);
831 if (retval)
832 goto failed_restart;
833
834 xhci_dbg(xhci, "Start the secondary HCD\n");
835 retval = xhci_run(secondary_hcd);
836 if (!retval) {
837 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
838 set_bit(HCD_FLAG_HW_ACCESSIBLE,
839 &xhci->shared_hcd->flags);
840 }
841failed_restart:
842 hcd->state = HC_STATE_SUSPENDED;
843 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
844 return retval;
845 }
846
847 /* step 4: set Run/Stop bit */
848 command = xhci_readl(xhci, &xhci->op_regs->command);
849 command |= CMD_RUN;
850 xhci_writel(xhci, command, &xhci->op_regs->command);
851 handshake(xhci, &xhci->op_regs->status, STS_HALT,
852 0, 250 * 1000);
853
854 /* step 5: walk topology and initialize portsc,
855 * portpmsc and portli
856 */
857 /* this is done in bus_resume */
858
859 /* step 6: restart each of the previously
860 * Running endpoints by ringing their doorbells
861 */
862
863 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
864 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
865
866 spin_unlock_irq(&xhci->lock);
867 return 0;
868}
869#endif /* CONFIG_PM */
870
871/*-------------------------------------------------------------------------*/
872
873/**
874 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
875 * HCDs. Find the index for an endpoint given its descriptor. Use the return
876 * value to right shift 1 for the bitmask.
877 *
878 * Index = (epnum * 2) + direction - 1,
879 * where direction = 0 for OUT, 1 for IN.
880 * For control endpoints, the IN index is used (OUT index is unused), so
881 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
882 */
883unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
884{
885 unsigned int index;
886 if (usb_endpoint_xfer_control(desc))
887 index = (unsigned int) (usb_endpoint_num(desc)*2);
888 else
889 index = (unsigned int) (usb_endpoint_num(desc)*2) +
890 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
891 return index;
892}
893
894/* Find the flag for this endpoint (for use in the control context). Use the
895 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
896 * bit 1, etc.
897 */
898unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
899{
900 return 1 << (xhci_get_endpoint_index(desc) + 1);
901}
902
903/* Find the flag for this endpoint (for use in the control context). Use the
904 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
905 * bit 1, etc.
906 */
907unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
908{
909 return 1 << (ep_index + 1);
910}
911
912/* Compute the last valid endpoint context index. Basically, this is the
913 * endpoint index plus one. For slot contexts with more than valid endpoint,
914 * we find the most significant bit set in the added contexts flags.
915 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
916 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
917 */
918unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
919{
920 return fls(added_ctxs) - 1;
921}
922
923/* Returns 1 if the arguments are OK;
924 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
925 */
926static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
927 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
928 const char *func) {
929 struct xhci_hcd *xhci;
930 struct xhci_virt_device *virt_dev;
931
932 if (!hcd || (check_ep && !ep) || !udev) {
933 printk(KERN_DEBUG "xHCI %s called with invalid args\n",
934 func);
935 return -EINVAL;
936 }
937 if (!udev->parent) {
938 printk(KERN_DEBUG "xHCI %s called for root hub\n",
939 func);
940 return 0;
941 }
942
943 xhci = hcd_to_xhci(hcd);
944 if (xhci->xhc_state & XHCI_STATE_HALTED)
945 return -ENODEV;
946
947 if (check_virt_dev) {
948 if (!udev->slot_id || !xhci->devs
949 || !xhci->devs[udev->slot_id]) {
950 printk(KERN_DEBUG "xHCI %s called with unaddressed "
951 "device\n", func);
952 return -EINVAL;
953 }
954
955 virt_dev = xhci->devs[udev->slot_id];
956 if (virt_dev->udev != udev) {
957 printk(KERN_DEBUG "xHCI %s called with udev and "
958 "virt_dev does not match\n", func);
959 return -EINVAL;
960 }
961 }
962
963 return 1;
964}
965
966static int xhci_configure_endpoint(struct xhci_hcd *xhci,
967 struct usb_device *udev, struct xhci_command *command,
968 bool ctx_change, bool must_succeed);
969
970/*
971 * Full speed devices may have a max packet size greater than 8 bytes, but the
972 * USB core doesn't know that until it reads the first 8 bytes of the
973 * descriptor. If the usb_device's max packet size changes after that point,
974 * we need to issue an evaluate context command and wait on it.
975 */
976static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
977 unsigned int ep_index, struct urb *urb)
978{
979 struct xhci_container_ctx *in_ctx;
980 struct xhci_container_ctx *out_ctx;
981 struct xhci_input_control_ctx *ctrl_ctx;
982 struct xhci_ep_ctx *ep_ctx;
983 int max_packet_size;
984 int hw_max_packet_size;
985 int ret = 0;
986
987 out_ctx = xhci->devs[slot_id]->out_ctx;
988 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
989 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
990 max_packet_size = le16_to_cpu(urb->dev->ep0.desc.wMaxPacketSize);
991 if (hw_max_packet_size != max_packet_size) {
992 xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
993 xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
994 max_packet_size);
995 xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
996 hw_max_packet_size);
997 xhci_dbg(xhci, "Issuing evaluate context command.\n");
998
999 /* Set up the modified control endpoint 0 */
1000 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1001 xhci->devs[slot_id]->out_ctx, ep_index);
1002 in_ctx = xhci->devs[slot_id]->in_ctx;
1003 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1004 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1005 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1006
1007 /* Set up the input context flags for the command */
1008 /* FIXME: This won't work if a non-default control endpoint
1009 * changes max packet sizes.
1010 */
1011 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1012 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1013 ctrl_ctx->drop_flags = 0;
1014
1015 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1016 xhci_dbg_ctx(xhci, in_ctx, ep_index);
1017 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1018 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1019
1020 ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
1021 true, false);
1022
1023 /* Clean up the input context for later use by bandwidth
1024 * functions.
1025 */
1026 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1027 }
1028 return ret;
1029}
1030
1031/*
1032 * non-error returns are a promise to giveback() the urb later
1033 * we drop ownership so next owner (or urb unlink) can get it
1034 */
1035int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1036{
1037 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1038 unsigned long flags;
1039 int ret = 0;
1040 unsigned int slot_id, ep_index;
1041 struct urb_priv *urb_priv;
1042 int size, i;
1043
1044 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1045 true, true, __func__) <= 0)
1046 return -EINVAL;
1047
1048 slot_id = urb->dev->slot_id;
1049 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1050
1051 if (!HCD_HW_ACCESSIBLE(hcd)) {
1052 if (!in_interrupt())
1053 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1054 ret = -ESHUTDOWN;
1055 goto exit;
1056 }
1057
1058 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1059 size = urb->number_of_packets;
1060 else
1061 size = 1;
1062
1063 urb_priv = kzalloc(sizeof(struct urb_priv) +
1064 size * sizeof(struct xhci_td *), mem_flags);
1065 if (!urb_priv)
1066 return -ENOMEM;
1067
1068 for (i = 0; i < size; i++) {
1069 urb_priv->td[i] = kzalloc(sizeof(struct xhci_td), mem_flags);
1070 if (!urb_priv->td[i]) {
1071 urb_priv->length = i;
1072 xhci_urb_free_priv(xhci, urb_priv);
1073 return -ENOMEM;
1074 }
1075 }
1076
1077 urb_priv->length = size;
1078 urb_priv->td_cnt = 0;
1079 urb->hcpriv = urb_priv;
1080
1081 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1082 /* Check to see if the max packet size for the default control
1083 * endpoint changed during FS device enumeration
1084 */
1085 if (urb->dev->speed == USB_SPEED_FULL) {
1086 ret = xhci_check_maxpacket(xhci, slot_id,
1087 ep_index, urb);
1088 if (ret < 0) {
1089 xhci_urb_free_priv(xhci, urb_priv);
1090 urb->hcpriv = NULL;
1091 return ret;
1092 }
1093 }
1094
1095 /* We have a spinlock and interrupts disabled, so we must pass
1096 * atomic context to this function, which may allocate memory.
1097 */
1098 spin_lock_irqsave(&xhci->lock, flags);
1099 if (xhci->xhc_state & XHCI_STATE_DYING)
1100 goto dying;
1101 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1102 slot_id, ep_index);
1103 if (ret)
1104 goto free_priv;
1105 spin_unlock_irqrestore(&xhci->lock, flags);
1106 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1107 spin_lock_irqsave(&xhci->lock, flags);
1108 if (xhci->xhc_state & XHCI_STATE_DYING)
1109 goto dying;
1110 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1111 EP_GETTING_STREAMS) {
1112 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1113 "is transitioning to using streams.\n");
1114 ret = -EINVAL;
1115 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1116 EP_GETTING_NO_STREAMS) {
1117 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1118 "is transitioning to "
1119 "not having streams.\n");
1120 ret = -EINVAL;
1121 } else {
1122 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1123 slot_id, ep_index);
1124 }
1125 if (ret)
1126 goto free_priv;
1127 spin_unlock_irqrestore(&xhci->lock, flags);
1128 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1129 spin_lock_irqsave(&xhci->lock, flags);
1130 if (xhci->xhc_state & XHCI_STATE_DYING)
1131 goto dying;
1132 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1133 slot_id, ep_index);
1134 if (ret)
1135 goto free_priv;
1136 spin_unlock_irqrestore(&xhci->lock, flags);
1137 } else {
1138 spin_lock_irqsave(&xhci->lock, flags);
1139 if (xhci->xhc_state & XHCI_STATE_DYING)
1140 goto dying;
1141 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1142 slot_id, ep_index);
1143 if (ret)
1144 goto free_priv;
1145 spin_unlock_irqrestore(&xhci->lock, flags);
1146 }
1147exit:
1148 return ret;
1149dying:
1150 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1151 "non-responsive xHCI host.\n",
1152 urb->ep->desc.bEndpointAddress, urb);
1153 ret = -ESHUTDOWN;
1154free_priv:
1155 xhci_urb_free_priv(xhci, urb_priv);
1156 urb->hcpriv = NULL;
1157 spin_unlock_irqrestore(&xhci->lock, flags);
1158 return ret;
1159}
1160
1161/* Get the right ring for the given URB.
1162 * If the endpoint supports streams, boundary check the URB's stream ID.
1163 * If the endpoint doesn't support streams, return the singular endpoint ring.
1164 */
1165static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1166 struct urb *urb)
1167{
1168 unsigned int slot_id;
1169 unsigned int ep_index;
1170 unsigned int stream_id;
1171 struct xhci_virt_ep *ep;
1172
1173 slot_id = urb->dev->slot_id;
1174 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1175 stream_id = urb->stream_id;
1176 ep = &xhci->devs[slot_id]->eps[ep_index];
1177 /* Common case: no streams */
1178 if (!(ep->ep_state & EP_HAS_STREAMS))
1179 return ep->ring;
1180
1181 if (stream_id == 0) {
1182 xhci_warn(xhci,
1183 "WARN: Slot ID %u, ep index %u has streams, "
1184 "but URB has no stream ID.\n",
1185 slot_id, ep_index);
1186 return NULL;
1187 }
1188
1189 if (stream_id < ep->stream_info->num_streams)
1190 return ep->stream_info->stream_rings[stream_id];
1191
1192 xhci_warn(xhci,
1193 "WARN: Slot ID %u, ep index %u has "
1194 "stream IDs 1 to %u allocated, "
1195 "but stream ID %u is requested.\n",
1196 slot_id, ep_index,
1197 ep->stream_info->num_streams - 1,
1198 stream_id);
1199 return NULL;
1200}
1201
1202/*
1203 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1204 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1205 * should pick up where it left off in the TD, unless a Set Transfer Ring
1206 * Dequeue Pointer is issued.
1207 *
1208 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1209 * the ring. Since the ring is a contiguous structure, they can't be physically
1210 * removed. Instead, there are two options:
1211 *
1212 * 1) If the HC is in the middle of processing the URB to be canceled, we
1213 * simply move the ring's dequeue pointer past those TRBs using the Set
1214 * Transfer Ring Dequeue Pointer command. This will be the common case,
1215 * when drivers timeout on the last submitted URB and attempt to cancel.
1216 *
1217 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1218 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1219 * HC will need to invalidate the any TRBs it has cached after the stop
1220 * endpoint command, as noted in the xHCI 0.95 errata.
1221 *
1222 * 3) The TD may have completed by the time the Stop Endpoint Command
1223 * completes, so software needs to handle that case too.
1224 *
1225 * This function should protect against the TD enqueueing code ringing the
1226 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1227 * It also needs to account for multiple cancellations on happening at the same
1228 * time for the same endpoint.
1229 *
1230 * Note that this function can be called in any context, or so says
1231 * usb_hcd_unlink_urb()
1232 */
1233int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1234{
1235 unsigned long flags;
1236 int ret, i;
1237 u32 temp;
1238 struct xhci_hcd *xhci;
1239 struct urb_priv *urb_priv;
1240 struct xhci_td *td;
1241 unsigned int ep_index;
1242 struct xhci_ring *ep_ring;
1243 struct xhci_virt_ep *ep;
1244
1245 xhci = hcd_to_xhci(hcd);
1246 spin_lock_irqsave(&xhci->lock, flags);
1247 /* Make sure the URB hasn't completed or been unlinked already */
1248 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1249 if (ret || !urb->hcpriv)
1250 goto done;
1251 temp = xhci_readl(xhci, &xhci->op_regs->status);
1252 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1253 xhci_dbg(xhci, "HW died, freeing TD.\n");
1254 urb_priv = urb->hcpriv;
1255 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1256 td = urb_priv->td[i];
1257 if (!list_empty(&td->td_list))
1258 list_del_init(&td->td_list);
1259 if (!list_empty(&td->cancelled_td_list))
1260 list_del_init(&td->cancelled_td_list);
1261 }
1262
1263 usb_hcd_unlink_urb_from_ep(hcd, urb);
1264 spin_unlock_irqrestore(&xhci->lock, flags);
1265 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1266 xhci_urb_free_priv(xhci, urb_priv);
1267 return ret;
1268 }
1269 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1270 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1271 xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
1272 "non-responsive xHCI host.\n",
1273 urb->ep->desc.bEndpointAddress, urb);
1274 /* Let the stop endpoint command watchdog timer (which set this
1275 * state) finish cleaning up the endpoint TD lists. We must
1276 * have caught it in the middle of dropping a lock and giving
1277 * back an URB.
1278 */
1279 goto done;
1280 }
1281
1282 xhci_dbg(xhci, "Cancel URB %p\n", urb);
1283 xhci_dbg(xhci, "Event ring:\n");
1284 xhci_debug_ring(xhci, xhci->event_ring);
1285 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1286 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1287 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1288 if (!ep_ring) {
1289 ret = -EINVAL;
1290 goto done;
1291 }
1292
1293 xhci_dbg(xhci, "Endpoint ring:\n");
1294 xhci_debug_ring(xhci, ep_ring);
1295
1296 urb_priv = urb->hcpriv;
1297
1298 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1299 td = urb_priv->td[i];
1300 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1301 }
1302
1303 /* Queue a stop endpoint command, but only if this is
1304 * the first cancellation to be handled.
1305 */
1306 if (!(ep->ep_state & EP_HALT_PENDING)) {
1307 ep->ep_state |= EP_HALT_PENDING;
1308 ep->stop_cmds_pending++;
1309 ep->stop_cmd_timer.expires = jiffies +
1310 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1311 add_timer(&ep->stop_cmd_timer);
1312 xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
1313 xhci_ring_cmd_db(xhci);
1314 }
1315done:
1316 spin_unlock_irqrestore(&xhci->lock, flags);
1317 return ret;
1318}
1319
1320/* Drop an endpoint from a new bandwidth configuration for this device.
1321 * Only one call to this function is allowed per endpoint before
1322 * check_bandwidth() or reset_bandwidth() must be called.
1323 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1324 * add the endpoint to the schedule with possibly new parameters denoted by a
1325 * different endpoint descriptor in usb_host_endpoint.
1326 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1327 * not allowed.
1328 *
1329 * The USB core will not allow URBs to be queued to an endpoint that is being
1330 * disabled, so there's no need for mutual exclusion to protect
1331 * the xhci->devs[slot_id] structure.
1332 */
1333int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1334 struct usb_host_endpoint *ep)
1335{
1336 struct xhci_hcd *xhci;
1337 struct xhci_container_ctx *in_ctx, *out_ctx;
1338 struct xhci_input_control_ctx *ctrl_ctx;
1339 struct xhci_slot_ctx *slot_ctx;
1340 unsigned int last_ctx;
1341 unsigned int ep_index;
1342 struct xhci_ep_ctx *ep_ctx;
1343 u32 drop_flag;
1344 u32 new_add_flags, new_drop_flags, new_slot_info;
1345 int ret;
1346
1347 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1348 if (ret <= 0)
1349 return ret;
1350 xhci = hcd_to_xhci(hcd);
1351 if (xhci->xhc_state & XHCI_STATE_DYING)
1352 return -ENODEV;
1353
1354 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1355 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1356 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1357 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1358 __func__, drop_flag);
1359 return 0;
1360 }
1361
1362 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1363 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1364 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1365 ep_index = xhci_get_endpoint_index(&ep->desc);
1366 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1367 /* If the HC already knows the endpoint is disabled,
1368 * or the HCD has noted it is disabled, ignore this request
1369 */
1370 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1371 cpu_to_le32(EP_STATE_DISABLED)) ||
1372 le32_to_cpu(ctrl_ctx->drop_flags) &
1373 xhci_get_endpoint_flag(&ep->desc)) {
1374 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1375 __func__, ep);
1376 return 0;
1377 }
1378
1379 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1380 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1381
1382 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1383 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1384
1385 last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
1386 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1387 /* Update the last valid endpoint context, if we deleted the last one */
1388 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
1389 LAST_CTX(last_ctx)) {
1390 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1391 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1392 }
1393 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1394
1395 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1396
1397 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1398 (unsigned int) ep->desc.bEndpointAddress,
1399 udev->slot_id,
1400 (unsigned int) new_drop_flags,
1401 (unsigned int) new_add_flags,
1402 (unsigned int) new_slot_info);
1403 return 0;
1404}
1405
1406/* Add an endpoint to a new possible bandwidth configuration for this device.
1407 * Only one call to this function is allowed per endpoint before
1408 * check_bandwidth() or reset_bandwidth() must be called.
1409 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1410 * add the endpoint to the schedule with possibly new parameters denoted by a
1411 * different endpoint descriptor in usb_host_endpoint.
1412 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1413 * not allowed.
1414 *
1415 * The USB core will not allow URBs to be queued to an endpoint until the
1416 * configuration or alt setting is installed in the device, so there's no need
1417 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1418 */
1419int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1420 struct usb_host_endpoint *ep)
1421{
1422 struct xhci_hcd *xhci;
1423 struct xhci_container_ctx *in_ctx, *out_ctx;
1424 unsigned int ep_index;
1425 struct xhci_ep_ctx *ep_ctx;
1426 struct xhci_slot_ctx *slot_ctx;
1427 struct xhci_input_control_ctx *ctrl_ctx;
1428 u32 added_ctxs;
1429 unsigned int last_ctx;
1430 u32 new_add_flags, new_drop_flags, new_slot_info;
1431 struct xhci_virt_device *virt_dev;
1432 int ret = 0;
1433
1434 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1435 if (ret <= 0) {
1436 /* So we won't queue a reset ep command for a root hub */
1437 ep->hcpriv = NULL;
1438 return ret;
1439 }
1440 xhci = hcd_to_xhci(hcd);
1441 if (xhci->xhc_state & XHCI_STATE_DYING)
1442 return -ENODEV;
1443
1444 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1445 last_ctx = xhci_last_valid_endpoint(added_ctxs);
1446 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1447 /* FIXME when we have to issue an evaluate endpoint command to
1448 * deal with ep0 max packet size changing once we get the
1449 * descriptors
1450 */
1451 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1452 __func__, added_ctxs);
1453 return 0;
1454 }
1455
1456 virt_dev = xhci->devs[udev->slot_id];
1457 in_ctx = virt_dev->in_ctx;
1458 out_ctx = virt_dev->out_ctx;
1459 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1460 ep_index = xhci_get_endpoint_index(&ep->desc);
1461 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1462
1463 /* If this endpoint is already in use, and the upper layers are trying
1464 * to add it again without dropping it, reject the addition.
1465 */
1466 if (virt_dev->eps[ep_index].ring &&
1467 !(le32_to_cpu(ctrl_ctx->drop_flags) &
1468 xhci_get_endpoint_flag(&ep->desc))) {
1469 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1470 "without dropping it.\n",
1471 (unsigned int) ep->desc.bEndpointAddress);
1472 return -EINVAL;
1473 }
1474
1475 /* If the HCD has already noted the endpoint is enabled,
1476 * ignore this request.
1477 */
1478 if (le32_to_cpu(ctrl_ctx->add_flags) &
1479 xhci_get_endpoint_flag(&ep->desc)) {
1480 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1481 __func__, ep);
1482 return 0;
1483 }
1484
1485 /*
1486 * Configuration and alternate setting changes must be done in
1487 * process context, not interrupt context (or so documenation
1488 * for usb_set_interface() and usb_set_configuration() claim).
1489 */
1490 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1491 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1492 __func__, ep->desc.bEndpointAddress);
1493 return -ENOMEM;
1494 }
1495
1496 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1497 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1498
1499 /* If xhci_endpoint_disable() was called for this endpoint, but the
1500 * xHC hasn't been notified yet through the check_bandwidth() call,
1501 * this re-adds a new state for the endpoint from the new endpoint
1502 * descriptors. We must drop and re-add this endpoint, so we leave the
1503 * drop flags alone.
1504 */
1505 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1506
1507 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1508 /* Update the last valid endpoint context, if we just added one past */
1509 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
1510 LAST_CTX(last_ctx)) {
1511 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1512 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1513 }
1514 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1515
1516 /* Store the usb_device pointer for later use */
1517 ep->hcpriv = udev;
1518
1519 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1520 (unsigned int) ep->desc.bEndpointAddress,
1521 udev->slot_id,
1522 (unsigned int) new_drop_flags,
1523 (unsigned int) new_add_flags,
1524 (unsigned int) new_slot_info);
1525 return 0;
1526}
1527
1528static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1529{
1530 struct xhci_input_control_ctx *ctrl_ctx;
1531 struct xhci_ep_ctx *ep_ctx;
1532 struct xhci_slot_ctx *slot_ctx;
1533 int i;
1534
1535 /* When a device's add flag and drop flag are zero, any subsequent
1536 * configure endpoint command will leave that endpoint's state
1537 * untouched. Make sure we don't leave any old state in the input
1538 * endpoint contexts.
1539 */
1540 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1541 ctrl_ctx->drop_flags = 0;
1542 ctrl_ctx->add_flags = 0;
1543 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1544 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1545 /* Endpoint 0 is always valid */
1546 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1547 for (i = 1; i < 31; ++i) {
1548 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1549 ep_ctx->ep_info = 0;
1550 ep_ctx->ep_info2 = 0;
1551 ep_ctx->deq = 0;
1552 ep_ctx->tx_info = 0;
1553 }
1554}
1555
1556static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1557 struct usb_device *udev, u32 *cmd_status)
1558{
1559 int ret;
1560
1561 switch (*cmd_status) {
1562 case COMP_ENOMEM:
1563 dev_warn(&udev->dev, "Not enough host controller resources "
1564 "for new device state.\n");
1565 ret = -ENOMEM;
1566 /* FIXME: can we allocate more resources for the HC? */
1567 break;
1568 case COMP_BW_ERR:
1569 dev_warn(&udev->dev, "Not enough bandwidth "
1570 "for new device state.\n");
1571 ret = -ENOSPC;
1572 /* FIXME: can we go back to the old state? */
1573 break;
1574 case COMP_TRB_ERR:
1575 /* the HCD set up something wrong */
1576 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1577 "add flag = 1, "
1578 "and endpoint is not disabled.\n");
1579 ret = -EINVAL;
1580 break;
1581 case COMP_DEV_ERR:
1582 dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
1583 "configure command.\n");
1584 ret = -ENODEV;
1585 break;
1586 case COMP_SUCCESS:
1587 dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
1588 ret = 0;
1589 break;
1590 default:
1591 xhci_err(xhci, "ERROR: unexpected command completion "
1592 "code 0x%x.\n", *cmd_status);
1593 ret = -EINVAL;
1594 break;
1595 }
1596 return ret;
1597}
1598
1599static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1600 struct usb_device *udev, u32 *cmd_status)
1601{
1602 int ret;
1603 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1604
1605 switch (*cmd_status) {
1606 case COMP_EINVAL:
1607 dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1608 "context command.\n");
1609 ret = -EINVAL;
1610 break;
1611 case COMP_EBADSLT:
1612 dev_warn(&udev->dev, "WARN: slot not enabled for"
1613 "evaluate context command.\n");
1614 case COMP_CTX_STATE:
1615 dev_warn(&udev->dev, "WARN: invalid context state for "
1616 "evaluate context command.\n");
1617 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1618 ret = -EINVAL;
1619 break;
1620 case COMP_DEV_ERR:
1621 dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
1622 "context command.\n");
1623 ret = -ENODEV;
1624 break;
1625 case COMP_MEL_ERR:
1626 /* Max Exit Latency too large error */
1627 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1628 ret = -EINVAL;
1629 break;
1630 case COMP_SUCCESS:
1631 dev_dbg(&udev->dev, "Successful evaluate context command\n");
1632 ret = 0;
1633 break;
1634 default:
1635 xhci_err(xhci, "ERROR: unexpected command completion "
1636 "code 0x%x.\n", *cmd_status);
1637 ret = -EINVAL;
1638 break;
1639 }
1640 return ret;
1641}
1642
1643static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1644 struct xhci_container_ctx *in_ctx)
1645{
1646 struct xhci_input_control_ctx *ctrl_ctx;
1647 u32 valid_add_flags;
1648 u32 valid_drop_flags;
1649
1650 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1651 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1652 * (bit 1). The default control endpoint is added during the Address
1653 * Device command and is never removed until the slot is disabled.
1654 */
1655 valid_add_flags = ctrl_ctx->add_flags >> 2;
1656 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1657
1658 /* Use hweight32 to count the number of ones in the add flags, or
1659 * number of endpoints added. Don't count endpoints that are changed
1660 * (both added and dropped).
1661 */
1662 return hweight32(valid_add_flags) -
1663 hweight32(valid_add_flags & valid_drop_flags);
1664}
1665
1666static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1667 struct xhci_container_ctx *in_ctx)
1668{
1669 struct xhci_input_control_ctx *ctrl_ctx;
1670 u32 valid_add_flags;
1671 u32 valid_drop_flags;
1672
1673 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1674 valid_add_flags = ctrl_ctx->add_flags >> 2;
1675 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1676
1677 return hweight32(valid_drop_flags) -
1678 hweight32(valid_add_flags & valid_drop_flags);
1679}
1680
1681/*
1682 * We need to reserve the new number of endpoints before the configure endpoint
1683 * command completes. We can't subtract the dropped endpoints from the number
1684 * of active endpoints until the command completes because we can oversubscribe
1685 * the host in this case:
1686 *
1687 * - the first configure endpoint command drops more endpoints than it adds
1688 * - a second configure endpoint command that adds more endpoints is queued
1689 * - the first configure endpoint command fails, so the config is unchanged
1690 * - the second command may succeed, even though there isn't enough resources
1691 *
1692 * Must be called with xhci->lock held.
1693 */
1694static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1695 struct xhci_container_ctx *in_ctx)
1696{
1697 u32 added_eps;
1698
1699 added_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1700 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1701 xhci_dbg(xhci, "Not enough ep ctxs: "
1702 "%u active, need to add %u, limit is %u.\n",
1703 xhci->num_active_eps, added_eps,
1704 xhci->limit_active_eps);
1705 return -ENOMEM;
1706 }
1707 xhci->num_active_eps += added_eps;
1708 xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps,
1709 xhci->num_active_eps);
1710 return 0;
1711}
1712
1713/*
1714 * The configure endpoint was failed by the xHC for some other reason, so we
1715 * need to revert the resources that failed configuration would have used.
1716 *
1717 * Must be called with xhci->lock held.
1718 */
1719static void xhci_free_host_resources(struct xhci_hcd *xhci,
1720 struct xhci_container_ctx *in_ctx)
1721{
1722 u32 num_failed_eps;
1723
1724 num_failed_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1725 xhci->num_active_eps -= num_failed_eps;
1726 xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n",
1727 num_failed_eps,
1728 xhci->num_active_eps);
1729}
1730
1731/*
1732 * Now that the command has completed, clean up the active endpoint count by
1733 * subtracting out the endpoints that were dropped (but not changed).
1734 *
1735 * Must be called with xhci->lock held.
1736 */
1737static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
1738 struct xhci_container_ctx *in_ctx)
1739{
1740 u32 num_dropped_eps;
1741
1742 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, in_ctx);
1743 xhci->num_active_eps -= num_dropped_eps;
1744 if (num_dropped_eps)
1745 xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n",
1746 num_dropped_eps,
1747 xhci->num_active_eps);
1748}
1749
1750/* Issue a configure endpoint command or evaluate context command
1751 * and wait for it to finish.
1752 */
1753static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1754 struct usb_device *udev,
1755 struct xhci_command *command,
1756 bool ctx_change, bool must_succeed)
1757{
1758 int ret;
1759 int timeleft;
1760 unsigned long flags;
1761 struct xhci_container_ctx *in_ctx;
1762 struct completion *cmd_completion;
1763 u32 *cmd_status;
1764 struct xhci_virt_device *virt_dev;
1765
1766 spin_lock_irqsave(&xhci->lock, flags);
1767 virt_dev = xhci->devs[udev->slot_id];
1768 if (command) {
1769 in_ctx = command->in_ctx;
1770 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
1771 xhci_reserve_host_resources(xhci, in_ctx)) {
1772 spin_unlock_irqrestore(&xhci->lock, flags);
1773 xhci_warn(xhci, "Not enough host resources, "
1774 "active endpoint contexts = %u\n",
1775 xhci->num_active_eps);
1776 return -ENOMEM;
1777 }
1778
1779 cmd_completion = command->completion;
1780 cmd_status = &command->status;
1781 command->command_trb = xhci->cmd_ring->enqueue;
1782
1783 /* Enqueue pointer can be left pointing to the link TRB,
1784 * we must handle that
1785 */
1786 if (TRB_TYPE_LINK_LE32(command->command_trb->link.control))
1787 command->command_trb =
1788 xhci->cmd_ring->enq_seg->next->trbs;
1789
1790 list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
1791 } else {
1792 in_ctx = virt_dev->in_ctx;
1793 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
1794 xhci_reserve_host_resources(xhci, in_ctx)) {
1795 spin_unlock_irqrestore(&xhci->lock, flags);
1796 xhci_warn(xhci, "Not enough host resources, "
1797 "active endpoint contexts = %u\n",
1798 xhci->num_active_eps);
1799 return -ENOMEM;
1800 }
1801 cmd_completion = &virt_dev->cmd_completion;
1802 cmd_status = &virt_dev->cmd_status;
1803 }
1804 init_completion(cmd_completion);
1805
1806 if (!ctx_change)
1807 ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
1808 udev->slot_id, must_succeed);
1809 else
1810 ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
1811 udev->slot_id);
1812 if (ret < 0) {
1813 if (command)
1814 list_del(&command->cmd_list);
1815 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
1816 xhci_free_host_resources(xhci, in_ctx);
1817 spin_unlock_irqrestore(&xhci->lock, flags);
1818 xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
1819 return -ENOMEM;
1820 }
1821 xhci_ring_cmd_db(xhci);
1822 spin_unlock_irqrestore(&xhci->lock, flags);
1823
1824 /* Wait for the configure endpoint command to complete */
1825 timeleft = wait_for_completion_interruptible_timeout(
1826 cmd_completion,
1827 USB_CTRL_SET_TIMEOUT);
1828 if (timeleft <= 0) {
1829 xhci_warn(xhci, "%s while waiting for %s command\n",
1830 timeleft == 0 ? "Timeout" : "Signal",
1831 ctx_change == 0 ?
1832 "configure endpoint" :
1833 "evaluate context");
1834 /* FIXME cancel the configure endpoint command */
1835 return -ETIME;
1836 }
1837
1838 if (!ctx_change)
1839 ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
1840 else
1841 ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
1842
1843 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
1844 spin_lock_irqsave(&xhci->lock, flags);
1845 /* If the command failed, remove the reserved resources.
1846 * Otherwise, clean up the estimate to include dropped eps.
1847 */
1848 if (ret)
1849 xhci_free_host_resources(xhci, in_ctx);
1850 else
1851 xhci_finish_resource_reservation(xhci, in_ctx);
1852 spin_unlock_irqrestore(&xhci->lock, flags);
1853 }
1854 return ret;
1855}
1856
1857/* Called after one or more calls to xhci_add_endpoint() or
1858 * xhci_drop_endpoint(). If this call fails, the USB core is expected
1859 * to call xhci_reset_bandwidth().
1860 *
1861 * Since we are in the middle of changing either configuration or
1862 * installing a new alt setting, the USB core won't allow URBs to be
1863 * enqueued for any endpoint on the old config or interface. Nothing
1864 * else should be touching the xhci->devs[slot_id] structure, so we
1865 * don't need to take the xhci->lock for manipulating that.
1866 */
1867int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
1868{
1869 int i;
1870 int ret = 0;
1871 struct xhci_hcd *xhci;
1872 struct xhci_virt_device *virt_dev;
1873 struct xhci_input_control_ctx *ctrl_ctx;
1874 struct xhci_slot_ctx *slot_ctx;
1875
1876 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
1877 if (ret <= 0)
1878 return ret;
1879 xhci = hcd_to_xhci(hcd);
1880 if (xhci->xhc_state & XHCI_STATE_DYING)
1881 return -ENODEV;
1882
1883 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1884 virt_dev = xhci->devs[udev->slot_id];
1885
1886 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
1887 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1888 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
1889 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
1890 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
1891 xhci_dbg(xhci, "New Input Control Context:\n");
1892 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1893 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
1894 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
1895
1896 ret = xhci_configure_endpoint(xhci, udev, NULL,
1897 false, false);
1898 if (ret) {
1899 /* Callee should call reset_bandwidth() */
1900 return ret;
1901 }
1902
1903 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
1904 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
1905 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
1906
1907 /* Free any rings that were dropped, but not changed. */
1908 for (i = 1; i < 31; ++i) {
1909 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
1910 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
1911 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
1912 }
1913 xhci_zero_in_ctx(xhci, virt_dev);
1914 /*
1915 * Install any rings for completely new endpoints or changed endpoints,
1916 * and free or cache any old rings from changed endpoints.
1917 */
1918 for (i = 1; i < 31; ++i) {
1919 if (!virt_dev->eps[i].new_ring)
1920 continue;
1921 /* Only cache or free the old ring if it exists.
1922 * It may not if this is the first add of an endpoint.
1923 */
1924 if (virt_dev->eps[i].ring) {
1925 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
1926 }
1927 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
1928 virt_dev->eps[i].new_ring = NULL;
1929 }
1930
1931 return ret;
1932}
1933
1934void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
1935{
1936 struct xhci_hcd *xhci;
1937 struct xhci_virt_device *virt_dev;
1938 int i, ret;
1939
1940 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
1941 if (ret <= 0)
1942 return;
1943 xhci = hcd_to_xhci(hcd);
1944
1945 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1946 virt_dev = xhci->devs[udev->slot_id];
1947 /* Free any rings allocated for added endpoints */
1948 for (i = 0; i < 31; ++i) {
1949 if (virt_dev->eps[i].new_ring) {
1950 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
1951 virt_dev->eps[i].new_ring = NULL;
1952 }
1953 }
1954 xhci_zero_in_ctx(xhci, virt_dev);
1955}
1956
1957static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
1958 struct xhci_container_ctx *in_ctx,
1959 struct xhci_container_ctx *out_ctx,
1960 u32 add_flags, u32 drop_flags)
1961{
1962 struct xhci_input_control_ctx *ctrl_ctx;
1963 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1964 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
1965 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
1966 xhci_slot_copy(xhci, in_ctx, out_ctx);
1967 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
1968
1969 xhci_dbg(xhci, "Input Context:\n");
1970 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
1971}
1972
1973static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
1974 unsigned int slot_id, unsigned int ep_index,
1975 struct xhci_dequeue_state *deq_state)
1976{
1977 struct xhci_container_ctx *in_ctx;
1978 struct xhci_ep_ctx *ep_ctx;
1979 u32 added_ctxs;
1980 dma_addr_t addr;
1981
1982 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1983 xhci->devs[slot_id]->out_ctx, ep_index);
1984 in_ctx = xhci->devs[slot_id]->in_ctx;
1985 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1986 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
1987 deq_state->new_deq_ptr);
1988 if (addr == 0) {
1989 xhci_warn(xhci, "WARN Cannot submit config ep after "
1990 "reset ep command\n");
1991 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
1992 deq_state->new_deq_seg,
1993 deq_state->new_deq_ptr);
1994 return;
1995 }
1996 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
1997
1998 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
1999 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2000 xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
2001}
2002
2003void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2004 struct usb_device *udev, unsigned int ep_index)
2005{
2006 struct xhci_dequeue_state deq_state;
2007 struct xhci_virt_ep *ep;
2008
2009 xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
2010 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2011 /* We need to move the HW's dequeue pointer past this TD,
2012 * or it will attempt to resend it on the next doorbell ring.
2013 */
2014 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2015 ep_index, ep->stopped_stream, ep->stopped_td,
2016 &deq_state);
2017
2018 /* HW with the reset endpoint quirk will use the saved dequeue state to
2019 * issue a configure endpoint command later.
2020 */
2021 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2022 xhci_dbg(xhci, "Queueing new dequeue state\n");
2023 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2024 ep_index, ep->stopped_stream, &deq_state);
2025 } else {
2026 /* Better hope no one uses the input context between now and the
2027 * reset endpoint completion!
2028 * XXX: No idea how this hardware will react when stream rings
2029 * are enabled.
2030 */
2031 xhci_dbg(xhci, "Setting up input context for "
2032 "configure endpoint command\n");
2033 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2034 ep_index, &deq_state);
2035 }
2036}
2037
2038/* Deal with stalled endpoints. The core should have sent the control message
2039 * to clear the halt condition. However, we need to make the xHCI hardware
2040 * reset its sequence number, since a device will expect a sequence number of
2041 * zero after the halt condition is cleared.
2042 * Context: in_interrupt
2043 */
2044void xhci_endpoint_reset(struct usb_hcd *hcd,
2045 struct usb_host_endpoint *ep)
2046{
2047 struct xhci_hcd *xhci;
2048 struct usb_device *udev;
2049 unsigned int ep_index;
2050 unsigned long flags;
2051 int ret;
2052 struct xhci_virt_ep *virt_ep;
2053
2054 xhci = hcd_to_xhci(hcd);
2055 udev = (struct usb_device *) ep->hcpriv;
2056 /* Called with a root hub endpoint (or an endpoint that wasn't added
2057 * with xhci_add_endpoint()
2058 */
2059 if (!ep->hcpriv)
2060 return;
2061 ep_index = xhci_get_endpoint_index(&ep->desc);
2062 virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2063 if (!virt_ep->stopped_td) {
2064 xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
2065 ep->desc.bEndpointAddress);
2066 return;
2067 }
2068 if (usb_endpoint_xfer_control(&ep->desc)) {
2069 xhci_dbg(xhci, "Control endpoint stall already handled.\n");
2070 return;
2071 }
2072
2073 xhci_dbg(xhci, "Queueing reset endpoint command\n");
2074 spin_lock_irqsave(&xhci->lock, flags);
2075 ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
2076 /*
2077 * Can't change the ring dequeue pointer until it's transitioned to the
2078 * stopped state, which is only upon a successful reset endpoint
2079 * command. Better hope that last command worked!
2080 */
2081 if (!ret) {
2082 xhci_cleanup_stalled_ring(xhci, udev, ep_index);
2083 kfree(virt_ep->stopped_td);
2084 xhci_ring_cmd_db(xhci);
2085 }
2086 virt_ep->stopped_td = NULL;
2087 virt_ep->stopped_trb = NULL;
2088 virt_ep->stopped_stream = 0;
2089 spin_unlock_irqrestore(&xhci->lock, flags);
2090
2091 if (ret)
2092 xhci_warn(xhci, "FIXME allocate a new ring segment\n");
2093}
2094
2095static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2096 struct usb_device *udev, struct usb_host_endpoint *ep,
2097 unsigned int slot_id)
2098{
2099 int ret;
2100 unsigned int ep_index;
2101 unsigned int ep_state;
2102
2103 if (!ep)
2104 return -EINVAL;
2105 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2106 if (ret <= 0)
2107 return -EINVAL;
2108 if (ep->ss_ep_comp.bmAttributes == 0) {
2109 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2110 " descriptor for ep 0x%x does not support streams\n",
2111 ep->desc.bEndpointAddress);
2112 return -EINVAL;
2113 }
2114
2115 ep_index = xhci_get_endpoint_index(&ep->desc);
2116 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2117 if (ep_state & EP_HAS_STREAMS ||
2118 ep_state & EP_GETTING_STREAMS) {
2119 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2120 "already has streams set up.\n",
2121 ep->desc.bEndpointAddress);
2122 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2123 "dynamic stream context array reallocation.\n");
2124 return -EINVAL;
2125 }
2126 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2127 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2128 "endpoint 0x%x; URBs are pending.\n",
2129 ep->desc.bEndpointAddress);
2130 return -EINVAL;
2131 }
2132 return 0;
2133}
2134
2135static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
2136 unsigned int *num_streams, unsigned int *num_stream_ctxs)
2137{
2138 unsigned int max_streams;
2139
2140 /* The stream context array size must be a power of two */
2141 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
2142 /*
2143 * Find out how many primary stream array entries the host controller
2144 * supports. Later we may use secondary stream arrays (similar to 2nd
2145 * level page entries), but that's an optional feature for xHCI host
2146 * controllers. xHCs must support at least 4 stream IDs.
2147 */
2148 max_streams = HCC_MAX_PSA(xhci->hcc_params);
2149 if (*num_stream_ctxs > max_streams) {
2150 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
2151 max_streams);
2152 *num_stream_ctxs = max_streams;
2153 *num_streams = max_streams;
2154 }
2155}
2156
2157/* Returns an error code if one of the endpoint already has streams.
2158 * This does not change any data structures, it only checks and gathers
2159 * information.
2160 */
2161static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
2162 struct usb_device *udev,
2163 struct usb_host_endpoint **eps, unsigned int num_eps,
2164 unsigned int *num_streams, u32 *changed_ep_bitmask)
2165{
2166 unsigned int max_streams;
2167 unsigned int endpoint_flag;
2168 int i;
2169 int ret;
2170
2171 for (i = 0; i < num_eps; i++) {
2172 ret = xhci_check_streams_endpoint(xhci, udev,
2173 eps[i], udev->slot_id);
2174 if (ret < 0)
2175 return ret;
2176
2177 max_streams = USB_SS_MAX_STREAMS(
2178 eps[i]->ss_ep_comp.bmAttributes);
2179 if (max_streams < (*num_streams - 1)) {
2180 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
2181 eps[i]->desc.bEndpointAddress,
2182 max_streams);
2183 *num_streams = max_streams+1;
2184 }
2185
2186 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
2187 if (*changed_ep_bitmask & endpoint_flag)
2188 return -EINVAL;
2189 *changed_ep_bitmask |= endpoint_flag;
2190 }
2191 return 0;
2192}
2193
2194static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
2195 struct usb_device *udev,
2196 struct usb_host_endpoint **eps, unsigned int num_eps)
2197{
2198 u32 changed_ep_bitmask = 0;
2199 unsigned int slot_id;
2200 unsigned int ep_index;
2201 unsigned int ep_state;
2202 int i;
2203
2204 slot_id = udev->slot_id;
2205 if (!xhci->devs[slot_id])
2206 return 0;
2207
2208 for (i = 0; i < num_eps; i++) {
2209 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2210 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2211 /* Are streams already being freed for the endpoint? */
2212 if (ep_state & EP_GETTING_NO_STREAMS) {
2213 xhci_warn(xhci, "WARN Can't disable streams for "
2214 "endpoint 0x%x\n, "
2215 "streams are being disabled already.",
2216 eps[i]->desc.bEndpointAddress);
2217 return 0;
2218 }
2219 /* Are there actually any streams to free? */
2220 if (!(ep_state & EP_HAS_STREAMS) &&
2221 !(ep_state & EP_GETTING_STREAMS)) {
2222 xhci_warn(xhci, "WARN Can't disable streams for "
2223 "endpoint 0x%x\n, "
2224 "streams are already disabled!",
2225 eps[i]->desc.bEndpointAddress);
2226 xhci_warn(xhci, "WARN xhci_free_streams() called "
2227 "with non-streams endpoint\n");
2228 return 0;
2229 }
2230 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
2231 }
2232 return changed_ep_bitmask;
2233}
2234
2235/*
2236 * The USB device drivers use this function (though the HCD interface in USB
2237 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
2238 * coordinate mass storage command queueing across multiple endpoints (basically
2239 * a stream ID == a task ID).
2240 *
2241 * Setting up streams involves allocating the same size stream context array
2242 * for each endpoint and issuing a configure endpoint command for all endpoints.
2243 *
2244 * Don't allow the call to succeed if one endpoint only supports one stream
2245 * (which means it doesn't support streams at all).
2246 *
2247 * Drivers may get less stream IDs than they asked for, if the host controller
2248 * hardware or endpoints claim they can't support the number of requested
2249 * stream IDs.
2250 */
2251int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
2252 struct usb_host_endpoint **eps, unsigned int num_eps,
2253 unsigned int num_streams, gfp_t mem_flags)
2254{
2255 int i, ret;
2256 struct xhci_hcd *xhci;
2257 struct xhci_virt_device *vdev;
2258 struct xhci_command *config_cmd;
2259 unsigned int ep_index;
2260 unsigned int num_stream_ctxs;
2261 unsigned long flags;
2262 u32 changed_ep_bitmask = 0;
2263
2264 if (!eps)
2265 return -EINVAL;
2266
2267 /* Add one to the number of streams requested to account for
2268 * stream 0 that is reserved for xHCI usage.
2269 */
2270 num_streams += 1;
2271 xhci = hcd_to_xhci(hcd);
2272 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
2273 num_streams);
2274
2275 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
2276 if (!config_cmd) {
2277 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
2278 return -ENOMEM;
2279 }
2280
2281 /* Check to make sure all endpoints are not already configured for
2282 * streams. While we're at it, find the maximum number of streams that
2283 * all the endpoints will support and check for duplicate endpoints.
2284 */
2285 spin_lock_irqsave(&xhci->lock, flags);
2286 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
2287 num_eps, &num_streams, &changed_ep_bitmask);
2288 if (ret < 0) {
2289 xhci_free_command(xhci, config_cmd);
2290 spin_unlock_irqrestore(&xhci->lock, flags);
2291 return ret;
2292 }
2293 if (num_streams <= 1) {
2294 xhci_warn(xhci, "WARN: endpoints can't handle "
2295 "more than one stream.\n");
2296 xhci_free_command(xhci, config_cmd);
2297 spin_unlock_irqrestore(&xhci->lock, flags);
2298 return -EINVAL;
2299 }
2300 vdev = xhci->devs[udev->slot_id];
2301 /* Mark each endpoint as being in transition, so
2302 * xhci_urb_enqueue() will reject all URBs.
2303 */
2304 for (i = 0; i < num_eps; i++) {
2305 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2306 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
2307 }
2308 spin_unlock_irqrestore(&xhci->lock, flags);
2309
2310 /* Setup internal data structures and allocate HW data structures for
2311 * streams (but don't install the HW structures in the input context
2312 * until we're sure all memory allocation succeeded).
2313 */
2314 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
2315 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
2316 num_stream_ctxs, num_streams);
2317
2318 for (i = 0; i < num_eps; i++) {
2319 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2320 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
2321 num_stream_ctxs,
2322 num_streams, mem_flags);
2323 if (!vdev->eps[ep_index].stream_info)
2324 goto cleanup;
2325 /* Set maxPstreams in endpoint context and update deq ptr to
2326 * point to stream context array. FIXME
2327 */
2328 }
2329
2330 /* Set up the input context for a configure endpoint command. */
2331 for (i = 0; i < num_eps; i++) {
2332 struct xhci_ep_ctx *ep_ctx;
2333
2334 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2335 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
2336
2337 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
2338 vdev->out_ctx, ep_index);
2339 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
2340 vdev->eps[ep_index].stream_info);
2341 }
2342 /* Tell the HW to drop its old copy of the endpoint context info
2343 * and add the updated copy from the input context.
2344 */
2345 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
2346 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
2347
2348 /* Issue and wait for the configure endpoint command */
2349 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
2350 false, false);
2351
2352 /* xHC rejected the configure endpoint command for some reason, so we
2353 * leave the old ring intact and free our internal streams data
2354 * structure.
2355 */
2356 if (ret < 0)
2357 goto cleanup;
2358
2359 spin_lock_irqsave(&xhci->lock, flags);
2360 for (i = 0; i < num_eps; i++) {
2361 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2362 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
2363 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
2364 udev->slot_id, ep_index);
2365 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
2366 }
2367 xhci_free_command(xhci, config_cmd);
2368 spin_unlock_irqrestore(&xhci->lock, flags);
2369
2370 /* Subtract 1 for stream 0, which drivers can't use */
2371 return num_streams - 1;
2372
2373cleanup:
2374 /* If it didn't work, free the streams! */
2375 for (i = 0; i < num_eps; i++) {
2376 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2377 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
2378 vdev->eps[ep_index].stream_info = NULL;
2379 /* FIXME Unset maxPstreams in endpoint context and
2380 * update deq ptr to point to normal string ring.
2381 */
2382 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
2383 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
2384 xhci_endpoint_zero(xhci, vdev, eps[i]);
2385 }
2386 xhci_free_command(xhci, config_cmd);
2387 return -ENOMEM;
2388}
2389
2390/* Transition the endpoint from using streams to being a "normal" endpoint
2391 * without streams.
2392 *
2393 * Modify the endpoint context state, submit a configure endpoint command,
2394 * and free all endpoint rings for streams if that completes successfully.
2395 */
2396int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
2397 struct usb_host_endpoint **eps, unsigned int num_eps,
2398 gfp_t mem_flags)
2399{
2400 int i, ret;
2401 struct xhci_hcd *xhci;
2402 struct xhci_virt_device *vdev;
2403 struct xhci_command *command;
2404 unsigned int ep_index;
2405 unsigned long flags;
2406 u32 changed_ep_bitmask;
2407
2408 xhci = hcd_to_xhci(hcd);
2409 vdev = xhci->devs[udev->slot_id];
2410
2411 /* Set up a configure endpoint command to remove the streams rings */
2412 spin_lock_irqsave(&xhci->lock, flags);
2413 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
2414 udev, eps, num_eps);
2415 if (changed_ep_bitmask == 0) {
2416 spin_unlock_irqrestore(&xhci->lock, flags);
2417 return -EINVAL;
2418 }
2419
2420 /* Use the xhci_command structure from the first endpoint. We may have
2421 * allocated too many, but the driver may call xhci_free_streams() for
2422 * each endpoint it grouped into one call to xhci_alloc_streams().
2423 */
2424 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
2425 command = vdev->eps[ep_index].stream_info->free_streams_command;
2426 for (i = 0; i < num_eps; i++) {
2427 struct xhci_ep_ctx *ep_ctx;
2428
2429 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2430 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
2431 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
2432 EP_GETTING_NO_STREAMS;
2433
2434 xhci_endpoint_copy(xhci, command->in_ctx,
2435 vdev->out_ctx, ep_index);
2436 xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
2437 &vdev->eps[ep_index]);
2438 }
2439 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
2440 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
2441 spin_unlock_irqrestore(&xhci->lock, flags);
2442
2443 /* Issue and wait for the configure endpoint command,
2444 * which must succeed.
2445 */
2446 ret = xhci_configure_endpoint(xhci, udev, command,
2447 false, true);
2448
2449 /* xHC rejected the configure endpoint command for some reason, so we
2450 * leave the streams rings intact.
2451 */
2452 if (ret < 0)
2453 return ret;
2454
2455 spin_lock_irqsave(&xhci->lock, flags);
2456 for (i = 0; i < num_eps; i++) {
2457 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2458 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
2459 vdev->eps[ep_index].stream_info = NULL;
2460 /* FIXME Unset maxPstreams in endpoint context and
2461 * update deq ptr to point to normal string ring.
2462 */
2463 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
2464 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
2465 }
2466 spin_unlock_irqrestore(&xhci->lock, flags);
2467
2468 return 0;
2469}
2470
2471/*
2472 * Deletes endpoint resources for endpoints that were active before a Reset
2473 * Device command, or a Disable Slot command. The Reset Device command leaves
2474 * the control endpoint intact, whereas the Disable Slot command deletes it.
2475 *
2476 * Must be called with xhci->lock held.
2477 */
2478void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2479 struct xhci_virt_device *virt_dev, bool drop_control_ep)
2480{
2481 int i;
2482 unsigned int num_dropped_eps = 0;
2483 unsigned int drop_flags = 0;
2484
2485 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
2486 if (virt_dev->eps[i].ring) {
2487 drop_flags |= 1 << i;
2488 num_dropped_eps++;
2489 }
2490 }
2491 xhci->num_active_eps -= num_dropped_eps;
2492 if (num_dropped_eps)
2493 xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, "
2494 "%u now active.\n",
2495 num_dropped_eps, drop_flags,
2496 xhci->num_active_eps);
2497}
2498
2499/*
2500 * This submits a Reset Device Command, which will set the device state to 0,
2501 * set the device address to 0, and disable all the endpoints except the default
2502 * control endpoint. The USB core should come back and call
2503 * xhci_address_device(), and then re-set up the configuration. If this is
2504 * called because of a usb_reset_and_verify_device(), then the old alternate
2505 * settings will be re-installed through the normal bandwidth allocation
2506 * functions.
2507 *
2508 * Wait for the Reset Device command to finish. Remove all structures
2509 * associated with the endpoints that were disabled. Clear the input device
2510 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
2511 *
2512 * If the virt_dev to be reset does not exist or does not match the udev,
2513 * it means the device is lost, possibly due to the xHC restore error and
2514 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
2515 * re-allocate the device.
2516 */
2517int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
2518{
2519 int ret, i;
2520 unsigned long flags;
2521 struct xhci_hcd *xhci;
2522 unsigned int slot_id;
2523 struct xhci_virt_device *virt_dev;
2524 struct xhci_command *reset_device_cmd;
2525 int timeleft;
2526 int last_freed_endpoint;
2527 struct xhci_slot_ctx *slot_ctx;
2528
2529 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
2530 if (ret <= 0)
2531 return ret;
2532 xhci = hcd_to_xhci(hcd);
2533 slot_id = udev->slot_id;
2534 virt_dev = xhci->devs[slot_id];
2535 if (!virt_dev) {
2536 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
2537 "not exist. Re-allocate the device\n", slot_id);
2538 ret = xhci_alloc_dev(hcd, udev);
2539 if (ret == 1)
2540 return 0;
2541 else
2542 return -EINVAL;
2543 }
2544
2545 if (virt_dev->udev != udev) {
2546 /* If the virt_dev and the udev does not match, this virt_dev
2547 * may belong to another udev.
2548 * Re-allocate the device.
2549 */
2550 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
2551 "not match the udev. Re-allocate the device\n",
2552 slot_id);
2553 ret = xhci_alloc_dev(hcd, udev);
2554 if (ret == 1)
2555 return 0;
2556 else
2557 return -EINVAL;
2558 }
2559
2560 /* If device is not setup, there is no point in resetting it */
2561 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
2562 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
2563 SLOT_STATE_DISABLED)
2564 return 0;
2565
2566 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
2567 /* Allocate the command structure that holds the struct completion.
2568 * Assume we're in process context, since the normal device reset
2569 * process has to wait for the device anyway. Storage devices are
2570 * reset as part of error handling, so use GFP_NOIO instead of
2571 * GFP_KERNEL.
2572 */
2573 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
2574 if (!reset_device_cmd) {
2575 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
2576 return -ENOMEM;
2577 }
2578
2579 /* Attempt to submit the Reset Device command to the command ring */
2580 spin_lock_irqsave(&xhci->lock, flags);
2581 reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
2582
2583 /* Enqueue pointer can be left pointing to the link TRB,
2584 * we must handle that
2585 */
2586 if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control))
2587 reset_device_cmd->command_trb =
2588 xhci->cmd_ring->enq_seg->next->trbs;
2589
2590 list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
2591 ret = xhci_queue_reset_device(xhci, slot_id);
2592 if (ret) {
2593 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2594 list_del(&reset_device_cmd->cmd_list);
2595 spin_unlock_irqrestore(&xhci->lock, flags);
2596 goto command_cleanup;
2597 }
2598 xhci_ring_cmd_db(xhci);
2599 spin_unlock_irqrestore(&xhci->lock, flags);
2600
2601 /* Wait for the Reset Device command to finish */
2602 timeleft = wait_for_completion_interruptible_timeout(
2603 reset_device_cmd->completion,
2604 USB_CTRL_SET_TIMEOUT);
2605 if (timeleft <= 0) {
2606 xhci_warn(xhci, "%s while waiting for reset device command\n",
2607 timeleft == 0 ? "Timeout" : "Signal");
2608 spin_lock_irqsave(&xhci->lock, flags);
2609 /* The timeout might have raced with the event ring handler, so
2610 * only delete from the list if the item isn't poisoned.
2611 */
2612 if (reset_device_cmd->cmd_list.next != LIST_POISON1)
2613 list_del(&reset_device_cmd->cmd_list);
2614 spin_unlock_irqrestore(&xhci->lock, flags);
2615 ret = -ETIME;
2616 goto command_cleanup;
2617 }
2618
2619 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
2620 * unless we tried to reset a slot ID that wasn't enabled,
2621 * or the device wasn't in the addressed or configured state.
2622 */
2623 ret = reset_device_cmd->status;
2624 switch (ret) {
2625 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
2626 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
2627 xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
2628 slot_id,
2629 xhci_get_slot_state(xhci, virt_dev->out_ctx));
2630 xhci_info(xhci, "Not freeing device rings.\n");
2631 /* Don't treat this as an error. May change my mind later. */
2632 ret = 0;
2633 goto command_cleanup;
2634 case COMP_SUCCESS:
2635 xhci_dbg(xhci, "Successful reset device command.\n");
2636 break;
2637 default:
2638 if (xhci_is_vendor_info_code(xhci, ret))
2639 break;
2640 xhci_warn(xhci, "Unknown completion code %u for "
2641 "reset device command.\n", ret);
2642 ret = -EINVAL;
2643 goto command_cleanup;
2644 }
2645
2646 /* Free up host controller endpoint resources */
2647 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2648 spin_lock_irqsave(&xhci->lock, flags);
2649 /* Don't delete the default control endpoint resources */
2650 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
2651 spin_unlock_irqrestore(&xhci->lock, flags);
2652 }
2653
2654 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
2655 last_freed_endpoint = 1;
2656 for (i = 1; i < 31; ++i) {
2657 struct xhci_virt_ep *ep = &virt_dev->eps[i];
2658
2659 if (ep->ep_state & EP_HAS_STREAMS) {
2660 xhci_free_stream_info(xhci, ep->stream_info);
2661 ep->stream_info = NULL;
2662 ep->ep_state &= ~EP_HAS_STREAMS;
2663 }
2664
2665 if (ep->ring) {
2666 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2667 last_freed_endpoint = i;
2668 }
2669 }
2670 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
2671 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
2672 ret = 0;
2673
2674command_cleanup:
2675 xhci_free_command(xhci, reset_device_cmd);
2676 return ret;
2677}
2678
2679/*
2680 * At this point, the struct usb_device is about to go away, the device has
2681 * disconnected, and all traffic has been stopped and the endpoints have been
2682 * disabled. Free any HC data structures associated with that device.
2683 */
2684void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
2685{
2686 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2687 struct xhci_virt_device *virt_dev;
2688 unsigned long flags;
2689 u32 state;
2690 int i, ret;
2691
2692 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2693 /* If the host is halted due to driver unload, we still need to free the
2694 * device.
2695 */
2696 if (ret <= 0 && ret != -ENODEV)
2697 return;
2698
2699 virt_dev = xhci->devs[udev->slot_id];
2700
2701 /* Stop any wayward timer functions (which may grab the lock) */
2702 for (i = 0; i < 31; ++i) {
2703 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
2704 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
2705 }
2706
2707 spin_lock_irqsave(&xhci->lock, flags);
2708 /* Don't disable the slot if the host controller is dead. */
2709 state = xhci_readl(xhci, &xhci->op_regs->status);
2710 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
2711 (xhci->xhc_state & XHCI_STATE_HALTED)) {
2712 xhci_free_virt_device(xhci, udev->slot_id);
2713 spin_unlock_irqrestore(&xhci->lock, flags);
2714 return;
2715 }
2716
2717 if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
2718 spin_unlock_irqrestore(&xhci->lock, flags);
2719 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2720 return;
2721 }
2722 xhci_ring_cmd_db(xhci);
2723 spin_unlock_irqrestore(&xhci->lock, flags);
2724 /*
2725 * Event command completion handler will free any data structures
2726 * associated with the slot. XXX Can free sleep?
2727 */
2728}
2729
2730/*
2731 * Checks if we have enough host controller resources for the default control
2732 * endpoint.
2733 *
2734 * Must be called with xhci->lock held.
2735 */
2736static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
2737{
2738 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
2739 xhci_dbg(xhci, "Not enough ep ctxs: "
2740 "%u active, need to add 1, limit is %u.\n",
2741 xhci->num_active_eps, xhci->limit_active_eps);
2742 return -ENOMEM;
2743 }
2744 xhci->num_active_eps += 1;
2745 xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n",
2746 xhci->num_active_eps);
2747 return 0;
2748}
2749
2750
2751/*
2752 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
2753 * timed out, or allocating memory failed. Returns 1 on success.
2754 */
2755int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
2756{
2757 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2758 unsigned long flags;
2759 int timeleft;
2760 int ret;
2761
2762 spin_lock_irqsave(&xhci->lock, flags);
2763 ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
2764 if (ret) {
2765 spin_unlock_irqrestore(&xhci->lock, flags);
2766 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2767 return 0;
2768 }
2769 xhci_ring_cmd_db(xhci);
2770 spin_unlock_irqrestore(&xhci->lock, flags);
2771
2772 /* XXX: how much time for xHC slot assignment? */
2773 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
2774 USB_CTRL_SET_TIMEOUT);
2775 if (timeleft <= 0) {
2776 xhci_warn(xhci, "%s while waiting for a slot\n",
2777 timeleft == 0 ? "Timeout" : "Signal");
2778 /* FIXME cancel the enable slot request */
2779 return 0;
2780 }
2781
2782 if (!xhci->slot_id) {
2783 xhci_err(xhci, "Error while assigning device slot ID\n");
2784 return 0;
2785 }
2786
2787 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2788 spin_lock_irqsave(&xhci->lock, flags);
2789 ret = xhci_reserve_host_control_ep_resources(xhci);
2790 if (ret) {
2791 spin_unlock_irqrestore(&xhci->lock, flags);
2792 xhci_warn(xhci, "Not enough host resources, "
2793 "active endpoint contexts = %u\n",
2794 xhci->num_active_eps);
2795 goto disable_slot;
2796 }
2797 spin_unlock_irqrestore(&xhci->lock, flags);
2798 }
2799 /* Use GFP_NOIO, since this function can be called from
2800 * xhci_discover_or_reset_device(), which may be called as part of
2801 * mass storage driver error handling.
2802 */
2803 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
2804 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
2805 goto disable_slot;
2806 }
2807 udev->slot_id = xhci->slot_id;
2808 /* Is this a LS or FS device under a HS hub? */
2809 /* Hub or peripherial? */
2810 return 1;
2811
2812disable_slot:
2813 /* Disable slot, if we can do it without mem alloc */
2814 spin_lock_irqsave(&xhci->lock, flags);
2815 if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
2816 xhci_ring_cmd_db(xhci);
2817 spin_unlock_irqrestore(&xhci->lock, flags);
2818 return 0;
2819}
2820
2821/*
2822 * Issue an Address Device command (which will issue a SetAddress request to
2823 * the device).
2824 * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
2825 * we should only issue and wait on one address command at the same time.
2826 *
2827 * We add one to the device address issued by the hardware because the USB core
2828 * uses address 1 for the root hubs (even though they're not really devices).
2829 */
2830int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
2831{
2832 unsigned long flags;
2833 int timeleft;
2834 struct xhci_virt_device *virt_dev;
2835 int ret = 0;
2836 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2837 struct xhci_slot_ctx *slot_ctx;
2838 struct xhci_input_control_ctx *ctrl_ctx;
2839 u64 temp_64;
2840
2841 if (!udev->slot_id) {
2842 xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
2843 return -EINVAL;
2844 }
2845
2846 virt_dev = xhci->devs[udev->slot_id];
2847
2848 if (WARN_ON(!virt_dev)) {
2849 /*
2850 * In plug/unplug torture test with an NEC controller,
2851 * a zero-dereference was observed once due to virt_dev = 0.
2852 * Print useful debug rather than crash if it is observed again!
2853 */
2854 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
2855 udev->slot_id);
2856 return -EINVAL;
2857 }
2858
2859 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2860 /*
2861 * If this is the first Set Address since device plug-in or
2862 * virt_device realloaction after a resume with an xHCI power loss,
2863 * then set up the slot context.
2864 */
2865 if (!slot_ctx->dev_info)
2866 xhci_setup_addressable_virt_dev(xhci, udev);
2867 /* Otherwise, update the control endpoint ring enqueue pointer. */
2868 else
2869 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
2870 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
2871 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
2872
2873 spin_lock_irqsave(&xhci->lock, flags);
2874 ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
2875 udev->slot_id);
2876 if (ret) {
2877 spin_unlock_irqrestore(&xhci->lock, flags);
2878 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2879 return ret;
2880 }
2881 xhci_ring_cmd_db(xhci);
2882 spin_unlock_irqrestore(&xhci->lock, flags);
2883
2884 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
2885 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
2886 USB_CTRL_SET_TIMEOUT);
2887 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
2888 * the SetAddress() "recovery interval" required by USB and aborting the
2889 * command on a timeout.
2890 */
2891 if (timeleft <= 0) {
2892 xhci_warn(xhci, "%s while waiting for a slot\n",
2893 timeleft == 0 ? "Timeout" : "Signal");
2894 /* FIXME cancel the address device command */
2895 return -ETIME;
2896 }
2897
2898 switch (virt_dev->cmd_status) {
2899 case COMP_CTX_STATE:
2900 case COMP_EBADSLT:
2901 xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
2902 udev->slot_id);
2903 ret = -EINVAL;
2904 break;
2905 case COMP_TX_ERR:
2906 dev_warn(&udev->dev, "Device not responding to set address.\n");
2907 ret = -EPROTO;
2908 break;
2909 case COMP_DEV_ERR:
2910 dev_warn(&udev->dev, "ERROR: Incompatible device for address "
2911 "device command.\n");
2912 ret = -ENODEV;
2913 break;
2914 case COMP_SUCCESS:
2915 xhci_dbg(xhci, "Successful Address Device command\n");
2916 break;
2917 default:
2918 xhci_err(xhci, "ERROR: unexpected command completion "
2919 "code 0x%x.\n", virt_dev->cmd_status);
2920 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
2921 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
2922 ret = -EINVAL;
2923 break;
2924 }
2925 if (ret) {
2926 return ret;
2927 }
2928 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
2929 xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
2930 xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
2931 udev->slot_id,
2932 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
2933 (unsigned long long)
2934 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
2935 xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
2936 (unsigned long long)virt_dev->out_ctx->dma);
2937 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
2938 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
2939 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
2940 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
2941 /*
2942 * USB core uses address 1 for the roothubs, so we add one to the
2943 * address given back to us by the HC.
2944 */
2945 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
2946 /* Use kernel assigned address for devices; store xHC assigned
2947 * address locally. */
2948 virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
2949 + 1;
2950 /* Zero the input context control for later use */
2951 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
2952 ctrl_ctx->add_flags = 0;
2953 ctrl_ctx->drop_flags = 0;
2954
2955 xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address);
2956
2957 return 0;
2958}
2959
2960/* Once a hub descriptor is fetched for a device, we need to update the xHC's
2961 * internal data structures for the device.
2962 */
2963int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
2964 struct usb_tt *tt, gfp_t mem_flags)
2965{
2966 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2967 struct xhci_virt_device *vdev;
2968 struct xhci_command *config_cmd;
2969 struct xhci_input_control_ctx *ctrl_ctx;
2970 struct xhci_slot_ctx *slot_ctx;
2971 unsigned long flags;
2972 unsigned think_time;
2973 int ret;
2974
2975 /* Ignore root hubs */
2976 if (!hdev->parent)
2977 return 0;
2978
2979 vdev = xhci->devs[hdev->slot_id];
2980 if (!vdev) {
2981 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
2982 return -EINVAL;
2983 }
2984 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
2985 if (!config_cmd) {
2986 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
2987 return -ENOMEM;
2988 }
2989
2990 spin_lock_irqsave(&xhci->lock, flags);
2991 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
2992 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
2993 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2994 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
2995 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
2996 if (tt->multi)
2997 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
2998 if (xhci->hci_version > 0x95) {
2999 xhci_dbg(xhci, "xHCI version %x needs hub "
3000 "TT think time and number of ports\n",
3001 (unsigned int) xhci->hci_version);
3002 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
3003 /* Set TT think time - convert from ns to FS bit times.
3004 * 0 = 8 FS bit times, 1 = 16 FS bit times,
3005 * 2 = 24 FS bit times, 3 = 32 FS bit times.
3006 *
3007 * xHCI 1.0: this field shall be 0 if the device is not a
3008 * High-spped hub.
3009 */
3010 think_time = tt->think_time;
3011 if (think_time != 0)
3012 think_time = (think_time / 666) - 1;
3013 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
3014 slot_ctx->tt_info |=
3015 cpu_to_le32(TT_THINK_TIME(think_time));
3016 } else {
3017 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
3018 "TT think time or number of ports\n",
3019 (unsigned int) xhci->hci_version);
3020 }
3021 slot_ctx->dev_state = 0;
3022 spin_unlock_irqrestore(&xhci->lock, flags);
3023
3024 xhci_dbg(xhci, "Set up %s for hub device.\n",
3025 (xhci->hci_version > 0x95) ?
3026 "configure endpoint" : "evaluate context");
3027 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
3028 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
3029
3030 /* Issue and wait for the configure endpoint or
3031 * evaluate context command.
3032 */
3033 if (xhci->hci_version > 0x95)
3034 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
3035 false, false);
3036 else
3037 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
3038 true, false);
3039
3040 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
3041 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
3042
3043 xhci_free_command(xhci, config_cmd);
3044 return ret;
3045}
3046
3047int xhci_get_frame(struct usb_hcd *hcd)
3048{
3049 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3050 /* EHCI mods by the periodic size. Why? */
3051 return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
3052}
3053
3054MODULE_DESCRIPTION(DRIVER_DESC);
3055MODULE_AUTHOR(DRIVER_AUTHOR);
3056MODULE_LICENSE("GPL");
3057
3058static int __init xhci_hcd_init(void)
3059{
3060#ifdef CONFIG_PCI
3061 int retval = 0;
3062
3063 retval = xhci_register_pci();
3064
3065 if (retval < 0) {
3066 printk(KERN_DEBUG "Problem registering PCI driver.");
3067 return retval;
3068 }
3069#endif
3070 /*
3071 * Check the compiler generated sizes of structures that must be laid
3072 * out in specific ways for hardware access.
3073 */
3074 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
3075 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
3076 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
3077 /* xhci_device_control has eight fields, and also
3078 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
3079 */
3080 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
3081 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
3082 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
3083 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
3084 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
3085 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
3086 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
3087 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
3088 return 0;
3089}
3090module_init(xhci_hcd_init);
3091
3092static void __exit xhci_hcd_cleanup(void)
3093{
3094#ifdef CONFIG_PCI
3095 xhci_unregister_pci();
3096#endif
3097}
3098module_exit(xhci_hcd_cleanup);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/pci.h>
12#include <linux/iopoll.h>
13#include <linux/irq.h>
14#include <linux/log2.h>
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/slab.h>
18#include <linux/dmi.h>
19#include <linux/dma-mapping.h>
20
21#include "xhci.h"
22#include "xhci-trace.h"
23#include "xhci-mtk.h"
24#include "xhci-debugfs.h"
25#include "xhci-dbgcap.h"
26
27#define DRIVER_AUTHOR "Sarah Sharp"
28#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29
30#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31
32/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33static int link_quirk;
34module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36
37static unsigned long long quirks;
38module_param(quirks, ullong, S_IRUGO);
39MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40
41static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42{
43 struct xhci_segment *seg = ring->first_seg;
44
45 if (!td || !td->start_seg)
46 return false;
47 do {
48 if (seg == td->start_seg)
49 return true;
50 seg = seg->next;
51 } while (seg && seg != ring->first_seg);
52
53 return false;
54}
55
56/*
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
62 *
63 * Returns negative errno, or zero on success
64 *
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 */
69int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
70{
71 u32 result;
72 int ret;
73
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
76 result == U32_MAX,
77 1, usec);
78 if (result == U32_MAX) /* card removed */
79 return -ENODEV;
80
81 return ret;
82}
83
84/*
85 * Disable interrupts and begin the xHCI halting process.
86 */
87void xhci_quiesce(struct xhci_hcd *xhci)
88{
89 u32 halted;
90 u32 cmd;
91 u32 mask;
92
93 mask = ~(XHCI_IRQS);
94 halted = readl(&xhci->op_regs->status) & STS_HALT;
95 if (!halted)
96 mask &= ~CMD_RUN;
97
98 cmd = readl(&xhci->op_regs->command);
99 cmd &= mask;
100 writel(cmd, &xhci->op_regs->command);
101}
102
103/*
104 * Force HC into halt state.
105 *
106 * Disable any IRQs and clear the run/stop bit.
107 * HC will complete any current and actively pipelined transactions, and
108 * should halt within 16 ms of the run/stop bit being cleared.
109 * Read HC Halted bit in the status register to see when the HC is finished.
110 */
111int xhci_halt(struct xhci_hcd *xhci)
112{
113 int ret;
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
115 xhci_quiesce(xhci);
116
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
119 if (ret) {
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
121 return ret;
122 }
123 xhci->xhc_state |= XHCI_STATE_HALTED;
124 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
125 return ret;
126}
127
128/*
129 * Set the run bit and wait for the host to be running.
130 */
131int xhci_start(struct xhci_hcd *xhci)
132{
133 u32 temp;
134 int ret;
135
136 temp = readl(&xhci->op_regs->command);
137 temp |= (CMD_RUN);
138 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
139 temp);
140 writel(temp, &xhci->op_regs->command);
141
142 /*
143 * Wait for the HCHalted Status bit to be 0 to indicate the host is
144 * running.
145 */
146 ret = xhci_handshake(&xhci->op_regs->status,
147 STS_HALT, 0, XHCI_MAX_HALT_USEC);
148 if (ret == -ETIMEDOUT)
149 xhci_err(xhci, "Host took too long to start, "
150 "waited %u microseconds.\n",
151 XHCI_MAX_HALT_USEC);
152 if (!ret)
153 /* clear state flags. Including dying, halted or removing */
154 xhci->xhc_state = 0;
155
156 return ret;
157}
158
159/*
160 * Reset a halted HC.
161 *
162 * This resets pipelines, timers, counters, state machines, etc.
163 * Transactions will be terminated immediately, and operational registers
164 * will be set to their defaults.
165 */
166int xhci_reset(struct xhci_hcd *xhci)
167{
168 u32 command;
169 u32 state;
170 int ret;
171
172 state = readl(&xhci->op_regs->status);
173
174 if (state == ~(u32)0) {
175 xhci_warn(xhci, "Host not accessible, reset failed.\n");
176 return -ENODEV;
177 }
178
179 if ((state & STS_HALT) == 0) {
180 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
181 return 0;
182 }
183
184 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
185 command = readl(&xhci->op_regs->command);
186 command |= CMD_RESET;
187 writel(command, &xhci->op_regs->command);
188
189 /* Existing Intel xHCI controllers require a delay of 1 mS,
190 * after setting the CMD_RESET bit, and before accessing any
191 * HC registers. This allows the HC to complete the
192 * reset operation and be ready for HC register access.
193 * Without this delay, the subsequent HC register access,
194 * may result in a system hang very rarely.
195 */
196 if (xhci->quirks & XHCI_INTEL_HOST)
197 udelay(1000);
198
199 ret = xhci_handshake(&xhci->op_regs->command,
200 CMD_RESET, 0, 10 * 1000 * 1000);
201 if (ret)
202 return ret;
203
204 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
205 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
206
207 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
208 "Wait for controller to be ready for doorbell rings");
209 /*
210 * xHCI cannot write to any doorbells or operational registers other
211 * than status until the "Controller Not Ready" flag is cleared.
212 */
213 ret = xhci_handshake(&xhci->op_regs->status,
214 STS_CNR, 0, 10 * 1000 * 1000);
215
216 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
217 xhci->usb2_rhub.bus_state.suspended_ports = 0;
218 xhci->usb2_rhub.bus_state.resuming_ports = 0;
219 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
220 xhci->usb3_rhub.bus_state.suspended_ports = 0;
221 xhci->usb3_rhub.bus_state.resuming_ports = 0;
222
223 return ret;
224}
225
226static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
227{
228 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
229 int err, i;
230 u64 val;
231
232 /*
233 * Some Renesas controllers get into a weird state if they are
234 * reset while programmed with 64bit addresses (they will preserve
235 * the top half of the address in internal, non visible
236 * registers). You end up with half the address coming from the
237 * kernel, and the other half coming from the firmware. Also,
238 * changing the programming leads to extra accesses even if the
239 * controller is supposed to be halted. The controller ends up with
240 * a fatal fault, and is then ripe for being properly reset.
241 *
242 * Special care is taken to only apply this if the device is behind
243 * an iommu. Doing anything when there is no iommu is definitely
244 * unsafe...
245 */
246 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
247 return;
248
249 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
250
251 /* Clear HSEIE so that faults do not get signaled */
252 val = readl(&xhci->op_regs->command);
253 val &= ~CMD_HSEIE;
254 writel(val, &xhci->op_regs->command);
255
256 /* Clear HSE (aka FATAL) */
257 val = readl(&xhci->op_regs->status);
258 val |= STS_FATAL;
259 writel(val, &xhci->op_regs->status);
260
261 /* Now zero the registers, and brace for impact */
262 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
263 if (upper_32_bits(val))
264 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
265 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
268
269 for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
270 struct xhci_intr_reg __iomem *ir;
271
272 ir = &xhci->run_regs->ir_set[i];
273 val = xhci_read_64(xhci, &ir->erst_base);
274 if (upper_32_bits(val))
275 xhci_write_64(xhci, 0, &ir->erst_base);
276 val= xhci_read_64(xhci, &ir->erst_dequeue);
277 if (upper_32_bits(val))
278 xhci_write_64(xhci, 0, &ir->erst_dequeue);
279 }
280
281 /* Wait for the fault to appear. It will be cleared on reset */
282 err = xhci_handshake(&xhci->op_regs->status,
283 STS_FATAL, STS_FATAL,
284 XHCI_MAX_HALT_USEC);
285 if (!err)
286 xhci_info(xhci, "Fault detected\n");
287}
288
289#ifdef CONFIG_USB_PCI
290/*
291 * Set up MSI
292 */
293static int xhci_setup_msi(struct xhci_hcd *xhci)
294{
295 int ret;
296 /*
297 * TODO:Check with MSI Soc for sysdev
298 */
299 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
300
301 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
302 if (ret < 0) {
303 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
304 "failed to allocate MSI entry");
305 return ret;
306 }
307
308 ret = request_irq(pdev->irq, xhci_msi_irq,
309 0, "xhci_hcd", xhci_to_hcd(xhci));
310 if (ret) {
311 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
312 "disable MSI interrupt");
313 pci_free_irq_vectors(pdev);
314 }
315
316 return ret;
317}
318
319/*
320 * Set up MSI-X
321 */
322static int xhci_setup_msix(struct xhci_hcd *xhci)
323{
324 int i, ret = 0;
325 struct usb_hcd *hcd = xhci_to_hcd(xhci);
326 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
327
328 /*
329 * calculate number of msi-x vectors supported.
330 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
331 * with max number of interrupters based on the xhci HCSPARAMS1.
332 * - num_online_cpus: maximum msi-x vectors per CPUs core.
333 * Add additional 1 vector to ensure always available interrupt.
334 */
335 xhci->msix_count = min(num_online_cpus() + 1,
336 HCS_MAX_INTRS(xhci->hcs_params1));
337
338 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
339 PCI_IRQ_MSIX);
340 if (ret < 0) {
341 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
342 "Failed to enable MSI-X");
343 return ret;
344 }
345
346 for (i = 0; i < xhci->msix_count; i++) {
347 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
348 "xhci_hcd", xhci_to_hcd(xhci));
349 if (ret)
350 goto disable_msix;
351 }
352
353 hcd->msix_enabled = 1;
354 return ret;
355
356disable_msix:
357 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
358 while (--i >= 0)
359 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
360 pci_free_irq_vectors(pdev);
361 return ret;
362}
363
364/* Free any IRQs and disable MSI-X */
365static void xhci_cleanup_msix(struct xhci_hcd *xhci)
366{
367 struct usb_hcd *hcd = xhci_to_hcd(xhci);
368 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
369
370 if (xhci->quirks & XHCI_PLAT)
371 return;
372
373 /* return if using legacy interrupt */
374 if (hcd->irq > 0)
375 return;
376
377 if (hcd->msix_enabled) {
378 int i;
379
380 for (i = 0; i < xhci->msix_count; i++)
381 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
382 } else {
383 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
384 }
385
386 pci_free_irq_vectors(pdev);
387 hcd->msix_enabled = 0;
388}
389
390static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
391{
392 struct usb_hcd *hcd = xhci_to_hcd(xhci);
393
394 if (hcd->msix_enabled) {
395 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
396 int i;
397
398 for (i = 0; i < xhci->msix_count; i++)
399 synchronize_irq(pci_irq_vector(pdev, i));
400 }
401}
402
403static int xhci_try_enable_msi(struct usb_hcd *hcd)
404{
405 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
406 struct pci_dev *pdev;
407 int ret;
408
409 /* The xhci platform device has set up IRQs through usb_add_hcd. */
410 if (xhci->quirks & XHCI_PLAT)
411 return 0;
412
413 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
414 /*
415 * Some Fresco Logic host controllers advertise MSI, but fail to
416 * generate interrupts. Don't even try to enable MSI.
417 */
418 if (xhci->quirks & XHCI_BROKEN_MSI)
419 goto legacy_irq;
420
421 /* unregister the legacy interrupt */
422 if (hcd->irq)
423 free_irq(hcd->irq, hcd);
424 hcd->irq = 0;
425
426 ret = xhci_setup_msix(xhci);
427 if (ret)
428 /* fall back to msi*/
429 ret = xhci_setup_msi(xhci);
430
431 if (!ret) {
432 hcd->msi_enabled = 1;
433 return 0;
434 }
435
436 if (!pdev->irq) {
437 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
438 return -EINVAL;
439 }
440
441 legacy_irq:
442 if (!strlen(hcd->irq_descr))
443 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
444 hcd->driver->description, hcd->self.busnum);
445
446 /* fall back to legacy interrupt*/
447 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
448 hcd->irq_descr, hcd);
449 if (ret) {
450 xhci_err(xhci, "request interrupt %d failed\n",
451 pdev->irq);
452 return ret;
453 }
454 hcd->irq = pdev->irq;
455 return 0;
456}
457
458#else
459
460static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
461{
462 return 0;
463}
464
465static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
466{
467}
468
469static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
470{
471}
472
473#endif
474
475static void compliance_mode_recovery(struct timer_list *t)
476{
477 struct xhci_hcd *xhci;
478 struct usb_hcd *hcd;
479 struct xhci_hub *rhub;
480 u32 temp;
481 int i;
482
483 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
484 rhub = &xhci->usb3_rhub;
485
486 for (i = 0; i < rhub->num_ports; i++) {
487 temp = readl(rhub->ports[i]->addr);
488 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
489 /*
490 * Compliance Mode Detected. Letting USB Core
491 * handle the Warm Reset
492 */
493 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
494 "Compliance mode detected->port %d",
495 i + 1);
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Attempting compliance mode recovery");
498 hcd = xhci->shared_hcd;
499
500 if (hcd->state == HC_STATE_SUSPENDED)
501 usb_hcd_resume_root_hub(hcd);
502
503 usb_hcd_poll_rh_status(hcd);
504 }
505 }
506
507 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
508 mod_timer(&xhci->comp_mode_recovery_timer,
509 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
510}
511
512/*
513 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
514 * that causes ports behind that hardware to enter compliance mode sometimes.
515 * The quirk creates a timer that polls every 2 seconds the link state of
516 * each host controller's port and recovers it by issuing a Warm reset
517 * if Compliance mode is detected, otherwise the port will become "dead" (no
518 * device connections or disconnections will be detected anymore). Becasue no
519 * status event is generated when entering compliance mode (per xhci spec),
520 * this quirk is needed on systems that have the failing hardware installed.
521 */
522static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
523{
524 xhci->port_status_u0 = 0;
525 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
526 0);
527 xhci->comp_mode_recovery_timer.expires = jiffies +
528 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
529
530 add_timer(&xhci->comp_mode_recovery_timer);
531 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
532 "Compliance mode recovery timer initialized");
533}
534
535/*
536 * This function identifies the systems that have installed the SN65LVPE502CP
537 * USB3.0 re-driver and that need the Compliance Mode Quirk.
538 * Systems:
539 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
540 */
541static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
542{
543 const char *dmi_product_name, *dmi_sys_vendor;
544
545 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
546 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
547 if (!dmi_product_name || !dmi_sys_vendor)
548 return false;
549
550 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
551 return false;
552
553 if (strstr(dmi_product_name, "Z420") ||
554 strstr(dmi_product_name, "Z620") ||
555 strstr(dmi_product_name, "Z820") ||
556 strstr(dmi_product_name, "Z1 Workstation"))
557 return true;
558
559 return false;
560}
561
562static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
563{
564 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
565}
566
567
568/*
569 * Initialize memory for HCD and xHC (one-time init).
570 *
571 * Program the PAGESIZE register, initialize the device context array, create
572 * device contexts (?), set up a command ring segment (or two?), create event
573 * ring (one for now).
574 */
575static int xhci_init(struct usb_hcd *hcd)
576{
577 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
578 int retval = 0;
579
580 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
581 spin_lock_init(&xhci->lock);
582 if (xhci->hci_version == 0x95 && link_quirk) {
583 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
584 "QUIRK: Not clearing Link TRB chain bits.");
585 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
586 } else {
587 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
588 "xHCI doesn't need link TRB QUIRK");
589 }
590 retval = xhci_mem_init(xhci, GFP_KERNEL);
591 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
592
593 /* Initializing Compliance Mode Recovery Data If Needed */
594 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
595 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
596 compliance_mode_recovery_timer_init(xhci);
597 }
598
599 return retval;
600}
601
602/*-------------------------------------------------------------------------*/
603
604
605static int xhci_run_finished(struct xhci_hcd *xhci)
606{
607 if (xhci_start(xhci)) {
608 xhci_halt(xhci);
609 return -ENODEV;
610 }
611 xhci->shared_hcd->state = HC_STATE_RUNNING;
612 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
613
614 if (xhci->quirks & XHCI_NEC_HOST)
615 xhci_ring_cmd_db(xhci);
616
617 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
618 "Finished xhci_run for USB3 roothub");
619 return 0;
620}
621
622/*
623 * Start the HC after it was halted.
624 *
625 * This function is called by the USB core when the HC driver is added.
626 * Its opposite is xhci_stop().
627 *
628 * xhci_init() must be called once before this function can be called.
629 * Reset the HC, enable device slot contexts, program DCBAAP, and
630 * set command ring pointer and event ring pointer.
631 *
632 * Setup MSI-X vectors and enable interrupts.
633 */
634int xhci_run(struct usb_hcd *hcd)
635{
636 u32 temp;
637 u64 temp_64;
638 int ret;
639 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
640
641 /* Start the xHCI host controller running only after the USB 2.0 roothub
642 * is setup.
643 */
644
645 hcd->uses_new_polling = 1;
646 if (!usb_hcd_is_primary_hcd(hcd))
647 return xhci_run_finished(xhci);
648
649 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
650
651 ret = xhci_try_enable_msi(hcd);
652 if (ret)
653 return ret;
654
655 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
656 temp_64 &= ~ERST_PTR_MASK;
657 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
658 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
659
660 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
661 "// Set the interrupt modulation register");
662 temp = readl(&xhci->ir_set->irq_control);
663 temp &= ~ER_IRQ_INTERVAL_MASK;
664 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
665 writel(temp, &xhci->ir_set->irq_control);
666
667 /* Set the HCD state before we enable the irqs */
668 temp = readl(&xhci->op_regs->command);
669 temp |= (CMD_EIE);
670 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
671 "// Enable interrupts, cmd = 0x%x.", temp);
672 writel(temp, &xhci->op_regs->command);
673
674 temp = readl(&xhci->ir_set->irq_pending);
675 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
676 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
677 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
678 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
679
680 if (xhci->quirks & XHCI_NEC_HOST) {
681 struct xhci_command *command;
682
683 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
684 if (!command)
685 return -ENOMEM;
686
687 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
688 TRB_TYPE(TRB_NEC_GET_FW));
689 if (ret)
690 xhci_free_command(xhci, command);
691 }
692 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
693 "Finished xhci_run for USB2 roothub");
694
695 xhci_dbc_init(xhci);
696
697 xhci_debugfs_init(xhci);
698
699 return 0;
700}
701EXPORT_SYMBOL_GPL(xhci_run);
702
703/*
704 * Stop xHCI driver.
705 *
706 * This function is called by the USB core when the HC driver is removed.
707 * Its opposite is xhci_run().
708 *
709 * Disable device contexts, disable IRQs, and quiesce the HC.
710 * Reset the HC, finish any completed transactions, and cleanup memory.
711 */
712static void xhci_stop(struct usb_hcd *hcd)
713{
714 u32 temp;
715 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
716
717 mutex_lock(&xhci->mutex);
718
719 /* Only halt host and free memory after both hcds are removed */
720 if (!usb_hcd_is_primary_hcd(hcd)) {
721 mutex_unlock(&xhci->mutex);
722 return;
723 }
724
725 xhci_dbc_exit(xhci);
726
727 spin_lock_irq(&xhci->lock);
728 xhci->xhc_state |= XHCI_STATE_HALTED;
729 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
730 xhci_halt(xhci);
731 xhci_reset(xhci);
732 spin_unlock_irq(&xhci->lock);
733
734 xhci_cleanup_msix(xhci);
735
736 /* Deleting Compliance Mode Recovery Timer */
737 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
738 (!(xhci_all_ports_seen_u0(xhci)))) {
739 del_timer_sync(&xhci->comp_mode_recovery_timer);
740 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
741 "%s: compliance mode recovery timer deleted",
742 __func__);
743 }
744
745 if (xhci->quirks & XHCI_AMD_PLL_FIX)
746 usb_amd_dev_put();
747
748 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
749 "// Disabling event ring interrupts");
750 temp = readl(&xhci->op_regs->status);
751 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
752 temp = readl(&xhci->ir_set->irq_pending);
753 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
754
755 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
756 xhci_mem_cleanup(xhci);
757 xhci_debugfs_exit(xhci);
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "xhci_stop completed - status = %x",
760 readl(&xhci->op_regs->status));
761 mutex_unlock(&xhci->mutex);
762}
763
764/*
765 * Shutdown HC (not bus-specific)
766 *
767 * This is called when the machine is rebooting or halting. We assume that the
768 * machine will be powered off, and the HC's internal state will be reset.
769 * Don't bother to free memory.
770 *
771 * This will only ever be called with the main usb_hcd (the USB3 roothub).
772 */
773void xhci_shutdown(struct usb_hcd *hcd)
774{
775 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
776
777 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
778 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
779
780 spin_lock_irq(&xhci->lock);
781 xhci_halt(xhci);
782 /* Workaround for spurious wakeups at shutdown with HSW */
783 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
784 xhci_reset(xhci);
785 spin_unlock_irq(&xhci->lock);
786
787 xhci_cleanup_msix(xhci);
788
789 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
790 "xhci_shutdown completed - status = %x",
791 readl(&xhci->op_regs->status));
792}
793EXPORT_SYMBOL_GPL(xhci_shutdown);
794
795#ifdef CONFIG_PM
796static void xhci_save_registers(struct xhci_hcd *xhci)
797{
798 xhci->s3.command = readl(&xhci->op_regs->command);
799 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
800 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
801 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
802 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
803 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
804 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
805 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
806 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
807}
808
809static void xhci_restore_registers(struct xhci_hcd *xhci)
810{
811 writel(xhci->s3.command, &xhci->op_regs->command);
812 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
813 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
814 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
815 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
816 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
817 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
818 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
819 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
820}
821
822static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
823{
824 u64 val_64;
825
826 /* step 2: initialize command ring buffer */
827 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
828 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
829 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
830 xhci->cmd_ring->dequeue) &
831 (u64) ~CMD_RING_RSVD_BITS) |
832 xhci->cmd_ring->cycle_state;
833 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
834 "// Setting command ring address to 0x%llx",
835 (long unsigned long) val_64);
836 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
837}
838
839/*
840 * The whole command ring must be cleared to zero when we suspend the host.
841 *
842 * The host doesn't save the command ring pointer in the suspend well, so we
843 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
844 * aligned, because of the reserved bits in the command ring dequeue pointer
845 * register. Therefore, we can't just set the dequeue pointer back in the
846 * middle of the ring (TRBs are 16-byte aligned).
847 */
848static void xhci_clear_command_ring(struct xhci_hcd *xhci)
849{
850 struct xhci_ring *ring;
851 struct xhci_segment *seg;
852
853 ring = xhci->cmd_ring;
854 seg = ring->deq_seg;
855 do {
856 memset(seg->trbs, 0,
857 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
858 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
859 cpu_to_le32(~TRB_CYCLE);
860 seg = seg->next;
861 } while (seg != ring->deq_seg);
862
863 /* Reset the software enqueue and dequeue pointers */
864 ring->deq_seg = ring->first_seg;
865 ring->dequeue = ring->first_seg->trbs;
866 ring->enq_seg = ring->deq_seg;
867 ring->enqueue = ring->dequeue;
868
869 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
870 /*
871 * Ring is now zeroed, so the HW should look for change of ownership
872 * when the cycle bit is set to 1.
873 */
874 ring->cycle_state = 1;
875
876 /*
877 * Reset the hardware dequeue pointer.
878 * Yes, this will need to be re-written after resume, but we're paranoid
879 * and want to make sure the hardware doesn't access bogus memory
880 * because, say, the BIOS or an SMI started the host without changing
881 * the command ring pointers.
882 */
883 xhci_set_cmd_ring_deq(xhci);
884}
885
886static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
887{
888 struct xhci_port **ports;
889 int port_index;
890 unsigned long flags;
891 u32 t1, t2, portsc;
892
893 spin_lock_irqsave(&xhci->lock, flags);
894
895 /* disable usb3 ports Wake bits */
896 port_index = xhci->usb3_rhub.num_ports;
897 ports = xhci->usb3_rhub.ports;
898 while (port_index--) {
899 t1 = readl(ports[port_index]->addr);
900 portsc = t1;
901 t1 = xhci_port_state_to_neutral(t1);
902 t2 = t1 & ~PORT_WAKE_BITS;
903 if (t1 != t2) {
904 writel(t2, ports[port_index]->addr);
905 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
906 xhci->usb3_rhub.hcd->self.busnum,
907 port_index + 1, portsc, t2);
908 }
909 }
910
911 /* disable usb2 ports Wake bits */
912 port_index = xhci->usb2_rhub.num_ports;
913 ports = xhci->usb2_rhub.ports;
914 while (port_index--) {
915 t1 = readl(ports[port_index]->addr);
916 portsc = t1;
917 t1 = xhci_port_state_to_neutral(t1);
918 t2 = t1 & ~PORT_WAKE_BITS;
919 if (t1 != t2) {
920 writel(t2, ports[port_index]->addr);
921 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
922 xhci->usb2_rhub.hcd->self.busnum,
923 port_index + 1, portsc, t2);
924 }
925 }
926 spin_unlock_irqrestore(&xhci->lock, flags);
927}
928
929static bool xhci_pending_portevent(struct xhci_hcd *xhci)
930{
931 struct xhci_port **ports;
932 int port_index;
933 u32 status;
934 u32 portsc;
935
936 status = readl(&xhci->op_regs->status);
937 if (status & STS_EINT)
938 return true;
939 /*
940 * Checking STS_EINT is not enough as there is a lag between a change
941 * bit being set and the Port Status Change Event that it generated
942 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
943 */
944
945 port_index = xhci->usb2_rhub.num_ports;
946 ports = xhci->usb2_rhub.ports;
947 while (port_index--) {
948 portsc = readl(ports[port_index]->addr);
949 if (portsc & PORT_CHANGE_MASK ||
950 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
951 return true;
952 }
953 port_index = xhci->usb3_rhub.num_ports;
954 ports = xhci->usb3_rhub.ports;
955 while (port_index--) {
956 portsc = readl(ports[port_index]->addr);
957 if (portsc & PORT_CHANGE_MASK ||
958 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
959 return true;
960 }
961 return false;
962}
963
964/*
965 * Stop HC (not bus-specific)
966 *
967 * This is called when the machine transition into S3/S4 mode.
968 *
969 */
970int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
971{
972 int rc = 0;
973 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
974 struct usb_hcd *hcd = xhci_to_hcd(xhci);
975 u32 command;
976 u32 res;
977
978 if (!hcd->state)
979 return 0;
980
981 if (hcd->state != HC_STATE_SUSPENDED ||
982 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
983 return -EINVAL;
984
985 xhci_dbc_suspend(xhci);
986
987 /* Clear root port wake on bits if wakeup not allowed. */
988 if (!do_wakeup)
989 xhci_disable_port_wake_on_bits(xhci);
990
991 /* Don't poll the roothubs on bus suspend. */
992 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
993 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
994 del_timer_sync(&hcd->rh_timer);
995 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
996 del_timer_sync(&xhci->shared_hcd->rh_timer);
997
998 if (xhci->quirks & XHCI_SUSPEND_DELAY)
999 usleep_range(1000, 1500);
1000
1001 spin_lock_irq(&xhci->lock);
1002 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1003 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1004 /* step 1: stop endpoint */
1005 /* skipped assuming that port suspend has done */
1006
1007 /* step 2: clear Run/Stop bit */
1008 command = readl(&xhci->op_regs->command);
1009 command &= ~CMD_RUN;
1010 writel(command, &xhci->op_regs->command);
1011
1012 /* Some chips from Fresco Logic need an extraordinary delay */
1013 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1014
1015 if (xhci_handshake(&xhci->op_regs->status,
1016 STS_HALT, STS_HALT, delay)) {
1017 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1018 spin_unlock_irq(&xhci->lock);
1019 return -ETIMEDOUT;
1020 }
1021 xhci_clear_command_ring(xhci);
1022
1023 /* step 3: save registers */
1024 xhci_save_registers(xhci);
1025
1026 /* step 4: set CSS flag */
1027 command = readl(&xhci->op_regs->command);
1028 command |= CMD_CSS;
1029 writel(command, &xhci->op_regs->command);
1030 xhci->broken_suspend = 0;
1031 if (xhci_handshake(&xhci->op_regs->status,
1032 STS_SAVE, 0, 20 * 1000)) {
1033 /*
1034 * AMD SNPS xHC 3.0 occasionally does not clear the
1035 * SSS bit of USBSTS and when driver tries to poll
1036 * to see if the xHC clears BIT(8) which never happens
1037 * and driver assumes that controller is not responding
1038 * and times out. To workaround this, its good to check
1039 * if SRE and HCE bits are not set (as per xhci
1040 * Section 5.4.2) and bypass the timeout.
1041 */
1042 res = readl(&xhci->op_regs->status);
1043 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1044 (((res & STS_SRE) == 0) &&
1045 ((res & STS_HCE) == 0))) {
1046 xhci->broken_suspend = 1;
1047 } else {
1048 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1049 spin_unlock_irq(&xhci->lock);
1050 return -ETIMEDOUT;
1051 }
1052 }
1053 spin_unlock_irq(&xhci->lock);
1054
1055 /*
1056 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1057 * is about to be suspended.
1058 */
1059 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1060 (!(xhci_all_ports_seen_u0(xhci)))) {
1061 del_timer_sync(&xhci->comp_mode_recovery_timer);
1062 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1063 "%s: compliance mode recovery timer deleted",
1064 __func__);
1065 }
1066
1067 /* step 5: remove core well power */
1068 /* synchronize irq when using MSI-X */
1069 xhci_msix_sync_irqs(xhci);
1070
1071 return rc;
1072}
1073EXPORT_SYMBOL_GPL(xhci_suspend);
1074
1075/*
1076 * start xHC (not bus-specific)
1077 *
1078 * This is called when the machine transition from S3/S4 mode.
1079 *
1080 */
1081int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1082{
1083 u32 command, temp = 0;
1084 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1085 struct usb_hcd *secondary_hcd;
1086 int retval = 0;
1087 bool comp_timer_running = false;
1088
1089 if (!hcd->state)
1090 return 0;
1091
1092 /* Wait a bit if either of the roothubs need to settle from the
1093 * transition into bus suspend.
1094 */
1095
1096 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1097 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1098 msleep(100);
1099
1100 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1101 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1102
1103 spin_lock_irq(&xhci->lock);
1104 if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
1105 hibernated = true;
1106
1107 if (!hibernated) {
1108 /*
1109 * Some controllers might lose power during suspend, so wait
1110 * for controller not ready bit to clear, just as in xHC init.
1111 */
1112 retval = xhci_handshake(&xhci->op_regs->status,
1113 STS_CNR, 0, 10 * 1000 * 1000);
1114 if (retval) {
1115 xhci_warn(xhci, "Controller not ready at resume %d\n",
1116 retval);
1117 spin_unlock_irq(&xhci->lock);
1118 return retval;
1119 }
1120 /* step 1: restore register */
1121 xhci_restore_registers(xhci);
1122 /* step 2: initialize command ring buffer */
1123 xhci_set_cmd_ring_deq(xhci);
1124 /* step 3: restore state and start state*/
1125 /* step 3: set CRS flag */
1126 command = readl(&xhci->op_regs->command);
1127 command |= CMD_CRS;
1128 writel(command, &xhci->op_regs->command);
1129 /*
1130 * Some controllers take up to 55+ ms to complete the controller
1131 * restore so setting the timeout to 100ms. Xhci specification
1132 * doesn't mention any timeout value.
1133 */
1134 if (xhci_handshake(&xhci->op_regs->status,
1135 STS_RESTORE, 0, 100 * 1000)) {
1136 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1137 spin_unlock_irq(&xhci->lock);
1138 return -ETIMEDOUT;
1139 }
1140 temp = readl(&xhci->op_regs->status);
1141 }
1142
1143 /* If restore operation fails, re-initialize the HC during resume */
1144 if ((temp & STS_SRE) || hibernated) {
1145
1146 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1147 !(xhci_all_ports_seen_u0(xhci))) {
1148 del_timer_sync(&xhci->comp_mode_recovery_timer);
1149 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1150 "Compliance Mode Recovery Timer deleted!");
1151 }
1152
1153 /* Let the USB core know _both_ roothubs lost power. */
1154 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1155 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1156
1157 xhci_dbg(xhci, "Stop HCD\n");
1158 xhci_halt(xhci);
1159 xhci_zero_64b_regs(xhci);
1160 retval = xhci_reset(xhci);
1161 spin_unlock_irq(&xhci->lock);
1162 if (retval)
1163 return retval;
1164 xhci_cleanup_msix(xhci);
1165
1166 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1167 temp = readl(&xhci->op_regs->status);
1168 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1169 temp = readl(&xhci->ir_set->irq_pending);
1170 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1171
1172 xhci_dbg(xhci, "cleaning up memory\n");
1173 xhci_mem_cleanup(xhci);
1174 xhci_debugfs_exit(xhci);
1175 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1176 readl(&xhci->op_regs->status));
1177
1178 /* USB core calls the PCI reinit and start functions twice:
1179 * first with the primary HCD, and then with the secondary HCD.
1180 * If we don't do the same, the host will never be started.
1181 */
1182 if (!usb_hcd_is_primary_hcd(hcd))
1183 secondary_hcd = hcd;
1184 else
1185 secondary_hcd = xhci->shared_hcd;
1186
1187 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1188 retval = xhci_init(hcd->primary_hcd);
1189 if (retval)
1190 return retval;
1191 comp_timer_running = true;
1192
1193 xhci_dbg(xhci, "Start the primary HCD\n");
1194 retval = xhci_run(hcd->primary_hcd);
1195 if (!retval) {
1196 xhci_dbg(xhci, "Start the secondary HCD\n");
1197 retval = xhci_run(secondary_hcd);
1198 }
1199 hcd->state = HC_STATE_SUSPENDED;
1200 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1201 goto done;
1202 }
1203
1204 /* step 4: set Run/Stop bit */
1205 command = readl(&xhci->op_regs->command);
1206 command |= CMD_RUN;
1207 writel(command, &xhci->op_regs->command);
1208 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1209 0, 250 * 1000);
1210
1211 /* step 5: walk topology and initialize portsc,
1212 * portpmsc and portli
1213 */
1214 /* this is done in bus_resume */
1215
1216 /* step 6: restart each of the previously
1217 * Running endpoints by ringing their doorbells
1218 */
1219
1220 spin_unlock_irq(&xhci->lock);
1221
1222 xhci_dbc_resume(xhci);
1223
1224 done:
1225 if (retval == 0) {
1226 /* Resume root hubs only when have pending events. */
1227 if (xhci_pending_portevent(xhci)) {
1228 usb_hcd_resume_root_hub(xhci->shared_hcd);
1229 usb_hcd_resume_root_hub(hcd);
1230 }
1231 }
1232
1233 /*
1234 * If system is subject to the Quirk, Compliance Mode Timer needs to
1235 * be re-initialized Always after a system resume. Ports are subject
1236 * to suffer the Compliance Mode issue again. It doesn't matter if
1237 * ports have entered previously to U0 before system's suspension.
1238 */
1239 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1240 compliance_mode_recovery_timer_init(xhci);
1241
1242 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1243 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1244
1245 /* Re-enable port polling. */
1246 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1247 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1248 usb_hcd_poll_rh_status(xhci->shared_hcd);
1249 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1250 usb_hcd_poll_rh_status(hcd);
1251
1252 return retval;
1253}
1254EXPORT_SYMBOL_GPL(xhci_resume);
1255#endif /* CONFIG_PM */
1256
1257/*-------------------------------------------------------------------------*/
1258
1259/*
1260 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1261 * we'll copy the actual data into the TRB address register. This is limited to
1262 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1263 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1264 */
1265static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1266 gfp_t mem_flags)
1267{
1268 if (xhci_urb_suitable_for_idt(urb))
1269 return 0;
1270
1271 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1272}
1273
1274/*
1275 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1276 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1277 * value to right shift 1 for the bitmask.
1278 *
1279 * Index = (epnum * 2) + direction - 1,
1280 * where direction = 0 for OUT, 1 for IN.
1281 * For control endpoints, the IN index is used (OUT index is unused), so
1282 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1283 */
1284unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1285{
1286 unsigned int index;
1287 if (usb_endpoint_xfer_control(desc))
1288 index = (unsigned int) (usb_endpoint_num(desc)*2);
1289 else
1290 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1291 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1292 return index;
1293}
1294
1295/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1296 * address from the XHCI endpoint index.
1297 */
1298unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1299{
1300 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1301 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1302 return direction | number;
1303}
1304
1305/* Find the flag for this endpoint (for use in the control context). Use the
1306 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1307 * bit 1, etc.
1308 */
1309static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1310{
1311 return 1 << (xhci_get_endpoint_index(desc) + 1);
1312}
1313
1314/* Find the flag for this endpoint (for use in the control context). Use the
1315 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1316 * bit 1, etc.
1317 */
1318static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1319{
1320 return 1 << (ep_index + 1);
1321}
1322
1323/* Compute the last valid endpoint context index. Basically, this is the
1324 * endpoint index plus one. For slot contexts with more than valid endpoint,
1325 * we find the most significant bit set in the added contexts flags.
1326 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1327 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1328 */
1329unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1330{
1331 return fls(added_ctxs) - 1;
1332}
1333
1334/* Returns 1 if the arguments are OK;
1335 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1336 */
1337static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1338 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1339 const char *func) {
1340 struct xhci_hcd *xhci;
1341 struct xhci_virt_device *virt_dev;
1342
1343 if (!hcd || (check_ep && !ep) || !udev) {
1344 pr_debug("xHCI %s called with invalid args\n", func);
1345 return -EINVAL;
1346 }
1347 if (!udev->parent) {
1348 pr_debug("xHCI %s called for root hub\n", func);
1349 return 0;
1350 }
1351
1352 xhci = hcd_to_xhci(hcd);
1353 if (check_virt_dev) {
1354 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1355 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1356 func);
1357 return -EINVAL;
1358 }
1359
1360 virt_dev = xhci->devs[udev->slot_id];
1361 if (virt_dev->udev != udev) {
1362 xhci_dbg(xhci, "xHCI %s called with udev and "
1363 "virt_dev does not match\n", func);
1364 return -EINVAL;
1365 }
1366 }
1367
1368 if (xhci->xhc_state & XHCI_STATE_HALTED)
1369 return -ENODEV;
1370
1371 return 1;
1372}
1373
1374static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1375 struct usb_device *udev, struct xhci_command *command,
1376 bool ctx_change, bool must_succeed);
1377
1378/*
1379 * Full speed devices may have a max packet size greater than 8 bytes, but the
1380 * USB core doesn't know that until it reads the first 8 bytes of the
1381 * descriptor. If the usb_device's max packet size changes after that point,
1382 * we need to issue an evaluate context command and wait on it.
1383 */
1384static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1385 unsigned int ep_index, struct urb *urb)
1386{
1387 struct xhci_container_ctx *out_ctx;
1388 struct xhci_input_control_ctx *ctrl_ctx;
1389 struct xhci_ep_ctx *ep_ctx;
1390 struct xhci_command *command;
1391 int max_packet_size;
1392 int hw_max_packet_size;
1393 int ret = 0;
1394
1395 out_ctx = xhci->devs[slot_id]->out_ctx;
1396 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1397 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1398 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1399 if (hw_max_packet_size != max_packet_size) {
1400 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1401 "Max Packet Size for ep 0 changed.");
1402 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1403 "Max packet size in usb_device = %d",
1404 max_packet_size);
1405 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1406 "Max packet size in xHCI HW = %d",
1407 hw_max_packet_size);
1408 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1409 "Issuing evaluate context command.");
1410
1411 /* Set up the input context flags for the command */
1412 /* FIXME: This won't work if a non-default control endpoint
1413 * changes max packet sizes.
1414 */
1415
1416 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1417 if (!command)
1418 return -ENOMEM;
1419
1420 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1421 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1422 if (!ctrl_ctx) {
1423 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1424 __func__);
1425 ret = -ENOMEM;
1426 goto command_cleanup;
1427 }
1428 /* Set up the modified control endpoint 0 */
1429 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1430 xhci->devs[slot_id]->out_ctx, ep_index);
1431
1432 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1433 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1434 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1435 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1436
1437 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1438 ctrl_ctx->drop_flags = 0;
1439
1440 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1441 true, false);
1442
1443 /* Clean up the input context for later use by bandwidth
1444 * functions.
1445 */
1446 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1447command_cleanup:
1448 kfree(command->completion);
1449 kfree(command);
1450 }
1451 return ret;
1452}
1453
1454/*
1455 * non-error returns are a promise to giveback() the urb later
1456 * we drop ownership so next owner (or urb unlink) can get it
1457 */
1458static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1459{
1460 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1461 unsigned long flags;
1462 int ret = 0;
1463 unsigned int slot_id, ep_index;
1464 unsigned int *ep_state;
1465 struct urb_priv *urb_priv;
1466 int num_tds;
1467
1468 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1469 true, true, __func__) <= 0)
1470 return -EINVAL;
1471
1472 slot_id = urb->dev->slot_id;
1473 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1474 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1475
1476 if (!HCD_HW_ACCESSIBLE(hcd)) {
1477 if (!in_interrupt())
1478 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1479 return -ESHUTDOWN;
1480 }
1481 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1482 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1483 return -ENODEV;
1484 }
1485
1486 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1487 num_tds = urb->number_of_packets;
1488 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1489 urb->transfer_buffer_length > 0 &&
1490 urb->transfer_flags & URB_ZERO_PACKET &&
1491 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1492 num_tds = 2;
1493 else
1494 num_tds = 1;
1495
1496 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1497 if (!urb_priv)
1498 return -ENOMEM;
1499
1500 urb_priv->num_tds = num_tds;
1501 urb_priv->num_tds_done = 0;
1502 urb->hcpriv = urb_priv;
1503
1504 trace_xhci_urb_enqueue(urb);
1505
1506 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1507 /* Check to see if the max packet size for the default control
1508 * endpoint changed during FS device enumeration
1509 */
1510 if (urb->dev->speed == USB_SPEED_FULL) {
1511 ret = xhci_check_maxpacket(xhci, slot_id,
1512 ep_index, urb);
1513 if (ret < 0) {
1514 xhci_urb_free_priv(urb_priv);
1515 urb->hcpriv = NULL;
1516 return ret;
1517 }
1518 }
1519 }
1520
1521 spin_lock_irqsave(&xhci->lock, flags);
1522
1523 if (xhci->xhc_state & XHCI_STATE_DYING) {
1524 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1525 urb->ep->desc.bEndpointAddress, urb);
1526 ret = -ESHUTDOWN;
1527 goto free_priv;
1528 }
1529 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1530 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1531 *ep_state);
1532 ret = -EINVAL;
1533 goto free_priv;
1534 }
1535 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1536 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1537 ret = -EINVAL;
1538 goto free_priv;
1539 }
1540
1541 switch (usb_endpoint_type(&urb->ep->desc)) {
1542
1543 case USB_ENDPOINT_XFER_CONTROL:
1544 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1545 slot_id, ep_index);
1546 break;
1547 case USB_ENDPOINT_XFER_BULK:
1548 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1549 slot_id, ep_index);
1550 break;
1551 case USB_ENDPOINT_XFER_INT:
1552 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1553 slot_id, ep_index);
1554 break;
1555 case USB_ENDPOINT_XFER_ISOC:
1556 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1557 slot_id, ep_index);
1558 }
1559
1560 if (ret) {
1561free_priv:
1562 xhci_urb_free_priv(urb_priv);
1563 urb->hcpriv = NULL;
1564 }
1565 spin_unlock_irqrestore(&xhci->lock, flags);
1566 return ret;
1567}
1568
1569/*
1570 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1571 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1572 * should pick up where it left off in the TD, unless a Set Transfer Ring
1573 * Dequeue Pointer is issued.
1574 *
1575 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1576 * the ring. Since the ring is a contiguous structure, they can't be physically
1577 * removed. Instead, there are two options:
1578 *
1579 * 1) If the HC is in the middle of processing the URB to be canceled, we
1580 * simply move the ring's dequeue pointer past those TRBs using the Set
1581 * Transfer Ring Dequeue Pointer command. This will be the common case,
1582 * when drivers timeout on the last submitted URB and attempt to cancel.
1583 *
1584 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1585 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1586 * HC will need to invalidate the any TRBs it has cached after the stop
1587 * endpoint command, as noted in the xHCI 0.95 errata.
1588 *
1589 * 3) The TD may have completed by the time the Stop Endpoint Command
1590 * completes, so software needs to handle that case too.
1591 *
1592 * This function should protect against the TD enqueueing code ringing the
1593 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1594 * It also needs to account for multiple cancellations on happening at the same
1595 * time for the same endpoint.
1596 *
1597 * Note that this function can be called in any context, or so says
1598 * usb_hcd_unlink_urb()
1599 */
1600static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1601{
1602 unsigned long flags;
1603 int ret, i;
1604 u32 temp;
1605 struct xhci_hcd *xhci;
1606 struct urb_priv *urb_priv;
1607 struct xhci_td *td;
1608 unsigned int ep_index;
1609 struct xhci_ring *ep_ring;
1610 struct xhci_virt_ep *ep;
1611 struct xhci_command *command;
1612 struct xhci_virt_device *vdev;
1613
1614 xhci = hcd_to_xhci(hcd);
1615 spin_lock_irqsave(&xhci->lock, flags);
1616
1617 trace_xhci_urb_dequeue(urb);
1618
1619 /* Make sure the URB hasn't completed or been unlinked already */
1620 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1621 if (ret)
1622 goto done;
1623
1624 /* give back URB now if we can't queue it for cancel */
1625 vdev = xhci->devs[urb->dev->slot_id];
1626 urb_priv = urb->hcpriv;
1627 if (!vdev || !urb_priv)
1628 goto err_giveback;
1629
1630 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1631 ep = &vdev->eps[ep_index];
1632 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1633 if (!ep || !ep_ring)
1634 goto err_giveback;
1635
1636 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1637 temp = readl(&xhci->op_regs->status);
1638 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1639 xhci_hc_died(xhci);
1640 goto done;
1641 }
1642
1643 /*
1644 * check ring is not re-allocated since URB was enqueued. If it is, then
1645 * make sure none of the ring related pointers in this URB private data
1646 * are touched, such as td_list, otherwise we overwrite freed data
1647 */
1648 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1649 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1650 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1651 td = &urb_priv->td[i];
1652 if (!list_empty(&td->cancelled_td_list))
1653 list_del_init(&td->cancelled_td_list);
1654 }
1655 goto err_giveback;
1656 }
1657
1658 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1659 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1660 "HC halted, freeing TD manually.");
1661 for (i = urb_priv->num_tds_done;
1662 i < urb_priv->num_tds;
1663 i++) {
1664 td = &urb_priv->td[i];
1665 if (!list_empty(&td->td_list))
1666 list_del_init(&td->td_list);
1667 if (!list_empty(&td->cancelled_td_list))
1668 list_del_init(&td->cancelled_td_list);
1669 }
1670 goto err_giveback;
1671 }
1672
1673 i = urb_priv->num_tds_done;
1674 if (i < urb_priv->num_tds)
1675 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1676 "Cancel URB %p, dev %s, ep 0x%x, "
1677 "starting at offset 0x%llx",
1678 urb, urb->dev->devpath,
1679 urb->ep->desc.bEndpointAddress,
1680 (unsigned long long) xhci_trb_virt_to_dma(
1681 urb_priv->td[i].start_seg,
1682 urb_priv->td[i].first_trb));
1683
1684 for (; i < urb_priv->num_tds; i++) {
1685 td = &urb_priv->td[i];
1686 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1687 }
1688
1689 /* Queue a stop endpoint command, but only if this is
1690 * the first cancellation to be handled.
1691 */
1692 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1693 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1694 if (!command) {
1695 ret = -ENOMEM;
1696 goto done;
1697 }
1698 ep->ep_state |= EP_STOP_CMD_PENDING;
1699 ep->stop_cmd_timer.expires = jiffies +
1700 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1701 add_timer(&ep->stop_cmd_timer);
1702 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1703 ep_index, 0);
1704 xhci_ring_cmd_db(xhci);
1705 }
1706done:
1707 spin_unlock_irqrestore(&xhci->lock, flags);
1708 return ret;
1709
1710err_giveback:
1711 if (urb_priv)
1712 xhci_urb_free_priv(urb_priv);
1713 usb_hcd_unlink_urb_from_ep(hcd, urb);
1714 spin_unlock_irqrestore(&xhci->lock, flags);
1715 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1716 return ret;
1717}
1718
1719/* Drop an endpoint from a new bandwidth configuration for this device.
1720 * Only one call to this function is allowed per endpoint before
1721 * check_bandwidth() or reset_bandwidth() must be called.
1722 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1723 * add the endpoint to the schedule with possibly new parameters denoted by a
1724 * different endpoint descriptor in usb_host_endpoint.
1725 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1726 * not allowed.
1727 *
1728 * The USB core will not allow URBs to be queued to an endpoint that is being
1729 * disabled, so there's no need for mutual exclusion to protect
1730 * the xhci->devs[slot_id] structure.
1731 */
1732static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1733 struct usb_host_endpoint *ep)
1734{
1735 struct xhci_hcd *xhci;
1736 struct xhci_container_ctx *in_ctx, *out_ctx;
1737 struct xhci_input_control_ctx *ctrl_ctx;
1738 unsigned int ep_index;
1739 struct xhci_ep_ctx *ep_ctx;
1740 u32 drop_flag;
1741 u32 new_add_flags, new_drop_flags;
1742 int ret;
1743
1744 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1745 if (ret <= 0)
1746 return ret;
1747 xhci = hcd_to_xhci(hcd);
1748 if (xhci->xhc_state & XHCI_STATE_DYING)
1749 return -ENODEV;
1750
1751 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1752 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1753 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1754 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1755 __func__, drop_flag);
1756 return 0;
1757 }
1758
1759 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1760 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1761 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1762 if (!ctrl_ctx) {
1763 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1764 __func__);
1765 return 0;
1766 }
1767
1768 ep_index = xhci_get_endpoint_index(&ep->desc);
1769 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1770 /* If the HC already knows the endpoint is disabled,
1771 * or the HCD has noted it is disabled, ignore this request
1772 */
1773 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1774 le32_to_cpu(ctrl_ctx->drop_flags) &
1775 xhci_get_endpoint_flag(&ep->desc)) {
1776 /* Do not warn when called after a usb_device_reset */
1777 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1778 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1779 __func__, ep);
1780 return 0;
1781 }
1782
1783 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1784 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1785
1786 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1787 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1788
1789 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1790
1791 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1792
1793 if (xhci->quirks & XHCI_MTK_HOST)
1794 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1795
1796 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1797 (unsigned int) ep->desc.bEndpointAddress,
1798 udev->slot_id,
1799 (unsigned int) new_drop_flags,
1800 (unsigned int) new_add_flags);
1801 return 0;
1802}
1803
1804/* Add an endpoint to a new possible bandwidth configuration for this device.
1805 * Only one call to this function is allowed per endpoint before
1806 * check_bandwidth() or reset_bandwidth() must be called.
1807 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1808 * add the endpoint to the schedule with possibly new parameters denoted by a
1809 * different endpoint descriptor in usb_host_endpoint.
1810 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1811 * not allowed.
1812 *
1813 * The USB core will not allow URBs to be queued to an endpoint until the
1814 * configuration or alt setting is installed in the device, so there's no need
1815 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1816 */
1817static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1818 struct usb_host_endpoint *ep)
1819{
1820 struct xhci_hcd *xhci;
1821 struct xhci_container_ctx *in_ctx;
1822 unsigned int ep_index;
1823 struct xhci_input_control_ctx *ctrl_ctx;
1824 struct xhci_ep_ctx *ep_ctx;
1825 u32 added_ctxs;
1826 u32 new_add_flags, new_drop_flags;
1827 struct xhci_virt_device *virt_dev;
1828 int ret = 0;
1829
1830 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1831 if (ret <= 0) {
1832 /* So we won't queue a reset ep command for a root hub */
1833 ep->hcpriv = NULL;
1834 return ret;
1835 }
1836 xhci = hcd_to_xhci(hcd);
1837 if (xhci->xhc_state & XHCI_STATE_DYING)
1838 return -ENODEV;
1839
1840 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1841 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1842 /* FIXME when we have to issue an evaluate endpoint command to
1843 * deal with ep0 max packet size changing once we get the
1844 * descriptors
1845 */
1846 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1847 __func__, added_ctxs);
1848 return 0;
1849 }
1850
1851 virt_dev = xhci->devs[udev->slot_id];
1852 in_ctx = virt_dev->in_ctx;
1853 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1854 if (!ctrl_ctx) {
1855 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1856 __func__);
1857 return 0;
1858 }
1859
1860 ep_index = xhci_get_endpoint_index(&ep->desc);
1861 /* If this endpoint is already in use, and the upper layers are trying
1862 * to add it again without dropping it, reject the addition.
1863 */
1864 if (virt_dev->eps[ep_index].ring &&
1865 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1866 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1867 "without dropping it.\n",
1868 (unsigned int) ep->desc.bEndpointAddress);
1869 return -EINVAL;
1870 }
1871
1872 /* If the HCD has already noted the endpoint is enabled,
1873 * ignore this request.
1874 */
1875 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1876 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1877 __func__, ep);
1878 return 0;
1879 }
1880
1881 /*
1882 * Configuration and alternate setting changes must be done in
1883 * process context, not interrupt context (or so documenation
1884 * for usb_set_interface() and usb_set_configuration() claim).
1885 */
1886 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1887 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1888 __func__, ep->desc.bEndpointAddress);
1889 return -ENOMEM;
1890 }
1891
1892 if (xhci->quirks & XHCI_MTK_HOST) {
1893 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1894 if (ret < 0) {
1895 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1896 virt_dev->eps[ep_index].new_ring = NULL;
1897 return ret;
1898 }
1899 }
1900
1901 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1902 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1903
1904 /* If xhci_endpoint_disable() was called for this endpoint, but the
1905 * xHC hasn't been notified yet through the check_bandwidth() call,
1906 * this re-adds a new state for the endpoint from the new endpoint
1907 * descriptors. We must drop and re-add this endpoint, so we leave the
1908 * drop flags alone.
1909 */
1910 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1911
1912 /* Store the usb_device pointer for later use */
1913 ep->hcpriv = udev;
1914
1915 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1916 trace_xhci_add_endpoint(ep_ctx);
1917
1918 xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index);
1919
1920 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1921 (unsigned int) ep->desc.bEndpointAddress,
1922 udev->slot_id,
1923 (unsigned int) new_drop_flags,
1924 (unsigned int) new_add_flags);
1925 return 0;
1926}
1927
1928static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1929{
1930 struct xhci_input_control_ctx *ctrl_ctx;
1931 struct xhci_ep_ctx *ep_ctx;
1932 struct xhci_slot_ctx *slot_ctx;
1933 int i;
1934
1935 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1936 if (!ctrl_ctx) {
1937 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1938 __func__);
1939 return;
1940 }
1941
1942 /* When a device's add flag and drop flag are zero, any subsequent
1943 * configure endpoint command will leave that endpoint's state
1944 * untouched. Make sure we don't leave any old state in the input
1945 * endpoint contexts.
1946 */
1947 ctrl_ctx->drop_flags = 0;
1948 ctrl_ctx->add_flags = 0;
1949 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1950 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1951 /* Endpoint 0 is always valid */
1952 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1953 for (i = 1; i < 31; i++) {
1954 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1955 ep_ctx->ep_info = 0;
1956 ep_ctx->ep_info2 = 0;
1957 ep_ctx->deq = 0;
1958 ep_ctx->tx_info = 0;
1959 }
1960}
1961
1962static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1963 struct usb_device *udev, u32 *cmd_status)
1964{
1965 int ret;
1966
1967 switch (*cmd_status) {
1968 case COMP_COMMAND_ABORTED:
1969 case COMP_COMMAND_RING_STOPPED:
1970 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1971 ret = -ETIME;
1972 break;
1973 case COMP_RESOURCE_ERROR:
1974 dev_warn(&udev->dev,
1975 "Not enough host controller resources for new device state.\n");
1976 ret = -ENOMEM;
1977 /* FIXME: can we allocate more resources for the HC? */
1978 break;
1979 case COMP_BANDWIDTH_ERROR:
1980 case COMP_SECONDARY_BANDWIDTH_ERROR:
1981 dev_warn(&udev->dev,
1982 "Not enough bandwidth for new device state.\n");
1983 ret = -ENOSPC;
1984 /* FIXME: can we go back to the old state? */
1985 break;
1986 case COMP_TRB_ERROR:
1987 /* the HCD set up something wrong */
1988 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1989 "add flag = 1, "
1990 "and endpoint is not disabled.\n");
1991 ret = -EINVAL;
1992 break;
1993 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1994 dev_warn(&udev->dev,
1995 "ERROR: Incompatible device for endpoint configure command.\n");
1996 ret = -ENODEV;
1997 break;
1998 case COMP_SUCCESS:
1999 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2000 "Successful Endpoint Configure command");
2001 ret = 0;
2002 break;
2003 default:
2004 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2005 *cmd_status);
2006 ret = -EINVAL;
2007 break;
2008 }
2009 return ret;
2010}
2011
2012static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2013 struct usb_device *udev, u32 *cmd_status)
2014{
2015 int ret;
2016
2017 switch (*cmd_status) {
2018 case COMP_COMMAND_ABORTED:
2019 case COMP_COMMAND_RING_STOPPED:
2020 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2021 ret = -ETIME;
2022 break;
2023 case COMP_PARAMETER_ERROR:
2024 dev_warn(&udev->dev,
2025 "WARN: xHCI driver setup invalid evaluate context command.\n");
2026 ret = -EINVAL;
2027 break;
2028 case COMP_SLOT_NOT_ENABLED_ERROR:
2029 dev_warn(&udev->dev,
2030 "WARN: slot not enabled for evaluate context command.\n");
2031 ret = -EINVAL;
2032 break;
2033 case COMP_CONTEXT_STATE_ERROR:
2034 dev_warn(&udev->dev,
2035 "WARN: invalid context state for evaluate context command.\n");
2036 ret = -EINVAL;
2037 break;
2038 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2039 dev_warn(&udev->dev,
2040 "ERROR: Incompatible device for evaluate context command.\n");
2041 ret = -ENODEV;
2042 break;
2043 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2044 /* Max Exit Latency too large error */
2045 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2046 ret = -EINVAL;
2047 break;
2048 case COMP_SUCCESS:
2049 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2050 "Successful evaluate context command");
2051 ret = 0;
2052 break;
2053 default:
2054 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2055 *cmd_status);
2056 ret = -EINVAL;
2057 break;
2058 }
2059 return ret;
2060}
2061
2062static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2063 struct xhci_input_control_ctx *ctrl_ctx)
2064{
2065 u32 valid_add_flags;
2066 u32 valid_drop_flags;
2067
2068 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2069 * (bit 1). The default control endpoint is added during the Address
2070 * Device command and is never removed until the slot is disabled.
2071 */
2072 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2073 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2074
2075 /* Use hweight32 to count the number of ones in the add flags, or
2076 * number of endpoints added. Don't count endpoints that are changed
2077 * (both added and dropped).
2078 */
2079 return hweight32(valid_add_flags) -
2080 hweight32(valid_add_flags & valid_drop_flags);
2081}
2082
2083static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2084 struct xhci_input_control_ctx *ctrl_ctx)
2085{
2086 u32 valid_add_flags;
2087 u32 valid_drop_flags;
2088
2089 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2090 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2091
2092 return hweight32(valid_drop_flags) -
2093 hweight32(valid_add_flags & valid_drop_flags);
2094}
2095
2096/*
2097 * We need to reserve the new number of endpoints before the configure endpoint
2098 * command completes. We can't subtract the dropped endpoints from the number
2099 * of active endpoints until the command completes because we can oversubscribe
2100 * the host in this case:
2101 *
2102 * - the first configure endpoint command drops more endpoints than it adds
2103 * - a second configure endpoint command that adds more endpoints is queued
2104 * - the first configure endpoint command fails, so the config is unchanged
2105 * - the second command may succeed, even though there isn't enough resources
2106 *
2107 * Must be called with xhci->lock held.
2108 */
2109static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2110 struct xhci_input_control_ctx *ctrl_ctx)
2111{
2112 u32 added_eps;
2113
2114 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2115 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2116 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2117 "Not enough ep ctxs: "
2118 "%u active, need to add %u, limit is %u.",
2119 xhci->num_active_eps, added_eps,
2120 xhci->limit_active_eps);
2121 return -ENOMEM;
2122 }
2123 xhci->num_active_eps += added_eps;
2124 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2125 "Adding %u ep ctxs, %u now active.", added_eps,
2126 xhci->num_active_eps);
2127 return 0;
2128}
2129
2130/*
2131 * The configure endpoint was failed by the xHC for some other reason, so we
2132 * need to revert the resources that failed configuration would have used.
2133 *
2134 * Must be called with xhci->lock held.
2135 */
2136static void xhci_free_host_resources(struct xhci_hcd *xhci,
2137 struct xhci_input_control_ctx *ctrl_ctx)
2138{
2139 u32 num_failed_eps;
2140
2141 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2142 xhci->num_active_eps -= num_failed_eps;
2143 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2144 "Removing %u failed ep ctxs, %u now active.",
2145 num_failed_eps,
2146 xhci->num_active_eps);
2147}
2148
2149/*
2150 * Now that the command has completed, clean up the active endpoint count by
2151 * subtracting out the endpoints that were dropped (but not changed).
2152 *
2153 * Must be called with xhci->lock held.
2154 */
2155static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2156 struct xhci_input_control_ctx *ctrl_ctx)
2157{
2158 u32 num_dropped_eps;
2159
2160 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2161 xhci->num_active_eps -= num_dropped_eps;
2162 if (num_dropped_eps)
2163 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2164 "Removing %u dropped ep ctxs, %u now active.",
2165 num_dropped_eps,
2166 xhci->num_active_eps);
2167}
2168
2169static unsigned int xhci_get_block_size(struct usb_device *udev)
2170{
2171 switch (udev->speed) {
2172 case USB_SPEED_LOW:
2173 case USB_SPEED_FULL:
2174 return FS_BLOCK;
2175 case USB_SPEED_HIGH:
2176 return HS_BLOCK;
2177 case USB_SPEED_SUPER:
2178 case USB_SPEED_SUPER_PLUS:
2179 return SS_BLOCK;
2180 case USB_SPEED_UNKNOWN:
2181 case USB_SPEED_WIRELESS:
2182 default:
2183 /* Should never happen */
2184 return 1;
2185 }
2186}
2187
2188static unsigned int
2189xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2190{
2191 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2192 return LS_OVERHEAD;
2193 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2194 return FS_OVERHEAD;
2195 return HS_OVERHEAD;
2196}
2197
2198/* If we are changing a LS/FS device under a HS hub,
2199 * make sure (if we are activating a new TT) that the HS bus has enough
2200 * bandwidth for this new TT.
2201 */
2202static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2203 struct xhci_virt_device *virt_dev,
2204 int old_active_eps)
2205{
2206 struct xhci_interval_bw_table *bw_table;
2207 struct xhci_tt_bw_info *tt_info;
2208
2209 /* Find the bandwidth table for the root port this TT is attached to. */
2210 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2211 tt_info = virt_dev->tt_info;
2212 /* If this TT already had active endpoints, the bandwidth for this TT
2213 * has already been added. Removing all periodic endpoints (and thus
2214 * making the TT enactive) will only decrease the bandwidth used.
2215 */
2216 if (old_active_eps)
2217 return 0;
2218 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2219 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2220 return -ENOMEM;
2221 return 0;
2222 }
2223 /* Not sure why we would have no new active endpoints...
2224 *
2225 * Maybe because of an Evaluate Context change for a hub update or a
2226 * control endpoint 0 max packet size change?
2227 * FIXME: skip the bandwidth calculation in that case.
2228 */
2229 return 0;
2230}
2231
2232static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2233 struct xhci_virt_device *virt_dev)
2234{
2235 unsigned int bw_reserved;
2236
2237 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2238 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2239 return -ENOMEM;
2240
2241 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2242 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2243 return -ENOMEM;
2244
2245 return 0;
2246}
2247
2248/*
2249 * This algorithm is a very conservative estimate of the worst-case scheduling
2250 * scenario for any one interval. The hardware dynamically schedules the
2251 * packets, so we can't tell which microframe could be the limiting factor in
2252 * the bandwidth scheduling. This only takes into account periodic endpoints.
2253 *
2254 * Obviously, we can't solve an NP complete problem to find the minimum worst
2255 * case scenario. Instead, we come up with an estimate that is no less than
2256 * the worst case bandwidth used for any one microframe, but may be an
2257 * over-estimate.
2258 *
2259 * We walk the requirements for each endpoint by interval, starting with the
2260 * smallest interval, and place packets in the schedule where there is only one
2261 * possible way to schedule packets for that interval. In order to simplify
2262 * this algorithm, we record the largest max packet size for each interval, and
2263 * assume all packets will be that size.
2264 *
2265 * For interval 0, we obviously must schedule all packets for each interval.
2266 * The bandwidth for interval 0 is just the amount of data to be transmitted
2267 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2268 * the number of packets).
2269 *
2270 * For interval 1, we have two possible microframes to schedule those packets
2271 * in. For this algorithm, if we can schedule the same number of packets for
2272 * each possible scheduling opportunity (each microframe), we will do so. The
2273 * remaining number of packets will be saved to be transmitted in the gaps in
2274 * the next interval's scheduling sequence.
2275 *
2276 * As we move those remaining packets to be scheduled with interval 2 packets,
2277 * we have to double the number of remaining packets to transmit. This is
2278 * because the intervals are actually powers of 2, and we would be transmitting
2279 * the previous interval's packets twice in this interval. We also have to be
2280 * sure that when we look at the largest max packet size for this interval, we
2281 * also look at the largest max packet size for the remaining packets and take
2282 * the greater of the two.
2283 *
2284 * The algorithm continues to evenly distribute packets in each scheduling
2285 * opportunity, and push the remaining packets out, until we get to the last
2286 * interval. Then those packets and their associated overhead are just added
2287 * to the bandwidth used.
2288 */
2289static int xhci_check_bw_table(struct xhci_hcd *xhci,
2290 struct xhci_virt_device *virt_dev,
2291 int old_active_eps)
2292{
2293 unsigned int bw_reserved;
2294 unsigned int max_bandwidth;
2295 unsigned int bw_used;
2296 unsigned int block_size;
2297 struct xhci_interval_bw_table *bw_table;
2298 unsigned int packet_size = 0;
2299 unsigned int overhead = 0;
2300 unsigned int packets_transmitted = 0;
2301 unsigned int packets_remaining = 0;
2302 unsigned int i;
2303
2304 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2305 return xhci_check_ss_bw(xhci, virt_dev);
2306
2307 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2308 max_bandwidth = HS_BW_LIMIT;
2309 /* Convert percent of bus BW reserved to blocks reserved */
2310 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2311 } else {
2312 max_bandwidth = FS_BW_LIMIT;
2313 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2314 }
2315
2316 bw_table = virt_dev->bw_table;
2317 /* We need to translate the max packet size and max ESIT payloads into
2318 * the units the hardware uses.
2319 */
2320 block_size = xhci_get_block_size(virt_dev->udev);
2321
2322 /* If we are manipulating a LS/FS device under a HS hub, double check
2323 * that the HS bus has enough bandwidth if we are activing a new TT.
2324 */
2325 if (virt_dev->tt_info) {
2326 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2327 "Recalculating BW for rootport %u",
2328 virt_dev->real_port);
2329 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2330 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2331 "newly activated TT.\n");
2332 return -ENOMEM;
2333 }
2334 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2335 "Recalculating BW for TT slot %u port %u",
2336 virt_dev->tt_info->slot_id,
2337 virt_dev->tt_info->ttport);
2338 } else {
2339 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2340 "Recalculating BW for rootport %u",
2341 virt_dev->real_port);
2342 }
2343
2344 /* Add in how much bandwidth will be used for interval zero, or the
2345 * rounded max ESIT payload + number of packets * largest overhead.
2346 */
2347 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2348 bw_table->interval_bw[0].num_packets *
2349 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2350
2351 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2352 unsigned int bw_added;
2353 unsigned int largest_mps;
2354 unsigned int interval_overhead;
2355
2356 /*
2357 * How many packets could we transmit in this interval?
2358 * If packets didn't fit in the previous interval, we will need
2359 * to transmit that many packets twice within this interval.
2360 */
2361 packets_remaining = 2 * packets_remaining +
2362 bw_table->interval_bw[i].num_packets;
2363
2364 /* Find the largest max packet size of this or the previous
2365 * interval.
2366 */
2367 if (list_empty(&bw_table->interval_bw[i].endpoints))
2368 largest_mps = 0;
2369 else {
2370 struct xhci_virt_ep *virt_ep;
2371 struct list_head *ep_entry;
2372
2373 ep_entry = bw_table->interval_bw[i].endpoints.next;
2374 virt_ep = list_entry(ep_entry,
2375 struct xhci_virt_ep, bw_endpoint_list);
2376 /* Convert to blocks, rounding up */
2377 largest_mps = DIV_ROUND_UP(
2378 virt_ep->bw_info.max_packet_size,
2379 block_size);
2380 }
2381 if (largest_mps > packet_size)
2382 packet_size = largest_mps;
2383
2384 /* Use the larger overhead of this or the previous interval. */
2385 interval_overhead = xhci_get_largest_overhead(
2386 &bw_table->interval_bw[i]);
2387 if (interval_overhead > overhead)
2388 overhead = interval_overhead;
2389
2390 /* How many packets can we evenly distribute across
2391 * (1 << (i + 1)) possible scheduling opportunities?
2392 */
2393 packets_transmitted = packets_remaining >> (i + 1);
2394
2395 /* Add in the bandwidth used for those scheduled packets */
2396 bw_added = packets_transmitted * (overhead + packet_size);
2397
2398 /* How many packets do we have remaining to transmit? */
2399 packets_remaining = packets_remaining % (1 << (i + 1));
2400
2401 /* What largest max packet size should those packets have? */
2402 /* If we've transmitted all packets, don't carry over the
2403 * largest packet size.
2404 */
2405 if (packets_remaining == 0) {
2406 packet_size = 0;
2407 overhead = 0;
2408 } else if (packets_transmitted > 0) {
2409 /* Otherwise if we do have remaining packets, and we've
2410 * scheduled some packets in this interval, take the
2411 * largest max packet size from endpoints with this
2412 * interval.
2413 */
2414 packet_size = largest_mps;
2415 overhead = interval_overhead;
2416 }
2417 /* Otherwise carry over packet_size and overhead from the last
2418 * time we had a remainder.
2419 */
2420 bw_used += bw_added;
2421 if (bw_used > max_bandwidth) {
2422 xhci_warn(xhci, "Not enough bandwidth. "
2423 "Proposed: %u, Max: %u\n",
2424 bw_used, max_bandwidth);
2425 return -ENOMEM;
2426 }
2427 }
2428 /*
2429 * Ok, we know we have some packets left over after even-handedly
2430 * scheduling interval 15. We don't know which microframes they will
2431 * fit into, so we over-schedule and say they will be scheduled every
2432 * microframe.
2433 */
2434 if (packets_remaining > 0)
2435 bw_used += overhead + packet_size;
2436
2437 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2438 unsigned int port_index = virt_dev->real_port - 1;
2439
2440 /* OK, we're manipulating a HS device attached to a
2441 * root port bandwidth domain. Include the number of active TTs
2442 * in the bandwidth used.
2443 */
2444 bw_used += TT_HS_OVERHEAD *
2445 xhci->rh_bw[port_index].num_active_tts;
2446 }
2447
2448 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2449 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2450 "Available: %u " "percent",
2451 bw_used, max_bandwidth, bw_reserved,
2452 (max_bandwidth - bw_used - bw_reserved) * 100 /
2453 max_bandwidth);
2454
2455 bw_used += bw_reserved;
2456 if (bw_used > max_bandwidth) {
2457 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2458 bw_used, max_bandwidth);
2459 return -ENOMEM;
2460 }
2461
2462 bw_table->bw_used = bw_used;
2463 return 0;
2464}
2465
2466static bool xhci_is_async_ep(unsigned int ep_type)
2467{
2468 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2469 ep_type != ISOC_IN_EP &&
2470 ep_type != INT_IN_EP);
2471}
2472
2473static bool xhci_is_sync_in_ep(unsigned int ep_type)
2474{
2475 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2476}
2477
2478static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2479{
2480 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2481
2482 if (ep_bw->ep_interval == 0)
2483 return SS_OVERHEAD_BURST +
2484 (ep_bw->mult * ep_bw->num_packets *
2485 (SS_OVERHEAD + mps));
2486 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2487 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2488 1 << ep_bw->ep_interval);
2489
2490}
2491
2492static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2493 struct xhci_bw_info *ep_bw,
2494 struct xhci_interval_bw_table *bw_table,
2495 struct usb_device *udev,
2496 struct xhci_virt_ep *virt_ep,
2497 struct xhci_tt_bw_info *tt_info)
2498{
2499 struct xhci_interval_bw *interval_bw;
2500 int normalized_interval;
2501
2502 if (xhci_is_async_ep(ep_bw->type))
2503 return;
2504
2505 if (udev->speed >= USB_SPEED_SUPER) {
2506 if (xhci_is_sync_in_ep(ep_bw->type))
2507 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2508 xhci_get_ss_bw_consumed(ep_bw);
2509 else
2510 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2511 xhci_get_ss_bw_consumed(ep_bw);
2512 return;
2513 }
2514
2515 /* SuperSpeed endpoints never get added to intervals in the table, so
2516 * this check is only valid for HS/FS/LS devices.
2517 */
2518 if (list_empty(&virt_ep->bw_endpoint_list))
2519 return;
2520 /* For LS/FS devices, we need to translate the interval expressed in
2521 * microframes to frames.
2522 */
2523 if (udev->speed == USB_SPEED_HIGH)
2524 normalized_interval = ep_bw->ep_interval;
2525 else
2526 normalized_interval = ep_bw->ep_interval - 3;
2527
2528 if (normalized_interval == 0)
2529 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2530 interval_bw = &bw_table->interval_bw[normalized_interval];
2531 interval_bw->num_packets -= ep_bw->num_packets;
2532 switch (udev->speed) {
2533 case USB_SPEED_LOW:
2534 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2535 break;
2536 case USB_SPEED_FULL:
2537 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2538 break;
2539 case USB_SPEED_HIGH:
2540 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2541 break;
2542 case USB_SPEED_SUPER:
2543 case USB_SPEED_SUPER_PLUS:
2544 case USB_SPEED_UNKNOWN:
2545 case USB_SPEED_WIRELESS:
2546 /* Should never happen because only LS/FS/HS endpoints will get
2547 * added to the endpoint list.
2548 */
2549 return;
2550 }
2551 if (tt_info)
2552 tt_info->active_eps -= 1;
2553 list_del_init(&virt_ep->bw_endpoint_list);
2554}
2555
2556static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2557 struct xhci_bw_info *ep_bw,
2558 struct xhci_interval_bw_table *bw_table,
2559 struct usb_device *udev,
2560 struct xhci_virt_ep *virt_ep,
2561 struct xhci_tt_bw_info *tt_info)
2562{
2563 struct xhci_interval_bw *interval_bw;
2564 struct xhci_virt_ep *smaller_ep;
2565 int normalized_interval;
2566
2567 if (xhci_is_async_ep(ep_bw->type))
2568 return;
2569
2570 if (udev->speed == USB_SPEED_SUPER) {
2571 if (xhci_is_sync_in_ep(ep_bw->type))
2572 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2573 xhci_get_ss_bw_consumed(ep_bw);
2574 else
2575 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2576 xhci_get_ss_bw_consumed(ep_bw);
2577 return;
2578 }
2579
2580 /* For LS/FS devices, we need to translate the interval expressed in
2581 * microframes to frames.
2582 */
2583 if (udev->speed == USB_SPEED_HIGH)
2584 normalized_interval = ep_bw->ep_interval;
2585 else
2586 normalized_interval = ep_bw->ep_interval - 3;
2587
2588 if (normalized_interval == 0)
2589 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2590 interval_bw = &bw_table->interval_bw[normalized_interval];
2591 interval_bw->num_packets += ep_bw->num_packets;
2592 switch (udev->speed) {
2593 case USB_SPEED_LOW:
2594 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2595 break;
2596 case USB_SPEED_FULL:
2597 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2598 break;
2599 case USB_SPEED_HIGH:
2600 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2601 break;
2602 case USB_SPEED_SUPER:
2603 case USB_SPEED_SUPER_PLUS:
2604 case USB_SPEED_UNKNOWN:
2605 case USB_SPEED_WIRELESS:
2606 /* Should never happen because only LS/FS/HS endpoints will get
2607 * added to the endpoint list.
2608 */
2609 return;
2610 }
2611
2612 if (tt_info)
2613 tt_info->active_eps += 1;
2614 /* Insert the endpoint into the list, largest max packet size first. */
2615 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2616 bw_endpoint_list) {
2617 if (ep_bw->max_packet_size >=
2618 smaller_ep->bw_info.max_packet_size) {
2619 /* Add the new ep before the smaller endpoint */
2620 list_add_tail(&virt_ep->bw_endpoint_list,
2621 &smaller_ep->bw_endpoint_list);
2622 return;
2623 }
2624 }
2625 /* Add the new endpoint at the end of the list. */
2626 list_add_tail(&virt_ep->bw_endpoint_list,
2627 &interval_bw->endpoints);
2628}
2629
2630void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2631 struct xhci_virt_device *virt_dev,
2632 int old_active_eps)
2633{
2634 struct xhci_root_port_bw_info *rh_bw_info;
2635 if (!virt_dev->tt_info)
2636 return;
2637
2638 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2639 if (old_active_eps == 0 &&
2640 virt_dev->tt_info->active_eps != 0) {
2641 rh_bw_info->num_active_tts += 1;
2642 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2643 } else if (old_active_eps != 0 &&
2644 virt_dev->tt_info->active_eps == 0) {
2645 rh_bw_info->num_active_tts -= 1;
2646 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2647 }
2648}
2649
2650static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2651 struct xhci_virt_device *virt_dev,
2652 struct xhci_container_ctx *in_ctx)
2653{
2654 struct xhci_bw_info ep_bw_info[31];
2655 int i;
2656 struct xhci_input_control_ctx *ctrl_ctx;
2657 int old_active_eps = 0;
2658
2659 if (virt_dev->tt_info)
2660 old_active_eps = virt_dev->tt_info->active_eps;
2661
2662 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2663 if (!ctrl_ctx) {
2664 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2665 __func__);
2666 return -ENOMEM;
2667 }
2668
2669 for (i = 0; i < 31; i++) {
2670 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2671 continue;
2672
2673 /* Make a copy of the BW info in case we need to revert this */
2674 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2675 sizeof(ep_bw_info[i]));
2676 /* Drop the endpoint from the interval table if the endpoint is
2677 * being dropped or changed.
2678 */
2679 if (EP_IS_DROPPED(ctrl_ctx, i))
2680 xhci_drop_ep_from_interval_table(xhci,
2681 &virt_dev->eps[i].bw_info,
2682 virt_dev->bw_table,
2683 virt_dev->udev,
2684 &virt_dev->eps[i],
2685 virt_dev->tt_info);
2686 }
2687 /* Overwrite the information stored in the endpoints' bw_info */
2688 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2689 for (i = 0; i < 31; i++) {
2690 /* Add any changed or added endpoints to the interval table */
2691 if (EP_IS_ADDED(ctrl_ctx, i))
2692 xhci_add_ep_to_interval_table(xhci,
2693 &virt_dev->eps[i].bw_info,
2694 virt_dev->bw_table,
2695 virt_dev->udev,
2696 &virt_dev->eps[i],
2697 virt_dev->tt_info);
2698 }
2699
2700 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2701 /* Ok, this fits in the bandwidth we have.
2702 * Update the number of active TTs.
2703 */
2704 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2705 return 0;
2706 }
2707
2708 /* We don't have enough bandwidth for this, revert the stored info. */
2709 for (i = 0; i < 31; i++) {
2710 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2711 continue;
2712
2713 /* Drop the new copies of any added or changed endpoints from
2714 * the interval table.
2715 */
2716 if (EP_IS_ADDED(ctrl_ctx, i)) {
2717 xhci_drop_ep_from_interval_table(xhci,
2718 &virt_dev->eps[i].bw_info,
2719 virt_dev->bw_table,
2720 virt_dev->udev,
2721 &virt_dev->eps[i],
2722 virt_dev->tt_info);
2723 }
2724 /* Revert the endpoint back to its old information */
2725 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2726 sizeof(ep_bw_info[i]));
2727 /* Add any changed or dropped endpoints back into the table */
2728 if (EP_IS_DROPPED(ctrl_ctx, i))
2729 xhci_add_ep_to_interval_table(xhci,
2730 &virt_dev->eps[i].bw_info,
2731 virt_dev->bw_table,
2732 virt_dev->udev,
2733 &virt_dev->eps[i],
2734 virt_dev->tt_info);
2735 }
2736 return -ENOMEM;
2737}
2738
2739
2740/* Issue a configure endpoint command or evaluate context command
2741 * and wait for it to finish.
2742 */
2743static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2744 struct usb_device *udev,
2745 struct xhci_command *command,
2746 bool ctx_change, bool must_succeed)
2747{
2748 int ret;
2749 unsigned long flags;
2750 struct xhci_input_control_ctx *ctrl_ctx;
2751 struct xhci_virt_device *virt_dev;
2752 struct xhci_slot_ctx *slot_ctx;
2753
2754 if (!command)
2755 return -EINVAL;
2756
2757 spin_lock_irqsave(&xhci->lock, flags);
2758
2759 if (xhci->xhc_state & XHCI_STATE_DYING) {
2760 spin_unlock_irqrestore(&xhci->lock, flags);
2761 return -ESHUTDOWN;
2762 }
2763
2764 virt_dev = xhci->devs[udev->slot_id];
2765
2766 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2767 if (!ctrl_ctx) {
2768 spin_unlock_irqrestore(&xhci->lock, flags);
2769 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2770 __func__);
2771 return -ENOMEM;
2772 }
2773
2774 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2775 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2776 spin_unlock_irqrestore(&xhci->lock, flags);
2777 xhci_warn(xhci, "Not enough host resources, "
2778 "active endpoint contexts = %u\n",
2779 xhci->num_active_eps);
2780 return -ENOMEM;
2781 }
2782 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2783 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2784 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2785 xhci_free_host_resources(xhci, ctrl_ctx);
2786 spin_unlock_irqrestore(&xhci->lock, flags);
2787 xhci_warn(xhci, "Not enough bandwidth\n");
2788 return -ENOMEM;
2789 }
2790
2791 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2792
2793 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2794 trace_xhci_configure_endpoint(slot_ctx);
2795
2796 if (!ctx_change)
2797 ret = xhci_queue_configure_endpoint(xhci, command,
2798 command->in_ctx->dma,
2799 udev->slot_id, must_succeed);
2800 else
2801 ret = xhci_queue_evaluate_context(xhci, command,
2802 command->in_ctx->dma,
2803 udev->slot_id, must_succeed);
2804 if (ret < 0) {
2805 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2806 xhci_free_host_resources(xhci, ctrl_ctx);
2807 spin_unlock_irqrestore(&xhci->lock, flags);
2808 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2809 "FIXME allocate a new ring segment");
2810 return -ENOMEM;
2811 }
2812 xhci_ring_cmd_db(xhci);
2813 spin_unlock_irqrestore(&xhci->lock, flags);
2814
2815 /* Wait for the configure endpoint command to complete */
2816 wait_for_completion(command->completion);
2817
2818 if (!ctx_change)
2819 ret = xhci_configure_endpoint_result(xhci, udev,
2820 &command->status);
2821 else
2822 ret = xhci_evaluate_context_result(xhci, udev,
2823 &command->status);
2824
2825 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2826 spin_lock_irqsave(&xhci->lock, flags);
2827 /* If the command failed, remove the reserved resources.
2828 * Otherwise, clean up the estimate to include dropped eps.
2829 */
2830 if (ret)
2831 xhci_free_host_resources(xhci, ctrl_ctx);
2832 else
2833 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2834 spin_unlock_irqrestore(&xhci->lock, flags);
2835 }
2836 return ret;
2837}
2838
2839static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2840 struct xhci_virt_device *vdev, int i)
2841{
2842 struct xhci_virt_ep *ep = &vdev->eps[i];
2843
2844 if (ep->ep_state & EP_HAS_STREAMS) {
2845 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2846 xhci_get_endpoint_address(i));
2847 xhci_free_stream_info(xhci, ep->stream_info);
2848 ep->stream_info = NULL;
2849 ep->ep_state &= ~EP_HAS_STREAMS;
2850 }
2851}
2852
2853/* Called after one or more calls to xhci_add_endpoint() or
2854 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2855 * to call xhci_reset_bandwidth().
2856 *
2857 * Since we are in the middle of changing either configuration or
2858 * installing a new alt setting, the USB core won't allow URBs to be
2859 * enqueued for any endpoint on the old config or interface. Nothing
2860 * else should be touching the xhci->devs[slot_id] structure, so we
2861 * don't need to take the xhci->lock for manipulating that.
2862 */
2863static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2864{
2865 int i;
2866 int ret = 0;
2867 struct xhci_hcd *xhci;
2868 struct xhci_virt_device *virt_dev;
2869 struct xhci_input_control_ctx *ctrl_ctx;
2870 struct xhci_slot_ctx *slot_ctx;
2871 struct xhci_command *command;
2872
2873 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2874 if (ret <= 0)
2875 return ret;
2876 xhci = hcd_to_xhci(hcd);
2877 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2878 (xhci->xhc_state & XHCI_STATE_REMOVING))
2879 return -ENODEV;
2880
2881 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2882 virt_dev = xhci->devs[udev->slot_id];
2883
2884 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2885 if (!command)
2886 return -ENOMEM;
2887
2888 command->in_ctx = virt_dev->in_ctx;
2889
2890 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2891 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2892 if (!ctrl_ctx) {
2893 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2894 __func__);
2895 ret = -ENOMEM;
2896 goto command_cleanup;
2897 }
2898 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2899 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2900 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2901
2902 /* Don't issue the command if there's no endpoints to update. */
2903 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2904 ctrl_ctx->drop_flags == 0) {
2905 ret = 0;
2906 goto command_cleanup;
2907 }
2908 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2909 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2910 for (i = 31; i >= 1; i--) {
2911 __le32 le32 = cpu_to_le32(BIT(i));
2912
2913 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2914 || (ctrl_ctx->add_flags & le32) || i == 1) {
2915 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2916 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2917 break;
2918 }
2919 }
2920
2921 ret = xhci_configure_endpoint(xhci, udev, command,
2922 false, false);
2923 if (ret)
2924 /* Callee should call reset_bandwidth() */
2925 goto command_cleanup;
2926
2927 /* Free any rings that were dropped, but not changed. */
2928 for (i = 1; i < 31; i++) {
2929 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2930 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2931 xhci_free_endpoint_ring(xhci, virt_dev, i);
2932 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2933 }
2934 }
2935 xhci_zero_in_ctx(xhci, virt_dev);
2936 /*
2937 * Install any rings for completely new endpoints or changed endpoints,
2938 * and free any old rings from changed endpoints.
2939 */
2940 for (i = 1; i < 31; i++) {
2941 if (!virt_dev->eps[i].new_ring)
2942 continue;
2943 /* Only free the old ring if it exists.
2944 * It may not if this is the first add of an endpoint.
2945 */
2946 if (virt_dev->eps[i].ring) {
2947 xhci_free_endpoint_ring(xhci, virt_dev, i);
2948 }
2949 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2950 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2951 virt_dev->eps[i].new_ring = NULL;
2952 }
2953command_cleanup:
2954 kfree(command->completion);
2955 kfree(command);
2956
2957 return ret;
2958}
2959
2960static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2961{
2962 struct xhci_hcd *xhci;
2963 struct xhci_virt_device *virt_dev;
2964 int i, ret;
2965
2966 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2967 if (ret <= 0)
2968 return;
2969 xhci = hcd_to_xhci(hcd);
2970
2971 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2972 virt_dev = xhci->devs[udev->slot_id];
2973 /* Free any rings allocated for added endpoints */
2974 for (i = 0; i < 31; i++) {
2975 if (virt_dev->eps[i].new_ring) {
2976 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
2977 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2978 virt_dev->eps[i].new_ring = NULL;
2979 }
2980 }
2981 xhci_zero_in_ctx(xhci, virt_dev);
2982}
2983
2984static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2985 struct xhci_container_ctx *in_ctx,
2986 struct xhci_container_ctx *out_ctx,
2987 struct xhci_input_control_ctx *ctrl_ctx,
2988 u32 add_flags, u32 drop_flags)
2989{
2990 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2991 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2992 xhci_slot_copy(xhci, in_ctx, out_ctx);
2993 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2994}
2995
2996static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2997 unsigned int slot_id, unsigned int ep_index,
2998 struct xhci_dequeue_state *deq_state)
2999{
3000 struct xhci_input_control_ctx *ctrl_ctx;
3001 struct xhci_container_ctx *in_ctx;
3002 struct xhci_ep_ctx *ep_ctx;
3003 u32 added_ctxs;
3004 dma_addr_t addr;
3005
3006 in_ctx = xhci->devs[slot_id]->in_ctx;
3007 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
3008 if (!ctrl_ctx) {
3009 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3010 __func__);
3011 return;
3012 }
3013
3014 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
3015 xhci->devs[slot_id]->out_ctx, ep_index);
3016 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
3017 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3018 deq_state->new_deq_ptr);
3019 if (addr == 0) {
3020 xhci_warn(xhci, "WARN Cannot submit config ep after "
3021 "reset ep command\n");
3022 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
3023 deq_state->new_deq_seg,
3024 deq_state->new_deq_ptr);
3025 return;
3026 }
3027 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
3028
3029 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
3030 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
3031 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
3032 added_ctxs, added_ctxs);
3033}
3034
3035void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
3036 unsigned int ep_index, unsigned int stream_id,
3037 struct xhci_td *td)
3038{
3039 struct xhci_dequeue_state deq_state;
3040
3041 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3042 "Cleaning up stalled endpoint ring");
3043 /* We need to move the HW's dequeue pointer past this TD,
3044 * or it will attempt to resend it on the next doorbell ring.
3045 */
3046 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, stream_id, td,
3047 &deq_state);
3048
3049 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
3050 return;
3051
3052 /* HW with the reset endpoint quirk will use the saved dequeue state to
3053 * issue a configure endpoint command later.
3054 */
3055 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
3056 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3057 "Queueing new dequeue state");
3058 xhci_queue_new_dequeue_state(xhci, slot_id,
3059 ep_index, &deq_state);
3060 } else {
3061 /* Better hope no one uses the input context between now and the
3062 * reset endpoint completion!
3063 * XXX: No idea how this hardware will react when stream rings
3064 * are enabled.
3065 */
3066 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3067 "Setting up input context for "
3068 "configure endpoint command");
3069 xhci_setup_input_ctx_for_quirk(xhci, slot_id,
3070 ep_index, &deq_state);
3071 }
3072}
3073
3074static void xhci_endpoint_disable(struct usb_hcd *hcd,
3075 struct usb_host_endpoint *host_ep)
3076{
3077 struct xhci_hcd *xhci;
3078 struct xhci_virt_device *vdev;
3079 struct xhci_virt_ep *ep;
3080 struct usb_device *udev;
3081 unsigned long flags;
3082 unsigned int ep_index;
3083
3084 xhci = hcd_to_xhci(hcd);
3085rescan:
3086 spin_lock_irqsave(&xhci->lock, flags);
3087
3088 udev = (struct usb_device *)host_ep->hcpriv;
3089 if (!udev || !udev->slot_id)
3090 goto done;
3091
3092 vdev = xhci->devs[udev->slot_id];
3093 if (!vdev)
3094 goto done;
3095
3096 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3097 ep = &vdev->eps[ep_index];
3098 if (!ep)
3099 goto done;
3100
3101 /* wait for hub_tt_work to finish clearing hub TT */
3102 if (ep->ep_state & EP_CLEARING_TT) {
3103 spin_unlock_irqrestore(&xhci->lock, flags);
3104 schedule_timeout_uninterruptible(1);
3105 goto rescan;
3106 }
3107
3108 if (ep->ep_state)
3109 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3110 ep->ep_state);
3111done:
3112 host_ep->hcpriv = NULL;
3113 spin_unlock_irqrestore(&xhci->lock, flags);
3114}
3115
3116/*
3117 * Called after usb core issues a clear halt control message.
3118 * The host side of the halt should already be cleared by a reset endpoint
3119 * command issued when the STALL event was received.
3120 *
3121 * The reset endpoint command may only be issued to endpoints in the halted
3122 * state. For software that wishes to reset the data toggle or sequence number
3123 * of an endpoint that isn't in the halted state this function will issue a
3124 * configure endpoint command with the Drop and Add bits set for the target
3125 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3126 */
3127
3128static void xhci_endpoint_reset(struct usb_hcd *hcd,
3129 struct usb_host_endpoint *host_ep)
3130{
3131 struct xhci_hcd *xhci;
3132 struct usb_device *udev;
3133 struct xhci_virt_device *vdev;
3134 struct xhci_virt_ep *ep;
3135 struct xhci_input_control_ctx *ctrl_ctx;
3136 struct xhci_command *stop_cmd, *cfg_cmd;
3137 unsigned int ep_index;
3138 unsigned long flags;
3139 u32 ep_flag;
3140 int err;
3141
3142 xhci = hcd_to_xhci(hcd);
3143 if (!host_ep->hcpriv)
3144 return;
3145 udev = (struct usb_device *) host_ep->hcpriv;
3146 vdev = xhci->devs[udev->slot_id];
3147
3148 /*
3149 * vdev may be lost due to xHC restore error and re-initialization
3150 * during S3/S4 resume. A new vdev will be allocated later by
3151 * xhci_discover_or_reset_device()
3152 */
3153 if (!udev->slot_id || !vdev)
3154 return;
3155 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3156 ep = &vdev->eps[ep_index];
3157 if (!ep)
3158 return;
3159
3160 /* Bail out if toggle is already being cleared by a endpoint reset */
3161 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3162 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3163 return;
3164 }
3165 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3166 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3167 usb_endpoint_xfer_isoc(&host_ep->desc))
3168 return;
3169
3170 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3171
3172 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3173 return;
3174
3175 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3176 if (!stop_cmd)
3177 return;
3178
3179 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3180 if (!cfg_cmd)
3181 goto cleanup;
3182
3183 spin_lock_irqsave(&xhci->lock, flags);
3184
3185 /* block queuing new trbs and ringing ep doorbell */
3186 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3187
3188 /*
3189 * Make sure endpoint ring is empty before resetting the toggle/seq.
3190 * Driver is required to synchronously cancel all transfer request.
3191 * Stop the endpoint to force xHC to update the output context
3192 */
3193
3194 if (!list_empty(&ep->ring->td_list)) {
3195 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3196 spin_unlock_irqrestore(&xhci->lock, flags);
3197 xhci_free_command(xhci, cfg_cmd);
3198 goto cleanup;
3199 }
3200
3201 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3202 ep_index, 0);
3203 if (err < 0) {
3204 spin_unlock_irqrestore(&xhci->lock, flags);
3205 xhci_free_command(xhci, cfg_cmd);
3206 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3207 __func__, err);
3208 goto cleanup;
3209 }
3210
3211 xhci_ring_cmd_db(xhci);
3212 spin_unlock_irqrestore(&xhci->lock, flags);
3213
3214 wait_for_completion(stop_cmd->completion);
3215
3216 spin_lock_irqsave(&xhci->lock, flags);
3217
3218 /* config ep command clears toggle if add and drop ep flags are set */
3219 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3220 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3221 ctrl_ctx, ep_flag, ep_flag);
3222 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3223
3224 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3225 udev->slot_id, false);
3226 if (err < 0) {
3227 spin_unlock_irqrestore(&xhci->lock, flags);
3228 xhci_free_command(xhci, cfg_cmd);
3229 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3230 __func__, err);
3231 goto cleanup;
3232 }
3233
3234 xhci_ring_cmd_db(xhci);
3235 spin_unlock_irqrestore(&xhci->lock, flags);
3236
3237 wait_for_completion(cfg_cmd->completion);
3238
3239 xhci_free_command(xhci, cfg_cmd);
3240cleanup:
3241 xhci_free_command(xhci, stop_cmd);
3242 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3243 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3244}
3245
3246static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3247 struct usb_device *udev, struct usb_host_endpoint *ep,
3248 unsigned int slot_id)
3249{
3250 int ret;
3251 unsigned int ep_index;
3252 unsigned int ep_state;
3253
3254 if (!ep)
3255 return -EINVAL;
3256 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3257 if (ret <= 0)
3258 return -EINVAL;
3259 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3260 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3261 " descriptor for ep 0x%x does not support streams\n",
3262 ep->desc.bEndpointAddress);
3263 return -EINVAL;
3264 }
3265
3266 ep_index = xhci_get_endpoint_index(&ep->desc);
3267 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3268 if (ep_state & EP_HAS_STREAMS ||
3269 ep_state & EP_GETTING_STREAMS) {
3270 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3271 "already has streams set up.\n",
3272 ep->desc.bEndpointAddress);
3273 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3274 "dynamic stream context array reallocation.\n");
3275 return -EINVAL;
3276 }
3277 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3278 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3279 "endpoint 0x%x; URBs are pending.\n",
3280 ep->desc.bEndpointAddress);
3281 return -EINVAL;
3282 }
3283 return 0;
3284}
3285
3286static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3287 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3288{
3289 unsigned int max_streams;
3290
3291 /* The stream context array size must be a power of two */
3292 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3293 /*
3294 * Find out how many primary stream array entries the host controller
3295 * supports. Later we may use secondary stream arrays (similar to 2nd
3296 * level page entries), but that's an optional feature for xHCI host
3297 * controllers. xHCs must support at least 4 stream IDs.
3298 */
3299 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3300 if (*num_stream_ctxs > max_streams) {
3301 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3302 max_streams);
3303 *num_stream_ctxs = max_streams;
3304 *num_streams = max_streams;
3305 }
3306}
3307
3308/* Returns an error code if one of the endpoint already has streams.
3309 * This does not change any data structures, it only checks and gathers
3310 * information.
3311 */
3312static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3313 struct usb_device *udev,
3314 struct usb_host_endpoint **eps, unsigned int num_eps,
3315 unsigned int *num_streams, u32 *changed_ep_bitmask)
3316{
3317 unsigned int max_streams;
3318 unsigned int endpoint_flag;
3319 int i;
3320 int ret;
3321
3322 for (i = 0; i < num_eps; i++) {
3323 ret = xhci_check_streams_endpoint(xhci, udev,
3324 eps[i], udev->slot_id);
3325 if (ret < 0)
3326 return ret;
3327
3328 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3329 if (max_streams < (*num_streams - 1)) {
3330 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3331 eps[i]->desc.bEndpointAddress,
3332 max_streams);
3333 *num_streams = max_streams+1;
3334 }
3335
3336 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3337 if (*changed_ep_bitmask & endpoint_flag)
3338 return -EINVAL;
3339 *changed_ep_bitmask |= endpoint_flag;
3340 }
3341 return 0;
3342}
3343
3344static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3345 struct usb_device *udev,
3346 struct usb_host_endpoint **eps, unsigned int num_eps)
3347{
3348 u32 changed_ep_bitmask = 0;
3349 unsigned int slot_id;
3350 unsigned int ep_index;
3351 unsigned int ep_state;
3352 int i;
3353
3354 slot_id = udev->slot_id;
3355 if (!xhci->devs[slot_id])
3356 return 0;
3357
3358 for (i = 0; i < num_eps; i++) {
3359 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3360 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3361 /* Are streams already being freed for the endpoint? */
3362 if (ep_state & EP_GETTING_NO_STREAMS) {
3363 xhci_warn(xhci, "WARN Can't disable streams for "
3364 "endpoint 0x%x, "
3365 "streams are being disabled already\n",
3366 eps[i]->desc.bEndpointAddress);
3367 return 0;
3368 }
3369 /* Are there actually any streams to free? */
3370 if (!(ep_state & EP_HAS_STREAMS) &&
3371 !(ep_state & EP_GETTING_STREAMS)) {
3372 xhci_warn(xhci, "WARN Can't disable streams for "
3373 "endpoint 0x%x, "
3374 "streams are already disabled!\n",
3375 eps[i]->desc.bEndpointAddress);
3376 xhci_warn(xhci, "WARN xhci_free_streams() called "
3377 "with non-streams endpoint\n");
3378 return 0;
3379 }
3380 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3381 }
3382 return changed_ep_bitmask;
3383}
3384
3385/*
3386 * The USB device drivers use this function (through the HCD interface in USB
3387 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3388 * coordinate mass storage command queueing across multiple endpoints (basically
3389 * a stream ID == a task ID).
3390 *
3391 * Setting up streams involves allocating the same size stream context array
3392 * for each endpoint and issuing a configure endpoint command for all endpoints.
3393 *
3394 * Don't allow the call to succeed if one endpoint only supports one stream
3395 * (which means it doesn't support streams at all).
3396 *
3397 * Drivers may get less stream IDs than they asked for, if the host controller
3398 * hardware or endpoints claim they can't support the number of requested
3399 * stream IDs.
3400 */
3401static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3402 struct usb_host_endpoint **eps, unsigned int num_eps,
3403 unsigned int num_streams, gfp_t mem_flags)
3404{
3405 int i, ret;
3406 struct xhci_hcd *xhci;
3407 struct xhci_virt_device *vdev;
3408 struct xhci_command *config_cmd;
3409 struct xhci_input_control_ctx *ctrl_ctx;
3410 unsigned int ep_index;
3411 unsigned int num_stream_ctxs;
3412 unsigned int max_packet;
3413 unsigned long flags;
3414 u32 changed_ep_bitmask = 0;
3415
3416 if (!eps)
3417 return -EINVAL;
3418
3419 /* Add one to the number of streams requested to account for
3420 * stream 0 that is reserved for xHCI usage.
3421 */
3422 num_streams += 1;
3423 xhci = hcd_to_xhci(hcd);
3424 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3425 num_streams);
3426
3427 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3428 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3429 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3430 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3431 return -ENOSYS;
3432 }
3433
3434 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3435 if (!config_cmd)
3436 return -ENOMEM;
3437
3438 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3439 if (!ctrl_ctx) {
3440 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3441 __func__);
3442 xhci_free_command(xhci, config_cmd);
3443 return -ENOMEM;
3444 }
3445
3446 /* Check to make sure all endpoints are not already configured for
3447 * streams. While we're at it, find the maximum number of streams that
3448 * all the endpoints will support and check for duplicate endpoints.
3449 */
3450 spin_lock_irqsave(&xhci->lock, flags);
3451 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3452 num_eps, &num_streams, &changed_ep_bitmask);
3453 if (ret < 0) {
3454 xhci_free_command(xhci, config_cmd);
3455 spin_unlock_irqrestore(&xhci->lock, flags);
3456 return ret;
3457 }
3458 if (num_streams <= 1) {
3459 xhci_warn(xhci, "WARN: endpoints can't handle "
3460 "more than one stream.\n");
3461 xhci_free_command(xhci, config_cmd);
3462 spin_unlock_irqrestore(&xhci->lock, flags);
3463 return -EINVAL;
3464 }
3465 vdev = xhci->devs[udev->slot_id];
3466 /* Mark each endpoint as being in transition, so
3467 * xhci_urb_enqueue() will reject all URBs.
3468 */
3469 for (i = 0; i < num_eps; i++) {
3470 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3471 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3472 }
3473 spin_unlock_irqrestore(&xhci->lock, flags);
3474
3475 /* Setup internal data structures and allocate HW data structures for
3476 * streams (but don't install the HW structures in the input context
3477 * until we're sure all memory allocation succeeded).
3478 */
3479 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3480 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3481 num_stream_ctxs, num_streams);
3482
3483 for (i = 0; i < num_eps; i++) {
3484 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3485 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3486 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3487 num_stream_ctxs,
3488 num_streams,
3489 max_packet, mem_flags);
3490 if (!vdev->eps[ep_index].stream_info)
3491 goto cleanup;
3492 /* Set maxPstreams in endpoint context and update deq ptr to
3493 * point to stream context array. FIXME
3494 */
3495 }
3496
3497 /* Set up the input context for a configure endpoint command. */
3498 for (i = 0; i < num_eps; i++) {
3499 struct xhci_ep_ctx *ep_ctx;
3500
3501 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3502 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3503
3504 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3505 vdev->out_ctx, ep_index);
3506 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3507 vdev->eps[ep_index].stream_info);
3508 }
3509 /* Tell the HW to drop its old copy of the endpoint context info
3510 * and add the updated copy from the input context.
3511 */
3512 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3513 vdev->out_ctx, ctrl_ctx,
3514 changed_ep_bitmask, changed_ep_bitmask);
3515
3516 /* Issue and wait for the configure endpoint command */
3517 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3518 false, false);
3519
3520 /* xHC rejected the configure endpoint command for some reason, so we
3521 * leave the old ring intact and free our internal streams data
3522 * structure.
3523 */
3524 if (ret < 0)
3525 goto cleanup;
3526
3527 spin_lock_irqsave(&xhci->lock, flags);
3528 for (i = 0; i < num_eps; i++) {
3529 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3530 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3531 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3532 udev->slot_id, ep_index);
3533 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3534 }
3535 xhci_free_command(xhci, config_cmd);
3536 spin_unlock_irqrestore(&xhci->lock, flags);
3537
3538 /* Subtract 1 for stream 0, which drivers can't use */
3539 return num_streams - 1;
3540
3541cleanup:
3542 /* If it didn't work, free the streams! */
3543 for (i = 0; i < num_eps; i++) {
3544 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3545 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3546 vdev->eps[ep_index].stream_info = NULL;
3547 /* FIXME Unset maxPstreams in endpoint context and
3548 * update deq ptr to point to normal string ring.
3549 */
3550 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3551 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3552 xhci_endpoint_zero(xhci, vdev, eps[i]);
3553 }
3554 xhci_free_command(xhci, config_cmd);
3555 return -ENOMEM;
3556}
3557
3558/* Transition the endpoint from using streams to being a "normal" endpoint
3559 * without streams.
3560 *
3561 * Modify the endpoint context state, submit a configure endpoint command,
3562 * and free all endpoint rings for streams if that completes successfully.
3563 */
3564static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3565 struct usb_host_endpoint **eps, unsigned int num_eps,
3566 gfp_t mem_flags)
3567{
3568 int i, ret;
3569 struct xhci_hcd *xhci;
3570 struct xhci_virt_device *vdev;
3571 struct xhci_command *command;
3572 struct xhci_input_control_ctx *ctrl_ctx;
3573 unsigned int ep_index;
3574 unsigned long flags;
3575 u32 changed_ep_bitmask;
3576
3577 xhci = hcd_to_xhci(hcd);
3578 vdev = xhci->devs[udev->slot_id];
3579
3580 /* Set up a configure endpoint command to remove the streams rings */
3581 spin_lock_irqsave(&xhci->lock, flags);
3582 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3583 udev, eps, num_eps);
3584 if (changed_ep_bitmask == 0) {
3585 spin_unlock_irqrestore(&xhci->lock, flags);
3586 return -EINVAL;
3587 }
3588
3589 /* Use the xhci_command structure from the first endpoint. We may have
3590 * allocated too many, but the driver may call xhci_free_streams() for
3591 * each endpoint it grouped into one call to xhci_alloc_streams().
3592 */
3593 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3594 command = vdev->eps[ep_index].stream_info->free_streams_command;
3595 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3596 if (!ctrl_ctx) {
3597 spin_unlock_irqrestore(&xhci->lock, flags);
3598 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3599 __func__);
3600 return -EINVAL;
3601 }
3602
3603 for (i = 0; i < num_eps; i++) {
3604 struct xhci_ep_ctx *ep_ctx;
3605
3606 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3607 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3608 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3609 EP_GETTING_NO_STREAMS;
3610
3611 xhci_endpoint_copy(xhci, command->in_ctx,
3612 vdev->out_ctx, ep_index);
3613 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3614 &vdev->eps[ep_index]);
3615 }
3616 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3617 vdev->out_ctx, ctrl_ctx,
3618 changed_ep_bitmask, changed_ep_bitmask);
3619 spin_unlock_irqrestore(&xhci->lock, flags);
3620
3621 /* Issue and wait for the configure endpoint command,
3622 * which must succeed.
3623 */
3624 ret = xhci_configure_endpoint(xhci, udev, command,
3625 false, true);
3626
3627 /* xHC rejected the configure endpoint command for some reason, so we
3628 * leave the streams rings intact.
3629 */
3630 if (ret < 0)
3631 return ret;
3632
3633 spin_lock_irqsave(&xhci->lock, flags);
3634 for (i = 0; i < num_eps; i++) {
3635 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3636 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3637 vdev->eps[ep_index].stream_info = NULL;
3638 /* FIXME Unset maxPstreams in endpoint context and
3639 * update deq ptr to point to normal string ring.
3640 */
3641 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3642 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3643 }
3644 spin_unlock_irqrestore(&xhci->lock, flags);
3645
3646 return 0;
3647}
3648
3649/*
3650 * Deletes endpoint resources for endpoints that were active before a Reset
3651 * Device command, or a Disable Slot command. The Reset Device command leaves
3652 * the control endpoint intact, whereas the Disable Slot command deletes it.
3653 *
3654 * Must be called with xhci->lock held.
3655 */
3656void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3657 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3658{
3659 int i;
3660 unsigned int num_dropped_eps = 0;
3661 unsigned int drop_flags = 0;
3662
3663 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3664 if (virt_dev->eps[i].ring) {
3665 drop_flags |= 1 << i;
3666 num_dropped_eps++;
3667 }
3668 }
3669 xhci->num_active_eps -= num_dropped_eps;
3670 if (num_dropped_eps)
3671 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3672 "Dropped %u ep ctxs, flags = 0x%x, "
3673 "%u now active.",
3674 num_dropped_eps, drop_flags,
3675 xhci->num_active_eps);
3676}
3677
3678/*
3679 * This submits a Reset Device Command, which will set the device state to 0,
3680 * set the device address to 0, and disable all the endpoints except the default
3681 * control endpoint. The USB core should come back and call
3682 * xhci_address_device(), and then re-set up the configuration. If this is
3683 * called because of a usb_reset_and_verify_device(), then the old alternate
3684 * settings will be re-installed through the normal bandwidth allocation
3685 * functions.
3686 *
3687 * Wait for the Reset Device command to finish. Remove all structures
3688 * associated with the endpoints that were disabled. Clear the input device
3689 * structure? Reset the control endpoint 0 max packet size?
3690 *
3691 * If the virt_dev to be reset does not exist or does not match the udev,
3692 * it means the device is lost, possibly due to the xHC restore error and
3693 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3694 * re-allocate the device.
3695 */
3696static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3697 struct usb_device *udev)
3698{
3699 int ret, i;
3700 unsigned long flags;
3701 struct xhci_hcd *xhci;
3702 unsigned int slot_id;
3703 struct xhci_virt_device *virt_dev;
3704 struct xhci_command *reset_device_cmd;
3705 struct xhci_slot_ctx *slot_ctx;
3706 int old_active_eps = 0;
3707
3708 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3709 if (ret <= 0)
3710 return ret;
3711 xhci = hcd_to_xhci(hcd);
3712 slot_id = udev->slot_id;
3713 virt_dev = xhci->devs[slot_id];
3714 if (!virt_dev) {
3715 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3716 "not exist. Re-allocate the device\n", slot_id);
3717 ret = xhci_alloc_dev(hcd, udev);
3718 if (ret == 1)
3719 return 0;
3720 else
3721 return -EINVAL;
3722 }
3723
3724 if (virt_dev->tt_info)
3725 old_active_eps = virt_dev->tt_info->active_eps;
3726
3727 if (virt_dev->udev != udev) {
3728 /* If the virt_dev and the udev does not match, this virt_dev
3729 * may belong to another udev.
3730 * Re-allocate the device.
3731 */
3732 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3733 "not match the udev. Re-allocate the device\n",
3734 slot_id);
3735 ret = xhci_alloc_dev(hcd, udev);
3736 if (ret == 1)
3737 return 0;
3738 else
3739 return -EINVAL;
3740 }
3741
3742 /* If device is not setup, there is no point in resetting it */
3743 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3744 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3745 SLOT_STATE_DISABLED)
3746 return 0;
3747
3748 trace_xhci_discover_or_reset_device(slot_ctx);
3749
3750 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3751 /* Allocate the command structure that holds the struct completion.
3752 * Assume we're in process context, since the normal device reset
3753 * process has to wait for the device anyway. Storage devices are
3754 * reset as part of error handling, so use GFP_NOIO instead of
3755 * GFP_KERNEL.
3756 */
3757 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3758 if (!reset_device_cmd) {
3759 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3760 return -ENOMEM;
3761 }
3762
3763 /* Attempt to submit the Reset Device command to the command ring */
3764 spin_lock_irqsave(&xhci->lock, flags);
3765
3766 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3767 if (ret) {
3768 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3769 spin_unlock_irqrestore(&xhci->lock, flags);
3770 goto command_cleanup;
3771 }
3772 xhci_ring_cmd_db(xhci);
3773 spin_unlock_irqrestore(&xhci->lock, flags);
3774
3775 /* Wait for the Reset Device command to finish */
3776 wait_for_completion(reset_device_cmd->completion);
3777
3778 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3779 * unless we tried to reset a slot ID that wasn't enabled,
3780 * or the device wasn't in the addressed or configured state.
3781 */
3782 ret = reset_device_cmd->status;
3783 switch (ret) {
3784 case COMP_COMMAND_ABORTED:
3785 case COMP_COMMAND_RING_STOPPED:
3786 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3787 ret = -ETIME;
3788 goto command_cleanup;
3789 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3790 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3791 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3792 slot_id,
3793 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3794 xhci_dbg(xhci, "Not freeing device rings.\n");
3795 /* Don't treat this as an error. May change my mind later. */
3796 ret = 0;
3797 goto command_cleanup;
3798 case COMP_SUCCESS:
3799 xhci_dbg(xhci, "Successful reset device command.\n");
3800 break;
3801 default:
3802 if (xhci_is_vendor_info_code(xhci, ret))
3803 break;
3804 xhci_warn(xhci, "Unknown completion code %u for "
3805 "reset device command.\n", ret);
3806 ret = -EINVAL;
3807 goto command_cleanup;
3808 }
3809
3810 /* Free up host controller endpoint resources */
3811 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3812 spin_lock_irqsave(&xhci->lock, flags);
3813 /* Don't delete the default control endpoint resources */
3814 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3815 spin_unlock_irqrestore(&xhci->lock, flags);
3816 }
3817
3818 /* Everything but endpoint 0 is disabled, so free the rings. */
3819 for (i = 1; i < 31; i++) {
3820 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3821
3822 if (ep->ep_state & EP_HAS_STREAMS) {
3823 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3824 xhci_get_endpoint_address(i));
3825 xhci_free_stream_info(xhci, ep->stream_info);
3826 ep->stream_info = NULL;
3827 ep->ep_state &= ~EP_HAS_STREAMS;
3828 }
3829
3830 if (ep->ring) {
3831 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3832 xhci_free_endpoint_ring(xhci, virt_dev, i);
3833 }
3834 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3835 xhci_drop_ep_from_interval_table(xhci,
3836 &virt_dev->eps[i].bw_info,
3837 virt_dev->bw_table,
3838 udev,
3839 &virt_dev->eps[i],
3840 virt_dev->tt_info);
3841 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3842 }
3843 /* If necessary, update the number of active TTs on this root port */
3844 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3845 virt_dev->flags = 0;
3846 ret = 0;
3847
3848command_cleanup:
3849 xhci_free_command(xhci, reset_device_cmd);
3850 return ret;
3851}
3852
3853/*
3854 * At this point, the struct usb_device is about to go away, the device has
3855 * disconnected, and all traffic has been stopped and the endpoints have been
3856 * disabled. Free any HC data structures associated with that device.
3857 */
3858static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3859{
3860 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3861 struct xhci_virt_device *virt_dev;
3862 struct xhci_slot_ctx *slot_ctx;
3863 int i, ret;
3864
3865#ifndef CONFIG_USB_DEFAULT_PERSIST
3866 /*
3867 * We called pm_runtime_get_noresume when the device was attached.
3868 * Decrement the counter here to allow controller to runtime suspend
3869 * if no devices remain.
3870 */
3871 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3872 pm_runtime_put_noidle(hcd->self.controller);
3873#endif
3874
3875 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3876 /* If the host is halted due to driver unload, we still need to free the
3877 * device.
3878 */
3879 if (ret <= 0 && ret != -ENODEV)
3880 return;
3881
3882 virt_dev = xhci->devs[udev->slot_id];
3883 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3884 trace_xhci_free_dev(slot_ctx);
3885
3886 /* Stop any wayward timer functions (which may grab the lock) */
3887 for (i = 0; i < 31; i++) {
3888 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3889 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3890 }
3891 virt_dev->udev = NULL;
3892 ret = xhci_disable_slot(xhci, udev->slot_id);
3893 if (ret)
3894 xhci_free_virt_device(xhci, udev->slot_id);
3895}
3896
3897int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3898{
3899 struct xhci_command *command;
3900 unsigned long flags;
3901 u32 state;
3902 int ret = 0;
3903
3904 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
3905 if (!command)
3906 return -ENOMEM;
3907
3908 xhci_debugfs_remove_slot(xhci, slot_id);
3909
3910 spin_lock_irqsave(&xhci->lock, flags);
3911 /* Don't disable the slot if the host controller is dead. */
3912 state = readl(&xhci->op_regs->status);
3913 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3914 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3915 spin_unlock_irqrestore(&xhci->lock, flags);
3916 kfree(command);
3917 return -ENODEV;
3918 }
3919
3920 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3921 slot_id);
3922 if (ret) {
3923 spin_unlock_irqrestore(&xhci->lock, flags);
3924 kfree(command);
3925 return ret;
3926 }
3927 xhci_ring_cmd_db(xhci);
3928 spin_unlock_irqrestore(&xhci->lock, flags);
3929 return ret;
3930}
3931
3932/*
3933 * Checks if we have enough host controller resources for the default control
3934 * endpoint.
3935 *
3936 * Must be called with xhci->lock held.
3937 */
3938static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3939{
3940 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3941 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3942 "Not enough ep ctxs: "
3943 "%u active, need to add 1, limit is %u.",
3944 xhci->num_active_eps, xhci->limit_active_eps);
3945 return -ENOMEM;
3946 }
3947 xhci->num_active_eps += 1;
3948 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3949 "Adding 1 ep ctx, %u now active.",
3950 xhci->num_active_eps);
3951 return 0;
3952}
3953
3954
3955/*
3956 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3957 * timed out, or allocating memory failed. Returns 1 on success.
3958 */
3959int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3960{
3961 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3962 struct xhci_virt_device *vdev;
3963 struct xhci_slot_ctx *slot_ctx;
3964 unsigned long flags;
3965 int ret, slot_id;
3966 struct xhci_command *command;
3967
3968 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3969 if (!command)
3970 return 0;
3971
3972 spin_lock_irqsave(&xhci->lock, flags);
3973 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3974 if (ret) {
3975 spin_unlock_irqrestore(&xhci->lock, flags);
3976 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3977 xhci_free_command(xhci, command);
3978 return 0;
3979 }
3980 xhci_ring_cmd_db(xhci);
3981 spin_unlock_irqrestore(&xhci->lock, flags);
3982
3983 wait_for_completion(command->completion);
3984 slot_id = command->slot_id;
3985
3986 if (!slot_id || command->status != COMP_SUCCESS) {
3987 xhci_err(xhci, "Error while assigning device slot ID\n");
3988 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3989 HCS_MAX_SLOTS(
3990 readl(&xhci->cap_regs->hcs_params1)));
3991 xhci_free_command(xhci, command);
3992 return 0;
3993 }
3994
3995 xhci_free_command(xhci, command);
3996
3997 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3998 spin_lock_irqsave(&xhci->lock, flags);
3999 ret = xhci_reserve_host_control_ep_resources(xhci);
4000 if (ret) {
4001 spin_unlock_irqrestore(&xhci->lock, flags);
4002 xhci_warn(xhci, "Not enough host resources, "
4003 "active endpoint contexts = %u\n",
4004 xhci->num_active_eps);
4005 goto disable_slot;
4006 }
4007 spin_unlock_irqrestore(&xhci->lock, flags);
4008 }
4009 /* Use GFP_NOIO, since this function can be called from
4010 * xhci_discover_or_reset_device(), which may be called as part of
4011 * mass storage driver error handling.
4012 */
4013 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4014 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4015 goto disable_slot;
4016 }
4017 vdev = xhci->devs[slot_id];
4018 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4019 trace_xhci_alloc_dev(slot_ctx);
4020
4021 udev->slot_id = slot_id;
4022
4023 xhci_debugfs_create_slot(xhci, slot_id);
4024
4025#ifndef CONFIG_USB_DEFAULT_PERSIST
4026 /*
4027 * If resetting upon resume, we can't put the controller into runtime
4028 * suspend if there is a device attached.
4029 */
4030 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4031 pm_runtime_get_noresume(hcd->self.controller);
4032#endif
4033
4034 /* Is this a LS or FS device under a HS hub? */
4035 /* Hub or peripherial? */
4036 return 1;
4037
4038disable_slot:
4039 ret = xhci_disable_slot(xhci, udev->slot_id);
4040 if (ret)
4041 xhci_free_virt_device(xhci, udev->slot_id);
4042
4043 return 0;
4044}
4045
4046/*
4047 * Issue an Address Device command and optionally send a corresponding
4048 * SetAddress request to the device.
4049 */
4050static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4051 enum xhci_setup_dev setup)
4052{
4053 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4054 unsigned long flags;
4055 struct xhci_virt_device *virt_dev;
4056 int ret = 0;
4057 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4058 struct xhci_slot_ctx *slot_ctx;
4059 struct xhci_input_control_ctx *ctrl_ctx;
4060 u64 temp_64;
4061 struct xhci_command *command = NULL;
4062
4063 mutex_lock(&xhci->mutex);
4064
4065 if (xhci->xhc_state) { /* dying, removing or halted */
4066 ret = -ESHUTDOWN;
4067 goto out;
4068 }
4069
4070 if (!udev->slot_id) {
4071 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4072 "Bad Slot ID %d", udev->slot_id);
4073 ret = -EINVAL;
4074 goto out;
4075 }
4076
4077 virt_dev = xhci->devs[udev->slot_id];
4078
4079 if (WARN_ON(!virt_dev)) {
4080 /*
4081 * In plug/unplug torture test with an NEC controller,
4082 * a zero-dereference was observed once due to virt_dev = 0.
4083 * Print useful debug rather than crash if it is observed again!
4084 */
4085 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4086 udev->slot_id);
4087 ret = -EINVAL;
4088 goto out;
4089 }
4090 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4091 trace_xhci_setup_device_slot(slot_ctx);
4092
4093 if (setup == SETUP_CONTEXT_ONLY) {
4094 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4095 SLOT_STATE_DEFAULT) {
4096 xhci_dbg(xhci, "Slot already in default state\n");
4097 goto out;
4098 }
4099 }
4100
4101 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4102 if (!command) {
4103 ret = -ENOMEM;
4104 goto out;
4105 }
4106
4107 command->in_ctx = virt_dev->in_ctx;
4108
4109 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4110 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4111 if (!ctrl_ctx) {
4112 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4113 __func__);
4114 ret = -EINVAL;
4115 goto out;
4116 }
4117 /*
4118 * If this is the first Set Address since device plug-in or
4119 * virt_device realloaction after a resume with an xHCI power loss,
4120 * then set up the slot context.
4121 */
4122 if (!slot_ctx->dev_info)
4123 xhci_setup_addressable_virt_dev(xhci, udev);
4124 /* Otherwise, update the control endpoint ring enqueue pointer. */
4125 else
4126 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4127 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4128 ctrl_ctx->drop_flags = 0;
4129
4130 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4131 le32_to_cpu(slot_ctx->dev_info) >> 27);
4132
4133 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4134 spin_lock_irqsave(&xhci->lock, flags);
4135 trace_xhci_setup_device(virt_dev);
4136 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4137 udev->slot_id, setup);
4138 if (ret) {
4139 spin_unlock_irqrestore(&xhci->lock, flags);
4140 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4141 "FIXME: allocate a command ring segment");
4142 goto out;
4143 }
4144 xhci_ring_cmd_db(xhci);
4145 spin_unlock_irqrestore(&xhci->lock, flags);
4146
4147 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4148 wait_for_completion(command->completion);
4149
4150 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4151 * the SetAddress() "recovery interval" required by USB and aborting the
4152 * command on a timeout.
4153 */
4154 switch (command->status) {
4155 case COMP_COMMAND_ABORTED:
4156 case COMP_COMMAND_RING_STOPPED:
4157 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4158 ret = -ETIME;
4159 break;
4160 case COMP_CONTEXT_STATE_ERROR:
4161 case COMP_SLOT_NOT_ENABLED_ERROR:
4162 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4163 act, udev->slot_id);
4164 ret = -EINVAL;
4165 break;
4166 case COMP_USB_TRANSACTION_ERROR:
4167 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4168
4169 mutex_unlock(&xhci->mutex);
4170 ret = xhci_disable_slot(xhci, udev->slot_id);
4171 if (!ret)
4172 xhci_alloc_dev(hcd, udev);
4173 kfree(command->completion);
4174 kfree(command);
4175 return -EPROTO;
4176 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4177 dev_warn(&udev->dev,
4178 "ERROR: Incompatible device for setup %s command\n", act);
4179 ret = -ENODEV;
4180 break;
4181 case COMP_SUCCESS:
4182 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4183 "Successful setup %s command", act);
4184 break;
4185 default:
4186 xhci_err(xhci,
4187 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4188 act, command->status);
4189 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4190 ret = -EINVAL;
4191 break;
4192 }
4193 if (ret)
4194 goto out;
4195 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4196 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4197 "Op regs DCBAA ptr = %#016llx", temp_64);
4198 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4199 "Slot ID %d dcbaa entry @%p = %#016llx",
4200 udev->slot_id,
4201 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4202 (unsigned long long)
4203 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4204 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4205 "Output Context DMA address = %#08llx",
4206 (unsigned long long)virt_dev->out_ctx->dma);
4207 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4208 le32_to_cpu(slot_ctx->dev_info) >> 27);
4209 /*
4210 * USB core uses address 1 for the roothubs, so we add one to the
4211 * address given back to us by the HC.
4212 */
4213 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4214 le32_to_cpu(slot_ctx->dev_info) >> 27);
4215 /* Zero the input context control for later use */
4216 ctrl_ctx->add_flags = 0;
4217 ctrl_ctx->drop_flags = 0;
4218 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4219 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4220
4221 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4222 "Internal device address = %d",
4223 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4224out:
4225 mutex_unlock(&xhci->mutex);
4226 if (command) {
4227 kfree(command->completion);
4228 kfree(command);
4229 }
4230 return ret;
4231}
4232
4233static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4234{
4235 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4236}
4237
4238static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4239{
4240 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4241}
4242
4243/*
4244 * Transfer the port index into real index in the HW port status
4245 * registers. Caculate offset between the port's PORTSC register
4246 * and port status base. Divide the number of per port register
4247 * to get the real index. The raw port number bases 1.
4248 */
4249int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4250{
4251 struct xhci_hub *rhub;
4252
4253 rhub = xhci_get_rhub(hcd);
4254 return rhub->ports[port1 - 1]->hw_portnum + 1;
4255}
4256
4257/*
4258 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4259 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4260 */
4261static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4262 struct usb_device *udev, u16 max_exit_latency)
4263{
4264 struct xhci_virt_device *virt_dev;
4265 struct xhci_command *command;
4266 struct xhci_input_control_ctx *ctrl_ctx;
4267 struct xhci_slot_ctx *slot_ctx;
4268 unsigned long flags;
4269 int ret;
4270
4271 spin_lock_irqsave(&xhci->lock, flags);
4272
4273 virt_dev = xhci->devs[udev->slot_id];
4274
4275 /*
4276 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4277 * xHC was re-initialized. Exit latency will be set later after
4278 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4279 */
4280
4281 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4282 spin_unlock_irqrestore(&xhci->lock, flags);
4283 return 0;
4284 }
4285
4286 /* Attempt to issue an Evaluate Context command to change the MEL. */
4287 command = xhci->lpm_command;
4288 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4289 if (!ctrl_ctx) {
4290 spin_unlock_irqrestore(&xhci->lock, flags);
4291 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4292 __func__);
4293 return -ENOMEM;
4294 }
4295
4296 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4297 spin_unlock_irqrestore(&xhci->lock, flags);
4298
4299 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4300 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4301 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4302 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4303 slot_ctx->dev_state = 0;
4304
4305 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4306 "Set up evaluate context for LPM MEL change.");
4307
4308 /* Issue and wait for the evaluate context command. */
4309 ret = xhci_configure_endpoint(xhci, udev, command,
4310 true, true);
4311
4312 if (!ret) {
4313 spin_lock_irqsave(&xhci->lock, flags);
4314 virt_dev->current_mel = max_exit_latency;
4315 spin_unlock_irqrestore(&xhci->lock, flags);
4316 }
4317 return ret;
4318}
4319
4320#ifdef CONFIG_PM
4321
4322/* BESL to HIRD Encoding array for USB2 LPM */
4323static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4324 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4325
4326/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4327static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4328 struct usb_device *udev)
4329{
4330 int u2del, besl, besl_host;
4331 int besl_device = 0;
4332 u32 field;
4333
4334 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4335 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4336
4337 if (field & USB_BESL_SUPPORT) {
4338 for (besl_host = 0; besl_host < 16; besl_host++) {
4339 if (xhci_besl_encoding[besl_host] >= u2del)
4340 break;
4341 }
4342 /* Use baseline BESL value as default */
4343 if (field & USB_BESL_BASELINE_VALID)
4344 besl_device = USB_GET_BESL_BASELINE(field);
4345 else if (field & USB_BESL_DEEP_VALID)
4346 besl_device = USB_GET_BESL_DEEP(field);
4347 } else {
4348 if (u2del <= 50)
4349 besl_host = 0;
4350 else
4351 besl_host = (u2del - 51) / 75 + 1;
4352 }
4353
4354 besl = besl_host + besl_device;
4355 if (besl > 15)
4356 besl = 15;
4357
4358 return besl;
4359}
4360
4361/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4362static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4363{
4364 u32 field;
4365 int l1;
4366 int besld = 0;
4367 int hirdm = 0;
4368
4369 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4370
4371 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4372 l1 = udev->l1_params.timeout / 256;
4373
4374 /* device has preferred BESLD */
4375 if (field & USB_BESL_DEEP_VALID) {
4376 besld = USB_GET_BESL_DEEP(field);
4377 hirdm = 1;
4378 }
4379
4380 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4381}
4382
4383static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4384 struct usb_device *udev, int enable)
4385{
4386 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4387 struct xhci_port **ports;
4388 __le32 __iomem *pm_addr, *hlpm_addr;
4389 u32 pm_val, hlpm_val, field;
4390 unsigned int port_num;
4391 unsigned long flags;
4392 int hird, exit_latency;
4393 int ret;
4394
4395 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4396 return -EPERM;
4397
4398 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4399 !udev->lpm_capable)
4400 return -EPERM;
4401
4402 if (!udev->parent || udev->parent->parent ||
4403 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4404 return -EPERM;
4405
4406 if (udev->usb2_hw_lpm_capable != 1)
4407 return -EPERM;
4408
4409 spin_lock_irqsave(&xhci->lock, flags);
4410
4411 ports = xhci->usb2_rhub.ports;
4412 port_num = udev->portnum - 1;
4413 pm_addr = ports[port_num]->addr + PORTPMSC;
4414 pm_val = readl(pm_addr);
4415 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4416
4417 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4418 enable ? "enable" : "disable", port_num + 1);
4419
4420 if (enable) {
4421 /* Host supports BESL timeout instead of HIRD */
4422 if (udev->usb2_hw_lpm_besl_capable) {
4423 /* if device doesn't have a preferred BESL value use a
4424 * default one which works with mixed HIRD and BESL
4425 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4426 */
4427 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4428 if ((field & USB_BESL_SUPPORT) &&
4429 (field & USB_BESL_BASELINE_VALID))
4430 hird = USB_GET_BESL_BASELINE(field);
4431 else
4432 hird = udev->l1_params.besl;
4433
4434 exit_latency = xhci_besl_encoding[hird];
4435 spin_unlock_irqrestore(&xhci->lock, flags);
4436
4437 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4438 * input context for link powermanagement evaluate
4439 * context commands. It is protected by hcd->bandwidth
4440 * mutex and is shared by all devices. We need to set
4441 * the max ext latency in USB 2 BESL LPM as well, so
4442 * use the same mutex and xhci_change_max_exit_latency()
4443 */
4444 mutex_lock(hcd->bandwidth_mutex);
4445 ret = xhci_change_max_exit_latency(xhci, udev,
4446 exit_latency);
4447 mutex_unlock(hcd->bandwidth_mutex);
4448
4449 if (ret < 0)
4450 return ret;
4451 spin_lock_irqsave(&xhci->lock, flags);
4452
4453 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4454 writel(hlpm_val, hlpm_addr);
4455 /* flush write */
4456 readl(hlpm_addr);
4457 } else {
4458 hird = xhci_calculate_hird_besl(xhci, udev);
4459 }
4460
4461 pm_val &= ~PORT_HIRD_MASK;
4462 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4463 writel(pm_val, pm_addr);
4464 pm_val = readl(pm_addr);
4465 pm_val |= PORT_HLE;
4466 writel(pm_val, pm_addr);
4467 /* flush write */
4468 readl(pm_addr);
4469 } else {
4470 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4471 writel(pm_val, pm_addr);
4472 /* flush write */
4473 readl(pm_addr);
4474 if (udev->usb2_hw_lpm_besl_capable) {
4475 spin_unlock_irqrestore(&xhci->lock, flags);
4476 mutex_lock(hcd->bandwidth_mutex);
4477 xhci_change_max_exit_latency(xhci, udev, 0);
4478 mutex_unlock(hcd->bandwidth_mutex);
4479 readl_poll_timeout(ports[port_num]->addr, pm_val,
4480 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4481 100, 10000);
4482 return 0;
4483 }
4484 }
4485
4486 spin_unlock_irqrestore(&xhci->lock, flags);
4487 return 0;
4488}
4489
4490/* check if a usb2 port supports a given extened capability protocol
4491 * only USB2 ports extended protocol capability values are cached.
4492 * Return 1 if capability is supported
4493 */
4494static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4495 unsigned capability)
4496{
4497 u32 port_offset, port_count;
4498 int i;
4499
4500 for (i = 0; i < xhci->num_ext_caps; i++) {
4501 if (xhci->ext_caps[i] & capability) {
4502 /* port offsets starts at 1 */
4503 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4504 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4505 if (port >= port_offset &&
4506 port < port_offset + port_count)
4507 return 1;
4508 }
4509 }
4510 return 0;
4511}
4512
4513static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4514{
4515 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4516 int portnum = udev->portnum - 1;
4517
4518 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4519 return 0;
4520
4521 /* we only support lpm for non-hub device connected to root hub yet */
4522 if (!udev->parent || udev->parent->parent ||
4523 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4524 return 0;
4525
4526 if (xhci->hw_lpm_support == 1 &&
4527 xhci_check_usb2_port_capability(
4528 xhci, portnum, XHCI_HLC)) {
4529 udev->usb2_hw_lpm_capable = 1;
4530 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4531 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4532 if (xhci_check_usb2_port_capability(xhci, portnum,
4533 XHCI_BLC))
4534 udev->usb2_hw_lpm_besl_capable = 1;
4535 }
4536
4537 return 0;
4538}
4539
4540/*---------------------- USB 3.0 Link PM functions ------------------------*/
4541
4542/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4543static unsigned long long xhci_service_interval_to_ns(
4544 struct usb_endpoint_descriptor *desc)
4545{
4546 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4547}
4548
4549static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4550 enum usb3_link_state state)
4551{
4552 unsigned long long sel;
4553 unsigned long long pel;
4554 unsigned int max_sel_pel;
4555 char *state_name;
4556
4557 switch (state) {
4558 case USB3_LPM_U1:
4559 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4560 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4561 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4562 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4563 state_name = "U1";
4564 break;
4565 case USB3_LPM_U2:
4566 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4567 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4568 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4569 state_name = "U2";
4570 break;
4571 default:
4572 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4573 __func__);
4574 return USB3_LPM_DISABLED;
4575 }
4576
4577 if (sel <= max_sel_pel && pel <= max_sel_pel)
4578 return USB3_LPM_DEVICE_INITIATED;
4579
4580 if (sel > max_sel_pel)
4581 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4582 "due to long SEL %llu ms\n",
4583 state_name, sel);
4584 else
4585 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4586 "due to long PEL %llu ms\n",
4587 state_name, pel);
4588 return USB3_LPM_DISABLED;
4589}
4590
4591/* The U1 timeout should be the maximum of the following values:
4592 * - For control endpoints, U1 system exit latency (SEL) * 3
4593 * - For bulk endpoints, U1 SEL * 5
4594 * - For interrupt endpoints:
4595 * - Notification EPs, U1 SEL * 3
4596 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4597 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4598 */
4599static unsigned long long xhci_calculate_intel_u1_timeout(
4600 struct usb_device *udev,
4601 struct usb_endpoint_descriptor *desc)
4602{
4603 unsigned long long timeout_ns;
4604 int ep_type;
4605 int intr_type;
4606
4607 ep_type = usb_endpoint_type(desc);
4608 switch (ep_type) {
4609 case USB_ENDPOINT_XFER_CONTROL:
4610 timeout_ns = udev->u1_params.sel * 3;
4611 break;
4612 case USB_ENDPOINT_XFER_BULK:
4613 timeout_ns = udev->u1_params.sel * 5;
4614 break;
4615 case USB_ENDPOINT_XFER_INT:
4616 intr_type = usb_endpoint_interrupt_type(desc);
4617 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4618 timeout_ns = udev->u1_params.sel * 3;
4619 break;
4620 }
4621 /* Otherwise the calculation is the same as isoc eps */
4622 fallthrough;
4623 case USB_ENDPOINT_XFER_ISOC:
4624 timeout_ns = xhci_service_interval_to_ns(desc);
4625 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4626 if (timeout_ns < udev->u1_params.sel * 2)
4627 timeout_ns = udev->u1_params.sel * 2;
4628 break;
4629 default:
4630 return 0;
4631 }
4632
4633 return timeout_ns;
4634}
4635
4636/* Returns the hub-encoded U1 timeout value. */
4637static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4638 struct usb_device *udev,
4639 struct usb_endpoint_descriptor *desc)
4640{
4641 unsigned long long timeout_ns;
4642
4643 /* Prevent U1 if service interval is shorter than U1 exit latency */
4644 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4645 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4646 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4647 return USB3_LPM_DISABLED;
4648 }
4649 }
4650
4651 if (xhci->quirks & XHCI_INTEL_HOST)
4652 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4653 else
4654 timeout_ns = udev->u1_params.sel;
4655
4656 /* The U1 timeout is encoded in 1us intervals.
4657 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4658 */
4659 if (timeout_ns == USB3_LPM_DISABLED)
4660 timeout_ns = 1;
4661 else
4662 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4663
4664 /* If the necessary timeout value is bigger than what we can set in the
4665 * USB 3.0 hub, we have to disable hub-initiated U1.
4666 */
4667 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4668 return timeout_ns;
4669 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4670 "due to long timeout %llu ms\n", timeout_ns);
4671 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4672}
4673
4674/* The U2 timeout should be the maximum of:
4675 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4676 * - largest bInterval of any active periodic endpoint (to avoid going
4677 * into lower power link states between intervals).
4678 * - the U2 Exit Latency of the device
4679 */
4680static unsigned long long xhci_calculate_intel_u2_timeout(
4681 struct usb_device *udev,
4682 struct usb_endpoint_descriptor *desc)
4683{
4684 unsigned long long timeout_ns;
4685 unsigned long long u2_del_ns;
4686
4687 timeout_ns = 10 * 1000 * 1000;
4688
4689 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4690 (xhci_service_interval_to_ns(desc) > timeout_ns))
4691 timeout_ns = xhci_service_interval_to_ns(desc);
4692
4693 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4694 if (u2_del_ns > timeout_ns)
4695 timeout_ns = u2_del_ns;
4696
4697 return timeout_ns;
4698}
4699
4700/* Returns the hub-encoded U2 timeout value. */
4701static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4702 struct usb_device *udev,
4703 struct usb_endpoint_descriptor *desc)
4704{
4705 unsigned long long timeout_ns;
4706
4707 /* Prevent U2 if service interval is shorter than U2 exit latency */
4708 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4709 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4710 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4711 return USB3_LPM_DISABLED;
4712 }
4713 }
4714
4715 if (xhci->quirks & XHCI_INTEL_HOST)
4716 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4717 else
4718 timeout_ns = udev->u2_params.sel;
4719
4720 /* The U2 timeout is encoded in 256us intervals */
4721 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4722 /* If the necessary timeout value is bigger than what we can set in the
4723 * USB 3.0 hub, we have to disable hub-initiated U2.
4724 */
4725 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4726 return timeout_ns;
4727 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4728 "due to long timeout %llu ms\n", timeout_ns);
4729 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4730}
4731
4732static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4733 struct usb_device *udev,
4734 struct usb_endpoint_descriptor *desc,
4735 enum usb3_link_state state,
4736 u16 *timeout)
4737{
4738 if (state == USB3_LPM_U1)
4739 return xhci_calculate_u1_timeout(xhci, udev, desc);
4740 else if (state == USB3_LPM_U2)
4741 return xhci_calculate_u2_timeout(xhci, udev, desc);
4742
4743 return USB3_LPM_DISABLED;
4744}
4745
4746static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4747 struct usb_device *udev,
4748 struct usb_endpoint_descriptor *desc,
4749 enum usb3_link_state state,
4750 u16 *timeout)
4751{
4752 u16 alt_timeout;
4753
4754 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4755 desc, state, timeout);
4756
4757 /* If we found we can't enable hub-initiated LPM, and
4758 * the U1 or U2 exit latency was too high to allow
4759 * device-initiated LPM as well, then we will disable LPM
4760 * for this device, so stop searching any further.
4761 */
4762 if (alt_timeout == USB3_LPM_DISABLED) {
4763 *timeout = alt_timeout;
4764 return -E2BIG;
4765 }
4766 if (alt_timeout > *timeout)
4767 *timeout = alt_timeout;
4768 return 0;
4769}
4770
4771static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4772 struct usb_device *udev,
4773 struct usb_host_interface *alt,
4774 enum usb3_link_state state,
4775 u16 *timeout)
4776{
4777 int j;
4778
4779 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4780 if (xhci_update_timeout_for_endpoint(xhci, udev,
4781 &alt->endpoint[j].desc, state, timeout))
4782 return -E2BIG;
4783 continue;
4784 }
4785 return 0;
4786}
4787
4788static int xhci_check_intel_tier_policy(struct usb_device *udev,
4789 enum usb3_link_state state)
4790{
4791 struct usb_device *parent;
4792 unsigned int num_hubs;
4793
4794 if (state == USB3_LPM_U2)
4795 return 0;
4796
4797 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4798 for (parent = udev->parent, num_hubs = 0; parent->parent;
4799 parent = parent->parent)
4800 num_hubs++;
4801
4802 if (num_hubs < 2)
4803 return 0;
4804
4805 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4806 " below second-tier hub.\n");
4807 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4808 "to decrease power consumption.\n");
4809 return -E2BIG;
4810}
4811
4812static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4813 struct usb_device *udev,
4814 enum usb3_link_state state)
4815{
4816 if (xhci->quirks & XHCI_INTEL_HOST)
4817 return xhci_check_intel_tier_policy(udev, state);
4818 else
4819 return 0;
4820}
4821
4822/* Returns the U1 or U2 timeout that should be enabled.
4823 * If the tier check or timeout setting functions return with a non-zero exit
4824 * code, that means the timeout value has been finalized and we shouldn't look
4825 * at any more endpoints.
4826 */
4827static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4828 struct usb_device *udev, enum usb3_link_state state)
4829{
4830 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4831 struct usb_host_config *config;
4832 char *state_name;
4833 int i;
4834 u16 timeout = USB3_LPM_DISABLED;
4835
4836 if (state == USB3_LPM_U1)
4837 state_name = "U1";
4838 else if (state == USB3_LPM_U2)
4839 state_name = "U2";
4840 else {
4841 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4842 state);
4843 return timeout;
4844 }
4845
4846 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4847 return timeout;
4848
4849 /* Gather some information about the currently installed configuration
4850 * and alternate interface settings.
4851 */
4852 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4853 state, &timeout))
4854 return timeout;
4855
4856 config = udev->actconfig;
4857 if (!config)
4858 return timeout;
4859
4860 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4861 struct usb_driver *driver;
4862 struct usb_interface *intf = config->interface[i];
4863
4864 if (!intf)
4865 continue;
4866
4867 /* Check if any currently bound drivers want hub-initiated LPM
4868 * disabled.
4869 */
4870 if (intf->dev.driver) {
4871 driver = to_usb_driver(intf->dev.driver);
4872 if (driver && driver->disable_hub_initiated_lpm) {
4873 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4874 state_name, driver->name);
4875 timeout = xhci_get_timeout_no_hub_lpm(udev,
4876 state);
4877 if (timeout == USB3_LPM_DISABLED)
4878 return timeout;
4879 }
4880 }
4881
4882 /* Not sure how this could happen... */
4883 if (!intf->cur_altsetting)
4884 continue;
4885
4886 if (xhci_update_timeout_for_interface(xhci, udev,
4887 intf->cur_altsetting,
4888 state, &timeout))
4889 return timeout;
4890 }
4891 return timeout;
4892}
4893
4894static int calculate_max_exit_latency(struct usb_device *udev,
4895 enum usb3_link_state state_changed,
4896 u16 hub_encoded_timeout)
4897{
4898 unsigned long long u1_mel_us = 0;
4899 unsigned long long u2_mel_us = 0;
4900 unsigned long long mel_us = 0;
4901 bool disabling_u1;
4902 bool disabling_u2;
4903 bool enabling_u1;
4904 bool enabling_u2;
4905
4906 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4907 hub_encoded_timeout == USB3_LPM_DISABLED);
4908 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4909 hub_encoded_timeout == USB3_LPM_DISABLED);
4910
4911 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4912 hub_encoded_timeout != USB3_LPM_DISABLED);
4913 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4914 hub_encoded_timeout != USB3_LPM_DISABLED);
4915
4916 /* If U1 was already enabled and we're not disabling it,
4917 * or we're going to enable U1, account for the U1 max exit latency.
4918 */
4919 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4920 enabling_u1)
4921 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4922 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4923 enabling_u2)
4924 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4925
4926 if (u1_mel_us > u2_mel_us)
4927 mel_us = u1_mel_us;
4928 else
4929 mel_us = u2_mel_us;
4930 /* xHCI host controller max exit latency field is only 16 bits wide. */
4931 if (mel_us > MAX_EXIT) {
4932 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4933 "is too big.\n", mel_us);
4934 return -E2BIG;
4935 }
4936 return mel_us;
4937}
4938
4939/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4940static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4941 struct usb_device *udev, enum usb3_link_state state)
4942{
4943 struct xhci_hcd *xhci;
4944 u16 hub_encoded_timeout;
4945 int mel;
4946 int ret;
4947
4948 xhci = hcd_to_xhci(hcd);
4949 /* The LPM timeout values are pretty host-controller specific, so don't
4950 * enable hub-initiated timeouts unless the vendor has provided
4951 * information about their timeout algorithm.
4952 */
4953 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4954 !xhci->devs[udev->slot_id])
4955 return USB3_LPM_DISABLED;
4956
4957 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4958 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4959 if (mel < 0) {
4960 /* Max Exit Latency is too big, disable LPM. */
4961 hub_encoded_timeout = USB3_LPM_DISABLED;
4962 mel = 0;
4963 }
4964
4965 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4966 if (ret)
4967 return ret;
4968 return hub_encoded_timeout;
4969}
4970
4971static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4972 struct usb_device *udev, enum usb3_link_state state)
4973{
4974 struct xhci_hcd *xhci;
4975 u16 mel;
4976
4977 xhci = hcd_to_xhci(hcd);
4978 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4979 !xhci->devs[udev->slot_id])
4980 return 0;
4981
4982 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4983 return xhci_change_max_exit_latency(xhci, udev, mel);
4984}
4985#else /* CONFIG_PM */
4986
4987static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4988 struct usb_device *udev, int enable)
4989{
4990 return 0;
4991}
4992
4993static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4994{
4995 return 0;
4996}
4997
4998static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4999 struct usb_device *udev, enum usb3_link_state state)
5000{
5001 return USB3_LPM_DISABLED;
5002}
5003
5004static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5005 struct usb_device *udev, enum usb3_link_state state)
5006{
5007 return 0;
5008}
5009#endif /* CONFIG_PM */
5010
5011/*-------------------------------------------------------------------------*/
5012
5013/* Once a hub descriptor is fetched for a device, we need to update the xHC's
5014 * internal data structures for the device.
5015 */
5016static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5017 struct usb_tt *tt, gfp_t mem_flags)
5018{
5019 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5020 struct xhci_virt_device *vdev;
5021 struct xhci_command *config_cmd;
5022 struct xhci_input_control_ctx *ctrl_ctx;
5023 struct xhci_slot_ctx *slot_ctx;
5024 unsigned long flags;
5025 unsigned think_time;
5026 int ret;
5027
5028 /* Ignore root hubs */
5029 if (!hdev->parent)
5030 return 0;
5031
5032 vdev = xhci->devs[hdev->slot_id];
5033 if (!vdev) {
5034 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5035 return -EINVAL;
5036 }
5037
5038 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5039 if (!config_cmd)
5040 return -ENOMEM;
5041
5042 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5043 if (!ctrl_ctx) {
5044 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5045 __func__);
5046 xhci_free_command(xhci, config_cmd);
5047 return -ENOMEM;
5048 }
5049
5050 spin_lock_irqsave(&xhci->lock, flags);
5051 if (hdev->speed == USB_SPEED_HIGH &&
5052 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5053 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5054 xhci_free_command(xhci, config_cmd);
5055 spin_unlock_irqrestore(&xhci->lock, flags);
5056 return -ENOMEM;
5057 }
5058
5059 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5060 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5061 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5062 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5063 /*
5064 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5065 * but it may be already set to 1 when setup an xHCI virtual
5066 * device, so clear it anyway.
5067 */
5068 if (tt->multi)
5069 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5070 else if (hdev->speed == USB_SPEED_FULL)
5071 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5072
5073 if (xhci->hci_version > 0x95) {
5074 xhci_dbg(xhci, "xHCI version %x needs hub "
5075 "TT think time and number of ports\n",
5076 (unsigned int) xhci->hci_version);
5077 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5078 /* Set TT think time - convert from ns to FS bit times.
5079 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5080 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5081 *
5082 * xHCI 1.0: this field shall be 0 if the device is not a
5083 * High-spped hub.
5084 */
5085 think_time = tt->think_time;
5086 if (think_time != 0)
5087 think_time = (think_time / 666) - 1;
5088 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5089 slot_ctx->tt_info |=
5090 cpu_to_le32(TT_THINK_TIME(think_time));
5091 } else {
5092 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5093 "TT think time or number of ports\n",
5094 (unsigned int) xhci->hci_version);
5095 }
5096 slot_ctx->dev_state = 0;
5097 spin_unlock_irqrestore(&xhci->lock, flags);
5098
5099 xhci_dbg(xhci, "Set up %s for hub device.\n",
5100 (xhci->hci_version > 0x95) ?
5101 "configure endpoint" : "evaluate context");
5102
5103 /* Issue and wait for the configure endpoint or
5104 * evaluate context command.
5105 */
5106 if (xhci->hci_version > 0x95)
5107 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5108 false, false);
5109 else
5110 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5111 true, false);
5112
5113 xhci_free_command(xhci, config_cmd);
5114 return ret;
5115}
5116
5117static int xhci_get_frame(struct usb_hcd *hcd)
5118{
5119 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5120 /* EHCI mods by the periodic size. Why? */
5121 return readl(&xhci->run_regs->microframe_index) >> 3;
5122}
5123
5124int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5125{
5126 struct xhci_hcd *xhci;
5127 /*
5128 * TODO: Check with DWC3 clients for sysdev according to
5129 * quirks
5130 */
5131 struct device *dev = hcd->self.sysdev;
5132 unsigned int minor_rev;
5133 int retval;
5134
5135 /* Accept arbitrarily long scatter-gather lists */
5136 hcd->self.sg_tablesize = ~0;
5137
5138 /* support to build packet from discontinuous buffers */
5139 hcd->self.no_sg_constraint = 1;
5140
5141 /* XHCI controllers don't stop the ep queue on short packets :| */
5142 hcd->self.no_stop_on_short = 1;
5143
5144 xhci = hcd_to_xhci(hcd);
5145
5146 if (usb_hcd_is_primary_hcd(hcd)) {
5147 xhci->main_hcd = hcd;
5148 xhci->usb2_rhub.hcd = hcd;
5149 /* Mark the first roothub as being USB 2.0.
5150 * The xHCI driver will register the USB 3.0 roothub.
5151 */
5152 hcd->speed = HCD_USB2;
5153 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5154 /*
5155 * USB 2.0 roothub under xHCI has an integrated TT,
5156 * (rate matching hub) as opposed to having an OHCI/UHCI
5157 * companion controller.
5158 */
5159 hcd->has_tt = 1;
5160 } else {
5161 /*
5162 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5163 * should return 0x31 for sbrn, or that the minor revision
5164 * is a two digit BCD containig minor and sub-minor numbers.
5165 * This was later clarified in xHCI 1.2.
5166 *
5167 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5168 * minor revision set to 0x1 instead of 0x10.
5169 */
5170 if (xhci->usb3_rhub.min_rev == 0x1)
5171 minor_rev = 1;
5172 else
5173 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5174
5175 switch (minor_rev) {
5176 case 2:
5177 hcd->speed = HCD_USB32;
5178 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5179 hcd->self.root_hub->rx_lanes = 2;
5180 hcd->self.root_hub->tx_lanes = 2;
5181 break;
5182 case 1:
5183 hcd->speed = HCD_USB31;
5184 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5185 break;
5186 }
5187 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5188 minor_rev,
5189 minor_rev ? "Enhanced " : "");
5190
5191 xhci->usb3_rhub.hcd = hcd;
5192 /* xHCI private pointer was set in xhci_pci_probe for the second
5193 * registered roothub.
5194 */
5195 return 0;
5196 }
5197
5198 mutex_init(&xhci->mutex);
5199 xhci->cap_regs = hcd->regs;
5200 xhci->op_regs = hcd->regs +
5201 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5202 xhci->run_regs = hcd->regs +
5203 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5204 /* Cache read-only capability registers */
5205 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5206 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5207 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5208 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5209 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5210 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5211 if (xhci->hci_version > 0x100)
5212 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5213
5214 xhci->quirks |= quirks;
5215
5216 get_quirks(dev, xhci);
5217
5218 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5219 * success event after a short transfer. This quirk will ignore such
5220 * spurious event.
5221 */
5222 if (xhci->hci_version > 0x96)
5223 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5224
5225 /* Make sure the HC is halted. */
5226 retval = xhci_halt(xhci);
5227 if (retval)
5228 return retval;
5229
5230 xhci_zero_64b_regs(xhci);
5231
5232 xhci_dbg(xhci, "Resetting HCD\n");
5233 /* Reset the internal HC memory state and registers. */
5234 retval = xhci_reset(xhci);
5235 if (retval)
5236 return retval;
5237 xhci_dbg(xhci, "Reset complete\n");
5238
5239 /*
5240 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5241 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5242 * address memory pointers actually. So, this driver clears the AC64
5243 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5244 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5245 */
5246 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5247 xhci->hcc_params &= ~BIT(0);
5248
5249 /* Set dma_mask and coherent_dma_mask to 64-bits,
5250 * if xHC supports 64-bit addressing */
5251 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5252 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5253 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5254 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5255 } else {
5256 /*
5257 * This is to avoid error in cases where a 32-bit USB
5258 * controller is used on a 64-bit capable system.
5259 */
5260 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5261 if (retval)
5262 return retval;
5263 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5264 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5265 }
5266
5267 xhci_dbg(xhci, "Calling HCD init\n");
5268 /* Initialize HCD and host controller data structures. */
5269 retval = xhci_init(hcd);
5270 if (retval)
5271 return retval;
5272 xhci_dbg(xhci, "Called HCD init\n");
5273
5274 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5275 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5276
5277 return 0;
5278}
5279EXPORT_SYMBOL_GPL(xhci_gen_setup);
5280
5281static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5282 struct usb_host_endpoint *ep)
5283{
5284 struct xhci_hcd *xhci;
5285 struct usb_device *udev;
5286 unsigned int slot_id;
5287 unsigned int ep_index;
5288 unsigned long flags;
5289
5290 xhci = hcd_to_xhci(hcd);
5291
5292 spin_lock_irqsave(&xhci->lock, flags);
5293 udev = (struct usb_device *)ep->hcpriv;
5294 slot_id = udev->slot_id;
5295 ep_index = xhci_get_endpoint_index(&ep->desc);
5296
5297 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5298 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5299 spin_unlock_irqrestore(&xhci->lock, flags);
5300}
5301
5302static const struct hc_driver xhci_hc_driver = {
5303 .description = "xhci-hcd",
5304 .product_desc = "xHCI Host Controller",
5305 .hcd_priv_size = sizeof(struct xhci_hcd),
5306
5307 /*
5308 * generic hardware linkage
5309 */
5310 .irq = xhci_irq,
5311 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5312 HCD_BH,
5313
5314 /*
5315 * basic lifecycle operations
5316 */
5317 .reset = NULL, /* set in xhci_init_driver() */
5318 .start = xhci_run,
5319 .stop = xhci_stop,
5320 .shutdown = xhci_shutdown,
5321
5322 /*
5323 * managing i/o requests and associated device resources
5324 */
5325 .map_urb_for_dma = xhci_map_urb_for_dma,
5326 .urb_enqueue = xhci_urb_enqueue,
5327 .urb_dequeue = xhci_urb_dequeue,
5328 .alloc_dev = xhci_alloc_dev,
5329 .free_dev = xhci_free_dev,
5330 .alloc_streams = xhci_alloc_streams,
5331 .free_streams = xhci_free_streams,
5332 .add_endpoint = xhci_add_endpoint,
5333 .drop_endpoint = xhci_drop_endpoint,
5334 .endpoint_disable = xhci_endpoint_disable,
5335 .endpoint_reset = xhci_endpoint_reset,
5336 .check_bandwidth = xhci_check_bandwidth,
5337 .reset_bandwidth = xhci_reset_bandwidth,
5338 .address_device = xhci_address_device,
5339 .enable_device = xhci_enable_device,
5340 .update_hub_device = xhci_update_hub_device,
5341 .reset_device = xhci_discover_or_reset_device,
5342
5343 /*
5344 * scheduling support
5345 */
5346 .get_frame_number = xhci_get_frame,
5347
5348 /*
5349 * root hub support
5350 */
5351 .hub_control = xhci_hub_control,
5352 .hub_status_data = xhci_hub_status_data,
5353 .bus_suspend = xhci_bus_suspend,
5354 .bus_resume = xhci_bus_resume,
5355 .get_resuming_ports = xhci_get_resuming_ports,
5356
5357 /*
5358 * call back when device connected and addressed
5359 */
5360 .update_device = xhci_update_device,
5361 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5362 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5363 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5364 .find_raw_port_number = xhci_find_raw_port_number,
5365 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5366};
5367
5368void xhci_init_driver(struct hc_driver *drv,
5369 const struct xhci_driver_overrides *over)
5370{
5371 BUG_ON(!over);
5372
5373 /* Copy the generic table to drv then apply the overrides */
5374 *drv = xhci_hc_driver;
5375
5376 if (over) {
5377 drv->hcd_priv_size += over->extra_priv_size;
5378 if (over->reset)
5379 drv->reset = over->reset;
5380 if (over->start)
5381 drv->start = over->start;
5382 }
5383}
5384EXPORT_SYMBOL_GPL(xhci_init_driver);
5385
5386MODULE_DESCRIPTION(DRIVER_DESC);
5387MODULE_AUTHOR(DRIVER_AUTHOR);
5388MODULE_LICENSE("GPL");
5389
5390static int __init xhci_hcd_init(void)
5391{
5392 /*
5393 * Check the compiler generated sizes of structures that must be laid
5394 * out in specific ways for hardware access.
5395 */
5396 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5397 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5398 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5399 /* xhci_device_control has eight fields, and also
5400 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5401 */
5402 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5403 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5404 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5405 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5406 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5407 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5408 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5409
5410 if (usb_disabled())
5411 return -ENODEV;
5412
5413 xhci_debugfs_create_root();
5414
5415 return 0;
5416}
5417
5418/*
5419 * If an init function is provided, an exit function must also be provided
5420 * to allow module unload.
5421 */
5422static void __exit xhci_hcd_fini(void)
5423{
5424 xhci_debugfs_remove_root();
5425}
5426
5427module_init(xhci_hcd_init);
5428module_exit(xhci_hcd_fini);