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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/irq.h>
25#include <linux/log2.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/slab.h>
29
30#include "xhci.h"
31
32#define DRIVER_AUTHOR "Sarah Sharp"
33#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
34
35/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
36static int link_quirk;
37module_param(link_quirk, int, S_IRUGO | S_IWUSR);
38MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
39
40/* TODO: copied from ehci-hcd.c - can this be refactored? */
41/*
42 * handshake - spin reading hc until handshake completes or fails
43 * @ptr: address of hc register to be read
44 * @mask: bits to look at in result of read
45 * @done: value of those bits when handshake succeeds
46 * @usec: timeout in microseconds
47 *
48 * Returns negative errno, or zero on success
49 *
50 * Success happens when the "mask" bits have the specified value (hardware
51 * handshake done). There are two failure modes: "usec" have passed (major
52 * hardware flakeout), or the register reads as all-ones (hardware removed).
53 */
54static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
55 u32 mask, u32 done, int usec)
56{
57 u32 result;
58
59 do {
60 result = xhci_readl(xhci, ptr);
61 if (result == ~(u32)0) /* card removed */
62 return -ENODEV;
63 result &= mask;
64 if (result == done)
65 return 0;
66 udelay(1);
67 usec--;
68 } while (usec > 0);
69 return -ETIMEDOUT;
70}
71
72/*
73 * Disable interrupts and begin the xHCI halting process.
74 */
75void xhci_quiesce(struct xhci_hcd *xhci)
76{
77 u32 halted;
78 u32 cmd;
79 u32 mask;
80
81 mask = ~(XHCI_IRQS);
82 halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
83 if (!halted)
84 mask &= ~CMD_RUN;
85
86 cmd = xhci_readl(xhci, &xhci->op_regs->command);
87 cmd &= mask;
88 xhci_writel(xhci, cmd, &xhci->op_regs->command);
89}
90
91/*
92 * Force HC into halt state.
93 *
94 * Disable any IRQs and clear the run/stop bit.
95 * HC will complete any current and actively pipelined transactions, and
96 * should halt within 16 ms of the run/stop bit being cleared.
97 * Read HC Halted bit in the status register to see when the HC is finished.
98 */
99int xhci_halt(struct xhci_hcd *xhci)
100{
101 int ret;
102 xhci_dbg(xhci, "// Halt the HC\n");
103 xhci_quiesce(xhci);
104
105 ret = handshake(xhci, &xhci->op_regs->status,
106 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
107 if (!ret)
108 xhci->xhc_state |= XHCI_STATE_HALTED;
109 return ret;
110}
111
112/*
113 * Set the run bit and wait for the host to be running.
114 */
115static int xhci_start(struct xhci_hcd *xhci)
116{
117 u32 temp;
118 int ret;
119
120 temp = xhci_readl(xhci, &xhci->op_regs->command);
121 temp |= (CMD_RUN);
122 xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
123 temp);
124 xhci_writel(xhci, temp, &xhci->op_regs->command);
125
126 /*
127 * Wait for the HCHalted Status bit to be 0 to indicate the host is
128 * running.
129 */
130 ret = handshake(xhci, &xhci->op_regs->status,
131 STS_HALT, 0, XHCI_MAX_HALT_USEC);
132 if (ret == -ETIMEDOUT)
133 xhci_err(xhci, "Host took too long to start, "
134 "waited %u microseconds.\n",
135 XHCI_MAX_HALT_USEC);
136 if (!ret)
137 xhci->xhc_state &= ~XHCI_STATE_HALTED;
138 return ret;
139}
140
141/*
142 * Reset a halted HC.
143 *
144 * This resets pipelines, timers, counters, state machines, etc.
145 * Transactions will be terminated immediately, and operational registers
146 * will be set to their defaults.
147 */
148int xhci_reset(struct xhci_hcd *xhci)
149{
150 u32 command;
151 u32 state;
152 int ret;
153
154 state = xhci_readl(xhci, &xhci->op_regs->status);
155 if ((state & STS_HALT) == 0) {
156 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
157 return 0;
158 }
159
160 xhci_dbg(xhci, "// Reset the HC\n");
161 command = xhci_readl(xhci, &xhci->op_regs->command);
162 command |= CMD_RESET;
163 xhci_writel(xhci, command, &xhci->op_regs->command);
164
165 ret = handshake(xhci, &xhci->op_regs->command,
166 CMD_RESET, 0, 250 * 1000);
167 if (ret)
168 return ret;
169
170 xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
171 /*
172 * xHCI cannot write to any doorbells or operational registers other
173 * than status until the "Controller Not Ready" flag is cleared.
174 */
175 return handshake(xhci, &xhci->op_regs->status, STS_CNR, 0, 250 * 1000);
176}
177
178/*
179 * Free IRQs
180 * free all IRQs request
181 */
182static void xhci_free_irq(struct xhci_hcd *xhci)
183{
184 int i;
185 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
186
187 /* return if using legacy interrupt */
188 if (xhci_to_hcd(xhci)->irq >= 0)
189 return;
190
191 if (xhci->msix_entries) {
192 for (i = 0; i < xhci->msix_count; i++)
193 if (xhci->msix_entries[i].vector)
194 free_irq(xhci->msix_entries[i].vector,
195 xhci_to_hcd(xhci));
196 } else if (pdev->irq >= 0)
197 free_irq(pdev->irq, xhci_to_hcd(xhci));
198
199 return;
200}
201
202/*
203 * Set up MSI
204 */
205static int xhci_setup_msi(struct xhci_hcd *xhci)
206{
207 int ret;
208 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
209
210 ret = pci_enable_msi(pdev);
211 if (ret) {
212 xhci_err(xhci, "failed to allocate MSI entry\n");
213 return ret;
214 }
215
216 ret = request_irq(pdev->irq, (irq_handler_t)xhci_msi_irq,
217 0, "xhci_hcd", xhci_to_hcd(xhci));
218 if (ret) {
219 xhci_err(xhci, "disable MSI interrupt\n");
220 pci_disable_msi(pdev);
221 }
222
223 return ret;
224}
225
226/*
227 * Set up MSI-X
228 */
229static int xhci_setup_msix(struct xhci_hcd *xhci)
230{
231 int i, ret = 0;
232 struct usb_hcd *hcd = xhci_to_hcd(xhci);
233 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
234
235 /*
236 * calculate number of msi-x vectors supported.
237 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
238 * with max number of interrupters based on the xhci HCSPARAMS1.
239 * - num_online_cpus: maximum msi-x vectors per CPUs core.
240 * Add additional 1 vector to ensure always available interrupt.
241 */
242 xhci->msix_count = min(num_online_cpus() + 1,
243 HCS_MAX_INTRS(xhci->hcs_params1));
244
245 xhci->msix_entries =
246 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
247 GFP_KERNEL);
248 if (!xhci->msix_entries) {
249 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
250 return -ENOMEM;
251 }
252
253 for (i = 0; i < xhci->msix_count; i++) {
254 xhci->msix_entries[i].entry = i;
255 xhci->msix_entries[i].vector = 0;
256 }
257
258 ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
259 if (ret) {
260 xhci_err(xhci, "Failed to enable MSI-X\n");
261 goto free_entries;
262 }
263
264 for (i = 0; i < xhci->msix_count; i++) {
265 ret = request_irq(xhci->msix_entries[i].vector,
266 (irq_handler_t)xhci_msi_irq,
267 0, "xhci_hcd", xhci_to_hcd(xhci));
268 if (ret)
269 goto disable_msix;
270 }
271
272 hcd->msix_enabled = 1;
273 return ret;
274
275disable_msix:
276 xhci_err(xhci, "disable MSI-X interrupt\n");
277 xhci_free_irq(xhci);
278 pci_disable_msix(pdev);
279free_entries:
280 kfree(xhci->msix_entries);
281 xhci->msix_entries = NULL;
282 return ret;
283}
284
285/* Free any IRQs and disable MSI-X */
286static void xhci_cleanup_msix(struct xhci_hcd *xhci)
287{
288 struct usb_hcd *hcd = xhci_to_hcd(xhci);
289 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
290
291 xhci_free_irq(xhci);
292
293 if (xhci->msix_entries) {
294 pci_disable_msix(pdev);
295 kfree(xhci->msix_entries);
296 xhci->msix_entries = NULL;
297 } else {
298 pci_disable_msi(pdev);
299 }
300
301 hcd->msix_enabled = 0;
302 return;
303}
304
305/*
306 * Initialize memory for HCD and xHC (one-time init).
307 *
308 * Program the PAGESIZE register, initialize the device context array, create
309 * device contexts (?), set up a command ring segment (or two?), create event
310 * ring (one for now).
311 */
312int xhci_init(struct usb_hcd *hcd)
313{
314 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
315 int retval = 0;
316
317 xhci_dbg(xhci, "xhci_init\n");
318 spin_lock_init(&xhci->lock);
319 if (link_quirk) {
320 xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
321 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
322 } else {
323 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
324 }
325 retval = xhci_mem_init(xhci, GFP_KERNEL);
326 xhci_dbg(xhci, "Finished xhci_init\n");
327
328 return retval;
329}
330
331/*-------------------------------------------------------------------------*/
332
333
334#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
335static void xhci_event_ring_work(unsigned long arg)
336{
337 unsigned long flags;
338 int temp;
339 u64 temp_64;
340 struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
341 int i, j;
342
343 xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
344
345 spin_lock_irqsave(&xhci->lock, flags);
346 temp = xhci_readl(xhci, &xhci->op_regs->status);
347 xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
348 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
349 (xhci->xhc_state & XHCI_STATE_HALTED)) {
350 xhci_dbg(xhci, "HW died, polling stopped.\n");
351 spin_unlock_irqrestore(&xhci->lock, flags);
352 return;
353 }
354
355 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
356 xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
357 xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
358 xhci->error_bitmask = 0;
359 xhci_dbg(xhci, "Event ring:\n");
360 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
361 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
362 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
363 temp_64 &= ~ERST_PTR_MASK;
364 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
365 xhci_dbg(xhci, "Command ring:\n");
366 xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
367 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
368 xhci_dbg_cmd_ptrs(xhci);
369 for (i = 0; i < MAX_HC_SLOTS; ++i) {
370 if (!xhci->devs[i])
371 continue;
372 for (j = 0; j < 31; ++j) {
373 xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
374 }
375 }
376 spin_unlock_irqrestore(&xhci->lock, flags);
377
378 if (!xhci->zombie)
379 mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
380 else
381 xhci_dbg(xhci, "Quit polling the event ring.\n");
382}
383#endif
384
385static int xhci_run_finished(struct xhci_hcd *xhci)
386{
387 if (xhci_start(xhci)) {
388 xhci_halt(xhci);
389 return -ENODEV;
390 }
391 xhci->shared_hcd->state = HC_STATE_RUNNING;
392
393 if (xhci->quirks & XHCI_NEC_HOST)
394 xhci_ring_cmd_db(xhci);
395
396 xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
397 return 0;
398}
399
400/*
401 * Start the HC after it was halted.
402 *
403 * This function is called by the USB core when the HC driver is added.
404 * Its opposite is xhci_stop().
405 *
406 * xhci_init() must be called once before this function can be called.
407 * Reset the HC, enable device slot contexts, program DCBAAP, and
408 * set command ring pointer and event ring pointer.
409 *
410 * Setup MSI-X vectors and enable interrupts.
411 */
412int xhci_run(struct usb_hcd *hcd)
413{
414 u32 temp;
415 u64 temp_64;
416 u32 ret;
417 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
418 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
419
420 /* Start the xHCI host controller running only after the USB 2.0 roothub
421 * is setup.
422 */
423
424 hcd->uses_new_polling = 1;
425 if (!usb_hcd_is_primary_hcd(hcd))
426 return xhci_run_finished(xhci);
427
428 xhci_dbg(xhci, "xhci_run\n");
429 /* unregister the legacy interrupt */
430 if (hcd->irq)
431 free_irq(hcd->irq, hcd);
432 hcd->irq = -1;
433
434 /* Some Fresco Logic host controllers advertise MSI, but fail to
435 * generate interrupts. Don't even try to enable MSI.
436 */
437 if (xhci->quirks & XHCI_BROKEN_MSI)
438 goto legacy_irq;
439
440 ret = xhci_setup_msix(xhci);
441 if (ret)
442 /* fall back to msi*/
443 ret = xhci_setup_msi(xhci);
444
445 if (ret) {
446legacy_irq:
447 /* fall back to legacy interrupt*/
448 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
449 hcd->irq_descr, hcd);
450 if (ret) {
451 xhci_err(xhci, "request interrupt %d failed\n",
452 pdev->irq);
453 return ret;
454 }
455 hcd->irq = pdev->irq;
456 }
457
458#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
459 init_timer(&xhci->event_ring_timer);
460 xhci->event_ring_timer.data = (unsigned long) xhci;
461 xhci->event_ring_timer.function = xhci_event_ring_work;
462 /* Poll the event ring */
463 xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
464 xhci->zombie = 0;
465 xhci_dbg(xhci, "Setting event ring polling timer\n");
466 add_timer(&xhci->event_ring_timer);
467#endif
468
469 xhci_dbg(xhci, "Command ring memory map follows:\n");
470 xhci_debug_ring(xhci, xhci->cmd_ring);
471 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
472 xhci_dbg_cmd_ptrs(xhci);
473
474 xhci_dbg(xhci, "ERST memory map follows:\n");
475 xhci_dbg_erst(xhci, &xhci->erst);
476 xhci_dbg(xhci, "Event ring:\n");
477 xhci_debug_ring(xhci, xhci->event_ring);
478 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
479 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
480 temp_64 &= ~ERST_PTR_MASK;
481 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
482
483 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
484 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
485 temp &= ~ER_IRQ_INTERVAL_MASK;
486 temp |= (u32) 160;
487 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
488
489 /* Set the HCD state before we enable the irqs */
490 temp = xhci_readl(xhci, &xhci->op_regs->command);
491 temp |= (CMD_EIE);
492 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
493 temp);
494 xhci_writel(xhci, temp, &xhci->op_regs->command);
495
496 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
497 xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
498 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
499 xhci_writel(xhci, ER_IRQ_ENABLE(temp),
500 &xhci->ir_set->irq_pending);
501 xhci_print_ir_set(xhci, 0);
502
503 if (xhci->quirks & XHCI_NEC_HOST)
504 xhci_queue_vendor_command(xhci, 0, 0, 0,
505 TRB_TYPE(TRB_NEC_GET_FW));
506
507 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
508 return 0;
509}
510
511static void xhci_only_stop_hcd(struct usb_hcd *hcd)
512{
513 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
514
515 spin_lock_irq(&xhci->lock);
516 xhci_halt(xhci);
517
518 /* The shared_hcd is going to be deallocated shortly (the USB core only
519 * calls this function when allocation fails in usb_add_hcd(), or
520 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
521 */
522 xhci->shared_hcd = NULL;
523 spin_unlock_irq(&xhci->lock);
524}
525
526/*
527 * Stop xHCI driver.
528 *
529 * This function is called by the USB core when the HC driver is removed.
530 * Its opposite is xhci_run().
531 *
532 * Disable device contexts, disable IRQs, and quiesce the HC.
533 * Reset the HC, finish any completed transactions, and cleanup memory.
534 */
535void xhci_stop(struct usb_hcd *hcd)
536{
537 u32 temp;
538 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
539
540 if (!usb_hcd_is_primary_hcd(hcd)) {
541 xhci_only_stop_hcd(xhci->shared_hcd);
542 return;
543 }
544
545 spin_lock_irq(&xhci->lock);
546 /* Make sure the xHC is halted for a USB3 roothub
547 * (xhci_stop() could be called as part of failed init).
548 */
549 xhci_halt(xhci);
550 xhci_reset(xhci);
551 spin_unlock_irq(&xhci->lock);
552
553 xhci_cleanup_msix(xhci);
554
555#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
556 /* Tell the event ring poll function not to reschedule */
557 xhci->zombie = 1;
558 del_timer_sync(&xhci->event_ring_timer);
559#endif
560
561 if (xhci->quirks & XHCI_AMD_PLL_FIX)
562 usb_amd_dev_put();
563
564 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
565 temp = xhci_readl(xhci, &xhci->op_regs->status);
566 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
567 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
568 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
569 &xhci->ir_set->irq_pending);
570 xhci_print_ir_set(xhci, 0);
571
572 xhci_dbg(xhci, "cleaning up memory\n");
573 xhci_mem_cleanup(xhci);
574 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
575 xhci_readl(xhci, &xhci->op_regs->status));
576}
577
578/*
579 * Shutdown HC (not bus-specific)
580 *
581 * This is called when the machine is rebooting or halting. We assume that the
582 * machine will be powered off, and the HC's internal state will be reset.
583 * Don't bother to free memory.
584 *
585 * This will only ever be called with the main usb_hcd (the USB3 roothub).
586 */
587void xhci_shutdown(struct usb_hcd *hcd)
588{
589 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
590
591 spin_lock_irq(&xhci->lock);
592 xhci_halt(xhci);
593 spin_unlock_irq(&xhci->lock);
594
595 xhci_cleanup_msix(xhci);
596
597 xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
598 xhci_readl(xhci, &xhci->op_regs->status));
599}
600
601#ifdef CONFIG_PM
602static void xhci_save_registers(struct xhci_hcd *xhci)
603{
604 xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
605 xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
606 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
607 xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
608 xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
609 xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
610 xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
611 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
612 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
613}
614
615static void xhci_restore_registers(struct xhci_hcd *xhci)
616{
617 xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
618 xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
619 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
620 xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
621 xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
622 xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
623 xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
624 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
625}
626
627static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
628{
629 u64 val_64;
630
631 /* step 2: initialize command ring buffer */
632 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
633 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
634 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
635 xhci->cmd_ring->dequeue) &
636 (u64) ~CMD_RING_RSVD_BITS) |
637 xhci->cmd_ring->cycle_state;
638 xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
639 (long unsigned long) val_64);
640 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
641}
642
643/*
644 * The whole command ring must be cleared to zero when we suspend the host.
645 *
646 * The host doesn't save the command ring pointer in the suspend well, so we
647 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
648 * aligned, because of the reserved bits in the command ring dequeue pointer
649 * register. Therefore, we can't just set the dequeue pointer back in the
650 * middle of the ring (TRBs are 16-byte aligned).
651 */
652static void xhci_clear_command_ring(struct xhci_hcd *xhci)
653{
654 struct xhci_ring *ring;
655 struct xhci_segment *seg;
656
657 ring = xhci->cmd_ring;
658 seg = ring->deq_seg;
659 do {
660 memset(seg->trbs, 0, SEGMENT_SIZE);
661 seg = seg->next;
662 } while (seg != ring->deq_seg);
663
664 /* Reset the software enqueue and dequeue pointers */
665 ring->deq_seg = ring->first_seg;
666 ring->dequeue = ring->first_seg->trbs;
667 ring->enq_seg = ring->deq_seg;
668 ring->enqueue = ring->dequeue;
669
670 /*
671 * Ring is now zeroed, so the HW should look for change of ownership
672 * when the cycle bit is set to 1.
673 */
674 ring->cycle_state = 1;
675
676 /*
677 * Reset the hardware dequeue pointer.
678 * Yes, this will need to be re-written after resume, but we're paranoid
679 * and want to make sure the hardware doesn't access bogus memory
680 * because, say, the BIOS or an SMI started the host without changing
681 * the command ring pointers.
682 */
683 xhci_set_cmd_ring_deq(xhci);
684}
685
686/*
687 * Stop HC (not bus-specific)
688 *
689 * This is called when the machine transition into S3/S4 mode.
690 *
691 */
692int xhci_suspend(struct xhci_hcd *xhci)
693{
694 int rc = 0;
695 struct usb_hcd *hcd = xhci_to_hcd(xhci);
696 u32 command;
697 int i;
698
699 spin_lock_irq(&xhci->lock);
700 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
701 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
702 /* step 1: stop endpoint */
703 /* skipped assuming that port suspend has done */
704
705 /* step 2: clear Run/Stop bit */
706 command = xhci_readl(xhci, &xhci->op_regs->command);
707 command &= ~CMD_RUN;
708 xhci_writel(xhci, command, &xhci->op_regs->command);
709 if (handshake(xhci, &xhci->op_regs->status,
710 STS_HALT, STS_HALT, 100*100)) {
711 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
712 spin_unlock_irq(&xhci->lock);
713 return -ETIMEDOUT;
714 }
715 xhci_clear_command_ring(xhci);
716
717 /* step 3: save registers */
718 xhci_save_registers(xhci);
719
720 /* step 4: set CSS flag */
721 command = xhci_readl(xhci, &xhci->op_regs->command);
722 command |= CMD_CSS;
723 xhci_writel(xhci, command, &xhci->op_regs->command);
724 if (handshake(xhci, &xhci->op_regs->status, STS_SAVE, 0, 10*100)) {
725 xhci_warn(xhci, "WARN: xHC CMD_CSS timeout\n");
726 spin_unlock_irq(&xhci->lock);
727 return -ETIMEDOUT;
728 }
729 spin_unlock_irq(&xhci->lock);
730
731 /* step 5: remove core well power */
732 /* synchronize irq when using MSI-X */
733 if (xhci->msix_entries) {
734 for (i = 0; i < xhci->msix_count; i++)
735 synchronize_irq(xhci->msix_entries[i].vector);
736 }
737
738 return rc;
739}
740
741/*
742 * start xHC (not bus-specific)
743 *
744 * This is called when the machine transition from S3/S4 mode.
745 *
746 */
747int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
748{
749 u32 command, temp = 0;
750 struct usb_hcd *hcd = xhci_to_hcd(xhci);
751 struct usb_hcd *secondary_hcd;
752 int retval;
753
754 /* Wait a bit if either of the roothubs need to settle from the
755 * transition into bus suspend.
756 */
757 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
758 time_before(jiffies,
759 xhci->bus_state[1].next_statechange))
760 msleep(100);
761
762 spin_lock_irq(&xhci->lock);
763 if (xhci->quirks & XHCI_RESET_ON_RESUME)
764 hibernated = true;
765
766 if (!hibernated) {
767 /* step 1: restore register */
768 xhci_restore_registers(xhci);
769 /* step 2: initialize command ring buffer */
770 xhci_set_cmd_ring_deq(xhci);
771 /* step 3: restore state and start state*/
772 /* step 3: set CRS flag */
773 command = xhci_readl(xhci, &xhci->op_regs->command);
774 command |= CMD_CRS;
775 xhci_writel(xhci, command, &xhci->op_regs->command);
776 if (handshake(xhci, &xhci->op_regs->status,
777 STS_RESTORE, 0, 10*100)) {
778 xhci_dbg(xhci, "WARN: xHC CMD_CSS timeout\n");
779 spin_unlock_irq(&xhci->lock);
780 return -ETIMEDOUT;
781 }
782 temp = xhci_readl(xhci, &xhci->op_regs->status);
783 }
784
785 /* If restore operation fails, re-initialize the HC during resume */
786 if ((temp & STS_SRE) || hibernated) {
787 /* Let the USB core know _both_ roothubs lost power. */
788 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
789 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
790
791 xhci_dbg(xhci, "Stop HCD\n");
792 xhci_halt(xhci);
793 xhci_reset(xhci);
794 spin_unlock_irq(&xhci->lock);
795 xhci_cleanup_msix(xhci);
796
797#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
798 /* Tell the event ring poll function not to reschedule */
799 xhci->zombie = 1;
800 del_timer_sync(&xhci->event_ring_timer);
801#endif
802
803 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
804 temp = xhci_readl(xhci, &xhci->op_regs->status);
805 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
806 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
807 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
808 &xhci->ir_set->irq_pending);
809 xhci_print_ir_set(xhci, 0);
810
811 xhci_dbg(xhci, "cleaning up memory\n");
812 xhci_mem_cleanup(xhci);
813 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
814 xhci_readl(xhci, &xhci->op_regs->status));
815
816 /* USB core calls the PCI reinit and start functions twice:
817 * first with the primary HCD, and then with the secondary HCD.
818 * If we don't do the same, the host will never be started.
819 */
820 if (!usb_hcd_is_primary_hcd(hcd))
821 secondary_hcd = hcd;
822 else
823 secondary_hcd = xhci->shared_hcd;
824
825 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
826 retval = xhci_init(hcd->primary_hcd);
827 if (retval)
828 return retval;
829 xhci_dbg(xhci, "Start the primary HCD\n");
830 retval = xhci_run(hcd->primary_hcd);
831 if (retval)
832 goto failed_restart;
833
834 xhci_dbg(xhci, "Start the secondary HCD\n");
835 retval = xhci_run(secondary_hcd);
836 if (!retval) {
837 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
838 set_bit(HCD_FLAG_HW_ACCESSIBLE,
839 &xhci->shared_hcd->flags);
840 }
841failed_restart:
842 hcd->state = HC_STATE_SUSPENDED;
843 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
844 return retval;
845 }
846
847 /* step 4: set Run/Stop bit */
848 command = xhci_readl(xhci, &xhci->op_regs->command);
849 command |= CMD_RUN;
850 xhci_writel(xhci, command, &xhci->op_regs->command);
851 handshake(xhci, &xhci->op_regs->status, STS_HALT,
852 0, 250 * 1000);
853
854 /* step 5: walk topology and initialize portsc,
855 * portpmsc and portli
856 */
857 /* this is done in bus_resume */
858
859 /* step 6: restart each of the previously
860 * Running endpoints by ringing their doorbells
861 */
862
863 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
864 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
865
866 spin_unlock_irq(&xhci->lock);
867 return 0;
868}
869#endif /* CONFIG_PM */
870
871/*-------------------------------------------------------------------------*/
872
873/**
874 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
875 * HCDs. Find the index for an endpoint given its descriptor. Use the return
876 * value to right shift 1 for the bitmask.
877 *
878 * Index = (epnum * 2) + direction - 1,
879 * where direction = 0 for OUT, 1 for IN.
880 * For control endpoints, the IN index is used (OUT index is unused), so
881 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
882 */
883unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
884{
885 unsigned int index;
886 if (usb_endpoint_xfer_control(desc))
887 index = (unsigned int) (usb_endpoint_num(desc)*2);
888 else
889 index = (unsigned int) (usb_endpoint_num(desc)*2) +
890 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
891 return index;
892}
893
894/* Find the flag for this endpoint (for use in the control context). Use the
895 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
896 * bit 1, etc.
897 */
898unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
899{
900 return 1 << (xhci_get_endpoint_index(desc) + 1);
901}
902
903/* Find the flag for this endpoint (for use in the control context). Use the
904 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
905 * bit 1, etc.
906 */
907unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
908{
909 return 1 << (ep_index + 1);
910}
911
912/* Compute the last valid endpoint context index. Basically, this is the
913 * endpoint index plus one. For slot contexts with more than valid endpoint,
914 * we find the most significant bit set in the added contexts flags.
915 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
916 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
917 */
918unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
919{
920 return fls(added_ctxs) - 1;
921}
922
923/* Returns 1 if the arguments are OK;
924 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
925 */
926static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
927 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
928 const char *func) {
929 struct xhci_hcd *xhci;
930 struct xhci_virt_device *virt_dev;
931
932 if (!hcd || (check_ep && !ep) || !udev) {
933 printk(KERN_DEBUG "xHCI %s called with invalid args\n",
934 func);
935 return -EINVAL;
936 }
937 if (!udev->parent) {
938 printk(KERN_DEBUG "xHCI %s called for root hub\n",
939 func);
940 return 0;
941 }
942
943 xhci = hcd_to_xhci(hcd);
944 if (xhci->xhc_state & XHCI_STATE_HALTED)
945 return -ENODEV;
946
947 if (check_virt_dev) {
948 if (!udev->slot_id || !xhci->devs
949 || !xhci->devs[udev->slot_id]) {
950 printk(KERN_DEBUG "xHCI %s called with unaddressed "
951 "device\n", func);
952 return -EINVAL;
953 }
954
955 virt_dev = xhci->devs[udev->slot_id];
956 if (virt_dev->udev != udev) {
957 printk(KERN_DEBUG "xHCI %s called with udev and "
958 "virt_dev does not match\n", func);
959 return -EINVAL;
960 }
961 }
962
963 return 1;
964}
965
966static int xhci_configure_endpoint(struct xhci_hcd *xhci,
967 struct usb_device *udev, struct xhci_command *command,
968 bool ctx_change, bool must_succeed);
969
970/*
971 * Full speed devices may have a max packet size greater than 8 bytes, but the
972 * USB core doesn't know that until it reads the first 8 bytes of the
973 * descriptor. If the usb_device's max packet size changes after that point,
974 * we need to issue an evaluate context command and wait on it.
975 */
976static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
977 unsigned int ep_index, struct urb *urb)
978{
979 struct xhci_container_ctx *in_ctx;
980 struct xhci_container_ctx *out_ctx;
981 struct xhci_input_control_ctx *ctrl_ctx;
982 struct xhci_ep_ctx *ep_ctx;
983 int max_packet_size;
984 int hw_max_packet_size;
985 int ret = 0;
986
987 out_ctx = xhci->devs[slot_id]->out_ctx;
988 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
989 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
990 max_packet_size = le16_to_cpu(urb->dev->ep0.desc.wMaxPacketSize);
991 if (hw_max_packet_size != max_packet_size) {
992 xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
993 xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
994 max_packet_size);
995 xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
996 hw_max_packet_size);
997 xhci_dbg(xhci, "Issuing evaluate context command.\n");
998
999 /* Set up the modified control endpoint 0 */
1000 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1001 xhci->devs[slot_id]->out_ctx, ep_index);
1002 in_ctx = xhci->devs[slot_id]->in_ctx;
1003 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1004 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1005 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1006
1007 /* Set up the input context flags for the command */
1008 /* FIXME: This won't work if a non-default control endpoint
1009 * changes max packet sizes.
1010 */
1011 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1012 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1013 ctrl_ctx->drop_flags = 0;
1014
1015 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1016 xhci_dbg_ctx(xhci, in_ctx, ep_index);
1017 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1018 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1019
1020 ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
1021 true, false);
1022
1023 /* Clean up the input context for later use by bandwidth
1024 * functions.
1025 */
1026 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1027 }
1028 return ret;
1029}
1030
1031/*
1032 * non-error returns are a promise to giveback() the urb later
1033 * we drop ownership so next owner (or urb unlink) can get it
1034 */
1035int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1036{
1037 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1038 unsigned long flags;
1039 int ret = 0;
1040 unsigned int slot_id, ep_index;
1041 struct urb_priv *urb_priv;
1042 int size, i;
1043
1044 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1045 true, true, __func__) <= 0)
1046 return -EINVAL;
1047
1048 slot_id = urb->dev->slot_id;
1049 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1050
1051 if (!HCD_HW_ACCESSIBLE(hcd)) {
1052 if (!in_interrupt())
1053 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1054 ret = -ESHUTDOWN;
1055 goto exit;
1056 }
1057
1058 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1059 size = urb->number_of_packets;
1060 else
1061 size = 1;
1062
1063 urb_priv = kzalloc(sizeof(struct urb_priv) +
1064 size * sizeof(struct xhci_td *), mem_flags);
1065 if (!urb_priv)
1066 return -ENOMEM;
1067
1068 for (i = 0; i < size; i++) {
1069 urb_priv->td[i] = kzalloc(sizeof(struct xhci_td), mem_flags);
1070 if (!urb_priv->td[i]) {
1071 urb_priv->length = i;
1072 xhci_urb_free_priv(xhci, urb_priv);
1073 return -ENOMEM;
1074 }
1075 }
1076
1077 urb_priv->length = size;
1078 urb_priv->td_cnt = 0;
1079 urb->hcpriv = urb_priv;
1080
1081 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1082 /* Check to see if the max packet size for the default control
1083 * endpoint changed during FS device enumeration
1084 */
1085 if (urb->dev->speed == USB_SPEED_FULL) {
1086 ret = xhci_check_maxpacket(xhci, slot_id,
1087 ep_index, urb);
1088 if (ret < 0) {
1089 xhci_urb_free_priv(xhci, urb_priv);
1090 urb->hcpriv = NULL;
1091 return ret;
1092 }
1093 }
1094
1095 /* We have a spinlock and interrupts disabled, so we must pass
1096 * atomic context to this function, which may allocate memory.
1097 */
1098 spin_lock_irqsave(&xhci->lock, flags);
1099 if (xhci->xhc_state & XHCI_STATE_DYING)
1100 goto dying;
1101 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1102 slot_id, ep_index);
1103 if (ret)
1104 goto free_priv;
1105 spin_unlock_irqrestore(&xhci->lock, flags);
1106 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1107 spin_lock_irqsave(&xhci->lock, flags);
1108 if (xhci->xhc_state & XHCI_STATE_DYING)
1109 goto dying;
1110 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1111 EP_GETTING_STREAMS) {
1112 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1113 "is transitioning to using streams.\n");
1114 ret = -EINVAL;
1115 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1116 EP_GETTING_NO_STREAMS) {
1117 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1118 "is transitioning to "
1119 "not having streams.\n");
1120 ret = -EINVAL;
1121 } else {
1122 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1123 slot_id, ep_index);
1124 }
1125 if (ret)
1126 goto free_priv;
1127 spin_unlock_irqrestore(&xhci->lock, flags);
1128 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1129 spin_lock_irqsave(&xhci->lock, flags);
1130 if (xhci->xhc_state & XHCI_STATE_DYING)
1131 goto dying;
1132 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1133 slot_id, ep_index);
1134 if (ret)
1135 goto free_priv;
1136 spin_unlock_irqrestore(&xhci->lock, flags);
1137 } else {
1138 spin_lock_irqsave(&xhci->lock, flags);
1139 if (xhci->xhc_state & XHCI_STATE_DYING)
1140 goto dying;
1141 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1142 slot_id, ep_index);
1143 if (ret)
1144 goto free_priv;
1145 spin_unlock_irqrestore(&xhci->lock, flags);
1146 }
1147exit:
1148 return ret;
1149dying:
1150 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1151 "non-responsive xHCI host.\n",
1152 urb->ep->desc.bEndpointAddress, urb);
1153 ret = -ESHUTDOWN;
1154free_priv:
1155 xhci_urb_free_priv(xhci, urb_priv);
1156 urb->hcpriv = NULL;
1157 spin_unlock_irqrestore(&xhci->lock, flags);
1158 return ret;
1159}
1160
1161/* Get the right ring for the given URB.
1162 * If the endpoint supports streams, boundary check the URB's stream ID.
1163 * If the endpoint doesn't support streams, return the singular endpoint ring.
1164 */
1165static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1166 struct urb *urb)
1167{
1168 unsigned int slot_id;
1169 unsigned int ep_index;
1170 unsigned int stream_id;
1171 struct xhci_virt_ep *ep;
1172
1173 slot_id = urb->dev->slot_id;
1174 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1175 stream_id = urb->stream_id;
1176 ep = &xhci->devs[slot_id]->eps[ep_index];
1177 /* Common case: no streams */
1178 if (!(ep->ep_state & EP_HAS_STREAMS))
1179 return ep->ring;
1180
1181 if (stream_id == 0) {
1182 xhci_warn(xhci,
1183 "WARN: Slot ID %u, ep index %u has streams, "
1184 "but URB has no stream ID.\n",
1185 slot_id, ep_index);
1186 return NULL;
1187 }
1188
1189 if (stream_id < ep->stream_info->num_streams)
1190 return ep->stream_info->stream_rings[stream_id];
1191
1192 xhci_warn(xhci,
1193 "WARN: Slot ID %u, ep index %u has "
1194 "stream IDs 1 to %u allocated, "
1195 "but stream ID %u is requested.\n",
1196 slot_id, ep_index,
1197 ep->stream_info->num_streams - 1,
1198 stream_id);
1199 return NULL;
1200}
1201
1202/*
1203 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1204 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1205 * should pick up where it left off in the TD, unless a Set Transfer Ring
1206 * Dequeue Pointer is issued.
1207 *
1208 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1209 * the ring. Since the ring is a contiguous structure, they can't be physically
1210 * removed. Instead, there are two options:
1211 *
1212 * 1) If the HC is in the middle of processing the URB to be canceled, we
1213 * simply move the ring's dequeue pointer past those TRBs using the Set
1214 * Transfer Ring Dequeue Pointer command. This will be the common case,
1215 * when drivers timeout on the last submitted URB and attempt to cancel.
1216 *
1217 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1218 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1219 * HC will need to invalidate the any TRBs it has cached after the stop
1220 * endpoint command, as noted in the xHCI 0.95 errata.
1221 *
1222 * 3) The TD may have completed by the time the Stop Endpoint Command
1223 * completes, so software needs to handle that case too.
1224 *
1225 * This function should protect against the TD enqueueing code ringing the
1226 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1227 * It also needs to account for multiple cancellations on happening at the same
1228 * time for the same endpoint.
1229 *
1230 * Note that this function can be called in any context, or so says
1231 * usb_hcd_unlink_urb()
1232 */
1233int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1234{
1235 unsigned long flags;
1236 int ret, i;
1237 u32 temp;
1238 struct xhci_hcd *xhci;
1239 struct urb_priv *urb_priv;
1240 struct xhci_td *td;
1241 unsigned int ep_index;
1242 struct xhci_ring *ep_ring;
1243 struct xhci_virt_ep *ep;
1244
1245 xhci = hcd_to_xhci(hcd);
1246 spin_lock_irqsave(&xhci->lock, flags);
1247 /* Make sure the URB hasn't completed or been unlinked already */
1248 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1249 if (ret || !urb->hcpriv)
1250 goto done;
1251 temp = xhci_readl(xhci, &xhci->op_regs->status);
1252 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1253 xhci_dbg(xhci, "HW died, freeing TD.\n");
1254 urb_priv = urb->hcpriv;
1255 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1256 td = urb_priv->td[i];
1257 if (!list_empty(&td->td_list))
1258 list_del_init(&td->td_list);
1259 if (!list_empty(&td->cancelled_td_list))
1260 list_del_init(&td->cancelled_td_list);
1261 }
1262
1263 usb_hcd_unlink_urb_from_ep(hcd, urb);
1264 spin_unlock_irqrestore(&xhci->lock, flags);
1265 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1266 xhci_urb_free_priv(xhci, urb_priv);
1267 return ret;
1268 }
1269 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1270 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1271 xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
1272 "non-responsive xHCI host.\n",
1273 urb->ep->desc.bEndpointAddress, urb);
1274 /* Let the stop endpoint command watchdog timer (which set this
1275 * state) finish cleaning up the endpoint TD lists. We must
1276 * have caught it in the middle of dropping a lock and giving
1277 * back an URB.
1278 */
1279 goto done;
1280 }
1281
1282 xhci_dbg(xhci, "Cancel URB %p\n", urb);
1283 xhci_dbg(xhci, "Event ring:\n");
1284 xhci_debug_ring(xhci, xhci->event_ring);
1285 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1286 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1287 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1288 if (!ep_ring) {
1289 ret = -EINVAL;
1290 goto done;
1291 }
1292
1293 xhci_dbg(xhci, "Endpoint ring:\n");
1294 xhci_debug_ring(xhci, ep_ring);
1295
1296 urb_priv = urb->hcpriv;
1297
1298 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1299 td = urb_priv->td[i];
1300 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1301 }
1302
1303 /* Queue a stop endpoint command, but only if this is
1304 * the first cancellation to be handled.
1305 */
1306 if (!(ep->ep_state & EP_HALT_PENDING)) {
1307 ep->ep_state |= EP_HALT_PENDING;
1308 ep->stop_cmds_pending++;
1309 ep->stop_cmd_timer.expires = jiffies +
1310 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1311 add_timer(&ep->stop_cmd_timer);
1312 xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
1313 xhci_ring_cmd_db(xhci);
1314 }
1315done:
1316 spin_unlock_irqrestore(&xhci->lock, flags);
1317 return ret;
1318}
1319
1320/* Drop an endpoint from a new bandwidth configuration for this device.
1321 * Only one call to this function is allowed per endpoint before
1322 * check_bandwidth() or reset_bandwidth() must be called.
1323 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1324 * add the endpoint to the schedule with possibly new parameters denoted by a
1325 * different endpoint descriptor in usb_host_endpoint.
1326 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1327 * not allowed.
1328 *
1329 * The USB core will not allow URBs to be queued to an endpoint that is being
1330 * disabled, so there's no need for mutual exclusion to protect
1331 * the xhci->devs[slot_id] structure.
1332 */
1333int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1334 struct usb_host_endpoint *ep)
1335{
1336 struct xhci_hcd *xhci;
1337 struct xhci_container_ctx *in_ctx, *out_ctx;
1338 struct xhci_input_control_ctx *ctrl_ctx;
1339 struct xhci_slot_ctx *slot_ctx;
1340 unsigned int last_ctx;
1341 unsigned int ep_index;
1342 struct xhci_ep_ctx *ep_ctx;
1343 u32 drop_flag;
1344 u32 new_add_flags, new_drop_flags, new_slot_info;
1345 int ret;
1346
1347 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1348 if (ret <= 0)
1349 return ret;
1350 xhci = hcd_to_xhci(hcd);
1351 if (xhci->xhc_state & XHCI_STATE_DYING)
1352 return -ENODEV;
1353
1354 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1355 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1356 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1357 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1358 __func__, drop_flag);
1359 return 0;
1360 }
1361
1362 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1363 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1364 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1365 ep_index = xhci_get_endpoint_index(&ep->desc);
1366 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1367 /* If the HC already knows the endpoint is disabled,
1368 * or the HCD has noted it is disabled, ignore this request
1369 */
1370 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1371 cpu_to_le32(EP_STATE_DISABLED)) ||
1372 le32_to_cpu(ctrl_ctx->drop_flags) &
1373 xhci_get_endpoint_flag(&ep->desc)) {
1374 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1375 __func__, ep);
1376 return 0;
1377 }
1378
1379 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1380 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1381
1382 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1383 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1384
1385 last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
1386 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1387 /* Update the last valid endpoint context, if we deleted the last one */
1388 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
1389 LAST_CTX(last_ctx)) {
1390 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1391 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1392 }
1393 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1394
1395 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1396
1397 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1398 (unsigned int) ep->desc.bEndpointAddress,
1399 udev->slot_id,
1400 (unsigned int) new_drop_flags,
1401 (unsigned int) new_add_flags,
1402 (unsigned int) new_slot_info);
1403 return 0;
1404}
1405
1406/* Add an endpoint to a new possible bandwidth configuration for this device.
1407 * Only one call to this function is allowed per endpoint before
1408 * check_bandwidth() or reset_bandwidth() must be called.
1409 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1410 * add the endpoint to the schedule with possibly new parameters denoted by a
1411 * different endpoint descriptor in usb_host_endpoint.
1412 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1413 * not allowed.
1414 *
1415 * The USB core will not allow URBs to be queued to an endpoint until the
1416 * configuration or alt setting is installed in the device, so there's no need
1417 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1418 */
1419int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1420 struct usb_host_endpoint *ep)
1421{
1422 struct xhci_hcd *xhci;
1423 struct xhci_container_ctx *in_ctx, *out_ctx;
1424 unsigned int ep_index;
1425 struct xhci_ep_ctx *ep_ctx;
1426 struct xhci_slot_ctx *slot_ctx;
1427 struct xhci_input_control_ctx *ctrl_ctx;
1428 u32 added_ctxs;
1429 unsigned int last_ctx;
1430 u32 new_add_flags, new_drop_flags, new_slot_info;
1431 struct xhci_virt_device *virt_dev;
1432 int ret = 0;
1433
1434 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1435 if (ret <= 0) {
1436 /* So we won't queue a reset ep command for a root hub */
1437 ep->hcpriv = NULL;
1438 return ret;
1439 }
1440 xhci = hcd_to_xhci(hcd);
1441 if (xhci->xhc_state & XHCI_STATE_DYING)
1442 return -ENODEV;
1443
1444 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1445 last_ctx = xhci_last_valid_endpoint(added_ctxs);
1446 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1447 /* FIXME when we have to issue an evaluate endpoint command to
1448 * deal with ep0 max packet size changing once we get the
1449 * descriptors
1450 */
1451 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1452 __func__, added_ctxs);
1453 return 0;
1454 }
1455
1456 virt_dev = xhci->devs[udev->slot_id];
1457 in_ctx = virt_dev->in_ctx;
1458 out_ctx = virt_dev->out_ctx;
1459 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1460 ep_index = xhci_get_endpoint_index(&ep->desc);
1461 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1462
1463 /* If this endpoint is already in use, and the upper layers are trying
1464 * to add it again without dropping it, reject the addition.
1465 */
1466 if (virt_dev->eps[ep_index].ring &&
1467 !(le32_to_cpu(ctrl_ctx->drop_flags) &
1468 xhci_get_endpoint_flag(&ep->desc))) {
1469 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1470 "without dropping it.\n",
1471 (unsigned int) ep->desc.bEndpointAddress);
1472 return -EINVAL;
1473 }
1474
1475 /* If the HCD has already noted the endpoint is enabled,
1476 * ignore this request.
1477 */
1478 if (le32_to_cpu(ctrl_ctx->add_flags) &
1479 xhci_get_endpoint_flag(&ep->desc)) {
1480 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1481 __func__, ep);
1482 return 0;
1483 }
1484
1485 /*
1486 * Configuration and alternate setting changes must be done in
1487 * process context, not interrupt context (or so documenation
1488 * for usb_set_interface() and usb_set_configuration() claim).
1489 */
1490 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1491 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1492 __func__, ep->desc.bEndpointAddress);
1493 return -ENOMEM;
1494 }
1495
1496 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1497 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1498
1499 /* If xhci_endpoint_disable() was called for this endpoint, but the
1500 * xHC hasn't been notified yet through the check_bandwidth() call,
1501 * this re-adds a new state for the endpoint from the new endpoint
1502 * descriptors. We must drop and re-add this endpoint, so we leave the
1503 * drop flags alone.
1504 */
1505 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1506
1507 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1508 /* Update the last valid endpoint context, if we just added one past */
1509 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
1510 LAST_CTX(last_ctx)) {
1511 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1512 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1513 }
1514 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1515
1516 /* Store the usb_device pointer for later use */
1517 ep->hcpriv = udev;
1518
1519 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1520 (unsigned int) ep->desc.bEndpointAddress,
1521 udev->slot_id,
1522 (unsigned int) new_drop_flags,
1523 (unsigned int) new_add_flags,
1524 (unsigned int) new_slot_info);
1525 return 0;
1526}
1527
1528static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1529{
1530 struct xhci_input_control_ctx *ctrl_ctx;
1531 struct xhci_ep_ctx *ep_ctx;
1532 struct xhci_slot_ctx *slot_ctx;
1533 int i;
1534
1535 /* When a device's add flag and drop flag are zero, any subsequent
1536 * configure endpoint command will leave that endpoint's state
1537 * untouched. Make sure we don't leave any old state in the input
1538 * endpoint contexts.
1539 */
1540 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1541 ctrl_ctx->drop_flags = 0;
1542 ctrl_ctx->add_flags = 0;
1543 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1544 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1545 /* Endpoint 0 is always valid */
1546 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1547 for (i = 1; i < 31; ++i) {
1548 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1549 ep_ctx->ep_info = 0;
1550 ep_ctx->ep_info2 = 0;
1551 ep_ctx->deq = 0;
1552 ep_ctx->tx_info = 0;
1553 }
1554}
1555
1556static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1557 struct usb_device *udev, u32 *cmd_status)
1558{
1559 int ret;
1560
1561 switch (*cmd_status) {
1562 case COMP_ENOMEM:
1563 dev_warn(&udev->dev, "Not enough host controller resources "
1564 "for new device state.\n");
1565 ret = -ENOMEM;
1566 /* FIXME: can we allocate more resources for the HC? */
1567 break;
1568 case COMP_BW_ERR:
1569 dev_warn(&udev->dev, "Not enough bandwidth "
1570 "for new device state.\n");
1571 ret = -ENOSPC;
1572 /* FIXME: can we go back to the old state? */
1573 break;
1574 case COMP_TRB_ERR:
1575 /* the HCD set up something wrong */
1576 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1577 "add flag = 1, "
1578 "and endpoint is not disabled.\n");
1579 ret = -EINVAL;
1580 break;
1581 case COMP_DEV_ERR:
1582 dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
1583 "configure command.\n");
1584 ret = -ENODEV;
1585 break;
1586 case COMP_SUCCESS:
1587 dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
1588 ret = 0;
1589 break;
1590 default:
1591 xhci_err(xhci, "ERROR: unexpected command completion "
1592 "code 0x%x.\n", *cmd_status);
1593 ret = -EINVAL;
1594 break;
1595 }
1596 return ret;
1597}
1598
1599static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1600 struct usb_device *udev, u32 *cmd_status)
1601{
1602 int ret;
1603 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1604
1605 switch (*cmd_status) {
1606 case COMP_EINVAL:
1607 dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1608 "context command.\n");
1609 ret = -EINVAL;
1610 break;
1611 case COMP_EBADSLT:
1612 dev_warn(&udev->dev, "WARN: slot not enabled for"
1613 "evaluate context command.\n");
1614 case COMP_CTX_STATE:
1615 dev_warn(&udev->dev, "WARN: invalid context state for "
1616 "evaluate context command.\n");
1617 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1618 ret = -EINVAL;
1619 break;
1620 case COMP_DEV_ERR:
1621 dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
1622 "context command.\n");
1623 ret = -ENODEV;
1624 break;
1625 case COMP_MEL_ERR:
1626 /* Max Exit Latency too large error */
1627 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1628 ret = -EINVAL;
1629 break;
1630 case COMP_SUCCESS:
1631 dev_dbg(&udev->dev, "Successful evaluate context command\n");
1632 ret = 0;
1633 break;
1634 default:
1635 xhci_err(xhci, "ERROR: unexpected command completion "
1636 "code 0x%x.\n", *cmd_status);
1637 ret = -EINVAL;
1638 break;
1639 }
1640 return ret;
1641}
1642
1643static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1644 struct xhci_container_ctx *in_ctx)
1645{
1646 struct xhci_input_control_ctx *ctrl_ctx;
1647 u32 valid_add_flags;
1648 u32 valid_drop_flags;
1649
1650 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1651 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1652 * (bit 1). The default control endpoint is added during the Address
1653 * Device command and is never removed until the slot is disabled.
1654 */
1655 valid_add_flags = ctrl_ctx->add_flags >> 2;
1656 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1657
1658 /* Use hweight32 to count the number of ones in the add flags, or
1659 * number of endpoints added. Don't count endpoints that are changed
1660 * (both added and dropped).
1661 */
1662 return hweight32(valid_add_flags) -
1663 hweight32(valid_add_flags & valid_drop_flags);
1664}
1665
1666static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1667 struct xhci_container_ctx *in_ctx)
1668{
1669 struct xhci_input_control_ctx *ctrl_ctx;
1670 u32 valid_add_flags;
1671 u32 valid_drop_flags;
1672
1673 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1674 valid_add_flags = ctrl_ctx->add_flags >> 2;
1675 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1676
1677 return hweight32(valid_drop_flags) -
1678 hweight32(valid_add_flags & valid_drop_flags);
1679}
1680
1681/*
1682 * We need to reserve the new number of endpoints before the configure endpoint
1683 * command completes. We can't subtract the dropped endpoints from the number
1684 * of active endpoints until the command completes because we can oversubscribe
1685 * the host in this case:
1686 *
1687 * - the first configure endpoint command drops more endpoints than it adds
1688 * - a second configure endpoint command that adds more endpoints is queued
1689 * - the first configure endpoint command fails, so the config is unchanged
1690 * - the second command may succeed, even though there isn't enough resources
1691 *
1692 * Must be called with xhci->lock held.
1693 */
1694static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1695 struct xhci_container_ctx *in_ctx)
1696{
1697 u32 added_eps;
1698
1699 added_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1700 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1701 xhci_dbg(xhci, "Not enough ep ctxs: "
1702 "%u active, need to add %u, limit is %u.\n",
1703 xhci->num_active_eps, added_eps,
1704 xhci->limit_active_eps);
1705 return -ENOMEM;
1706 }
1707 xhci->num_active_eps += added_eps;
1708 xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps,
1709 xhci->num_active_eps);
1710 return 0;
1711}
1712
1713/*
1714 * The configure endpoint was failed by the xHC for some other reason, so we
1715 * need to revert the resources that failed configuration would have used.
1716 *
1717 * Must be called with xhci->lock held.
1718 */
1719static void xhci_free_host_resources(struct xhci_hcd *xhci,
1720 struct xhci_container_ctx *in_ctx)
1721{
1722 u32 num_failed_eps;
1723
1724 num_failed_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1725 xhci->num_active_eps -= num_failed_eps;
1726 xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n",
1727 num_failed_eps,
1728 xhci->num_active_eps);
1729}
1730
1731/*
1732 * Now that the command has completed, clean up the active endpoint count by
1733 * subtracting out the endpoints that were dropped (but not changed).
1734 *
1735 * Must be called with xhci->lock held.
1736 */
1737static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
1738 struct xhci_container_ctx *in_ctx)
1739{
1740 u32 num_dropped_eps;
1741
1742 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, in_ctx);
1743 xhci->num_active_eps -= num_dropped_eps;
1744 if (num_dropped_eps)
1745 xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n",
1746 num_dropped_eps,
1747 xhci->num_active_eps);
1748}
1749
1750/* Issue a configure endpoint command or evaluate context command
1751 * and wait for it to finish.
1752 */
1753static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1754 struct usb_device *udev,
1755 struct xhci_command *command,
1756 bool ctx_change, bool must_succeed)
1757{
1758 int ret;
1759 int timeleft;
1760 unsigned long flags;
1761 struct xhci_container_ctx *in_ctx;
1762 struct completion *cmd_completion;
1763 u32 *cmd_status;
1764 struct xhci_virt_device *virt_dev;
1765
1766 spin_lock_irqsave(&xhci->lock, flags);
1767 virt_dev = xhci->devs[udev->slot_id];
1768 if (command) {
1769 in_ctx = command->in_ctx;
1770 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
1771 xhci_reserve_host_resources(xhci, in_ctx)) {
1772 spin_unlock_irqrestore(&xhci->lock, flags);
1773 xhci_warn(xhci, "Not enough host resources, "
1774 "active endpoint contexts = %u\n",
1775 xhci->num_active_eps);
1776 return -ENOMEM;
1777 }
1778
1779 cmd_completion = command->completion;
1780 cmd_status = &command->status;
1781 command->command_trb = xhci->cmd_ring->enqueue;
1782
1783 /* Enqueue pointer can be left pointing to the link TRB,
1784 * we must handle that
1785 */
1786 if (TRB_TYPE_LINK_LE32(command->command_trb->link.control))
1787 command->command_trb =
1788 xhci->cmd_ring->enq_seg->next->trbs;
1789
1790 list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
1791 } else {
1792 in_ctx = virt_dev->in_ctx;
1793 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
1794 xhci_reserve_host_resources(xhci, in_ctx)) {
1795 spin_unlock_irqrestore(&xhci->lock, flags);
1796 xhci_warn(xhci, "Not enough host resources, "
1797 "active endpoint contexts = %u\n",
1798 xhci->num_active_eps);
1799 return -ENOMEM;
1800 }
1801 cmd_completion = &virt_dev->cmd_completion;
1802 cmd_status = &virt_dev->cmd_status;
1803 }
1804 init_completion(cmd_completion);
1805
1806 if (!ctx_change)
1807 ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
1808 udev->slot_id, must_succeed);
1809 else
1810 ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
1811 udev->slot_id);
1812 if (ret < 0) {
1813 if (command)
1814 list_del(&command->cmd_list);
1815 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
1816 xhci_free_host_resources(xhci, in_ctx);
1817 spin_unlock_irqrestore(&xhci->lock, flags);
1818 xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
1819 return -ENOMEM;
1820 }
1821 xhci_ring_cmd_db(xhci);
1822 spin_unlock_irqrestore(&xhci->lock, flags);
1823
1824 /* Wait for the configure endpoint command to complete */
1825 timeleft = wait_for_completion_interruptible_timeout(
1826 cmd_completion,
1827 USB_CTRL_SET_TIMEOUT);
1828 if (timeleft <= 0) {
1829 xhci_warn(xhci, "%s while waiting for %s command\n",
1830 timeleft == 0 ? "Timeout" : "Signal",
1831 ctx_change == 0 ?
1832 "configure endpoint" :
1833 "evaluate context");
1834 /* FIXME cancel the configure endpoint command */
1835 return -ETIME;
1836 }
1837
1838 if (!ctx_change)
1839 ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
1840 else
1841 ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
1842
1843 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
1844 spin_lock_irqsave(&xhci->lock, flags);
1845 /* If the command failed, remove the reserved resources.
1846 * Otherwise, clean up the estimate to include dropped eps.
1847 */
1848 if (ret)
1849 xhci_free_host_resources(xhci, in_ctx);
1850 else
1851 xhci_finish_resource_reservation(xhci, in_ctx);
1852 spin_unlock_irqrestore(&xhci->lock, flags);
1853 }
1854 return ret;
1855}
1856
1857/* Called after one or more calls to xhci_add_endpoint() or
1858 * xhci_drop_endpoint(). If this call fails, the USB core is expected
1859 * to call xhci_reset_bandwidth().
1860 *
1861 * Since we are in the middle of changing either configuration or
1862 * installing a new alt setting, the USB core won't allow URBs to be
1863 * enqueued for any endpoint on the old config or interface. Nothing
1864 * else should be touching the xhci->devs[slot_id] structure, so we
1865 * don't need to take the xhci->lock for manipulating that.
1866 */
1867int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
1868{
1869 int i;
1870 int ret = 0;
1871 struct xhci_hcd *xhci;
1872 struct xhci_virt_device *virt_dev;
1873 struct xhci_input_control_ctx *ctrl_ctx;
1874 struct xhci_slot_ctx *slot_ctx;
1875
1876 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
1877 if (ret <= 0)
1878 return ret;
1879 xhci = hcd_to_xhci(hcd);
1880 if (xhci->xhc_state & XHCI_STATE_DYING)
1881 return -ENODEV;
1882
1883 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1884 virt_dev = xhci->devs[udev->slot_id];
1885
1886 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
1887 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1888 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
1889 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
1890 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
1891 xhci_dbg(xhci, "New Input Control Context:\n");
1892 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1893 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
1894 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
1895
1896 ret = xhci_configure_endpoint(xhci, udev, NULL,
1897 false, false);
1898 if (ret) {
1899 /* Callee should call reset_bandwidth() */
1900 return ret;
1901 }
1902
1903 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
1904 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
1905 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
1906
1907 /* Free any rings that were dropped, but not changed. */
1908 for (i = 1; i < 31; ++i) {
1909 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
1910 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
1911 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
1912 }
1913 xhci_zero_in_ctx(xhci, virt_dev);
1914 /*
1915 * Install any rings for completely new endpoints or changed endpoints,
1916 * and free or cache any old rings from changed endpoints.
1917 */
1918 for (i = 1; i < 31; ++i) {
1919 if (!virt_dev->eps[i].new_ring)
1920 continue;
1921 /* Only cache or free the old ring if it exists.
1922 * It may not if this is the first add of an endpoint.
1923 */
1924 if (virt_dev->eps[i].ring) {
1925 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
1926 }
1927 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
1928 virt_dev->eps[i].new_ring = NULL;
1929 }
1930
1931 return ret;
1932}
1933
1934void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
1935{
1936 struct xhci_hcd *xhci;
1937 struct xhci_virt_device *virt_dev;
1938 int i, ret;
1939
1940 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
1941 if (ret <= 0)
1942 return;
1943 xhci = hcd_to_xhci(hcd);
1944
1945 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1946 virt_dev = xhci->devs[udev->slot_id];
1947 /* Free any rings allocated for added endpoints */
1948 for (i = 0; i < 31; ++i) {
1949 if (virt_dev->eps[i].new_ring) {
1950 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
1951 virt_dev->eps[i].new_ring = NULL;
1952 }
1953 }
1954 xhci_zero_in_ctx(xhci, virt_dev);
1955}
1956
1957static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
1958 struct xhci_container_ctx *in_ctx,
1959 struct xhci_container_ctx *out_ctx,
1960 u32 add_flags, u32 drop_flags)
1961{
1962 struct xhci_input_control_ctx *ctrl_ctx;
1963 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1964 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
1965 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
1966 xhci_slot_copy(xhci, in_ctx, out_ctx);
1967 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
1968
1969 xhci_dbg(xhci, "Input Context:\n");
1970 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
1971}
1972
1973static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
1974 unsigned int slot_id, unsigned int ep_index,
1975 struct xhci_dequeue_state *deq_state)
1976{
1977 struct xhci_container_ctx *in_ctx;
1978 struct xhci_ep_ctx *ep_ctx;
1979 u32 added_ctxs;
1980 dma_addr_t addr;
1981
1982 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1983 xhci->devs[slot_id]->out_ctx, ep_index);
1984 in_ctx = xhci->devs[slot_id]->in_ctx;
1985 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1986 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
1987 deq_state->new_deq_ptr);
1988 if (addr == 0) {
1989 xhci_warn(xhci, "WARN Cannot submit config ep after "
1990 "reset ep command\n");
1991 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
1992 deq_state->new_deq_seg,
1993 deq_state->new_deq_ptr);
1994 return;
1995 }
1996 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
1997
1998 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
1999 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2000 xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
2001}
2002
2003void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2004 struct usb_device *udev, unsigned int ep_index)
2005{
2006 struct xhci_dequeue_state deq_state;
2007 struct xhci_virt_ep *ep;
2008
2009 xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
2010 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2011 /* We need to move the HW's dequeue pointer past this TD,
2012 * or it will attempt to resend it on the next doorbell ring.
2013 */
2014 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2015 ep_index, ep->stopped_stream, ep->stopped_td,
2016 &deq_state);
2017
2018 /* HW with the reset endpoint quirk will use the saved dequeue state to
2019 * issue a configure endpoint command later.
2020 */
2021 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2022 xhci_dbg(xhci, "Queueing new dequeue state\n");
2023 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2024 ep_index, ep->stopped_stream, &deq_state);
2025 } else {
2026 /* Better hope no one uses the input context between now and the
2027 * reset endpoint completion!
2028 * XXX: No idea how this hardware will react when stream rings
2029 * are enabled.
2030 */
2031 xhci_dbg(xhci, "Setting up input context for "
2032 "configure endpoint command\n");
2033 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2034 ep_index, &deq_state);
2035 }
2036}
2037
2038/* Deal with stalled endpoints. The core should have sent the control message
2039 * to clear the halt condition. However, we need to make the xHCI hardware
2040 * reset its sequence number, since a device will expect a sequence number of
2041 * zero after the halt condition is cleared.
2042 * Context: in_interrupt
2043 */
2044void xhci_endpoint_reset(struct usb_hcd *hcd,
2045 struct usb_host_endpoint *ep)
2046{
2047 struct xhci_hcd *xhci;
2048 struct usb_device *udev;
2049 unsigned int ep_index;
2050 unsigned long flags;
2051 int ret;
2052 struct xhci_virt_ep *virt_ep;
2053
2054 xhci = hcd_to_xhci(hcd);
2055 udev = (struct usb_device *) ep->hcpriv;
2056 /* Called with a root hub endpoint (or an endpoint that wasn't added
2057 * with xhci_add_endpoint()
2058 */
2059 if (!ep->hcpriv)
2060 return;
2061 ep_index = xhci_get_endpoint_index(&ep->desc);
2062 virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2063 if (!virt_ep->stopped_td) {
2064 xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
2065 ep->desc.bEndpointAddress);
2066 return;
2067 }
2068 if (usb_endpoint_xfer_control(&ep->desc)) {
2069 xhci_dbg(xhci, "Control endpoint stall already handled.\n");
2070 return;
2071 }
2072
2073 xhci_dbg(xhci, "Queueing reset endpoint command\n");
2074 spin_lock_irqsave(&xhci->lock, flags);
2075 ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
2076 /*
2077 * Can't change the ring dequeue pointer until it's transitioned to the
2078 * stopped state, which is only upon a successful reset endpoint
2079 * command. Better hope that last command worked!
2080 */
2081 if (!ret) {
2082 xhci_cleanup_stalled_ring(xhci, udev, ep_index);
2083 kfree(virt_ep->stopped_td);
2084 xhci_ring_cmd_db(xhci);
2085 }
2086 virt_ep->stopped_td = NULL;
2087 virt_ep->stopped_trb = NULL;
2088 virt_ep->stopped_stream = 0;
2089 spin_unlock_irqrestore(&xhci->lock, flags);
2090
2091 if (ret)
2092 xhci_warn(xhci, "FIXME allocate a new ring segment\n");
2093}
2094
2095static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2096 struct usb_device *udev, struct usb_host_endpoint *ep,
2097 unsigned int slot_id)
2098{
2099 int ret;
2100 unsigned int ep_index;
2101 unsigned int ep_state;
2102
2103 if (!ep)
2104 return -EINVAL;
2105 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2106 if (ret <= 0)
2107 return -EINVAL;
2108 if (ep->ss_ep_comp.bmAttributes == 0) {
2109 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2110 " descriptor for ep 0x%x does not support streams\n",
2111 ep->desc.bEndpointAddress);
2112 return -EINVAL;
2113 }
2114
2115 ep_index = xhci_get_endpoint_index(&ep->desc);
2116 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2117 if (ep_state & EP_HAS_STREAMS ||
2118 ep_state & EP_GETTING_STREAMS) {
2119 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2120 "already has streams set up.\n",
2121 ep->desc.bEndpointAddress);
2122 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2123 "dynamic stream context array reallocation.\n");
2124 return -EINVAL;
2125 }
2126 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2127 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2128 "endpoint 0x%x; URBs are pending.\n",
2129 ep->desc.bEndpointAddress);
2130 return -EINVAL;
2131 }
2132 return 0;
2133}
2134
2135static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
2136 unsigned int *num_streams, unsigned int *num_stream_ctxs)
2137{
2138 unsigned int max_streams;
2139
2140 /* The stream context array size must be a power of two */
2141 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
2142 /*
2143 * Find out how many primary stream array entries the host controller
2144 * supports. Later we may use secondary stream arrays (similar to 2nd
2145 * level page entries), but that's an optional feature for xHCI host
2146 * controllers. xHCs must support at least 4 stream IDs.
2147 */
2148 max_streams = HCC_MAX_PSA(xhci->hcc_params);
2149 if (*num_stream_ctxs > max_streams) {
2150 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
2151 max_streams);
2152 *num_stream_ctxs = max_streams;
2153 *num_streams = max_streams;
2154 }
2155}
2156
2157/* Returns an error code if one of the endpoint already has streams.
2158 * This does not change any data structures, it only checks and gathers
2159 * information.
2160 */
2161static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
2162 struct usb_device *udev,
2163 struct usb_host_endpoint **eps, unsigned int num_eps,
2164 unsigned int *num_streams, u32 *changed_ep_bitmask)
2165{
2166 unsigned int max_streams;
2167 unsigned int endpoint_flag;
2168 int i;
2169 int ret;
2170
2171 for (i = 0; i < num_eps; i++) {
2172 ret = xhci_check_streams_endpoint(xhci, udev,
2173 eps[i], udev->slot_id);
2174 if (ret < 0)
2175 return ret;
2176
2177 max_streams = USB_SS_MAX_STREAMS(
2178 eps[i]->ss_ep_comp.bmAttributes);
2179 if (max_streams < (*num_streams - 1)) {
2180 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
2181 eps[i]->desc.bEndpointAddress,
2182 max_streams);
2183 *num_streams = max_streams+1;
2184 }
2185
2186 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
2187 if (*changed_ep_bitmask & endpoint_flag)
2188 return -EINVAL;
2189 *changed_ep_bitmask |= endpoint_flag;
2190 }
2191 return 0;
2192}
2193
2194static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
2195 struct usb_device *udev,
2196 struct usb_host_endpoint **eps, unsigned int num_eps)
2197{
2198 u32 changed_ep_bitmask = 0;
2199 unsigned int slot_id;
2200 unsigned int ep_index;
2201 unsigned int ep_state;
2202 int i;
2203
2204 slot_id = udev->slot_id;
2205 if (!xhci->devs[slot_id])
2206 return 0;
2207
2208 for (i = 0; i < num_eps; i++) {
2209 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2210 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2211 /* Are streams already being freed for the endpoint? */
2212 if (ep_state & EP_GETTING_NO_STREAMS) {
2213 xhci_warn(xhci, "WARN Can't disable streams for "
2214 "endpoint 0x%x\n, "
2215 "streams are being disabled already.",
2216 eps[i]->desc.bEndpointAddress);
2217 return 0;
2218 }
2219 /* Are there actually any streams to free? */
2220 if (!(ep_state & EP_HAS_STREAMS) &&
2221 !(ep_state & EP_GETTING_STREAMS)) {
2222 xhci_warn(xhci, "WARN Can't disable streams for "
2223 "endpoint 0x%x\n, "
2224 "streams are already disabled!",
2225 eps[i]->desc.bEndpointAddress);
2226 xhci_warn(xhci, "WARN xhci_free_streams() called "
2227 "with non-streams endpoint\n");
2228 return 0;
2229 }
2230 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
2231 }
2232 return changed_ep_bitmask;
2233}
2234
2235/*
2236 * The USB device drivers use this function (though the HCD interface in USB
2237 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
2238 * coordinate mass storage command queueing across multiple endpoints (basically
2239 * a stream ID == a task ID).
2240 *
2241 * Setting up streams involves allocating the same size stream context array
2242 * for each endpoint and issuing a configure endpoint command for all endpoints.
2243 *
2244 * Don't allow the call to succeed if one endpoint only supports one stream
2245 * (which means it doesn't support streams at all).
2246 *
2247 * Drivers may get less stream IDs than they asked for, if the host controller
2248 * hardware or endpoints claim they can't support the number of requested
2249 * stream IDs.
2250 */
2251int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
2252 struct usb_host_endpoint **eps, unsigned int num_eps,
2253 unsigned int num_streams, gfp_t mem_flags)
2254{
2255 int i, ret;
2256 struct xhci_hcd *xhci;
2257 struct xhci_virt_device *vdev;
2258 struct xhci_command *config_cmd;
2259 unsigned int ep_index;
2260 unsigned int num_stream_ctxs;
2261 unsigned long flags;
2262 u32 changed_ep_bitmask = 0;
2263
2264 if (!eps)
2265 return -EINVAL;
2266
2267 /* Add one to the number of streams requested to account for
2268 * stream 0 that is reserved for xHCI usage.
2269 */
2270 num_streams += 1;
2271 xhci = hcd_to_xhci(hcd);
2272 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
2273 num_streams);
2274
2275 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
2276 if (!config_cmd) {
2277 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
2278 return -ENOMEM;
2279 }
2280
2281 /* Check to make sure all endpoints are not already configured for
2282 * streams. While we're at it, find the maximum number of streams that
2283 * all the endpoints will support and check for duplicate endpoints.
2284 */
2285 spin_lock_irqsave(&xhci->lock, flags);
2286 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
2287 num_eps, &num_streams, &changed_ep_bitmask);
2288 if (ret < 0) {
2289 xhci_free_command(xhci, config_cmd);
2290 spin_unlock_irqrestore(&xhci->lock, flags);
2291 return ret;
2292 }
2293 if (num_streams <= 1) {
2294 xhci_warn(xhci, "WARN: endpoints can't handle "
2295 "more than one stream.\n");
2296 xhci_free_command(xhci, config_cmd);
2297 spin_unlock_irqrestore(&xhci->lock, flags);
2298 return -EINVAL;
2299 }
2300 vdev = xhci->devs[udev->slot_id];
2301 /* Mark each endpoint as being in transition, so
2302 * xhci_urb_enqueue() will reject all URBs.
2303 */
2304 for (i = 0; i < num_eps; i++) {
2305 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2306 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
2307 }
2308 spin_unlock_irqrestore(&xhci->lock, flags);
2309
2310 /* Setup internal data structures and allocate HW data structures for
2311 * streams (but don't install the HW structures in the input context
2312 * until we're sure all memory allocation succeeded).
2313 */
2314 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
2315 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
2316 num_stream_ctxs, num_streams);
2317
2318 for (i = 0; i < num_eps; i++) {
2319 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2320 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
2321 num_stream_ctxs,
2322 num_streams, mem_flags);
2323 if (!vdev->eps[ep_index].stream_info)
2324 goto cleanup;
2325 /* Set maxPstreams in endpoint context and update deq ptr to
2326 * point to stream context array. FIXME
2327 */
2328 }
2329
2330 /* Set up the input context for a configure endpoint command. */
2331 for (i = 0; i < num_eps; i++) {
2332 struct xhci_ep_ctx *ep_ctx;
2333
2334 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2335 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
2336
2337 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
2338 vdev->out_ctx, ep_index);
2339 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
2340 vdev->eps[ep_index].stream_info);
2341 }
2342 /* Tell the HW to drop its old copy of the endpoint context info
2343 * and add the updated copy from the input context.
2344 */
2345 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
2346 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
2347
2348 /* Issue and wait for the configure endpoint command */
2349 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
2350 false, false);
2351
2352 /* xHC rejected the configure endpoint command for some reason, so we
2353 * leave the old ring intact and free our internal streams data
2354 * structure.
2355 */
2356 if (ret < 0)
2357 goto cleanup;
2358
2359 spin_lock_irqsave(&xhci->lock, flags);
2360 for (i = 0; i < num_eps; i++) {
2361 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2362 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
2363 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
2364 udev->slot_id, ep_index);
2365 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
2366 }
2367 xhci_free_command(xhci, config_cmd);
2368 spin_unlock_irqrestore(&xhci->lock, flags);
2369
2370 /* Subtract 1 for stream 0, which drivers can't use */
2371 return num_streams - 1;
2372
2373cleanup:
2374 /* If it didn't work, free the streams! */
2375 for (i = 0; i < num_eps; i++) {
2376 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2377 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
2378 vdev->eps[ep_index].stream_info = NULL;
2379 /* FIXME Unset maxPstreams in endpoint context and
2380 * update deq ptr to point to normal string ring.
2381 */
2382 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
2383 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
2384 xhci_endpoint_zero(xhci, vdev, eps[i]);
2385 }
2386 xhci_free_command(xhci, config_cmd);
2387 return -ENOMEM;
2388}
2389
2390/* Transition the endpoint from using streams to being a "normal" endpoint
2391 * without streams.
2392 *
2393 * Modify the endpoint context state, submit a configure endpoint command,
2394 * and free all endpoint rings for streams if that completes successfully.
2395 */
2396int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
2397 struct usb_host_endpoint **eps, unsigned int num_eps,
2398 gfp_t mem_flags)
2399{
2400 int i, ret;
2401 struct xhci_hcd *xhci;
2402 struct xhci_virt_device *vdev;
2403 struct xhci_command *command;
2404 unsigned int ep_index;
2405 unsigned long flags;
2406 u32 changed_ep_bitmask;
2407
2408 xhci = hcd_to_xhci(hcd);
2409 vdev = xhci->devs[udev->slot_id];
2410
2411 /* Set up a configure endpoint command to remove the streams rings */
2412 spin_lock_irqsave(&xhci->lock, flags);
2413 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
2414 udev, eps, num_eps);
2415 if (changed_ep_bitmask == 0) {
2416 spin_unlock_irqrestore(&xhci->lock, flags);
2417 return -EINVAL;
2418 }
2419
2420 /* Use the xhci_command structure from the first endpoint. We may have
2421 * allocated too many, but the driver may call xhci_free_streams() for
2422 * each endpoint it grouped into one call to xhci_alloc_streams().
2423 */
2424 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
2425 command = vdev->eps[ep_index].stream_info->free_streams_command;
2426 for (i = 0; i < num_eps; i++) {
2427 struct xhci_ep_ctx *ep_ctx;
2428
2429 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2430 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
2431 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
2432 EP_GETTING_NO_STREAMS;
2433
2434 xhci_endpoint_copy(xhci, command->in_ctx,
2435 vdev->out_ctx, ep_index);
2436 xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
2437 &vdev->eps[ep_index]);
2438 }
2439 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
2440 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
2441 spin_unlock_irqrestore(&xhci->lock, flags);
2442
2443 /* Issue and wait for the configure endpoint command,
2444 * which must succeed.
2445 */
2446 ret = xhci_configure_endpoint(xhci, udev, command,
2447 false, true);
2448
2449 /* xHC rejected the configure endpoint command for some reason, so we
2450 * leave the streams rings intact.
2451 */
2452 if (ret < 0)
2453 return ret;
2454
2455 spin_lock_irqsave(&xhci->lock, flags);
2456 for (i = 0; i < num_eps; i++) {
2457 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2458 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
2459 vdev->eps[ep_index].stream_info = NULL;
2460 /* FIXME Unset maxPstreams in endpoint context and
2461 * update deq ptr to point to normal string ring.
2462 */
2463 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
2464 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
2465 }
2466 spin_unlock_irqrestore(&xhci->lock, flags);
2467
2468 return 0;
2469}
2470
2471/*
2472 * Deletes endpoint resources for endpoints that were active before a Reset
2473 * Device command, or a Disable Slot command. The Reset Device command leaves
2474 * the control endpoint intact, whereas the Disable Slot command deletes it.
2475 *
2476 * Must be called with xhci->lock held.
2477 */
2478void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2479 struct xhci_virt_device *virt_dev, bool drop_control_ep)
2480{
2481 int i;
2482 unsigned int num_dropped_eps = 0;
2483 unsigned int drop_flags = 0;
2484
2485 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
2486 if (virt_dev->eps[i].ring) {
2487 drop_flags |= 1 << i;
2488 num_dropped_eps++;
2489 }
2490 }
2491 xhci->num_active_eps -= num_dropped_eps;
2492 if (num_dropped_eps)
2493 xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, "
2494 "%u now active.\n",
2495 num_dropped_eps, drop_flags,
2496 xhci->num_active_eps);
2497}
2498
2499/*
2500 * This submits a Reset Device Command, which will set the device state to 0,
2501 * set the device address to 0, and disable all the endpoints except the default
2502 * control endpoint. The USB core should come back and call
2503 * xhci_address_device(), and then re-set up the configuration. If this is
2504 * called because of a usb_reset_and_verify_device(), then the old alternate
2505 * settings will be re-installed through the normal bandwidth allocation
2506 * functions.
2507 *
2508 * Wait for the Reset Device command to finish. Remove all structures
2509 * associated with the endpoints that were disabled. Clear the input device
2510 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
2511 *
2512 * If the virt_dev to be reset does not exist or does not match the udev,
2513 * it means the device is lost, possibly due to the xHC restore error and
2514 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
2515 * re-allocate the device.
2516 */
2517int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
2518{
2519 int ret, i;
2520 unsigned long flags;
2521 struct xhci_hcd *xhci;
2522 unsigned int slot_id;
2523 struct xhci_virt_device *virt_dev;
2524 struct xhci_command *reset_device_cmd;
2525 int timeleft;
2526 int last_freed_endpoint;
2527 struct xhci_slot_ctx *slot_ctx;
2528
2529 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
2530 if (ret <= 0)
2531 return ret;
2532 xhci = hcd_to_xhci(hcd);
2533 slot_id = udev->slot_id;
2534 virt_dev = xhci->devs[slot_id];
2535 if (!virt_dev) {
2536 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
2537 "not exist. Re-allocate the device\n", slot_id);
2538 ret = xhci_alloc_dev(hcd, udev);
2539 if (ret == 1)
2540 return 0;
2541 else
2542 return -EINVAL;
2543 }
2544
2545 if (virt_dev->udev != udev) {
2546 /* If the virt_dev and the udev does not match, this virt_dev
2547 * may belong to another udev.
2548 * Re-allocate the device.
2549 */
2550 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
2551 "not match the udev. Re-allocate the device\n",
2552 slot_id);
2553 ret = xhci_alloc_dev(hcd, udev);
2554 if (ret == 1)
2555 return 0;
2556 else
2557 return -EINVAL;
2558 }
2559
2560 /* If device is not setup, there is no point in resetting it */
2561 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
2562 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
2563 SLOT_STATE_DISABLED)
2564 return 0;
2565
2566 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
2567 /* Allocate the command structure that holds the struct completion.
2568 * Assume we're in process context, since the normal device reset
2569 * process has to wait for the device anyway. Storage devices are
2570 * reset as part of error handling, so use GFP_NOIO instead of
2571 * GFP_KERNEL.
2572 */
2573 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
2574 if (!reset_device_cmd) {
2575 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
2576 return -ENOMEM;
2577 }
2578
2579 /* Attempt to submit the Reset Device command to the command ring */
2580 spin_lock_irqsave(&xhci->lock, flags);
2581 reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
2582
2583 /* Enqueue pointer can be left pointing to the link TRB,
2584 * we must handle that
2585 */
2586 if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control))
2587 reset_device_cmd->command_trb =
2588 xhci->cmd_ring->enq_seg->next->trbs;
2589
2590 list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
2591 ret = xhci_queue_reset_device(xhci, slot_id);
2592 if (ret) {
2593 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2594 list_del(&reset_device_cmd->cmd_list);
2595 spin_unlock_irqrestore(&xhci->lock, flags);
2596 goto command_cleanup;
2597 }
2598 xhci_ring_cmd_db(xhci);
2599 spin_unlock_irqrestore(&xhci->lock, flags);
2600
2601 /* Wait for the Reset Device command to finish */
2602 timeleft = wait_for_completion_interruptible_timeout(
2603 reset_device_cmd->completion,
2604 USB_CTRL_SET_TIMEOUT);
2605 if (timeleft <= 0) {
2606 xhci_warn(xhci, "%s while waiting for reset device command\n",
2607 timeleft == 0 ? "Timeout" : "Signal");
2608 spin_lock_irqsave(&xhci->lock, flags);
2609 /* The timeout might have raced with the event ring handler, so
2610 * only delete from the list if the item isn't poisoned.
2611 */
2612 if (reset_device_cmd->cmd_list.next != LIST_POISON1)
2613 list_del(&reset_device_cmd->cmd_list);
2614 spin_unlock_irqrestore(&xhci->lock, flags);
2615 ret = -ETIME;
2616 goto command_cleanup;
2617 }
2618
2619 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
2620 * unless we tried to reset a slot ID that wasn't enabled,
2621 * or the device wasn't in the addressed or configured state.
2622 */
2623 ret = reset_device_cmd->status;
2624 switch (ret) {
2625 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
2626 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
2627 xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
2628 slot_id,
2629 xhci_get_slot_state(xhci, virt_dev->out_ctx));
2630 xhci_info(xhci, "Not freeing device rings.\n");
2631 /* Don't treat this as an error. May change my mind later. */
2632 ret = 0;
2633 goto command_cleanup;
2634 case COMP_SUCCESS:
2635 xhci_dbg(xhci, "Successful reset device command.\n");
2636 break;
2637 default:
2638 if (xhci_is_vendor_info_code(xhci, ret))
2639 break;
2640 xhci_warn(xhci, "Unknown completion code %u for "
2641 "reset device command.\n", ret);
2642 ret = -EINVAL;
2643 goto command_cleanup;
2644 }
2645
2646 /* Free up host controller endpoint resources */
2647 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2648 spin_lock_irqsave(&xhci->lock, flags);
2649 /* Don't delete the default control endpoint resources */
2650 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
2651 spin_unlock_irqrestore(&xhci->lock, flags);
2652 }
2653
2654 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
2655 last_freed_endpoint = 1;
2656 for (i = 1; i < 31; ++i) {
2657 struct xhci_virt_ep *ep = &virt_dev->eps[i];
2658
2659 if (ep->ep_state & EP_HAS_STREAMS) {
2660 xhci_free_stream_info(xhci, ep->stream_info);
2661 ep->stream_info = NULL;
2662 ep->ep_state &= ~EP_HAS_STREAMS;
2663 }
2664
2665 if (ep->ring) {
2666 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2667 last_freed_endpoint = i;
2668 }
2669 }
2670 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
2671 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
2672 ret = 0;
2673
2674command_cleanup:
2675 xhci_free_command(xhci, reset_device_cmd);
2676 return ret;
2677}
2678
2679/*
2680 * At this point, the struct usb_device is about to go away, the device has
2681 * disconnected, and all traffic has been stopped and the endpoints have been
2682 * disabled. Free any HC data structures associated with that device.
2683 */
2684void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
2685{
2686 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2687 struct xhci_virt_device *virt_dev;
2688 unsigned long flags;
2689 u32 state;
2690 int i, ret;
2691
2692 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2693 /* If the host is halted due to driver unload, we still need to free the
2694 * device.
2695 */
2696 if (ret <= 0 && ret != -ENODEV)
2697 return;
2698
2699 virt_dev = xhci->devs[udev->slot_id];
2700
2701 /* Stop any wayward timer functions (which may grab the lock) */
2702 for (i = 0; i < 31; ++i) {
2703 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
2704 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
2705 }
2706
2707 spin_lock_irqsave(&xhci->lock, flags);
2708 /* Don't disable the slot if the host controller is dead. */
2709 state = xhci_readl(xhci, &xhci->op_regs->status);
2710 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
2711 (xhci->xhc_state & XHCI_STATE_HALTED)) {
2712 xhci_free_virt_device(xhci, udev->slot_id);
2713 spin_unlock_irqrestore(&xhci->lock, flags);
2714 return;
2715 }
2716
2717 if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
2718 spin_unlock_irqrestore(&xhci->lock, flags);
2719 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2720 return;
2721 }
2722 xhci_ring_cmd_db(xhci);
2723 spin_unlock_irqrestore(&xhci->lock, flags);
2724 /*
2725 * Event command completion handler will free any data structures
2726 * associated with the slot. XXX Can free sleep?
2727 */
2728}
2729
2730/*
2731 * Checks if we have enough host controller resources for the default control
2732 * endpoint.
2733 *
2734 * Must be called with xhci->lock held.
2735 */
2736static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
2737{
2738 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
2739 xhci_dbg(xhci, "Not enough ep ctxs: "
2740 "%u active, need to add 1, limit is %u.\n",
2741 xhci->num_active_eps, xhci->limit_active_eps);
2742 return -ENOMEM;
2743 }
2744 xhci->num_active_eps += 1;
2745 xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n",
2746 xhci->num_active_eps);
2747 return 0;
2748}
2749
2750
2751/*
2752 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
2753 * timed out, or allocating memory failed. Returns 1 on success.
2754 */
2755int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
2756{
2757 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2758 unsigned long flags;
2759 int timeleft;
2760 int ret;
2761
2762 spin_lock_irqsave(&xhci->lock, flags);
2763 ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
2764 if (ret) {
2765 spin_unlock_irqrestore(&xhci->lock, flags);
2766 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2767 return 0;
2768 }
2769 xhci_ring_cmd_db(xhci);
2770 spin_unlock_irqrestore(&xhci->lock, flags);
2771
2772 /* XXX: how much time for xHC slot assignment? */
2773 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
2774 USB_CTRL_SET_TIMEOUT);
2775 if (timeleft <= 0) {
2776 xhci_warn(xhci, "%s while waiting for a slot\n",
2777 timeleft == 0 ? "Timeout" : "Signal");
2778 /* FIXME cancel the enable slot request */
2779 return 0;
2780 }
2781
2782 if (!xhci->slot_id) {
2783 xhci_err(xhci, "Error while assigning device slot ID\n");
2784 return 0;
2785 }
2786
2787 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2788 spin_lock_irqsave(&xhci->lock, flags);
2789 ret = xhci_reserve_host_control_ep_resources(xhci);
2790 if (ret) {
2791 spin_unlock_irqrestore(&xhci->lock, flags);
2792 xhci_warn(xhci, "Not enough host resources, "
2793 "active endpoint contexts = %u\n",
2794 xhci->num_active_eps);
2795 goto disable_slot;
2796 }
2797 spin_unlock_irqrestore(&xhci->lock, flags);
2798 }
2799 /* Use GFP_NOIO, since this function can be called from
2800 * xhci_discover_or_reset_device(), which may be called as part of
2801 * mass storage driver error handling.
2802 */
2803 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
2804 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
2805 goto disable_slot;
2806 }
2807 udev->slot_id = xhci->slot_id;
2808 /* Is this a LS or FS device under a HS hub? */
2809 /* Hub or peripherial? */
2810 return 1;
2811
2812disable_slot:
2813 /* Disable slot, if we can do it without mem alloc */
2814 spin_lock_irqsave(&xhci->lock, flags);
2815 if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
2816 xhci_ring_cmd_db(xhci);
2817 spin_unlock_irqrestore(&xhci->lock, flags);
2818 return 0;
2819}
2820
2821/*
2822 * Issue an Address Device command (which will issue a SetAddress request to
2823 * the device).
2824 * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
2825 * we should only issue and wait on one address command at the same time.
2826 *
2827 * We add one to the device address issued by the hardware because the USB core
2828 * uses address 1 for the root hubs (even though they're not really devices).
2829 */
2830int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
2831{
2832 unsigned long flags;
2833 int timeleft;
2834 struct xhci_virt_device *virt_dev;
2835 int ret = 0;
2836 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2837 struct xhci_slot_ctx *slot_ctx;
2838 struct xhci_input_control_ctx *ctrl_ctx;
2839 u64 temp_64;
2840
2841 if (!udev->slot_id) {
2842 xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
2843 return -EINVAL;
2844 }
2845
2846 virt_dev = xhci->devs[udev->slot_id];
2847
2848 if (WARN_ON(!virt_dev)) {
2849 /*
2850 * In plug/unplug torture test with an NEC controller,
2851 * a zero-dereference was observed once due to virt_dev = 0.
2852 * Print useful debug rather than crash if it is observed again!
2853 */
2854 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
2855 udev->slot_id);
2856 return -EINVAL;
2857 }
2858
2859 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2860 /*
2861 * If this is the first Set Address since device plug-in or
2862 * virt_device realloaction after a resume with an xHCI power loss,
2863 * then set up the slot context.
2864 */
2865 if (!slot_ctx->dev_info)
2866 xhci_setup_addressable_virt_dev(xhci, udev);
2867 /* Otherwise, update the control endpoint ring enqueue pointer. */
2868 else
2869 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
2870 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
2871 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
2872
2873 spin_lock_irqsave(&xhci->lock, flags);
2874 ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
2875 udev->slot_id);
2876 if (ret) {
2877 spin_unlock_irqrestore(&xhci->lock, flags);
2878 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2879 return ret;
2880 }
2881 xhci_ring_cmd_db(xhci);
2882 spin_unlock_irqrestore(&xhci->lock, flags);
2883
2884 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
2885 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
2886 USB_CTRL_SET_TIMEOUT);
2887 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
2888 * the SetAddress() "recovery interval" required by USB and aborting the
2889 * command on a timeout.
2890 */
2891 if (timeleft <= 0) {
2892 xhci_warn(xhci, "%s while waiting for a slot\n",
2893 timeleft == 0 ? "Timeout" : "Signal");
2894 /* FIXME cancel the address device command */
2895 return -ETIME;
2896 }
2897
2898 switch (virt_dev->cmd_status) {
2899 case COMP_CTX_STATE:
2900 case COMP_EBADSLT:
2901 xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
2902 udev->slot_id);
2903 ret = -EINVAL;
2904 break;
2905 case COMP_TX_ERR:
2906 dev_warn(&udev->dev, "Device not responding to set address.\n");
2907 ret = -EPROTO;
2908 break;
2909 case COMP_DEV_ERR:
2910 dev_warn(&udev->dev, "ERROR: Incompatible device for address "
2911 "device command.\n");
2912 ret = -ENODEV;
2913 break;
2914 case COMP_SUCCESS:
2915 xhci_dbg(xhci, "Successful Address Device command\n");
2916 break;
2917 default:
2918 xhci_err(xhci, "ERROR: unexpected command completion "
2919 "code 0x%x.\n", virt_dev->cmd_status);
2920 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
2921 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
2922 ret = -EINVAL;
2923 break;
2924 }
2925 if (ret) {
2926 return ret;
2927 }
2928 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
2929 xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
2930 xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
2931 udev->slot_id,
2932 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
2933 (unsigned long long)
2934 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
2935 xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
2936 (unsigned long long)virt_dev->out_ctx->dma);
2937 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
2938 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
2939 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
2940 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
2941 /*
2942 * USB core uses address 1 for the roothubs, so we add one to the
2943 * address given back to us by the HC.
2944 */
2945 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
2946 /* Use kernel assigned address for devices; store xHC assigned
2947 * address locally. */
2948 virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
2949 + 1;
2950 /* Zero the input context control for later use */
2951 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
2952 ctrl_ctx->add_flags = 0;
2953 ctrl_ctx->drop_flags = 0;
2954
2955 xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address);
2956
2957 return 0;
2958}
2959
2960/* Once a hub descriptor is fetched for a device, we need to update the xHC's
2961 * internal data structures for the device.
2962 */
2963int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
2964 struct usb_tt *tt, gfp_t mem_flags)
2965{
2966 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2967 struct xhci_virt_device *vdev;
2968 struct xhci_command *config_cmd;
2969 struct xhci_input_control_ctx *ctrl_ctx;
2970 struct xhci_slot_ctx *slot_ctx;
2971 unsigned long flags;
2972 unsigned think_time;
2973 int ret;
2974
2975 /* Ignore root hubs */
2976 if (!hdev->parent)
2977 return 0;
2978
2979 vdev = xhci->devs[hdev->slot_id];
2980 if (!vdev) {
2981 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
2982 return -EINVAL;
2983 }
2984 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
2985 if (!config_cmd) {
2986 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
2987 return -ENOMEM;
2988 }
2989
2990 spin_lock_irqsave(&xhci->lock, flags);
2991 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
2992 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
2993 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2994 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
2995 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
2996 if (tt->multi)
2997 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
2998 if (xhci->hci_version > 0x95) {
2999 xhci_dbg(xhci, "xHCI version %x needs hub "
3000 "TT think time and number of ports\n",
3001 (unsigned int) xhci->hci_version);
3002 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
3003 /* Set TT think time - convert from ns to FS bit times.
3004 * 0 = 8 FS bit times, 1 = 16 FS bit times,
3005 * 2 = 24 FS bit times, 3 = 32 FS bit times.
3006 *
3007 * xHCI 1.0: this field shall be 0 if the device is not a
3008 * High-spped hub.
3009 */
3010 think_time = tt->think_time;
3011 if (think_time != 0)
3012 think_time = (think_time / 666) - 1;
3013 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
3014 slot_ctx->tt_info |=
3015 cpu_to_le32(TT_THINK_TIME(think_time));
3016 } else {
3017 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
3018 "TT think time or number of ports\n",
3019 (unsigned int) xhci->hci_version);
3020 }
3021 slot_ctx->dev_state = 0;
3022 spin_unlock_irqrestore(&xhci->lock, flags);
3023
3024 xhci_dbg(xhci, "Set up %s for hub device.\n",
3025 (xhci->hci_version > 0x95) ?
3026 "configure endpoint" : "evaluate context");
3027 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
3028 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
3029
3030 /* Issue and wait for the configure endpoint or
3031 * evaluate context command.
3032 */
3033 if (xhci->hci_version > 0x95)
3034 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
3035 false, false);
3036 else
3037 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
3038 true, false);
3039
3040 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
3041 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
3042
3043 xhci_free_command(xhci, config_cmd);
3044 return ret;
3045}
3046
3047int xhci_get_frame(struct usb_hcd *hcd)
3048{
3049 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3050 /* EHCI mods by the periodic size. Why? */
3051 return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
3052}
3053
3054MODULE_DESCRIPTION(DRIVER_DESC);
3055MODULE_AUTHOR(DRIVER_AUTHOR);
3056MODULE_LICENSE("GPL");
3057
3058static int __init xhci_hcd_init(void)
3059{
3060#ifdef CONFIG_PCI
3061 int retval = 0;
3062
3063 retval = xhci_register_pci();
3064
3065 if (retval < 0) {
3066 printk(KERN_DEBUG "Problem registering PCI driver.");
3067 return retval;
3068 }
3069#endif
3070 /*
3071 * Check the compiler generated sizes of structures that must be laid
3072 * out in specific ways for hardware access.
3073 */
3074 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
3075 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
3076 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
3077 /* xhci_device_control has eight fields, and also
3078 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
3079 */
3080 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
3081 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
3082 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
3083 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
3084 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
3085 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
3086 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
3087 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
3088 return 0;
3089}
3090module_init(xhci_hcd_init);
3091
3092static void __exit xhci_hcd_cleanup(void)
3093{
3094#ifdef CONFIG_PCI
3095 xhci_unregister_pci();
3096#endif
3097}
3098module_exit(xhci_hcd_cleanup);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/jiffies.h>
12#include <linux/pci.h>
13#include <linux/iommu.h>
14#include <linux/iopoll.h>
15#include <linux/irq.h>
16#include <linux/log2.h>
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/slab.h>
20#include <linux/dmi.h>
21#include <linux/dma-mapping.h>
22
23#include "xhci.h"
24#include "xhci-trace.h"
25#include "xhci-debugfs.h"
26#include "xhci-dbgcap.h"
27
28#define DRIVER_AUTHOR "Sarah Sharp"
29#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
30
31#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
32
33/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
34static int link_quirk;
35module_param(link_quirk, int, S_IRUGO | S_IWUSR);
36MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
37
38static unsigned long long quirks;
39module_param(quirks, ullong, S_IRUGO);
40MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
41
42static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
43{
44 struct xhci_segment *seg;
45
46 if (!td || !td->start_seg)
47 return false;
48
49 xhci_for_each_ring_seg(ring->first_seg, seg) {
50 if (seg == td->start_seg)
51 return true;
52 }
53
54 return false;
55}
56
57/*
58 * xhci_handshake - spin reading hc until handshake completes or fails
59 * @ptr: address of hc register to be read
60 * @mask: bits to look at in result of read
61 * @done: value of those bits when handshake succeeds
62 * @usec: timeout in microseconds
63 *
64 * Returns negative errno, or zero on success
65 *
66 * Success happens when the "mask" bits have the specified value (hardware
67 * handshake done). There are two failure modes: "usec" have passed (major
68 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 */
70int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
71{
72 u32 result;
73 int ret;
74
75 ret = readl_poll_timeout_atomic(ptr, result,
76 (result & mask) == done ||
77 result == U32_MAX,
78 1, timeout_us);
79 if (result == U32_MAX) /* card removed */
80 return -ENODEV;
81
82 return ret;
83}
84
85/*
86 * xhci_handshake_check_state - same as xhci_handshake but takes an additional
87 * exit_state parameter, and bails out with an error immediately when xhc_state
88 * has exit_state flag set.
89 */
90int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
91 u32 mask, u32 done, int usec, unsigned int exit_state)
92{
93 u32 result;
94 int ret;
95
96 ret = readl_poll_timeout_atomic(ptr, result,
97 (result & mask) == done ||
98 result == U32_MAX ||
99 xhci->xhc_state & exit_state,
100 1, usec);
101
102 if (result == U32_MAX || xhci->xhc_state & exit_state)
103 return -ENODEV;
104
105 return ret;
106}
107
108/*
109 * Disable interrupts and begin the xHCI halting process.
110 */
111void xhci_quiesce(struct xhci_hcd *xhci)
112{
113 u32 halted;
114 u32 cmd;
115 u32 mask;
116
117 mask = ~(XHCI_IRQS);
118 halted = readl(&xhci->op_regs->status) & STS_HALT;
119 if (!halted)
120 mask &= ~CMD_RUN;
121
122 cmd = readl(&xhci->op_regs->command);
123 cmd &= mask;
124 writel(cmd, &xhci->op_regs->command);
125}
126
127/*
128 * Force HC into halt state.
129 *
130 * Disable any IRQs and clear the run/stop bit.
131 * HC will complete any current and actively pipelined transactions, and
132 * should halt within 16 ms of the run/stop bit being cleared.
133 * Read HC Halted bit in the status register to see when the HC is finished.
134 */
135int xhci_halt(struct xhci_hcd *xhci)
136{
137 int ret;
138
139 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
140 xhci_quiesce(xhci);
141
142 ret = xhci_handshake(&xhci->op_regs->status,
143 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
144 if (ret) {
145 xhci_warn(xhci, "Host halt failed, %d\n", ret);
146 return ret;
147 }
148
149 xhci->xhc_state |= XHCI_STATE_HALTED;
150 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
151
152 return ret;
153}
154
155/*
156 * Set the run bit and wait for the host to be running.
157 */
158int xhci_start(struct xhci_hcd *xhci)
159{
160 u32 temp;
161 int ret;
162
163 temp = readl(&xhci->op_regs->command);
164 temp |= (CMD_RUN);
165 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
166 temp);
167 writel(temp, &xhci->op_regs->command);
168
169 /*
170 * Wait for the HCHalted Status bit to be 0 to indicate the host is
171 * running.
172 */
173 ret = xhci_handshake(&xhci->op_regs->status,
174 STS_HALT, 0, XHCI_MAX_HALT_USEC);
175 if (ret == -ETIMEDOUT)
176 xhci_err(xhci, "Host took too long to start, "
177 "waited %u microseconds.\n",
178 XHCI_MAX_HALT_USEC);
179 if (!ret) {
180 /* clear state flags. Including dying, halted or removing */
181 xhci->xhc_state = 0;
182 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
183 }
184
185 return ret;
186}
187
188/*
189 * Reset a halted HC.
190 *
191 * This resets pipelines, timers, counters, state machines, etc.
192 * Transactions will be terminated immediately, and operational registers
193 * will be set to their defaults.
194 */
195int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
196{
197 u32 command;
198 u32 state;
199 int ret;
200
201 state = readl(&xhci->op_regs->status);
202
203 if (state == ~(u32)0) {
204 xhci_warn(xhci, "Host not accessible, reset failed.\n");
205 return -ENODEV;
206 }
207
208 if ((state & STS_HALT) == 0) {
209 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
210 return 0;
211 }
212
213 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
214 command = readl(&xhci->op_regs->command);
215 command |= CMD_RESET;
216 writel(command, &xhci->op_regs->command);
217
218 /* Existing Intel xHCI controllers require a delay of 1 mS,
219 * after setting the CMD_RESET bit, and before accessing any
220 * HC registers. This allows the HC to complete the
221 * reset operation and be ready for HC register access.
222 * Without this delay, the subsequent HC register access,
223 * may result in a system hang very rarely.
224 */
225 if (xhci->quirks & XHCI_INTEL_HOST)
226 udelay(1000);
227
228 ret = xhci_handshake_check_state(xhci, &xhci->op_regs->command,
229 CMD_RESET, 0, timeout_us, XHCI_STATE_REMOVING);
230 if (ret)
231 return ret;
232
233 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
234 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
235
236 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
237 "Wait for controller to be ready for doorbell rings");
238 /*
239 * xHCI cannot write to any doorbells or operational registers other
240 * than status until the "Controller Not Ready" flag is cleared.
241 */
242 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
243
244 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
245 xhci->usb2_rhub.bus_state.suspended_ports = 0;
246 xhci->usb2_rhub.bus_state.resuming_ports = 0;
247 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
248 xhci->usb3_rhub.bus_state.suspended_ports = 0;
249 xhci->usb3_rhub.bus_state.resuming_ports = 0;
250
251 return ret;
252}
253
254static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
255{
256 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
257 struct iommu_domain *domain;
258 int err, i;
259 u64 val;
260 u32 intrs;
261
262 /*
263 * Some Renesas controllers get into a weird state if they are
264 * reset while programmed with 64bit addresses (they will preserve
265 * the top half of the address in internal, non visible
266 * registers). You end up with half the address coming from the
267 * kernel, and the other half coming from the firmware. Also,
268 * changing the programming leads to extra accesses even if the
269 * controller is supposed to be halted. The controller ends up with
270 * a fatal fault, and is then ripe for being properly reset.
271 *
272 * Special care is taken to only apply this if the device is behind
273 * an iommu. Doing anything when there is no iommu is definitely
274 * unsafe...
275 */
276 domain = iommu_get_domain_for_dev(dev);
277 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !domain ||
278 domain->type == IOMMU_DOMAIN_IDENTITY)
279 return;
280
281 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
282
283 /* Clear HSEIE so that faults do not get signaled */
284 val = readl(&xhci->op_regs->command);
285 val &= ~CMD_HSEIE;
286 writel(val, &xhci->op_regs->command);
287
288 /* Clear HSE (aka FATAL) */
289 val = readl(&xhci->op_regs->status);
290 val |= STS_FATAL;
291 writel(val, &xhci->op_regs->status);
292
293 /* Now zero the registers, and brace for impact */
294 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
295 if (upper_32_bits(val))
296 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
297 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
298 if (upper_32_bits(val))
299 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
300
301 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
302 ARRAY_SIZE(xhci->run_regs->ir_set));
303
304 for (i = 0; i < intrs; i++) {
305 struct xhci_intr_reg __iomem *ir;
306
307 ir = &xhci->run_regs->ir_set[i];
308 val = xhci_read_64(xhci, &ir->erst_base);
309 if (upper_32_bits(val))
310 xhci_write_64(xhci, 0, &ir->erst_base);
311 val= xhci_read_64(xhci, &ir->erst_dequeue);
312 if (upper_32_bits(val))
313 xhci_write_64(xhci, 0, &ir->erst_dequeue);
314 }
315
316 /* Wait for the fault to appear. It will be cleared on reset */
317 err = xhci_handshake(&xhci->op_regs->status,
318 STS_FATAL, STS_FATAL,
319 XHCI_MAX_HALT_USEC);
320 if (!err)
321 xhci_info(xhci, "Fault detected\n");
322}
323
324static int xhci_enable_interrupter(struct xhci_interrupter *ir)
325{
326 u32 iman;
327
328 if (!ir || !ir->ir_set)
329 return -EINVAL;
330
331 iman = readl(&ir->ir_set->irq_pending);
332 writel(ER_IRQ_ENABLE(iman), &ir->ir_set->irq_pending);
333
334 return 0;
335}
336
337static int xhci_disable_interrupter(struct xhci_interrupter *ir)
338{
339 u32 iman;
340
341 if (!ir || !ir->ir_set)
342 return -EINVAL;
343
344 iman = readl(&ir->ir_set->irq_pending);
345 writel(ER_IRQ_DISABLE(iman), &ir->ir_set->irq_pending);
346
347 return 0;
348}
349
350/* interrupt moderation interval imod_interval in nanoseconds */
351int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
352 u32 imod_interval)
353{
354 u32 imod;
355
356 if (!ir || !ir->ir_set || imod_interval > U16_MAX * 250)
357 return -EINVAL;
358
359 imod = readl(&ir->ir_set->irq_control);
360 imod &= ~ER_IRQ_INTERVAL_MASK;
361 imod |= (imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
362 writel(imod, &ir->ir_set->irq_control);
363
364 return 0;
365}
366
367static void compliance_mode_recovery(struct timer_list *t)
368{
369 struct xhci_hcd *xhci;
370 struct usb_hcd *hcd;
371 struct xhci_hub *rhub;
372 u32 temp;
373 int i;
374
375 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
376 rhub = &xhci->usb3_rhub;
377 hcd = rhub->hcd;
378
379 if (!hcd)
380 return;
381
382 for (i = 0; i < rhub->num_ports; i++) {
383 temp = readl(rhub->ports[i]->addr);
384 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
385 /*
386 * Compliance Mode Detected. Letting USB Core
387 * handle the Warm Reset
388 */
389 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
390 "Compliance mode detected->port %d",
391 i + 1);
392 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
393 "Attempting compliance mode recovery");
394
395 if (hcd->state == HC_STATE_SUSPENDED)
396 usb_hcd_resume_root_hub(hcd);
397
398 usb_hcd_poll_rh_status(hcd);
399 }
400 }
401
402 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
403 mod_timer(&xhci->comp_mode_recovery_timer,
404 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
405}
406
407/*
408 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
409 * that causes ports behind that hardware to enter compliance mode sometimes.
410 * The quirk creates a timer that polls every 2 seconds the link state of
411 * each host controller's port and recovers it by issuing a Warm reset
412 * if Compliance mode is detected, otherwise the port will become "dead" (no
413 * device connections or disconnections will be detected anymore). Becasue no
414 * status event is generated when entering compliance mode (per xhci spec),
415 * this quirk is needed on systems that have the failing hardware installed.
416 */
417static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
418{
419 xhci->port_status_u0 = 0;
420 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
421 0);
422 xhci->comp_mode_recovery_timer.expires = jiffies +
423 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
424
425 add_timer(&xhci->comp_mode_recovery_timer);
426 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
427 "Compliance mode recovery timer initialized");
428}
429
430/*
431 * This function identifies the systems that have installed the SN65LVPE502CP
432 * USB3.0 re-driver and that need the Compliance Mode Quirk.
433 * Systems:
434 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
435 */
436static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
437{
438 const char *dmi_product_name, *dmi_sys_vendor;
439
440 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
441 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
442 if (!dmi_product_name || !dmi_sys_vendor)
443 return false;
444
445 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
446 return false;
447
448 if (strstr(dmi_product_name, "Z420") ||
449 strstr(dmi_product_name, "Z620") ||
450 strstr(dmi_product_name, "Z820") ||
451 strstr(dmi_product_name, "Z1 Workstation"))
452 return true;
453
454 return false;
455}
456
457static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
458{
459 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
460}
461
462
463/*
464 * Initialize memory for HCD and xHC (one-time init).
465 *
466 * Program the PAGESIZE register, initialize the device context array, create
467 * device contexts (?), set up a command ring segment (or two?), create event
468 * ring (one for now).
469 */
470static int xhci_init(struct usb_hcd *hcd)
471{
472 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
473 int retval;
474
475 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
476 spin_lock_init(&xhci->lock);
477
478 retval = xhci_mem_init(xhci, GFP_KERNEL);
479 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
480
481 /* Initializing Compliance Mode Recovery Data If Needed */
482 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
483 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
484 compliance_mode_recovery_timer_init(xhci);
485 }
486
487 return retval;
488}
489
490/*-------------------------------------------------------------------------*/
491
492static int xhci_run_finished(struct xhci_hcd *xhci)
493{
494 struct xhci_interrupter *ir = xhci->interrupters[0];
495 unsigned long flags;
496 u32 temp;
497
498 /*
499 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
500 * Protect the short window before host is running with a lock
501 */
502 spin_lock_irqsave(&xhci->lock, flags);
503
504 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
505 temp = readl(&xhci->op_regs->command);
506 temp |= (CMD_EIE);
507 writel(temp, &xhci->op_regs->command);
508
509 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
510 xhci_enable_interrupter(ir);
511
512 if (xhci_start(xhci)) {
513 xhci_halt(xhci);
514 spin_unlock_irqrestore(&xhci->lock, flags);
515 return -ENODEV;
516 }
517
518 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
519
520 if (xhci->quirks & XHCI_NEC_HOST)
521 xhci_ring_cmd_db(xhci);
522
523 spin_unlock_irqrestore(&xhci->lock, flags);
524
525 return 0;
526}
527
528/*
529 * Start the HC after it was halted.
530 *
531 * This function is called by the USB core when the HC driver is added.
532 * Its opposite is xhci_stop().
533 *
534 * xhci_init() must be called once before this function can be called.
535 * Reset the HC, enable device slot contexts, program DCBAAP, and
536 * set command ring pointer and event ring pointer.
537 *
538 * Setup MSI-X vectors and enable interrupts.
539 */
540int xhci_run(struct usb_hcd *hcd)
541{
542 u64 temp_64;
543 int ret;
544 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
545 struct xhci_interrupter *ir = xhci->interrupters[0];
546 /* Start the xHCI host controller running only after the USB 2.0 roothub
547 * is setup.
548 */
549
550 hcd->uses_new_polling = 1;
551 if (hcd->msi_enabled)
552 ir->ip_autoclear = true;
553
554 if (!usb_hcd_is_primary_hcd(hcd))
555 return xhci_run_finished(xhci);
556
557 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
558
559 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
560 temp_64 &= ERST_PTR_MASK;
561 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
562 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
563
564 xhci_set_interrupter_moderation(ir, xhci->imod_interval);
565
566 if (xhci->quirks & XHCI_NEC_HOST) {
567 struct xhci_command *command;
568
569 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
570 if (!command)
571 return -ENOMEM;
572
573 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
574 TRB_TYPE(TRB_NEC_GET_FW));
575 if (ret)
576 xhci_free_command(xhci, command);
577 }
578 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
579 "Finished %s for main hcd", __func__);
580
581 xhci_create_dbc_dev(xhci);
582
583 xhci_debugfs_init(xhci);
584
585 if (xhci_has_one_roothub(xhci))
586 return xhci_run_finished(xhci);
587
588 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
589
590 return 0;
591}
592EXPORT_SYMBOL_GPL(xhci_run);
593
594/*
595 * Stop xHCI driver.
596 *
597 * This function is called by the USB core when the HC driver is removed.
598 * Its opposite is xhci_run().
599 *
600 * Disable device contexts, disable IRQs, and quiesce the HC.
601 * Reset the HC, finish any completed transactions, and cleanup memory.
602 */
603void xhci_stop(struct usb_hcd *hcd)
604{
605 u32 temp;
606 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
607 struct xhci_interrupter *ir = xhci->interrupters[0];
608
609 mutex_lock(&xhci->mutex);
610
611 /* Only halt host and free memory after both hcds are removed */
612 if (!usb_hcd_is_primary_hcd(hcd)) {
613 mutex_unlock(&xhci->mutex);
614 return;
615 }
616
617 xhci_remove_dbc_dev(xhci);
618
619 spin_lock_irq(&xhci->lock);
620 xhci->xhc_state |= XHCI_STATE_HALTED;
621 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
622 xhci_halt(xhci);
623 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
624 spin_unlock_irq(&xhci->lock);
625
626 /* Deleting Compliance Mode Recovery Timer */
627 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
628 (!(xhci_all_ports_seen_u0(xhci)))) {
629 del_timer_sync(&xhci->comp_mode_recovery_timer);
630 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
631 "%s: compliance mode recovery timer deleted",
632 __func__);
633 }
634
635 if (xhci->quirks & XHCI_AMD_PLL_FIX)
636 usb_amd_dev_put();
637
638 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
639 "// Disabling event ring interrupts");
640 temp = readl(&xhci->op_regs->status);
641 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
642 xhci_disable_interrupter(ir);
643
644 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
645 xhci_mem_cleanup(xhci);
646 xhci_debugfs_exit(xhci);
647 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
648 "xhci_stop completed - status = %x",
649 readl(&xhci->op_regs->status));
650 mutex_unlock(&xhci->mutex);
651}
652EXPORT_SYMBOL_GPL(xhci_stop);
653
654/*
655 * Shutdown HC (not bus-specific)
656 *
657 * This is called when the machine is rebooting or halting. We assume that the
658 * machine will be powered off, and the HC's internal state will be reset.
659 * Don't bother to free memory.
660 *
661 * This will only ever be called with the main usb_hcd (the USB3 roothub).
662 */
663void xhci_shutdown(struct usb_hcd *hcd)
664{
665 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
666
667 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
668 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
669
670 /* Don't poll the roothubs after shutdown. */
671 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
672 __func__, hcd->self.busnum);
673 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
674 del_timer_sync(&hcd->rh_timer);
675
676 if (xhci->shared_hcd) {
677 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
678 del_timer_sync(&xhci->shared_hcd->rh_timer);
679 }
680
681 spin_lock_irq(&xhci->lock);
682 xhci_halt(xhci);
683
684 /*
685 * Workaround for spurious wakeps at shutdown with HSW, and for boot
686 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
687 */
688 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
689 xhci->quirks & XHCI_RESET_TO_DEFAULT)
690 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
691
692 spin_unlock_irq(&xhci->lock);
693
694 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
695 "xhci_shutdown completed - status = %x",
696 readl(&xhci->op_regs->status));
697}
698EXPORT_SYMBOL_GPL(xhci_shutdown);
699
700#ifdef CONFIG_PM
701static void xhci_save_registers(struct xhci_hcd *xhci)
702{
703 struct xhci_interrupter *ir;
704 unsigned int i;
705
706 xhci->s3.command = readl(&xhci->op_regs->command);
707 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
708 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
709 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
710
711 /* save both primary and all secondary interrupters */
712 /* fixme, shold we lock to prevent race with remove secondary interrupter? */
713 for (i = 0; i < xhci->max_interrupters; i++) {
714 ir = xhci->interrupters[i];
715 if (!ir)
716 continue;
717
718 ir->s3_erst_size = readl(&ir->ir_set->erst_size);
719 ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
720 ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
721 ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);
722 ir->s3_irq_control = readl(&ir->ir_set->irq_control);
723 }
724}
725
726static void xhci_restore_registers(struct xhci_hcd *xhci)
727{
728 struct xhci_interrupter *ir;
729 unsigned int i;
730
731 writel(xhci->s3.command, &xhci->op_regs->command);
732 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
733 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
734 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
735
736 /* FIXME should we lock to protect against freeing of interrupters */
737 for (i = 0; i < xhci->max_interrupters; i++) {
738 ir = xhci->interrupters[i];
739 if (!ir)
740 continue;
741
742 writel(ir->s3_erst_size, &ir->ir_set->erst_size);
743 xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
744 xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
745 writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);
746 writel(ir->s3_irq_control, &ir->ir_set->irq_control);
747 }
748}
749
750static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
751{
752 u64 val_64;
753
754 /* step 2: initialize command ring buffer */
755 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
756 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
757 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
758 xhci->cmd_ring->dequeue) &
759 (u64) ~CMD_RING_RSVD_BITS) |
760 xhci->cmd_ring->cycle_state;
761 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
762 "// Setting command ring address to 0x%llx",
763 (long unsigned long) val_64);
764 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
765}
766
767/*
768 * The whole command ring must be cleared to zero when we suspend the host.
769 *
770 * The host doesn't save the command ring pointer in the suspend well, so we
771 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
772 * aligned, because of the reserved bits in the command ring dequeue pointer
773 * register. Therefore, we can't just set the dequeue pointer back in the
774 * middle of the ring (TRBs are 16-byte aligned).
775 */
776static void xhci_clear_command_ring(struct xhci_hcd *xhci)
777{
778 struct xhci_ring *ring;
779 struct xhci_segment *seg;
780
781 ring = xhci->cmd_ring;
782 xhci_for_each_ring_seg(ring->first_seg, seg) {
783 /* erase all TRBs before the link */
784 memset(seg->trbs, 0, sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
785 /* clear link cycle bit */
786 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= cpu_to_le32(~TRB_CYCLE);
787 }
788
789 xhci_initialize_ring_info(ring);
790 /*
791 * Reset the hardware dequeue pointer.
792 * Yes, this will need to be re-written after resume, but we're paranoid
793 * and want to make sure the hardware doesn't access bogus memory
794 * because, say, the BIOS or an SMI started the host without changing
795 * the command ring pointers.
796 */
797 xhci_set_cmd_ring_deq(xhci);
798}
799
800/*
801 * Disable port wake bits if do_wakeup is not set.
802 *
803 * Also clear a possible internal port wake state left hanging for ports that
804 * detected termination but never successfully enumerated (trained to 0U).
805 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
806 * at enumeration clears this wake, force one here as well for unconnected ports
807 */
808
809static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
810 struct xhci_hub *rhub,
811 bool do_wakeup)
812{
813 unsigned long flags;
814 u32 t1, t2, portsc;
815 int i;
816
817 spin_lock_irqsave(&xhci->lock, flags);
818
819 for (i = 0; i < rhub->num_ports; i++) {
820 portsc = readl(rhub->ports[i]->addr);
821 t1 = xhci_port_state_to_neutral(portsc);
822 t2 = t1;
823
824 /* clear wake bits if do_wake is not set */
825 if (!do_wakeup)
826 t2 &= ~PORT_WAKE_BITS;
827
828 /* Don't touch csc bit if connected or connect change is set */
829 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
830 t2 |= PORT_CSC;
831
832 if (t1 != t2) {
833 writel(t2, rhub->ports[i]->addr);
834 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
835 rhub->hcd->self.busnum, i + 1, portsc, t2);
836 }
837 }
838 spin_unlock_irqrestore(&xhci->lock, flags);
839}
840
841static bool xhci_pending_portevent(struct xhci_hcd *xhci)
842{
843 struct xhci_port **ports;
844 int port_index;
845 u32 status;
846 u32 portsc;
847
848 status = readl(&xhci->op_regs->status);
849 if (status & STS_EINT)
850 return true;
851 /*
852 * Checking STS_EINT is not enough as there is a lag between a change
853 * bit being set and the Port Status Change Event that it generated
854 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
855 */
856
857 port_index = xhci->usb2_rhub.num_ports;
858 ports = xhci->usb2_rhub.ports;
859 while (port_index--) {
860 portsc = readl(ports[port_index]->addr);
861 if (portsc & PORT_CHANGE_MASK ||
862 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
863 return true;
864 }
865 port_index = xhci->usb3_rhub.num_ports;
866 ports = xhci->usb3_rhub.ports;
867 while (port_index--) {
868 portsc = readl(ports[port_index]->addr);
869 if (portsc & (PORT_CHANGE_MASK | PORT_CAS) ||
870 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
871 return true;
872 }
873 return false;
874}
875
876/*
877 * Stop HC (not bus-specific)
878 *
879 * This is called when the machine transition into S3/S4 mode.
880 *
881 */
882int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
883{
884 int rc = 0;
885 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
886 struct usb_hcd *hcd = xhci_to_hcd(xhci);
887 u32 command;
888 u32 res;
889
890 if (!hcd->state)
891 return 0;
892
893 if (hcd->state != HC_STATE_SUSPENDED ||
894 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
895 return -EINVAL;
896
897 /* Clear root port wake on bits if wakeup not allowed. */
898 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
899 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
900
901 if (!HCD_HW_ACCESSIBLE(hcd))
902 return 0;
903
904 xhci_dbc_suspend(xhci);
905
906 /* Don't poll the roothubs on bus suspend. */
907 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
908 __func__, hcd->self.busnum);
909 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
910 del_timer_sync(&hcd->rh_timer);
911 if (xhci->shared_hcd) {
912 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
913 del_timer_sync(&xhci->shared_hcd->rh_timer);
914 }
915
916 if (xhci->quirks & XHCI_SUSPEND_DELAY)
917 usleep_range(1000, 1500);
918
919 spin_lock_irq(&xhci->lock);
920 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
921 if (xhci->shared_hcd)
922 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
923 /* step 1: stop endpoint */
924 /* skipped assuming that port suspend has done */
925
926 /* step 2: clear Run/Stop bit */
927 command = readl(&xhci->op_regs->command);
928 command &= ~CMD_RUN;
929 writel(command, &xhci->op_regs->command);
930
931 /* Some chips from Fresco Logic need an extraordinary delay */
932 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
933
934 if (xhci_handshake(&xhci->op_regs->status,
935 STS_HALT, STS_HALT, delay)) {
936 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
937 spin_unlock_irq(&xhci->lock);
938 return -ETIMEDOUT;
939 }
940 xhci_clear_command_ring(xhci);
941
942 /* step 3: save registers */
943 xhci_save_registers(xhci);
944
945 /* step 4: set CSS flag */
946 command = readl(&xhci->op_regs->command);
947 command |= CMD_CSS;
948 writel(command, &xhci->op_regs->command);
949 xhci->broken_suspend = 0;
950 if (xhci_handshake(&xhci->op_regs->status,
951 STS_SAVE, 0, 20 * 1000)) {
952 /*
953 * AMD SNPS xHC 3.0 occasionally does not clear the
954 * SSS bit of USBSTS and when driver tries to poll
955 * to see if the xHC clears BIT(8) which never happens
956 * and driver assumes that controller is not responding
957 * and times out. To workaround this, its good to check
958 * if SRE and HCE bits are not set (as per xhci
959 * Section 5.4.2) and bypass the timeout.
960 */
961 res = readl(&xhci->op_regs->status);
962 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
963 (((res & STS_SRE) == 0) &&
964 ((res & STS_HCE) == 0))) {
965 xhci->broken_suspend = 1;
966 } else {
967 xhci_warn(xhci, "WARN: xHC save state timeout\n");
968 spin_unlock_irq(&xhci->lock);
969 return -ETIMEDOUT;
970 }
971 }
972 spin_unlock_irq(&xhci->lock);
973
974 /*
975 * Deleting Compliance Mode Recovery Timer because the xHCI Host
976 * is about to be suspended.
977 */
978 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
979 (!(xhci_all_ports_seen_u0(xhci)))) {
980 del_timer_sync(&xhci->comp_mode_recovery_timer);
981 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
982 "%s: compliance mode recovery timer deleted",
983 __func__);
984 }
985
986 return rc;
987}
988EXPORT_SYMBOL_GPL(xhci_suspend);
989
990/*
991 * start xHC (not bus-specific)
992 *
993 * This is called when the machine transition from S3/S4 mode.
994 *
995 */
996int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg)
997{
998 bool hibernated = (msg.event == PM_EVENT_RESTORE);
999 u32 command, temp = 0;
1000 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1001 int retval = 0;
1002 bool comp_timer_running = false;
1003 bool pending_portevent = false;
1004 bool suspended_usb3_devs = false;
1005 bool reinit_xhc = false;
1006
1007 if (!hcd->state)
1008 return 0;
1009
1010 /* Wait a bit if either of the roothubs need to settle from the
1011 * transition into bus suspend.
1012 */
1013
1014 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1015 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1016 msleep(100);
1017
1018 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1019 if (xhci->shared_hcd)
1020 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1021
1022 spin_lock_irq(&xhci->lock);
1023
1024 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1025 reinit_xhc = true;
1026
1027 if (!reinit_xhc) {
1028 /*
1029 * Some controllers might lose power during suspend, so wait
1030 * for controller not ready bit to clear, just as in xHC init.
1031 */
1032 retval = xhci_handshake(&xhci->op_regs->status,
1033 STS_CNR, 0, 10 * 1000 * 1000);
1034 if (retval) {
1035 xhci_warn(xhci, "Controller not ready at resume %d\n",
1036 retval);
1037 spin_unlock_irq(&xhci->lock);
1038 return retval;
1039 }
1040 /* step 1: restore register */
1041 xhci_restore_registers(xhci);
1042 /* step 2: initialize command ring buffer */
1043 xhci_set_cmd_ring_deq(xhci);
1044 /* step 3: restore state and start state*/
1045 /* step 3: set CRS flag */
1046 command = readl(&xhci->op_regs->command);
1047 command |= CMD_CRS;
1048 writel(command, &xhci->op_regs->command);
1049 /*
1050 * Some controllers take up to 55+ ms to complete the controller
1051 * restore so setting the timeout to 100ms. Xhci specification
1052 * doesn't mention any timeout value.
1053 */
1054 if (xhci_handshake(&xhci->op_regs->status,
1055 STS_RESTORE, 0, 100 * 1000)) {
1056 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1057 spin_unlock_irq(&xhci->lock);
1058 return -ETIMEDOUT;
1059 }
1060 }
1061
1062 temp = readl(&xhci->op_regs->status);
1063
1064 /* re-initialize the HC on Restore Error, or Host Controller Error */
1065 if ((temp & (STS_SRE | STS_HCE)) &&
1066 !(xhci->xhc_state & XHCI_STATE_REMOVING)) {
1067 reinit_xhc = true;
1068 if (!xhci->broken_suspend)
1069 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1070 }
1071
1072 if (reinit_xhc) {
1073 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1074 !(xhci_all_ports_seen_u0(xhci))) {
1075 del_timer_sync(&xhci->comp_mode_recovery_timer);
1076 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1077 "Compliance Mode Recovery Timer deleted!");
1078 }
1079
1080 /* Let the USB core know _both_ roothubs lost power. */
1081 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1082 if (xhci->shared_hcd)
1083 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1084
1085 xhci_dbg(xhci, "Stop HCD\n");
1086 xhci_halt(xhci);
1087 xhci_zero_64b_regs(xhci);
1088 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1089 spin_unlock_irq(&xhci->lock);
1090 if (retval)
1091 return retval;
1092
1093 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1094 temp = readl(&xhci->op_regs->status);
1095 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1096 xhci_disable_interrupter(xhci->interrupters[0]);
1097
1098 xhci_dbg(xhci, "cleaning up memory\n");
1099 xhci_mem_cleanup(xhci);
1100 xhci_debugfs_exit(xhci);
1101 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1102 readl(&xhci->op_regs->status));
1103
1104 /* USB core calls the PCI reinit and start functions twice:
1105 * first with the primary HCD, and then with the secondary HCD.
1106 * If we don't do the same, the host will never be started.
1107 */
1108 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1109 retval = xhci_init(hcd);
1110 if (retval)
1111 return retval;
1112 comp_timer_running = true;
1113
1114 xhci_dbg(xhci, "Start the primary HCD\n");
1115 retval = xhci_run(hcd);
1116 if (!retval && xhci->shared_hcd) {
1117 xhci_dbg(xhci, "Start the secondary HCD\n");
1118 retval = xhci_run(xhci->shared_hcd);
1119 }
1120 if (retval)
1121 return retval;
1122 /*
1123 * Resume roothubs unconditionally as PORTSC change bits are not
1124 * immediately visible after xHC reset
1125 */
1126 hcd->state = HC_STATE_SUSPENDED;
1127
1128 if (xhci->shared_hcd) {
1129 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1130 usb_hcd_resume_root_hub(xhci->shared_hcd);
1131 }
1132 usb_hcd_resume_root_hub(hcd);
1133
1134 goto done;
1135 }
1136
1137 /* step 4: set Run/Stop bit */
1138 command = readl(&xhci->op_regs->command);
1139 command |= CMD_RUN;
1140 writel(command, &xhci->op_regs->command);
1141 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1142 0, 250 * 1000);
1143
1144 /* step 5: walk topology and initialize portsc,
1145 * portpmsc and portli
1146 */
1147 /* this is done in bus_resume */
1148
1149 /* step 6: restart each of the previously
1150 * Running endpoints by ringing their doorbells
1151 */
1152
1153 spin_unlock_irq(&xhci->lock);
1154
1155 xhci_dbc_resume(xhci);
1156
1157 if (retval == 0) {
1158 /*
1159 * Resume roothubs only if there are pending events.
1160 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1161 * the first wake signalling failed, give it that chance if
1162 * there are suspended USB 3 devices.
1163 */
1164 if (xhci->usb3_rhub.bus_state.suspended_ports ||
1165 xhci->usb3_rhub.bus_state.bus_suspended)
1166 suspended_usb3_devs = true;
1167
1168 pending_portevent = xhci_pending_portevent(xhci);
1169
1170 if (suspended_usb3_devs && !pending_portevent &&
1171 msg.event == PM_EVENT_AUTO_RESUME) {
1172 msleep(120);
1173 pending_portevent = xhci_pending_portevent(xhci);
1174 }
1175
1176 if (pending_portevent) {
1177 if (xhci->shared_hcd)
1178 usb_hcd_resume_root_hub(xhci->shared_hcd);
1179 usb_hcd_resume_root_hub(hcd);
1180 }
1181 }
1182done:
1183 /*
1184 * If system is subject to the Quirk, Compliance Mode Timer needs to
1185 * be re-initialized Always after a system resume. Ports are subject
1186 * to suffer the Compliance Mode issue again. It doesn't matter if
1187 * ports have entered previously to U0 before system's suspension.
1188 */
1189 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1190 compliance_mode_recovery_timer_init(xhci);
1191
1192 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1193 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1194
1195 /* Re-enable port polling. */
1196 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1197 __func__, hcd->self.busnum);
1198 if (xhci->shared_hcd) {
1199 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1200 usb_hcd_poll_rh_status(xhci->shared_hcd);
1201 }
1202 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1203 usb_hcd_poll_rh_status(hcd);
1204
1205 return retval;
1206}
1207EXPORT_SYMBOL_GPL(xhci_resume);
1208#endif /* CONFIG_PM */
1209
1210/*-------------------------------------------------------------------------*/
1211
1212static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1213{
1214 void *temp;
1215 int ret = 0;
1216 unsigned int buf_len;
1217 enum dma_data_direction dir;
1218
1219 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1220 buf_len = urb->transfer_buffer_length;
1221
1222 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1223 dev_to_node(hcd->self.sysdev));
1224 if (!temp)
1225 return -ENOMEM;
1226
1227 if (usb_urb_dir_out(urb))
1228 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1229 temp, buf_len, 0);
1230
1231 urb->transfer_buffer = temp;
1232 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1233 urb->transfer_buffer,
1234 urb->transfer_buffer_length,
1235 dir);
1236
1237 if (dma_mapping_error(hcd->self.sysdev,
1238 urb->transfer_dma)) {
1239 ret = -EAGAIN;
1240 kfree(temp);
1241 } else {
1242 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1243 }
1244
1245 return ret;
1246}
1247
1248static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1249 struct urb *urb)
1250{
1251 bool ret = false;
1252 unsigned int i;
1253 unsigned int len = 0;
1254 unsigned int trb_size;
1255 unsigned int max_pkt;
1256 struct scatterlist *sg;
1257 struct scatterlist *tail_sg;
1258
1259 tail_sg = urb->sg;
1260 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1261
1262 if (!urb->num_sgs)
1263 return ret;
1264
1265 if (urb->dev->speed >= USB_SPEED_SUPER)
1266 trb_size = TRB_CACHE_SIZE_SS;
1267 else
1268 trb_size = TRB_CACHE_SIZE_HS;
1269
1270 if (urb->transfer_buffer_length != 0 &&
1271 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1272 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1273 len = len + sg->length;
1274 if (i > trb_size - 2) {
1275 len = len - tail_sg->length;
1276 if (len < max_pkt) {
1277 ret = true;
1278 break;
1279 }
1280
1281 tail_sg = sg_next(tail_sg);
1282 }
1283 }
1284 }
1285 return ret;
1286}
1287
1288static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1289{
1290 unsigned int len;
1291 unsigned int buf_len;
1292 enum dma_data_direction dir;
1293
1294 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1295
1296 buf_len = urb->transfer_buffer_length;
1297
1298 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1299 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1300 dma_unmap_single(hcd->self.sysdev,
1301 urb->transfer_dma,
1302 urb->transfer_buffer_length,
1303 dir);
1304
1305 if (usb_urb_dir_in(urb)) {
1306 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1307 urb->transfer_buffer,
1308 buf_len,
1309 0);
1310 if (len != buf_len) {
1311 xhci_dbg(hcd_to_xhci(hcd),
1312 "Copy from tmp buf to urb sg list failed\n");
1313 urb->actual_length = len;
1314 }
1315 }
1316 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1317 kfree(urb->transfer_buffer);
1318 urb->transfer_buffer = NULL;
1319}
1320
1321/*
1322 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1323 * we'll copy the actual data into the TRB address register. This is limited to
1324 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1325 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1326 */
1327static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1328 gfp_t mem_flags)
1329{
1330 struct xhci_hcd *xhci;
1331
1332 xhci = hcd_to_xhci(hcd);
1333
1334 if (xhci_urb_suitable_for_idt(urb))
1335 return 0;
1336
1337 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1338 if (xhci_urb_temp_buffer_required(hcd, urb))
1339 return xhci_map_temp_buffer(hcd, urb);
1340 }
1341 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1342}
1343
1344static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1345{
1346 struct xhci_hcd *xhci;
1347 bool unmap_temp_buf = false;
1348
1349 xhci = hcd_to_xhci(hcd);
1350
1351 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1352 unmap_temp_buf = true;
1353
1354 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1355 xhci_unmap_temp_buf(hcd, urb);
1356 else
1357 usb_hcd_unmap_urb_for_dma(hcd, urb);
1358}
1359
1360/**
1361 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1362 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1363 * value to right shift 1 for the bitmask.
1364 *
1365 * Index = (epnum * 2) + direction - 1,
1366 * where direction = 0 for OUT, 1 for IN.
1367 * For control endpoints, the IN index is used (OUT index is unused), so
1368 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1369 */
1370unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1371{
1372 unsigned int index;
1373 if (usb_endpoint_xfer_control(desc))
1374 index = (unsigned int) (usb_endpoint_num(desc)*2);
1375 else
1376 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1377 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1378 return index;
1379}
1380EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1381
1382/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1383 * address from the XHCI endpoint index.
1384 */
1385static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1386{
1387 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1388 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1389 return direction | number;
1390}
1391
1392/* Find the flag for this endpoint (for use in the control context). Use the
1393 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1394 * bit 1, etc.
1395 */
1396static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1397{
1398 return 1 << (xhci_get_endpoint_index(desc) + 1);
1399}
1400
1401/* Compute the last valid endpoint context index. Basically, this is the
1402 * endpoint index plus one. For slot contexts with more than valid endpoint,
1403 * we find the most significant bit set in the added contexts flags.
1404 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1405 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1406 */
1407unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1408{
1409 return fls(added_ctxs) - 1;
1410}
1411
1412/* Returns 1 if the arguments are OK;
1413 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1414 */
1415static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1416 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1417 const char *func) {
1418 struct xhci_hcd *xhci;
1419 struct xhci_virt_device *virt_dev;
1420
1421 if (!hcd || (check_ep && !ep) || !udev) {
1422 pr_debug("xHCI %s called with invalid args\n", func);
1423 return -EINVAL;
1424 }
1425 if (!udev->parent) {
1426 pr_debug("xHCI %s called for root hub\n", func);
1427 return 0;
1428 }
1429
1430 xhci = hcd_to_xhci(hcd);
1431 if (check_virt_dev) {
1432 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1433 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1434 func);
1435 return -EINVAL;
1436 }
1437
1438 virt_dev = xhci->devs[udev->slot_id];
1439 if (virt_dev->udev != udev) {
1440 xhci_dbg(xhci, "xHCI %s called with udev and "
1441 "virt_dev does not match\n", func);
1442 return -EINVAL;
1443 }
1444 }
1445
1446 if (xhci->xhc_state & XHCI_STATE_HALTED)
1447 return -ENODEV;
1448
1449 return 1;
1450}
1451
1452static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1453 struct usb_device *udev, struct xhci_command *command,
1454 bool ctx_change, bool must_succeed);
1455
1456/*
1457 * Full speed devices may have a max packet size greater than 8 bytes, but the
1458 * USB core doesn't know that until it reads the first 8 bytes of the
1459 * descriptor. If the usb_device's max packet size changes after that point,
1460 * we need to issue an evaluate context command and wait on it.
1461 */
1462static int xhci_check_ep0_maxpacket(struct xhci_hcd *xhci, struct xhci_virt_device *vdev)
1463{
1464 struct xhci_input_control_ctx *ctrl_ctx;
1465 struct xhci_ep_ctx *ep_ctx;
1466 struct xhci_command *command;
1467 int max_packet_size;
1468 int hw_max_packet_size;
1469 int ret = 0;
1470
1471 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, 0);
1472 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1473 max_packet_size = usb_endpoint_maxp(&vdev->udev->ep0.desc);
1474
1475 if (hw_max_packet_size == max_packet_size)
1476 return 0;
1477
1478 switch (max_packet_size) {
1479 case 8: case 16: case 32: case 64: case 9:
1480 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1481 "Max Packet Size for ep 0 changed.");
1482 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1483 "Max packet size in usb_device = %d",
1484 max_packet_size);
1485 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1486 "Max packet size in xHCI HW = %d",
1487 hw_max_packet_size);
1488 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1489 "Issuing evaluate context command.");
1490
1491 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1492 if (!command)
1493 return -ENOMEM;
1494
1495 command->in_ctx = vdev->in_ctx;
1496 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1497 if (!ctrl_ctx) {
1498 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1499 __func__);
1500 ret = -ENOMEM;
1501 break;
1502 }
1503 /* Set up the modified control endpoint 0 */
1504 xhci_endpoint_copy(xhci, vdev->in_ctx, vdev->out_ctx, 0);
1505
1506 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, 0);
1507 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1508 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1509 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1510
1511 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1512 ctrl_ctx->drop_flags = 0;
1513
1514 ret = xhci_configure_endpoint(xhci, vdev->udev, command,
1515 true, false);
1516 /* Clean up the input context for later use by bandwidth functions */
1517 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1518 break;
1519 default:
1520 dev_dbg(&vdev->udev->dev, "incorrect max packet size %d for ep0\n",
1521 max_packet_size);
1522 return -EINVAL;
1523 }
1524
1525 kfree(command->completion);
1526 kfree(command);
1527
1528 return ret;
1529}
1530
1531/*
1532 * non-error returns are a promise to giveback() the urb later
1533 * we drop ownership so next owner (or urb unlink) can get it
1534 */
1535static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1536{
1537 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1538 unsigned long flags;
1539 int ret = 0;
1540 unsigned int slot_id, ep_index;
1541 unsigned int *ep_state;
1542 struct urb_priv *urb_priv;
1543 int num_tds;
1544
1545 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1546
1547 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1548 num_tds = urb->number_of_packets;
1549 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1550 urb->transfer_buffer_length > 0 &&
1551 urb->transfer_flags & URB_ZERO_PACKET &&
1552 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1553 num_tds = 2;
1554 else
1555 num_tds = 1;
1556
1557 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1558 if (!urb_priv)
1559 return -ENOMEM;
1560
1561 urb_priv->num_tds = num_tds;
1562 urb_priv->num_tds_done = 0;
1563 urb->hcpriv = urb_priv;
1564
1565 trace_xhci_urb_enqueue(urb);
1566
1567 spin_lock_irqsave(&xhci->lock, flags);
1568
1569 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1570 true, true, __func__);
1571 if (ret <= 0) {
1572 ret = ret ? ret : -EINVAL;
1573 goto free_priv;
1574 }
1575
1576 slot_id = urb->dev->slot_id;
1577
1578 if (!HCD_HW_ACCESSIBLE(hcd)) {
1579 ret = -ESHUTDOWN;
1580 goto free_priv;
1581 }
1582
1583 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1584 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1585 ret = -ENODEV;
1586 goto free_priv;
1587 }
1588
1589 if (xhci->xhc_state & XHCI_STATE_DYING) {
1590 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1591 urb->ep->desc.bEndpointAddress, urb);
1592 ret = -ESHUTDOWN;
1593 goto free_priv;
1594 }
1595
1596 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1597
1598 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1599 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1600 *ep_state);
1601 ret = -EINVAL;
1602 goto free_priv;
1603 }
1604 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1605 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1606 ret = -EINVAL;
1607 goto free_priv;
1608 }
1609
1610 switch (usb_endpoint_type(&urb->ep->desc)) {
1611
1612 case USB_ENDPOINT_XFER_CONTROL:
1613 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1614 slot_id, ep_index);
1615 break;
1616 case USB_ENDPOINT_XFER_BULK:
1617 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1618 slot_id, ep_index);
1619 break;
1620 case USB_ENDPOINT_XFER_INT:
1621 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1622 slot_id, ep_index);
1623 break;
1624 case USB_ENDPOINT_XFER_ISOC:
1625 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1626 slot_id, ep_index);
1627 }
1628
1629 if (ret) {
1630free_priv:
1631 xhci_urb_free_priv(urb_priv);
1632 urb->hcpriv = NULL;
1633 }
1634 spin_unlock_irqrestore(&xhci->lock, flags);
1635 return ret;
1636}
1637
1638/*
1639 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1640 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1641 * should pick up where it left off in the TD, unless a Set Transfer Ring
1642 * Dequeue Pointer is issued.
1643 *
1644 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1645 * the ring. Since the ring is a contiguous structure, they can't be physically
1646 * removed. Instead, there are two options:
1647 *
1648 * 1) If the HC is in the middle of processing the URB to be canceled, we
1649 * simply move the ring's dequeue pointer past those TRBs using the Set
1650 * Transfer Ring Dequeue Pointer command. This will be the common case,
1651 * when drivers timeout on the last submitted URB and attempt to cancel.
1652 *
1653 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1654 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1655 * HC will need to invalidate the any TRBs it has cached after the stop
1656 * endpoint command, as noted in the xHCI 0.95 errata.
1657 *
1658 * 3) The TD may have completed by the time the Stop Endpoint Command
1659 * completes, so software needs to handle that case too.
1660 *
1661 * This function should protect against the TD enqueueing code ringing the
1662 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1663 * It also needs to account for multiple cancellations on happening at the same
1664 * time for the same endpoint.
1665 *
1666 * Note that this function can be called in any context, or so says
1667 * usb_hcd_unlink_urb()
1668 */
1669static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1670{
1671 unsigned long flags;
1672 int ret, i;
1673 u32 temp;
1674 struct xhci_hcd *xhci;
1675 struct urb_priv *urb_priv;
1676 struct xhci_td *td;
1677 unsigned int ep_index;
1678 struct xhci_ring *ep_ring;
1679 struct xhci_virt_ep *ep;
1680 struct xhci_command *command;
1681 struct xhci_virt_device *vdev;
1682
1683 xhci = hcd_to_xhci(hcd);
1684 spin_lock_irqsave(&xhci->lock, flags);
1685
1686 trace_xhci_urb_dequeue(urb);
1687
1688 /* Make sure the URB hasn't completed or been unlinked already */
1689 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1690 if (ret)
1691 goto done;
1692
1693 /* give back URB now if we can't queue it for cancel */
1694 vdev = xhci->devs[urb->dev->slot_id];
1695 urb_priv = urb->hcpriv;
1696 if (!vdev || !urb_priv)
1697 goto err_giveback;
1698
1699 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1700 ep = &vdev->eps[ep_index];
1701 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1702 if (!ep || !ep_ring)
1703 goto err_giveback;
1704
1705 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1706 temp = readl(&xhci->op_regs->status);
1707 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1708 xhci_hc_died(xhci);
1709 goto done;
1710 }
1711
1712 /*
1713 * check ring is not re-allocated since URB was enqueued. If it is, then
1714 * make sure none of the ring related pointers in this URB private data
1715 * are touched, such as td_list, otherwise we overwrite freed data
1716 */
1717 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1718 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1719 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1720 td = &urb_priv->td[i];
1721 if (!list_empty(&td->cancelled_td_list))
1722 list_del_init(&td->cancelled_td_list);
1723 }
1724 goto err_giveback;
1725 }
1726
1727 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1728 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1729 "HC halted, freeing TD manually.");
1730 for (i = urb_priv->num_tds_done;
1731 i < urb_priv->num_tds;
1732 i++) {
1733 td = &urb_priv->td[i];
1734 if (!list_empty(&td->td_list))
1735 list_del_init(&td->td_list);
1736 if (!list_empty(&td->cancelled_td_list))
1737 list_del_init(&td->cancelled_td_list);
1738 }
1739 goto err_giveback;
1740 }
1741
1742 i = urb_priv->num_tds_done;
1743 if (i < urb_priv->num_tds)
1744 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1745 "Cancel URB %p, dev %s, ep 0x%x, "
1746 "starting at offset 0x%llx",
1747 urb, urb->dev->devpath,
1748 urb->ep->desc.bEndpointAddress,
1749 (unsigned long long) xhci_trb_virt_to_dma(
1750 urb_priv->td[i].start_seg,
1751 urb_priv->td[i].start_trb));
1752
1753 for (; i < urb_priv->num_tds; i++) {
1754 td = &urb_priv->td[i];
1755 /* TD can already be on cancelled list if ep halted on it */
1756 if (list_empty(&td->cancelled_td_list)) {
1757 td->cancel_status = TD_DIRTY;
1758 list_add_tail(&td->cancelled_td_list,
1759 &ep->cancelled_td_list);
1760 }
1761 }
1762
1763 /* These completion handlers will sort out cancelled TDs for us */
1764 if (ep->ep_state & (EP_STOP_CMD_PENDING | EP_HALTED | SET_DEQ_PENDING)) {
1765 xhci_dbg(xhci, "Not queuing Stop Endpoint on slot %d ep %d in state 0x%x\n",
1766 urb->dev->slot_id, ep_index, ep->ep_state);
1767 goto done;
1768 }
1769
1770 /* In this case no commands are pending but the endpoint is stopped */
1771 if (ep->ep_state & EP_CLEARING_TT) {
1772 /* and cancelled TDs can be given back right away */
1773 xhci_dbg(xhci, "Invalidating TDs instantly on slot %d ep %d in state 0x%x\n",
1774 urb->dev->slot_id, ep_index, ep->ep_state);
1775 xhci_process_cancelled_tds(ep);
1776 } else {
1777 /* Otherwise, queue a new Stop Endpoint command */
1778 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1779 if (!command) {
1780 ret = -ENOMEM;
1781 goto done;
1782 }
1783 ep->stop_time = jiffies;
1784 ep->ep_state |= EP_STOP_CMD_PENDING;
1785 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1786 ep_index, 0);
1787 xhci_ring_cmd_db(xhci);
1788 }
1789done:
1790 spin_unlock_irqrestore(&xhci->lock, flags);
1791 return ret;
1792
1793err_giveback:
1794 if (urb_priv)
1795 xhci_urb_free_priv(urb_priv);
1796 usb_hcd_unlink_urb_from_ep(hcd, urb);
1797 spin_unlock_irqrestore(&xhci->lock, flags);
1798 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1799 return ret;
1800}
1801
1802/* Drop an endpoint from a new bandwidth configuration for this device.
1803 * Only one call to this function is allowed per endpoint before
1804 * check_bandwidth() or reset_bandwidth() must be called.
1805 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1806 * add the endpoint to the schedule with possibly new parameters denoted by a
1807 * different endpoint descriptor in usb_host_endpoint.
1808 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1809 * not allowed.
1810 *
1811 * The USB core will not allow URBs to be queued to an endpoint that is being
1812 * disabled, so there's no need for mutual exclusion to protect
1813 * the xhci->devs[slot_id] structure.
1814 */
1815int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1816 struct usb_host_endpoint *ep)
1817{
1818 struct xhci_hcd *xhci;
1819 struct xhci_container_ctx *in_ctx, *out_ctx;
1820 struct xhci_input_control_ctx *ctrl_ctx;
1821 unsigned int ep_index;
1822 struct xhci_ep_ctx *ep_ctx;
1823 u32 drop_flag;
1824 u32 new_add_flags, new_drop_flags;
1825 int ret;
1826
1827 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1828 if (ret <= 0)
1829 return ret;
1830 xhci = hcd_to_xhci(hcd);
1831 if (xhci->xhc_state & XHCI_STATE_DYING)
1832 return -ENODEV;
1833
1834 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1835 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1836 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1837 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1838 __func__, drop_flag);
1839 return 0;
1840 }
1841
1842 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1843 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1844 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1845 if (!ctrl_ctx) {
1846 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1847 __func__);
1848 return 0;
1849 }
1850
1851 ep_index = xhci_get_endpoint_index(&ep->desc);
1852 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1853 /* If the HC already knows the endpoint is disabled,
1854 * or the HCD has noted it is disabled, ignore this request
1855 */
1856 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1857 le32_to_cpu(ctrl_ctx->drop_flags) &
1858 xhci_get_endpoint_flag(&ep->desc)) {
1859 /* Do not warn when called after a usb_device_reset */
1860 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1861 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1862 __func__, ep);
1863 return 0;
1864 }
1865
1866 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1867 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1868
1869 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1870 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1871
1872 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1873
1874 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1875
1876 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1877 (unsigned int) ep->desc.bEndpointAddress,
1878 udev->slot_id,
1879 (unsigned int) new_drop_flags,
1880 (unsigned int) new_add_flags);
1881 return 0;
1882}
1883EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1884
1885/* Add an endpoint to a new possible bandwidth configuration for this device.
1886 * Only one call to this function is allowed per endpoint before
1887 * check_bandwidth() or reset_bandwidth() must be called.
1888 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1889 * add the endpoint to the schedule with possibly new parameters denoted by a
1890 * different endpoint descriptor in usb_host_endpoint.
1891 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1892 * not allowed.
1893 *
1894 * The USB core will not allow URBs to be queued to an endpoint until the
1895 * configuration or alt setting is installed in the device, so there's no need
1896 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1897 */
1898int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1899 struct usb_host_endpoint *ep)
1900{
1901 struct xhci_hcd *xhci;
1902 struct xhci_container_ctx *in_ctx;
1903 unsigned int ep_index;
1904 struct xhci_input_control_ctx *ctrl_ctx;
1905 struct xhci_ep_ctx *ep_ctx;
1906 u32 added_ctxs;
1907 u32 new_add_flags, new_drop_flags;
1908 struct xhci_virt_device *virt_dev;
1909 int ret = 0;
1910
1911 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1912 if (ret <= 0) {
1913 /* So we won't queue a reset ep command for a root hub */
1914 ep->hcpriv = NULL;
1915 return ret;
1916 }
1917 xhci = hcd_to_xhci(hcd);
1918 if (xhci->xhc_state & XHCI_STATE_DYING)
1919 return -ENODEV;
1920
1921 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1922 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1923 /* FIXME when we have to issue an evaluate endpoint command to
1924 * deal with ep0 max packet size changing once we get the
1925 * descriptors
1926 */
1927 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1928 __func__, added_ctxs);
1929 return 0;
1930 }
1931
1932 virt_dev = xhci->devs[udev->slot_id];
1933 in_ctx = virt_dev->in_ctx;
1934 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1935 if (!ctrl_ctx) {
1936 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1937 __func__);
1938 return 0;
1939 }
1940
1941 ep_index = xhci_get_endpoint_index(&ep->desc);
1942 /* If this endpoint is already in use, and the upper layers are trying
1943 * to add it again without dropping it, reject the addition.
1944 */
1945 if (virt_dev->eps[ep_index].ring &&
1946 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1947 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1948 "without dropping it.\n",
1949 (unsigned int) ep->desc.bEndpointAddress);
1950 return -EINVAL;
1951 }
1952
1953 /* If the HCD has already noted the endpoint is enabled,
1954 * ignore this request.
1955 */
1956 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1957 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1958 __func__, ep);
1959 return 0;
1960 }
1961
1962 /*
1963 * Configuration and alternate setting changes must be done in
1964 * process context, not interrupt context (or so documenation
1965 * for usb_set_interface() and usb_set_configuration() claim).
1966 */
1967 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1968 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1969 __func__, ep->desc.bEndpointAddress);
1970 return -ENOMEM;
1971 }
1972
1973 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1974 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1975
1976 /* If xhci_endpoint_disable() was called for this endpoint, but the
1977 * xHC hasn't been notified yet through the check_bandwidth() call,
1978 * this re-adds a new state for the endpoint from the new endpoint
1979 * descriptors. We must drop and re-add this endpoint, so we leave the
1980 * drop flags alone.
1981 */
1982 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1983
1984 /* Store the usb_device pointer for later use */
1985 ep->hcpriv = udev;
1986
1987 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1988 trace_xhci_add_endpoint(ep_ctx);
1989
1990 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1991 (unsigned int) ep->desc.bEndpointAddress,
1992 udev->slot_id,
1993 (unsigned int) new_drop_flags,
1994 (unsigned int) new_add_flags);
1995 return 0;
1996}
1997EXPORT_SYMBOL_GPL(xhci_add_endpoint);
1998
1999static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2000{
2001 struct xhci_input_control_ctx *ctrl_ctx;
2002 struct xhci_ep_ctx *ep_ctx;
2003 struct xhci_slot_ctx *slot_ctx;
2004 int i;
2005
2006 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2007 if (!ctrl_ctx) {
2008 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2009 __func__);
2010 return;
2011 }
2012
2013 /* When a device's add flag and drop flag are zero, any subsequent
2014 * configure endpoint command will leave that endpoint's state
2015 * untouched. Make sure we don't leave any old state in the input
2016 * endpoint contexts.
2017 */
2018 ctrl_ctx->drop_flags = 0;
2019 ctrl_ctx->add_flags = 0;
2020 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2021 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2022 /* Endpoint 0 is always valid */
2023 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2024 for (i = 1; i < 31; i++) {
2025 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2026 ep_ctx->ep_info = 0;
2027 ep_ctx->ep_info2 = 0;
2028 ep_ctx->deq = 0;
2029 ep_ctx->tx_info = 0;
2030 }
2031}
2032
2033static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2034 struct usb_device *udev, u32 *cmd_status)
2035{
2036 int ret;
2037
2038 switch (*cmd_status) {
2039 case COMP_COMMAND_ABORTED:
2040 case COMP_COMMAND_RING_STOPPED:
2041 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2042 ret = -ETIME;
2043 break;
2044 case COMP_RESOURCE_ERROR:
2045 dev_warn(&udev->dev,
2046 "Not enough host controller resources for new device state.\n");
2047 ret = -ENOMEM;
2048 /* FIXME: can we allocate more resources for the HC? */
2049 break;
2050 case COMP_BANDWIDTH_ERROR:
2051 case COMP_SECONDARY_BANDWIDTH_ERROR:
2052 dev_warn(&udev->dev,
2053 "Not enough bandwidth for new device state.\n");
2054 ret = -ENOSPC;
2055 /* FIXME: can we go back to the old state? */
2056 break;
2057 case COMP_TRB_ERROR:
2058 /* the HCD set up something wrong */
2059 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2060 "add flag = 1, "
2061 "and endpoint is not disabled.\n");
2062 ret = -EINVAL;
2063 break;
2064 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2065 dev_warn(&udev->dev,
2066 "ERROR: Incompatible device for endpoint configure command.\n");
2067 ret = -ENODEV;
2068 break;
2069 case COMP_SUCCESS:
2070 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2071 "Successful Endpoint Configure command");
2072 ret = 0;
2073 break;
2074 default:
2075 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2076 *cmd_status);
2077 ret = -EINVAL;
2078 break;
2079 }
2080 return ret;
2081}
2082
2083static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2084 struct usb_device *udev, u32 *cmd_status)
2085{
2086 int ret;
2087
2088 switch (*cmd_status) {
2089 case COMP_COMMAND_ABORTED:
2090 case COMP_COMMAND_RING_STOPPED:
2091 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2092 ret = -ETIME;
2093 break;
2094 case COMP_PARAMETER_ERROR:
2095 dev_warn(&udev->dev,
2096 "WARN: xHCI driver setup invalid evaluate context command.\n");
2097 ret = -EINVAL;
2098 break;
2099 case COMP_SLOT_NOT_ENABLED_ERROR:
2100 dev_warn(&udev->dev,
2101 "WARN: slot not enabled for evaluate context command.\n");
2102 ret = -EINVAL;
2103 break;
2104 case COMP_CONTEXT_STATE_ERROR:
2105 dev_warn(&udev->dev,
2106 "WARN: invalid context state for evaluate context command.\n");
2107 ret = -EINVAL;
2108 break;
2109 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2110 dev_warn(&udev->dev,
2111 "ERROR: Incompatible device for evaluate context command.\n");
2112 ret = -ENODEV;
2113 break;
2114 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2115 /* Max Exit Latency too large error */
2116 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2117 ret = -EINVAL;
2118 break;
2119 case COMP_SUCCESS:
2120 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2121 "Successful evaluate context command");
2122 ret = 0;
2123 break;
2124 default:
2125 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2126 *cmd_status);
2127 ret = -EINVAL;
2128 break;
2129 }
2130 return ret;
2131}
2132
2133static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2134 struct xhci_input_control_ctx *ctrl_ctx)
2135{
2136 u32 valid_add_flags;
2137 u32 valid_drop_flags;
2138
2139 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2140 * (bit 1). The default control endpoint is added during the Address
2141 * Device command and is never removed until the slot is disabled.
2142 */
2143 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2144 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2145
2146 /* Use hweight32 to count the number of ones in the add flags, or
2147 * number of endpoints added. Don't count endpoints that are changed
2148 * (both added and dropped).
2149 */
2150 return hweight32(valid_add_flags) -
2151 hweight32(valid_add_flags & valid_drop_flags);
2152}
2153
2154static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2155 struct xhci_input_control_ctx *ctrl_ctx)
2156{
2157 u32 valid_add_flags;
2158 u32 valid_drop_flags;
2159
2160 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2161 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2162
2163 return hweight32(valid_drop_flags) -
2164 hweight32(valid_add_flags & valid_drop_flags);
2165}
2166
2167/*
2168 * We need to reserve the new number of endpoints before the configure endpoint
2169 * command completes. We can't subtract the dropped endpoints from the number
2170 * of active endpoints until the command completes because we can oversubscribe
2171 * the host in this case:
2172 *
2173 * - the first configure endpoint command drops more endpoints than it adds
2174 * - a second configure endpoint command that adds more endpoints is queued
2175 * - the first configure endpoint command fails, so the config is unchanged
2176 * - the second command may succeed, even though there isn't enough resources
2177 *
2178 * Must be called with xhci->lock held.
2179 */
2180static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2181 struct xhci_input_control_ctx *ctrl_ctx)
2182{
2183 u32 added_eps;
2184
2185 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2186 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2187 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2188 "Not enough ep ctxs: "
2189 "%u active, need to add %u, limit is %u.",
2190 xhci->num_active_eps, added_eps,
2191 xhci->limit_active_eps);
2192 return -ENOMEM;
2193 }
2194 xhci->num_active_eps += added_eps;
2195 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2196 "Adding %u ep ctxs, %u now active.", added_eps,
2197 xhci->num_active_eps);
2198 return 0;
2199}
2200
2201/*
2202 * The configure endpoint was failed by the xHC for some other reason, so we
2203 * need to revert the resources that failed configuration would have used.
2204 *
2205 * Must be called with xhci->lock held.
2206 */
2207static void xhci_free_host_resources(struct xhci_hcd *xhci,
2208 struct xhci_input_control_ctx *ctrl_ctx)
2209{
2210 u32 num_failed_eps;
2211
2212 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2213 xhci->num_active_eps -= num_failed_eps;
2214 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2215 "Removing %u failed ep ctxs, %u now active.",
2216 num_failed_eps,
2217 xhci->num_active_eps);
2218}
2219
2220/*
2221 * Now that the command has completed, clean up the active endpoint count by
2222 * subtracting out the endpoints that were dropped (but not changed).
2223 *
2224 * Must be called with xhci->lock held.
2225 */
2226static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2227 struct xhci_input_control_ctx *ctrl_ctx)
2228{
2229 u32 num_dropped_eps;
2230
2231 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2232 xhci->num_active_eps -= num_dropped_eps;
2233 if (num_dropped_eps)
2234 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2235 "Removing %u dropped ep ctxs, %u now active.",
2236 num_dropped_eps,
2237 xhci->num_active_eps);
2238}
2239
2240static unsigned int xhci_get_block_size(struct usb_device *udev)
2241{
2242 switch (udev->speed) {
2243 case USB_SPEED_LOW:
2244 case USB_SPEED_FULL:
2245 return FS_BLOCK;
2246 case USB_SPEED_HIGH:
2247 return HS_BLOCK;
2248 case USB_SPEED_SUPER:
2249 case USB_SPEED_SUPER_PLUS:
2250 return SS_BLOCK;
2251 case USB_SPEED_UNKNOWN:
2252 default:
2253 /* Should never happen */
2254 return 1;
2255 }
2256}
2257
2258static unsigned int
2259xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2260{
2261 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2262 return LS_OVERHEAD;
2263 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2264 return FS_OVERHEAD;
2265 return HS_OVERHEAD;
2266}
2267
2268/* If we are changing a LS/FS device under a HS hub,
2269 * make sure (if we are activating a new TT) that the HS bus has enough
2270 * bandwidth for this new TT.
2271 */
2272static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2273 struct xhci_virt_device *virt_dev,
2274 int old_active_eps)
2275{
2276 struct xhci_interval_bw_table *bw_table;
2277 struct xhci_tt_bw_info *tt_info;
2278
2279 /* Find the bandwidth table for the root port this TT is attached to. */
2280 bw_table = &xhci->rh_bw[virt_dev->rhub_port->hw_portnum].bw_table;
2281 tt_info = virt_dev->tt_info;
2282 /* If this TT already had active endpoints, the bandwidth for this TT
2283 * has already been added. Removing all periodic endpoints (and thus
2284 * making the TT enactive) will only decrease the bandwidth used.
2285 */
2286 if (old_active_eps)
2287 return 0;
2288 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2289 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2290 return -ENOMEM;
2291 return 0;
2292 }
2293 /* Not sure why we would have no new active endpoints...
2294 *
2295 * Maybe because of an Evaluate Context change for a hub update or a
2296 * control endpoint 0 max packet size change?
2297 * FIXME: skip the bandwidth calculation in that case.
2298 */
2299 return 0;
2300}
2301
2302static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2303 struct xhci_virt_device *virt_dev)
2304{
2305 unsigned int bw_reserved;
2306
2307 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2308 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2309 return -ENOMEM;
2310
2311 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2312 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2313 return -ENOMEM;
2314
2315 return 0;
2316}
2317
2318/*
2319 * This algorithm is a very conservative estimate of the worst-case scheduling
2320 * scenario for any one interval. The hardware dynamically schedules the
2321 * packets, so we can't tell which microframe could be the limiting factor in
2322 * the bandwidth scheduling. This only takes into account periodic endpoints.
2323 *
2324 * Obviously, we can't solve an NP complete problem to find the minimum worst
2325 * case scenario. Instead, we come up with an estimate that is no less than
2326 * the worst case bandwidth used for any one microframe, but may be an
2327 * over-estimate.
2328 *
2329 * We walk the requirements for each endpoint by interval, starting with the
2330 * smallest interval, and place packets in the schedule where there is only one
2331 * possible way to schedule packets for that interval. In order to simplify
2332 * this algorithm, we record the largest max packet size for each interval, and
2333 * assume all packets will be that size.
2334 *
2335 * For interval 0, we obviously must schedule all packets for each interval.
2336 * The bandwidth for interval 0 is just the amount of data to be transmitted
2337 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2338 * the number of packets).
2339 *
2340 * For interval 1, we have two possible microframes to schedule those packets
2341 * in. For this algorithm, if we can schedule the same number of packets for
2342 * each possible scheduling opportunity (each microframe), we will do so. The
2343 * remaining number of packets will be saved to be transmitted in the gaps in
2344 * the next interval's scheduling sequence.
2345 *
2346 * As we move those remaining packets to be scheduled with interval 2 packets,
2347 * we have to double the number of remaining packets to transmit. This is
2348 * because the intervals are actually powers of 2, and we would be transmitting
2349 * the previous interval's packets twice in this interval. We also have to be
2350 * sure that when we look at the largest max packet size for this interval, we
2351 * also look at the largest max packet size for the remaining packets and take
2352 * the greater of the two.
2353 *
2354 * The algorithm continues to evenly distribute packets in each scheduling
2355 * opportunity, and push the remaining packets out, until we get to the last
2356 * interval. Then those packets and their associated overhead are just added
2357 * to the bandwidth used.
2358 */
2359static int xhci_check_bw_table(struct xhci_hcd *xhci,
2360 struct xhci_virt_device *virt_dev,
2361 int old_active_eps)
2362{
2363 unsigned int bw_reserved;
2364 unsigned int max_bandwidth;
2365 unsigned int bw_used;
2366 unsigned int block_size;
2367 struct xhci_interval_bw_table *bw_table;
2368 unsigned int packet_size = 0;
2369 unsigned int overhead = 0;
2370 unsigned int packets_transmitted = 0;
2371 unsigned int packets_remaining = 0;
2372 unsigned int i;
2373
2374 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2375 return xhci_check_ss_bw(xhci, virt_dev);
2376
2377 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2378 max_bandwidth = HS_BW_LIMIT;
2379 /* Convert percent of bus BW reserved to blocks reserved */
2380 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2381 } else {
2382 max_bandwidth = FS_BW_LIMIT;
2383 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2384 }
2385
2386 bw_table = virt_dev->bw_table;
2387 /* We need to translate the max packet size and max ESIT payloads into
2388 * the units the hardware uses.
2389 */
2390 block_size = xhci_get_block_size(virt_dev->udev);
2391
2392 /* If we are manipulating a LS/FS device under a HS hub, double check
2393 * that the HS bus has enough bandwidth if we are activing a new TT.
2394 */
2395 if (virt_dev->tt_info) {
2396 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2397 "Recalculating BW for rootport %u",
2398 virt_dev->rhub_port->hw_portnum + 1);
2399 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2400 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2401 "newly activated TT.\n");
2402 return -ENOMEM;
2403 }
2404 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2405 "Recalculating BW for TT slot %u port %u",
2406 virt_dev->tt_info->slot_id,
2407 virt_dev->tt_info->ttport);
2408 } else {
2409 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2410 "Recalculating BW for rootport %u",
2411 virt_dev->rhub_port->hw_portnum + 1);
2412 }
2413
2414 /* Add in how much bandwidth will be used for interval zero, or the
2415 * rounded max ESIT payload + number of packets * largest overhead.
2416 */
2417 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2418 bw_table->interval_bw[0].num_packets *
2419 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2420
2421 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2422 unsigned int bw_added;
2423 unsigned int largest_mps;
2424 unsigned int interval_overhead;
2425
2426 /*
2427 * How many packets could we transmit in this interval?
2428 * If packets didn't fit in the previous interval, we will need
2429 * to transmit that many packets twice within this interval.
2430 */
2431 packets_remaining = 2 * packets_remaining +
2432 bw_table->interval_bw[i].num_packets;
2433
2434 /* Find the largest max packet size of this or the previous
2435 * interval.
2436 */
2437 if (list_empty(&bw_table->interval_bw[i].endpoints))
2438 largest_mps = 0;
2439 else {
2440 struct xhci_virt_ep *virt_ep;
2441 struct list_head *ep_entry;
2442
2443 ep_entry = bw_table->interval_bw[i].endpoints.next;
2444 virt_ep = list_entry(ep_entry,
2445 struct xhci_virt_ep, bw_endpoint_list);
2446 /* Convert to blocks, rounding up */
2447 largest_mps = DIV_ROUND_UP(
2448 virt_ep->bw_info.max_packet_size,
2449 block_size);
2450 }
2451 if (largest_mps > packet_size)
2452 packet_size = largest_mps;
2453
2454 /* Use the larger overhead of this or the previous interval. */
2455 interval_overhead = xhci_get_largest_overhead(
2456 &bw_table->interval_bw[i]);
2457 if (interval_overhead > overhead)
2458 overhead = interval_overhead;
2459
2460 /* How many packets can we evenly distribute across
2461 * (1 << (i + 1)) possible scheduling opportunities?
2462 */
2463 packets_transmitted = packets_remaining >> (i + 1);
2464
2465 /* Add in the bandwidth used for those scheduled packets */
2466 bw_added = packets_transmitted * (overhead + packet_size);
2467
2468 /* How many packets do we have remaining to transmit? */
2469 packets_remaining = packets_remaining % (1 << (i + 1));
2470
2471 /* What largest max packet size should those packets have? */
2472 /* If we've transmitted all packets, don't carry over the
2473 * largest packet size.
2474 */
2475 if (packets_remaining == 0) {
2476 packet_size = 0;
2477 overhead = 0;
2478 } else if (packets_transmitted > 0) {
2479 /* Otherwise if we do have remaining packets, and we've
2480 * scheduled some packets in this interval, take the
2481 * largest max packet size from endpoints with this
2482 * interval.
2483 */
2484 packet_size = largest_mps;
2485 overhead = interval_overhead;
2486 }
2487 /* Otherwise carry over packet_size and overhead from the last
2488 * time we had a remainder.
2489 */
2490 bw_used += bw_added;
2491 if (bw_used > max_bandwidth) {
2492 xhci_warn(xhci, "Not enough bandwidth. "
2493 "Proposed: %u, Max: %u\n",
2494 bw_used, max_bandwidth);
2495 return -ENOMEM;
2496 }
2497 }
2498 /*
2499 * Ok, we know we have some packets left over after even-handedly
2500 * scheduling interval 15. We don't know which microframes they will
2501 * fit into, so we over-schedule and say they will be scheduled every
2502 * microframe.
2503 */
2504 if (packets_remaining > 0)
2505 bw_used += overhead + packet_size;
2506
2507 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2508 /* OK, we're manipulating a HS device attached to a
2509 * root port bandwidth domain. Include the number of active TTs
2510 * in the bandwidth used.
2511 */
2512 bw_used += TT_HS_OVERHEAD *
2513 xhci->rh_bw[virt_dev->rhub_port->hw_portnum].num_active_tts;
2514 }
2515
2516 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2517 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2518 "Available: %u " "percent",
2519 bw_used, max_bandwidth, bw_reserved,
2520 (max_bandwidth - bw_used - bw_reserved) * 100 /
2521 max_bandwidth);
2522
2523 bw_used += bw_reserved;
2524 if (bw_used > max_bandwidth) {
2525 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2526 bw_used, max_bandwidth);
2527 return -ENOMEM;
2528 }
2529
2530 bw_table->bw_used = bw_used;
2531 return 0;
2532}
2533
2534static bool xhci_is_async_ep(unsigned int ep_type)
2535{
2536 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2537 ep_type != ISOC_IN_EP &&
2538 ep_type != INT_IN_EP);
2539}
2540
2541static bool xhci_is_sync_in_ep(unsigned int ep_type)
2542{
2543 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2544}
2545
2546static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2547{
2548 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2549
2550 if (ep_bw->ep_interval == 0)
2551 return SS_OVERHEAD_BURST +
2552 (ep_bw->mult * ep_bw->num_packets *
2553 (SS_OVERHEAD + mps));
2554 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2555 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2556 1 << ep_bw->ep_interval);
2557
2558}
2559
2560static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2561 struct xhci_bw_info *ep_bw,
2562 struct xhci_interval_bw_table *bw_table,
2563 struct usb_device *udev,
2564 struct xhci_virt_ep *virt_ep,
2565 struct xhci_tt_bw_info *tt_info)
2566{
2567 struct xhci_interval_bw *interval_bw;
2568 int normalized_interval;
2569
2570 if (xhci_is_async_ep(ep_bw->type))
2571 return;
2572
2573 if (udev->speed >= USB_SPEED_SUPER) {
2574 if (xhci_is_sync_in_ep(ep_bw->type))
2575 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2576 xhci_get_ss_bw_consumed(ep_bw);
2577 else
2578 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2579 xhci_get_ss_bw_consumed(ep_bw);
2580 return;
2581 }
2582
2583 /* SuperSpeed endpoints never get added to intervals in the table, so
2584 * this check is only valid for HS/FS/LS devices.
2585 */
2586 if (list_empty(&virt_ep->bw_endpoint_list))
2587 return;
2588 /* For LS/FS devices, we need to translate the interval expressed in
2589 * microframes to frames.
2590 */
2591 if (udev->speed == USB_SPEED_HIGH)
2592 normalized_interval = ep_bw->ep_interval;
2593 else
2594 normalized_interval = ep_bw->ep_interval - 3;
2595
2596 if (normalized_interval == 0)
2597 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2598 interval_bw = &bw_table->interval_bw[normalized_interval];
2599 interval_bw->num_packets -= ep_bw->num_packets;
2600 switch (udev->speed) {
2601 case USB_SPEED_LOW:
2602 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2603 break;
2604 case USB_SPEED_FULL:
2605 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2606 break;
2607 case USB_SPEED_HIGH:
2608 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2609 break;
2610 default:
2611 /* Should never happen because only LS/FS/HS endpoints will get
2612 * added to the endpoint list.
2613 */
2614 return;
2615 }
2616 if (tt_info)
2617 tt_info->active_eps -= 1;
2618 list_del_init(&virt_ep->bw_endpoint_list);
2619}
2620
2621static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2622 struct xhci_bw_info *ep_bw,
2623 struct xhci_interval_bw_table *bw_table,
2624 struct usb_device *udev,
2625 struct xhci_virt_ep *virt_ep,
2626 struct xhci_tt_bw_info *tt_info)
2627{
2628 struct xhci_interval_bw *interval_bw;
2629 struct xhci_virt_ep *smaller_ep;
2630 int normalized_interval;
2631
2632 if (xhci_is_async_ep(ep_bw->type))
2633 return;
2634
2635 if (udev->speed == USB_SPEED_SUPER) {
2636 if (xhci_is_sync_in_ep(ep_bw->type))
2637 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2638 xhci_get_ss_bw_consumed(ep_bw);
2639 else
2640 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2641 xhci_get_ss_bw_consumed(ep_bw);
2642 return;
2643 }
2644
2645 /* For LS/FS devices, we need to translate the interval expressed in
2646 * microframes to frames.
2647 */
2648 if (udev->speed == USB_SPEED_HIGH)
2649 normalized_interval = ep_bw->ep_interval;
2650 else
2651 normalized_interval = ep_bw->ep_interval - 3;
2652
2653 if (normalized_interval == 0)
2654 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2655 interval_bw = &bw_table->interval_bw[normalized_interval];
2656 interval_bw->num_packets += ep_bw->num_packets;
2657 switch (udev->speed) {
2658 case USB_SPEED_LOW:
2659 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2660 break;
2661 case USB_SPEED_FULL:
2662 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2663 break;
2664 case USB_SPEED_HIGH:
2665 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2666 break;
2667 default:
2668 /* Should never happen because only LS/FS/HS endpoints will get
2669 * added to the endpoint list.
2670 */
2671 return;
2672 }
2673
2674 if (tt_info)
2675 tt_info->active_eps += 1;
2676 /* Insert the endpoint into the list, largest max packet size first. */
2677 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2678 bw_endpoint_list) {
2679 if (ep_bw->max_packet_size >=
2680 smaller_ep->bw_info.max_packet_size) {
2681 /* Add the new ep before the smaller endpoint */
2682 list_add_tail(&virt_ep->bw_endpoint_list,
2683 &smaller_ep->bw_endpoint_list);
2684 return;
2685 }
2686 }
2687 /* Add the new endpoint at the end of the list. */
2688 list_add_tail(&virt_ep->bw_endpoint_list,
2689 &interval_bw->endpoints);
2690}
2691
2692void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2693 struct xhci_virt_device *virt_dev,
2694 int old_active_eps)
2695{
2696 struct xhci_root_port_bw_info *rh_bw_info;
2697 if (!virt_dev->tt_info)
2698 return;
2699
2700 rh_bw_info = &xhci->rh_bw[virt_dev->rhub_port->hw_portnum];
2701 if (old_active_eps == 0 &&
2702 virt_dev->tt_info->active_eps != 0) {
2703 rh_bw_info->num_active_tts += 1;
2704 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2705 } else if (old_active_eps != 0 &&
2706 virt_dev->tt_info->active_eps == 0) {
2707 rh_bw_info->num_active_tts -= 1;
2708 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2709 }
2710}
2711
2712static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2713 struct xhci_virt_device *virt_dev,
2714 struct xhci_container_ctx *in_ctx)
2715{
2716 struct xhci_bw_info ep_bw_info[31];
2717 int i;
2718 struct xhci_input_control_ctx *ctrl_ctx;
2719 int old_active_eps = 0;
2720
2721 if (virt_dev->tt_info)
2722 old_active_eps = virt_dev->tt_info->active_eps;
2723
2724 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2725 if (!ctrl_ctx) {
2726 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2727 __func__);
2728 return -ENOMEM;
2729 }
2730
2731 for (i = 0; i < 31; i++) {
2732 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2733 continue;
2734
2735 /* Make a copy of the BW info in case we need to revert this */
2736 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2737 sizeof(ep_bw_info[i]));
2738 /* Drop the endpoint from the interval table if the endpoint is
2739 * being dropped or changed.
2740 */
2741 if (EP_IS_DROPPED(ctrl_ctx, i))
2742 xhci_drop_ep_from_interval_table(xhci,
2743 &virt_dev->eps[i].bw_info,
2744 virt_dev->bw_table,
2745 virt_dev->udev,
2746 &virt_dev->eps[i],
2747 virt_dev->tt_info);
2748 }
2749 /* Overwrite the information stored in the endpoints' bw_info */
2750 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2751 for (i = 0; i < 31; i++) {
2752 /* Add any changed or added endpoints to the interval table */
2753 if (EP_IS_ADDED(ctrl_ctx, i))
2754 xhci_add_ep_to_interval_table(xhci,
2755 &virt_dev->eps[i].bw_info,
2756 virt_dev->bw_table,
2757 virt_dev->udev,
2758 &virt_dev->eps[i],
2759 virt_dev->tt_info);
2760 }
2761
2762 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2763 /* Ok, this fits in the bandwidth we have.
2764 * Update the number of active TTs.
2765 */
2766 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2767 return 0;
2768 }
2769
2770 /* We don't have enough bandwidth for this, revert the stored info. */
2771 for (i = 0; i < 31; i++) {
2772 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2773 continue;
2774
2775 /* Drop the new copies of any added or changed endpoints from
2776 * the interval table.
2777 */
2778 if (EP_IS_ADDED(ctrl_ctx, i)) {
2779 xhci_drop_ep_from_interval_table(xhci,
2780 &virt_dev->eps[i].bw_info,
2781 virt_dev->bw_table,
2782 virt_dev->udev,
2783 &virt_dev->eps[i],
2784 virt_dev->tt_info);
2785 }
2786 /* Revert the endpoint back to its old information */
2787 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2788 sizeof(ep_bw_info[i]));
2789 /* Add any changed or dropped endpoints back into the table */
2790 if (EP_IS_DROPPED(ctrl_ctx, i))
2791 xhci_add_ep_to_interval_table(xhci,
2792 &virt_dev->eps[i].bw_info,
2793 virt_dev->bw_table,
2794 virt_dev->udev,
2795 &virt_dev->eps[i],
2796 virt_dev->tt_info);
2797 }
2798 return -ENOMEM;
2799}
2800
2801/*
2802 * Synchronous XHCI stop endpoint helper. Issues the stop endpoint command and
2803 * waits for the command completion before returning. This does not call
2804 * xhci_handle_cmd_stop_ep(), which has additional handling for 'context error'
2805 * cases, along with transfer ring cleanup.
2806 *
2807 * xhci_stop_endpoint_sync() is intended to be utilized by clients that manage
2808 * their own transfer ring, such as offload situations.
2809 */
2810int xhci_stop_endpoint_sync(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, int suspend,
2811 gfp_t gfp_flags)
2812{
2813 struct xhci_command *command;
2814 unsigned long flags;
2815 int ret;
2816
2817 command = xhci_alloc_command(xhci, true, gfp_flags);
2818 if (!command)
2819 return -ENOMEM;
2820
2821 spin_lock_irqsave(&xhci->lock, flags);
2822 ret = xhci_queue_stop_endpoint(xhci, command, ep->vdev->slot_id,
2823 ep->ep_index, suspend);
2824 if (ret < 0) {
2825 spin_unlock_irqrestore(&xhci->lock, flags);
2826 goto out;
2827 }
2828
2829 xhci_ring_cmd_db(xhci);
2830 spin_unlock_irqrestore(&xhci->lock, flags);
2831
2832 wait_for_completion(command->completion);
2833
2834 /* No handling for COMP_CONTEXT_STATE_ERROR done at command completion*/
2835 if (command->status == COMP_COMMAND_ABORTED ||
2836 command->status == COMP_COMMAND_RING_STOPPED) {
2837 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
2838 ret = -ETIME;
2839 }
2840out:
2841 xhci_free_command(xhci, command);
2842
2843 return ret;
2844}
2845EXPORT_SYMBOL_GPL(xhci_stop_endpoint_sync);
2846
2847/* Issue a configure endpoint command or evaluate context command
2848 * and wait for it to finish.
2849 */
2850static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2851 struct usb_device *udev,
2852 struct xhci_command *command,
2853 bool ctx_change, bool must_succeed)
2854{
2855 int ret;
2856 unsigned long flags;
2857 struct xhci_input_control_ctx *ctrl_ctx;
2858 struct xhci_virt_device *virt_dev;
2859 struct xhci_slot_ctx *slot_ctx;
2860
2861 if (!command)
2862 return -EINVAL;
2863
2864 spin_lock_irqsave(&xhci->lock, flags);
2865
2866 if (xhci->xhc_state & XHCI_STATE_DYING) {
2867 spin_unlock_irqrestore(&xhci->lock, flags);
2868 return -ESHUTDOWN;
2869 }
2870
2871 virt_dev = xhci->devs[udev->slot_id];
2872
2873 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2874 if (!ctrl_ctx) {
2875 spin_unlock_irqrestore(&xhci->lock, flags);
2876 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2877 __func__);
2878 return -ENOMEM;
2879 }
2880
2881 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2882 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2883 spin_unlock_irqrestore(&xhci->lock, flags);
2884 xhci_warn(xhci, "Not enough host resources, "
2885 "active endpoint contexts = %u\n",
2886 xhci->num_active_eps);
2887 return -ENOMEM;
2888 }
2889 if ((xhci->quirks & XHCI_SW_BW_CHECKING) && !ctx_change &&
2890 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2891 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2892 xhci_free_host_resources(xhci, ctrl_ctx);
2893 spin_unlock_irqrestore(&xhci->lock, flags);
2894 xhci_warn(xhci, "Not enough bandwidth\n");
2895 return -ENOMEM;
2896 }
2897
2898 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2899
2900 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2901 trace_xhci_configure_endpoint(slot_ctx);
2902
2903 if (!ctx_change)
2904 ret = xhci_queue_configure_endpoint(xhci, command,
2905 command->in_ctx->dma,
2906 udev->slot_id, must_succeed);
2907 else
2908 ret = xhci_queue_evaluate_context(xhci, command,
2909 command->in_ctx->dma,
2910 udev->slot_id, must_succeed);
2911 if (ret < 0) {
2912 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2913 xhci_free_host_resources(xhci, ctrl_ctx);
2914 spin_unlock_irqrestore(&xhci->lock, flags);
2915 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2916 "FIXME allocate a new ring segment");
2917 return -ENOMEM;
2918 }
2919 xhci_ring_cmd_db(xhci);
2920 spin_unlock_irqrestore(&xhci->lock, flags);
2921
2922 /* Wait for the configure endpoint command to complete */
2923 wait_for_completion(command->completion);
2924
2925 if (!ctx_change)
2926 ret = xhci_configure_endpoint_result(xhci, udev,
2927 &command->status);
2928 else
2929 ret = xhci_evaluate_context_result(xhci, udev,
2930 &command->status);
2931
2932 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2933 spin_lock_irqsave(&xhci->lock, flags);
2934 /* If the command failed, remove the reserved resources.
2935 * Otherwise, clean up the estimate to include dropped eps.
2936 */
2937 if (ret)
2938 xhci_free_host_resources(xhci, ctrl_ctx);
2939 else
2940 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2941 spin_unlock_irqrestore(&xhci->lock, flags);
2942 }
2943 return ret;
2944}
2945
2946static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2947 struct xhci_virt_device *vdev, int i)
2948{
2949 struct xhci_virt_ep *ep = &vdev->eps[i];
2950
2951 if (ep->ep_state & EP_HAS_STREAMS) {
2952 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2953 xhci_get_endpoint_address(i));
2954 xhci_free_stream_info(xhci, ep->stream_info);
2955 ep->stream_info = NULL;
2956 ep->ep_state &= ~EP_HAS_STREAMS;
2957 }
2958}
2959
2960/* Called after one or more calls to xhci_add_endpoint() or
2961 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2962 * to call xhci_reset_bandwidth().
2963 *
2964 * Since we are in the middle of changing either configuration or
2965 * installing a new alt setting, the USB core won't allow URBs to be
2966 * enqueued for any endpoint on the old config or interface. Nothing
2967 * else should be touching the xhci->devs[slot_id] structure, so we
2968 * don't need to take the xhci->lock for manipulating that.
2969 */
2970int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2971{
2972 int i;
2973 int ret = 0;
2974 struct xhci_hcd *xhci;
2975 struct xhci_virt_device *virt_dev;
2976 struct xhci_input_control_ctx *ctrl_ctx;
2977 struct xhci_slot_ctx *slot_ctx;
2978 struct xhci_command *command;
2979
2980 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2981 if (ret <= 0)
2982 return ret;
2983 xhci = hcd_to_xhci(hcd);
2984 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2985 (xhci->xhc_state & XHCI_STATE_REMOVING))
2986 return -ENODEV;
2987
2988 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2989 virt_dev = xhci->devs[udev->slot_id];
2990
2991 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2992 if (!command)
2993 return -ENOMEM;
2994
2995 command->in_ctx = virt_dev->in_ctx;
2996
2997 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2998 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2999 if (!ctrl_ctx) {
3000 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3001 __func__);
3002 ret = -ENOMEM;
3003 goto command_cleanup;
3004 }
3005 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3006 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3007 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3008
3009 /* Don't issue the command if there's no endpoints to update. */
3010 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3011 ctrl_ctx->drop_flags == 0) {
3012 ret = 0;
3013 goto command_cleanup;
3014 }
3015 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3016 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3017 for (i = 31; i >= 1; i--) {
3018 __le32 le32 = cpu_to_le32(BIT(i));
3019
3020 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3021 || (ctrl_ctx->add_flags & le32) || i == 1) {
3022 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3023 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3024 break;
3025 }
3026 }
3027
3028 ret = xhci_configure_endpoint(xhci, udev, command,
3029 false, false);
3030 if (ret)
3031 /* Callee should call reset_bandwidth() */
3032 goto command_cleanup;
3033
3034 /* Free any rings that were dropped, but not changed. */
3035 for (i = 1; i < 31; i++) {
3036 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3037 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3038 xhci_free_endpoint_ring(xhci, virt_dev, i);
3039 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3040 }
3041 }
3042 xhci_zero_in_ctx(xhci, virt_dev);
3043 /*
3044 * Install any rings for completely new endpoints or changed endpoints,
3045 * and free any old rings from changed endpoints.
3046 */
3047 for (i = 1; i < 31; i++) {
3048 if (!virt_dev->eps[i].new_ring)
3049 continue;
3050 /* Only free the old ring if it exists.
3051 * It may not if this is the first add of an endpoint.
3052 */
3053 if (virt_dev->eps[i].ring) {
3054 xhci_free_endpoint_ring(xhci, virt_dev, i);
3055 }
3056 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3057 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3058 virt_dev->eps[i].new_ring = NULL;
3059 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3060 }
3061command_cleanup:
3062 kfree(command->completion);
3063 kfree(command);
3064
3065 return ret;
3066}
3067EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3068
3069void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3070{
3071 struct xhci_hcd *xhci;
3072 struct xhci_virt_device *virt_dev;
3073 int i, ret;
3074
3075 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3076 if (ret <= 0)
3077 return;
3078 xhci = hcd_to_xhci(hcd);
3079
3080 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3081 virt_dev = xhci->devs[udev->slot_id];
3082 /* Free any rings allocated for added endpoints */
3083 for (i = 0; i < 31; i++) {
3084 if (virt_dev->eps[i].new_ring) {
3085 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3086 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3087 virt_dev->eps[i].new_ring = NULL;
3088 }
3089 }
3090 xhci_zero_in_ctx(xhci, virt_dev);
3091}
3092EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3093
3094static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3095 struct xhci_container_ctx *in_ctx,
3096 struct xhci_container_ctx *out_ctx,
3097 struct xhci_input_control_ctx *ctrl_ctx,
3098 u32 add_flags, u32 drop_flags)
3099{
3100 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3101 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3102 xhci_slot_copy(xhci, in_ctx, out_ctx);
3103 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3104}
3105
3106static void xhci_endpoint_disable(struct usb_hcd *hcd,
3107 struct usb_host_endpoint *host_ep)
3108{
3109 struct xhci_hcd *xhci;
3110 struct xhci_virt_device *vdev;
3111 struct xhci_virt_ep *ep;
3112 struct usb_device *udev;
3113 unsigned long flags;
3114 unsigned int ep_index;
3115
3116 xhci = hcd_to_xhci(hcd);
3117rescan:
3118 spin_lock_irqsave(&xhci->lock, flags);
3119
3120 udev = (struct usb_device *)host_ep->hcpriv;
3121 if (!udev || !udev->slot_id)
3122 goto done;
3123
3124 vdev = xhci->devs[udev->slot_id];
3125 if (!vdev)
3126 goto done;
3127
3128 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3129 ep = &vdev->eps[ep_index];
3130
3131 /* wait for hub_tt_work to finish clearing hub TT */
3132 if (ep->ep_state & EP_CLEARING_TT) {
3133 spin_unlock_irqrestore(&xhci->lock, flags);
3134 schedule_timeout_uninterruptible(1);
3135 goto rescan;
3136 }
3137
3138 if (ep->ep_state)
3139 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3140 ep->ep_state);
3141done:
3142 host_ep->hcpriv = NULL;
3143 spin_unlock_irqrestore(&xhci->lock, flags);
3144}
3145
3146/*
3147 * Called after usb core issues a clear halt control message.
3148 * The host side of the halt should already be cleared by a reset endpoint
3149 * command issued when the STALL event was received.
3150 *
3151 * The reset endpoint command may only be issued to endpoints in the halted
3152 * state. For software that wishes to reset the data toggle or sequence number
3153 * of an endpoint that isn't in the halted state this function will issue a
3154 * configure endpoint command with the Drop and Add bits set for the target
3155 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3156 *
3157 * vdev may be lost due to xHC restore error and re-initialization during S3/S4
3158 * resume. A new vdev will be allocated later by xhci_discover_or_reset_device()
3159 */
3160
3161static void xhci_endpoint_reset(struct usb_hcd *hcd,
3162 struct usb_host_endpoint *host_ep)
3163{
3164 struct xhci_hcd *xhci;
3165 struct usb_device *udev;
3166 struct xhci_virt_device *vdev;
3167 struct xhci_virt_ep *ep;
3168 struct xhci_input_control_ctx *ctrl_ctx;
3169 struct xhci_command *stop_cmd, *cfg_cmd;
3170 unsigned int ep_index;
3171 unsigned long flags;
3172 u32 ep_flag;
3173 int err;
3174
3175 xhci = hcd_to_xhci(hcd);
3176 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3177
3178 /*
3179 * Usb core assumes a max packet value for ep0 on FS devices until the
3180 * real value is read from the descriptor. Core resets Ep0 if values
3181 * mismatch. Reconfigure the xhci ep0 endpoint context here in that case
3182 */
3183 if (usb_endpoint_xfer_control(&host_ep->desc) && ep_index == 0) {
3184
3185 udev = container_of(host_ep, struct usb_device, ep0);
3186 if (udev->speed != USB_SPEED_FULL || !udev->slot_id)
3187 return;
3188
3189 vdev = xhci->devs[udev->slot_id];
3190 if (!vdev || vdev->udev != udev)
3191 return;
3192
3193 xhci_check_ep0_maxpacket(xhci, vdev);
3194
3195 /* Nothing else should be done here for ep0 during ep reset */
3196 return;
3197 }
3198
3199 if (!host_ep->hcpriv)
3200 return;
3201 udev = (struct usb_device *) host_ep->hcpriv;
3202 vdev = xhci->devs[udev->slot_id];
3203
3204 if (!udev->slot_id || !vdev)
3205 return;
3206
3207 ep = &vdev->eps[ep_index];
3208
3209 /* Bail out if toggle is already being cleared by a endpoint reset */
3210 spin_lock_irqsave(&xhci->lock, flags);
3211 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3212 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3213 spin_unlock_irqrestore(&xhci->lock, flags);
3214 return;
3215 }
3216 spin_unlock_irqrestore(&xhci->lock, flags);
3217 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3218 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3219 usb_endpoint_xfer_isoc(&host_ep->desc))
3220 return;
3221
3222 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3223
3224 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3225 return;
3226
3227 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3228 if (!stop_cmd)
3229 return;
3230
3231 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3232 if (!cfg_cmd)
3233 goto cleanup;
3234
3235 spin_lock_irqsave(&xhci->lock, flags);
3236
3237 /* block queuing new trbs and ringing ep doorbell */
3238 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3239
3240 /*
3241 * Make sure endpoint ring is empty before resetting the toggle/seq.
3242 * Driver is required to synchronously cancel all transfer request.
3243 * Stop the endpoint to force xHC to update the output context
3244 */
3245
3246 if (!list_empty(&ep->ring->td_list)) {
3247 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3248 spin_unlock_irqrestore(&xhci->lock, flags);
3249 xhci_free_command(xhci, cfg_cmd);
3250 goto cleanup;
3251 }
3252
3253 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3254 ep_index, 0);
3255 if (err < 0) {
3256 spin_unlock_irqrestore(&xhci->lock, flags);
3257 xhci_free_command(xhci, cfg_cmd);
3258 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3259 __func__, err);
3260 goto cleanup;
3261 }
3262
3263 xhci_ring_cmd_db(xhci);
3264 spin_unlock_irqrestore(&xhci->lock, flags);
3265
3266 wait_for_completion(stop_cmd->completion);
3267
3268 spin_lock_irqsave(&xhci->lock, flags);
3269
3270 /* config ep command clears toggle if add and drop ep flags are set */
3271 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3272 if (!ctrl_ctx) {
3273 spin_unlock_irqrestore(&xhci->lock, flags);
3274 xhci_free_command(xhci, cfg_cmd);
3275 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3276 __func__);
3277 goto cleanup;
3278 }
3279
3280 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3281 ctrl_ctx, ep_flag, ep_flag);
3282 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3283
3284 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3285 udev->slot_id, false);
3286 if (err < 0) {
3287 spin_unlock_irqrestore(&xhci->lock, flags);
3288 xhci_free_command(xhci, cfg_cmd);
3289 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3290 __func__, err);
3291 goto cleanup;
3292 }
3293
3294 xhci_ring_cmd_db(xhci);
3295 spin_unlock_irqrestore(&xhci->lock, flags);
3296
3297 wait_for_completion(cfg_cmd->completion);
3298
3299 xhci_free_command(xhci, cfg_cmd);
3300cleanup:
3301 xhci_free_command(xhci, stop_cmd);
3302 spin_lock_irqsave(&xhci->lock, flags);
3303 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3304 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3305 spin_unlock_irqrestore(&xhci->lock, flags);
3306}
3307
3308static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3309 struct usb_device *udev, struct usb_host_endpoint *ep,
3310 unsigned int slot_id)
3311{
3312 int ret;
3313 unsigned int ep_index;
3314 unsigned int ep_state;
3315
3316 if (!ep)
3317 return -EINVAL;
3318 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3319 if (ret <= 0)
3320 return ret ? ret : -EINVAL;
3321 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3322 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3323 " descriptor for ep 0x%x does not support streams\n",
3324 ep->desc.bEndpointAddress);
3325 return -EINVAL;
3326 }
3327
3328 ep_index = xhci_get_endpoint_index(&ep->desc);
3329 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3330 if (ep_state & EP_HAS_STREAMS ||
3331 ep_state & EP_GETTING_STREAMS) {
3332 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3333 "already has streams set up.\n",
3334 ep->desc.bEndpointAddress);
3335 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3336 "dynamic stream context array reallocation.\n");
3337 return -EINVAL;
3338 }
3339 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3340 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3341 "endpoint 0x%x; URBs are pending.\n",
3342 ep->desc.bEndpointAddress);
3343 return -EINVAL;
3344 }
3345 return 0;
3346}
3347
3348static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3349 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3350{
3351 unsigned int max_streams;
3352
3353 /* The stream context array size must be a power of two */
3354 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3355 /*
3356 * Find out how many primary stream array entries the host controller
3357 * supports. Later we may use secondary stream arrays (similar to 2nd
3358 * level page entries), but that's an optional feature for xHCI host
3359 * controllers. xHCs must support at least 4 stream IDs.
3360 */
3361 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3362 if (*num_stream_ctxs > max_streams) {
3363 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3364 max_streams);
3365 *num_stream_ctxs = max_streams;
3366 *num_streams = max_streams;
3367 }
3368}
3369
3370/* Returns an error code if one of the endpoint already has streams.
3371 * This does not change any data structures, it only checks and gathers
3372 * information.
3373 */
3374static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3375 struct usb_device *udev,
3376 struct usb_host_endpoint **eps, unsigned int num_eps,
3377 unsigned int *num_streams, u32 *changed_ep_bitmask)
3378{
3379 unsigned int max_streams;
3380 unsigned int endpoint_flag;
3381 int i;
3382 int ret;
3383
3384 for (i = 0; i < num_eps; i++) {
3385 ret = xhci_check_streams_endpoint(xhci, udev,
3386 eps[i], udev->slot_id);
3387 if (ret < 0)
3388 return ret;
3389
3390 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3391 if (max_streams < (*num_streams - 1)) {
3392 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3393 eps[i]->desc.bEndpointAddress,
3394 max_streams);
3395 *num_streams = max_streams+1;
3396 }
3397
3398 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3399 if (*changed_ep_bitmask & endpoint_flag)
3400 return -EINVAL;
3401 *changed_ep_bitmask |= endpoint_flag;
3402 }
3403 return 0;
3404}
3405
3406static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3407 struct usb_device *udev,
3408 struct usb_host_endpoint **eps, unsigned int num_eps)
3409{
3410 u32 changed_ep_bitmask = 0;
3411 unsigned int slot_id;
3412 unsigned int ep_index;
3413 unsigned int ep_state;
3414 int i;
3415
3416 slot_id = udev->slot_id;
3417 if (!xhci->devs[slot_id])
3418 return 0;
3419
3420 for (i = 0; i < num_eps; i++) {
3421 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3422 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3423 /* Are streams already being freed for the endpoint? */
3424 if (ep_state & EP_GETTING_NO_STREAMS) {
3425 xhci_warn(xhci, "WARN Can't disable streams for "
3426 "endpoint 0x%x, "
3427 "streams are being disabled already\n",
3428 eps[i]->desc.bEndpointAddress);
3429 return 0;
3430 }
3431 /* Are there actually any streams to free? */
3432 if (!(ep_state & EP_HAS_STREAMS) &&
3433 !(ep_state & EP_GETTING_STREAMS)) {
3434 xhci_warn(xhci, "WARN Can't disable streams for "
3435 "endpoint 0x%x, "
3436 "streams are already disabled!\n",
3437 eps[i]->desc.bEndpointAddress);
3438 xhci_warn(xhci, "WARN xhci_free_streams() called "
3439 "with non-streams endpoint\n");
3440 return 0;
3441 }
3442 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3443 }
3444 return changed_ep_bitmask;
3445}
3446
3447/*
3448 * The USB device drivers use this function (through the HCD interface in USB
3449 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3450 * coordinate mass storage command queueing across multiple endpoints (basically
3451 * a stream ID == a task ID).
3452 *
3453 * Setting up streams involves allocating the same size stream context array
3454 * for each endpoint and issuing a configure endpoint command for all endpoints.
3455 *
3456 * Don't allow the call to succeed if one endpoint only supports one stream
3457 * (which means it doesn't support streams at all).
3458 *
3459 * Drivers may get less stream IDs than they asked for, if the host controller
3460 * hardware or endpoints claim they can't support the number of requested
3461 * stream IDs.
3462 */
3463static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3464 struct usb_host_endpoint **eps, unsigned int num_eps,
3465 unsigned int num_streams, gfp_t mem_flags)
3466{
3467 int i, ret;
3468 struct xhci_hcd *xhci;
3469 struct xhci_virt_device *vdev;
3470 struct xhci_command *config_cmd;
3471 struct xhci_input_control_ctx *ctrl_ctx;
3472 unsigned int ep_index;
3473 unsigned int num_stream_ctxs;
3474 unsigned int max_packet;
3475 unsigned long flags;
3476 u32 changed_ep_bitmask = 0;
3477
3478 if (!eps)
3479 return -EINVAL;
3480
3481 /* Add one to the number of streams requested to account for
3482 * stream 0 that is reserved for xHCI usage.
3483 */
3484 num_streams += 1;
3485 xhci = hcd_to_xhci(hcd);
3486 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3487 num_streams);
3488
3489 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3490 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3491 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3492 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3493 return -ENOSYS;
3494 }
3495
3496 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3497 if (!config_cmd)
3498 return -ENOMEM;
3499
3500 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3501 if (!ctrl_ctx) {
3502 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3503 __func__);
3504 xhci_free_command(xhci, config_cmd);
3505 return -ENOMEM;
3506 }
3507
3508 /* Check to make sure all endpoints are not already configured for
3509 * streams. While we're at it, find the maximum number of streams that
3510 * all the endpoints will support and check for duplicate endpoints.
3511 */
3512 spin_lock_irqsave(&xhci->lock, flags);
3513 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3514 num_eps, &num_streams, &changed_ep_bitmask);
3515 if (ret < 0) {
3516 xhci_free_command(xhci, config_cmd);
3517 spin_unlock_irqrestore(&xhci->lock, flags);
3518 return ret;
3519 }
3520 if (num_streams <= 1) {
3521 xhci_warn(xhci, "WARN: endpoints can't handle "
3522 "more than one stream.\n");
3523 xhci_free_command(xhci, config_cmd);
3524 spin_unlock_irqrestore(&xhci->lock, flags);
3525 return -EINVAL;
3526 }
3527 vdev = xhci->devs[udev->slot_id];
3528 /* Mark each endpoint as being in transition, so
3529 * xhci_urb_enqueue() will reject all URBs.
3530 */
3531 for (i = 0; i < num_eps; i++) {
3532 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3533 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3534 }
3535 spin_unlock_irqrestore(&xhci->lock, flags);
3536
3537 /* Setup internal data structures and allocate HW data structures for
3538 * streams (but don't install the HW structures in the input context
3539 * until we're sure all memory allocation succeeded).
3540 */
3541 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3542 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3543 num_stream_ctxs, num_streams);
3544
3545 for (i = 0; i < num_eps; i++) {
3546 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3547 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3548 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3549 num_stream_ctxs,
3550 num_streams,
3551 max_packet, mem_flags);
3552 if (!vdev->eps[ep_index].stream_info)
3553 goto cleanup;
3554 /* Set maxPstreams in endpoint context and update deq ptr to
3555 * point to stream context array. FIXME
3556 */
3557 }
3558
3559 /* Set up the input context for a configure endpoint command. */
3560 for (i = 0; i < num_eps; i++) {
3561 struct xhci_ep_ctx *ep_ctx;
3562
3563 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3564 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3565
3566 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3567 vdev->out_ctx, ep_index);
3568 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3569 vdev->eps[ep_index].stream_info);
3570 }
3571 /* Tell the HW to drop its old copy of the endpoint context info
3572 * and add the updated copy from the input context.
3573 */
3574 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3575 vdev->out_ctx, ctrl_ctx,
3576 changed_ep_bitmask, changed_ep_bitmask);
3577
3578 /* Issue and wait for the configure endpoint command */
3579 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3580 false, false);
3581
3582 /* xHC rejected the configure endpoint command for some reason, so we
3583 * leave the old ring intact and free our internal streams data
3584 * structure.
3585 */
3586 if (ret < 0)
3587 goto cleanup;
3588
3589 spin_lock_irqsave(&xhci->lock, flags);
3590 for (i = 0; i < num_eps; i++) {
3591 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3592 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3593 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3594 udev->slot_id, ep_index);
3595 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3596 }
3597 xhci_free_command(xhci, config_cmd);
3598 spin_unlock_irqrestore(&xhci->lock, flags);
3599
3600 for (i = 0; i < num_eps; i++) {
3601 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3602 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3603 }
3604 /* Subtract 1 for stream 0, which drivers can't use */
3605 return num_streams - 1;
3606
3607cleanup:
3608 /* If it didn't work, free the streams! */
3609 for (i = 0; i < num_eps; i++) {
3610 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3611 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3612 vdev->eps[ep_index].stream_info = NULL;
3613 /* FIXME Unset maxPstreams in endpoint context and
3614 * update deq ptr to point to normal string ring.
3615 */
3616 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3617 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3618 xhci_endpoint_zero(xhci, vdev, eps[i]);
3619 }
3620 xhci_free_command(xhci, config_cmd);
3621 return -ENOMEM;
3622}
3623
3624/* Transition the endpoint from using streams to being a "normal" endpoint
3625 * without streams.
3626 *
3627 * Modify the endpoint context state, submit a configure endpoint command,
3628 * and free all endpoint rings for streams if that completes successfully.
3629 */
3630static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3631 struct usb_host_endpoint **eps, unsigned int num_eps,
3632 gfp_t mem_flags)
3633{
3634 int i, ret;
3635 struct xhci_hcd *xhci;
3636 struct xhci_virt_device *vdev;
3637 struct xhci_command *command;
3638 struct xhci_input_control_ctx *ctrl_ctx;
3639 unsigned int ep_index;
3640 unsigned long flags;
3641 u32 changed_ep_bitmask;
3642
3643 xhci = hcd_to_xhci(hcd);
3644 vdev = xhci->devs[udev->slot_id];
3645
3646 /* Set up a configure endpoint command to remove the streams rings */
3647 spin_lock_irqsave(&xhci->lock, flags);
3648 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3649 udev, eps, num_eps);
3650 if (changed_ep_bitmask == 0) {
3651 spin_unlock_irqrestore(&xhci->lock, flags);
3652 return -EINVAL;
3653 }
3654
3655 /* Use the xhci_command structure from the first endpoint. We may have
3656 * allocated too many, but the driver may call xhci_free_streams() for
3657 * each endpoint it grouped into one call to xhci_alloc_streams().
3658 */
3659 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3660 command = vdev->eps[ep_index].stream_info->free_streams_command;
3661 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3662 if (!ctrl_ctx) {
3663 spin_unlock_irqrestore(&xhci->lock, flags);
3664 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3665 __func__);
3666 return -EINVAL;
3667 }
3668
3669 for (i = 0; i < num_eps; i++) {
3670 struct xhci_ep_ctx *ep_ctx;
3671
3672 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3673 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3674 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3675 EP_GETTING_NO_STREAMS;
3676
3677 xhci_endpoint_copy(xhci, command->in_ctx,
3678 vdev->out_ctx, ep_index);
3679 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3680 &vdev->eps[ep_index]);
3681 }
3682 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3683 vdev->out_ctx, ctrl_ctx,
3684 changed_ep_bitmask, changed_ep_bitmask);
3685 spin_unlock_irqrestore(&xhci->lock, flags);
3686
3687 /* Issue and wait for the configure endpoint command,
3688 * which must succeed.
3689 */
3690 ret = xhci_configure_endpoint(xhci, udev, command,
3691 false, true);
3692
3693 /* xHC rejected the configure endpoint command for some reason, so we
3694 * leave the streams rings intact.
3695 */
3696 if (ret < 0)
3697 return ret;
3698
3699 spin_lock_irqsave(&xhci->lock, flags);
3700 for (i = 0; i < num_eps; i++) {
3701 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3702 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3703 vdev->eps[ep_index].stream_info = NULL;
3704 /* FIXME Unset maxPstreams in endpoint context and
3705 * update deq ptr to point to normal string ring.
3706 */
3707 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3708 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3709 }
3710 spin_unlock_irqrestore(&xhci->lock, flags);
3711
3712 return 0;
3713}
3714
3715/*
3716 * Deletes endpoint resources for endpoints that were active before a Reset
3717 * Device command, or a Disable Slot command. The Reset Device command leaves
3718 * the control endpoint intact, whereas the Disable Slot command deletes it.
3719 *
3720 * Must be called with xhci->lock held.
3721 */
3722void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3723 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3724{
3725 int i;
3726 unsigned int num_dropped_eps = 0;
3727 unsigned int drop_flags = 0;
3728
3729 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3730 if (virt_dev->eps[i].ring) {
3731 drop_flags |= 1 << i;
3732 num_dropped_eps++;
3733 }
3734 }
3735 xhci->num_active_eps -= num_dropped_eps;
3736 if (num_dropped_eps)
3737 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3738 "Dropped %u ep ctxs, flags = 0x%x, "
3739 "%u now active.",
3740 num_dropped_eps, drop_flags,
3741 xhci->num_active_eps);
3742}
3743
3744static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
3745
3746/*
3747 * This submits a Reset Device Command, which will set the device state to 0,
3748 * set the device address to 0, and disable all the endpoints except the default
3749 * control endpoint. The USB core should come back and call
3750 * xhci_address_device(), and then re-set up the configuration. If this is
3751 * called because of a usb_reset_and_verify_device(), then the old alternate
3752 * settings will be re-installed through the normal bandwidth allocation
3753 * functions.
3754 *
3755 * Wait for the Reset Device command to finish. Remove all structures
3756 * associated with the endpoints that were disabled. Clear the input device
3757 * structure? Reset the control endpoint 0 max packet size?
3758 *
3759 * If the virt_dev to be reset does not exist or does not match the udev,
3760 * it means the device is lost, possibly due to the xHC restore error and
3761 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3762 * re-allocate the device.
3763 */
3764static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3765 struct usb_device *udev)
3766{
3767 int ret, i;
3768 unsigned long flags;
3769 struct xhci_hcd *xhci;
3770 unsigned int slot_id;
3771 struct xhci_virt_device *virt_dev;
3772 struct xhci_command *reset_device_cmd;
3773 struct xhci_slot_ctx *slot_ctx;
3774 int old_active_eps = 0;
3775
3776 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3777 if (ret <= 0)
3778 return ret;
3779 xhci = hcd_to_xhci(hcd);
3780 slot_id = udev->slot_id;
3781 virt_dev = xhci->devs[slot_id];
3782 if (!virt_dev) {
3783 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3784 "not exist. Re-allocate the device\n", slot_id);
3785 ret = xhci_alloc_dev(hcd, udev);
3786 if (ret == 1)
3787 return 0;
3788 else
3789 return -EINVAL;
3790 }
3791
3792 if (virt_dev->tt_info)
3793 old_active_eps = virt_dev->tt_info->active_eps;
3794
3795 if (virt_dev->udev != udev) {
3796 /* If the virt_dev and the udev does not match, this virt_dev
3797 * may belong to another udev.
3798 * Re-allocate the device.
3799 */
3800 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3801 "not match the udev. Re-allocate the device\n",
3802 slot_id);
3803 ret = xhci_alloc_dev(hcd, udev);
3804 if (ret == 1)
3805 return 0;
3806 else
3807 return -EINVAL;
3808 }
3809
3810 /* If device is not setup, there is no point in resetting it */
3811 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3812 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3813 SLOT_STATE_DISABLED)
3814 return 0;
3815
3816 if (xhci->quirks & XHCI_ETRON_HOST) {
3817 /*
3818 * Obtaining a new device slot to inform the xHCI host that
3819 * the USB device has been reset.
3820 */
3821 ret = xhci_disable_slot(xhci, udev->slot_id);
3822 xhci_free_virt_device(xhci, udev->slot_id);
3823 if (!ret) {
3824 ret = xhci_alloc_dev(hcd, udev);
3825 if (ret == 1)
3826 ret = 0;
3827 else
3828 ret = -EINVAL;
3829 }
3830 return ret;
3831 }
3832
3833 trace_xhci_discover_or_reset_device(slot_ctx);
3834
3835 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3836 /* Allocate the command structure that holds the struct completion.
3837 * Assume we're in process context, since the normal device reset
3838 * process has to wait for the device anyway. Storage devices are
3839 * reset as part of error handling, so use GFP_NOIO instead of
3840 * GFP_KERNEL.
3841 */
3842 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3843 if (!reset_device_cmd) {
3844 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3845 return -ENOMEM;
3846 }
3847
3848 /* Attempt to submit the Reset Device command to the command ring */
3849 spin_lock_irqsave(&xhci->lock, flags);
3850
3851 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3852 if (ret) {
3853 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3854 spin_unlock_irqrestore(&xhci->lock, flags);
3855 goto command_cleanup;
3856 }
3857 xhci_ring_cmd_db(xhci);
3858 spin_unlock_irqrestore(&xhci->lock, flags);
3859
3860 /* Wait for the Reset Device command to finish */
3861 wait_for_completion(reset_device_cmd->completion);
3862
3863 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3864 * unless we tried to reset a slot ID that wasn't enabled,
3865 * or the device wasn't in the addressed or configured state.
3866 */
3867 ret = reset_device_cmd->status;
3868 switch (ret) {
3869 case COMP_COMMAND_ABORTED:
3870 case COMP_COMMAND_RING_STOPPED:
3871 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3872 ret = -ETIME;
3873 goto command_cleanup;
3874 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3875 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3876 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3877 slot_id,
3878 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3879 xhci_dbg(xhci, "Not freeing device rings.\n");
3880 /* Don't treat this as an error. May change my mind later. */
3881 ret = 0;
3882 goto command_cleanup;
3883 case COMP_SUCCESS:
3884 xhci_dbg(xhci, "Successful reset device command.\n");
3885 break;
3886 default:
3887 if (xhci_is_vendor_info_code(xhci, ret))
3888 break;
3889 xhci_warn(xhci, "Unknown completion code %u for "
3890 "reset device command.\n", ret);
3891 ret = -EINVAL;
3892 goto command_cleanup;
3893 }
3894
3895 /* Free up host controller endpoint resources */
3896 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3897 spin_lock_irqsave(&xhci->lock, flags);
3898 /* Don't delete the default control endpoint resources */
3899 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3900 spin_unlock_irqrestore(&xhci->lock, flags);
3901 }
3902
3903 /* Everything but endpoint 0 is disabled, so free the rings. */
3904 for (i = 1; i < 31; i++) {
3905 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3906
3907 if (ep->ep_state & EP_HAS_STREAMS) {
3908 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3909 xhci_get_endpoint_address(i));
3910 xhci_free_stream_info(xhci, ep->stream_info);
3911 ep->stream_info = NULL;
3912 ep->ep_state &= ~EP_HAS_STREAMS;
3913 }
3914
3915 if (ep->ring) {
3916 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3917 xhci_free_endpoint_ring(xhci, virt_dev, i);
3918 }
3919 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3920 xhci_drop_ep_from_interval_table(xhci,
3921 &virt_dev->eps[i].bw_info,
3922 virt_dev->bw_table,
3923 udev,
3924 &virt_dev->eps[i],
3925 virt_dev->tt_info);
3926 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3927 }
3928 /* If necessary, update the number of active TTs on this root port */
3929 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3930 virt_dev->flags = 0;
3931 ret = 0;
3932
3933command_cleanup:
3934 xhci_free_command(xhci, reset_device_cmd);
3935 return ret;
3936}
3937
3938/*
3939 * At this point, the struct usb_device is about to go away, the device has
3940 * disconnected, and all traffic has been stopped and the endpoints have been
3941 * disabled. Free any HC data structures associated with that device.
3942 */
3943static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3944{
3945 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3946 struct xhci_virt_device *virt_dev;
3947 struct xhci_slot_ctx *slot_ctx;
3948 unsigned long flags;
3949 int i, ret;
3950
3951 /*
3952 * We called pm_runtime_get_noresume when the device was attached.
3953 * Decrement the counter here to allow controller to runtime suspend
3954 * if no devices remain.
3955 */
3956 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3957 pm_runtime_put_noidle(hcd->self.controller);
3958
3959 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3960 /* If the host is halted due to driver unload, we still need to free the
3961 * device.
3962 */
3963 if (ret <= 0 && ret != -ENODEV)
3964 return;
3965
3966 virt_dev = xhci->devs[udev->slot_id];
3967 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3968 trace_xhci_free_dev(slot_ctx);
3969
3970 /* Stop any wayward timer functions (which may grab the lock) */
3971 for (i = 0; i < 31; i++)
3972 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3973 virt_dev->udev = NULL;
3974 xhci_disable_slot(xhci, udev->slot_id);
3975
3976 spin_lock_irqsave(&xhci->lock, flags);
3977 xhci_free_virt_device(xhci, udev->slot_id);
3978 spin_unlock_irqrestore(&xhci->lock, flags);
3979
3980}
3981
3982int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3983{
3984 struct xhci_command *command;
3985 unsigned long flags;
3986 u32 state;
3987 int ret;
3988
3989 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3990 if (!command)
3991 return -ENOMEM;
3992
3993 xhci_debugfs_remove_slot(xhci, slot_id);
3994
3995 spin_lock_irqsave(&xhci->lock, flags);
3996 /* Don't disable the slot if the host controller is dead. */
3997 state = readl(&xhci->op_regs->status);
3998 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3999 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4000 spin_unlock_irqrestore(&xhci->lock, flags);
4001 kfree(command);
4002 return -ENODEV;
4003 }
4004
4005 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4006 slot_id);
4007 if (ret) {
4008 spin_unlock_irqrestore(&xhci->lock, flags);
4009 kfree(command);
4010 return ret;
4011 }
4012 xhci_ring_cmd_db(xhci);
4013 spin_unlock_irqrestore(&xhci->lock, flags);
4014
4015 wait_for_completion(command->completion);
4016
4017 if (command->status != COMP_SUCCESS)
4018 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4019 slot_id, command->status);
4020
4021 xhci_free_command(xhci, command);
4022
4023 return 0;
4024}
4025
4026/*
4027 * Checks if we have enough host controller resources for the default control
4028 * endpoint.
4029 *
4030 * Must be called with xhci->lock held.
4031 */
4032static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4033{
4034 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4035 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4036 "Not enough ep ctxs: "
4037 "%u active, need to add 1, limit is %u.",
4038 xhci->num_active_eps, xhci->limit_active_eps);
4039 return -ENOMEM;
4040 }
4041 xhci->num_active_eps += 1;
4042 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4043 "Adding 1 ep ctx, %u now active.",
4044 xhci->num_active_eps);
4045 return 0;
4046}
4047
4048
4049/*
4050 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4051 * timed out, or allocating memory failed. Returns 1 on success.
4052 */
4053int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4054{
4055 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4056 struct xhci_virt_device *vdev;
4057 struct xhci_slot_ctx *slot_ctx;
4058 unsigned long flags;
4059 int ret, slot_id;
4060 struct xhci_command *command;
4061
4062 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4063 if (!command)
4064 return 0;
4065
4066 spin_lock_irqsave(&xhci->lock, flags);
4067 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4068 if (ret) {
4069 spin_unlock_irqrestore(&xhci->lock, flags);
4070 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4071 xhci_free_command(xhci, command);
4072 return 0;
4073 }
4074 xhci_ring_cmd_db(xhci);
4075 spin_unlock_irqrestore(&xhci->lock, flags);
4076
4077 wait_for_completion(command->completion);
4078 slot_id = command->slot_id;
4079
4080 if (!slot_id || command->status != COMP_SUCCESS) {
4081 xhci_err(xhci, "Error while assigning device slot ID: %s\n",
4082 xhci_trb_comp_code_string(command->status));
4083 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4084 HCS_MAX_SLOTS(
4085 readl(&xhci->cap_regs->hcs_params1)));
4086 xhci_free_command(xhci, command);
4087 return 0;
4088 }
4089
4090 xhci_free_command(xhci, command);
4091
4092 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4093 spin_lock_irqsave(&xhci->lock, flags);
4094 ret = xhci_reserve_host_control_ep_resources(xhci);
4095 if (ret) {
4096 spin_unlock_irqrestore(&xhci->lock, flags);
4097 xhci_warn(xhci, "Not enough host resources, "
4098 "active endpoint contexts = %u\n",
4099 xhci->num_active_eps);
4100 goto disable_slot;
4101 }
4102 spin_unlock_irqrestore(&xhci->lock, flags);
4103 }
4104 /* Use GFP_NOIO, since this function can be called from
4105 * xhci_discover_or_reset_device(), which may be called as part of
4106 * mass storage driver error handling.
4107 */
4108 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4109 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4110 goto disable_slot;
4111 }
4112 vdev = xhci->devs[slot_id];
4113 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4114 trace_xhci_alloc_dev(slot_ctx);
4115
4116 udev->slot_id = slot_id;
4117
4118 xhci_debugfs_create_slot(xhci, slot_id);
4119
4120 /*
4121 * If resetting upon resume, we can't put the controller into runtime
4122 * suspend if there is a device attached.
4123 */
4124 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4125 pm_runtime_get_noresume(hcd->self.controller);
4126
4127 /* Is this a LS or FS device under a HS hub? */
4128 /* Hub or peripherial? */
4129 return 1;
4130
4131disable_slot:
4132 xhci_disable_slot(xhci, udev->slot_id);
4133 xhci_free_virt_device(xhci, udev->slot_id);
4134
4135 return 0;
4136}
4137
4138/**
4139 * xhci_setup_device - issues an Address Device command to assign a unique
4140 * USB bus address.
4141 * @hcd: USB host controller data structure.
4142 * @udev: USB dev structure representing the connected device.
4143 * @setup: Enum specifying setup mode: address only or with context.
4144 * @timeout_ms: Max wait time (ms) for the command operation to complete.
4145 *
4146 * Return: 0 if successful; otherwise, negative error code.
4147 */
4148static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4149 enum xhci_setup_dev setup, unsigned int timeout_ms)
4150{
4151 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4152 unsigned long flags;
4153 struct xhci_virt_device *virt_dev;
4154 int ret = 0;
4155 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4156 struct xhci_slot_ctx *slot_ctx;
4157 struct xhci_input_control_ctx *ctrl_ctx;
4158 u64 temp_64;
4159 struct xhci_command *command = NULL;
4160
4161 mutex_lock(&xhci->mutex);
4162
4163 if (xhci->xhc_state) { /* dying, removing or halted */
4164 ret = -ESHUTDOWN;
4165 goto out;
4166 }
4167
4168 if (!udev->slot_id) {
4169 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4170 "Bad Slot ID %d", udev->slot_id);
4171 ret = -EINVAL;
4172 goto out;
4173 }
4174
4175 virt_dev = xhci->devs[udev->slot_id];
4176
4177 if (WARN_ON(!virt_dev)) {
4178 /*
4179 * In plug/unplug torture test with an NEC controller,
4180 * a zero-dereference was observed once due to virt_dev = 0.
4181 * Print useful debug rather than crash if it is observed again!
4182 */
4183 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4184 udev->slot_id);
4185 ret = -EINVAL;
4186 goto out;
4187 }
4188 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4189 trace_xhci_setup_device_slot(slot_ctx);
4190
4191 if (setup == SETUP_CONTEXT_ONLY) {
4192 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4193 SLOT_STATE_DEFAULT) {
4194 xhci_dbg(xhci, "Slot already in default state\n");
4195 goto out;
4196 }
4197 }
4198
4199 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4200 if (!command) {
4201 ret = -ENOMEM;
4202 goto out;
4203 }
4204
4205 command->in_ctx = virt_dev->in_ctx;
4206 command->timeout_ms = timeout_ms;
4207
4208 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4209 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4210 if (!ctrl_ctx) {
4211 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4212 __func__);
4213 ret = -EINVAL;
4214 goto out;
4215 }
4216 /*
4217 * If this is the first Set Address since device plug-in or
4218 * virt_device realloaction after a resume with an xHCI power loss,
4219 * then set up the slot context.
4220 */
4221 if (!slot_ctx->dev_info)
4222 xhci_setup_addressable_virt_dev(xhci, udev);
4223 /* Otherwise, update the control endpoint ring enqueue pointer. */
4224 else
4225 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4226 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4227 ctrl_ctx->drop_flags = 0;
4228
4229 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4230 le32_to_cpu(slot_ctx->dev_info) >> 27);
4231
4232 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4233 spin_lock_irqsave(&xhci->lock, flags);
4234 trace_xhci_setup_device(virt_dev);
4235 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4236 udev->slot_id, setup);
4237 if (ret) {
4238 spin_unlock_irqrestore(&xhci->lock, flags);
4239 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4240 "FIXME: allocate a command ring segment");
4241 goto out;
4242 }
4243 xhci_ring_cmd_db(xhci);
4244 spin_unlock_irqrestore(&xhci->lock, flags);
4245
4246 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4247 wait_for_completion(command->completion);
4248
4249 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4250 * the SetAddress() "recovery interval" required by USB and aborting the
4251 * command on a timeout.
4252 */
4253 switch (command->status) {
4254 case COMP_COMMAND_ABORTED:
4255 case COMP_COMMAND_RING_STOPPED:
4256 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4257 ret = -ETIME;
4258 break;
4259 case COMP_CONTEXT_STATE_ERROR:
4260 case COMP_SLOT_NOT_ENABLED_ERROR:
4261 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4262 act, udev->slot_id);
4263 ret = -EINVAL;
4264 break;
4265 case COMP_USB_TRANSACTION_ERROR:
4266 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4267
4268 mutex_unlock(&xhci->mutex);
4269 ret = xhci_disable_slot(xhci, udev->slot_id);
4270 xhci_free_virt_device(xhci, udev->slot_id);
4271 if (!ret) {
4272 if (xhci_alloc_dev(hcd, udev) == 1)
4273 xhci_setup_addressable_virt_dev(xhci, udev);
4274 }
4275 kfree(command->completion);
4276 kfree(command);
4277 return -EPROTO;
4278 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4279 dev_warn(&udev->dev,
4280 "ERROR: Incompatible device for setup %s command\n", act);
4281 ret = -ENODEV;
4282 break;
4283 case COMP_SUCCESS:
4284 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4285 "Successful setup %s command", act);
4286 break;
4287 default:
4288 xhci_err(xhci,
4289 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4290 act, command->status);
4291 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4292 ret = -EINVAL;
4293 break;
4294 }
4295 if (ret)
4296 goto out;
4297 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4298 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4299 "Op regs DCBAA ptr = %#016llx", temp_64);
4300 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4301 "Slot ID %d dcbaa entry @%p = %#016llx",
4302 udev->slot_id,
4303 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4304 (unsigned long long)
4305 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4306 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4307 "Output Context DMA address = %#08llx",
4308 (unsigned long long)virt_dev->out_ctx->dma);
4309 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4310 le32_to_cpu(slot_ctx->dev_info) >> 27);
4311 /*
4312 * USB core uses address 1 for the roothubs, so we add one to the
4313 * address given back to us by the HC.
4314 */
4315 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4316 le32_to_cpu(slot_ctx->dev_info) >> 27);
4317 /* Zero the input context control for later use */
4318 ctrl_ctx->add_flags = 0;
4319 ctrl_ctx->drop_flags = 0;
4320 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4321 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4322
4323 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4324 "Internal device address = %d",
4325 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4326out:
4327 mutex_unlock(&xhci->mutex);
4328 if (command) {
4329 kfree(command->completion);
4330 kfree(command);
4331 }
4332 return ret;
4333}
4334
4335static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev,
4336 unsigned int timeout_ms)
4337{
4338 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS, timeout_ms);
4339}
4340
4341static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4342{
4343 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY,
4344 XHCI_CMD_DEFAULT_TIMEOUT);
4345}
4346
4347/*
4348 * Transfer the port index into real index in the HW port status
4349 * registers. Caculate offset between the port's PORTSC register
4350 * and port status base. Divide the number of per port register
4351 * to get the real index. The raw port number bases 1.
4352 */
4353int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4354{
4355 struct xhci_hub *rhub;
4356
4357 rhub = xhci_get_rhub(hcd);
4358 return rhub->ports[port1 - 1]->hw_portnum + 1;
4359}
4360
4361/*
4362 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4363 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4364 */
4365static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4366 struct usb_device *udev, u16 max_exit_latency)
4367{
4368 struct xhci_virt_device *virt_dev;
4369 struct xhci_command *command;
4370 struct xhci_input_control_ctx *ctrl_ctx;
4371 struct xhci_slot_ctx *slot_ctx;
4372 unsigned long flags;
4373 int ret;
4374
4375 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4376 if (!command)
4377 return -ENOMEM;
4378
4379 spin_lock_irqsave(&xhci->lock, flags);
4380
4381 virt_dev = xhci->devs[udev->slot_id];
4382
4383 /*
4384 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4385 * xHC was re-initialized. Exit latency will be set later after
4386 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4387 */
4388
4389 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4390 spin_unlock_irqrestore(&xhci->lock, flags);
4391 xhci_free_command(xhci, command);
4392 return 0;
4393 }
4394
4395 /* Attempt to issue an Evaluate Context command to change the MEL. */
4396 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4397 if (!ctrl_ctx) {
4398 spin_unlock_irqrestore(&xhci->lock, flags);
4399 xhci_free_command(xhci, command);
4400 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4401 __func__);
4402 return -ENOMEM;
4403 }
4404
4405 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4406 spin_unlock_irqrestore(&xhci->lock, flags);
4407
4408 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4409 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4410 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4411 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4412 slot_ctx->dev_state = 0;
4413
4414 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4415 "Set up evaluate context for LPM MEL change.");
4416
4417 /* Issue and wait for the evaluate context command. */
4418 ret = xhci_configure_endpoint(xhci, udev, command,
4419 true, true);
4420
4421 if (!ret) {
4422 spin_lock_irqsave(&xhci->lock, flags);
4423 virt_dev->current_mel = max_exit_latency;
4424 spin_unlock_irqrestore(&xhci->lock, flags);
4425 }
4426
4427 xhci_free_command(xhci, command);
4428
4429 return ret;
4430}
4431
4432#ifdef CONFIG_PM
4433
4434/* BESL to HIRD Encoding array for USB2 LPM */
4435static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4436 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4437
4438/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4439static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4440 struct usb_device *udev)
4441{
4442 int u2del, besl, besl_host;
4443 int besl_device = 0;
4444 u32 field;
4445
4446 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4447 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4448
4449 if (field & USB_BESL_SUPPORT) {
4450 for (besl_host = 0; besl_host < 16; besl_host++) {
4451 if (xhci_besl_encoding[besl_host] >= u2del)
4452 break;
4453 }
4454 /* Use baseline BESL value as default */
4455 if (field & USB_BESL_BASELINE_VALID)
4456 besl_device = USB_GET_BESL_BASELINE(field);
4457 else if (field & USB_BESL_DEEP_VALID)
4458 besl_device = USB_GET_BESL_DEEP(field);
4459 } else {
4460 if (u2del <= 50)
4461 besl_host = 0;
4462 else
4463 besl_host = (u2del - 51) / 75 + 1;
4464 }
4465
4466 besl = besl_host + besl_device;
4467 if (besl > 15)
4468 besl = 15;
4469
4470 return besl;
4471}
4472
4473/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4474static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4475{
4476 u32 field;
4477 int l1;
4478 int besld = 0;
4479 int hirdm = 0;
4480
4481 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4482
4483 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4484 l1 = udev->l1_params.timeout / 256;
4485
4486 /* device has preferred BESLD */
4487 if (field & USB_BESL_DEEP_VALID) {
4488 besld = USB_GET_BESL_DEEP(field);
4489 hirdm = 1;
4490 }
4491
4492 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4493}
4494
4495static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4496 struct usb_device *udev, int enable)
4497{
4498 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4499 struct xhci_port **ports;
4500 __le32 __iomem *pm_addr, *hlpm_addr;
4501 u32 pm_val, hlpm_val, field;
4502 unsigned int port_num;
4503 unsigned long flags;
4504 int hird, exit_latency;
4505 int ret;
4506
4507 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4508 return -EPERM;
4509
4510 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4511 !udev->lpm_capable)
4512 return -EPERM;
4513
4514 if (!udev->parent || udev->parent->parent ||
4515 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4516 return -EPERM;
4517
4518 if (udev->usb2_hw_lpm_capable != 1)
4519 return -EPERM;
4520
4521 spin_lock_irqsave(&xhci->lock, flags);
4522
4523 ports = xhci->usb2_rhub.ports;
4524 port_num = udev->portnum - 1;
4525 pm_addr = ports[port_num]->addr + PORTPMSC;
4526 pm_val = readl(pm_addr);
4527 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4528
4529 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4530 enable ? "enable" : "disable", port_num + 1);
4531
4532 if (enable) {
4533 /* Host supports BESL timeout instead of HIRD */
4534 if (udev->usb2_hw_lpm_besl_capable) {
4535 /* if device doesn't have a preferred BESL value use a
4536 * default one which works with mixed HIRD and BESL
4537 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4538 */
4539 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4540 if ((field & USB_BESL_SUPPORT) &&
4541 (field & USB_BESL_BASELINE_VALID))
4542 hird = USB_GET_BESL_BASELINE(field);
4543 else
4544 hird = udev->l1_params.besl;
4545
4546 exit_latency = xhci_besl_encoding[hird];
4547 spin_unlock_irqrestore(&xhci->lock, flags);
4548
4549 ret = xhci_change_max_exit_latency(xhci, udev,
4550 exit_latency);
4551 if (ret < 0)
4552 return ret;
4553 spin_lock_irqsave(&xhci->lock, flags);
4554
4555 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4556 writel(hlpm_val, hlpm_addr);
4557 /* flush write */
4558 readl(hlpm_addr);
4559 } else {
4560 hird = xhci_calculate_hird_besl(xhci, udev);
4561 }
4562
4563 pm_val &= ~PORT_HIRD_MASK;
4564 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4565 writel(pm_val, pm_addr);
4566 pm_val = readl(pm_addr);
4567 pm_val |= PORT_HLE;
4568 writel(pm_val, pm_addr);
4569 /* flush write */
4570 readl(pm_addr);
4571 } else {
4572 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4573 writel(pm_val, pm_addr);
4574 /* flush write */
4575 readl(pm_addr);
4576 if (udev->usb2_hw_lpm_besl_capable) {
4577 spin_unlock_irqrestore(&xhci->lock, flags);
4578 xhci_change_max_exit_latency(xhci, udev, 0);
4579 readl_poll_timeout(ports[port_num]->addr, pm_val,
4580 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4581 100, 10000);
4582 return 0;
4583 }
4584 }
4585
4586 spin_unlock_irqrestore(&xhci->lock, flags);
4587 return 0;
4588}
4589
4590static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4591{
4592 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4593 struct xhci_port *port;
4594 u32 capability;
4595
4596 /* Check if USB3 device at root port is tunneled over USB4 */
4597 if (hcd->speed >= HCD_USB3 && !udev->parent->parent) {
4598 port = xhci->usb3_rhub.ports[udev->portnum - 1];
4599
4600 udev->tunnel_mode = xhci_port_is_tunneled(xhci, port);
4601 if (udev->tunnel_mode == USB_LINK_UNKNOWN)
4602 dev_dbg(&udev->dev, "link tunnel state unknown\n");
4603 else if (udev->tunnel_mode == USB_LINK_TUNNELED)
4604 dev_dbg(&udev->dev, "tunneled over USB4 link\n");
4605 else if (udev->tunnel_mode == USB_LINK_NATIVE)
4606 dev_dbg(&udev->dev, "native USB 3.x link\n");
4607 return 0;
4608 }
4609
4610 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable || !xhci->hw_lpm_support)
4611 return 0;
4612
4613 /* we only support lpm for non-hub device connected to root hub yet */
4614 if (!udev->parent || udev->parent->parent ||
4615 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4616 return 0;
4617
4618 port = xhci->usb2_rhub.ports[udev->portnum - 1];
4619 capability = port->port_cap->protocol_caps;
4620
4621 if (capability & XHCI_HLC) {
4622 udev->usb2_hw_lpm_capable = 1;
4623 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4624 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4625 if (capability & XHCI_BLC)
4626 udev->usb2_hw_lpm_besl_capable = 1;
4627 }
4628
4629 return 0;
4630}
4631
4632/*---------------------- USB 3.0 Link PM functions ------------------------*/
4633
4634/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4635static unsigned long long xhci_service_interval_to_ns(
4636 struct usb_endpoint_descriptor *desc)
4637{
4638 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4639}
4640
4641static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4642 enum usb3_link_state state)
4643{
4644 unsigned long long sel;
4645 unsigned long long pel;
4646 unsigned int max_sel_pel;
4647 char *state_name;
4648
4649 switch (state) {
4650 case USB3_LPM_U1:
4651 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4652 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4653 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4654 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4655 state_name = "U1";
4656 break;
4657 case USB3_LPM_U2:
4658 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4659 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4660 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4661 state_name = "U2";
4662 break;
4663 default:
4664 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4665 __func__);
4666 return USB3_LPM_DISABLED;
4667 }
4668
4669 if (sel <= max_sel_pel && pel <= max_sel_pel)
4670 return USB3_LPM_DEVICE_INITIATED;
4671
4672 if (sel > max_sel_pel)
4673 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4674 "due to long SEL %llu ms\n",
4675 state_name, sel);
4676 else
4677 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4678 "due to long PEL %llu ms\n",
4679 state_name, pel);
4680 return USB3_LPM_DISABLED;
4681}
4682
4683/* The U1 timeout should be the maximum of the following values:
4684 * - For control endpoints, U1 system exit latency (SEL) * 3
4685 * - For bulk endpoints, U1 SEL * 5
4686 * - For interrupt endpoints:
4687 * - Notification EPs, U1 SEL * 3
4688 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4689 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4690 */
4691static unsigned long long xhci_calculate_intel_u1_timeout(
4692 struct usb_device *udev,
4693 struct usb_endpoint_descriptor *desc)
4694{
4695 unsigned long long timeout_ns;
4696 int ep_type;
4697 int intr_type;
4698
4699 ep_type = usb_endpoint_type(desc);
4700 switch (ep_type) {
4701 case USB_ENDPOINT_XFER_CONTROL:
4702 timeout_ns = udev->u1_params.sel * 3;
4703 break;
4704 case USB_ENDPOINT_XFER_BULK:
4705 timeout_ns = udev->u1_params.sel * 5;
4706 break;
4707 case USB_ENDPOINT_XFER_INT:
4708 intr_type = usb_endpoint_interrupt_type(desc);
4709 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4710 timeout_ns = udev->u1_params.sel * 3;
4711 break;
4712 }
4713 /* Otherwise the calculation is the same as isoc eps */
4714 fallthrough;
4715 case USB_ENDPOINT_XFER_ISOC:
4716 timeout_ns = xhci_service_interval_to_ns(desc);
4717 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4718 if (timeout_ns < udev->u1_params.sel * 2)
4719 timeout_ns = udev->u1_params.sel * 2;
4720 break;
4721 default:
4722 return 0;
4723 }
4724
4725 return timeout_ns;
4726}
4727
4728/* Returns the hub-encoded U1 timeout value. */
4729static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4730 struct usb_device *udev,
4731 struct usb_endpoint_descriptor *desc)
4732{
4733 unsigned long long timeout_ns;
4734
4735 /* Prevent U1 if service interval is shorter than U1 exit latency */
4736 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4737 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4738 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4739 return USB3_LPM_DISABLED;
4740 }
4741 }
4742
4743 if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4744 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4745 else
4746 timeout_ns = udev->u1_params.sel;
4747
4748 /* The U1 timeout is encoded in 1us intervals.
4749 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4750 */
4751 if (timeout_ns == USB3_LPM_DISABLED)
4752 timeout_ns = 1;
4753 else
4754 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4755
4756 /* If the necessary timeout value is bigger than what we can set in the
4757 * USB 3.0 hub, we have to disable hub-initiated U1.
4758 */
4759 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4760 return timeout_ns;
4761 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4762 "due to long timeout %llu ms\n", timeout_ns);
4763 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4764}
4765
4766/* The U2 timeout should be the maximum of:
4767 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4768 * - largest bInterval of any active periodic endpoint (to avoid going
4769 * into lower power link states between intervals).
4770 * - the U2 Exit Latency of the device
4771 */
4772static unsigned long long xhci_calculate_intel_u2_timeout(
4773 struct usb_device *udev,
4774 struct usb_endpoint_descriptor *desc)
4775{
4776 unsigned long long timeout_ns;
4777 unsigned long long u2_del_ns;
4778
4779 timeout_ns = 10 * 1000 * 1000;
4780
4781 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4782 (xhci_service_interval_to_ns(desc) > timeout_ns))
4783 timeout_ns = xhci_service_interval_to_ns(desc);
4784
4785 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4786 if (u2_del_ns > timeout_ns)
4787 timeout_ns = u2_del_ns;
4788
4789 return timeout_ns;
4790}
4791
4792/* Returns the hub-encoded U2 timeout value. */
4793static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4794 struct usb_device *udev,
4795 struct usb_endpoint_descriptor *desc)
4796{
4797 unsigned long long timeout_ns;
4798
4799 /* Prevent U2 if service interval is shorter than U2 exit latency */
4800 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4801 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4802 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4803 return USB3_LPM_DISABLED;
4804 }
4805 }
4806
4807 if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4808 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4809 else
4810 timeout_ns = udev->u2_params.sel;
4811
4812 /* The U2 timeout is encoded in 256us intervals */
4813 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4814 /* If the necessary timeout value is bigger than what we can set in the
4815 * USB 3.0 hub, we have to disable hub-initiated U2.
4816 */
4817 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4818 return timeout_ns;
4819 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4820 "due to long timeout %llu ms\n", timeout_ns);
4821 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4822}
4823
4824static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4825 struct usb_device *udev,
4826 struct usb_endpoint_descriptor *desc,
4827 enum usb3_link_state state,
4828 u16 *timeout)
4829{
4830 if (state == USB3_LPM_U1)
4831 return xhci_calculate_u1_timeout(xhci, udev, desc);
4832 else if (state == USB3_LPM_U2)
4833 return xhci_calculate_u2_timeout(xhci, udev, desc);
4834
4835 return USB3_LPM_DISABLED;
4836}
4837
4838static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4839 struct usb_device *udev,
4840 struct usb_endpoint_descriptor *desc,
4841 enum usb3_link_state state,
4842 u16 *timeout)
4843{
4844 u16 alt_timeout;
4845
4846 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4847 desc, state, timeout);
4848
4849 /* If we found we can't enable hub-initiated LPM, and
4850 * the U1 or U2 exit latency was too high to allow
4851 * device-initiated LPM as well, then we will disable LPM
4852 * for this device, so stop searching any further.
4853 */
4854 if (alt_timeout == USB3_LPM_DISABLED) {
4855 *timeout = alt_timeout;
4856 return -E2BIG;
4857 }
4858 if (alt_timeout > *timeout)
4859 *timeout = alt_timeout;
4860 return 0;
4861}
4862
4863static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4864 struct usb_device *udev,
4865 struct usb_host_interface *alt,
4866 enum usb3_link_state state,
4867 u16 *timeout)
4868{
4869 int j;
4870
4871 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4872 if (xhci_update_timeout_for_endpoint(xhci, udev,
4873 &alt->endpoint[j].desc, state, timeout))
4874 return -E2BIG;
4875 }
4876 return 0;
4877}
4878
4879static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4880 struct usb_device *udev,
4881 enum usb3_link_state state)
4882{
4883 struct usb_device *parent = udev->parent;
4884 int tier = 1; /* roothub is tier1 */
4885
4886 while (parent) {
4887 parent = parent->parent;
4888 tier++;
4889 }
4890
4891 if (xhci->quirks & XHCI_INTEL_HOST && tier > 3)
4892 goto fail;
4893 if (xhci->quirks & XHCI_ZHAOXIN_HOST && tier > 2)
4894 goto fail;
4895
4896 return 0;
4897fail:
4898 dev_dbg(&udev->dev, "Tier policy prevents U1/U2 LPM states for devices at tier %d\n",
4899 tier);
4900 return -E2BIG;
4901}
4902
4903/* Returns the U1 or U2 timeout that should be enabled.
4904 * If the tier check or timeout setting functions return with a non-zero exit
4905 * code, that means the timeout value has been finalized and we shouldn't look
4906 * at any more endpoints.
4907 */
4908static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4909 struct usb_device *udev, enum usb3_link_state state)
4910{
4911 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4912 struct usb_host_config *config;
4913 char *state_name;
4914 int i;
4915 u16 timeout = USB3_LPM_DISABLED;
4916
4917 if (state == USB3_LPM_U1)
4918 state_name = "U1";
4919 else if (state == USB3_LPM_U2)
4920 state_name = "U2";
4921 else {
4922 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4923 state);
4924 return timeout;
4925 }
4926
4927 /* Gather some information about the currently installed configuration
4928 * and alternate interface settings.
4929 */
4930 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4931 state, &timeout))
4932 return timeout;
4933
4934 config = udev->actconfig;
4935 if (!config)
4936 return timeout;
4937
4938 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4939 struct usb_driver *driver;
4940 struct usb_interface *intf = config->interface[i];
4941
4942 if (!intf)
4943 continue;
4944
4945 /* Check if any currently bound drivers want hub-initiated LPM
4946 * disabled.
4947 */
4948 if (intf->dev.driver) {
4949 driver = to_usb_driver(intf->dev.driver);
4950 if (driver && driver->disable_hub_initiated_lpm) {
4951 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4952 state_name, driver->name);
4953 timeout = xhci_get_timeout_no_hub_lpm(udev,
4954 state);
4955 if (timeout == USB3_LPM_DISABLED)
4956 return timeout;
4957 }
4958 }
4959
4960 /* Not sure how this could happen... */
4961 if (!intf->cur_altsetting)
4962 continue;
4963
4964 if (xhci_update_timeout_for_interface(xhci, udev,
4965 intf->cur_altsetting,
4966 state, &timeout))
4967 return timeout;
4968 }
4969 return timeout;
4970}
4971
4972static int calculate_max_exit_latency(struct usb_device *udev,
4973 enum usb3_link_state state_changed,
4974 u16 hub_encoded_timeout)
4975{
4976 unsigned long long u1_mel_us = 0;
4977 unsigned long long u2_mel_us = 0;
4978 unsigned long long mel_us = 0;
4979 bool disabling_u1;
4980 bool disabling_u2;
4981 bool enabling_u1;
4982 bool enabling_u2;
4983
4984 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4985 hub_encoded_timeout == USB3_LPM_DISABLED);
4986 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4987 hub_encoded_timeout == USB3_LPM_DISABLED);
4988
4989 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4990 hub_encoded_timeout != USB3_LPM_DISABLED);
4991 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4992 hub_encoded_timeout != USB3_LPM_DISABLED);
4993
4994 /* If U1 was already enabled and we're not disabling it,
4995 * or we're going to enable U1, account for the U1 max exit latency.
4996 */
4997 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4998 enabling_u1)
4999 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5000 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5001 enabling_u2)
5002 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5003
5004 mel_us = max(u1_mel_us, u2_mel_us);
5005
5006 /* xHCI host controller max exit latency field is only 16 bits wide. */
5007 if (mel_us > MAX_EXIT) {
5008 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5009 "is too big.\n", mel_us);
5010 return -E2BIG;
5011 }
5012 return mel_us;
5013}
5014
5015/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5016static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5017 struct usb_device *udev, enum usb3_link_state state)
5018{
5019 struct xhci_hcd *xhci;
5020 struct xhci_port *port;
5021 u16 hub_encoded_timeout;
5022 int mel;
5023 int ret;
5024
5025 xhci = hcd_to_xhci(hcd);
5026 /* The LPM timeout values are pretty host-controller specific, so don't
5027 * enable hub-initiated timeouts unless the vendor has provided
5028 * information about their timeout algorithm.
5029 */
5030 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5031 !xhci->devs[udev->slot_id])
5032 return USB3_LPM_DISABLED;
5033
5034 if (xhci_check_tier_policy(xhci, udev, state) < 0)
5035 return USB3_LPM_DISABLED;
5036
5037 /* If connected to root port then check port can handle lpm */
5038 if (udev->parent && !udev->parent->parent) {
5039 port = xhci->usb3_rhub.ports[udev->portnum - 1];
5040 if (port->lpm_incapable)
5041 return USB3_LPM_DISABLED;
5042 }
5043
5044 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5045 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5046 if (mel < 0) {
5047 /* Max Exit Latency is too big, disable LPM. */
5048 hub_encoded_timeout = USB3_LPM_DISABLED;
5049 mel = 0;
5050 }
5051
5052 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5053 if (ret)
5054 return ret;
5055 return hub_encoded_timeout;
5056}
5057
5058static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5059 struct usb_device *udev, enum usb3_link_state state)
5060{
5061 struct xhci_hcd *xhci;
5062 u16 mel;
5063
5064 xhci = hcd_to_xhci(hcd);
5065 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5066 !xhci->devs[udev->slot_id])
5067 return 0;
5068
5069 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5070 return xhci_change_max_exit_latency(xhci, udev, mel);
5071}
5072#else /* CONFIG_PM */
5073
5074static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5075 struct usb_device *udev, int enable)
5076{
5077 return 0;
5078}
5079
5080static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5081{
5082 return 0;
5083}
5084
5085static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5086 struct usb_device *udev, enum usb3_link_state state)
5087{
5088 return USB3_LPM_DISABLED;
5089}
5090
5091static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5092 struct usb_device *udev, enum usb3_link_state state)
5093{
5094 return 0;
5095}
5096#endif /* CONFIG_PM */
5097
5098/*-------------------------------------------------------------------------*/
5099
5100/* Once a hub descriptor is fetched for a device, we need to update the xHC's
5101 * internal data structures for the device.
5102 */
5103int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5104 struct usb_tt *tt, gfp_t mem_flags)
5105{
5106 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5107 struct xhci_virt_device *vdev;
5108 struct xhci_command *config_cmd;
5109 struct xhci_input_control_ctx *ctrl_ctx;
5110 struct xhci_slot_ctx *slot_ctx;
5111 unsigned long flags;
5112 unsigned think_time;
5113 int ret;
5114
5115 /* Ignore root hubs */
5116 if (!hdev->parent)
5117 return 0;
5118
5119 vdev = xhci->devs[hdev->slot_id];
5120 if (!vdev) {
5121 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5122 return -EINVAL;
5123 }
5124
5125 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5126 if (!config_cmd)
5127 return -ENOMEM;
5128
5129 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5130 if (!ctrl_ctx) {
5131 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5132 __func__);
5133 xhci_free_command(xhci, config_cmd);
5134 return -ENOMEM;
5135 }
5136
5137 spin_lock_irqsave(&xhci->lock, flags);
5138 if (hdev->speed == USB_SPEED_HIGH &&
5139 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5140 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5141 xhci_free_command(xhci, config_cmd);
5142 spin_unlock_irqrestore(&xhci->lock, flags);
5143 return -ENOMEM;
5144 }
5145
5146 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5147 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5148 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5149 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5150 /*
5151 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5152 * but it may be already set to 1 when setup an xHCI virtual
5153 * device, so clear it anyway.
5154 */
5155 if (tt->multi)
5156 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5157 else if (hdev->speed == USB_SPEED_FULL)
5158 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5159
5160 if (xhci->hci_version > 0x95) {
5161 xhci_dbg(xhci, "xHCI version %x needs hub "
5162 "TT think time and number of ports\n",
5163 (unsigned int) xhci->hci_version);
5164 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5165 /* Set TT think time - convert from ns to FS bit times.
5166 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5167 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5168 *
5169 * xHCI 1.0: this field shall be 0 if the device is not a
5170 * High-spped hub.
5171 */
5172 think_time = tt->think_time;
5173 if (think_time != 0)
5174 think_time = (think_time / 666) - 1;
5175 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5176 slot_ctx->tt_info |=
5177 cpu_to_le32(TT_THINK_TIME(think_time));
5178 } else {
5179 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5180 "TT think time or number of ports\n",
5181 (unsigned int) xhci->hci_version);
5182 }
5183 slot_ctx->dev_state = 0;
5184 spin_unlock_irqrestore(&xhci->lock, flags);
5185
5186 xhci_dbg(xhci, "Set up %s for hub device.\n",
5187 (xhci->hci_version > 0x95) ?
5188 "configure endpoint" : "evaluate context");
5189
5190 /* Issue and wait for the configure endpoint or
5191 * evaluate context command.
5192 */
5193 if (xhci->hci_version > 0x95)
5194 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5195 false, false);
5196 else
5197 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5198 true, false);
5199
5200 xhci_free_command(xhci, config_cmd);
5201 return ret;
5202}
5203EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5204
5205static int xhci_get_frame(struct usb_hcd *hcd)
5206{
5207 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5208 /* EHCI mods by the periodic size. Why? */
5209 return readl(&xhci->run_regs->microframe_index) >> 3;
5210}
5211
5212static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5213{
5214 xhci->usb2_rhub.hcd = hcd;
5215 hcd->speed = HCD_USB2;
5216 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5217 /*
5218 * USB 2.0 roothub under xHCI has an integrated TT,
5219 * (rate matching hub) as opposed to having an OHCI/UHCI
5220 * companion controller.
5221 */
5222 hcd->has_tt = 1;
5223}
5224
5225static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5226{
5227 unsigned int minor_rev;
5228
5229 /*
5230 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5231 * should return 0x31 for sbrn, or that the minor revision
5232 * is a two digit BCD containig minor and sub-minor numbers.
5233 * This was later clarified in xHCI 1.2.
5234 *
5235 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5236 * minor revision set to 0x1 instead of 0x10.
5237 */
5238 if (xhci->usb3_rhub.min_rev == 0x1)
5239 minor_rev = 1;
5240 else
5241 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5242
5243 switch (minor_rev) {
5244 case 2:
5245 hcd->speed = HCD_USB32;
5246 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5247 hcd->self.root_hub->rx_lanes = 2;
5248 hcd->self.root_hub->tx_lanes = 2;
5249 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5250 break;
5251 case 1:
5252 hcd->speed = HCD_USB31;
5253 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5254 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5255 break;
5256 }
5257 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5258 minor_rev, minor_rev ? "Enhanced " : "");
5259
5260 xhci->usb3_rhub.hcd = hcd;
5261}
5262
5263int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5264{
5265 struct xhci_hcd *xhci;
5266 /*
5267 * TODO: Check with DWC3 clients for sysdev according to
5268 * quirks
5269 */
5270 struct device *dev = hcd->self.sysdev;
5271 int retval;
5272
5273 /* Accept arbitrarily long scatter-gather lists */
5274 hcd->self.sg_tablesize = ~0;
5275
5276 /* support to build packet from discontinuous buffers */
5277 hcd->self.no_sg_constraint = 1;
5278
5279 /* XHCI controllers don't stop the ep queue on short packets :| */
5280 hcd->self.no_stop_on_short = 1;
5281
5282 xhci = hcd_to_xhci(hcd);
5283
5284 if (!usb_hcd_is_primary_hcd(hcd)) {
5285 xhci_hcd_init_usb3_data(xhci, hcd);
5286 return 0;
5287 }
5288
5289 mutex_init(&xhci->mutex);
5290 xhci->main_hcd = hcd;
5291 xhci->cap_regs = hcd->regs;
5292 xhci->op_regs = hcd->regs +
5293 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5294 xhci->run_regs = hcd->regs +
5295 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5296 /* Cache read-only capability registers */
5297 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5298 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5299 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5300 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5301 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5302 if (xhci->hci_version > 0x100)
5303 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5304
5305 /* xhci-plat or xhci-pci might have set max_interrupters already */
5306 if ((!xhci->max_interrupters) ||
5307 xhci->max_interrupters > HCS_MAX_INTRS(xhci->hcs_params1))
5308 xhci->max_interrupters = HCS_MAX_INTRS(xhci->hcs_params1);
5309
5310 xhci->quirks |= quirks;
5311
5312 if (get_quirks)
5313 get_quirks(dev, xhci);
5314
5315 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5316 * success event after a short transfer. This quirk will ignore such
5317 * spurious event.
5318 */
5319 if (xhci->hci_version > 0x96)
5320 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5321
5322 if (xhci->hci_version == 0x95 && link_quirk) {
5323 xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits");
5324 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
5325 }
5326
5327 /* Make sure the HC is halted. */
5328 retval = xhci_halt(xhci);
5329 if (retval)
5330 return retval;
5331
5332 xhci_zero_64b_regs(xhci);
5333
5334 xhci_dbg(xhci, "Resetting HCD\n");
5335 /* Reset the internal HC memory state and registers. */
5336 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5337 if (retval)
5338 return retval;
5339 xhci_dbg(xhci, "Reset complete\n");
5340
5341 /*
5342 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5343 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5344 * address memory pointers actually. So, this driver clears the AC64
5345 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5346 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5347 */
5348 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5349 xhci->hcc_params &= ~BIT(0);
5350
5351 /* Set dma_mask and coherent_dma_mask to 64-bits,
5352 * if xHC supports 64-bit addressing */
5353 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5354 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5355 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5356 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5357 } else {
5358 /*
5359 * This is to avoid error in cases where a 32-bit USB
5360 * controller is used on a 64-bit capable system.
5361 */
5362 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5363 if (retval)
5364 return retval;
5365 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5366 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5367 }
5368
5369 xhci_dbg(xhci, "Calling HCD init\n");
5370 /* Initialize HCD and host controller data structures. */
5371 retval = xhci_init(hcd);
5372 if (retval)
5373 return retval;
5374 xhci_dbg(xhci, "Called HCD init\n");
5375
5376 if (xhci_hcd_is_usb3(hcd))
5377 xhci_hcd_init_usb3_data(xhci, hcd);
5378 else
5379 xhci_hcd_init_usb2_data(xhci, hcd);
5380
5381 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5382 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5383
5384 return 0;
5385}
5386EXPORT_SYMBOL_GPL(xhci_gen_setup);
5387
5388static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5389 struct usb_host_endpoint *ep)
5390{
5391 struct xhci_hcd *xhci;
5392 struct usb_device *udev;
5393 unsigned int slot_id;
5394 unsigned int ep_index;
5395 unsigned long flags;
5396
5397 xhci = hcd_to_xhci(hcd);
5398
5399 spin_lock_irqsave(&xhci->lock, flags);
5400 udev = (struct usb_device *)ep->hcpriv;
5401 slot_id = udev->slot_id;
5402 ep_index = xhci_get_endpoint_index(&ep->desc);
5403
5404 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5405 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5406 spin_unlock_irqrestore(&xhci->lock, flags);
5407}
5408
5409static const struct hc_driver xhci_hc_driver = {
5410 .description = "xhci-hcd",
5411 .product_desc = "xHCI Host Controller",
5412 .hcd_priv_size = sizeof(struct xhci_hcd),
5413
5414 /*
5415 * generic hardware linkage
5416 */
5417 .irq = xhci_irq,
5418 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5419 HCD_BH,
5420
5421 /*
5422 * basic lifecycle operations
5423 */
5424 .reset = NULL, /* set in xhci_init_driver() */
5425 .start = xhci_run,
5426 .stop = xhci_stop,
5427 .shutdown = xhci_shutdown,
5428
5429 /*
5430 * managing i/o requests and associated device resources
5431 */
5432 .map_urb_for_dma = xhci_map_urb_for_dma,
5433 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5434 .urb_enqueue = xhci_urb_enqueue,
5435 .urb_dequeue = xhci_urb_dequeue,
5436 .alloc_dev = xhci_alloc_dev,
5437 .free_dev = xhci_free_dev,
5438 .alloc_streams = xhci_alloc_streams,
5439 .free_streams = xhci_free_streams,
5440 .add_endpoint = xhci_add_endpoint,
5441 .drop_endpoint = xhci_drop_endpoint,
5442 .endpoint_disable = xhci_endpoint_disable,
5443 .endpoint_reset = xhci_endpoint_reset,
5444 .check_bandwidth = xhci_check_bandwidth,
5445 .reset_bandwidth = xhci_reset_bandwidth,
5446 .address_device = xhci_address_device,
5447 .enable_device = xhci_enable_device,
5448 .update_hub_device = xhci_update_hub_device,
5449 .reset_device = xhci_discover_or_reset_device,
5450
5451 /*
5452 * scheduling support
5453 */
5454 .get_frame_number = xhci_get_frame,
5455
5456 /*
5457 * root hub support
5458 */
5459 .hub_control = xhci_hub_control,
5460 .hub_status_data = xhci_hub_status_data,
5461 .bus_suspend = xhci_bus_suspend,
5462 .bus_resume = xhci_bus_resume,
5463 .get_resuming_ports = xhci_get_resuming_ports,
5464
5465 /*
5466 * call back when device connected and addressed
5467 */
5468 .update_device = xhci_update_device,
5469 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5470 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5471 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5472 .find_raw_port_number = xhci_find_raw_port_number,
5473 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5474};
5475
5476void xhci_init_driver(struct hc_driver *drv,
5477 const struct xhci_driver_overrides *over)
5478{
5479 BUG_ON(!over);
5480
5481 /* Copy the generic table to drv then apply the overrides */
5482 *drv = xhci_hc_driver;
5483
5484 if (over) {
5485 drv->hcd_priv_size += over->extra_priv_size;
5486 if (over->reset)
5487 drv->reset = over->reset;
5488 if (over->start)
5489 drv->start = over->start;
5490 if (over->add_endpoint)
5491 drv->add_endpoint = over->add_endpoint;
5492 if (over->drop_endpoint)
5493 drv->drop_endpoint = over->drop_endpoint;
5494 if (over->check_bandwidth)
5495 drv->check_bandwidth = over->check_bandwidth;
5496 if (over->reset_bandwidth)
5497 drv->reset_bandwidth = over->reset_bandwidth;
5498 if (over->update_hub_device)
5499 drv->update_hub_device = over->update_hub_device;
5500 if (over->hub_control)
5501 drv->hub_control = over->hub_control;
5502 }
5503}
5504EXPORT_SYMBOL_GPL(xhci_init_driver);
5505
5506MODULE_DESCRIPTION(DRIVER_DESC);
5507MODULE_AUTHOR(DRIVER_AUTHOR);
5508MODULE_LICENSE("GPL");
5509
5510static int __init xhci_hcd_init(void)
5511{
5512 /*
5513 * Check the compiler generated sizes of structures that must be laid
5514 * out in specific ways for hardware access.
5515 */
5516 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5517 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5518 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5519 /* xhci_device_control has eight fields, and also
5520 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5521 */
5522 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5523 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5524 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5525 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5526 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5527 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5528 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5529
5530 if (usb_disabled())
5531 return -ENODEV;
5532
5533 xhci_debugfs_create_root();
5534 xhci_dbc_init();
5535
5536 return 0;
5537}
5538
5539/*
5540 * If an init function is provided, an exit function must also be provided
5541 * to allow module unload.
5542 */
5543static void __exit xhci_hcd_fini(void)
5544{
5545 xhci_debugfs_remove_root();
5546 xhci_dbc_exit();
5547}
5548
5549module_init(xhci_hcd_init);
5550module_exit(xhci_hcd_fini);