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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/irq.h>
25#include <linux/log2.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/slab.h>
29
30#include "xhci.h"
31
32#define DRIVER_AUTHOR "Sarah Sharp"
33#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
34
35/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
36static int link_quirk;
37module_param(link_quirk, int, S_IRUGO | S_IWUSR);
38MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
39
40/* TODO: copied from ehci-hcd.c - can this be refactored? */
41/*
42 * handshake - spin reading hc until handshake completes or fails
43 * @ptr: address of hc register to be read
44 * @mask: bits to look at in result of read
45 * @done: value of those bits when handshake succeeds
46 * @usec: timeout in microseconds
47 *
48 * Returns negative errno, or zero on success
49 *
50 * Success happens when the "mask" bits have the specified value (hardware
51 * handshake done). There are two failure modes: "usec" have passed (major
52 * hardware flakeout), or the register reads as all-ones (hardware removed).
53 */
54static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
55 u32 mask, u32 done, int usec)
56{
57 u32 result;
58
59 do {
60 result = xhci_readl(xhci, ptr);
61 if (result == ~(u32)0) /* card removed */
62 return -ENODEV;
63 result &= mask;
64 if (result == done)
65 return 0;
66 udelay(1);
67 usec--;
68 } while (usec > 0);
69 return -ETIMEDOUT;
70}
71
72/*
73 * Disable interrupts and begin the xHCI halting process.
74 */
75void xhci_quiesce(struct xhci_hcd *xhci)
76{
77 u32 halted;
78 u32 cmd;
79 u32 mask;
80
81 mask = ~(XHCI_IRQS);
82 halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
83 if (!halted)
84 mask &= ~CMD_RUN;
85
86 cmd = xhci_readl(xhci, &xhci->op_regs->command);
87 cmd &= mask;
88 xhci_writel(xhci, cmd, &xhci->op_regs->command);
89}
90
91/*
92 * Force HC into halt state.
93 *
94 * Disable any IRQs and clear the run/stop bit.
95 * HC will complete any current and actively pipelined transactions, and
96 * should halt within 16 ms of the run/stop bit being cleared.
97 * Read HC Halted bit in the status register to see when the HC is finished.
98 */
99int xhci_halt(struct xhci_hcd *xhci)
100{
101 int ret;
102 xhci_dbg(xhci, "// Halt the HC\n");
103 xhci_quiesce(xhci);
104
105 ret = handshake(xhci, &xhci->op_regs->status,
106 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
107 if (!ret)
108 xhci->xhc_state |= XHCI_STATE_HALTED;
109 return ret;
110}
111
112/*
113 * Set the run bit and wait for the host to be running.
114 */
115static int xhci_start(struct xhci_hcd *xhci)
116{
117 u32 temp;
118 int ret;
119
120 temp = xhci_readl(xhci, &xhci->op_regs->command);
121 temp |= (CMD_RUN);
122 xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
123 temp);
124 xhci_writel(xhci, temp, &xhci->op_regs->command);
125
126 /*
127 * Wait for the HCHalted Status bit to be 0 to indicate the host is
128 * running.
129 */
130 ret = handshake(xhci, &xhci->op_regs->status,
131 STS_HALT, 0, XHCI_MAX_HALT_USEC);
132 if (ret == -ETIMEDOUT)
133 xhci_err(xhci, "Host took too long to start, "
134 "waited %u microseconds.\n",
135 XHCI_MAX_HALT_USEC);
136 if (!ret)
137 xhci->xhc_state &= ~XHCI_STATE_HALTED;
138 return ret;
139}
140
141/*
142 * Reset a halted HC.
143 *
144 * This resets pipelines, timers, counters, state machines, etc.
145 * Transactions will be terminated immediately, and operational registers
146 * will be set to their defaults.
147 */
148int xhci_reset(struct xhci_hcd *xhci)
149{
150 u32 command;
151 u32 state;
152 int ret;
153
154 state = xhci_readl(xhci, &xhci->op_regs->status);
155 if ((state & STS_HALT) == 0) {
156 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
157 return 0;
158 }
159
160 xhci_dbg(xhci, "// Reset the HC\n");
161 command = xhci_readl(xhci, &xhci->op_regs->command);
162 command |= CMD_RESET;
163 xhci_writel(xhci, command, &xhci->op_regs->command);
164
165 ret = handshake(xhci, &xhci->op_regs->command,
166 CMD_RESET, 0, 250 * 1000);
167 if (ret)
168 return ret;
169
170 xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
171 /*
172 * xHCI cannot write to any doorbells or operational registers other
173 * than status until the "Controller Not Ready" flag is cleared.
174 */
175 return handshake(xhci, &xhci->op_regs->status, STS_CNR, 0, 250 * 1000);
176}
177
178/*
179 * Free IRQs
180 * free all IRQs request
181 */
182static void xhci_free_irq(struct xhci_hcd *xhci)
183{
184 int i;
185 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
186
187 /* return if using legacy interrupt */
188 if (xhci_to_hcd(xhci)->irq >= 0)
189 return;
190
191 if (xhci->msix_entries) {
192 for (i = 0; i < xhci->msix_count; i++)
193 if (xhci->msix_entries[i].vector)
194 free_irq(xhci->msix_entries[i].vector,
195 xhci_to_hcd(xhci));
196 } else if (pdev->irq >= 0)
197 free_irq(pdev->irq, xhci_to_hcd(xhci));
198
199 return;
200}
201
202/*
203 * Set up MSI
204 */
205static int xhci_setup_msi(struct xhci_hcd *xhci)
206{
207 int ret;
208 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
209
210 ret = pci_enable_msi(pdev);
211 if (ret) {
212 xhci_err(xhci, "failed to allocate MSI entry\n");
213 return ret;
214 }
215
216 ret = request_irq(pdev->irq, (irq_handler_t)xhci_msi_irq,
217 0, "xhci_hcd", xhci_to_hcd(xhci));
218 if (ret) {
219 xhci_err(xhci, "disable MSI interrupt\n");
220 pci_disable_msi(pdev);
221 }
222
223 return ret;
224}
225
226/*
227 * Set up MSI-X
228 */
229static int xhci_setup_msix(struct xhci_hcd *xhci)
230{
231 int i, ret = 0;
232 struct usb_hcd *hcd = xhci_to_hcd(xhci);
233 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
234
235 /*
236 * calculate number of msi-x vectors supported.
237 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
238 * with max number of interrupters based on the xhci HCSPARAMS1.
239 * - num_online_cpus: maximum msi-x vectors per CPUs core.
240 * Add additional 1 vector to ensure always available interrupt.
241 */
242 xhci->msix_count = min(num_online_cpus() + 1,
243 HCS_MAX_INTRS(xhci->hcs_params1));
244
245 xhci->msix_entries =
246 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
247 GFP_KERNEL);
248 if (!xhci->msix_entries) {
249 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
250 return -ENOMEM;
251 }
252
253 for (i = 0; i < xhci->msix_count; i++) {
254 xhci->msix_entries[i].entry = i;
255 xhci->msix_entries[i].vector = 0;
256 }
257
258 ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
259 if (ret) {
260 xhci_err(xhci, "Failed to enable MSI-X\n");
261 goto free_entries;
262 }
263
264 for (i = 0; i < xhci->msix_count; i++) {
265 ret = request_irq(xhci->msix_entries[i].vector,
266 (irq_handler_t)xhci_msi_irq,
267 0, "xhci_hcd", xhci_to_hcd(xhci));
268 if (ret)
269 goto disable_msix;
270 }
271
272 hcd->msix_enabled = 1;
273 return ret;
274
275disable_msix:
276 xhci_err(xhci, "disable MSI-X interrupt\n");
277 xhci_free_irq(xhci);
278 pci_disable_msix(pdev);
279free_entries:
280 kfree(xhci->msix_entries);
281 xhci->msix_entries = NULL;
282 return ret;
283}
284
285/* Free any IRQs and disable MSI-X */
286static void xhci_cleanup_msix(struct xhci_hcd *xhci)
287{
288 struct usb_hcd *hcd = xhci_to_hcd(xhci);
289 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
290
291 xhci_free_irq(xhci);
292
293 if (xhci->msix_entries) {
294 pci_disable_msix(pdev);
295 kfree(xhci->msix_entries);
296 xhci->msix_entries = NULL;
297 } else {
298 pci_disable_msi(pdev);
299 }
300
301 hcd->msix_enabled = 0;
302 return;
303}
304
305/*
306 * Initialize memory for HCD and xHC (one-time init).
307 *
308 * Program the PAGESIZE register, initialize the device context array, create
309 * device contexts (?), set up a command ring segment (or two?), create event
310 * ring (one for now).
311 */
312int xhci_init(struct usb_hcd *hcd)
313{
314 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
315 int retval = 0;
316
317 xhci_dbg(xhci, "xhci_init\n");
318 spin_lock_init(&xhci->lock);
319 if (link_quirk) {
320 xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
321 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
322 } else {
323 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
324 }
325 retval = xhci_mem_init(xhci, GFP_KERNEL);
326 xhci_dbg(xhci, "Finished xhci_init\n");
327
328 return retval;
329}
330
331/*-------------------------------------------------------------------------*/
332
333
334#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
335static void xhci_event_ring_work(unsigned long arg)
336{
337 unsigned long flags;
338 int temp;
339 u64 temp_64;
340 struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
341 int i, j;
342
343 xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
344
345 spin_lock_irqsave(&xhci->lock, flags);
346 temp = xhci_readl(xhci, &xhci->op_regs->status);
347 xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
348 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
349 (xhci->xhc_state & XHCI_STATE_HALTED)) {
350 xhci_dbg(xhci, "HW died, polling stopped.\n");
351 spin_unlock_irqrestore(&xhci->lock, flags);
352 return;
353 }
354
355 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
356 xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
357 xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
358 xhci->error_bitmask = 0;
359 xhci_dbg(xhci, "Event ring:\n");
360 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
361 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
362 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
363 temp_64 &= ~ERST_PTR_MASK;
364 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
365 xhci_dbg(xhci, "Command ring:\n");
366 xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
367 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
368 xhci_dbg_cmd_ptrs(xhci);
369 for (i = 0; i < MAX_HC_SLOTS; ++i) {
370 if (!xhci->devs[i])
371 continue;
372 for (j = 0; j < 31; ++j) {
373 xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
374 }
375 }
376 spin_unlock_irqrestore(&xhci->lock, flags);
377
378 if (!xhci->zombie)
379 mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
380 else
381 xhci_dbg(xhci, "Quit polling the event ring.\n");
382}
383#endif
384
385static int xhci_run_finished(struct xhci_hcd *xhci)
386{
387 if (xhci_start(xhci)) {
388 xhci_halt(xhci);
389 return -ENODEV;
390 }
391 xhci->shared_hcd->state = HC_STATE_RUNNING;
392
393 if (xhci->quirks & XHCI_NEC_HOST)
394 xhci_ring_cmd_db(xhci);
395
396 xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
397 return 0;
398}
399
400/*
401 * Start the HC after it was halted.
402 *
403 * This function is called by the USB core when the HC driver is added.
404 * Its opposite is xhci_stop().
405 *
406 * xhci_init() must be called once before this function can be called.
407 * Reset the HC, enable device slot contexts, program DCBAAP, and
408 * set command ring pointer and event ring pointer.
409 *
410 * Setup MSI-X vectors and enable interrupts.
411 */
412int xhci_run(struct usb_hcd *hcd)
413{
414 u32 temp;
415 u64 temp_64;
416 u32 ret;
417 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
418 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
419
420 /* Start the xHCI host controller running only after the USB 2.0 roothub
421 * is setup.
422 */
423
424 hcd->uses_new_polling = 1;
425 if (!usb_hcd_is_primary_hcd(hcd))
426 return xhci_run_finished(xhci);
427
428 xhci_dbg(xhci, "xhci_run\n");
429 /* unregister the legacy interrupt */
430 if (hcd->irq)
431 free_irq(hcd->irq, hcd);
432 hcd->irq = -1;
433
434 /* Some Fresco Logic host controllers advertise MSI, but fail to
435 * generate interrupts. Don't even try to enable MSI.
436 */
437 if (xhci->quirks & XHCI_BROKEN_MSI)
438 goto legacy_irq;
439
440 ret = xhci_setup_msix(xhci);
441 if (ret)
442 /* fall back to msi*/
443 ret = xhci_setup_msi(xhci);
444
445 if (ret) {
446legacy_irq:
447 /* fall back to legacy interrupt*/
448 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
449 hcd->irq_descr, hcd);
450 if (ret) {
451 xhci_err(xhci, "request interrupt %d failed\n",
452 pdev->irq);
453 return ret;
454 }
455 hcd->irq = pdev->irq;
456 }
457
458#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
459 init_timer(&xhci->event_ring_timer);
460 xhci->event_ring_timer.data = (unsigned long) xhci;
461 xhci->event_ring_timer.function = xhci_event_ring_work;
462 /* Poll the event ring */
463 xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
464 xhci->zombie = 0;
465 xhci_dbg(xhci, "Setting event ring polling timer\n");
466 add_timer(&xhci->event_ring_timer);
467#endif
468
469 xhci_dbg(xhci, "Command ring memory map follows:\n");
470 xhci_debug_ring(xhci, xhci->cmd_ring);
471 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
472 xhci_dbg_cmd_ptrs(xhci);
473
474 xhci_dbg(xhci, "ERST memory map follows:\n");
475 xhci_dbg_erst(xhci, &xhci->erst);
476 xhci_dbg(xhci, "Event ring:\n");
477 xhci_debug_ring(xhci, xhci->event_ring);
478 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
479 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
480 temp_64 &= ~ERST_PTR_MASK;
481 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
482
483 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
484 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
485 temp &= ~ER_IRQ_INTERVAL_MASK;
486 temp |= (u32) 160;
487 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
488
489 /* Set the HCD state before we enable the irqs */
490 temp = xhci_readl(xhci, &xhci->op_regs->command);
491 temp |= (CMD_EIE);
492 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
493 temp);
494 xhci_writel(xhci, temp, &xhci->op_regs->command);
495
496 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
497 xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
498 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
499 xhci_writel(xhci, ER_IRQ_ENABLE(temp),
500 &xhci->ir_set->irq_pending);
501 xhci_print_ir_set(xhci, 0);
502
503 if (xhci->quirks & XHCI_NEC_HOST)
504 xhci_queue_vendor_command(xhci, 0, 0, 0,
505 TRB_TYPE(TRB_NEC_GET_FW));
506
507 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
508 return 0;
509}
510
511static void xhci_only_stop_hcd(struct usb_hcd *hcd)
512{
513 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
514
515 spin_lock_irq(&xhci->lock);
516 xhci_halt(xhci);
517
518 /* The shared_hcd is going to be deallocated shortly (the USB core only
519 * calls this function when allocation fails in usb_add_hcd(), or
520 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
521 */
522 xhci->shared_hcd = NULL;
523 spin_unlock_irq(&xhci->lock);
524}
525
526/*
527 * Stop xHCI driver.
528 *
529 * This function is called by the USB core when the HC driver is removed.
530 * Its opposite is xhci_run().
531 *
532 * Disable device contexts, disable IRQs, and quiesce the HC.
533 * Reset the HC, finish any completed transactions, and cleanup memory.
534 */
535void xhci_stop(struct usb_hcd *hcd)
536{
537 u32 temp;
538 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
539
540 if (!usb_hcd_is_primary_hcd(hcd)) {
541 xhci_only_stop_hcd(xhci->shared_hcd);
542 return;
543 }
544
545 spin_lock_irq(&xhci->lock);
546 /* Make sure the xHC is halted for a USB3 roothub
547 * (xhci_stop() could be called as part of failed init).
548 */
549 xhci_halt(xhci);
550 xhci_reset(xhci);
551 spin_unlock_irq(&xhci->lock);
552
553 xhci_cleanup_msix(xhci);
554
555#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
556 /* Tell the event ring poll function not to reschedule */
557 xhci->zombie = 1;
558 del_timer_sync(&xhci->event_ring_timer);
559#endif
560
561 if (xhci->quirks & XHCI_AMD_PLL_FIX)
562 usb_amd_dev_put();
563
564 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
565 temp = xhci_readl(xhci, &xhci->op_regs->status);
566 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
567 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
568 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
569 &xhci->ir_set->irq_pending);
570 xhci_print_ir_set(xhci, 0);
571
572 xhci_dbg(xhci, "cleaning up memory\n");
573 xhci_mem_cleanup(xhci);
574 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
575 xhci_readl(xhci, &xhci->op_regs->status));
576}
577
578/*
579 * Shutdown HC (not bus-specific)
580 *
581 * This is called when the machine is rebooting or halting. We assume that the
582 * machine will be powered off, and the HC's internal state will be reset.
583 * Don't bother to free memory.
584 *
585 * This will only ever be called with the main usb_hcd (the USB3 roothub).
586 */
587void xhci_shutdown(struct usb_hcd *hcd)
588{
589 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
590
591 spin_lock_irq(&xhci->lock);
592 xhci_halt(xhci);
593 spin_unlock_irq(&xhci->lock);
594
595 xhci_cleanup_msix(xhci);
596
597 xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
598 xhci_readl(xhci, &xhci->op_regs->status));
599}
600
601#ifdef CONFIG_PM
602static void xhci_save_registers(struct xhci_hcd *xhci)
603{
604 xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
605 xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
606 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
607 xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
608 xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
609 xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
610 xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
611 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
612 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
613}
614
615static void xhci_restore_registers(struct xhci_hcd *xhci)
616{
617 xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
618 xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
619 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
620 xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
621 xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
622 xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
623 xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
624 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
625}
626
627static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
628{
629 u64 val_64;
630
631 /* step 2: initialize command ring buffer */
632 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
633 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
634 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
635 xhci->cmd_ring->dequeue) &
636 (u64) ~CMD_RING_RSVD_BITS) |
637 xhci->cmd_ring->cycle_state;
638 xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
639 (long unsigned long) val_64);
640 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
641}
642
643/*
644 * The whole command ring must be cleared to zero when we suspend the host.
645 *
646 * The host doesn't save the command ring pointer in the suspend well, so we
647 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
648 * aligned, because of the reserved bits in the command ring dequeue pointer
649 * register. Therefore, we can't just set the dequeue pointer back in the
650 * middle of the ring (TRBs are 16-byte aligned).
651 */
652static void xhci_clear_command_ring(struct xhci_hcd *xhci)
653{
654 struct xhci_ring *ring;
655 struct xhci_segment *seg;
656
657 ring = xhci->cmd_ring;
658 seg = ring->deq_seg;
659 do {
660 memset(seg->trbs, 0, SEGMENT_SIZE);
661 seg = seg->next;
662 } while (seg != ring->deq_seg);
663
664 /* Reset the software enqueue and dequeue pointers */
665 ring->deq_seg = ring->first_seg;
666 ring->dequeue = ring->first_seg->trbs;
667 ring->enq_seg = ring->deq_seg;
668 ring->enqueue = ring->dequeue;
669
670 /*
671 * Ring is now zeroed, so the HW should look for change of ownership
672 * when the cycle bit is set to 1.
673 */
674 ring->cycle_state = 1;
675
676 /*
677 * Reset the hardware dequeue pointer.
678 * Yes, this will need to be re-written after resume, but we're paranoid
679 * and want to make sure the hardware doesn't access bogus memory
680 * because, say, the BIOS or an SMI started the host without changing
681 * the command ring pointers.
682 */
683 xhci_set_cmd_ring_deq(xhci);
684}
685
686/*
687 * Stop HC (not bus-specific)
688 *
689 * This is called when the machine transition into S3/S4 mode.
690 *
691 */
692int xhci_suspend(struct xhci_hcd *xhci)
693{
694 int rc = 0;
695 struct usb_hcd *hcd = xhci_to_hcd(xhci);
696 u32 command;
697 int i;
698
699 spin_lock_irq(&xhci->lock);
700 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
701 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
702 /* step 1: stop endpoint */
703 /* skipped assuming that port suspend has done */
704
705 /* step 2: clear Run/Stop bit */
706 command = xhci_readl(xhci, &xhci->op_regs->command);
707 command &= ~CMD_RUN;
708 xhci_writel(xhci, command, &xhci->op_regs->command);
709 if (handshake(xhci, &xhci->op_regs->status,
710 STS_HALT, STS_HALT, 100*100)) {
711 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
712 spin_unlock_irq(&xhci->lock);
713 return -ETIMEDOUT;
714 }
715 xhci_clear_command_ring(xhci);
716
717 /* step 3: save registers */
718 xhci_save_registers(xhci);
719
720 /* step 4: set CSS flag */
721 command = xhci_readl(xhci, &xhci->op_regs->command);
722 command |= CMD_CSS;
723 xhci_writel(xhci, command, &xhci->op_regs->command);
724 if (handshake(xhci, &xhci->op_regs->status, STS_SAVE, 0, 10*100)) {
725 xhci_warn(xhci, "WARN: xHC CMD_CSS timeout\n");
726 spin_unlock_irq(&xhci->lock);
727 return -ETIMEDOUT;
728 }
729 spin_unlock_irq(&xhci->lock);
730
731 /* step 5: remove core well power */
732 /* synchronize irq when using MSI-X */
733 if (xhci->msix_entries) {
734 for (i = 0; i < xhci->msix_count; i++)
735 synchronize_irq(xhci->msix_entries[i].vector);
736 }
737
738 return rc;
739}
740
741/*
742 * start xHC (not bus-specific)
743 *
744 * This is called when the machine transition from S3/S4 mode.
745 *
746 */
747int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
748{
749 u32 command, temp = 0;
750 struct usb_hcd *hcd = xhci_to_hcd(xhci);
751 struct usb_hcd *secondary_hcd;
752 int retval;
753
754 /* Wait a bit if either of the roothubs need to settle from the
755 * transition into bus suspend.
756 */
757 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
758 time_before(jiffies,
759 xhci->bus_state[1].next_statechange))
760 msleep(100);
761
762 spin_lock_irq(&xhci->lock);
763 if (xhci->quirks & XHCI_RESET_ON_RESUME)
764 hibernated = true;
765
766 if (!hibernated) {
767 /* step 1: restore register */
768 xhci_restore_registers(xhci);
769 /* step 2: initialize command ring buffer */
770 xhci_set_cmd_ring_deq(xhci);
771 /* step 3: restore state and start state*/
772 /* step 3: set CRS flag */
773 command = xhci_readl(xhci, &xhci->op_regs->command);
774 command |= CMD_CRS;
775 xhci_writel(xhci, command, &xhci->op_regs->command);
776 if (handshake(xhci, &xhci->op_regs->status,
777 STS_RESTORE, 0, 10*100)) {
778 xhci_dbg(xhci, "WARN: xHC CMD_CSS timeout\n");
779 spin_unlock_irq(&xhci->lock);
780 return -ETIMEDOUT;
781 }
782 temp = xhci_readl(xhci, &xhci->op_regs->status);
783 }
784
785 /* If restore operation fails, re-initialize the HC during resume */
786 if ((temp & STS_SRE) || hibernated) {
787 /* Let the USB core know _both_ roothubs lost power. */
788 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
789 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
790
791 xhci_dbg(xhci, "Stop HCD\n");
792 xhci_halt(xhci);
793 xhci_reset(xhci);
794 spin_unlock_irq(&xhci->lock);
795 xhci_cleanup_msix(xhci);
796
797#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
798 /* Tell the event ring poll function not to reschedule */
799 xhci->zombie = 1;
800 del_timer_sync(&xhci->event_ring_timer);
801#endif
802
803 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
804 temp = xhci_readl(xhci, &xhci->op_regs->status);
805 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
806 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
807 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
808 &xhci->ir_set->irq_pending);
809 xhci_print_ir_set(xhci, 0);
810
811 xhci_dbg(xhci, "cleaning up memory\n");
812 xhci_mem_cleanup(xhci);
813 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
814 xhci_readl(xhci, &xhci->op_regs->status));
815
816 /* USB core calls the PCI reinit and start functions twice:
817 * first with the primary HCD, and then with the secondary HCD.
818 * If we don't do the same, the host will never be started.
819 */
820 if (!usb_hcd_is_primary_hcd(hcd))
821 secondary_hcd = hcd;
822 else
823 secondary_hcd = xhci->shared_hcd;
824
825 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
826 retval = xhci_init(hcd->primary_hcd);
827 if (retval)
828 return retval;
829 xhci_dbg(xhci, "Start the primary HCD\n");
830 retval = xhci_run(hcd->primary_hcd);
831 if (retval)
832 goto failed_restart;
833
834 xhci_dbg(xhci, "Start the secondary HCD\n");
835 retval = xhci_run(secondary_hcd);
836 if (!retval) {
837 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
838 set_bit(HCD_FLAG_HW_ACCESSIBLE,
839 &xhci->shared_hcd->flags);
840 }
841failed_restart:
842 hcd->state = HC_STATE_SUSPENDED;
843 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
844 return retval;
845 }
846
847 /* step 4: set Run/Stop bit */
848 command = xhci_readl(xhci, &xhci->op_regs->command);
849 command |= CMD_RUN;
850 xhci_writel(xhci, command, &xhci->op_regs->command);
851 handshake(xhci, &xhci->op_regs->status, STS_HALT,
852 0, 250 * 1000);
853
854 /* step 5: walk topology and initialize portsc,
855 * portpmsc and portli
856 */
857 /* this is done in bus_resume */
858
859 /* step 6: restart each of the previously
860 * Running endpoints by ringing their doorbells
861 */
862
863 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
864 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
865
866 spin_unlock_irq(&xhci->lock);
867 return 0;
868}
869#endif /* CONFIG_PM */
870
871/*-------------------------------------------------------------------------*/
872
873/**
874 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
875 * HCDs. Find the index for an endpoint given its descriptor. Use the return
876 * value to right shift 1 for the bitmask.
877 *
878 * Index = (epnum * 2) + direction - 1,
879 * where direction = 0 for OUT, 1 for IN.
880 * For control endpoints, the IN index is used (OUT index is unused), so
881 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
882 */
883unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
884{
885 unsigned int index;
886 if (usb_endpoint_xfer_control(desc))
887 index = (unsigned int) (usb_endpoint_num(desc)*2);
888 else
889 index = (unsigned int) (usb_endpoint_num(desc)*2) +
890 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
891 return index;
892}
893
894/* Find the flag for this endpoint (for use in the control context). Use the
895 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
896 * bit 1, etc.
897 */
898unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
899{
900 return 1 << (xhci_get_endpoint_index(desc) + 1);
901}
902
903/* Find the flag for this endpoint (for use in the control context). Use the
904 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
905 * bit 1, etc.
906 */
907unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
908{
909 return 1 << (ep_index + 1);
910}
911
912/* Compute the last valid endpoint context index. Basically, this is the
913 * endpoint index plus one. For slot contexts with more than valid endpoint,
914 * we find the most significant bit set in the added contexts flags.
915 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
916 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
917 */
918unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
919{
920 return fls(added_ctxs) - 1;
921}
922
923/* Returns 1 if the arguments are OK;
924 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
925 */
926static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
927 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
928 const char *func) {
929 struct xhci_hcd *xhci;
930 struct xhci_virt_device *virt_dev;
931
932 if (!hcd || (check_ep && !ep) || !udev) {
933 printk(KERN_DEBUG "xHCI %s called with invalid args\n",
934 func);
935 return -EINVAL;
936 }
937 if (!udev->parent) {
938 printk(KERN_DEBUG "xHCI %s called for root hub\n",
939 func);
940 return 0;
941 }
942
943 xhci = hcd_to_xhci(hcd);
944 if (xhci->xhc_state & XHCI_STATE_HALTED)
945 return -ENODEV;
946
947 if (check_virt_dev) {
948 if (!udev->slot_id || !xhci->devs
949 || !xhci->devs[udev->slot_id]) {
950 printk(KERN_DEBUG "xHCI %s called with unaddressed "
951 "device\n", func);
952 return -EINVAL;
953 }
954
955 virt_dev = xhci->devs[udev->slot_id];
956 if (virt_dev->udev != udev) {
957 printk(KERN_DEBUG "xHCI %s called with udev and "
958 "virt_dev does not match\n", func);
959 return -EINVAL;
960 }
961 }
962
963 return 1;
964}
965
966static int xhci_configure_endpoint(struct xhci_hcd *xhci,
967 struct usb_device *udev, struct xhci_command *command,
968 bool ctx_change, bool must_succeed);
969
970/*
971 * Full speed devices may have a max packet size greater than 8 bytes, but the
972 * USB core doesn't know that until it reads the first 8 bytes of the
973 * descriptor. If the usb_device's max packet size changes after that point,
974 * we need to issue an evaluate context command and wait on it.
975 */
976static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
977 unsigned int ep_index, struct urb *urb)
978{
979 struct xhci_container_ctx *in_ctx;
980 struct xhci_container_ctx *out_ctx;
981 struct xhci_input_control_ctx *ctrl_ctx;
982 struct xhci_ep_ctx *ep_ctx;
983 int max_packet_size;
984 int hw_max_packet_size;
985 int ret = 0;
986
987 out_ctx = xhci->devs[slot_id]->out_ctx;
988 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
989 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
990 max_packet_size = le16_to_cpu(urb->dev->ep0.desc.wMaxPacketSize);
991 if (hw_max_packet_size != max_packet_size) {
992 xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
993 xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
994 max_packet_size);
995 xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
996 hw_max_packet_size);
997 xhci_dbg(xhci, "Issuing evaluate context command.\n");
998
999 /* Set up the modified control endpoint 0 */
1000 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1001 xhci->devs[slot_id]->out_ctx, ep_index);
1002 in_ctx = xhci->devs[slot_id]->in_ctx;
1003 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1004 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1005 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1006
1007 /* Set up the input context flags for the command */
1008 /* FIXME: This won't work if a non-default control endpoint
1009 * changes max packet sizes.
1010 */
1011 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1012 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1013 ctrl_ctx->drop_flags = 0;
1014
1015 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1016 xhci_dbg_ctx(xhci, in_ctx, ep_index);
1017 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1018 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1019
1020 ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
1021 true, false);
1022
1023 /* Clean up the input context for later use by bandwidth
1024 * functions.
1025 */
1026 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1027 }
1028 return ret;
1029}
1030
1031/*
1032 * non-error returns are a promise to giveback() the urb later
1033 * we drop ownership so next owner (or urb unlink) can get it
1034 */
1035int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1036{
1037 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1038 unsigned long flags;
1039 int ret = 0;
1040 unsigned int slot_id, ep_index;
1041 struct urb_priv *urb_priv;
1042 int size, i;
1043
1044 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1045 true, true, __func__) <= 0)
1046 return -EINVAL;
1047
1048 slot_id = urb->dev->slot_id;
1049 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1050
1051 if (!HCD_HW_ACCESSIBLE(hcd)) {
1052 if (!in_interrupt())
1053 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1054 ret = -ESHUTDOWN;
1055 goto exit;
1056 }
1057
1058 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1059 size = urb->number_of_packets;
1060 else
1061 size = 1;
1062
1063 urb_priv = kzalloc(sizeof(struct urb_priv) +
1064 size * sizeof(struct xhci_td *), mem_flags);
1065 if (!urb_priv)
1066 return -ENOMEM;
1067
1068 for (i = 0; i < size; i++) {
1069 urb_priv->td[i] = kzalloc(sizeof(struct xhci_td), mem_flags);
1070 if (!urb_priv->td[i]) {
1071 urb_priv->length = i;
1072 xhci_urb_free_priv(xhci, urb_priv);
1073 return -ENOMEM;
1074 }
1075 }
1076
1077 urb_priv->length = size;
1078 urb_priv->td_cnt = 0;
1079 urb->hcpriv = urb_priv;
1080
1081 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1082 /* Check to see if the max packet size for the default control
1083 * endpoint changed during FS device enumeration
1084 */
1085 if (urb->dev->speed == USB_SPEED_FULL) {
1086 ret = xhci_check_maxpacket(xhci, slot_id,
1087 ep_index, urb);
1088 if (ret < 0) {
1089 xhci_urb_free_priv(xhci, urb_priv);
1090 urb->hcpriv = NULL;
1091 return ret;
1092 }
1093 }
1094
1095 /* We have a spinlock and interrupts disabled, so we must pass
1096 * atomic context to this function, which may allocate memory.
1097 */
1098 spin_lock_irqsave(&xhci->lock, flags);
1099 if (xhci->xhc_state & XHCI_STATE_DYING)
1100 goto dying;
1101 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1102 slot_id, ep_index);
1103 if (ret)
1104 goto free_priv;
1105 spin_unlock_irqrestore(&xhci->lock, flags);
1106 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1107 spin_lock_irqsave(&xhci->lock, flags);
1108 if (xhci->xhc_state & XHCI_STATE_DYING)
1109 goto dying;
1110 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1111 EP_GETTING_STREAMS) {
1112 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1113 "is transitioning to using streams.\n");
1114 ret = -EINVAL;
1115 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1116 EP_GETTING_NO_STREAMS) {
1117 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1118 "is transitioning to "
1119 "not having streams.\n");
1120 ret = -EINVAL;
1121 } else {
1122 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1123 slot_id, ep_index);
1124 }
1125 if (ret)
1126 goto free_priv;
1127 spin_unlock_irqrestore(&xhci->lock, flags);
1128 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1129 spin_lock_irqsave(&xhci->lock, flags);
1130 if (xhci->xhc_state & XHCI_STATE_DYING)
1131 goto dying;
1132 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1133 slot_id, ep_index);
1134 if (ret)
1135 goto free_priv;
1136 spin_unlock_irqrestore(&xhci->lock, flags);
1137 } else {
1138 spin_lock_irqsave(&xhci->lock, flags);
1139 if (xhci->xhc_state & XHCI_STATE_DYING)
1140 goto dying;
1141 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1142 slot_id, ep_index);
1143 if (ret)
1144 goto free_priv;
1145 spin_unlock_irqrestore(&xhci->lock, flags);
1146 }
1147exit:
1148 return ret;
1149dying:
1150 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1151 "non-responsive xHCI host.\n",
1152 urb->ep->desc.bEndpointAddress, urb);
1153 ret = -ESHUTDOWN;
1154free_priv:
1155 xhci_urb_free_priv(xhci, urb_priv);
1156 urb->hcpriv = NULL;
1157 spin_unlock_irqrestore(&xhci->lock, flags);
1158 return ret;
1159}
1160
1161/* Get the right ring for the given URB.
1162 * If the endpoint supports streams, boundary check the URB's stream ID.
1163 * If the endpoint doesn't support streams, return the singular endpoint ring.
1164 */
1165static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1166 struct urb *urb)
1167{
1168 unsigned int slot_id;
1169 unsigned int ep_index;
1170 unsigned int stream_id;
1171 struct xhci_virt_ep *ep;
1172
1173 slot_id = urb->dev->slot_id;
1174 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1175 stream_id = urb->stream_id;
1176 ep = &xhci->devs[slot_id]->eps[ep_index];
1177 /* Common case: no streams */
1178 if (!(ep->ep_state & EP_HAS_STREAMS))
1179 return ep->ring;
1180
1181 if (stream_id == 0) {
1182 xhci_warn(xhci,
1183 "WARN: Slot ID %u, ep index %u has streams, "
1184 "but URB has no stream ID.\n",
1185 slot_id, ep_index);
1186 return NULL;
1187 }
1188
1189 if (stream_id < ep->stream_info->num_streams)
1190 return ep->stream_info->stream_rings[stream_id];
1191
1192 xhci_warn(xhci,
1193 "WARN: Slot ID %u, ep index %u has "
1194 "stream IDs 1 to %u allocated, "
1195 "but stream ID %u is requested.\n",
1196 slot_id, ep_index,
1197 ep->stream_info->num_streams - 1,
1198 stream_id);
1199 return NULL;
1200}
1201
1202/*
1203 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1204 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1205 * should pick up where it left off in the TD, unless a Set Transfer Ring
1206 * Dequeue Pointer is issued.
1207 *
1208 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1209 * the ring. Since the ring is a contiguous structure, they can't be physically
1210 * removed. Instead, there are two options:
1211 *
1212 * 1) If the HC is in the middle of processing the URB to be canceled, we
1213 * simply move the ring's dequeue pointer past those TRBs using the Set
1214 * Transfer Ring Dequeue Pointer command. This will be the common case,
1215 * when drivers timeout on the last submitted URB and attempt to cancel.
1216 *
1217 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1218 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1219 * HC will need to invalidate the any TRBs it has cached after the stop
1220 * endpoint command, as noted in the xHCI 0.95 errata.
1221 *
1222 * 3) The TD may have completed by the time the Stop Endpoint Command
1223 * completes, so software needs to handle that case too.
1224 *
1225 * This function should protect against the TD enqueueing code ringing the
1226 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1227 * It also needs to account for multiple cancellations on happening at the same
1228 * time for the same endpoint.
1229 *
1230 * Note that this function can be called in any context, or so says
1231 * usb_hcd_unlink_urb()
1232 */
1233int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1234{
1235 unsigned long flags;
1236 int ret, i;
1237 u32 temp;
1238 struct xhci_hcd *xhci;
1239 struct urb_priv *urb_priv;
1240 struct xhci_td *td;
1241 unsigned int ep_index;
1242 struct xhci_ring *ep_ring;
1243 struct xhci_virt_ep *ep;
1244
1245 xhci = hcd_to_xhci(hcd);
1246 spin_lock_irqsave(&xhci->lock, flags);
1247 /* Make sure the URB hasn't completed or been unlinked already */
1248 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1249 if (ret || !urb->hcpriv)
1250 goto done;
1251 temp = xhci_readl(xhci, &xhci->op_regs->status);
1252 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1253 xhci_dbg(xhci, "HW died, freeing TD.\n");
1254 urb_priv = urb->hcpriv;
1255 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1256 td = urb_priv->td[i];
1257 if (!list_empty(&td->td_list))
1258 list_del_init(&td->td_list);
1259 if (!list_empty(&td->cancelled_td_list))
1260 list_del_init(&td->cancelled_td_list);
1261 }
1262
1263 usb_hcd_unlink_urb_from_ep(hcd, urb);
1264 spin_unlock_irqrestore(&xhci->lock, flags);
1265 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1266 xhci_urb_free_priv(xhci, urb_priv);
1267 return ret;
1268 }
1269 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1270 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1271 xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
1272 "non-responsive xHCI host.\n",
1273 urb->ep->desc.bEndpointAddress, urb);
1274 /* Let the stop endpoint command watchdog timer (which set this
1275 * state) finish cleaning up the endpoint TD lists. We must
1276 * have caught it in the middle of dropping a lock and giving
1277 * back an URB.
1278 */
1279 goto done;
1280 }
1281
1282 xhci_dbg(xhci, "Cancel URB %p\n", urb);
1283 xhci_dbg(xhci, "Event ring:\n");
1284 xhci_debug_ring(xhci, xhci->event_ring);
1285 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1286 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1287 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1288 if (!ep_ring) {
1289 ret = -EINVAL;
1290 goto done;
1291 }
1292
1293 xhci_dbg(xhci, "Endpoint ring:\n");
1294 xhci_debug_ring(xhci, ep_ring);
1295
1296 urb_priv = urb->hcpriv;
1297
1298 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1299 td = urb_priv->td[i];
1300 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1301 }
1302
1303 /* Queue a stop endpoint command, but only if this is
1304 * the first cancellation to be handled.
1305 */
1306 if (!(ep->ep_state & EP_HALT_PENDING)) {
1307 ep->ep_state |= EP_HALT_PENDING;
1308 ep->stop_cmds_pending++;
1309 ep->stop_cmd_timer.expires = jiffies +
1310 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1311 add_timer(&ep->stop_cmd_timer);
1312 xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
1313 xhci_ring_cmd_db(xhci);
1314 }
1315done:
1316 spin_unlock_irqrestore(&xhci->lock, flags);
1317 return ret;
1318}
1319
1320/* Drop an endpoint from a new bandwidth configuration for this device.
1321 * Only one call to this function is allowed per endpoint before
1322 * check_bandwidth() or reset_bandwidth() must be called.
1323 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1324 * add the endpoint to the schedule with possibly new parameters denoted by a
1325 * different endpoint descriptor in usb_host_endpoint.
1326 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1327 * not allowed.
1328 *
1329 * The USB core will not allow URBs to be queued to an endpoint that is being
1330 * disabled, so there's no need for mutual exclusion to protect
1331 * the xhci->devs[slot_id] structure.
1332 */
1333int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1334 struct usb_host_endpoint *ep)
1335{
1336 struct xhci_hcd *xhci;
1337 struct xhci_container_ctx *in_ctx, *out_ctx;
1338 struct xhci_input_control_ctx *ctrl_ctx;
1339 struct xhci_slot_ctx *slot_ctx;
1340 unsigned int last_ctx;
1341 unsigned int ep_index;
1342 struct xhci_ep_ctx *ep_ctx;
1343 u32 drop_flag;
1344 u32 new_add_flags, new_drop_flags, new_slot_info;
1345 int ret;
1346
1347 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1348 if (ret <= 0)
1349 return ret;
1350 xhci = hcd_to_xhci(hcd);
1351 if (xhci->xhc_state & XHCI_STATE_DYING)
1352 return -ENODEV;
1353
1354 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1355 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1356 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1357 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1358 __func__, drop_flag);
1359 return 0;
1360 }
1361
1362 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1363 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1364 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1365 ep_index = xhci_get_endpoint_index(&ep->desc);
1366 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1367 /* If the HC already knows the endpoint is disabled,
1368 * or the HCD has noted it is disabled, ignore this request
1369 */
1370 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1371 cpu_to_le32(EP_STATE_DISABLED)) ||
1372 le32_to_cpu(ctrl_ctx->drop_flags) &
1373 xhci_get_endpoint_flag(&ep->desc)) {
1374 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1375 __func__, ep);
1376 return 0;
1377 }
1378
1379 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1380 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1381
1382 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1383 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1384
1385 last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
1386 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1387 /* Update the last valid endpoint context, if we deleted the last one */
1388 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
1389 LAST_CTX(last_ctx)) {
1390 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1391 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1392 }
1393 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1394
1395 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1396
1397 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1398 (unsigned int) ep->desc.bEndpointAddress,
1399 udev->slot_id,
1400 (unsigned int) new_drop_flags,
1401 (unsigned int) new_add_flags,
1402 (unsigned int) new_slot_info);
1403 return 0;
1404}
1405
1406/* Add an endpoint to a new possible bandwidth configuration for this device.
1407 * Only one call to this function is allowed per endpoint before
1408 * check_bandwidth() or reset_bandwidth() must be called.
1409 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1410 * add the endpoint to the schedule with possibly new parameters denoted by a
1411 * different endpoint descriptor in usb_host_endpoint.
1412 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1413 * not allowed.
1414 *
1415 * The USB core will not allow URBs to be queued to an endpoint until the
1416 * configuration or alt setting is installed in the device, so there's no need
1417 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1418 */
1419int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1420 struct usb_host_endpoint *ep)
1421{
1422 struct xhci_hcd *xhci;
1423 struct xhci_container_ctx *in_ctx, *out_ctx;
1424 unsigned int ep_index;
1425 struct xhci_ep_ctx *ep_ctx;
1426 struct xhci_slot_ctx *slot_ctx;
1427 struct xhci_input_control_ctx *ctrl_ctx;
1428 u32 added_ctxs;
1429 unsigned int last_ctx;
1430 u32 new_add_flags, new_drop_flags, new_slot_info;
1431 struct xhci_virt_device *virt_dev;
1432 int ret = 0;
1433
1434 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1435 if (ret <= 0) {
1436 /* So we won't queue a reset ep command for a root hub */
1437 ep->hcpriv = NULL;
1438 return ret;
1439 }
1440 xhci = hcd_to_xhci(hcd);
1441 if (xhci->xhc_state & XHCI_STATE_DYING)
1442 return -ENODEV;
1443
1444 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1445 last_ctx = xhci_last_valid_endpoint(added_ctxs);
1446 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1447 /* FIXME when we have to issue an evaluate endpoint command to
1448 * deal with ep0 max packet size changing once we get the
1449 * descriptors
1450 */
1451 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1452 __func__, added_ctxs);
1453 return 0;
1454 }
1455
1456 virt_dev = xhci->devs[udev->slot_id];
1457 in_ctx = virt_dev->in_ctx;
1458 out_ctx = virt_dev->out_ctx;
1459 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1460 ep_index = xhci_get_endpoint_index(&ep->desc);
1461 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1462
1463 /* If this endpoint is already in use, and the upper layers are trying
1464 * to add it again without dropping it, reject the addition.
1465 */
1466 if (virt_dev->eps[ep_index].ring &&
1467 !(le32_to_cpu(ctrl_ctx->drop_flags) &
1468 xhci_get_endpoint_flag(&ep->desc))) {
1469 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1470 "without dropping it.\n",
1471 (unsigned int) ep->desc.bEndpointAddress);
1472 return -EINVAL;
1473 }
1474
1475 /* If the HCD has already noted the endpoint is enabled,
1476 * ignore this request.
1477 */
1478 if (le32_to_cpu(ctrl_ctx->add_flags) &
1479 xhci_get_endpoint_flag(&ep->desc)) {
1480 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1481 __func__, ep);
1482 return 0;
1483 }
1484
1485 /*
1486 * Configuration and alternate setting changes must be done in
1487 * process context, not interrupt context (or so documenation
1488 * for usb_set_interface() and usb_set_configuration() claim).
1489 */
1490 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1491 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1492 __func__, ep->desc.bEndpointAddress);
1493 return -ENOMEM;
1494 }
1495
1496 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1497 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1498
1499 /* If xhci_endpoint_disable() was called for this endpoint, but the
1500 * xHC hasn't been notified yet through the check_bandwidth() call,
1501 * this re-adds a new state for the endpoint from the new endpoint
1502 * descriptors. We must drop and re-add this endpoint, so we leave the
1503 * drop flags alone.
1504 */
1505 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1506
1507 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1508 /* Update the last valid endpoint context, if we just added one past */
1509 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
1510 LAST_CTX(last_ctx)) {
1511 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1512 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1513 }
1514 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1515
1516 /* Store the usb_device pointer for later use */
1517 ep->hcpriv = udev;
1518
1519 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1520 (unsigned int) ep->desc.bEndpointAddress,
1521 udev->slot_id,
1522 (unsigned int) new_drop_flags,
1523 (unsigned int) new_add_flags,
1524 (unsigned int) new_slot_info);
1525 return 0;
1526}
1527
1528static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1529{
1530 struct xhci_input_control_ctx *ctrl_ctx;
1531 struct xhci_ep_ctx *ep_ctx;
1532 struct xhci_slot_ctx *slot_ctx;
1533 int i;
1534
1535 /* When a device's add flag and drop flag are zero, any subsequent
1536 * configure endpoint command will leave that endpoint's state
1537 * untouched. Make sure we don't leave any old state in the input
1538 * endpoint contexts.
1539 */
1540 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1541 ctrl_ctx->drop_flags = 0;
1542 ctrl_ctx->add_flags = 0;
1543 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1544 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1545 /* Endpoint 0 is always valid */
1546 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1547 for (i = 1; i < 31; ++i) {
1548 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1549 ep_ctx->ep_info = 0;
1550 ep_ctx->ep_info2 = 0;
1551 ep_ctx->deq = 0;
1552 ep_ctx->tx_info = 0;
1553 }
1554}
1555
1556static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1557 struct usb_device *udev, u32 *cmd_status)
1558{
1559 int ret;
1560
1561 switch (*cmd_status) {
1562 case COMP_ENOMEM:
1563 dev_warn(&udev->dev, "Not enough host controller resources "
1564 "for new device state.\n");
1565 ret = -ENOMEM;
1566 /* FIXME: can we allocate more resources for the HC? */
1567 break;
1568 case COMP_BW_ERR:
1569 dev_warn(&udev->dev, "Not enough bandwidth "
1570 "for new device state.\n");
1571 ret = -ENOSPC;
1572 /* FIXME: can we go back to the old state? */
1573 break;
1574 case COMP_TRB_ERR:
1575 /* the HCD set up something wrong */
1576 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1577 "add flag = 1, "
1578 "and endpoint is not disabled.\n");
1579 ret = -EINVAL;
1580 break;
1581 case COMP_DEV_ERR:
1582 dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
1583 "configure command.\n");
1584 ret = -ENODEV;
1585 break;
1586 case COMP_SUCCESS:
1587 dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
1588 ret = 0;
1589 break;
1590 default:
1591 xhci_err(xhci, "ERROR: unexpected command completion "
1592 "code 0x%x.\n", *cmd_status);
1593 ret = -EINVAL;
1594 break;
1595 }
1596 return ret;
1597}
1598
1599static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1600 struct usb_device *udev, u32 *cmd_status)
1601{
1602 int ret;
1603 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1604
1605 switch (*cmd_status) {
1606 case COMP_EINVAL:
1607 dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1608 "context command.\n");
1609 ret = -EINVAL;
1610 break;
1611 case COMP_EBADSLT:
1612 dev_warn(&udev->dev, "WARN: slot not enabled for"
1613 "evaluate context command.\n");
1614 case COMP_CTX_STATE:
1615 dev_warn(&udev->dev, "WARN: invalid context state for "
1616 "evaluate context command.\n");
1617 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1618 ret = -EINVAL;
1619 break;
1620 case COMP_DEV_ERR:
1621 dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
1622 "context command.\n");
1623 ret = -ENODEV;
1624 break;
1625 case COMP_MEL_ERR:
1626 /* Max Exit Latency too large error */
1627 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1628 ret = -EINVAL;
1629 break;
1630 case COMP_SUCCESS:
1631 dev_dbg(&udev->dev, "Successful evaluate context command\n");
1632 ret = 0;
1633 break;
1634 default:
1635 xhci_err(xhci, "ERROR: unexpected command completion "
1636 "code 0x%x.\n", *cmd_status);
1637 ret = -EINVAL;
1638 break;
1639 }
1640 return ret;
1641}
1642
1643static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1644 struct xhci_container_ctx *in_ctx)
1645{
1646 struct xhci_input_control_ctx *ctrl_ctx;
1647 u32 valid_add_flags;
1648 u32 valid_drop_flags;
1649
1650 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1651 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1652 * (bit 1). The default control endpoint is added during the Address
1653 * Device command and is never removed until the slot is disabled.
1654 */
1655 valid_add_flags = ctrl_ctx->add_flags >> 2;
1656 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1657
1658 /* Use hweight32 to count the number of ones in the add flags, or
1659 * number of endpoints added. Don't count endpoints that are changed
1660 * (both added and dropped).
1661 */
1662 return hweight32(valid_add_flags) -
1663 hweight32(valid_add_flags & valid_drop_flags);
1664}
1665
1666static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1667 struct xhci_container_ctx *in_ctx)
1668{
1669 struct xhci_input_control_ctx *ctrl_ctx;
1670 u32 valid_add_flags;
1671 u32 valid_drop_flags;
1672
1673 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1674 valid_add_flags = ctrl_ctx->add_flags >> 2;
1675 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1676
1677 return hweight32(valid_drop_flags) -
1678 hweight32(valid_add_flags & valid_drop_flags);
1679}
1680
1681/*
1682 * We need to reserve the new number of endpoints before the configure endpoint
1683 * command completes. We can't subtract the dropped endpoints from the number
1684 * of active endpoints until the command completes because we can oversubscribe
1685 * the host in this case:
1686 *
1687 * - the first configure endpoint command drops more endpoints than it adds
1688 * - a second configure endpoint command that adds more endpoints is queued
1689 * - the first configure endpoint command fails, so the config is unchanged
1690 * - the second command may succeed, even though there isn't enough resources
1691 *
1692 * Must be called with xhci->lock held.
1693 */
1694static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1695 struct xhci_container_ctx *in_ctx)
1696{
1697 u32 added_eps;
1698
1699 added_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1700 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1701 xhci_dbg(xhci, "Not enough ep ctxs: "
1702 "%u active, need to add %u, limit is %u.\n",
1703 xhci->num_active_eps, added_eps,
1704 xhci->limit_active_eps);
1705 return -ENOMEM;
1706 }
1707 xhci->num_active_eps += added_eps;
1708 xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps,
1709 xhci->num_active_eps);
1710 return 0;
1711}
1712
1713/*
1714 * The configure endpoint was failed by the xHC for some other reason, so we
1715 * need to revert the resources that failed configuration would have used.
1716 *
1717 * Must be called with xhci->lock held.
1718 */
1719static void xhci_free_host_resources(struct xhci_hcd *xhci,
1720 struct xhci_container_ctx *in_ctx)
1721{
1722 u32 num_failed_eps;
1723
1724 num_failed_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1725 xhci->num_active_eps -= num_failed_eps;
1726 xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n",
1727 num_failed_eps,
1728 xhci->num_active_eps);
1729}
1730
1731/*
1732 * Now that the command has completed, clean up the active endpoint count by
1733 * subtracting out the endpoints that were dropped (but not changed).
1734 *
1735 * Must be called with xhci->lock held.
1736 */
1737static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
1738 struct xhci_container_ctx *in_ctx)
1739{
1740 u32 num_dropped_eps;
1741
1742 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, in_ctx);
1743 xhci->num_active_eps -= num_dropped_eps;
1744 if (num_dropped_eps)
1745 xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n",
1746 num_dropped_eps,
1747 xhci->num_active_eps);
1748}
1749
1750/* Issue a configure endpoint command or evaluate context command
1751 * and wait for it to finish.
1752 */
1753static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1754 struct usb_device *udev,
1755 struct xhci_command *command,
1756 bool ctx_change, bool must_succeed)
1757{
1758 int ret;
1759 int timeleft;
1760 unsigned long flags;
1761 struct xhci_container_ctx *in_ctx;
1762 struct completion *cmd_completion;
1763 u32 *cmd_status;
1764 struct xhci_virt_device *virt_dev;
1765
1766 spin_lock_irqsave(&xhci->lock, flags);
1767 virt_dev = xhci->devs[udev->slot_id];
1768 if (command) {
1769 in_ctx = command->in_ctx;
1770 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
1771 xhci_reserve_host_resources(xhci, in_ctx)) {
1772 spin_unlock_irqrestore(&xhci->lock, flags);
1773 xhci_warn(xhci, "Not enough host resources, "
1774 "active endpoint contexts = %u\n",
1775 xhci->num_active_eps);
1776 return -ENOMEM;
1777 }
1778
1779 cmd_completion = command->completion;
1780 cmd_status = &command->status;
1781 command->command_trb = xhci->cmd_ring->enqueue;
1782
1783 /* Enqueue pointer can be left pointing to the link TRB,
1784 * we must handle that
1785 */
1786 if (TRB_TYPE_LINK_LE32(command->command_trb->link.control))
1787 command->command_trb =
1788 xhci->cmd_ring->enq_seg->next->trbs;
1789
1790 list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
1791 } else {
1792 in_ctx = virt_dev->in_ctx;
1793 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
1794 xhci_reserve_host_resources(xhci, in_ctx)) {
1795 spin_unlock_irqrestore(&xhci->lock, flags);
1796 xhci_warn(xhci, "Not enough host resources, "
1797 "active endpoint contexts = %u\n",
1798 xhci->num_active_eps);
1799 return -ENOMEM;
1800 }
1801 cmd_completion = &virt_dev->cmd_completion;
1802 cmd_status = &virt_dev->cmd_status;
1803 }
1804 init_completion(cmd_completion);
1805
1806 if (!ctx_change)
1807 ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
1808 udev->slot_id, must_succeed);
1809 else
1810 ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
1811 udev->slot_id);
1812 if (ret < 0) {
1813 if (command)
1814 list_del(&command->cmd_list);
1815 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
1816 xhci_free_host_resources(xhci, in_ctx);
1817 spin_unlock_irqrestore(&xhci->lock, flags);
1818 xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
1819 return -ENOMEM;
1820 }
1821 xhci_ring_cmd_db(xhci);
1822 spin_unlock_irqrestore(&xhci->lock, flags);
1823
1824 /* Wait for the configure endpoint command to complete */
1825 timeleft = wait_for_completion_interruptible_timeout(
1826 cmd_completion,
1827 USB_CTRL_SET_TIMEOUT);
1828 if (timeleft <= 0) {
1829 xhci_warn(xhci, "%s while waiting for %s command\n",
1830 timeleft == 0 ? "Timeout" : "Signal",
1831 ctx_change == 0 ?
1832 "configure endpoint" :
1833 "evaluate context");
1834 /* FIXME cancel the configure endpoint command */
1835 return -ETIME;
1836 }
1837
1838 if (!ctx_change)
1839 ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
1840 else
1841 ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
1842
1843 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
1844 spin_lock_irqsave(&xhci->lock, flags);
1845 /* If the command failed, remove the reserved resources.
1846 * Otherwise, clean up the estimate to include dropped eps.
1847 */
1848 if (ret)
1849 xhci_free_host_resources(xhci, in_ctx);
1850 else
1851 xhci_finish_resource_reservation(xhci, in_ctx);
1852 spin_unlock_irqrestore(&xhci->lock, flags);
1853 }
1854 return ret;
1855}
1856
1857/* Called after one or more calls to xhci_add_endpoint() or
1858 * xhci_drop_endpoint(). If this call fails, the USB core is expected
1859 * to call xhci_reset_bandwidth().
1860 *
1861 * Since we are in the middle of changing either configuration or
1862 * installing a new alt setting, the USB core won't allow URBs to be
1863 * enqueued for any endpoint on the old config or interface. Nothing
1864 * else should be touching the xhci->devs[slot_id] structure, so we
1865 * don't need to take the xhci->lock for manipulating that.
1866 */
1867int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
1868{
1869 int i;
1870 int ret = 0;
1871 struct xhci_hcd *xhci;
1872 struct xhci_virt_device *virt_dev;
1873 struct xhci_input_control_ctx *ctrl_ctx;
1874 struct xhci_slot_ctx *slot_ctx;
1875
1876 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
1877 if (ret <= 0)
1878 return ret;
1879 xhci = hcd_to_xhci(hcd);
1880 if (xhci->xhc_state & XHCI_STATE_DYING)
1881 return -ENODEV;
1882
1883 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1884 virt_dev = xhci->devs[udev->slot_id];
1885
1886 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
1887 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1888 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
1889 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
1890 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
1891 xhci_dbg(xhci, "New Input Control Context:\n");
1892 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1893 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
1894 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
1895
1896 ret = xhci_configure_endpoint(xhci, udev, NULL,
1897 false, false);
1898 if (ret) {
1899 /* Callee should call reset_bandwidth() */
1900 return ret;
1901 }
1902
1903 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
1904 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
1905 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
1906
1907 /* Free any rings that were dropped, but not changed. */
1908 for (i = 1; i < 31; ++i) {
1909 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
1910 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
1911 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
1912 }
1913 xhci_zero_in_ctx(xhci, virt_dev);
1914 /*
1915 * Install any rings for completely new endpoints or changed endpoints,
1916 * and free or cache any old rings from changed endpoints.
1917 */
1918 for (i = 1; i < 31; ++i) {
1919 if (!virt_dev->eps[i].new_ring)
1920 continue;
1921 /* Only cache or free the old ring if it exists.
1922 * It may not if this is the first add of an endpoint.
1923 */
1924 if (virt_dev->eps[i].ring) {
1925 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
1926 }
1927 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
1928 virt_dev->eps[i].new_ring = NULL;
1929 }
1930
1931 return ret;
1932}
1933
1934void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
1935{
1936 struct xhci_hcd *xhci;
1937 struct xhci_virt_device *virt_dev;
1938 int i, ret;
1939
1940 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
1941 if (ret <= 0)
1942 return;
1943 xhci = hcd_to_xhci(hcd);
1944
1945 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1946 virt_dev = xhci->devs[udev->slot_id];
1947 /* Free any rings allocated for added endpoints */
1948 for (i = 0; i < 31; ++i) {
1949 if (virt_dev->eps[i].new_ring) {
1950 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
1951 virt_dev->eps[i].new_ring = NULL;
1952 }
1953 }
1954 xhci_zero_in_ctx(xhci, virt_dev);
1955}
1956
1957static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
1958 struct xhci_container_ctx *in_ctx,
1959 struct xhci_container_ctx *out_ctx,
1960 u32 add_flags, u32 drop_flags)
1961{
1962 struct xhci_input_control_ctx *ctrl_ctx;
1963 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1964 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
1965 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
1966 xhci_slot_copy(xhci, in_ctx, out_ctx);
1967 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
1968
1969 xhci_dbg(xhci, "Input Context:\n");
1970 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
1971}
1972
1973static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
1974 unsigned int slot_id, unsigned int ep_index,
1975 struct xhci_dequeue_state *deq_state)
1976{
1977 struct xhci_container_ctx *in_ctx;
1978 struct xhci_ep_ctx *ep_ctx;
1979 u32 added_ctxs;
1980 dma_addr_t addr;
1981
1982 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1983 xhci->devs[slot_id]->out_ctx, ep_index);
1984 in_ctx = xhci->devs[slot_id]->in_ctx;
1985 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1986 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
1987 deq_state->new_deq_ptr);
1988 if (addr == 0) {
1989 xhci_warn(xhci, "WARN Cannot submit config ep after "
1990 "reset ep command\n");
1991 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
1992 deq_state->new_deq_seg,
1993 deq_state->new_deq_ptr);
1994 return;
1995 }
1996 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
1997
1998 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
1999 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2000 xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
2001}
2002
2003void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2004 struct usb_device *udev, unsigned int ep_index)
2005{
2006 struct xhci_dequeue_state deq_state;
2007 struct xhci_virt_ep *ep;
2008
2009 xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
2010 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2011 /* We need to move the HW's dequeue pointer past this TD,
2012 * or it will attempt to resend it on the next doorbell ring.
2013 */
2014 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2015 ep_index, ep->stopped_stream, ep->stopped_td,
2016 &deq_state);
2017
2018 /* HW with the reset endpoint quirk will use the saved dequeue state to
2019 * issue a configure endpoint command later.
2020 */
2021 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2022 xhci_dbg(xhci, "Queueing new dequeue state\n");
2023 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2024 ep_index, ep->stopped_stream, &deq_state);
2025 } else {
2026 /* Better hope no one uses the input context between now and the
2027 * reset endpoint completion!
2028 * XXX: No idea how this hardware will react when stream rings
2029 * are enabled.
2030 */
2031 xhci_dbg(xhci, "Setting up input context for "
2032 "configure endpoint command\n");
2033 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2034 ep_index, &deq_state);
2035 }
2036}
2037
2038/* Deal with stalled endpoints. The core should have sent the control message
2039 * to clear the halt condition. However, we need to make the xHCI hardware
2040 * reset its sequence number, since a device will expect a sequence number of
2041 * zero after the halt condition is cleared.
2042 * Context: in_interrupt
2043 */
2044void xhci_endpoint_reset(struct usb_hcd *hcd,
2045 struct usb_host_endpoint *ep)
2046{
2047 struct xhci_hcd *xhci;
2048 struct usb_device *udev;
2049 unsigned int ep_index;
2050 unsigned long flags;
2051 int ret;
2052 struct xhci_virt_ep *virt_ep;
2053
2054 xhci = hcd_to_xhci(hcd);
2055 udev = (struct usb_device *) ep->hcpriv;
2056 /* Called with a root hub endpoint (or an endpoint that wasn't added
2057 * with xhci_add_endpoint()
2058 */
2059 if (!ep->hcpriv)
2060 return;
2061 ep_index = xhci_get_endpoint_index(&ep->desc);
2062 virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2063 if (!virt_ep->stopped_td) {
2064 xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
2065 ep->desc.bEndpointAddress);
2066 return;
2067 }
2068 if (usb_endpoint_xfer_control(&ep->desc)) {
2069 xhci_dbg(xhci, "Control endpoint stall already handled.\n");
2070 return;
2071 }
2072
2073 xhci_dbg(xhci, "Queueing reset endpoint command\n");
2074 spin_lock_irqsave(&xhci->lock, flags);
2075 ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
2076 /*
2077 * Can't change the ring dequeue pointer until it's transitioned to the
2078 * stopped state, which is only upon a successful reset endpoint
2079 * command. Better hope that last command worked!
2080 */
2081 if (!ret) {
2082 xhci_cleanup_stalled_ring(xhci, udev, ep_index);
2083 kfree(virt_ep->stopped_td);
2084 xhci_ring_cmd_db(xhci);
2085 }
2086 virt_ep->stopped_td = NULL;
2087 virt_ep->stopped_trb = NULL;
2088 virt_ep->stopped_stream = 0;
2089 spin_unlock_irqrestore(&xhci->lock, flags);
2090
2091 if (ret)
2092 xhci_warn(xhci, "FIXME allocate a new ring segment\n");
2093}
2094
2095static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2096 struct usb_device *udev, struct usb_host_endpoint *ep,
2097 unsigned int slot_id)
2098{
2099 int ret;
2100 unsigned int ep_index;
2101 unsigned int ep_state;
2102
2103 if (!ep)
2104 return -EINVAL;
2105 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2106 if (ret <= 0)
2107 return -EINVAL;
2108 if (ep->ss_ep_comp.bmAttributes == 0) {
2109 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2110 " descriptor for ep 0x%x does not support streams\n",
2111 ep->desc.bEndpointAddress);
2112 return -EINVAL;
2113 }
2114
2115 ep_index = xhci_get_endpoint_index(&ep->desc);
2116 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2117 if (ep_state & EP_HAS_STREAMS ||
2118 ep_state & EP_GETTING_STREAMS) {
2119 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2120 "already has streams set up.\n",
2121 ep->desc.bEndpointAddress);
2122 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2123 "dynamic stream context array reallocation.\n");
2124 return -EINVAL;
2125 }
2126 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2127 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2128 "endpoint 0x%x; URBs are pending.\n",
2129 ep->desc.bEndpointAddress);
2130 return -EINVAL;
2131 }
2132 return 0;
2133}
2134
2135static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
2136 unsigned int *num_streams, unsigned int *num_stream_ctxs)
2137{
2138 unsigned int max_streams;
2139
2140 /* The stream context array size must be a power of two */
2141 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
2142 /*
2143 * Find out how many primary stream array entries the host controller
2144 * supports. Later we may use secondary stream arrays (similar to 2nd
2145 * level page entries), but that's an optional feature for xHCI host
2146 * controllers. xHCs must support at least 4 stream IDs.
2147 */
2148 max_streams = HCC_MAX_PSA(xhci->hcc_params);
2149 if (*num_stream_ctxs > max_streams) {
2150 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
2151 max_streams);
2152 *num_stream_ctxs = max_streams;
2153 *num_streams = max_streams;
2154 }
2155}
2156
2157/* Returns an error code if one of the endpoint already has streams.
2158 * This does not change any data structures, it only checks and gathers
2159 * information.
2160 */
2161static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
2162 struct usb_device *udev,
2163 struct usb_host_endpoint **eps, unsigned int num_eps,
2164 unsigned int *num_streams, u32 *changed_ep_bitmask)
2165{
2166 unsigned int max_streams;
2167 unsigned int endpoint_flag;
2168 int i;
2169 int ret;
2170
2171 for (i = 0; i < num_eps; i++) {
2172 ret = xhci_check_streams_endpoint(xhci, udev,
2173 eps[i], udev->slot_id);
2174 if (ret < 0)
2175 return ret;
2176
2177 max_streams = USB_SS_MAX_STREAMS(
2178 eps[i]->ss_ep_comp.bmAttributes);
2179 if (max_streams < (*num_streams - 1)) {
2180 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
2181 eps[i]->desc.bEndpointAddress,
2182 max_streams);
2183 *num_streams = max_streams+1;
2184 }
2185
2186 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
2187 if (*changed_ep_bitmask & endpoint_flag)
2188 return -EINVAL;
2189 *changed_ep_bitmask |= endpoint_flag;
2190 }
2191 return 0;
2192}
2193
2194static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
2195 struct usb_device *udev,
2196 struct usb_host_endpoint **eps, unsigned int num_eps)
2197{
2198 u32 changed_ep_bitmask = 0;
2199 unsigned int slot_id;
2200 unsigned int ep_index;
2201 unsigned int ep_state;
2202 int i;
2203
2204 slot_id = udev->slot_id;
2205 if (!xhci->devs[slot_id])
2206 return 0;
2207
2208 for (i = 0; i < num_eps; i++) {
2209 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2210 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2211 /* Are streams already being freed for the endpoint? */
2212 if (ep_state & EP_GETTING_NO_STREAMS) {
2213 xhci_warn(xhci, "WARN Can't disable streams for "
2214 "endpoint 0x%x\n, "
2215 "streams are being disabled already.",
2216 eps[i]->desc.bEndpointAddress);
2217 return 0;
2218 }
2219 /* Are there actually any streams to free? */
2220 if (!(ep_state & EP_HAS_STREAMS) &&
2221 !(ep_state & EP_GETTING_STREAMS)) {
2222 xhci_warn(xhci, "WARN Can't disable streams for "
2223 "endpoint 0x%x\n, "
2224 "streams are already disabled!",
2225 eps[i]->desc.bEndpointAddress);
2226 xhci_warn(xhci, "WARN xhci_free_streams() called "
2227 "with non-streams endpoint\n");
2228 return 0;
2229 }
2230 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
2231 }
2232 return changed_ep_bitmask;
2233}
2234
2235/*
2236 * The USB device drivers use this function (though the HCD interface in USB
2237 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
2238 * coordinate mass storage command queueing across multiple endpoints (basically
2239 * a stream ID == a task ID).
2240 *
2241 * Setting up streams involves allocating the same size stream context array
2242 * for each endpoint and issuing a configure endpoint command for all endpoints.
2243 *
2244 * Don't allow the call to succeed if one endpoint only supports one stream
2245 * (which means it doesn't support streams at all).
2246 *
2247 * Drivers may get less stream IDs than they asked for, if the host controller
2248 * hardware or endpoints claim they can't support the number of requested
2249 * stream IDs.
2250 */
2251int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
2252 struct usb_host_endpoint **eps, unsigned int num_eps,
2253 unsigned int num_streams, gfp_t mem_flags)
2254{
2255 int i, ret;
2256 struct xhci_hcd *xhci;
2257 struct xhci_virt_device *vdev;
2258 struct xhci_command *config_cmd;
2259 unsigned int ep_index;
2260 unsigned int num_stream_ctxs;
2261 unsigned long flags;
2262 u32 changed_ep_bitmask = 0;
2263
2264 if (!eps)
2265 return -EINVAL;
2266
2267 /* Add one to the number of streams requested to account for
2268 * stream 0 that is reserved for xHCI usage.
2269 */
2270 num_streams += 1;
2271 xhci = hcd_to_xhci(hcd);
2272 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
2273 num_streams);
2274
2275 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
2276 if (!config_cmd) {
2277 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
2278 return -ENOMEM;
2279 }
2280
2281 /* Check to make sure all endpoints are not already configured for
2282 * streams. While we're at it, find the maximum number of streams that
2283 * all the endpoints will support and check for duplicate endpoints.
2284 */
2285 spin_lock_irqsave(&xhci->lock, flags);
2286 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
2287 num_eps, &num_streams, &changed_ep_bitmask);
2288 if (ret < 0) {
2289 xhci_free_command(xhci, config_cmd);
2290 spin_unlock_irqrestore(&xhci->lock, flags);
2291 return ret;
2292 }
2293 if (num_streams <= 1) {
2294 xhci_warn(xhci, "WARN: endpoints can't handle "
2295 "more than one stream.\n");
2296 xhci_free_command(xhci, config_cmd);
2297 spin_unlock_irqrestore(&xhci->lock, flags);
2298 return -EINVAL;
2299 }
2300 vdev = xhci->devs[udev->slot_id];
2301 /* Mark each endpoint as being in transition, so
2302 * xhci_urb_enqueue() will reject all URBs.
2303 */
2304 for (i = 0; i < num_eps; i++) {
2305 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2306 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
2307 }
2308 spin_unlock_irqrestore(&xhci->lock, flags);
2309
2310 /* Setup internal data structures and allocate HW data structures for
2311 * streams (but don't install the HW structures in the input context
2312 * until we're sure all memory allocation succeeded).
2313 */
2314 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
2315 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
2316 num_stream_ctxs, num_streams);
2317
2318 for (i = 0; i < num_eps; i++) {
2319 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2320 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
2321 num_stream_ctxs,
2322 num_streams, mem_flags);
2323 if (!vdev->eps[ep_index].stream_info)
2324 goto cleanup;
2325 /* Set maxPstreams in endpoint context and update deq ptr to
2326 * point to stream context array. FIXME
2327 */
2328 }
2329
2330 /* Set up the input context for a configure endpoint command. */
2331 for (i = 0; i < num_eps; i++) {
2332 struct xhci_ep_ctx *ep_ctx;
2333
2334 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2335 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
2336
2337 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
2338 vdev->out_ctx, ep_index);
2339 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
2340 vdev->eps[ep_index].stream_info);
2341 }
2342 /* Tell the HW to drop its old copy of the endpoint context info
2343 * and add the updated copy from the input context.
2344 */
2345 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
2346 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
2347
2348 /* Issue and wait for the configure endpoint command */
2349 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
2350 false, false);
2351
2352 /* xHC rejected the configure endpoint command for some reason, so we
2353 * leave the old ring intact and free our internal streams data
2354 * structure.
2355 */
2356 if (ret < 0)
2357 goto cleanup;
2358
2359 spin_lock_irqsave(&xhci->lock, flags);
2360 for (i = 0; i < num_eps; i++) {
2361 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2362 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
2363 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
2364 udev->slot_id, ep_index);
2365 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
2366 }
2367 xhci_free_command(xhci, config_cmd);
2368 spin_unlock_irqrestore(&xhci->lock, flags);
2369
2370 /* Subtract 1 for stream 0, which drivers can't use */
2371 return num_streams - 1;
2372
2373cleanup:
2374 /* If it didn't work, free the streams! */
2375 for (i = 0; i < num_eps; i++) {
2376 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2377 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
2378 vdev->eps[ep_index].stream_info = NULL;
2379 /* FIXME Unset maxPstreams in endpoint context and
2380 * update deq ptr to point to normal string ring.
2381 */
2382 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
2383 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
2384 xhci_endpoint_zero(xhci, vdev, eps[i]);
2385 }
2386 xhci_free_command(xhci, config_cmd);
2387 return -ENOMEM;
2388}
2389
2390/* Transition the endpoint from using streams to being a "normal" endpoint
2391 * without streams.
2392 *
2393 * Modify the endpoint context state, submit a configure endpoint command,
2394 * and free all endpoint rings for streams if that completes successfully.
2395 */
2396int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
2397 struct usb_host_endpoint **eps, unsigned int num_eps,
2398 gfp_t mem_flags)
2399{
2400 int i, ret;
2401 struct xhci_hcd *xhci;
2402 struct xhci_virt_device *vdev;
2403 struct xhci_command *command;
2404 unsigned int ep_index;
2405 unsigned long flags;
2406 u32 changed_ep_bitmask;
2407
2408 xhci = hcd_to_xhci(hcd);
2409 vdev = xhci->devs[udev->slot_id];
2410
2411 /* Set up a configure endpoint command to remove the streams rings */
2412 spin_lock_irqsave(&xhci->lock, flags);
2413 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
2414 udev, eps, num_eps);
2415 if (changed_ep_bitmask == 0) {
2416 spin_unlock_irqrestore(&xhci->lock, flags);
2417 return -EINVAL;
2418 }
2419
2420 /* Use the xhci_command structure from the first endpoint. We may have
2421 * allocated too many, but the driver may call xhci_free_streams() for
2422 * each endpoint it grouped into one call to xhci_alloc_streams().
2423 */
2424 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
2425 command = vdev->eps[ep_index].stream_info->free_streams_command;
2426 for (i = 0; i < num_eps; i++) {
2427 struct xhci_ep_ctx *ep_ctx;
2428
2429 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2430 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
2431 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
2432 EP_GETTING_NO_STREAMS;
2433
2434 xhci_endpoint_copy(xhci, command->in_ctx,
2435 vdev->out_ctx, ep_index);
2436 xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
2437 &vdev->eps[ep_index]);
2438 }
2439 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
2440 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
2441 spin_unlock_irqrestore(&xhci->lock, flags);
2442
2443 /* Issue and wait for the configure endpoint command,
2444 * which must succeed.
2445 */
2446 ret = xhci_configure_endpoint(xhci, udev, command,
2447 false, true);
2448
2449 /* xHC rejected the configure endpoint command for some reason, so we
2450 * leave the streams rings intact.
2451 */
2452 if (ret < 0)
2453 return ret;
2454
2455 spin_lock_irqsave(&xhci->lock, flags);
2456 for (i = 0; i < num_eps; i++) {
2457 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2458 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
2459 vdev->eps[ep_index].stream_info = NULL;
2460 /* FIXME Unset maxPstreams in endpoint context and
2461 * update deq ptr to point to normal string ring.
2462 */
2463 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
2464 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
2465 }
2466 spin_unlock_irqrestore(&xhci->lock, flags);
2467
2468 return 0;
2469}
2470
2471/*
2472 * Deletes endpoint resources for endpoints that were active before a Reset
2473 * Device command, or a Disable Slot command. The Reset Device command leaves
2474 * the control endpoint intact, whereas the Disable Slot command deletes it.
2475 *
2476 * Must be called with xhci->lock held.
2477 */
2478void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2479 struct xhci_virt_device *virt_dev, bool drop_control_ep)
2480{
2481 int i;
2482 unsigned int num_dropped_eps = 0;
2483 unsigned int drop_flags = 0;
2484
2485 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
2486 if (virt_dev->eps[i].ring) {
2487 drop_flags |= 1 << i;
2488 num_dropped_eps++;
2489 }
2490 }
2491 xhci->num_active_eps -= num_dropped_eps;
2492 if (num_dropped_eps)
2493 xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, "
2494 "%u now active.\n",
2495 num_dropped_eps, drop_flags,
2496 xhci->num_active_eps);
2497}
2498
2499/*
2500 * This submits a Reset Device Command, which will set the device state to 0,
2501 * set the device address to 0, and disable all the endpoints except the default
2502 * control endpoint. The USB core should come back and call
2503 * xhci_address_device(), and then re-set up the configuration. If this is
2504 * called because of a usb_reset_and_verify_device(), then the old alternate
2505 * settings will be re-installed through the normal bandwidth allocation
2506 * functions.
2507 *
2508 * Wait for the Reset Device command to finish. Remove all structures
2509 * associated with the endpoints that were disabled. Clear the input device
2510 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
2511 *
2512 * If the virt_dev to be reset does not exist or does not match the udev,
2513 * it means the device is lost, possibly due to the xHC restore error and
2514 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
2515 * re-allocate the device.
2516 */
2517int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
2518{
2519 int ret, i;
2520 unsigned long flags;
2521 struct xhci_hcd *xhci;
2522 unsigned int slot_id;
2523 struct xhci_virt_device *virt_dev;
2524 struct xhci_command *reset_device_cmd;
2525 int timeleft;
2526 int last_freed_endpoint;
2527 struct xhci_slot_ctx *slot_ctx;
2528
2529 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
2530 if (ret <= 0)
2531 return ret;
2532 xhci = hcd_to_xhci(hcd);
2533 slot_id = udev->slot_id;
2534 virt_dev = xhci->devs[slot_id];
2535 if (!virt_dev) {
2536 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
2537 "not exist. Re-allocate the device\n", slot_id);
2538 ret = xhci_alloc_dev(hcd, udev);
2539 if (ret == 1)
2540 return 0;
2541 else
2542 return -EINVAL;
2543 }
2544
2545 if (virt_dev->udev != udev) {
2546 /* If the virt_dev and the udev does not match, this virt_dev
2547 * may belong to another udev.
2548 * Re-allocate the device.
2549 */
2550 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
2551 "not match the udev. Re-allocate the device\n",
2552 slot_id);
2553 ret = xhci_alloc_dev(hcd, udev);
2554 if (ret == 1)
2555 return 0;
2556 else
2557 return -EINVAL;
2558 }
2559
2560 /* If device is not setup, there is no point in resetting it */
2561 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
2562 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
2563 SLOT_STATE_DISABLED)
2564 return 0;
2565
2566 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
2567 /* Allocate the command structure that holds the struct completion.
2568 * Assume we're in process context, since the normal device reset
2569 * process has to wait for the device anyway. Storage devices are
2570 * reset as part of error handling, so use GFP_NOIO instead of
2571 * GFP_KERNEL.
2572 */
2573 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
2574 if (!reset_device_cmd) {
2575 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
2576 return -ENOMEM;
2577 }
2578
2579 /* Attempt to submit the Reset Device command to the command ring */
2580 spin_lock_irqsave(&xhci->lock, flags);
2581 reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
2582
2583 /* Enqueue pointer can be left pointing to the link TRB,
2584 * we must handle that
2585 */
2586 if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control))
2587 reset_device_cmd->command_trb =
2588 xhci->cmd_ring->enq_seg->next->trbs;
2589
2590 list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
2591 ret = xhci_queue_reset_device(xhci, slot_id);
2592 if (ret) {
2593 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2594 list_del(&reset_device_cmd->cmd_list);
2595 spin_unlock_irqrestore(&xhci->lock, flags);
2596 goto command_cleanup;
2597 }
2598 xhci_ring_cmd_db(xhci);
2599 spin_unlock_irqrestore(&xhci->lock, flags);
2600
2601 /* Wait for the Reset Device command to finish */
2602 timeleft = wait_for_completion_interruptible_timeout(
2603 reset_device_cmd->completion,
2604 USB_CTRL_SET_TIMEOUT);
2605 if (timeleft <= 0) {
2606 xhci_warn(xhci, "%s while waiting for reset device command\n",
2607 timeleft == 0 ? "Timeout" : "Signal");
2608 spin_lock_irqsave(&xhci->lock, flags);
2609 /* The timeout might have raced with the event ring handler, so
2610 * only delete from the list if the item isn't poisoned.
2611 */
2612 if (reset_device_cmd->cmd_list.next != LIST_POISON1)
2613 list_del(&reset_device_cmd->cmd_list);
2614 spin_unlock_irqrestore(&xhci->lock, flags);
2615 ret = -ETIME;
2616 goto command_cleanup;
2617 }
2618
2619 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
2620 * unless we tried to reset a slot ID that wasn't enabled,
2621 * or the device wasn't in the addressed or configured state.
2622 */
2623 ret = reset_device_cmd->status;
2624 switch (ret) {
2625 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
2626 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
2627 xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
2628 slot_id,
2629 xhci_get_slot_state(xhci, virt_dev->out_ctx));
2630 xhci_info(xhci, "Not freeing device rings.\n");
2631 /* Don't treat this as an error. May change my mind later. */
2632 ret = 0;
2633 goto command_cleanup;
2634 case COMP_SUCCESS:
2635 xhci_dbg(xhci, "Successful reset device command.\n");
2636 break;
2637 default:
2638 if (xhci_is_vendor_info_code(xhci, ret))
2639 break;
2640 xhci_warn(xhci, "Unknown completion code %u for "
2641 "reset device command.\n", ret);
2642 ret = -EINVAL;
2643 goto command_cleanup;
2644 }
2645
2646 /* Free up host controller endpoint resources */
2647 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2648 spin_lock_irqsave(&xhci->lock, flags);
2649 /* Don't delete the default control endpoint resources */
2650 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
2651 spin_unlock_irqrestore(&xhci->lock, flags);
2652 }
2653
2654 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
2655 last_freed_endpoint = 1;
2656 for (i = 1; i < 31; ++i) {
2657 struct xhci_virt_ep *ep = &virt_dev->eps[i];
2658
2659 if (ep->ep_state & EP_HAS_STREAMS) {
2660 xhci_free_stream_info(xhci, ep->stream_info);
2661 ep->stream_info = NULL;
2662 ep->ep_state &= ~EP_HAS_STREAMS;
2663 }
2664
2665 if (ep->ring) {
2666 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2667 last_freed_endpoint = i;
2668 }
2669 }
2670 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
2671 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
2672 ret = 0;
2673
2674command_cleanup:
2675 xhci_free_command(xhci, reset_device_cmd);
2676 return ret;
2677}
2678
2679/*
2680 * At this point, the struct usb_device is about to go away, the device has
2681 * disconnected, and all traffic has been stopped and the endpoints have been
2682 * disabled. Free any HC data structures associated with that device.
2683 */
2684void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
2685{
2686 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2687 struct xhci_virt_device *virt_dev;
2688 unsigned long flags;
2689 u32 state;
2690 int i, ret;
2691
2692 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2693 /* If the host is halted due to driver unload, we still need to free the
2694 * device.
2695 */
2696 if (ret <= 0 && ret != -ENODEV)
2697 return;
2698
2699 virt_dev = xhci->devs[udev->slot_id];
2700
2701 /* Stop any wayward timer functions (which may grab the lock) */
2702 for (i = 0; i < 31; ++i) {
2703 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
2704 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
2705 }
2706
2707 spin_lock_irqsave(&xhci->lock, flags);
2708 /* Don't disable the slot if the host controller is dead. */
2709 state = xhci_readl(xhci, &xhci->op_regs->status);
2710 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
2711 (xhci->xhc_state & XHCI_STATE_HALTED)) {
2712 xhci_free_virt_device(xhci, udev->slot_id);
2713 spin_unlock_irqrestore(&xhci->lock, flags);
2714 return;
2715 }
2716
2717 if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
2718 spin_unlock_irqrestore(&xhci->lock, flags);
2719 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2720 return;
2721 }
2722 xhci_ring_cmd_db(xhci);
2723 spin_unlock_irqrestore(&xhci->lock, flags);
2724 /*
2725 * Event command completion handler will free any data structures
2726 * associated with the slot. XXX Can free sleep?
2727 */
2728}
2729
2730/*
2731 * Checks if we have enough host controller resources for the default control
2732 * endpoint.
2733 *
2734 * Must be called with xhci->lock held.
2735 */
2736static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
2737{
2738 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
2739 xhci_dbg(xhci, "Not enough ep ctxs: "
2740 "%u active, need to add 1, limit is %u.\n",
2741 xhci->num_active_eps, xhci->limit_active_eps);
2742 return -ENOMEM;
2743 }
2744 xhci->num_active_eps += 1;
2745 xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n",
2746 xhci->num_active_eps);
2747 return 0;
2748}
2749
2750
2751/*
2752 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
2753 * timed out, or allocating memory failed. Returns 1 on success.
2754 */
2755int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
2756{
2757 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2758 unsigned long flags;
2759 int timeleft;
2760 int ret;
2761
2762 spin_lock_irqsave(&xhci->lock, flags);
2763 ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
2764 if (ret) {
2765 spin_unlock_irqrestore(&xhci->lock, flags);
2766 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2767 return 0;
2768 }
2769 xhci_ring_cmd_db(xhci);
2770 spin_unlock_irqrestore(&xhci->lock, flags);
2771
2772 /* XXX: how much time for xHC slot assignment? */
2773 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
2774 USB_CTRL_SET_TIMEOUT);
2775 if (timeleft <= 0) {
2776 xhci_warn(xhci, "%s while waiting for a slot\n",
2777 timeleft == 0 ? "Timeout" : "Signal");
2778 /* FIXME cancel the enable slot request */
2779 return 0;
2780 }
2781
2782 if (!xhci->slot_id) {
2783 xhci_err(xhci, "Error while assigning device slot ID\n");
2784 return 0;
2785 }
2786
2787 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2788 spin_lock_irqsave(&xhci->lock, flags);
2789 ret = xhci_reserve_host_control_ep_resources(xhci);
2790 if (ret) {
2791 spin_unlock_irqrestore(&xhci->lock, flags);
2792 xhci_warn(xhci, "Not enough host resources, "
2793 "active endpoint contexts = %u\n",
2794 xhci->num_active_eps);
2795 goto disable_slot;
2796 }
2797 spin_unlock_irqrestore(&xhci->lock, flags);
2798 }
2799 /* Use GFP_NOIO, since this function can be called from
2800 * xhci_discover_or_reset_device(), which may be called as part of
2801 * mass storage driver error handling.
2802 */
2803 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
2804 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
2805 goto disable_slot;
2806 }
2807 udev->slot_id = xhci->slot_id;
2808 /* Is this a LS or FS device under a HS hub? */
2809 /* Hub or peripherial? */
2810 return 1;
2811
2812disable_slot:
2813 /* Disable slot, if we can do it without mem alloc */
2814 spin_lock_irqsave(&xhci->lock, flags);
2815 if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
2816 xhci_ring_cmd_db(xhci);
2817 spin_unlock_irqrestore(&xhci->lock, flags);
2818 return 0;
2819}
2820
2821/*
2822 * Issue an Address Device command (which will issue a SetAddress request to
2823 * the device).
2824 * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
2825 * we should only issue and wait on one address command at the same time.
2826 *
2827 * We add one to the device address issued by the hardware because the USB core
2828 * uses address 1 for the root hubs (even though they're not really devices).
2829 */
2830int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
2831{
2832 unsigned long flags;
2833 int timeleft;
2834 struct xhci_virt_device *virt_dev;
2835 int ret = 0;
2836 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2837 struct xhci_slot_ctx *slot_ctx;
2838 struct xhci_input_control_ctx *ctrl_ctx;
2839 u64 temp_64;
2840
2841 if (!udev->slot_id) {
2842 xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
2843 return -EINVAL;
2844 }
2845
2846 virt_dev = xhci->devs[udev->slot_id];
2847
2848 if (WARN_ON(!virt_dev)) {
2849 /*
2850 * In plug/unplug torture test with an NEC controller,
2851 * a zero-dereference was observed once due to virt_dev = 0.
2852 * Print useful debug rather than crash if it is observed again!
2853 */
2854 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
2855 udev->slot_id);
2856 return -EINVAL;
2857 }
2858
2859 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2860 /*
2861 * If this is the first Set Address since device plug-in or
2862 * virt_device realloaction after a resume with an xHCI power loss,
2863 * then set up the slot context.
2864 */
2865 if (!slot_ctx->dev_info)
2866 xhci_setup_addressable_virt_dev(xhci, udev);
2867 /* Otherwise, update the control endpoint ring enqueue pointer. */
2868 else
2869 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
2870 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
2871 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
2872
2873 spin_lock_irqsave(&xhci->lock, flags);
2874 ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
2875 udev->slot_id);
2876 if (ret) {
2877 spin_unlock_irqrestore(&xhci->lock, flags);
2878 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
2879 return ret;
2880 }
2881 xhci_ring_cmd_db(xhci);
2882 spin_unlock_irqrestore(&xhci->lock, flags);
2883
2884 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
2885 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
2886 USB_CTRL_SET_TIMEOUT);
2887 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
2888 * the SetAddress() "recovery interval" required by USB and aborting the
2889 * command on a timeout.
2890 */
2891 if (timeleft <= 0) {
2892 xhci_warn(xhci, "%s while waiting for a slot\n",
2893 timeleft == 0 ? "Timeout" : "Signal");
2894 /* FIXME cancel the address device command */
2895 return -ETIME;
2896 }
2897
2898 switch (virt_dev->cmd_status) {
2899 case COMP_CTX_STATE:
2900 case COMP_EBADSLT:
2901 xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
2902 udev->slot_id);
2903 ret = -EINVAL;
2904 break;
2905 case COMP_TX_ERR:
2906 dev_warn(&udev->dev, "Device not responding to set address.\n");
2907 ret = -EPROTO;
2908 break;
2909 case COMP_DEV_ERR:
2910 dev_warn(&udev->dev, "ERROR: Incompatible device for address "
2911 "device command.\n");
2912 ret = -ENODEV;
2913 break;
2914 case COMP_SUCCESS:
2915 xhci_dbg(xhci, "Successful Address Device command\n");
2916 break;
2917 default:
2918 xhci_err(xhci, "ERROR: unexpected command completion "
2919 "code 0x%x.\n", virt_dev->cmd_status);
2920 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
2921 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
2922 ret = -EINVAL;
2923 break;
2924 }
2925 if (ret) {
2926 return ret;
2927 }
2928 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
2929 xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
2930 xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
2931 udev->slot_id,
2932 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
2933 (unsigned long long)
2934 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
2935 xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
2936 (unsigned long long)virt_dev->out_ctx->dma);
2937 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
2938 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
2939 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
2940 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
2941 /*
2942 * USB core uses address 1 for the roothubs, so we add one to the
2943 * address given back to us by the HC.
2944 */
2945 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
2946 /* Use kernel assigned address for devices; store xHC assigned
2947 * address locally. */
2948 virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
2949 + 1;
2950 /* Zero the input context control for later use */
2951 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
2952 ctrl_ctx->add_flags = 0;
2953 ctrl_ctx->drop_flags = 0;
2954
2955 xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address);
2956
2957 return 0;
2958}
2959
2960/* Once a hub descriptor is fetched for a device, we need to update the xHC's
2961 * internal data structures for the device.
2962 */
2963int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
2964 struct usb_tt *tt, gfp_t mem_flags)
2965{
2966 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2967 struct xhci_virt_device *vdev;
2968 struct xhci_command *config_cmd;
2969 struct xhci_input_control_ctx *ctrl_ctx;
2970 struct xhci_slot_ctx *slot_ctx;
2971 unsigned long flags;
2972 unsigned think_time;
2973 int ret;
2974
2975 /* Ignore root hubs */
2976 if (!hdev->parent)
2977 return 0;
2978
2979 vdev = xhci->devs[hdev->slot_id];
2980 if (!vdev) {
2981 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
2982 return -EINVAL;
2983 }
2984 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
2985 if (!config_cmd) {
2986 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
2987 return -ENOMEM;
2988 }
2989
2990 spin_lock_irqsave(&xhci->lock, flags);
2991 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
2992 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
2993 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2994 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
2995 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
2996 if (tt->multi)
2997 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
2998 if (xhci->hci_version > 0x95) {
2999 xhci_dbg(xhci, "xHCI version %x needs hub "
3000 "TT think time and number of ports\n",
3001 (unsigned int) xhci->hci_version);
3002 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
3003 /* Set TT think time - convert from ns to FS bit times.
3004 * 0 = 8 FS bit times, 1 = 16 FS bit times,
3005 * 2 = 24 FS bit times, 3 = 32 FS bit times.
3006 *
3007 * xHCI 1.0: this field shall be 0 if the device is not a
3008 * High-spped hub.
3009 */
3010 think_time = tt->think_time;
3011 if (think_time != 0)
3012 think_time = (think_time / 666) - 1;
3013 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
3014 slot_ctx->tt_info |=
3015 cpu_to_le32(TT_THINK_TIME(think_time));
3016 } else {
3017 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
3018 "TT think time or number of ports\n",
3019 (unsigned int) xhci->hci_version);
3020 }
3021 slot_ctx->dev_state = 0;
3022 spin_unlock_irqrestore(&xhci->lock, flags);
3023
3024 xhci_dbg(xhci, "Set up %s for hub device.\n",
3025 (xhci->hci_version > 0x95) ?
3026 "configure endpoint" : "evaluate context");
3027 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
3028 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
3029
3030 /* Issue and wait for the configure endpoint or
3031 * evaluate context command.
3032 */
3033 if (xhci->hci_version > 0x95)
3034 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
3035 false, false);
3036 else
3037 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
3038 true, false);
3039
3040 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
3041 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
3042
3043 xhci_free_command(xhci, config_cmd);
3044 return ret;
3045}
3046
3047int xhci_get_frame(struct usb_hcd *hcd)
3048{
3049 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3050 /* EHCI mods by the periodic size. Why? */
3051 return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
3052}
3053
3054MODULE_DESCRIPTION(DRIVER_DESC);
3055MODULE_AUTHOR(DRIVER_AUTHOR);
3056MODULE_LICENSE("GPL");
3057
3058static int __init xhci_hcd_init(void)
3059{
3060#ifdef CONFIG_PCI
3061 int retval = 0;
3062
3063 retval = xhci_register_pci();
3064
3065 if (retval < 0) {
3066 printk(KERN_DEBUG "Problem registering PCI driver.");
3067 return retval;
3068 }
3069#endif
3070 /*
3071 * Check the compiler generated sizes of structures that must be laid
3072 * out in specific ways for hardware access.
3073 */
3074 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
3075 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
3076 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
3077 /* xhci_device_control has eight fields, and also
3078 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
3079 */
3080 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
3081 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
3082 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
3083 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
3084 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
3085 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
3086 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
3087 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
3088 return 0;
3089}
3090module_init(xhci_hcd_init);
3091
3092static void __exit xhci_hcd_cleanup(void)
3093{
3094#ifdef CONFIG_PCI
3095 xhci_unregister_pci();
3096#endif
3097}
3098module_exit(xhci_hcd_cleanup);
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/irq.h>
25#include <linux/log2.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/slab.h>
29#include <linux/dmi.h>
30#include <linux/dma-mapping.h>
31
32#include "xhci.h"
33#include "xhci-trace.h"
34#include "xhci-mtk.h"
35
36#define DRIVER_AUTHOR "Sarah Sharp"
37#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
38
39#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
40
41/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
42static int link_quirk;
43module_param(link_quirk, int, S_IRUGO | S_IWUSR);
44MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
45
46static unsigned int quirks;
47module_param(quirks, uint, S_IRUGO);
48MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
49
50/* TODO: copied from ehci-hcd.c - can this be refactored? */
51/*
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
57 *
58 * Returns negative errno, or zero on success
59 *
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
63 */
64int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
65{
66 u32 result;
67
68 do {
69 result = readl(ptr);
70 if (result == ~(u32)0) /* card removed */
71 return -ENODEV;
72 result &= mask;
73 if (result == done)
74 return 0;
75 udelay(1);
76 usec--;
77 } while (usec > 0);
78 return -ETIMEDOUT;
79}
80
81/*
82 * Disable interrupts and begin the xHCI halting process.
83 */
84void xhci_quiesce(struct xhci_hcd *xhci)
85{
86 u32 halted;
87 u32 cmd;
88 u32 mask;
89
90 mask = ~(XHCI_IRQS);
91 halted = readl(&xhci->op_regs->status) & STS_HALT;
92 if (!halted)
93 mask &= ~CMD_RUN;
94
95 cmd = readl(&xhci->op_regs->command);
96 cmd &= mask;
97 writel(cmd, &xhci->op_regs->command);
98}
99
100/*
101 * Force HC into halt state.
102 *
103 * Disable any IRQs and clear the run/stop bit.
104 * HC will complete any current and actively pipelined transactions, and
105 * should halt within 16 ms of the run/stop bit being cleared.
106 * Read HC Halted bit in the status register to see when the HC is finished.
107 */
108int xhci_halt(struct xhci_hcd *xhci)
109{
110 int ret;
111 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
112 xhci_quiesce(xhci);
113
114 ret = xhci_handshake(&xhci->op_regs->status,
115 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
116 if (ret) {
117 xhci_warn(xhci, "Host halt failed, %d\n", ret);
118 return ret;
119 }
120 xhci->xhc_state |= XHCI_STATE_HALTED;
121 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
122 return ret;
123}
124
125/*
126 * Set the run bit and wait for the host to be running.
127 */
128static int xhci_start(struct xhci_hcd *xhci)
129{
130 u32 temp;
131 int ret;
132
133 temp = readl(&xhci->op_regs->command);
134 temp |= (CMD_RUN);
135 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
136 temp);
137 writel(temp, &xhci->op_regs->command);
138
139 /*
140 * Wait for the HCHalted Status bit to be 0 to indicate the host is
141 * running.
142 */
143 ret = xhci_handshake(&xhci->op_regs->status,
144 STS_HALT, 0, XHCI_MAX_HALT_USEC);
145 if (ret == -ETIMEDOUT)
146 xhci_err(xhci, "Host took too long to start, "
147 "waited %u microseconds.\n",
148 XHCI_MAX_HALT_USEC);
149 if (!ret)
150 /* clear state flags. Including dying, halted or removing */
151 xhci->xhc_state = 0;
152
153 return ret;
154}
155
156/*
157 * Reset a halted HC.
158 *
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
162 */
163int xhci_reset(struct xhci_hcd *xhci)
164{
165 u32 command;
166 u32 state;
167 int ret, i;
168
169 state = readl(&xhci->op_regs->status);
170
171 if (state == ~(u32)0) {
172 xhci_warn(xhci, "Host not accessible, reset failed.\n");
173 return -ENODEV;
174 }
175
176 if ((state & STS_HALT) == 0) {
177 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
178 return 0;
179 }
180
181 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
182 command = readl(&xhci->op_regs->command);
183 command |= CMD_RESET;
184 writel(command, &xhci->op_regs->command);
185
186 /* Existing Intel xHCI controllers require a delay of 1 mS,
187 * after setting the CMD_RESET bit, and before accessing any
188 * HC registers. This allows the HC to complete the
189 * reset operation and be ready for HC register access.
190 * Without this delay, the subsequent HC register access,
191 * may result in a system hang very rarely.
192 */
193 if (xhci->quirks & XHCI_INTEL_HOST)
194 udelay(1000);
195
196 ret = xhci_handshake(&xhci->op_regs->command,
197 CMD_RESET, 0, 10 * 1000 * 1000);
198 if (ret)
199 return ret;
200
201 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
202 "Wait for controller to be ready for doorbell rings");
203 /*
204 * xHCI cannot write to any doorbells or operational registers other
205 * than status until the "Controller Not Ready" flag is cleared.
206 */
207 ret = xhci_handshake(&xhci->op_regs->status,
208 STS_CNR, 0, 10 * 1000 * 1000);
209
210 for (i = 0; i < 2; ++i) {
211 xhci->bus_state[i].port_c_suspend = 0;
212 xhci->bus_state[i].suspended_ports = 0;
213 xhci->bus_state[i].resuming_ports = 0;
214 }
215
216 return ret;
217}
218
219#ifdef CONFIG_PCI
220static int xhci_free_msi(struct xhci_hcd *xhci)
221{
222 int i;
223
224 if (!xhci->msix_entries)
225 return -EINVAL;
226
227 for (i = 0; i < xhci->msix_count; i++)
228 if (xhci->msix_entries[i].vector)
229 free_irq(xhci->msix_entries[i].vector,
230 xhci_to_hcd(xhci));
231 return 0;
232}
233
234/*
235 * Set up MSI
236 */
237static int xhci_setup_msi(struct xhci_hcd *xhci)
238{
239 int ret;
240 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
241
242 ret = pci_enable_msi(pdev);
243 if (ret) {
244 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
245 "failed to allocate MSI entry");
246 return ret;
247 }
248
249 ret = request_irq(pdev->irq, xhci_msi_irq,
250 0, "xhci_hcd", xhci_to_hcd(xhci));
251 if (ret) {
252 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
253 "disable MSI interrupt");
254 pci_disable_msi(pdev);
255 }
256
257 return ret;
258}
259
260/*
261 * Free IRQs
262 * free all IRQs request
263 */
264static void xhci_free_irq(struct xhci_hcd *xhci)
265{
266 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
267 int ret;
268
269 /* return if using legacy interrupt */
270 if (xhci_to_hcd(xhci)->irq > 0)
271 return;
272
273 ret = xhci_free_msi(xhci);
274 if (!ret)
275 return;
276 if (pdev->irq > 0)
277 free_irq(pdev->irq, xhci_to_hcd(xhci));
278
279 return;
280}
281
282/*
283 * Set up MSI-X
284 */
285static int xhci_setup_msix(struct xhci_hcd *xhci)
286{
287 int i, ret = 0;
288 struct usb_hcd *hcd = xhci_to_hcd(xhci);
289 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
290
291 /*
292 * calculate number of msi-x vectors supported.
293 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
294 * with max number of interrupters based on the xhci HCSPARAMS1.
295 * - num_online_cpus: maximum msi-x vectors per CPUs core.
296 * Add additional 1 vector to ensure always available interrupt.
297 */
298 xhci->msix_count = min(num_online_cpus() + 1,
299 HCS_MAX_INTRS(xhci->hcs_params1));
300
301 xhci->msix_entries =
302 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
303 GFP_KERNEL);
304 if (!xhci->msix_entries)
305 return -ENOMEM;
306
307 for (i = 0; i < xhci->msix_count; i++) {
308 xhci->msix_entries[i].entry = i;
309 xhci->msix_entries[i].vector = 0;
310 }
311
312 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
313 if (ret) {
314 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
315 "Failed to enable MSI-X");
316 goto free_entries;
317 }
318
319 for (i = 0; i < xhci->msix_count; i++) {
320 ret = request_irq(xhci->msix_entries[i].vector,
321 xhci_msi_irq,
322 0, "xhci_hcd", xhci_to_hcd(xhci));
323 if (ret)
324 goto disable_msix;
325 }
326
327 hcd->msix_enabled = 1;
328 return ret;
329
330disable_msix:
331 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
332 xhci_free_irq(xhci);
333 pci_disable_msix(pdev);
334free_entries:
335 kfree(xhci->msix_entries);
336 xhci->msix_entries = NULL;
337 return ret;
338}
339
340/* Free any IRQs and disable MSI-X */
341static void xhci_cleanup_msix(struct xhci_hcd *xhci)
342{
343 struct usb_hcd *hcd = xhci_to_hcd(xhci);
344 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
345
346 if (xhci->quirks & XHCI_PLAT)
347 return;
348
349 xhci_free_irq(xhci);
350
351 if (xhci->msix_entries) {
352 pci_disable_msix(pdev);
353 kfree(xhci->msix_entries);
354 xhci->msix_entries = NULL;
355 } else {
356 pci_disable_msi(pdev);
357 }
358
359 hcd->msix_enabled = 0;
360 return;
361}
362
363static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
364{
365 int i;
366
367 if (xhci->msix_entries) {
368 for (i = 0; i < xhci->msix_count; i++)
369 synchronize_irq(xhci->msix_entries[i].vector);
370 }
371}
372
373static int xhci_try_enable_msi(struct usb_hcd *hcd)
374{
375 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
376 struct pci_dev *pdev;
377 int ret;
378
379 /* The xhci platform device has set up IRQs through usb_add_hcd. */
380 if (xhci->quirks & XHCI_PLAT)
381 return 0;
382
383 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
384 /*
385 * Some Fresco Logic host controllers advertise MSI, but fail to
386 * generate interrupts. Don't even try to enable MSI.
387 */
388 if (xhci->quirks & XHCI_BROKEN_MSI)
389 goto legacy_irq;
390
391 /* unregister the legacy interrupt */
392 if (hcd->irq)
393 free_irq(hcd->irq, hcd);
394 hcd->irq = 0;
395
396 ret = xhci_setup_msix(xhci);
397 if (ret)
398 /* fall back to msi*/
399 ret = xhci_setup_msi(xhci);
400
401 if (!ret)
402 /* hcd->irq is 0, we have MSI */
403 return 0;
404
405 if (!pdev->irq) {
406 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
407 return -EINVAL;
408 }
409
410 legacy_irq:
411 if (!strlen(hcd->irq_descr))
412 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
413 hcd->driver->description, hcd->self.busnum);
414
415 /* fall back to legacy interrupt*/
416 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
417 hcd->irq_descr, hcd);
418 if (ret) {
419 xhci_err(xhci, "request interrupt %d failed\n",
420 pdev->irq);
421 return ret;
422 }
423 hcd->irq = pdev->irq;
424 return 0;
425}
426
427#else
428
429static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
430{
431 return 0;
432}
433
434static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
435{
436}
437
438static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
439{
440}
441
442#endif
443
444static void compliance_mode_recovery(unsigned long arg)
445{
446 struct xhci_hcd *xhci;
447 struct usb_hcd *hcd;
448 u32 temp;
449 int i;
450
451 xhci = (struct xhci_hcd *)arg;
452
453 for (i = 0; i < xhci->num_usb3_ports; i++) {
454 temp = readl(xhci->usb3_ports[i]);
455 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
456 /*
457 * Compliance Mode Detected. Letting USB Core
458 * handle the Warm Reset
459 */
460 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
461 "Compliance mode detected->port %d",
462 i + 1);
463 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
464 "Attempting compliance mode recovery");
465 hcd = xhci->shared_hcd;
466
467 if (hcd->state == HC_STATE_SUSPENDED)
468 usb_hcd_resume_root_hub(hcd);
469
470 usb_hcd_poll_rh_status(hcd);
471 }
472 }
473
474 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
475 mod_timer(&xhci->comp_mode_recovery_timer,
476 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
477}
478
479/*
480 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
481 * that causes ports behind that hardware to enter compliance mode sometimes.
482 * The quirk creates a timer that polls every 2 seconds the link state of
483 * each host controller's port and recovers it by issuing a Warm reset
484 * if Compliance mode is detected, otherwise the port will become "dead" (no
485 * device connections or disconnections will be detected anymore). Becasue no
486 * status event is generated when entering compliance mode (per xhci spec),
487 * this quirk is needed on systems that have the failing hardware installed.
488 */
489static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
490{
491 xhci->port_status_u0 = 0;
492 setup_timer(&xhci->comp_mode_recovery_timer,
493 compliance_mode_recovery, (unsigned long)xhci);
494 xhci->comp_mode_recovery_timer.expires = jiffies +
495 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
496
497 add_timer(&xhci->comp_mode_recovery_timer);
498 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
499 "Compliance mode recovery timer initialized");
500}
501
502/*
503 * This function identifies the systems that have installed the SN65LVPE502CP
504 * USB3.0 re-driver and that need the Compliance Mode Quirk.
505 * Systems:
506 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
507 */
508static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
509{
510 const char *dmi_product_name, *dmi_sys_vendor;
511
512 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
513 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
514 if (!dmi_product_name || !dmi_sys_vendor)
515 return false;
516
517 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
518 return false;
519
520 if (strstr(dmi_product_name, "Z420") ||
521 strstr(dmi_product_name, "Z620") ||
522 strstr(dmi_product_name, "Z820") ||
523 strstr(dmi_product_name, "Z1 Workstation"))
524 return true;
525
526 return false;
527}
528
529static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
530{
531 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
532}
533
534
535/*
536 * Initialize memory for HCD and xHC (one-time init).
537 *
538 * Program the PAGESIZE register, initialize the device context array, create
539 * device contexts (?), set up a command ring segment (or two?), create event
540 * ring (one for now).
541 */
542int xhci_init(struct usb_hcd *hcd)
543{
544 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
545 int retval = 0;
546
547 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
548 spin_lock_init(&xhci->lock);
549 if (xhci->hci_version == 0x95 && link_quirk) {
550 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
551 "QUIRK: Not clearing Link TRB chain bits.");
552 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
553 } else {
554 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
555 "xHCI doesn't need link TRB QUIRK");
556 }
557 retval = xhci_mem_init(xhci, GFP_KERNEL);
558 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
559
560 /* Initializing Compliance Mode Recovery Data If Needed */
561 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
562 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
563 compliance_mode_recovery_timer_init(xhci);
564 }
565
566 return retval;
567}
568
569/*-------------------------------------------------------------------------*/
570
571
572static int xhci_run_finished(struct xhci_hcd *xhci)
573{
574 if (xhci_start(xhci)) {
575 xhci_halt(xhci);
576 return -ENODEV;
577 }
578 xhci->shared_hcd->state = HC_STATE_RUNNING;
579 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
580
581 if (xhci->quirks & XHCI_NEC_HOST)
582 xhci_ring_cmd_db(xhci);
583
584 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
585 "Finished xhci_run for USB3 roothub");
586 return 0;
587}
588
589/*
590 * Start the HC after it was halted.
591 *
592 * This function is called by the USB core when the HC driver is added.
593 * Its opposite is xhci_stop().
594 *
595 * xhci_init() must be called once before this function can be called.
596 * Reset the HC, enable device slot contexts, program DCBAAP, and
597 * set command ring pointer and event ring pointer.
598 *
599 * Setup MSI-X vectors and enable interrupts.
600 */
601int xhci_run(struct usb_hcd *hcd)
602{
603 u32 temp;
604 u64 temp_64;
605 int ret;
606 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
607
608 /* Start the xHCI host controller running only after the USB 2.0 roothub
609 * is setup.
610 */
611
612 hcd->uses_new_polling = 1;
613 if (!usb_hcd_is_primary_hcd(hcd))
614 return xhci_run_finished(xhci);
615
616 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
617
618 ret = xhci_try_enable_msi(hcd);
619 if (ret)
620 return ret;
621
622 xhci_dbg(xhci, "Command ring memory map follows:\n");
623 xhci_debug_ring(xhci, xhci->cmd_ring);
624 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
625 xhci_dbg_cmd_ptrs(xhci);
626
627 xhci_dbg(xhci, "ERST memory map follows:\n");
628 xhci_dbg_erst(xhci, &xhci->erst);
629 xhci_dbg(xhci, "Event ring:\n");
630 xhci_debug_ring(xhci, xhci->event_ring);
631 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
632 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
633 temp_64 &= ~ERST_PTR_MASK;
634 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
635 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
636
637 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
638 "// Set the interrupt modulation register");
639 temp = readl(&xhci->ir_set->irq_control);
640 temp &= ~ER_IRQ_INTERVAL_MASK;
641 /*
642 * the increment interval is 8 times as much as that defined
643 * in xHCI spec on MTK's controller
644 */
645 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
646 writel(temp, &xhci->ir_set->irq_control);
647
648 /* Set the HCD state before we enable the irqs */
649 temp = readl(&xhci->op_regs->command);
650 temp |= (CMD_EIE);
651 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
652 "// Enable interrupts, cmd = 0x%x.", temp);
653 writel(temp, &xhci->op_regs->command);
654
655 temp = readl(&xhci->ir_set->irq_pending);
656 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
657 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
658 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
659 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
660 xhci_print_ir_set(xhci, 0);
661
662 if (xhci->quirks & XHCI_NEC_HOST) {
663 struct xhci_command *command;
664 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
665 if (!command)
666 return -ENOMEM;
667 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
668 TRB_TYPE(TRB_NEC_GET_FW));
669 }
670 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
671 "Finished xhci_run for USB2 roothub");
672 return 0;
673}
674EXPORT_SYMBOL_GPL(xhci_run);
675
676/*
677 * Stop xHCI driver.
678 *
679 * This function is called by the USB core when the HC driver is removed.
680 * Its opposite is xhci_run().
681 *
682 * Disable device contexts, disable IRQs, and quiesce the HC.
683 * Reset the HC, finish any completed transactions, and cleanup memory.
684 */
685void xhci_stop(struct usb_hcd *hcd)
686{
687 u32 temp;
688 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
689
690 mutex_lock(&xhci->mutex);
691
692 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
693 spin_lock_irq(&xhci->lock);
694
695 xhci->xhc_state |= XHCI_STATE_HALTED;
696 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
697 xhci_halt(xhci);
698 xhci_reset(xhci);
699 spin_unlock_irq(&xhci->lock);
700 }
701
702 if (!usb_hcd_is_primary_hcd(hcd)) {
703 mutex_unlock(&xhci->mutex);
704 return;
705 }
706
707 xhci_cleanup_msix(xhci);
708
709 /* Deleting Compliance Mode Recovery Timer */
710 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
711 (!(xhci_all_ports_seen_u0(xhci)))) {
712 del_timer_sync(&xhci->comp_mode_recovery_timer);
713 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
714 "%s: compliance mode recovery timer deleted",
715 __func__);
716 }
717
718 if (xhci->quirks & XHCI_AMD_PLL_FIX)
719 usb_amd_dev_put();
720
721 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
722 "// Disabling event ring interrupts");
723 temp = readl(&xhci->op_regs->status);
724 writel(temp & ~STS_EINT, &xhci->op_regs->status);
725 temp = readl(&xhci->ir_set->irq_pending);
726 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
727 xhci_print_ir_set(xhci, 0);
728
729 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
730 xhci_mem_cleanup(xhci);
731 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
732 "xhci_stop completed - status = %x",
733 readl(&xhci->op_regs->status));
734 mutex_unlock(&xhci->mutex);
735}
736
737/*
738 * Shutdown HC (not bus-specific)
739 *
740 * This is called when the machine is rebooting or halting. We assume that the
741 * machine will be powered off, and the HC's internal state will be reset.
742 * Don't bother to free memory.
743 *
744 * This will only ever be called with the main usb_hcd (the USB3 roothub).
745 */
746void xhci_shutdown(struct usb_hcd *hcd)
747{
748 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
749
750 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
751 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
752
753 spin_lock_irq(&xhci->lock);
754 xhci_halt(xhci);
755 /* Workaround for spurious wakeups at shutdown with HSW */
756 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
757 xhci_reset(xhci);
758 spin_unlock_irq(&xhci->lock);
759
760 xhci_cleanup_msix(xhci);
761
762 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
763 "xhci_shutdown completed - status = %x",
764 readl(&xhci->op_regs->status));
765
766 /* Yet another workaround for spurious wakeups at shutdown with HSW */
767 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
768 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
769}
770
771#ifdef CONFIG_PM
772static void xhci_save_registers(struct xhci_hcd *xhci)
773{
774 xhci->s3.command = readl(&xhci->op_regs->command);
775 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
776 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
777 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
778 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
779 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
780 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
781 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
782 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
783}
784
785static void xhci_restore_registers(struct xhci_hcd *xhci)
786{
787 writel(xhci->s3.command, &xhci->op_regs->command);
788 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
789 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
790 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
791 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
792 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
793 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
794 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
795 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
796}
797
798static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
799{
800 u64 val_64;
801
802 /* step 2: initialize command ring buffer */
803 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
804 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
805 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
806 xhci->cmd_ring->dequeue) &
807 (u64) ~CMD_RING_RSVD_BITS) |
808 xhci->cmd_ring->cycle_state;
809 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
810 "// Setting command ring address to 0x%llx",
811 (long unsigned long) val_64);
812 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
813}
814
815/*
816 * The whole command ring must be cleared to zero when we suspend the host.
817 *
818 * The host doesn't save the command ring pointer in the suspend well, so we
819 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
820 * aligned, because of the reserved bits in the command ring dequeue pointer
821 * register. Therefore, we can't just set the dequeue pointer back in the
822 * middle of the ring (TRBs are 16-byte aligned).
823 */
824static void xhci_clear_command_ring(struct xhci_hcd *xhci)
825{
826 struct xhci_ring *ring;
827 struct xhci_segment *seg;
828
829 ring = xhci->cmd_ring;
830 seg = ring->deq_seg;
831 do {
832 memset(seg->trbs, 0,
833 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
834 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
835 cpu_to_le32(~TRB_CYCLE);
836 seg = seg->next;
837 } while (seg != ring->deq_seg);
838
839 /* Reset the software enqueue and dequeue pointers */
840 ring->deq_seg = ring->first_seg;
841 ring->dequeue = ring->first_seg->trbs;
842 ring->enq_seg = ring->deq_seg;
843 ring->enqueue = ring->dequeue;
844
845 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
846 /*
847 * Ring is now zeroed, so the HW should look for change of ownership
848 * when the cycle bit is set to 1.
849 */
850 ring->cycle_state = 1;
851
852 /*
853 * Reset the hardware dequeue pointer.
854 * Yes, this will need to be re-written after resume, but we're paranoid
855 * and want to make sure the hardware doesn't access bogus memory
856 * because, say, the BIOS or an SMI started the host without changing
857 * the command ring pointers.
858 */
859 xhci_set_cmd_ring_deq(xhci);
860}
861
862static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
863{
864 int port_index;
865 __le32 __iomem **port_array;
866 unsigned long flags;
867 u32 t1, t2;
868
869 spin_lock_irqsave(&xhci->lock, flags);
870
871 /* disble usb3 ports Wake bits*/
872 port_index = xhci->num_usb3_ports;
873 port_array = xhci->usb3_ports;
874 while (port_index--) {
875 t1 = readl(port_array[port_index]);
876 t1 = xhci_port_state_to_neutral(t1);
877 t2 = t1 & ~PORT_WAKE_BITS;
878 if (t1 != t2)
879 writel(t2, port_array[port_index]);
880 }
881
882 /* disble usb2 ports Wake bits*/
883 port_index = xhci->num_usb2_ports;
884 port_array = xhci->usb2_ports;
885 while (port_index--) {
886 t1 = readl(port_array[port_index]);
887 t1 = xhci_port_state_to_neutral(t1);
888 t2 = t1 & ~PORT_WAKE_BITS;
889 if (t1 != t2)
890 writel(t2, port_array[port_index]);
891 }
892
893 spin_unlock_irqrestore(&xhci->lock, flags);
894}
895
896/*
897 * Stop HC (not bus-specific)
898 *
899 * This is called when the machine transition into S3/S4 mode.
900 *
901 */
902int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
903{
904 int rc = 0;
905 unsigned int delay = XHCI_MAX_HALT_USEC;
906 struct usb_hcd *hcd = xhci_to_hcd(xhci);
907 u32 command;
908
909 if (!hcd->state)
910 return 0;
911
912 if (hcd->state != HC_STATE_SUSPENDED ||
913 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
914 return -EINVAL;
915
916 /* Clear root port wake on bits if wakeup not allowed. */
917 if (!do_wakeup)
918 xhci_disable_port_wake_on_bits(xhci);
919
920 /* Don't poll the roothubs on bus suspend. */
921 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
922 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
923 del_timer_sync(&hcd->rh_timer);
924 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
925 del_timer_sync(&xhci->shared_hcd->rh_timer);
926
927 spin_lock_irq(&xhci->lock);
928 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
929 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
930 /* step 1: stop endpoint */
931 /* skipped assuming that port suspend has done */
932
933 /* step 2: clear Run/Stop bit */
934 command = readl(&xhci->op_regs->command);
935 command &= ~CMD_RUN;
936 writel(command, &xhci->op_regs->command);
937
938 /* Some chips from Fresco Logic need an extraordinary delay */
939 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
940
941 if (xhci_handshake(&xhci->op_regs->status,
942 STS_HALT, STS_HALT, delay)) {
943 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
944 spin_unlock_irq(&xhci->lock);
945 return -ETIMEDOUT;
946 }
947 xhci_clear_command_ring(xhci);
948
949 /* step 3: save registers */
950 xhci_save_registers(xhci);
951
952 /* step 4: set CSS flag */
953 command = readl(&xhci->op_regs->command);
954 command |= CMD_CSS;
955 writel(command, &xhci->op_regs->command);
956 if (xhci_handshake(&xhci->op_regs->status,
957 STS_SAVE, 0, 10 * 1000)) {
958 xhci_warn(xhci, "WARN: xHC save state timeout\n");
959 spin_unlock_irq(&xhci->lock);
960 return -ETIMEDOUT;
961 }
962 spin_unlock_irq(&xhci->lock);
963
964 /*
965 * Deleting Compliance Mode Recovery Timer because the xHCI Host
966 * is about to be suspended.
967 */
968 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
969 (!(xhci_all_ports_seen_u0(xhci)))) {
970 del_timer_sync(&xhci->comp_mode_recovery_timer);
971 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
972 "%s: compliance mode recovery timer deleted",
973 __func__);
974 }
975
976 /* step 5: remove core well power */
977 /* synchronize irq when using MSI-X */
978 xhci_msix_sync_irqs(xhci);
979
980 return rc;
981}
982EXPORT_SYMBOL_GPL(xhci_suspend);
983
984/*
985 * start xHC (not bus-specific)
986 *
987 * This is called when the machine transition from S3/S4 mode.
988 *
989 */
990int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
991{
992 u32 command, temp = 0, status;
993 struct usb_hcd *hcd = xhci_to_hcd(xhci);
994 struct usb_hcd *secondary_hcd;
995 int retval = 0;
996 bool comp_timer_running = false;
997
998 if (!hcd->state)
999 return 0;
1000
1001 /* Wait a bit if either of the roothubs need to settle from the
1002 * transition into bus suspend.
1003 */
1004 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1005 time_before(jiffies,
1006 xhci->bus_state[1].next_statechange))
1007 msleep(100);
1008
1009 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1010 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1011
1012 spin_lock_irq(&xhci->lock);
1013 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1014 hibernated = true;
1015
1016 if (!hibernated) {
1017 /* step 1: restore register */
1018 xhci_restore_registers(xhci);
1019 /* step 2: initialize command ring buffer */
1020 xhci_set_cmd_ring_deq(xhci);
1021 /* step 3: restore state and start state*/
1022 /* step 3: set CRS flag */
1023 command = readl(&xhci->op_regs->command);
1024 command |= CMD_CRS;
1025 writel(command, &xhci->op_regs->command);
1026 if (xhci_handshake(&xhci->op_regs->status,
1027 STS_RESTORE, 0, 10 * 1000)) {
1028 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1029 spin_unlock_irq(&xhci->lock);
1030 return -ETIMEDOUT;
1031 }
1032 temp = readl(&xhci->op_regs->status);
1033 }
1034
1035 /* If restore operation fails, re-initialize the HC during resume */
1036 if ((temp & STS_SRE) || hibernated) {
1037
1038 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1039 !(xhci_all_ports_seen_u0(xhci))) {
1040 del_timer_sync(&xhci->comp_mode_recovery_timer);
1041 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1042 "Compliance Mode Recovery Timer deleted!");
1043 }
1044
1045 /* Let the USB core know _both_ roothubs lost power. */
1046 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1047 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1048
1049 xhci_dbg(xhci, "Stop HCD\n");
1050 xhci_halt(xhci);
1051 xhci_reset(xhci);
1052 spin_unlock_irq(&xhci->lock);
1053 xhci_cleanup_msix(xhci);
1054
1055 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1056 temp = readl(&xhci->op_regs->status);
1057 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1058 temp = readl(&xhci->ir_set->irq_pending);
1059 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1060 xhci_print_ir_set(xhci, 0);
1061
1062 xhci_dbg(xhci, "cleaning up memory\n");
1063 xhci_mem_cleanup(xhci);
1064 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1065 readl(&xhci->op_regs->status));
1066
1067 /* USB core calls the PCI reinit and start functions twice:
1068 * first with the primary HCD, and then with the secondary HCD.
1069 * If we don't do the same, the host will never be started.
1070 */
1071 if (!usb_hcd_is_primary_hcd(hcd))
1072 secondary_hcd = hcd;
1073 else
1074 secondary_hcd = xhci->shared_hcd;
1075
1076 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1077 retval = xhci_init(hcd->primary_hcd);
1078 if (retval)
1079 return retval;
1080 comp_timer_running = true;
1081
1082 xhci_dbg(xhci, "Start the primary HCD\n");
1083 retval = xhci_run(hcd->primary_hcd);
1084 if (!retval) {
1085 xhci_dbg(xhci, "Start the secondary HCD\n");
1086 retval = xhci_run(secondary_hcd);
1087 }
1088 hcd->state = HC_STATE_SUSPENDED;
1089 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1090 goto done;
1091 }
1092
1093 /* step 4: set Run/Stop bit */
1094 command = readl(&xhci->op_regs->command);
1095 command |= CMD_RUN;
1096 writel(command, &xhci->op_regs->command);
1097 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1098 0, 250 * 1000);
1099
1100 /* step 5: walk topology and initialize portsc,
1101 * portpmsc and portli
1102 */
1103 /* this is done in bus_resume */
1104
1105 /* step 6: restart each of the previously
1106 * Running endpoints by ringing their doorbells
1107 */
1108
1109 spin_unlock_irq(&xhci->lock);
1110
1111 done:
1112 if (retval == 0) {
1113 /* Resume root hubs only when have pending events. */
1114 status = readl(&xhci->op_regs->status);
1115 if (status & STS_EINT) {
1116 usb_hcd_resume_root_hub(xhci->shared_hcd);
1117 usb_hcd_resume_root_hub(hcd);
1118 }
1119 }
1120
1121 /*
1122 * If system is subject to the Quirk, Compliance Mode Timer needs to
1123 * be re-initialized Always after a system resume. Ports are subject
1124 * to suffer the Compliance Mode issue again. It doesn't matter if
1125 * ports have entered previously to U0 before system's suspension.
1126 */
1127 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1128 compliance_mode_recovery_timer_init(xhci);
1129
1130 /* Re-enable port polling. */
1131 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1132 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1133 usb_hcd_poll_rh_status(xhci->shared_hcd);
1134 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1135 usb_hcd_poll_rh_status(hcd);
1136
1137 return retval;
1138}
1139EXPORT_SYMBOL_GPL(xhci_resume);
1140#endif /* CONFIG_PM */
1141
1142/*-------------------------------------------------------------------------*/
1143
1144/**
1145 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1146 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1147 * value to right shift 1 for the bitmask.
1148 *
1149 * Index = (epnum * 2) + direction - 1,
1150 * where direction = 0 for OUT, 1 for IN.
1151 * For control endpoints, the IN index is used (OUT index is unused), so
1152 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1153 */
1154unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1155{
1156 unsigned int index;
1157 if (usb_endpoint_xfer_control(desc))
1158 index = (unsigned int) (usb_endpoint_num(desc)*2);
1159 else
1160 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1161 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1162 return index;
1163}
1164
1165/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1166 * address from the XHCI endpoint index.
1167 */
1168unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1169{
1170 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1171 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1172 return direction | number;
1173}
1174
1175/* Find the flag for this endpoint (for use in the control context). Use the
1176 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1177 * bit 1, etc.
1178 */
1179unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1180{
1181 return 1 << (xhci_get_endpoint_index(desc) + 1);
1182}
1183
1184/* Find the flag for this endpoint (for use in the control context). Use the
1185 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1186 * bit 1, etc.
1187 */
1188unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1189{
1190 return 1 << (ep_index + 1);
1191}
1192
1193/* Compute the last valid endpoint context index. Basically, this is the
1194 * endpoint index plus one. For slot contexts with more than valid endpoint,
1195 * we find the most significant bit set in the added contexts flags.
1196 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1197 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1198 */
1199unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1200{
1201 return fls(added_ctxs) - 1;
1202}
1203
1204/* Returns 1 if the arguments are OK;
1205 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1206 */
1207static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1208 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1209 const char *func) {
1210 struct xhci_hcd *xhci;
1211 struct xhci_virt_device *virt_dev;
1212
1213 if (!hcd || (check_ep && !ep) || !udev) {
1214 pr_debug("xHCI %s called with invalid args\n", func);
1215 return -EINVAL;
1216 }
1217 if (!udev->parent) {
1218 pr_debug("xHCI %s called for root hub\n", func);
1219 return 0;
1220 }
1221
1222 xhci = hcd_to_xhci(hcd);
1223 if (check_virt_dev) {
1224 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1225 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1226 func);
1227 return -EINVAL;
1228 }
1229
1230 virt_dev = xhci->devs[udev->slot_id];
1231 if (virt_dev->udev != udev) {
1232 xhci_dbg(xhci, "xHCI %s called with udev and "
1233 "virt_dev does not match\n", func);
1234 return -EINVAL;
1235 }
1236 }
1237
1238 if (xhci->xhc_state & XHCI_STATE_HALTED)
1239 return -ENODEV;
1240
1241 return 1;
1242}
1243
1244static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1245 struct usb_device *udev, struct xhci_command *command,
1246 bool ctx_change, bool must_succeed);
1247
1248/*
1249 * Full speed devices may have a max packet size greater than 8 bytes, but the
1250 * USB core doesn't know that until it reads the first 8 bytes of the
1251 * descriptor. If the usb_device's max packet size changes after that point,
1252 * we need to issue an evaluate context command and wait on it.
1253 */
1254static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1255 unsigned int ep_index, struct urb *urb)
1256{
1257 struct xhci_container_ctx *out_ctx;
1258 struct xhci_input_control_ctx *ctrl_ctx;
1259 struct xhci_ep_ctx *ep_ctx;
1260 struct xhci_command *command;
1261 int max_packet_size;
1262 int hw_max_packet_size;
1263 int ret = 0;
1264
1265 out_ctx = xhci->devs[slot_id]->out_ctx;
1266 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1267 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1268 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1269 if (hw_max_packet_size != max_packet_size) {
1270 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1271 "Max Packet Size for ep 0 changed.");
1272 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1273 "Max packet size in usb_device = %d",
1274 max_packet_size);
1275 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1276 "Max packet size in xHCI HW = %d",
1277 hw_max_packet_size);
1278 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1279 "Issuing evaluate context command.");
1280
1281 /* Set up the input context flags for the command */
1282 /* FIXME: This won't work if a non-default control endpoint
1283 * changes max packet sizes.
1284 */
1285
1286 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1287 if (!command)
1288 return -ENOMEM;
1289
1290 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1291 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1292 if (!ctrl_ctx) {
1293 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1294 __func__);
1295 ret = -ENOMEM;
1296 goto command_cleanup;
1297 }
1298 /* Set up the modified control endpoint 0 */
1299 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1300 xhci->devs[slot_id]->out_ctx, ep_index);
1301
1302 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1303 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1304 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1305
1306 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1307 ctrl_ctx->drop_flags = 0;
1308
1309 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1310 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1311 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1312 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1313
1314 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1315 true, false);
1316
1317 /* Clean up the input context for later use by bandwidth
1318 * functions.
1319 */
1320 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1321command_cleanup:
1322 kfree(command->completion);
1323 kfree(command);
1324 }
1325 return ret;
1326}
1327
1328/*
1329 * non-error returns are a promise to giveback() the urb later
1330 * we drop ownership so next owner (or urb unlink) can get it
1331 */
1332int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1333{
1334 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1335 struct xhci_td *buffer;
1336 unsigned long flags;
1337 int ret = 0;
1338 unsigned int slot_id, ep_index;
1339 struct urb_priv *urb_priv;
1340 int size, i;
1341
1342 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1343 true, true, __func__) <= 0)
1344 return -EINVAL;
1345
1346 slot_id = urb->dev->slot_id;
1347 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1348
1349 if (!HCD_HW_ACCESSIBLE(hcd)) {
1350 if (!in_interrupt())
1351 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1352 ret = -ESHUTDOWN;
1353 goto exit;
1354 }
1355
1356 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1357 size = urb->number_of_packets;
1358 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1359 urb->transfer_buffer_length > 0 &&
1360 urb->transfer_flags & URB_ZERO_PACKET &&
1361 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1362 size = 2;
1363 else
1364 size = 1;
1365
1366 urb_priv = kzalloc(sizeof(struct urb_priv) +
1367 size * sizeof(struct xhci_td *), mem_flags);
1368 if (!urb_priv)
1369 return -ENOMEM;
1370
1371 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1372 if (!buffer) {
1373 kfree(urb_priv);
1374 return -ENOMEM;
1375 }
1376
1377 for (i = 0; i < size; i++) {
1378 urb_priv->td[i] = buffer;
1379 buffer++;
1380 }
1381
1382 urb_priv->length = size;
1383 urb_priv->td_cnt = 0;
1384 urb->hcpriv = urb_priv;
1385
1386 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1387 /* Check to see if the max packet size for the default control
1388 * endpoint changed during FS device enumeration
1389 */
1390 if (urb->dev->speed == USB_SPEED_FULL) {
1391 ret = xhci_check_maxpacket(xhci, slot_id,
1392 ep_index, urb);
1393 if (ret < 0) {
1394 xhci_urb_free_priv(urb_priv);
1395 urb->hcpriv = NULL;
1396 return ret;
1397 }
1398 }
1399
1400 /* We have a spinlock and interrupts disabled, so we must pass
1401 * atomic context to this function, which may allocate memory.
1402 */
1403 spin_lock_irqsave(&xhci->lock, flags);
1404 if (xhci->xhc_state & XHCI_STATE_DYING)
1405 goto dying;
1406 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1407 slot_id, ep_index);
1408 if (ret)
1409 goto free_priv;
1410 spin_unlock_irqrestore(&xhci->lock, flags);
1411 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1412 spin_lock_irqsave(&xhci->lock, flags);
1413 if (xhci->xhc_state & XHCI_STATE_DYING)
1414 goto dying;
1415 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1416 EP_GETTING_STREAMS) {
1417 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1418 "is transitioning to using streams.\n");
1419 ret = -EINVAL;
1420 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1421 EP_GETTING_NO_STREAMS) {
1422 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1423 "is transitioning to "
1424 "not having streams.\n");
1425 ret = -EINVAL;
1426 } else {
1427 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1428 slot_id, ep_index);
1429 }
1430 if (ret)
1431 goto free_priv;
1432 spin_unlock_irqrestore(&xhci->lock, flags);
1433 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1434 spin_lock_irqsave(&xhci->lock, flags);
1435 if (xhci->xhc_state & XHCI_STATE_DYING)
1436 goto dying;
1437 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1438 slot_id, ep_index);
1439 if (ret)
1440 goto free_priv;
1441 spin_unlock_irqrestore(&xhci->lock, flags);
1442 } else {
1443 spin_lock_irqsave(&xhci->lock, flags);
1444 if (xhci->xhc_state & XHCI_STATE_DYING)
1445 goto dying;
1446 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1447 slot_id, ep_index);
1448 if (ret)
1449 goto free_priv;
1450 spin_unlock_irqrestore(&xhci->lock, flags);
1451 }
1452exit:
1453 return ret;
1454dying:
1455 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1456 "non-responsive xHCI host.\n",
1457 urb->ep->desc.bEndpointAddress, urb);
1458 ret = -ESHUTDOWN;
1459free_priv:
1460 xhci_urb_free_priv(urb_priv);
1461 urb->hcpriv = NULL;
1462 spin_unlock_irqrestore(&xhci->lock, flags);
1463 return ret;
1464}
1465
1466/*
1467 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1468 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1469 * should pick up where it left off in the TD, unless a Set Transfer Ring
1470 * Dequeue Pointer is issued.
1471 *
1472 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1473 * the ring. Since the ring is a contiguous structure, they can't be physically
1474 * removed. Instead, there are two options:
1475 *
1476 * 1) If the HC is in the middle of processing the URB to be canceled, we
1477 * simply move the ring's dequeue pointer past those TRBs using the Set
1478 * Transfer Ring Dequeue Pointer command. This will be the common case,
1479 * when drivers timeout on the last submitted URB and attempt to cancel.
1480 *
1481 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1482 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1483 * HC will need to invalidate the any TRBs it has cached after the stop
1484 * endpoint command, as noted in the xHCI 0.95 errata.
1485 *
1486 * 3) The TD may have completed by the time the Stop Endpoint Command
1487 * completes, so software needs to handle that case too.
1488 *
1489 * This function should protect against the TD enqueueing code ringing the
1490 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1491 * It also needs to account for multiple cancellations on happening at the same
1492 * time for the same endpoint.
1493 *
1494 * Note that this function can be called in any context, or so says
1495 * usb_hcd_unlink_urb()
1496 */
1497int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1498{
1499 unsigned long flags;
1500 int ret, i;
1501 u32 temp;
1502 struct xhci_hcd *xhci;
1503 struct urb_priv *urb_priv;
1504 struct xhci_td *td;
1505 unsigned int ep_index;
1506 struct xhci_ring *ep_ring;
1507 struct xhci_virt_ep *ep;
1508 struct xhci_command *command;
1509
1510 xhci = hcd_to_xhci(hcd);
1511 spin_lock_irqsave(&xhci->lock, flags);
1512 /* Make sure the URB hasn't completed or been unlinked already */
1513 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1514 if (ret || !urb->hcpriv)
1515 goto done;
1516 temp = readl(&xhci->op_regs->status);
1517 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1518 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1519 "HW died, freeing TD.");
1520 urb_priv = urb->hcpriv;
1521 for (i = urb_priv->td_cnt;
1522 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1523 i++) {
1524 td = urb_priv->td[i];
1525 if (!list_empty(&td->td_list))
1526 list_del_init(&td->td_list);
1527 if (!list_empty(&td->cancelled_td_list))
1528 list_del_init(&td->cancelled_td_list);
1529 }
1530
1531 usb_hcd_unlink_urb_from_ep(hcd, urb);
1532 spin_unlock_irqrestore(&xhci->lock, flags);
1533 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1534 xhci_urb_free_priv(urb_priv);
1535 return ret;
1536 }
1537
1538 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1539 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1540 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1541 if (!ep_ring) {
1542 ret = -EINVAL;
1543 goto done;
1544 }
1545
1546 urb_priv = urb->hcpriv;
1547 i = urb_priv->td_cnt;
1548 if (i < urb_priv->length)
1549 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1550 "Cancel URB %p, dev %s, ep 0x%x, "
1551 "starting at offset 0x%llx",
1552 urb, urb->dev->devpath,
1553 urb->ep->desc.bEndpointAddress,
1554 (unsigned long long) xhci_trb_virt_to_dma(
1555 urb_priv->td[i]->start_seg,
1556 urb_priv->td[i]->first_trb));
1557
1558 for (; i < urb_priv->length; i++) {
1559 td = urb_priv->td[i];
1560 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1561 }
1562
1563 /* Queue a stop endpoint command, but only if this is
1564 * the first cancellation to be handled.
1565 */
1566 if (!(ep->ep_state & EP_HALT_PENDING)) {
1567 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1568 if (!command) {
1569 ret = -ENOMEM;
1570 goto done;
1571 }
1572 ep->ep_state |= EP_HALT_PENDING;
1573 ep->stop_cmds_pending++;
1574 ep->stop_cmd_timer.expires = jiffies +
1575 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1576 add_timer(&ep->stop_cmd_timer);
1577 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1578 ep_index, 0);
1579 xhci_ring_cmd_db(xhci);
1580 }
1581done:
1582 spin_unlock_irqrestore(&xhci->lock, flags);
1583 return ret;
1584}
1585
1586/* Drop an endpoint from a new bandwidth configuration for this device.
1587 * Only one call to this function is allowed per endpoint before
1588 * check_bandwidth() or reset_bandwidth() must be called.
1589 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1590 * add the endpoint to the schedule with possibly new parameters denoted by a
1591 * different endpoint descriptor in usb_host_endpoint.
1592 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1593 * not allowed.
1594 *
1595 * The USB core will not allow URBs to be queued to an endpoint that is being
1596 * disabled, so there's no need for mutual exclusion to protect
1597 * the xhci->devs[slot_id] structure.
1598 */
1599int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1600 struct usb_host_endpoint *ep)
1601{
1602 struct xhci_hcd *xhci;
1603 struct xhci_container_ctx *in_ctx, *out_ctx;
1604 struct xhci_input_control_ctx *ctrl_ctx;
1605 unsigned int ep_index;
1606 struct xhci_ep_ctx *ep_ctx;
1607 u32 drop_flag;
1608 u32 new_add_flags, new_drop_flags;
1609 int ret;
1610
1611 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1612 if (ret <= 0)
1613 return ret;
1614 xhci = hcd_to_xhci(hcd);
1615 if (xhci->xhc_state & XHCI_STATE_DYING)
1616 return -ENODEV;
1617
1618 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1619 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1620 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1621 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1622 __func__, drop_flag);
1623 return 0;
1624 }
1625
1626 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1627 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1628 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1629 if (!ctrl_ctx) {
1630 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1631 __func__);
1632 return 0;
1633 }
1634
1635 ep_index = xhci_get_endpoint_index(&ep->desc);
1636 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1637 /* If the HC already knows the endpoint is disabled,
1638 * or the HCD has noted it is disabled, ignore this request
1639 */
1640 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1641 le32_to_cpu(ctrl_ctx->drop_flags) &
1642 xhci_get_endpoint_flag(&ep->desc)) {
1643 /* Do not warn when called after a usb_device_reset */
1644 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1645 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1646 __func__, ep);
1647 return 0;
1648 }
1649
1650 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1651 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1652
1653 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1654 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1655
1656 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1657
1658 if (xhci->quirks & XHCI_MTK_HOST)
1659 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1660
1661 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1662 (unsigned int) ep->desc.bEndpointAddress,
1663 udev->slot_id,
1664 (unsigned int) new_drop_flags,
1665 (unsigned int) new_add_flags);
1666 return 0;
1667}
1668
1669/* Add an endpoint to a new possible bandwidth configuration for this device.
1670 * Only one call to this function is allowed per endpoint before
1671 * check_bandwidth() or reset_bandwidth() must be called.
1672 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1673 * add the endpoint to the schedule with possibly new parameters denoted by a
1674 * different endpoint descriptor in usb_host_endpoint.
1675 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1676 * not allowed.
1677 *
1678 * The USB core will not allow URBs to be queued to an endpoint until the
1679 * configuration or alt setting is installed in the device, so there's no need
1680 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1681 */
1682int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1683 struct usb_host_endpoint *ep)
1684{
1685 struct xhci_hcd *xhci;
1686 struct xhci_container_ctx *in_ctx;
1687 unsigned int ep_index;
1688 struct xhci_input_control_ctx *ctrl_ctx;
1689 u32 added_ctxs;
1690 u32 new_add_flags, new_drop_flags;
1691 struct xhci_virt_device *virt_dev;
1692 int ret = 0;
1693
1694 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1695 if (ret <= 0) {
1696 /* So we won't queue a reset ep command for a root hub */
1697 ep->hcpriv = NULL;
1698 return ret;
1699 }
1700 xhci = hcd_to_xhci(hcd);
1701 if (xhci->xhc_state & XHCI_STATE_DYING)
1702 return -ENODEV;
1703
1704 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1705 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1706 /* FIXME when we have to issue an evaluate endpoint command to
1707 * deal with ep0 max packet size changing once we get the
1708 * descriptors
1709 */
1710 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1711 __func__, added_ctxs);
1712 return 0;
1713 }
1714
1715 virt_dev = xhci->devs[udev->slot_id];
1716 in_ctx = virt_dev->in_ctx;
1717 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1718 if (!ctrl_ctx) {
1719 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1720 __func__);
1721 return 0;
1722 }
1723
1724 ep_index = xhci_get_endpoint_index(&ep->desc);
1725 /* If this endpoint is already in use, and the upper layers are trying
1726 * to add it again without dropping it, reject the addition.
1727 */
1728 if (virt_dev->eps[ep_index].ring &&
1729 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1730 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1731 "without dropping it.\n",
1732 (unsigned int) ep->desc.bEndpointAddress);
1733 return -EINVAL;
1734 }
1735
1736 /* If the HCD has already noted the endpoint is enabled,
1737 * ignore this request.
1738 */
1739 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1740 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1741 __func__, ep);
1742 return 0;
1743 }
1744
1745 /*
1746 * Configuration and alternate setting changes must be done in
1747 * process context, not interrupt context (or so documenation
1748 * for usb_set_interface() and usb_set_configuration() claim).
1749 */
1750 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1751 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1752 __func__, ep->desc.bEndpointAddress);
1753 return -ENOMEM;
1754 }
1755
1756 if (xhci->quirks & XHCI_MTK_HOST) {
1757 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1758 if (ret < 0) {
1759 xhci_free_or_cache_endpoint_ring(xhci,
1760 virt_dev, ep_index);
1761 return ret;
1762 }
1763 }
1764
1765 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1766 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1767
1768 /* If xhci_endpoint_disable() was called for this endpoint, but the
1769 * xHC hasn't been notified yet through the check_bandwidth() call,
1770 * this re-adds a new state for the endpoint from the new endpoint
1771 * descriptors. We must drop and re-add this endpoint, so we leave the
1772 * drop flags alone.
1773 */
1774 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1775
1776 /* Store the usb_device pointer for later use */
1777 ep->hcpriv = udev;
1778
1779 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1780 (unsigned int) ep->desc.bEndpointAddress,
1781 udev->slot_id,
1782 (unsigned int) new_drop_flags,
1783 (unsigned int) new_add_flags);
1784 return 0;
1785}
1786
1787static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1788{
1789 struct xhci_input_control_ctx *ctrl_ctx;
1790 struct xhci_ep_ctx *ep_ctx;
1791 struct xhci_slot_ctx *slot_ctx;
1792 int i;
1793
1794 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1795 if (!ctrl_ctx) {
1796 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1797 __func__);
1798 return;
1799 }
1800
1801 /* When a device's add flag and drop flag are zero, any subsequent
1802 * configure endpoint command will leave that endpoint's state
1803 * untouched. Make sure we don't leave any old state in the input
1804 * endpoint contexts.
1805 */
1806 ctrl_ctx->drop_flags = 0;
1807 ctrl_ctx->add_flags = 0;
1808 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1809 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1810 /* Endpoint 0 is always valid */
1811 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1812 for (i = 1; i < 31; ++i) {
1813 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1814 ep_ctx->ep_info = 0;
1815 ep_ctx->ep_info2 = 0;
1816 ep_ctx->deq = 0;
1817 ep_ctx->tx_info = 0;
1818 }
1819}
1820
1821static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1822 struct usb_device *udev, u32 *cmd_status)
1823{
1824 int ret;
1825
1826 switch (*cmd_status) {
1827 case COMP_CMD_ABORT:
1828 case COMP_CMD_STOP:
1829 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1830 ret = -ETIME;
1831 break;
1832 case COMP_ENOMEM:
1833 dev_warn(&udev->dev,
1834 "Not enough host controller resources for new device state.\n");
1835 ret = -ENOMEM;
1836 /* FIXME: can we allocate more resources for the HC? */
1837 break;
1838 case COMP_BW_ERR:
1839 case COMP_2ND_BW_ERR:
1840 dev_warn(&udev->dev,
1841 "Not enough bandwidth for new device state.\n");
1842 ret = -ENOSPC;
1843 /* FIXME: can we go back to the old state? */
1844 break;
1845 case COMP_TRB_ERR:
1846 /* the HCD set up something wrong */
1847 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1848 "add flag = 1, "
1849 "and endpoint is not disabled.\n");
1850 ret = -EINVAL;
1851 break;
1852 case COMP_DEV_ERR:
1853 dev_warn(&udev->dev,
1854 "ERROR: Incompatible device for endpoint configure command.\n");
1855 ret = -ENODEV;
1856 break;
1857 case COMP_SUCCESS:
1858 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1859 "Successful Endpoint Configure command");
1860 ret = 0;
1861 break;
1862 default:
1863 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1864 *cmd_status);
1865 ret = -EINVAL;
1866 break;
1867 }
1868 return ret;
1869}
1870
1871static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1872 struct usb_device *udev, u32 *cmd_status)
1873{
1874 int ret;
1875 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1876
1877 switch (*cmd_status) {
1878 case COMP_CMD_ABORT:
1879 case COMP_CMD_STOP:
1880 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1881 ret = -ETIME;
1882 break;
1883 case COMP_EINVAL:
1884 dev_warn(&udev->dev,
1885 "WARN: xHCI driver setup invalid evaluate context command.\n");
1886 ret = -EINVAL;
1887 break;
1888 case COMP_EBADSLT:
1889 dev_warn(&udev->dev,
1890 "WARN: slot not enabled for evaluate context command.\n");
1891 ret = -EINVAL;
1892 break;
1893 case COMP_CTX_STATE:
1894 dev_warn(&udev->dev,
1895 "WARN: invalid context state for evaluate context command.\n");
1896 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1897 ret = -EINVAL;
1898 break;
1899 case COMP_DEV_ERR:
1900 dev_warn(&udev->dev,
1901 "ERROR: Incompatible device for evaluate context command.\n");
1902 ret = -ENODEV;
1903 break;
1904 case COMP_MEL_ERR:
1905 /* Max Exit Latency too large error */
1906 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1907 ret = -EINVAL;
1908 break;
1909 case COMP_SUCCESS:
1910 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1911 "Successful evaluate context command");
1912 ret = 0;
1913 break;
1914 default:
1915 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1916 *cmd_status);
1917 ret = -EINVAL;
1918 break;
1919 }
1920 return ret;
1921}
1922
1923static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1924 struct xhci_input_control_ctx *ctrl_ctx)
1925{
1926 u32 valid_add_flags;
1927 u32 valid_drop_flags;
1928
1929 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1930 * (bit 1). The default control endpoint is added during the Address
1931 * Device command and is never removed until the slot is disabled.
1932 */
1933 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1934 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1935
1936 /* Use hweight32 to count the number of ones in the add flags, or
1937 * number of endpoints added. Don't count endpoints that are changed
1938 * (both added and dropped).
1939 */
1940 return hweight32(valid_add_flags) -
1941 hweight32(valid_add_flags & valid_drop_flags);
1942}
1943
1944static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1945 struct xhci_input_control_ctx *ctrl_ctx)
1946{
1947 u32 valid_add_flags;
1948 u32 valid_drop_flags;
1949
1950 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1951 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1952
1953 return hweight32(valid_drop_flags) -
1954 hweight32(valid_add_flags & valid_drop_flags);
1955}
1956
1957/*
1958 * We need to reserve the new number of endpoints before the configure endpoint
1959 * command completes. We can't subtract the dropped endpoints from the number
1960 * of active endpoints until the command completes because we can oversubscribe
1961 * the host in this case:
1962 *
1963 * - the first configure endpoint command drops more endpoints than it adds
1964 * - a second configure endpoint command that adds more endpoints is queued
1965 * - the first configure endpoint command fails, so the config is unchanged
1966 * - the second command may succeed, even though there isn't enough resources
1967 *
1968 * Must be called with xhci->lock held.
1969 */
1970static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1971 struct xhci_input_control_ctx *ctrl_ctx)
1972{
1973 u32 added_eps;
1974
1975 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1976 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1977 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1978 "Not enough ep ctxs: "
1979 "%u active, need to add %u, limit is %u.",
1980 xhci->num_active_eps, added_eps,
1981 xhci->limit_active_eps);
1982 return -ENOMEM;
1983 }
1984 xhci->num_active_eps += added_eps;
1985 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1986 "Adding %u ep ctxs, %u now active.", added_eps,
1987 xhci->num_active_eps);
1988 return 0;
1989}
1990
1991/*
1992 * The configure endpoint was failed by the xHC for some other reason, so we
1993 * need to revert the resources that failed configuration would have used.
1994 *
1995 * Must be called with xhci->lock held.
1996 */
1997static void xhci_free_host_resources(struct xhci_hcd *xhci,
1998 struct xhci_input_control_ctx *ctrl_ctx)
1999{
2000 u32 num_failed_eps;
2001
2002 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2003 xhci->num_active_eps -= num_failed_eps;
2004 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2005 "Removing %u failed ep ctxs, %u now active.",
2006 num_failed_eps,
2007 xhci->num_active_eps);
2008}
2009
2010/*
2011 * Now that the command has completed, clean up the active endpoint count by
2012 * subtracting out the endpoints that were dropped (but not changed).
2013 *
2014 * Must be called with xhci->lock held.
2015 */
2016static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2017 struct xhci_input_control_ctx *ctrl_ctx)
2018{
2019 u32 num_dropped_eps;
2020
2021 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2022 xhci->num_active_eps -= num_dropped_eps;
2023 if (num_dropped_eps)
2024 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2025 "Removing %u dropped ep ctxs, %u now active.",
2026 num_dropped_eps,
2027 xhci->num_active_eps);
2028}
2029
2030static unsigned int xhci_get_block_size(struct usb_device *udev)
2031{
2032 switch (udev->speed) {
2033 case USB_SPEED_LOW:
2034 case USB_SPEED_FULL:
2035 return FS_BLOCK;
2036 case USB_SPEED_HIGH:
2037 return HS_BLOCK;
2038 case USB_SPEED_SUPER:
2039 case USB_SPEED_SUPER_PLUS:
2040 return SS_BLOCK;
2041 case USB_SPEED_UNKNOWN:
2042 case USB_SPEED_WIRELESS:
2043 default:
2044 /* Should never happen */
2045 return 1;
2046 }
2047}
2048
2049static unsigned int
2050xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2051{
2052 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2053 return LS_OVERHEAD;
2054 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2055 return FS_OVERHEAD;
2056 return HS_OVERHEAD;
2057}
2058
2059/* If we are changing a LS/FS device under a HS hub,
2060 * make sure (if we are activating a new TT) that the HS bus has enough
2061 * bandwidth for this new TT.
2062 */
2063static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2064 struct xhci_virt_device *virt_dev,
2065 int old_active_eps)
2066{
2067 struct xhci_interval_bw_table *bw_table;
2068 struct xhci_tt_bw_info *tt_info;
2069
2070 /* Find the bandwidth table for the root port this TT is attached to. */
2071 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2072 tt_info = virt_dev->tt_info;
2073 /* If this TT already had active endpoints, the bandwidth for this TT
2074 * has already been added. Removing all periodic endpoints (and thus
2075 * making the TT enactive) will only decrease the bandwidth used.
2076 */
2077 if (old_active_eps)
2078 return 0;
2079 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2080 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2081 return -ENOMEM;
2082 return 0;
2083 }
2084 /* Not sure why we would have no new active endpoints...
2085 *
2086 * Maybe because of an Evaluate Context change for a hub update or a
2087 * control endpoint 0 max packet size change?
2088 * FIXME: skip the bandwidth calculation in that case.
2089 */
2090 return 0;
2091}
2092
2093static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2094 struct xhci_virt_device *virt_dev)
2095{
2096 unsigned int bw_reserved;
2097
2098 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2099 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2100 return -ENOMEM;
2101
2102 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2103 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2104 return -ENOMEM;
2105
2106 return 0;
2107}
2108
2109/*
2110 * This algorithm is a very conservative estimate of the worst-case scheduling
2111 * scenario for any one interval. The hardware dynamically schedules the
2112 * packets, so we can't tell which microframe could be the limiting factor in
2113 * the bandwidth scheduling. This only takes into account periodic endpoints.
2114 *
2115 * Obviously, we can't solve an NP complete problem to find the minimum worst
2116 * case scenario. Instead, we come up with an estimate that is no less than
2117 * the worst case bandwidth used for any one microframe, but may be an
2118 * over-estimate.
2119 *
2120 * We walk the requirements for each endpoint by interval, starting with the
2121 * smallest interval, and place packets in the schedule where there is only one
2122 * possible way to schedule packets for that interval. In order to simplify
2123 * this algorithm, we record the largest max packet size for each interval, and
2124 * assume all packets will be that size.
2125 *
2126 * For interval 0, we obviously must schedule all packets for each interval.
2127 * The bandwidth for interval 0 is just the amount of data to be transmitted
2128 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2129 * the number of packets).
2130 *
2131 * For interval 1, we have two possible microframes to schedule those packets
2132 * in. For this algorithm, if we can schedule the same number of packets for
2133 * each possible scheduling opportunity (each microframe), we will do so. The
2134 * remaining number of packets will be saved to be transmitted in the gaps in
2135 * the next interval's scheduling sequence.
2136 *
2137 * As we move those remaining packets to be scheduled with interval 2 packets,
2138 * we have to double the number of remaining packets to transmit. This is
2139 * because the intervals are actually powers of 2, and we would be transmitting
2140 * the previous interval's packets twice in this interval. We also have to be
2141 * sure that when we look at the largest max packet size for this interval, we
2142 * also look at the largest max packet size for the remaining packets and take
2143 * the greater of the two.
2144 *
2145 * The algorithm continues to evenly distribute packets in each scheduling
2146 * opportunity, and push the remaining packets out, until we get to the last
2147 * interval. Then those packets and their associated overhead are just added
2148 * to the bandwidth used.
2149 */
2150static int xhci_check_bw_table(struct xhci_hcd *xhci,
2151 struct xhci_virt_device *virt_dev,
2152 int old_active_eps)
2153{
2154 unsigned int bw_reserved;
2155 unsigned int max_bandwidth;
2156 unsigned int bw_used;
2157 unsigned int block_size;
2158 struct xhci_interval_bw_table *bw_table;
2159 unsigned int packet_size = 0;
2160 unsigned int overhead = 0;
2161 unsigned int packets_transmitted = 0;
2162 unsigned int packets_remaining = 0;
2163 unsigned int i;
2164
2165 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2166 return xhci_check_ss_bw(xhci, virt_dev);
2167
2168 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2169 max_bandwidth = HS_BW_LIMIT;
2170 /* Convert percent of bus BW reserved to blocks reserved */
2171 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2172 } else {
2173 max_bandwidth = FS_BW_LIMIT;
2174 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2175 }
2176
2177 bw_table = virt_dev->bw_table;
2178 /* We need to translate the max packet size and max ESIT payloads into
2179 * the units the hardware uses.
2180 */
2181 block_size = xhci_get_block_size(virt_dev->udev);
2182
2183 /* If we are manipulating a LS/FS device under a HS hub, double check
2184 * that the HS bus has enough bandwidth if we are activing a new TT.
2185 */
2186 if (virt_dev->tt_info) {
2187 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2188 "Recalculating BW for rootport %u",
2189 virt_dev->real_port);
2190 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2191 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2192 "newly activated TT.\n");
2193 return -ENOMEM;
2194 }
2195 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2196 "Recalculating BW for TT slot %u port %u",
2197 virt_dev->tt_info->slot_id,
2198 virt_dev->tt_info->ttport);
2199 } else {
2200 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2201 "Recalculating BW for rootport %u",
2202 virt_dev->real_port);
2203 }
2204
2205 /* Add in how much bandwidth will be used for interval zero, or the
2206 * rounded max ESIT payload + number of packets * largest overhead.
2207 */
2208 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2209 bw_table->interval_bw[0].num_packets *
2210 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2211
2212 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2213 unsigned int bw_added;
2214 unsigned int largest_mps;
2215 unsigned int interval_overhead;
2216
2217 /*
2218 * How many packets could we transmit in this interval?
2219 * If packets didn't fit in the previous interval, we will need
2220 * to transmit that many packets twice within this interval.
2221 */
2222 packets_remaining = 2 * packets_remaining +
2223 bw_table->interval_bw[i].num_packets;
2224
2225 /* Find the largest max packet size of this or the previous
2226 * interval.
2227 */
2228 if (list_empty(&bw_table->interval_bw[i].endpoints))
2229 largest_mps = 0;
2230 else {
2231 struct xhci_virt_ep *virt_ep;
2232 struct list_head *ep_entry;
2233
2234 ep_entry = bw_table->interval_bw[i].endpoints.next;
2235 virt_ep = list_entry(ep_entry,
2236 struct xhci_virt_ep, bw_endpoint_list);
2237 /* Convert to blocks, rounding up */
2238 largest_mps = DIV_ROUND_UP(
2239 virt_ep->bw_info.max_packet_size,
2240 block_size);
2241 }
2242 if (largest_mps > packet_size)
2243 packet_size = largest_mps;
2244
2245 /* Use the larger overhead of this or the previous interval. */
2246 interval_overhead = xhci_get_largest_overhead(
2247 &bw_table->interval_bw[i]);
2248 if (interval_overhead > overhead)
2249 overhead = interval_overhead;
2250
2251 /* How many packets can we evenly distribute across
2252 * (1 << (i + 1)) possible scheduling opportunities?
2253 */
2254 packets_transmitted = packets_remaining >> (i + 1);
2255
2256 /* Add in the bandwidth used for those scheduled packets */
2257 bw_added = packets_transmitted * (overhead + packet_size);
2258
2259 /* How many packets do we have remaining to transmit? */
2260 packets_remaining = packets_remaining % (1 << (i + 1));
2261
2262 /* What largest max packet size should those packets have? */
2263 /* If we've transmitted all packets, don't carry over the
2264 * largest packet size.
2265 */
2266 if (packets_remaining == 0) {
2267 packet_size = 0;
2268 overhead = 0;
2269 } else if (packets_transmitted > 0) {
2270 /* Otherwise if we do have remaining packets, and we've
2271 * scheduled some packets in this interval, take the
2272 * largest max packet size from endpoints with this
2273 * interval.
2274 */
2275 packet_size = largest_mps;
2276 overhead = interval_overhead;
2277 }
2278 /* Otherwise carry over packet_size and overhead from the last
2279 * time we had a remainder.
2280 */
2281 bw_used += bw_added;
2282 if (bw_used > max_bandwidth) {
2283 xhci_warn(xhci, "Not enough bandwidth. "
2284 "Proposed: %u, Max: %u\n",
2285 bw_used, max_bandwidth);
2286 return -ENOMEM;
2287 }
2288 }
2289 /*
2290 * Ok, we know we have some packets left over after even-handedly
2291 * scheduling interval 15. We don't know which microframes they will
2292 * fit into, so we over-schedule and say they will be scheduled every
2293 * microframe.
2294 */
2295 if (packets_remaining > 0)
2296 bw_used += overhead + packet_size;
2297
2298 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2299 unsigned int port_index = virt_dev->real_port - 1;
2300
2301 /* OK, we're manipulating a HS device attached to a
2302 * root port bandwidth domain. Include the number of active TTs
2303 * in the bandwidth used.
2304 */
2305 bw_used += TT_HS_OVERHEAD *
2306 xhci->rh_bw[port_index].num_active_tts;
2307 }
2308
2309 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2310 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2311 "Available: %u " "percent",
2312 bw_used, max_bandwidth, bw_reserved,
2313 (max_bandwidth - bw_used - bw_reserved) * 100 /
2314 max_bandwidth);
2315
2316 bw_used += bw_reserved;
2317 if (bw_used > max_bandwidth) {
2318 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2319 bw_used, max_bandwidth);
2320 return -ENOMEM;
2321 }
2322
2323 bw_table->bw_used = bw_used;
2324 return 0;
2325}
2326
2327static bool xhci_is_async_ep(unsigned int ep_type)
2328{
2329 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2330 ep_type != ISOC_IN_EP &&
2331 ep_type != INT_IN_EP);
2332}
2333
2334static bool xhci_is_sync_in_ep(unsigned int ep_type)
2335{
2336 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2337}
2338
2339static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2340{
2341 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2342
2343 if (ep_bw->ep_interval == 0)
2344 return SS_OVERHEAD_BURST +
2345 (ep_bw->mult * ep_bw->num_packets *
2346 (SS_OVERHEAD + mps));
2347 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2348 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2349 1 << ep_bw->ep_interval);
2350
2351}
2352
2353void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2354 struct xhci_bw_info *ep_bw,
2355 struct xhci_interval_bw_table *bw_table,
2356 struct usb_device *udev,
2357 struct xhci_virt_ep *virt_ep,
2358 struct xhci_tt_bw_info *tt_info)
2359{
2360 struct xhci_interval_bw *interval_bw;
2361 int normalized_interval;
2362
2363 if (xhci_is_async_ep(ep_bw->type))
2364 return;
2365
2366 if (udev->speed >= USB_SPEED_SUPER) {
2367 if (xhci_is_sync_in_ep(ep_bw->type))
2368 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2369 xhci_get_ss_bw_consumed(ep_bw);
2370 else
2371 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2372 xhci_get_ss_bw_consumed(ep_bw);
2373 return;
2374 }
2375
2376 /* SuperSpeed endpoints never get added to intervals in the table, so
2377 * this check is only valid for HS/FS/LS devices.
2378 */
2379 if (list_empty(&virt_ep->bw_endpoint_list))
2380 return;
2381 /* For LS/FS devices, we need to translate the interval expressed in
2382 * microframes to frames.
2383 */
2384 if (udev->speed == USB_SPEED_HIGH)
2385 normalized_interval = ep_bw->ep_interval;
2386 else
2387 normalized_interval = ep_bw->ep_interval - 3;
2388
2389 if (normalized_interval == 0)
2390 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2391 interval_bw = &bw_table->interval_bw[normalized_interval];
2392 interval_bw->num_packets -= ep_bw->num_packets;
2393 switch (udev->speed) {
2394 case USB_SPEED_LOW:
2395 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2396 break;
2397 case USB_SPEED_FULL:
2398 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2399 break;
2400 case USB_SPEED_HIGH:
2401 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2402 break;
2403 case USB_SPEED_SUPER:
2404 case USB_SPEED_SUPER_PLUS:
2405 case USB_SPEED_UNKNOWN:
2406 case USB_SPEED_WIRELESS:
2407 /* Should never happen because only LS/FS/HS endpoints will get
2408 * added to the endpoint list.
2409 */
2410 return;
2411 }
2412 if (tt_info)
2413 tt_info->active_eps -= 1;
2414 list_del_init(&virt_ep->bw_endpoint_list);
2415}
2416
2417static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2418 struct xhci_bw_info *ep_bw,
2419 struct xhci_interval_bw_table *bw_table,
2420 struct usb_device *udev,
2421 struct xhci_virt_ep *virt_ep,
2422 struct xhci_tt_bw_info *tt_info)
2423{
2424 struct xhci_interval_bw *interval_bw;
2425 struct xhci_virt_ep *smaller_ep;
2426 int normalized_interval;
2427
2428 if (xhci_is_async_ep(ep_bw->type))
2429 return;
2430
2431 if (udev->speed == USB_SPEED_SUPER) {
2432 if (xhci_is_sync_in_ep(ep_bw->type))
2433 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2434 xhci_get_ss_bw_consumed(ep_bw);
2435 else
2436 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2437 xhci_get_ss_bw_consumed(ep_bw);
2438 return;
2439 }
2440
2441 /* For LS/FS devices, we need to translate the interval expressed in
2442 * microframes to frames.
2443 */
2444 if (udev->speed == USB_SPEED_HIGH)
2445 normalized_interval = ep_bw->ep_interval;
2446 else
2447 normalized_interval = ep_bw->ep_interval - 3;
2448
2449 if (normalized_interval == 0)
2450 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2451 interval_bw = &bw_table->interval_bw[normalized_interval];
2452 interval_bw->num_packets += ep_bw->num_packets;
2453 switch (udev->speed) {
2454 case USB_SPEED_LOW:
2455 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2456 break;
2457 case USB_SPEED_FULL:
2458 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2459 break;
2460 case USB_SPEED_HIGH:
2461 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2462 break;
2463 case USB_SPEED_SUPER:
2464 case USB_SPEED_SUPER_PLUS:
2465 case USB_SPEED_UNKNOWN:
2466 case USB_SPEED_WIRELESS:
2467 /* Should never happen because only LS/FS/HS endpoints will get
2468 * added to the endpoint list.
2469 */
2470 return;
2471 }
2472
2473 if (tt_info)
2474 tt_info->active_eps += 1;
2475 /* Insert the endpoint into the list, largest max packet size first. */
2476 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2477 bw_endpoint_list) {
2478 if (ep_bw->max_packet_size >=
2479 smaller_ep->bw_info.max_packet_size) {
2480 /* Add the new ep before the smaller endpoint */
2481 list_add_tail(&virt_ep->bw_endpoint_list,
2482 &smaller_ep->bw_endpoint_list);
2483 return;
2484 }
2485 }
2486 /* Add the new endpoint at the end of the list. */
2487 list_add_tail(&virt_ep->bw_endpoint_list,
2488 &interval_bw->endpoints);
2489}
2490
2491void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2492 struct xhci_virt_device *virt_dev,
2493 int old_active_eps)
2494{
2495 struct xhci_root_port_bw_info *rh_bw_info;
2496 if (!virt_dev->tt_info)
2497 return;
2498
2499 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2500 if (old_active_eps == 0 &&
2501 virt_dev->tt_info->active_eps != 0) {
2502 rh_bw_info->num_active_tts += 1;
2503 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2504 } else if (old_active_eps != 0 &&
2505 virt_dev->tt_info->active_eps == 0) {
2506 rh_bw_info->num_active_tts -= 1;
2507 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2508 }
2509}
2510
2511static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2512 struct xhci_virt_device *virt_dev,
2513 struct xhci_container_ctx *in_ctx)
2514{
2515 struct xhci_bw_info ep_bw_info[31];
2516 int i;
2517 struct xhci_input_control_ctx *ctrl_ctx;
2518 int old_active_eps = 0;
2519
2520 if (virt_dev->tt_info)
2521 old_active_eps = virt_dev->tt_info->active_eps;
2522
2523 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2524 if (!ctrl_ctx) {
2525 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2526 __func__);
2527 return -ENOMEM;
2528 }
2529
2530 for (i = 0; i < 31; i++) {
2531 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2532 continue;
2533
2534 /* Make a copy of the BW info in case we need to revert this */
2535 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2536 sizeof(ep_bw_info[i]));
2537 /* Drop the endpoint from the interval table if the endpoint is
2538 * being dropped or changed.
2539 */
2540 if (EP_IS_DROPPED(ctrl_ctx, i))
2541 xhci_drop_ep_from_interval_table(xhci,
2542 &virt_dev->eps[i].bw_info,
2543 virt_dev->bw_table,
2544 virt_dev->udev,
2545 &virt_dev->eps[i],
2546 virt_dev->tt_info);
2547 }
2548 /* Overwrite the information stored in the endpoints' bw_info */
2549 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2550 for (i = 0; i < 31; i++) {
2551 /* Add any changed or added endpoints to the interval table */
2552 if (EP_IS_ADDED(ctrl_ctx, i))
2553 xhci_add_ep_to_interval_table(xhci,
2554 &virt_dev->eps[i].bw_info,
2555 virt_dev->bw_table,
2556 virt_dev->udev,
2557 &virt_dev->eps[i],
2558 virt_dev->tt_info);
2559 }
2560
2561 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2562 /* Ok, this fits in the bandwidth we have.
2563 * Update the number of active TTs.
2564 */
2565 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2566 return 0;
2567 }
2568
2569 /* We don't have enough bandwidth for this, revert the stored info. */
2570 for (i = 0; i < 31; i++) {
2571 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2572 continue;
2573
2574 /* Drop the new copies of any added or changed endpoints from
2575 * the interval table.
2576 */
2577 if (EP_IS_ADDED(ctrl_ctx, i)) {
2578 xhci_drop_ep_from_interval_table(xhci,
2579 &virt_dev->eps[i].bw_info,
2580 virt_dev->bw_table,
2581 virt_dev->udev,
2582 &virt_dev->eps[i],
2583 virt_dev->tt_info);
2584 }
2585 /* Revert the endpoint back to its old information */
2586 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2587 sizeof(ep_bw_info[i]));
2588 /* Add any changed or dropped endpoints back into the table */
2589 if (EP_IS_DROPPED(ctrl_ctx, i))
2590 xhci_add_ep_to_interval_table(xhci,
2591 &virt_dev->eps[i].bw_info,
2592 virt_dev->bw_table,
2593 virt_dev->udev,
2594 &virt_dev->eps[i],
2595 virt_dev->tt_info);
2596 }
2597 return -ENOMEM;
2598}
2599
2600
2601/* Issue a configure endpoint command or evaluate context command
2602 * and wait for it to finish.
2603 */
2604static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2605 struct usb_device *udev,
2606 struct xhci_command *command,
2607 bool ctx_change, bool must_succeed)
2608{
2609 int ret;
2610 unsigned long flags;
2611 struct xhci_input_control_ctx *ctrl_ctx;
2612 struct xhci_virt_device *virt_dev;
2613
2614 if (!command)
2615 return -EINVAL;
2616
2617 spin_lock_irqsave(&xhci->lock, flags);
2618 virt_dev = xhci->devs[udev->slot_id];
2619
2620 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2621 if (!ctrl_ctx) {
2622 spin_unlock_irqrestore(&xhci->lock, flags);
2623 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2624 __func__);
2625 return -ENOMEM;
2626 }
2627
2628 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2629 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2630 spin_unlock_irqrestore(&xhci->lock, flags);
2631 xhci_warn(xhci, "Not enough host resources, "
2632 "active endpoint contexts = %u\n",
2633 xhci->num_active_eps);
2634 return -ENOMEM;
2635 }
2636 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2637 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2638 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2639 xhci_free_host_resources(xhci, ctrl_ctx);
2640 spin_unlock_irqrestore(&xhci->lock, flags);
2641 xhci_warn(xhci, "Not enough bandwidth\n");
2642 return -ENOMEM;
2643 }
2644
2645 if (!ctx_change)
2646 ret = xhci_queue_configure_endpoint(xhci, command,
2647 command->in_ctx->dma,
2648 udev->slot_id, must_succeed);
2649 else
2650 ret = xhci_queue_evaluate_context(xhci, command,
2651 command->in_ctx->dma,
2652 udev->slot_id, must_succeed);
2653 if (ret < 0) {
2654 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2655 xhci_free_host_resources(xhci, ctrl_ctx);
2656 spin_unlock_irqrestore(&xhci->lock, flags);
2657 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2658 "FIXME allocate a new ring segment");
2659 return -ENOMEM;
2660 }
2661 xhci_ring_cmd_db(xhci);
2662 spin_unlock_irqrestore(&xhci->lock, flags);
2663
2664 /* Wait for the configure endpoint command to complete */
2665 wait_for_completion(command->completion);
2666
2667 if (!ctx_change)
2668 ret = xhci_configure_endpoint_result(xhci, udev,
2669 &command->status);
2670 else
2671 ret = xhci_evaluate_context_result(xhci, udev,
2672 &command->status);
2673
2674 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2675 spin_lock_irqsave(&xhci->lock, flags);
2676 /* If the command failed, remove the reserved resources.
2677 * Otherwise, clean up the estimate to include dropped eps.
2678 */
2679 if (ret)
2680 xhci_free_host_resources(xhci, ctrl_ctx);
2681 else
2682 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2683 spin_unlock_irqrestore(&xhci->lock, flags);
2684 }
2685 return ret;
2686}
2687
2688static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2689 struct xhci_virt_device *vdev, int i)
2690{
2691 struct xhci_virt_ep *ep = &vdev->eps[i];
2692
2693 if (ep->ep_state & EP_HAS_STREAMS) {
2694 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2695 xhci_get_endpoint_address(i));
2696 xhci_free_stream_info(xhci, ep->stream_info);
2697 ep->stream_info = NULL;
2698 ep->ep_state &= ~EP_HAS_STREAMS;
2699 }
2700}
2701
2702/* Called after one or more calls to xhci_add_endpoint() or
2703 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2704 * to call xhci_reset_bandwidth().
2705 *
2706 * Since we are in the middle of changing either configuration or
2707 * installing a new alt setting, the USB core won't allow URBs to be
2708 * enqueued for any endpoint on the old config or interface. Nothing
2709 * else should be touching the xhci->devs[slot_id] structure, so we
2710 * don't need to take the xhci->lock for manipulating that.
2711 */
2712int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2713{
2714 int i;
2715 int ret = 0;
2716 struct xhci_hcd *xhci;
2717 struct xhci_virt_device *virt_dev;
2718 struct xhci_input_control_ctx *ctrl_ctx;
2719 struct xhci_slot_ctx *slot_ctx;
2720 struct xhci_command *command;
2721
2722 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2723 if (ret <= 0)
2724 return ret;
2725 xhci = hcd_to_xhci(hcd);
2726 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2727 (xhci->xhc_state & XHCI_STATE_REMOVING))
2728 return -ENODEV;
2729
2730 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2731 virt_dev = xhci->devs[udev->slot_id];
2732
2733 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2734 if (!command)
2735 return -ENOMEM;
2736
2737 command->in_ctx = virt_dev->in_ctx;
2738
2739 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2740 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2741 if (!ctrl_ctx) {
2742 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2743 __func__);
2744 ret = -ENOMEM;
2745 goto command_cleanup;
2746 }
2747 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2748 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2749 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2750
2751 /* Don't issue the command if there's no endpoints to update. */
2752 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2753 ctrl_ctx->drop_flags == 0) {
2754 ret = 0;
2755 goto command_cleanup;
2756 }
2757 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2758 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2759 for (i = 31; i >= 1; i--) {
2760 __le32 le32 = cpu_to_le32(BIT(i));
2761
2762 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2763 || (ctrl_ctx->add_flags & le32) || i == 1) {
2764 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2765 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2766 break;
2767 }
2768 }
2769 xhci_dbg(xhci, "New Input Control Context:\n");
2770 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2771 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2772
2773 ret = xhci_configure_endpoint(xhci, udev, command,
2774 false, false);
2775 if (ret)
2776 /* Callee should call reset_bandwidth() */
2777 goto command_cleanup;
2778
2779 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2780 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2781 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2782
2783 /* Free any rings that were dropped, but not changed. */
2784 for (i = 1; i < 31; ++i) {
2785 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2786 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2787 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2788 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2789 }
2790 }
2791 xhci_zero_in_ctx(xhci, virt_dev);
2792 /*
2793 * Install any rings for completely new endpoints or changed endpoints,
2794 * and free or cache any old rings from changed endpoints.
2795 */
2796 for (i = 1; i < 31; ++i) {
2797 if (!virt_dev->eps[i].new_ring)
2798 continue;
2799 /* Only cache or free the old ring if it exists.
2800 * It may not if this is the first add of an endpoint.
2801 */
2802 if (virt_dev->eps[i].ring) {
2803 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2804 }
2805 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2806 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2807 virt_dev->eps[i].new_ring = NULL;
2808 }
2809command_cleanup:
2810 kfree(command->completion);
2811 kfree(command);
2812
2813 return ret;
2814}
2815
2816void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2817{
2818 struct xhci_hcd *xhci;
2819 struct xhci_virt_device *virt_dev;
2820 int i, ret;
2821
2822 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2823 if (ret <= 0)
2824 return;
2825 xhci = hcd_to_xhci(hcd);
2826
2827 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2828 virt_dev = xhci->devs[udev->slot_id];
2829 /* Free any rings allocated for added endpoints */
2830 for (i = 0; i < 31; ++i) {
2831 if (virt_dev->eps[i].new_ring) {
2832 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2833 virt_dev->eps[i].new_ring = NULL;
2834 }
2835 }
2836 xhci_zero_in_ctx(xhci, virt_dev);
2837}
2838
2839static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2840 struct xhci_container_ctx *in_ctx,
2841 struct xhci_container_ctx *out_ctx,
2842 struct xhci_input_control_ctx *ctrl_ctx,
2843 u32 add_flags, u32 drop_flags)
2844{
2845 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2846 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2847 xhci_slot_copy(xhci, in_ctx, out_ctx);
2848 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2849
2850 xhci_dbg(xhci, "Input Context:\n");
2851 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2852}
2853
2854static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2855 unsigned int slot_id, unsigned int ep_index,
2856 struct xhci_dequeue_state *deq_state)
2857{
2858 struct xhci_input_control_ctx *ctrl_ctx;
2859 struct xhci_container_ctx *in_ctx;
2860 struct xhci_ep_ctx *ep_ctx;
2861 u32 added_ctxs;
2862 dma_addr_t addr;
2863
2864 in_ctx = xhci->devs[slot_id]->in_ctx;
2865 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2866 if (!ctrl_ctx) {
2867 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2868 __func__);
2869 return;
2870 }
2871
2872 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2873 xhci->devs[slot_id]->out_ctx, ep_index);
2874 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2875 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2876 deq_state->new_deq_ptr);
2877 if (addr == 0) {
2878 xhci_warn(xhci, "WARN Cannot submit config ep after "
2879 "reset ep command\n");
2880 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2881 deq_state->new_deq_seg,
2882 deq_state->new_deq_ptr);
2883 return;
2884 }
2885 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2886
2887 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2888 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2889 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2890 added_ctxs, added_ctxs);
2891}
2892
2893void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2894 unsigned int ep_index, struct xhci_td *td)
2895{
2896 struct xhci_dequeue_state deq_state;
2897 struct xhci_virt_ep *ep;
2898 struct usb_device *udev = td->urb->dev;
2899
2900 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2901 "Cleaning up stalled endpoint ring");
2902 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2903 /* We need to move the HW's dequeue pointer past this TD,
2904 * or it will attempt to resend it on the next doorbell ring.
2905 */
2906 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2907 ep_index, ep->stopped_stream, td, &deq_state);
2908
2909 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2910 return;
2911
2912 /* HW with the reset endpoint quirk will use the saved dequeue state to
2913 * issue a configure endpoint command later.
2914 */
2915 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2916 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2917 "Queueing new dequeue state");
2918 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2919 ep_index, ep->stopped_stream, &deq_state);
2920 } else {
2921 /* Better hope no one uses the input context between now and the
2922 * reset endpoint completion!
2923 * XXX: No idea how this hardware will react when stream rings
2924 * are enabled.
2925 */
2926 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2927 "Setting up input context for "
2928 "configure endpoint command");
2929 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2930 ep_index, &deq_state);
2931 }
2932}
2933
2934/* Called when clearing halted device. The core should have sent the control
2935 * message to clear the device halt condition. The host side of the halt should
2936 * already be cleared with a reset endpoint command issued when the STALL tx
2937 * event was received.
2938 *
2939 * Context: in_interrupt
2940 */
2941
2942void xhci_endpoint_reset(struct usb_hcd *hcd,
2943 struct usb_host_endpoint *ep)
2944{
2945 struct xhci_hcd *xhci;
2946
2947 xhci = hcd_to_xhci(hcd);
2948
2949 /*
2950 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2951 * The Reset Endpoint Command may only be issued to endpoints in the
2952 * Halted state. If software wishes reset the Data Toggle or Sequence
2953 * Number of an endpoint that isn't in the Halted state, then software
2954 * may issue a Configure Endpoint Command with the Drop and Add bits set
2955 * for the target endpoint. that is in the Stopped state.
2956 */
2957
2958 /* For now just print debug to follow the situation */
2959 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
2960 ep->desc.bEndpointAddress);
2961}
2962
2963static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2964 struct usb_device *udev, struct usb_host_endpoint *ep,
2965 unsigned int slot_id)
2966{
2967 int ret;
2968 unsigned int ep_index;
2969 unsigned int ep_state;
2970
2971 if (!ep)
2972 return -EINVAL;
2973 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2974 if (ret <= 0)
2975 return -EINVAL;
2976 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
2977 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2978 " descriptor for ep 0x%x does not support streams\n",
2979 ep->desc.bEndpointAddress);
2980 return -EINVAL;
2981 }
2982
2983 ep_index = xhci_get_endpoint_index(&ep->desc);
2984 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2985 if (ep_state & EP_HAS_STREAMS ||
2986 ep_state & EP_GETTING_STREAMS) {
2987 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2988 "already has streams set up.\n",
2989 ep->desc.bEndpointAddress);
2990 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2991 "dynamic stream context array reallocation.\n");
2992 return -EINVAL;
2993 }
2994 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2995 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2996 "endpoint 0x%x; URBs are pending.\n",
2997 ep->desc.bEndpointAddress);
2998 return -EINVAL;
2999 }
3000 return 0;
3001}
3002
3003static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3004 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3005{
3006 unsigned int max_streams;
3007
3008 /* The stream context array size must be a power of two */
3009 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3010 /*
3011 * Find out how many primary stream array entries the host controller
3012 * supports. Later we may use secondary stream arrays (similar to 2nd
3013 * level page entries), but that's an optional feature for xHCI host
3014 * controllers. xHCs must support at least 4 stream IDs.
3015 */
3016 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3017 if (*num_stream_ctxs > max_streams) {
3018 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3019 max_streams);
3020 *num_stream_ctxs = max_streams;
3021 *num_streams = max_streams;
3022 }
3023}
3024
3025/* Returns an error code if one of the endpoint already has streams.
3026 * This does not change any data structures, it only checks and gathers
3027 * information.
3028 */
3029static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3030 struct usb_device *udev,
3031 struct usb_host_endpoint **eps, unsigned int num_eps,
3032 unsigned int *num_streams, u32 *changed_ep_bitmask)
3033{
3034 unsigned int max_streams;
3035 unsigned int endpoint_flag;
3036 int i;
3037 int ret;
3038
3039 for (i = 0; i < num_eps; i++) {
3040 ret = xhci_check_streams_endpoint(xhci, udev,
3041 eps[i], udev->slot_id);
3042 if (ret < 0)
3043 return ret;
3044
3045 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3046 if (max_streams < (*num_streams - 1)) {
3047 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3048 eps[i]->desc.bEndpointAddress,
3049 max_streams);
3050 *num_streams = max_streams+1;
3051 }
3052
3053 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3054 if (*changed_ep_bitmask & endpoint_flag)
3055 return -EINVAL;
3056 *changed_ep_bitmask |= endpoint_flag;
3057 }
3058 return 0;
3059}
3060
3061static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3062 struct usb_device *udev,
3063 struct usb_host_endpoint **eps, unsigned int num_eps)
3064{
3065 u32 changed_ep_bitmask = 0;
3066 unsigned int slot_id;
3067 unsigned int ep_index;
3068 unsigned int ep_state;
3069 int i;
3070
3071 slot_id = udev->slot_id;
3072 if (!xhci->devs[slot_id])
3073 return 0;
3074
3075 for (i = 0; i < num_eps; i++) {
3076 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3077 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3078 /* Are streams already being freed for the endpoint? */
3079 if (ep_state & EP_GETTING_NO_STREAMS) {
3080 xhci_warn(xhci, "WARN Can't disable streams for "
3081 "endpoint 0x%x, "
3082 "streams are being disabled already\n",
3083 eps[i]->desc.bEndpointAddress);
3084 return 0;
3085 }
3086 /* Are there actually any streams to free? */
3087 if (!(ep_state & EP_HAS_STREAMS) &&
3088 !(ep_state & EP_GETTING_STREAMS)) {
3089 xhci_warn(xhci, "WARN Can't disable streams for "
3090 "endpoint 0x%x, "
3091 "streams are already disabled!\n",
3092 eps[i]->desc.bEndpointAddress);
3093 xhci_warn(xhci, "WARN xhci_free_streams() called "
3094 "with non-streams endpoint\n");
3095 return 0;
3096 }
3097 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3098 }
3099 return changed_ep_bitmask;
3100}
3101
3102/*
3103 * The USB device drivers use this function (through the HCD interface in USB
3104 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3105 * coordinate mass storage command queueing across multiple endpoints (basically
3106 * a stream ID == a task ID).
3107 *
3108 * Setting up streams involves allocating the same size stream context array
3109 * for each endpoint and issuing a configure endpoint command for all endpoints.
3110 *
3111 * Don't allow the call to succeed if one endpoint only supports one stream
3112 * (which means it doesn't support streams at all).
3113 *
3114 * Drivers may get less stream IDs than they asked for, if the host controller
3115 * hardware or endpoints claim they can't support the number of requested
3116 * stream IDs.
3117 */
3118int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3119 struct usb_host_endpoint **eps, unsigned int num_eps,
3120 unsigned int num_streams, gfp_t mem_flags)
3121{
3122 int i, ret;
3123 struct xhci_hcd *xhci;
3124 struct xhci_virt_device *vdev;
3125 struct xhci_command *config_cmd;
3126 struct xhci_input_control_ctx *ctrl_ctx;
3127 unsigned int ep_index;
3128 unsigned int num_stream_ctxs;
3129 unsigned int max_packet;
3130 unsigned long flags;
3131 u32 changed_ep_bitmask = 0;
3132
3133 if (!eps)
3134 return -EINVAL;
3135
3136 /* Add one to the number of streams requested to account for
3137 * stream 0 that is reserved for xHCI usage.
3138 */
3139 num_streams += 1;
3140 xhci = hcd_to_xhci(hcd);
3141 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3142 num_streams);
3143
3144 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3145 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3146 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3147 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3148 return -ENOSYS;
3149 }
3150
3151 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3152 if (!config_cmd) {
3153 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3154 return -ENOMEM;
3155 }
3156 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3157 if (!ctrl_ctx) {
3158 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3159 __func__);
3160 xhci_free_command(xhci, config_cmd);
3161 return -ENOMEM;
3162 }
3163
3164 /* Check to make sure all endpoints are not already configured for
3165 * streams. While we're at it, find the maximum number of streams that
3166 * all the endpoints will support and check for duplicate endpoints.
3167 */
3168 spin_lock_irqsave(&xhci->lock, flags);
3169 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3170 num_eps, &num_streams, &changed_ep_bitmask);
3171 if (ret < 0) {
3172 xhci_free_command(xhci, config_cmd);
3173 spin_unlock_irqrestore(&xhci->lock, flags);
3174 return ret;
3175 }
3176 if (num_streams <= 1) {
3177 xhci_warn(xhci, "WARN: endpoints can't handle "
3178 "more than one stream.\n");
3179 xhci_free_command(xhci, config_cmd);
3180 spin_unlock_irqrestore(&xhci->lock, flags);
3181 return -EINVAL;
3182 }
3183 vdev = xhci->devs[udev->slot_id];
3184 /* Mark each endpoint as being in transition, so
3185 * xhci_urb_enqueue() will reject all URBs.
3186 */
3187 for (i = 0; i < num_eps; i++) {
3188 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3189 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3190 }
3191 spin_unlock_irqrestore(&xhci->lock, flags);
3192
3193 /* Setup internal data structures and allocate HW data structures for
3194 * streams (but don't install the HW structures in the input context
3195 * until we're sure all memory allocation succeeded).
3196 */
3197 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3198 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3199 num_stream_ctxs, num_streams);
3200
3201 for (i = 0; i < num_eps; i++) {
3202 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3203 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3204 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3205 num_stream_ctxs,
3206 num_streams,
3207 max_packet, mem_flags);
3208 if (!vdev->eps[ep_index].stream_info)
3209 goto cleanup;
3210 /* Set maxPstreams in endpoint context and update deq ptr to
3211 * point to stream context array. FIXME
3212 */
3213 }
3214
3215 /* Set up the input context for a configure endpoint command. */
3216 for (i = 0; i < num_eps; i++) {
3217 struct xhci_ep_ctx *ep_ctx;
3218
3219 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3220 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3221
3222 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3223 vdev->out_ctx, ep_index);
3224 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3225 vdev->eps[ep_index].stream_info);
3226 }
3227 /* Tell the HW to drop its old copy of the endpoint context info
3228 * and add the updated copy from the input context.
3229 */
3230 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3231 vdev->out_ctx, ctrl_ctx,
3232 changed_ep_bitmask, changed_ep_bitmask);
3233
3234 /* Issue and wait for the configure endpoint command */
3235 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3236 false, false);
3237
3238 /* xHC rejected the configure endpoint command for some reason, so we
3239 * leave the old ring intact and free our internal streams data
3240 * structure.
3241 */
3242 if (ret < 0)
3243 goto cleanup;
3244
3245 spin_lock_irqsave(&xhci->lock, flags);
3246 for (i = 0; i < num_eps; i++) {
3247 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3248 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3249 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3250 udev->slot_id, ep_index);
3251 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3252 }
3253 xhci_free_command(xhci, config_cmd);
3254 spin_unlock_irqrestore(&xhci->lock, flags);
3255
3256 /* Subtract 1 for stream 0, which drivers can't use */
3257 return num_streams - 1;
3258
3259cleanup:
3260 /* If it didn't work, free the streams! */
3261 for (i = 0; i < num_eps; i++) {
3262 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3263 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3264 vdev->eps[ep_index].stream_info = NULL;
3265 /* FIXME Unset maxPstreams in endpoint context and
3266 * update deq ptr to point to normal string ring.
3267 */
3268 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3269 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3270 xhci_endpoint_zero(xhci, vdev, eps[i]);
3271 }
3272 xhci_free_command(xhci, config_cmd);
3273 return -ENOMEM;
3274}
3275
3276/* Transition the endpoint from using streams to being a "normal" endpoint
3277 * without streams.
3278 *
3279 * Modify the endpoint context state, submit a configure endpoint command,
3280 * and free all endpoint rings for streams if that completes successfully.
3281 */
3282int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3283 struct usb_host_endpoint **eps, unsigned int num_eps,
3284 gfp_t mem_flags)
3285{
3286 int i, ret;
3287 struct xhci_hcd *xhci;
3288 struct xhci_virt_device *vdev;
3289 struct xhci_command *command;
3290 struct xhci_input_control_ctx *ctrl_ctx;
3291 unsigned int ep_index;
3292 unsigned long flags;
3293 u32 changed_ep_bitmask;
3294
3295 xhci = hcd_to_xhci(hcd);
3296 vdev = xhci->devs[udev->slot_id];
3297
3298 /* Set up a configure endpoint command to remove the streams rings */
3299 spin_lock_irqsave(&xhci->lock, flags);
3300 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3301 udev, eps, num_eps);
3302 if (changed_ep_bitmask == 0) {
3303 spin_unlock_irqrestore(&xhci->lock, flags);
3304 return -EINVAL;
3305 }
3306
3307 /* Use the xhci_command structure from the first endpoint. We may have
3308 * allocated too many, but the driver may call xhci_free_streams() for
3309 * each endpoint it grouped into one call to xhci_alloc_streams().
3310 */
3311 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3312 command = vdev->eps[ep_index].stream_info->free_streams_command;
3313 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3314 if (!ctrl_ctx) {
3315 spin_unlock_irqrestore(&xhci->lock, flags);
3316 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3317 __func__);
3318 return -EINVAL;
3319 }
3320
3321 for (i = 0; i < num_eps; i++) {
3322 struct xhci_ep_ctx *ep_ctx;
3323
3324 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3325 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3326 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3327 EP_GETTING_NO_STREAMS;
3328
3329 xhci_endpoint_copy(xhci, command->in_ctx,
3330 vdev->out_ctx, ep_index);
3331 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3332 &vdev->eps[ep_index]);
3333 }
3334 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3335 vdev->out_ctx, ctrl_ctx,
3336 changed_ep_bitmask, changed_ep_bitmask);
3337 spin_unlock_irqrestore(&xhci->lock, flags);
3338
3339 /* Issue and wait for the configure endpoint command,
3340 * which must succeed.
3341 */
3342 ret = xhci_configure_endpoint(xhci, udev, command,
3343 false, true);
3344
3345 /* xHC rejected the configure endpoint command for some reason, so we
3346 * leave the streams rings intact.
3347 */
3348 if (ret < 0)
3349 return ret;
3350
3351 spin_lock_irqsave(&xhci->lock, flags);
3352 for (i = 0; i < num_eps; i++) {
3353 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3354 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3355 vdev->eps[ep_index].stream_info = NULL;
3356 /* FIXME Unset maxPstreams in endpoint context and
3357 * update deq ptr to point to normal string ring.
3358 */
3359 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3360 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3361 }
3362 spin_unlock_irqrestore(&xhci->lock, flags);
3363
3364 return 0;
3365}
3366
3367/*
3368 * Deletes endpoint resources for endpoints that were active before a Reset
3369 * Device command, or a Disable Slot command. The Reset Device command leaves
3370 * the control endpoint intact, whereas the Disable Slot command deletes it.
3371 *
3372 * Must be called with xhci->lock held.
3373 */
3374void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3375 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3376{
3377 int i;
3378 unsigned int num_dropped_eps = 0;
3379 unsigned int drop_flags = 0;
3380
3381 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3382 if (virt_dev->eps[i].ring) {
3383 drop_flags |= 1 << i;
3384 num_dropped_eps++;
3385 }
3386 }
3387 xhci->num_active_eps -= num_dropped_eps;
3388 if (num_dropped_eps)
3389 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3390 "Dropped %u ep ctxs, flags = 0x%x, "
3391 "%u now active.",
3392 num_dropped_eps, drop_flags,
3393 xhci->num_active_eps);
3394}
3395
3396/*
3397 * This submits a Reset Device Command, which will set the device state to 0,
3398 * set the device address to 0, and disable all the endpoints except the default
3399 * control endpoint. The USB core should come back and call
3400 * xhci_address_device(), and then re-set up the configuration. If this is
3401 * called because of a usb_reset_and_verify_device(), then the old alternate
3402 * settings will be re-installed through the normal bandwidth allocation
3403 * functions.
3404 *
3405 * Wait for the Reset Device command to finish. Remove all structures
3406 * associated with the endpoints that were disabled. Clear the input device
3407 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3408 *
3409 * If the virt_dev to be reset does not exist or does not match the udev,
3410 * it means the device is lost, possibly due to the xHC restore error and
3411 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3412 * re-allocate the device.
3413 */
3414int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3415{
3416 int ret, i;
3417 unsigned long flags;
3418 struct xhci_hcd *xhci;
3419 unsigned int slot_id;
3420 struct xhci_virt_device *virt_dev;
3421 struct xhci_command *reset_device_cmd;
3422 int last_freed_endpoint;
3423 struct xhci_slot_ctx *slot_ctx;
3424 int old_active_eps = 0;
3425
3426 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3427 if (ret <= 0)
3428 return ret;
3429 xhci = hcd_to_xhci(hcd);
3430 slot_id = udev->slot_id;
3431 virt_dev = xhci->devs[slot_id];
3432 if (!virt_dev) {
3433 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3434 "not exist. Re-allocate the device\n", slot_id);
3435 ret = xhci_alloc_dev(hcd, udev);
3436 if (ret == 1)
3437 return 0;
3438 else
3439 return -EINVAL;
3440 }
3441
3442 if (virt_dev->tt_info)
3443 old_active_eps = virt_dev->tt_info->active_eps;
3444
3445 if (virt_dev->udev != udev) {
3446 /* If the virt_dev and the udev does not match, this virt_dev
3447 * may belong to another udev.
3448 * Re-allocate the device.
3449 */
3450 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3451 "not match the udev. Re-allocate the device\n",
3452 slot_id);
3453 ret = xhci_alloc_dev(hcd, udev);
3454 if (ret == 1)
3455 return 0;
3456 else
3457 return -EINVAL;
3458 }
3459
3460 /* If device is not setup, there is no point in resetting it */
3461 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3462 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3463 SLOT_STATE_DISABLED)
3464 return 0;
3465
3466 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3467 /* Allocate the command structure that holds the struct completion.
3468 * Assume we're in process context, since the normal device reset
3469 * process has to wait for the device anyway. Storage devices are
3470 * reset as part of error handling, so use GFP_NOIO instead of
3471 * GFP_KERNEL.
3472 */
3473 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3474 if (!reset_device_cmd) {
3475 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3476 return -ENOMEM;
3477 }
3478
3479 /* Attempt to submit the Reset Device command to the command ring */
3480 spin_lock_irqsave(&xhci->lock, flags);
3481
3482 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3483 if (ret) {
3484 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3485 spin_unlock_irqrestore(&xhci->lock, flags);
3486 goto command_cleanup;
3487 }
3488 xhci_ring_cmd_db(xhci);
3489 spin_unlock_irqrestore(&xhci->lock, flags);
3490
3491 /* Wait for the Reset Device command to finish */
3492 wait_for_completion(reset_device_cmd->completion);
3493
3494 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3495 * unless we tried to reset a slot ID that wasn't enabled,
3496 * or the device wasn't in the addressed or configured state.
3497 */
3498 ret = reset_device_cmd->status;
3499 switch (ret) {
3500 case COMP_CMD_ABORT:
3501 case COMP_CMD_STOP:
3502 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3503 ret = -ETIME;
3504 goto command_cleanup;
3505 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3506 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3507 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3508 slot_id,
3509 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3510 xhci_dbg(xhci, "Not freeing device rings.\n");
3511 /* Don't treat this as an error. May change my mind later. */
3512 ret = 0;
3513 goto command_cleanup;
3514 case COMP_SUCCESS:
3515 xhci_dbg(xhci, "Successful reset device command.\n");
3516 break;
3517 default:
3518 if (xhci_is_vendor_info_code(xhci, ret))
3519 break;
3520 xhci_warn(xhci, "Unknown completion code %u for "
3521 "reset device command.\n", ret);
3522 ret = -EINVAL;
3523 goto command_cleanup;
3524 }
3525
3526 /* Free up host controller endpoint resources */
3527 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3528 spin_lock_irqsave(&xhci->lock, flags);
3529 /* Don't delete the default control endpoint resources */
3530 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3531 spin_unlock_irqrestore(&xhci->lock, flags);
3532 }
3533
3534 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3535 last_freed_endpoint = 1;
3536 for (i = 1; i < 31; ++i) {
3537 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3538
3539 if (ep->ep_state & EP_HAS_STREAMS) {
3540 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3541 xhci_get_endpoint_address(i));
3542 xhci_free_stream_info(xhci, ep->stream_info);
3543 ep->stream_info = NULL;
3544 ep->ep_state &= ~EP_HAS_STREAMS;
3545 }
3546
3547 if (ep->ring) {
3548 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3549 last_freed_endpoint = i;
3550 }
3551 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3552 xhci_drop_ep_from_interval_table(xhci,
3553 &virt_dev->eps[i].bw_info,
3554 virt_dev->bw_table,
3555 udev,
3556 &virt_dev->eps[i],
3557 virt_dev->tt_info);
3558 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3559 }
3560 /* If necessary, update the number of active TTs on this root port */
3561 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3562
3563 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3564 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3565 ret = 0;
3566
3567command_cleanup:
3568 xhci_free_command(xhci, reset_device_cmd);
3569 return ret;
3570}
3571
3572/*
3573 * At this point, the struct usb_device is about to go away, the device has
3574 * disconnected, and all traffic has been stopped and the endpoints have been
3575 * disabled. Free any HC data structures associated with that device.
3576 */
3577void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3578{
3579 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3580 struct xhci_virt_device *virt_dev;
3581 unsigned long flags;
3582 u32 state;
3583 int i, ret;
3584 struct xhci_command *command;
3585
3586 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3587 if (!command)
3588 return;
3589
3590#ifndef CONFIG_USB_DEFAULT_PERSIST
3591 /*
3592 * We called pm_runtime_get_noresume when the device was attached.
3593 * Decrement the counter here to allow controller to runtime suspend
3594 * if no devices remain.
3595 */
3596 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3597 pm_runtime_put_noidle(hcd->self.controller);
3598#endif
3599
3600 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3601 /* If the host is halted due to driver unload, we still need to free the
3602 * device.
3603 */
3604 if (ret <= 0 && ret != -ENODEV) {
3605 kfree(command);
3606 return;
3607 }
3608
3609 virt_dev = xhci->devs[udev->slot_id];
3610
3611 /* Stop any wayward timer functions (which may grab the lock) */
3612 for (i = 0; i < 31; ++i) {
3613 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3614 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3615 }
3616
3617 spin_lock_irqsave(&xhci->lock, flags);
3618 /* Don't disable the slot if the host controller is dead. */
3619 state = readl(&xhci->op_regs->status);
3620 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3621 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3622 xhci_free_virt_device(xhci, udev->slot_id);
3623 spin_unlock_irqrestore(&xhci->lock, flags);
3624 kfree(command);
3625 return;
3626 }
3627
3628 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3629 udev->slot_id)) {
3630 spin_unlock_irqrestore(&xhci->lock, flags);
3631 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3632 return;
3633 }
3634 xhci_ring_cmd_db(xhci);
3635 spin_unlock_irqrestore(&xhci->lock, flags);
3636
3637 /*
3638 * Event command completion handler will free any data structures
3639 * associated with the slot. XXX Can free sleep?
3640 */
3641}
3642
3643/*
3644 * Checks if we have enough host controller resources for the default control
3645 * endpoint.
3646 *
3647 * Must be called with xhci->lock held.
3648 */
3649static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3650{
3651 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3652 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3653 "Not enough ep ctxs: "
3654 "%u active, need to add 1, limit is %u.",
3655 xhci->num_active_eps, xhci->limit_active_eps);
3656 return -ENOMEM;
3657 }
3658 xhci->num_active_eps += 1;
3659 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3660 "Adding 1 ep ctx, %u now active.",
3661 xhci->num_active_eps);
3662 return 0;
3663}
3664
3665
3666/*
3667 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3668 * timed out, or allocating memory failed. Returns 1 on success.
3669 */
3670int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3671{
3672 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3673 unsigned long flags;
3674 int ret, slot_id;
3675 struct xhci_command *command;
3676
3677 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3678 if (!command)
3679 return 0;
3680
3681 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3682 mutex_lock(&xhci->mutex);
3683 spin_lock_irqsave(&xhci->lock, flags);
3684 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3685 if (ret) {
3686 spin_unlock_irqrestore(&xhci->lock, flags);
3687 mutex_unlock(&xhci->mutex);
3688 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3689 xhci_free_command(xhci, command);
3690 return 0;
3691 }
3692 xhci_ring_cmd_db(xhci);
3693 spin_unlock_irqrestore(&xhci->lock, flags);
3694
3695 wait_for_completion(command->completion);
3696 slot_id = command->slot_id;
3697 mutex_unlock(&xhci->mutex);
3698
3699 if (!slot_id || command->status != COMP_SUCCESS) {
3700 xhci_err(xhci, "Error while assigning device slot ID\n");
3701 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3702 HCS_MAX_SLOTS(
3703 readl(&xhci->cap_regs->hcs_params1)));
3704 xhci_free_command(xhci, command);
3705 return 0;
3706 }
3707
3708 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3709 spin_lock_irqsave(&xhci->lock, flags);
3710 ret = xhci_reserve_host_control_ep_resources(xhci);
3711 if (ret) {
3712 spin_unlock_irqrestore(&xhci->lock, flags);
3713 xhci_warn(xhci, "Not enough host resources, "
3714 "active endpoint contexts = %u\n",
3715 xhci->num_active_eps);
3716 goto disable_slot;
3717 }
3718 spin_unlock_irqrestore(&xhci->lock, flags);
3719 }
3720 /* Use GFP_NOIO, since this function can be called from
3721 * xhci_discover_or_reset_device(), which may be called as part of
3722 * mass storage driver error handling.
3723 */
3724 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3725 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3726 goto disable_slot;
3727 }
3728 udev->slot_id = slot_id;
3729
3730#ifndef CONFIG_USB_DEFAULT_PERSIST
3731 /*
3732 * If resetting upon resume, we can't put the controller into runtime
3733 * suspend if there is a device attached.
3734 */
3735 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3736 pm_runtime_get_noresume(hcd->self.controller);
3737#endif
3738
3739
3740 xhci_free_command(xhci, command);
3741 /* Is this a LS or FS device under a HS hub? */
3742 /* Hub or peripherial? */
3743 return 1;
3744
3745disable_slot:
3746 /* Disable slot, if we can do it without mem alloc */
3747 spin_lock_irqsave(&xhci->lock, flags);
3748 kfree(command->completion);
3749 command->completion = NULL;
3750 command->status = 0;
3751 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3752 udev->slot_id))
3753 xhci_ring_cmd_db(xhci);
3754 spin_unlock_irqrestore(&xhci->lock, flags);
3755 return 0;
3756}
3757
3758/*
3759 * Issue an Address Device command and optionally send a corresponding
3760 * SetAddress request to the device.
3761 */
3762static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3763 enum xhci_setup_dev setup)
3764{
3765 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3766 unsigned long flags;
3767 struct xhci_virt_device *virt_dev;
3768 int ret = 0;
3769 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3770 struct xhci_slot_ctx *slot_ctx;
3771 struct xhci_input_control_ctx *ctrl_ctx;
3772 u64 temp_64;
3773 struct xhci_command *command = NULL;
3774
3775 mutex_lock(&xhci->mutex);
3776
3777 if (xhci->xhc_state) { /* dying, removing or halted */
3778 ret = -ESHUTDOWN;
3779 goto out;
3780 }
3781
3782 if (!udev->slot_id) {
3783 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3784 "Bad Slot ID %d", udev->slot_id);
3785 ret = -EINVAL;
3786 goto out;
3787 }
3788
3789 virt_dev = xhci->devs[udev->slot_id];
3790
3791 if (WARN_ON(!virt_dev)) {
3792 /*
3793 * In plug/unplug torture test with an NEC controller,
3794 * a zero-dereference was observed once due to virt_dev = 0.
3795 * Print useful debug rather than crash if it is observed again!
3796 */
3797 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3798 udev->slot_id);
3799 ret = -EINVAL;
3800 goto out;
3801 }
3802
3803 if (setup == SETUP_CONTEXT_ONLY) {
3804 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3805 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3806 SLOT_STATE_DEFAULT) {
3807 xhci_dbg(xhci, "Slot already in default state\n");
3808 goto out;
3809 }
3810 }
3811
3812 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
3813 if (!command) {
3814 ret = -ENOMEM;
3815 goto out;
3816 }
3817
3818 command->in_ctx = virt_dev->in_ctx;
3819
3820 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3821 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3822 if (!ctrl_ctx) {
3823 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3824 __func__);
3825 ret = -EINVAL;
3826 goto out;
3827 }
3828 /*
3829 * If this is the first Set Address since device plug-in or
3830 * virt_device realloaction after a resume with an xHCI power loss,
3831 * then set up the slot context.
3832 */
3833 if (!slot_ctx->dev_info)
3834 xhci_setup_addressable_virt_dev(xhci, udev);
3835 /* Otherwise, update the control endpoint ring enqueue pointer. */
3836 else
3837 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3838 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3839 ctrl_ctx->drop_flags = 0;
3840
3841 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3842 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3843 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3844 le32_to_cpu(slot_ctx->dev_info) >> 27);
3845
3846 spin_lock_irqsave(&xhci->lock, flags);
3847 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3848 udev->slot_id, setup);
3849 if (ret) {
3850 spin_unlock_irqrestore(&xhci->lock, flags);
3851 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3852 "FIXME: allocate a command ring segment");
3853 goto out;
3854 }
3855 xhci_ring_cmd_db(xhci);
3856 spin_unlock_irqrestore(&xhci->lock, flags);
3857
3858 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3859 wait_for_completion(command->completion);
3860
3861 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3862 * the SetAddress() "recovery interval" required by USB and aborting the
3863 * command on a timeout.
3864 */
3865 switch (command->status) {
3866 case COMP_CMD_ABORT:
3867 case COMP_CMD_STOP:
3868 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3869 ret = -ETIME;
3870 break;
3871 case COMP_CTX_STATE:
3872 case COMP_EBADSLT:
3873 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3874 act, udev->slot_id);
3875 ret = -EINVAL;
3876 break;
3877 case COMP_TX_ERR:
3878 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3879 ret = -EPROTO;
3880 break;
3881 case COMP_DEV_ERR:
3882 dev_warn(&udev->dev,
3883 "ERROR: Incompatible device for setup %s command\n", act);
3884 ret = -ENODEV;
3885 break;
3886 case COMP_SUCCESS:
3887 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3888 "Successful setup %s command", act);
3889 break;
3890 default:
3891 xhci_err(xhci,
3892 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3893 act, command->status);
3894 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3895 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3896 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3897 ret = -EINVAL;
3898 break;
3899 }
3900 if (ret)
3901 goto out;
3902 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3903 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3904 "Op regs DCBAA ptr = %#016llx", temp_64);
3905 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3906 "Slot ID %d dcbaa entry @%p = %#016llx",
3907 udev->slot_id,
3908 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3909 (unsigned long long)
3910 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3911 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3912 "Output Context DMA address = %#08llx",
3913 (unsigned long long)virt_dev->out_ctx->dma);
3914 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3915 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3916 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3917 le32_to_cpu(slot_ctx->dev_info) >> 27);
3918 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3919 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3920 /*
3921 * USB core uses address 1 for the roothubs, so we add one to the
3922 * address given back to us by the HC.
3923 */
3924 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3925 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3926 le32_to_cpu(slot_ctx->dev_info) >> 27);
3927 /* Zero the input context control for later use */
3928 ctrl_ctx->add_flags = 0;
3929 ctrl_ctx->drop_flags = 0;
3930
3931 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3932 "Internal device address = %d",
3933 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3934out:
3935 mutex_unlock(&xhci->mutex);
3936 if (command) {
3937 kfree(command->completion);
3938 kfree(command);
3939 }
3940 return ret;
3941}
3942
3943int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3944{
3945 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3946}
3947
3948int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3949{
3950 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3951}
3952
3953/*
3954 * Transfer the port index into real index in the HW port status
3955 * registers. Caculate offset between the port's PORTSC register
3956 * and port status base. Divide the number of per port register
3957 * to get the real index. The raw port number bases 1.
3958 */
3959int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3960{
3961 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3962 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3963 __le32 __iomem *addr;
3964 int raw_port;
3965
3966 if (hcd->speed < HCD_USB3)
3967 addr = xhci->usb2_ports[port1 - 1];
3968 else
3969 addr = xhci->usb3_ports[port1 - 1];
3970
3971 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
3972 return raw_port;
3973}
3974
3975/*
3976 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3977 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3978 */
3979static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
3980 struct usb_device *udev, u16 max_exit_latency)
3981{
3982 struct xhci_virt_device *virt_dev;
3983 struct xhci_command *command;
3984 struct xhci_input_control_ctx *ctrl_ctx;
3985 struct xhci_slot_ctx *slot_ctx;
3986 unsigned long flags;
3987 int ret;
3988
3989 spin_lock_irqsave(&xhci->lock, flags);
3990
3991 virt_dev = xhci->devs[udev->slot_id];
3992
3993 /*
3994 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
3995 * xHC was re-initialized. Exit latency will be set later after
3996 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
3997 */
3998
3999 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4000 spin_unlock_irqrestore(&xhci->lock, flags);
4001 return 0;
4002 }
4003
4004 /* Attempt to issue an Evaluate Context command to change the MEL. */
4005 command = xhci->lpm_command;
4006 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4007 if (!ctrl_ctx) {
4008 spin_unlock_irqrestore(&xhci->lock, flags);
4009 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4010 __func__);
4011 return -ENOMEM;
4012 }
4013
4014 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4015 spin_unlock_irqrestore(&xhci->lock, flags);
4016
4017 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4018 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4019 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4020 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4021 slot_ctx->dev_state = 0;
4022
4023 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4024 "Set up evaluate context for LPM MEL change.");
4025 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4026 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4027
4028 /* Issue and wait for the evaluate context command. */
4029 ret = xhci_configure_endpoint(xhci, udev, command,
4030 true, true);
4031 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4032 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4033
4034 if (!ret) {
4035 spin_lock_irqsave(&xhci->lock, flags);
4036 virt_dev->current_mel = max_exit_latency;
4037 spin_unlock_irqrestore(&xhci->lock, flags);
4038 }
4039 return ret;
4040}
4041
4042#ifdef CONFIG_PM
4043
4044/* BESL to HIRD Encoding array for USB2 LPM */
4045static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4046 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4047
4048/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4049static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4050 struct usb_device *udev)
4051{
4052 int u2del, besl, besl_host;
4053 int besl_device = 0;
4054 u32 field;
4055
4056 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4057 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4058
4059 if (field & USB_BESL_SUPPORT) {
4060 for (besl_host = 0; besl_host < 16; besl_host++) {
4061 if (xhci_besl_encoding[besl_host] >= u2del)
4062 break;
4063 }
4064 /* Use baseline BESL value as default */
4065 if (field & USB_BESL_BASELINE_VALID)
4066 besl_device = USB_GET_BESL_BASELINE(field);
4067 else if (field & USB_BESL_DEEP_VALID)
4068 besl_device = USB_GET_BESL_DEEP(field);
4069 } else {
4070 if (u2del <= 50)
4071 besl_host = 0;
4072 else
4073 besl_host = (u2del - 51) / 75 + 1;
4074 }
4075
4076 besl = besl_host + besl_device;
4077 if (besl > 15)
4078 besl = 15;
4079
4080 return besl;
4081}
4082
4083/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4084static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4085{
4086 u32 field;
4087 int l1;
4088 int besld = 0;
4089 int hirdm = 0;
4090
4091 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4092
4093 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4094 l1 = udev->l1_params.timeout / 256;
4095
4096 /* device has preferred BESLD */
4097 if (field & USB_BESL_DEEP_VALID) {
4098 besld = USB_GET_BESL_DEEP(field);
4099 hirdm = 1;
4100 }
4101
4102 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4103}
4104
4105int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4106 struct usb_device *udev, int enable)
4107{
4108 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4109 __le32 __iomem **port_array;
4110 __le32 __iomem *pm_addr, *hlpm_addr;
4111 u32 pm_val, hlpm_val, field;
4112 unsigned int port_num;
4113 unsigned long flags;
4114 int hird, exit_latency;
4115 int ret;
4116
4117 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4118 !udev->lpm_capable)
4119 return -EPERM;
4120
4121 if (!udev->parent || udev->parent->parent ||
4122 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4123 return -EPERM;
4124
4125 if (udev->usb2_hw_lpm_capable != 1)
4126 return -EPERM;
4127
4128 spin_lock_irqsave(&xhci->lock, flags);
4129
4130 port_array = xhci->usb2_ports;
4131 port_num = udev->portnum - 1;
4132 pm_addr = port_array[port_num] + PORTPMSC;
4133 pm_val = readl(pm_addr);
4134 hlpm_addr = port_array[port_num] + PORTHLPMC;
4135 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4136
4137 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4138 enable ? "enable" : "disable", port_num + 1);
4139
4140 if (enable) {
4141 /* Host supports BESL timeout instead of HIRD */
4142 if (udev->usb2_hw_lpm_besl_capable) {
4143 /* if device doesn't have a preferred BESL value use a
4144 * default one which works with mixed HIRD and BESL
4145 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4146 */
4147 if ((field & USB_BESL_SUPPORT) &&
4148 (field & USB_BESL_BASELINE_VALID))
4149 hird = USB_GET_BESL_BASELINE(field);
4150 else
4151 hird = udev->l1_params.besl;
4152
4153 exit_latency = xhci_besl_encoding[hird];
4154 spin_unlock_irqrestore(&xhci->lock, flags);
4155
4156 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4157 * input context for link powermanagement evaluate
4158 * context commands. It is protected by hcd->bandwidth
4159 * mutex and is shared by all devices. We need to set
4160 * the max ext latency in USB 2 BESL LPM as well, so
4161 * use the same mutex and xhci_change_max_exit_latency()
4162 */
4163 mutex_lock(hcd->bandwidth_mutex);
4164 ret = xhci_change_max_exit_latency(xhci, udev,
4165 exit_latency);
4166 mutex_unlock(hcd->bandwidth_mutex);
4167
4168 if (ret < 0)
4169 return ret;
4170 spin_lock_irqsave(&xhci->lock, flags);
4171
4172 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4173 writel(hlpm_val, hlpm_addr);
4174 /* flush write */
4175 readl(hlpm_addr);
4176 } else {
4177 hird = xhci_calculate_hird_besl(xhci, udev);
4178 }
4179
4180 pm_val &= ~PORT_HIRD_MASK;
4181 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4182 writel(pm_val, pm_addr);
4183 pm_val = readl(pm_addr);
4184 pm_val |= PORT_HLE;
4185 writel(pm_val, pm_addr);
4186 /* flush write */
4187 readl(pm_addr);
4188 } else {
4189 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4190 writel(pm_val, pm_addr);
4191 /* flush write */
4192 readl(pm_addr);
4193 if (udev->usb2_hw_lpm_besl_capable) {
4194 spin_unlock_irqrestore(&xhci->lock, flags);
4195 mutex_lock(hcd->bandwidth_mutex);
4196 xhci_change_max_exit_latency(xhci, udev, 0);
4197 mutex_unlock(hcd->bandwidth_mutex);
4198 return 0;
4199 }
4200 }
4201
4202 spin_unlock_irqrestore(&xhci->lock, flags);
4203 return 0;
4204}
4205
4206/* check if a usb2 port supports a given extened capability protocol
4207 * only USB2 ports extended protocol capability values are cached.
4208 * Return 1 if capability is supported
4209 */
4210static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4211 unsigned capability)
4212{
4213 u32 port_offset, port_count;
4214 int i;
4215
4216 for (i = 0; i < xhci->num_ext_caps; i++) {
4217 if (xhci->ext_caps[i] & capability) {
4218 /* port offsets starts at 1 */
4219 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4220 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4221 if (port >= port_offset &&
4222 port < port_offset + port_count)
4223 return 1;
4224 }
4225 }
4226 return 0;
4227}
4228
4229int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4230{
4231 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4232 int portnum = udev->portnum - 1;
4233
4234 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4235 !udev->lpm_capable)
4236 return 0;
4237
4238 /* we only support lpm for non-hub device connected to root hub yet */
4239 if (!udev->parent || udev->parent->parent ||
4240 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4241 return 0;
4242
4243 if (xhci->hw_lpm_support == 1 &&
4244 xhci_check_usb2_port_capability(
4245 xhci, portnum, XHCI_HLC)) {
4246 udev->usb2_hw_lpm_capable = 1;
4247 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4248 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4249 if (xhci_check_usb2_port_capability(xhci, portnum,
4250 XHCI_BLC))
4251 udev->usb2_hw_lpm_besl_capable = 1;
4252 }
4253
4254 return 0;
4255}
4256
4257/*---------------------- USB 3.0 Link PM functions ------------------------*/
4258
4259/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4260static unsigned long long xhci_service_interval_to_ns(
4261 struct usb_endpoint_descriptor *desc)
4262{
4263 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4264}
4265
4266static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4267 enum usb3_link_state state)
4268{
4269 unsigned long long sel;
4270 unsigned long long pel;
4271 unsigned int max_sel_pel;
4272 char *state_name;
4273
4274 switch (state) {
4275 case USB3_LPM_U1:
4276 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4277 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4278 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4279 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4280 state_name = "U1";
4281 break;
4282 case USB3_LPM_U2:
4283 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4284 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4285 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4286 state_name = "U2";
4287 break;
4288 default:
4289 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4290 __func__);
4291 return USB3_LPM_DISABLED;
4292 }
4293
4294 if (sel <= max_sel_pel && pel <= max_sel_pel)
4295 return USB3_LPM_DEVICE_INITIATED;
4296
4297 if (sel > max_sel_pel)
4298 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4299 "due to long SEL %llu ms\n",
4300 state_name, sel);
4301 else
4302 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4303 "due to long PEL %llu ms\n",
4304 state_name, pel);
4305 return USB3_LPM_DISABLED;
4306}
4307
4308/* The U1 timeout should be the maximum of the following values:
4309 * - For control endpoints, U1 system exit latency (SEL) * 3
4310 * - For bulk endpoints, U1 SEL * 5
4311 * - For interrupt endpoints:
4312 * - Notification EPs, U1 SEL * 3
4313 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4314 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4315 */
4316static unsigned long long xhci_calculate_intel_u1_timeout(
4317 struct usb_device *udev,
4318 struct usb_endpoint_descriptor *desc)
4319{
4320 unsigned long long timeout_ns;
4321 int ep_type;
4322 int intr_type;
4323
4324 ep_type = usb_endpoint_type(desc);
4325 switch (ep_type) {
4326 case USB_ENDPOINT_XFER_CONTROL:
4327 timeout_ns = udev->u1_params.sel * 3;
4328 break;
4329 case USB_ENDPOINT_XFER_BULK:
4330 timeout_ns = udev->u1_params.sel * 5;
4331 break;
4332 case USB_ENDPOINT_XFER_INT:
4333 intr_type = usb_endpoint_interrupt_type(desc);
4334 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4335 timeout_ns = udev->u1_params.sel * 3;
4336 break;
4337 }
4338 /* Otherwise the calculation is the same as isoc eps */
4339 case USB_ENDPOINT_XFER_ISOC:
4340 timeout_ns = xhci_service_interval_to_ns(desc);
4341 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4342 if (timeout_ns < udev->u1_params.sel * 2)
4343 timeout_ns = udev->u1_params.sel * 2;
4344 break;
4345 default:
4346 return 0;
4347 }
4348
4349 return timeout_ns;
4350}
4351
4352/* Returns the hub-encoded U1 timeout value. */
4353static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4354 struct usb_device *udev,
4355 struct usb_endpoint_descriptor *desc)
4356{
4357 unsigned long long timeout_ns;
4358
4359 if (xhci->quirks & XHCI_INTEL_HOST)
4360 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4361 else
4362 timeout_ns = udev->u1_params.sel;
4363
4364 /* The U1 timeout is encoded in 1us intervals.
4365 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4366 */
4367 if (timeout_ns == USB3_LPM_DISABLED)
4368 timeout_ns = 1;
4369 else
4370 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4371
4372 /* If the necessary timeout value is bigger than what we can set in the
4373 * USB 3.0 hub, we have to disable hub-initiated U1.
4374 */
4375 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4376 return timeout_ns;
4377 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4378 "due to long timeout %llu ms\n", timeout_ns);
4379 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4380}
4381
4382/* The U2 timeout should be the maximum of:
4383 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4384 * - largest bInterval of any active periodic endpoint (to avoid going
4385 * into lower power link states between intervals).
4386 * - the U2 Exit Latency of the device
4387 */
4388static unsigned long long xhci_calculate_intel_u2_timeout(
4389 struct usb_device *udev,
4390 struct usb_endpoint_descriptor *desc)
4391{
4392 unsigned long long timeout_ns;
4393 unsigned long long u2_del_ns;
4394
4395 timeout_ns = 10 * 1000 * 1000;
4396
4397 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4398 (xhci_service_interval_to_ns(desc) > timeout_ns))
4399 timeout_ns = xhci_service_interval_to_ns(desc);
4400
4401 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4402 if (u2_del_ns > timeout_ns)
4403 timeout_ns = u2_del_ns;
4404
4405 return timeout_ns;
4406}
4407
4408/* Returns the hub-encoded U2 timeout value. */
4409static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4410 struct usb_device *udev,
4411 struct usb_endpoint_descriptor *desc)
4412{
4413 unsigned long long timeout_ns;
4414
4415 if (xhci->quirks & XHCI_INTEL_HOST)
4416 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4417 else
4418 timeout_ns = udev->u2_params.sel;
4419
4420 /* The U2 timeout is encoded in 256us intervals */
4421 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4422 /* If the necessary timeout value is bigger than what we can set in the
4423 * USB 3.0 hub, we have to disable hub-initiated U2.
4424 */
4425 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4426 return timeout_ns;
4427 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4428 "due to long timeout %llu ms\n", timeout_ns);
4429 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4430}
4431
4432static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4433 struct usb_device *udev,
4434 struct usb_endpoint_descriptor *desc,
4435 enum usb3_link_state state,
4436 u16 *timeout)
4437{
4438 if (state == USB3_LPM_U1)
4439 return xhci_calculate_u1_timeout(xhci, udev, desc);
4440 else if (state == USB3_LPM_U2)
4441 return xhci_calculate_u2_timeout(xhci, udev, desc);
4442
4443 return USB3_LPM_DISABLED;
4444}
4445
4446static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4447 struct usb_device *udev,
4448 struct usb_endpoint_descriptor *desc,
4449 enum usb3_link_state state,
4450 u16 *timeout)
4451{
4452 u16 alt_timeout;
4453
4454 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4455 desc, state, timeout);
4456
4457 /* If we found we can't enable hub-initiated LPM, or
4458 * the U1 or U2 exit latency was too high to allow
4459 * device-initiated LPM as well, just stop searching.
4460 */
4461 if (alt_timeout == USB3_LPM_DISABLED ||
4462 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4463 *timeout = alt_timeout;
4464 return -E2BIG;
4465 }
4466 if (alt_timeout > *timeout)
4467 *timeout = alt_timeout;
4468 return 0;
4469}
4470
4471static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4472 struct usb_device *udev,
4473 struct usb_host_interface *alt,
4474 enum usb3_link_state state,
4475 u16 *timeout)
4476{
4477 int j;
4478
4479 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4480 if (xhci_update_timeout_for_endpoint(xhci, udev,
4481 &alt->endpoint[j].desc, state, timeout))
4482 return -E2BIG;
4483 continue;
4484 }
4485 return 0;
4486}
4487
4488static int xhci_check_intel_tier_policy(struct usb_device *udev,
4489 enum usb3_link_state state)
4490{
4491 struct usb_device *parent;
4492 unsigned int num_hubs;
4493
4494 if (state == USB3_LPM_U2)
4495 return 0;
4496
4497 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4498 for (parent = udev->parent, num_hubs = 0; parent->parent;
4499 parent = parent->parent)
4500 num_hubs++;
4501
4502 if (num_hubs < 2)
4503 return 0;
4504
4505 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4506 " below second-tier hub.\n");
4507 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4508 "to decrease power consumption.\n");
4509 return -E2BIG;
4510}
4511
4512static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4513 struct usb_device *udev,
4514 enum usb3_link_state state)
4515{
4516 if (xhci->quirks & XHCI_INTEL_HOST)
4517 return xhci_check_intel_tier_policy(udev, state);
4518 else
4519 return 0;
4520}
4521
4522/* Returns the U1 or U2 timeout that should be enabled.
4523 * If the tier check or timeout setting functions return with a non-zero exit
4524 * code, that means the timeout value has been finalized and we shouldn't look
4525 * at any more endpoints.
4526 */
4527static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4528 struct usb_device *udev, enum usb3_link_state state)
4529{
4530 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4531 struct usb_host_config *config;
4532 char *state_name;
4533 int i;
4534 u16 timeout = USB3_LPM_DISABLED;
4535
4536 if (state == USB3_LPM_U1)
4537 state_name = "U1";
4538 else if (state == USB3_LPM_U2)
4539 state_name = "U2";
4540 else {
4541 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4542 state);
4543 return timeout;
4544 }
4545
4546 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4547 return timeout;
4548
4549 /* Gather some information about the currently installed configuration
4550 * and alternate interface settings.
4551 */
4552 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4553 state, &timeout))
4554 return timeout;
4555
4556 config = udev->actconfig;
4557 if (!config)
4558 return timeout;
4559
4560 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4561 struct usb_driver *driver;
4562 struct usb_interface *intf = config->interface[i];
4563
4564 if (!intf)
4565 continue;
4566
4567 /* Check if any currently bound drivers want hub-initiated LPM
4568 * disabled.
4569 */
4570 if (intf->dev.driver) {
4571 driver = to_usb_driver(intf->dev.driver);
4572 if (driver && driver->disable_hub_initiated_lpm) {
4573 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4574 "at request of driver %s\n",
4575 state_name, driver->name);
4576 return xhci_get_timeout_no_hub_lpm(udev, state);
4577 }
4578 }
4579
4580 /* Not sure how this could happen... */
4581 if (!intf->cur_altsetting)
4582 continue;
4583
4584 if (xhci_update_timeout_for_interface(xhci, udev,
4585 intf->cur_altsetting,
4586 state, &timeout))
4587 return timeout;
4588 }
4589 return timeout;
4590}
4591
4592static int calculate_max_exit_latency(struct usb_device *udev,
4593 enum usb3_link_state state_changed,
4594 u16 hub_encoded_timeout)
4595{
4596 unsigned long long u1_mel_us = 0;
4597 unsigned long long u2_mel_us = 0;
4598 unsigned long long mel_us = 0;
4599 bool disabling_u1;
4600 bool disabling_u2;
4601 bool enabling_u1;
4602 bool enabling_u2;
4603
4604 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4605 hub_encoded_timeout == USB3_LPM_DISABLED);
4606 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4607 hub_encoded_timeout == USB3_LPM_DISABLED);
4608
4609 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4610 hub_encoded_timeout != USB3_LPM_DISABLED);
4611 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4612 hub_encoded_timeout != USB3_LPM_DISABLED);
4613
4614 /* If U1 was already enabled and we're not disabling it,
4615 * or we're going to enable U1, account for the U1 max exit latency.
4616 */
4617 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4618 enabling_u1)
4619 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4620 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4621 enabling_u2)
4622 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4623
4624 if (u1_mel_us > u2_mel_us)
4625 mel_us = u1_mel_us;
4626 else
4627 mel_us = u2_mel_us;
4628 /* xHCI host controller max exit latency field is only 16 bits wide. */
4629 if (mel_us > MAX_EXIT) {
4630 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4631 "is too big.\n", mel_us);
4632 return -E2BIG;
4633 }
4634 return mel_us;
4635}
4636
4637/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4638int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4639 struct usb_device *udev, enum usb3_link_state state)
4640{
4641 struct xhci_hcd *xhci;
4642 u16 hub_encoded_timeout;
4643 int mel;
4644 int ret;
4645
4646 xhci = hcd_to_xhci(hcd);
4647 /* The LPM timeout values are pretty host-controller specific, so don't
4648 * enable hub-initiated timeouts unless the vendor has provided
4649 * information about their timeout algorithm.
4650 */
4651 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4652 !xhci->devs[udev->slot_id])
4653 return USB3_LPM_DISABLED;
4654
4655 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4656 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4657 if (mel < 0) {
4658 /* Max Exit Latency is too big, disable LPM. */
4659 hub_encoded_timeout = USB3_LPM_DISABLED;
4660 mel = 0;
4661 }
4662
4663 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4664 if (ret)
4665 return ret;
4666 return hub_encoded_timeout;
4667}
4668
4669int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4670 struct usb_device *udev, enum usb3_link_state state)
4671{
4672 struct xhci_hcd *xhci;
4673 u16 mel;
4674
4675 xhci = hcd_to_xhci(hcd);
4676 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4677 !xhci->devs[udev->slot_id])
4678 return 0;
4679
4680 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4681 return xhci_change_max_exit_latency(xhci, udev, mel);
4682}
4683#else /* CONFIG_PM */
4684
4685int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4686 struct usb_device *udev, int enable)
4687{
4688 return 0;
4689}
4690
4691int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4692{
4693 return 0;
4694}
4695
4696int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4697 struct usb_device *udev, enum usb3_link_state state)
4698{
4699 return USB3_LPM_DISABLED;
4700}
4701
4702int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4703 struct usb_device *udev, enum usb3_link_state state)
4704{
4705 return 0;
4706}
4707#endif /* CONFIG_PM */
4708
4709/*-------------------------------------------------------------------------*/
4710
4711/* Once a hub descriptor is fetched for a device, we need to update the xHC's
4712 * internal data structures for the device.
4713 */
4714int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4715 struct usb_tt *tt, gfp_t mem_flags)
4716{
4717 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4718 struct xhci_virt_device *vdev;
4719 struct xhci_command *config_cmd;
4720 struct xhci_input_control_ctx *ctrl_ctx;
4721 struct xhci_slot_ctx *slot_ctx;
4722 unsigned long flags;
4723 unsigned think_time;
4724 int ret;
4725
4726 /* Ignore root hubs */
4727 if (!hdev->parent)
4728 return 0;
4729
4730 vdev = xhci->devs[hdev->slot_id];
4731 if (!vdev) {
4732 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4733 return -EINVAL;
4734 }
4735 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4736 if (!config_cmd) {
4737 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4738 return -ENOMEM;
4739 }
4740 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4741 if (!ctrl_ctx) {
4742 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4743 __func__);
4744 xhci_free_command(xhci, config_cmd);
4745 return -ENOMEM;
4746 }
4747
4748 spin_lock_irqsave(&xhci->lock, flags);
4749 if (hdev->speed == USB_SPEED_HIGH &&
4750 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4751 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4752 xhci_free_command(xhci, config_cmd);
4753 spin_unlock_irqrestore(&xhci->lock, flags);
4754 return -ENOMEM;
4755 }
4756
4757 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4758 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4759 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4760 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4761 /*
4762 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4763 * but it may be already set to 1 when setup an xHCI virtual
4764 * device, so clear it anyway.
4765 */
4766 if (tt->multi)
4767 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4768 else if (hdev->speed == USB_SPEED_FULL)
4769 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4770
4771 if (xhci->hci_version > 0x95) {
4772 xhci_dbg(xhci, "xHCI version %x needs hub "
4773 "TT think time and number of ports\n",
4774 (unsigned int) xhci->hci_version);
4775 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4776 /* Set TT think time - convert from ns to FS bit times.
4777 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4778 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4779 *
4780 * xHCI 1.0: this field shall be 0 if the device is not a
4781 * High-spped hub.
4782 */
4783 think_time = tt->think_time;
4784 if (think_time != 0)
4785 think_time = (think_time / 666) - 1;
4786 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4787 slot_ctx->tt_info |=
4788 cpu_to_le32(TT_THINK_TIME(think_time));
4789 } else {
4790 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4791 "TT think time or number of ports\n",
4792 (unsigned int) xhci->hci_version);
4793 }
4794 slot_ctx->dev_state = 0;
4795 spin_unlock_irqrestore(&xhci->lock, flags);
4796
4797 xhci_dbg(xhci, "Set up %s for hub device.\n",
4798 (xhci->hci_version > 0x95) ?
4799 "configure endpoint" : "evaluate context");
4800 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4801 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4802
4803 /* Issue and wait for the configure endpoint or
4804 * evaluate context command.
4805 */
4806 if (xhci->hci_version > 0x95)
4807 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4808 false, false);
4809 else
4810 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4811 true, false);
4812
4813 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4814 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4815
4816 xhci_free_command(xhci, config_cmd);
4817 return ret;
4818}
4819
4820int xhci_get_frame(struct usb_hcd *hcd)
4821{
4822 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4823 /* EHCI mods by the periodic size. Why? */
4824 return readl(&xhci->run_regs->microframe_index) >> 3;
4825}
4826
4827int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4828{
4829 struct xhci_hcd *xhci;
4830 struct device *dev = hcd->self.controller;
4831 int retval;
4832
4833 /* Accept arbitrarily long scatter-gather lists */
4834 hcd->self.sg_tablesize = ~0;
4835
4836 /* support to build packet from discontinuous buffers */
4837 hcd->self.no_sg_constraint = 1;
4838
4839 /* XHCI controllers don't stop the ep queue on short packets :| */
4840 hcd->self.no_stop_on_short = 1;
4841
4842 xhci = hcd_to_xhci(hcd);
4843
4844 if (usb_hcd_is_primary_hcd(hcd)) {
4845 xhci->main_hcd = hcd;
4846 /* Mark the first roothub as being USB 2.0.
4847 * The xHCI driver will register the USB 3.0 roothub.
4848 */
4849 hcd->speed = HCD_USB2;
4850 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4851 /*
4852 * USB 2.0 roothub under xHCI has an integrated TT,
4853 * (rate matching hub) as opposed to having an OHCI/UHCI
4854 * companion controller.
4855 */
4856 hcd->has_tt = 1;
4857 } else {
4858 if (xhci->sbrn == 0x31) {
4859 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4860 hcd->speed = HCD_USB31;
4861 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4862 }
4863 /* xHCI private pointer was set in xhci_pci_probe for the second
4864 * registered roothub.
4865 */
4866 return 0;
4867 }
4868
4869 mutex_init(&xhci->mutex);
4870 xhci->cap_regs = hcd->regs;
4871 xhci->op_regs = hcd->regs +
4872 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4873 xhci->run_regs = hcd->regs +
4874 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4875 /* Cache read-only capability registers */
4876 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4877 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4878 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4879 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4880 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4881 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4882 if (xhci->hci_version > 0x100)
4883 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4884 xhci_print_registers(xhci);
4885
4886 xhci->quirks |= quirks;
4887
4888 get_quirks(dev, xhci);
4889
4890 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4891 * success event after a short transfer. This quirk will ignore such
4892 * spurious event.
4893 */
4894 if (xhci->hci_version > 0x96)
4895 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4896
4897 /* Make sure the HC is halted. */
4898 retval = xhci_halt(xhci);
4899 if (retval)
4900 return retval;
4901
4902 xhci_dbg(xhci, "Resetting HCD\n");
4903 /* Reset the internal HC memory state and registers. */
4904 retval = xhci_reset(xhci);
4905 if (retval)
4906 return retval;
4907 xhci_dbg(xhci, "Reset complete\n");
4908
4909 /*
4910 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4911 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4912 * address memory pointers actually. So, this driver clears the AC64
4913 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4914 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4915 */
4916 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
4917 xhci->hcc_params &= ~BIT(0);
4918
4919 /* Set dma_mask and coherent_dma_mask to 64-bits,
4920 * if xHC supports 64-bit addressing */
4921 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4922 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4923 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4924 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4925 } else {
4926 /*
4927 * This is to avoid error in cases where a 32-bit USB
4928 * controller is used on a 64-bit capable system.
4929 */
4930 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4931 if (retval)
4932 return retval;
4933 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4934 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4935 }
4936
4937 xhci_dbg(xhci, "Calling HCD init\n");
4938 /* Initialize HCD and host controller data structures. */
4939 retval = xhci_init(hcd);
4940 if (retval)
4941 return retval;
4942 xhci_dbg(xhci, "Called HCD init\n");
4943
4944 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4945 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4946
4947 return 0;
4948}
4949EXPORT_SYMBOL_GPL(xhci_gen_setup);
4950
4951static const struct hc_driver xhci_hc_driver = {
4952 .description = "xhci-hcd",
4953 .product_desc = "xHCI Host Controller",
4954 .hcd_priv_size = sizeof(struct xhci_hcd),
4955
4956 /*
4957 * generic hardware linkage
4958 */
4959 .irq = xhci_irq,
4960 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4961
4962 /*
4963 * basic lifecycle operations
4964 */
4965 .reset = NULL, /* set in xhci_init_driver() */
4966 .start = xhci_run,
4967 .stop = xhci_stop,
4968 .shutdown = xhci_shutdown,
4969
4970 /*
4971 * managing i/o requests and associated device resources
4972 */
4973 .urb_enqueue = xhci_urb_enqueue,
4974 .urb_dequeue = xhci_urb_dequeue,
4975 .alloc_dev = xhci_alloc_dev,
4976 .free_dev = xhci_free_dev,
4977 .alloc_streams = xhci_alloc_streams,
4978 .free_streams = xhci_free_streams,
4979 .add_endpoint = xhci_add_endpoint,
4980 .drop_endpoint = xhci_drop_endpoint,
4981 .endpoint_reset = xhci_endpoint_reset,
4982 .check_bandwidth = xhci_check_bandwidth,
4983 .reset_bandwidth = xhci_reset_bandwidth,
4984 .address_device = xhci_address_device,
4985 .enable_device = xhci_enable_device,
4986 .update_hub_device = xhci_update_hub_device,
4987 .reset_device = xhci_discover_or_reset_device,
4988
4989 /*
4990 * scheduling support
4991 */
4992 .get_frame_number = xhci_get_frame,
4993
4994 /*
4995 * root hub support
4996 */
4997 .hub_control = xhci_hub_control,
4998 .hub_status_data = xhci_hub_status_data,
4999 .bus_suspend = xhci_bus_suspend,
5000 .bus_resume = xhci_bus_resume,
5001
5002 /*
5003 * call back when device connected and addressed
5004 */
5005 .update_device = xhci_update_device,
5006 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5007 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5008 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5009 .find_raw_port_number = xhci_find_raw_port_number,
5010};
5011
5012void xhci_init_driver(struct hc_driver *drv,
5013 const struct xhci_driver_overrides *over)
5014{
5015 BUG_ON(!over);
5016
5017 /* Copy the generic table to drv then apply the overrides */
5018 *drv = xhci_hc_driver;
5019
5020 if (over) {
5021 drv->hcd_priv_size += over->extra_priv_size;
5022 if (over->reset)
5023 drv->reset = over->reset;
5024 if (over->start)
5025 drv->start = over->start;
5026 }
5027}
5028EXPORT_SYMBOL_GPL(xhci_init_driver);
5029
5030MODULE_DESCRIPTION(DRIVER_DESC);
5031MODULE_AUTHOR(DRIVER_AUTHOR);
5032MODULE_LICENSE("GPL");
5033
5034static int __init xhci_hcd_init(void)
5035{
5036 /*
5037 * Check the compiler generated sizes of structures that must be laid
5038 * out in specific ways for hardware access.
5039 */
5040 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5041 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5042 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5043 /* xhci_device_control has eight fields, and also
5044 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5045 */
5046 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5047 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5048 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5049 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5050 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5051 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5052 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5053
5054 if (usb_disabled())
5055 return -ENODEV;
5056
5057 return 0;
5058}
5059
5060/*
5061 * If an init function is provided, an exit function must also be provided
5062 * to allow module unload.
5063 */
5064static void __exit xhci_hcd_fini(void) { }
5065
5066module_init(xhci_hcd_init);
5067module_exit(xhci_hcd_fini);