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1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33#define SUPPORT_SYSRQ
34#endif
35
36#include <linux/module.h>
37#include <linux/ioport.h>
38#include <linux/init.h>
39#include <linux/console.h>
40#include <linux/sysrq.h>
41#include <linux/device.h>
42#include <linux/tty.h>
43#include <linux/tty_flip.h>
44#include <linux/serial_core.h>
45#include <linux/serial.h>
46#include <linux/amba/bus.h>
47#include <linux/amba/serial.h>
48#include <linux/clk.h>
49#include <linux/slab.h>
50#include <linux/dmaengine.h>
51#include <linux/dma-mapping.h>
52#include <linux/scatterlist.h>
53#include <linux/delay.h>
54
55#include <asm/io.h>
56#include <asm/sizes.h>
57
58#define UART_NR 14
59
60#define SERIAL_AMBA_MAJOR 204
61#define SERIAL_AMBA_MINOR 64
62#define SERIAL_AMBA_NR UART_NR
63
64#define AMBA_ISR_PASS_LIMIT 256
65
66#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
67#define UART_DUMMY_DR_RX (1 << 16)
68
69
70#define UART_WA_SAVE_NR 14
71
72static void pl011_lockup_wa(unsigned long data);
73static const u32 uart_wa_reg[UART_WA_SAVE_NR] = {
74 ST_UART011_DMAWM,
75 ST_UART011_TIMEOUT,
76 ST_UART011_LCRH_RX,
77 UART011_IBRD,
78 UART011_FBRD,
79 ST_UART011_LCRH_TX,
80 UART011_IFLS,
81 ST_UART011_XFCR,
82 ST_UART011_XON1,
83 ST_UART011_XON2,
84 ST_UART011_XOFF1,
85 ST_UART011_XOFF2,
86 UART011_CR,
87 UART011_IMSC
88};
89
90static u32 uart_wa_regdata[UART_WA_SAVE_NR];
91static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0);
92
93/* There is by now at least one vendor with differing details, so handle it */
94struct vendor_data {
95 unsigned int ifls;
96 unsigned int fifosize;
97 unsigned int lcrh_tx;
98 unsigned int lcrh_rx;
99 bool oversampling;
100 bool interrupt_may_hang; /* vendor-specific */
101 bool dma_threshold;
102};
103
104static struct vendor_data vendor_arm = {
105 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
106 .fifosize = 16,
107 .lcrh_tx = UART011_LCRH,
108 .lcrh_rx = UART011_LCRH,
109 .oversampling = false,
110 .dma_threshold = false,
111};
112
113static struct vendor_data vendor_st = {
114 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
115 .fifosize = 64,
116 .lcrh_tx = ST_UART011_LCRH_TX,
117 .lcrh_rx = ST_UART011_LCRH_RX,
118 .oversampling = true,
119 .interrupt_may_hang = true,
120 .dma_threshold = true,
121};
122
123static struct uart_amba_port *amba_ports[UART_NR];
124
125/* Deals with DMA transactions */
126
127struct pl011_sgbuf {
128 struct scatterlist sg;
129 char *buf;
130};
131
132struct pl011_dmarx_data {
133 struct dma_chan *chan;
134 struct completion complete;
135 bool use_buf_b;
136 struct pl011_sgbuf sgbuf_a;
137 struct pl011_sgbuf sgbuf_b;
138 dma_cookie_t cookie;
139 bool running;
140};
141
142struct pl011_dmatx_data {
143 struct dma_chan *chan;
144 struct scatterlist sg;
145 char *buf;
146 bool queued;
147};
148
149/*
150 * We wrap our port structure around the generic uart_port.
151 */
152struct uart_amba_port {
153 struct uart_port port;
154 struct clk *clk;
155 const struct vendor_data *vendor;
156 unsigned int dmacr; /* dma control reg */
157 unsigned int im; /* interrupt mask */
158 unsigned int old_status;
159 unsigned int fifosize; /* vendor-specific */
160 unsigned int lcrh_tx; /* vendor-specific */
161 unsigned int lcrh_rx; /* vendor-specific */
162 bool autorts;
163 char type[12];
164 bool interrupt_may_hang; /* vendor-specific */
165#ifdef CONFIG_DMA_ENGINE
166 /* DMA stuff */
167 bool using_tx_dma;
168 bool using_rx_dma;
169 struct pl011_dmarx_data dmarx;
170 struct pl011_dmatx_data dmatx;
171#endif
172};
173
174/*
175 * Reads up to 256 characters from the FIFO or until it's empty and
176 * inserts them into the TTY layer. Returns the number of characters
177 * read from the FIFO.
178 */
179static int pl011_fifo_to_tty(struct uart_amba_port *uap)
180{
181 u16 status, ch;
182 unsigned int flag, max_count = 256;
183 int fifotaken = 0;
184
185 while (max_count--) {
186 status = readw(uap->port.membase + UART01x_FR);
187 if (status & UART01x_FR_RXFE)
188 break;
189
190 /* Take chars from the FIFO and update status */
191 ch = readw(uap->port.membase + UART01x_DR) |
192 UART_DUMMY_DR_RX;
193 flag = TTY_NORMAL;
194 uap->port.icount.rx++;
195 fifotaken++;
196
197 if (unlikely(ch & UART_DR_ERROR)) {
198 if (ch & UART011_DR_BE) {
199 ch &= ~(UART011_DR_FE | UART011_DR_PE);
200 uap->port.icount.brk++;
201 if (uart_handle_break(&uap->port))
202 continue;
203 } else if (ch & UART011_DR_PE)
204 uap->port.icount.parity++;
205 else if (ch & UART011_DR_FE)
206 uap->port.icount.frame++;
207 if (ch & UART011_DR_OE)
208 uap->port.icount.overrun++;
209
210 ch &= uap->port.read_status_mask;
211
212 if (ch & UART011_DR_BE)
213 flag = TTY_BREAK;
214 else if (ch & UART011_DR_PE)
215 flag = TTY_PARITY;
216 else if (ch & UART011_DR_FE)
217 flag = TTY_FRAME;
218 }
219
220 if (uart_handle_sysrq_char(&uap->port, ch & 255))
221 continue;
222
223 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
224 }
225
226 return fifotaken;
227}
228
229
230/*
231 * All the DMA operation mode stuff goes inside this ifdef.
232 * This assumes that you have a generic DMA device interface,
233 * no custom DMA interfaces are supported.
234 */
235#ifdef CONFIG_DMA_ENGINE
236
237#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
238
239static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
240 enum dma_data_direction dir)
241{
242 sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
243 if (!sg->buf)
244 return -ENOMEM;
245
246 sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
247
248 if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
249 kfree(sg->buf);
250 return -EINVAL;
251 }
252 return 0;
253}
254
255static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
256 enum dma_data_direction dir)
257{
258 if (sg->buf) {
259 dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
260 kfree(sg->buf);
261 }
262}
263
264static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
265{
266 /* DMA is the sole user of the platform data right now */
267 struct amba_pl011_data *plat = uap->port.dev->platform_data;
268 struct dma_slave_config tx_conf = {
269 .dst_addr = uap->port.mapbase + UART01x_DR,
270 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
271 .direction = DMA_TO_DEVICE,
272 .dst_maxburst = uap->fifosize >> 1,
273 };
274 struct dma_chan *chan;
275 dma_cap_mask_t mask;
276
277 /* We need platform data */
278 if (!plat || !plat->dma_filter) {
279 dev_info(uap->port.dev, "no DMA platform data\n");
280 return;
281 }
282
283 /* Try to acquire a generic DMA engine slave TX channel */
284 dma_cap_zero(mask);
285 dma_cap_set(DMA_SLAVE, mask);
286
287 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
288 if (!chan) {
289 dev_err(uap->port.dev, "no TX DMA channel!\n");
290 return;
291 }
292
293 dmaengine_slave_config(chan, &tx_conf);
294 uap->dmatx.chan = chan;
295
296 dev_info(uap->port.dev, "DMA channel TX %s\n",
297 dma_chan_name(uap->dmatx.chan));
298
299 /* Optionally make use of an RX channel as well */
300 if (plat->dma_rx_param) {
301 struct dma_slave_config rx_conf = {
302 .src_addr = uap->port.mapbase + UART01x_DR,
303 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
304 .direction = DMA_FROM_DEVICE,
305 .src_maxburst = uap->fifosize >> 1,
306 };
307
308 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
309 if (!chan) {
310 dev_err(uap->port.dev, "no RX DMA channel!\n");
311 return;
312 }
313
314 dmaengine_slave_config(chan, &rx_conf);
315 uap->dmarx.chan = chan;
316
317 dev_info(uap->port.dev, "DMA channel RX %s\n",
318 dma_chan_name(uap->dmarx.chan));
319 }
320}
321
322#ifndef MODULE
323/*
324 * Stack up the UARTs and let the above initcall be done at device
325 * initcall time, because the serial driver is called as an arch
326 * initcall, and at this time the DMA subsystem is not yet registered.
327 * At this point the driver will switch over to using DMA where desired.
328 */
329struct dma_uap {
330 struct list_head node;
331 struct uart_amba_port *uap;
332};
333
334static LIST_HEAD(pl011_dma_uarts);
335
336static int __init pl011_dma_initcall(void)
337{
338 struct list_head *node, *tmp;
339
340 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
341 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
342 pl011_dma_probe_initcall(dmau->uap);
343 list_del(node);
344 kfree(dmau);
345 }
346 return 0;
347}
348
349device_initcall(pl011_dma_initcall);
350
351static void pl011_dma_probe(struct uart_amba_port *uap)
352{
353 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
354 if (dmau) {
355 dmau->uap = uap;
356 list_add_tail(&dmau->node, &pl011_dma_uarts);
357 }
358}
359#else
360static void pl011_dma_probe(struct uart_amba_port *uap)
361{
362 pl011_dma_probe_initcall(uap);
363}
364#endif
365
366static void pl011_dma_remove(struct uart_amba_port *uap)
367{
368 /* TODO: remove the initcall if it has not yet executed */
369 if (uap->dmatx.chan)
370 dma_release_channel(uap->dmatx.chan);
371 if (uap->dmarx.chan)
372 dma_release_channel(uap->dmarx.chan);
373}
374
375/* Forward declare this for the refill routine */
376static int pl011_dma_tx_refill(struct uart_amba_port *uap);
377
378/*
379 * The current DMA TX buffer has been sent.
380 * Try to queue up another DMA buffer.
381 */
382static void pl011_dma_tx_callback(void *data)
383{
384 struct uart_amba_port *uap = data;
385 struct pl011_dmatx_data *dmatx = &uap->dmatx;
386 unsigned long flags;
387 u16 dmacr;
388
389 spin_lock_irqsave(&uap->port.lock, flags);
390 if (uap->dmatx.queued)
391 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
392 DMA_TO_DEVICE);
393
394 dmacr = uap->dmacr;
395 uap->dmacr = dmacr & ~UART011_TXDMAE;
396 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
397
398 /*
399 * If TX DMA was disabled, it means that we've stopped the DMA for
400 * some reason (eg, XOFF received, or we want to send an X-char.)
401 *
402 * Note: we need to be careful here of a potential race between DMA
403 * and the rest of the driver - if the driver disables TX DMA while
404 * a TX buffer completing, we must update the tx queued status to
405 * get further refills (hence we check dmacr).
406 */
407 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
408 uart_circ_empty(&uap->port.state->xmit)) {
409 uap->dmatx.queued = false;
410 spin_unlock_irqrestore(&uap->port.lock, flags);
411 return;
412 }
413
414 if (pl011_dma_tx_refill(uap) <= 0) {
415 /*
416 * We didn't queue a DMA buffer for some reason, but we
417 * have data pending to be sent. Re-enable the TX IRQ.
418 */
419 uap->im |= UART011_TXIM;
420 writew(uap->im, uap->port.membase + UART011_IMSC);
421 }
422 spin_unlock_irqrestore(&uap->port.lock, flags);
423}
424
425/*
426 * Try to refill the TX DMA buffer.
427 * Locking: called with port lock held and IRQs disabled.
428 * Returns:
429 * 1 if we queued up a TX DMA buffer.
430 * 0 if we didn't want to handle this by DMA
431 * <0 on error
432 */
433static int pl011_dma_tx_refill(struct uart_amba_port *uap)
434{
435 struct pl011_dmatx_data *dmatx = &uap->dmatx;
436 struct dma_chan *chan = dmatx->chan;
437 struct dma_device *dma_dev = chan->device;
438 struct dma_async_tx_descriptor *desc;
439 struct circ_buf *xmit = &uap->port.state->xmit;
440 unsigned int count;
441
442 /*
443 * Try to avoid the overhead involved in using DMA if the
444 * transaction fits in the first half of the FIFO, by using
445 * the standard interrupt handling. This ensures that we
446 * issue a uart_write_wakeup() at the appropriate time.
447 */
448 count = uart_circ_chars_pending(xmit);
449 if (count < (uap->fifosize >> 1)) {
450 uap->dmatx.queued = false;
451 return 0;
452 }
453
454 /*
455 * Bodge: don't send the last character by DMA, as this
456 * will prevent XON from notifying us to restart DMA.
457 */
458 count -= 1;
459
460 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
461 if (count > PL011_DMA_BUFFER_SIZE)
462 count = PL011_DMA_BUFFER_SIZE;
463
464 if (xmit->tail < xmit->head)
465 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
466 else {
467 size_t first = UART_XMIT_SIZE - xmit->tail;
468 size_t second = xmit->head;
469
470 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
471 if (second)
472 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
473 }
474
475 dmatx->sg.length = count;
476
477 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
478 uap->dmatx.queued = false;
479 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
480 return -EBUSY;
481 }
482
483 desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_TO_DEVICE,
484 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
485 if (!desc) {
486 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
487 uap->dmatx.queued = false;
488 /*
489 * If DMA cannot be used right now, we complete this
490 * transaction via IRQ and let the TTY layer retry.
491 */
492 dev_dbg(uap->port.dev, "TX DMA busy\n");
493 return -EBUSY;
494 }
495
496 /* Some data to go along to the callback */
497 desc->callback = pl011_dma_tx_callback;
498 desc->callback_param = uap;
499
500 /* All errors should happen at prepare time */
501 dmaengine_submit(desc);
502
503 /* Fire the DMA transaction */
504 dma_dev->device_issue_pending(chan);
505
506 uap->dmacr |= UART011_TXDMAE;
507 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
508 uap->dmatx.queued = true;
509
510 /*
511 * Now we know that DMA will fire, so advance the ring buffer
512 * with the stuff we just dispatched.
513 */
514 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
515 uap->port.icount.tx += count;
516
517 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
518 uart_write_wakeup(&uap->port);
519
520 return 1;
521}
522
523/*
524 * We received a transmit interrupt without a pending X-char but with
525 * pending characters.
526 * Locking: called with port lock held and IRQs disabled.
527 * Returns:
528 * false if we want to use PIO to transmit
529 * true if we queued a DMA buffer
530 */
531static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
532{
533 if (!uap->using_tx_dma)
534 return false;
535
536 /*
537 * If we already have a TX buffer queued, but received a
538 * TX interrupt, it will be because we've just sent an X-char.
539 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
540 */
541 if (uap->dmatx.queued) {
542 uap->dmacr |= UART011_TXDMAE;
543 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
544 uap->im &= ~UART011_TXIM;
545 writew(uap->im, uap->port.membase + UART011_IMSC);
546 return true;
547 }
548
549 /*
550 * We don't have a TX buffer queued, so try to queue one.
551 * If we successfully queued a buffer, mask the TX IRQ.
552 */
553 if (pl011_dma_tx_refill(uap) > 0) {
554 uap->im &= ~UART011_TXIM;
555 writew(uap->im, uap->port.membase + UART011_IMSC);
556 return true;
557 }
558 return false;
559}
560
561/*
562 * Stop the DMA transmit (eg, due to received XOFF).
563 * Locking: called with port lock held and IRQs disabled.
564 */
565static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
566{
567 if (uap->dmatx.queued) {
568 uap->dmacr &= ~UART011_TXDMAE;
569 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
570 }
571}
572
573/*
574 * Try to start a DMA transmit, or in the case of an XON/OFF
575 * character queued for send, try to get that character out ASAP.
576 * Locking: called with port lock held and IRQs disabled.
577 * Returns:
578 * false if we want the TX IRQ to be enabled
579 * true if we have a buffer queued
580 */
581static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
582{
583 u16 dmacr;
584
585 if (!uap->using_tx_dma)
586 return false;
587
588 if (!uap->port.x_char) {
589 /* no X-char, try to push chars out in DMA mode */
590 bool ret = true;
591
592 if (!uap->dmatx.queued) {
593 if (pl011_dma_tx_refill(uap) > 0) {
594 uap->im &= ~UART011_TXIM;
595 ret = true;
596 } else {
597 uap->im |= UART011_TXIM;
598 ret = false;
599 }
600 writew(uap->im, uap->port.membase + UART011_IMSC);
601 } else if (!(uap->dmacr & UART011_TXDMAE)) {
602 uap->dmacr |= UART011_TXDMAE;
603 writew(uap->dmacr,
604 uap->port.membase + UART011_DMACR);
605 }
606 return ret;
607 }
608
609 /*
610 * We have an X-char to send. Disable DMA to prevent it loading
611 * the TX fifo, and then see if we can stuff it into the FIFO.
612 */
613 dmacr = uap->dmacr;
614 uap->dmacr &= ~UART011_TXDMAE;
615 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
616
617 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
618 /*
619 * No space in the FIFO, so enable the transmit interrupt
620 * so we know when there is space. Note that once we've
621 * loaded the character, we should just re-enable DMA.
622 */
623 return false;
624 }
625
626 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
627 uap->port.icount.tx++;
628 uap->port.x_char = 0;
629
630 /* Success - restore the DMA state */
631 uap->dmacr = dmacr;
632 writew(dmacr, uap->port.membase + UART011_DMACR);
633
634 return true;
635}
636
637/*
638 * Flush the transmit buffer.
639 * Locking: called with port lock held and IRQs disabled.
640 */
641static void pl011_dma_flush_buffer(struct uart_port *port)
642{
643 struct uart_amba_port *uap = (struct uart_amba_port *)port;
644
645 if (!uap->using_tx_dma)
646 return;
647
648 /* Avoid deadlock with the DMA engine callback */
649 spin_unlock(&uap->port.lock);
650 dmaengine_terminate_all(uap->dmatx.chan);
651 spin_lock(&uap->port.lock);
652 if (uap->dmatx.queued) {
653 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
654 DMA_TO_DEVICE);
655 uap->dmatx.queued = false;
656 uap->dmacr &= ~UART011_TXDMAE;
657 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
658 }
659}
660
661static void pl011_dma_rx_callback(void *data);
662
663static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
664{
665 struct dma_chan *rxchan = uap->dmarx.chan;
666 struct dma_device *dma_dev;
667 struct pl011_dmarx_data *dmarx = &uap->dmarx;
668 struct dma_async_tx_descriptor *desc;
669 struct pl011_sgbuf *sgbuf;
670
671 if (!rxchan)
672 return -EIO;
673
674 /* Start the RX DMA job */
675 sgbuf = uap->dmarx.use_buf_b ?
676 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
677 dma_dev = rxchan->device;
678 desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1,
679 DMA_FROM_DEVICE,
680 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
681 /*
682 * If the DMA engine is busy and cannot prepare a
683 * channel, no big deal, the driver will fall back
684 * to interrupt mode as a result of this error code.
685 */
686 if (!desc) {
687 uap->dmarx.running = false;
688 dmaengine_terminate_all(rxchan);
689 return -EBUSY;
690 }
691
692 /* Some data to go along to the callback */
693 desc->callback = pl011_dma_rx_callback;
694 desc->callback_param = uap;
695 dmarx->cookie = dmaengine_submit(desc);
696 dma_async_issue_pending(rxchan);
697
698 uap->dmacr |= UART011_RXDMAE;
699 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
700 uap->dmarx.running = true;
701
702 uap->im &= ~UART011_RXIM;
703 writew(uap->im, uap->port.membase + UART011_IMSC);
704
705 return 0;
706}
707
708/*
709 * This is called when either the DMA job is complete, or
710 * the FIFO timeout interrupt occurred. This must be called
711 * with the port spinlock uap->port.lock held.
712 */
713static void pl011_dma_rx_chars(struct uart_amba_port *uap,
714 u32 pending, bool use_buf_b,
715 bool readfifo)
716{
717 struct tty_struct *tty = uap->port.state->port.tty;
718 struct pl011_sgbuf *sgbuf = use_buf_b ?
719 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
720 struct device *dev = uap->dmarx.chan->device->dev;
721 int dma_count = 0;
722 u32 fifotaken = 0; /* only used for vdbg() */
723
724 /* Pick everything from the DMA first */
725 if (pending) {
726 /* Sync in buffer */
727 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
728
729 /*
730 * First take all chars in the DMA pipe, then look in the FIFO.
731 * Note that tty_insert_flip_buf() tries to take as many chars
732 * as it can.
733 */
734 dma_count = tty_insert_flip_string(uap->port.state->port.tty,
735 sgbuf->buf, pending);
736
737 /* Return buffer to device */
738 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
739
740 uap->port.icount.rx += dma_count;
741 if (dma_count < pending)
742 dev_warn(uap->port.dev,
743 "couldn't insert all characters (TTY is full?)\n");
744 }
745
746 /*
747 * Only continue with trying to read the FIFO if all DMA chars have
748 * been taken first.
749 */
750 if (dma_count == pending && readfifo) {
751 /* Clear any error flags */
752 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
753 uap->port.membase + UART011_ICR);
754
755 /*
756 * If we read all the DMA'd characters, and we had an
757 * incomplete buffer, that could be due to an rx error, or
758 * maybe we just timed out. Read any pending chars and check
759 * the error status.
760 *
761 * Error conditions will only occur in the FIFO, these will
762 * trigger an immediate interrupt and stop the DMA job, so we
763 * will always find the error in the FIFO, never in the DMA
764 * buffer.
765 */
766 fifotaken = pl011_fifo_to_tty(uap);
767 }
768
769 spin_unlock(&uap->port.lock);
770 dev_vdbg(uap->port.dev,
771 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
772 dma_count, fifotaken);
773 tty_flip_buffer_push(tty);
774 spin_lock(&uap->port.lock);
775}
776
777static void pl011_dma_rx_irq(struct uart_amba_port *uap)
778{
779 struct pl011_dmarx_data *dmarx = &uap->dmarx;
780 struct dma_chan *rxchan = dmarx->chan;
781 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
782 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
783 size_t pending;
784 struct dma_tx_state state;
785 enum dma_status dmastat;
786
787 /*
788 * Pause the transfer so we can trust the current counter,
789 * do this before we pause the PL011 block, else we may
790 * overflow the FIFO.
791 */
792 if (dmaengine_pause(rxchan))
793 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
794 dmastat = rxchan->device->device_tx_status(rxchan,
795 dmarx->cookie, &state);
796 if (dmastat != DMA_PAUSED)
797 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
798
799 /* Disable RX DMA - incoming data will wait in the FIFO */
800 uap->dmacr &= ~UART011_RXDMAE;
801 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
802 uap->dmarx.running = false;
803
804 pending = sgbuf->sg.length - state.residue;
805 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
806 /* Then we terminate the transfer - we now know our residue */
807 dmaengine_terminate_all(rxchan);
808
809 /*
810 * This will take the chars we have so far and insert
811 * into the framework.
812 */
813 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
814
815 /* Switch buffer & re-trigger DMA job */
816 dmarx->use_buf_b = !dmarx->use_buf_b;
817 if (pl011_dma_rx_trigger_dma(uap)) {
818 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
819 "fall back to interrupt mode\n");
820 uap->im |= UART011_RXIM;
821 writew(uap->im, uap->port.membase + UART011_IMSC);
822 }
823}
824
825static void pl011_dma_rx_callback(void *data)
826{
827 struct uart_amba_port *uap = data;
828 struct pl011_dmarx_data *dmarx = &uap->dmarx;
829 bool lastbuf = dmarx->use_buf_b;
830 int ret;
831
832 /*
833 * This completion interrupt occurs typically when the
834 * RX buffer is totally stuffed but no timeout has yet
835 * occurred. When that happens, we just want the RX
836 * routine to flush out the secondary DMA buffer while
837 * we immediately trigger the next DMA job.
838 */
839 spin_lock_irq(&uap->port.lock);
840 uap->dmarx.running = false;
841 dmarx->use_buf_b = !lastbuf;
842 ret = pl011_dma_rx_trigger_dma(uap);
843
844 pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false);
845 spin_unlock_irq(&uap->port.lock);
846 /*
847 * Do this check after we picked the DMA chars so we don't
848 * get some IRQ immediately from RX.
849 */
850 if (ret) {
851 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
852 "fall back to interrupt mode\n");
853 uap->im |= UART011_RXIM;
854 writew(uap->im, uap->port.membase + UART011_IMSC);
855 }
856}
857
858/*
859 * Stop accepting received characters, when we're shutting down or
860 * suspending this port.
861 * Locking: called with port lock held and IRQs disabled.
862 */
863static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
864{
865 /* FIXME. Just disable the DMA enable */
866 uap->dmacr &= ~UART011_RXDMAE;
867 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
868}
869
870static void pl011_dma_startup(struct uart_amba_port *uap)
871{
872 int ret;
873
874 if (!uap->dmatx.chan)
875 return;
876
877 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
878 if (!uap->dmatx.buf) {
879 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
880 uap->port.fifosize = uap->fifosize;
881 return;
882 }
883
884 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
885
886 /* The DMA buffer is now the FIFO the TTY subsystem can use */
887 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
888 uap->using_tx_dma = true;
889
890 if (!uap->dmarx.chan)
891 goto skip_rx;
892
893 /* Allocate and map DMA RX buffers */
894 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
895 DMA_FROM_DEVICE);
896 if (ret) {
897 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
898 "RX buffer A", ret);
899 goto skip_rx;
900 }
901
902 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
903 DMA_FROM_DEVICE);
904 if (ret) {
905 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
906 "RX buffer B", ret);
907 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
908 DMA_FROM_DEVICE);
909 goto skip_rx;
910 }
911
912 uap->using_rx_dma = true;
913
914skip_rx:
915 /* Turn on DMA error (RX/TX will be enabled on demand) */
916 uap->dmacr |= UART011_DMAONERR;
917 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
918
919 /*
920 * ST Micro variants has some specific dma burst threshold
921 * compensation. Set this to 16 bytes, so burst will only
922 * be issued above/below 16 bytes.
923 */
924 if (uap->vendor->dma_threshold)
925 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
926 uap->port.membase + ST_UART011_DMAWM);
927
928 if (uap->using_rx_dma) {
929 if (pl011_dma_rx_trigger_dma(uap))
930 dev_dbg(uap->port.dev, "could not trigger initial "
931 "RX DMA job, fall back to interrupt mode\n");
932 }
933}
934
935static void pl011_dma_shutdown(struct uart_amba_port *uap)
936{
937 if (!(uap->using_tx_dma || uap->using_rx_dma))
938 return;
939
940 /* Disable RX and TX DMA */
941 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
942 barrier();
943
944 spin_lock_irq(&uap->port.lock);
945 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
946 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
947 spin_unlock_irq(&uap->port.lock);
948
949 if (uap->using_tx_dma) {
950 /* In theory, this should already be done by pl011_dma_flush_buffer */
951 dmaengine_terminate_all(uap->dmatx.chan);
952 if (uap->dmatx.queued) {
953 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
954 DMA_TO_DEVICE);
955 uap->dmatx.queued = false;
956 }
957
958 kfree(uap->dmatx.buf);
959 uap->using_tx_dma = false;
960 }
961
962 if (uap->using_rx_dma) {
963 dmaengine_terminate_all(uap->dmarx.chan);
964 /* Clean up the RX DMA */
965 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
966 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
967 uap->using_rx_dma = false;
968 }
969}
970
971static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
972{
973 return uap->using_rx_dma;
974}
975
976static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
977{
978 return uap->using_rx_dma && uap->dmarx.running;
979}
980
981
982#else
983/* Blank functions if the DMA engine is not available */
984static inline void pl011_dma_probe(struct uart_amba_port *uap)
985{
986}
987
988static inline void pl011_dma_remove(struct uart_amba_port *uap)
989{
990}
991
992static inline void pl011_dma_startup(struct uart_amba_port *uap)
993{
994}
995
996static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
997{
998}
999
1000static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1001{
1002 return false;
1003}
1004
1005static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1006{
1007}
1008
1009static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1010{
1011 return false;
1012}
1013
1014static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1015{
1016}
1017
1018static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1019{
1020}
1021
1022static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1023{
1024 return -EIO;
1025}
1026
1027static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1028{
1029 return false;
1030}
1031
1032static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1033{
1034 return false;
1035}
1036
1037#define pl011_dma_flush_buffer NULL
1038#endif
1039
1040
1041/*
1042 * pl011_lockup_wa
1043 * This workaround aims to break the deadlock situation
1044 * when after long transfer over uart in hardware flow
1045 * control, uart interrupt registers cannot be cleared.
1046 * Hence uart transfer gets blocked.
1047 *
1048 * It is seen that during such deadlock condition ICR
1049 * don't get cleared even on multiple write. This leads
1050 * pass_counter to decrease and finally reach zero. This
1051 * can be taken as trigger point to run this UART_BT_WA.
1052 *
1053 */
1054static void pl011_lockup_wa(unsigned long data)
1055{
1056 struct uart_amba_port *uap = amba_ports[0];
1057 void __iomem *base = uap->port.membase;
1058 struct circ_buf *xmit = &uap->port.state->xmit;
1059 struct tty_struct *tty = uap->port.state->port.tty;
1060 int buf_empty_retries = 200;
1061 int loop;
1062
1063 /* Stop HCI layer from submitting data for tx */
1064 tty->hw_stopped = 1;
1065 while (!uart_circ_empty(xmit)) {
1066 if (buf_empty_retries-- == 0)
1067 break;
1068 udelay(100);
1069 }
1070
1071 /* Backup registers */
1072 for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
1073 uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]);
1074
1075 /* Disable UART so that FIFO data is flushed out */
1076 writew(0x00, uap->port.membase + UART011_CR);
1077
1078 /* Soft reset UART module */
1079 if (uap->port.dev->platform_data) {
1080 struct amba_pl011_data *plat;
1081
1082 plat = uap->port.dev->platform_data;
1083 if (plat->reset)
1084 plat->reset();
1085 }
1086
1087 /* Restore registers */
1088 for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
1089 writew(uart_wa_regdata[loop] ,
1090 uap->port.membase + uart_wa_reg[loop]);
1091
1092 /* Initialise the old status of the modem signals */
1093 uap->old_status = readw(uap->port.membase + UART01x_FR) &
1094 UART01x_FR_MODEM_ANY;
1095
1096 if (readl(base + UART011_MIS) & 0x2)
1097 printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n");
1098
1099 /* Start Tx/Rx */
1100 tty->hw_stopped = 0;
1101}
1102
1103static void pl011_stop_tx(struct uart_port *port)
1104{
1105 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1106
1107 uap->im &= ~UART011_TXIM;
1108 writew(uap->im, uap->port.membase + UART011_IMSC);
1109 pl011_dma_tx_stop(uap);
1110}
1111
1112static void pl011_start_tx(struct uart_port *port)
1113{
1114 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1115
1116 if (!pl011_dma_tx_start(uap)) {
1117 uap->im |= UART011_TXIM;
1118 writew(uap->im, uap->port.membase + UART011_IMSC);
1119 }
1120}
1121
1122static void pl011_stop_rx(struct uart_port *port)
1123{
1124 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1125
1126 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1127 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1128 writew(uap->im, uap->port.membase + UART011_IMSC);
1129
1130 pl011_dma_rx_stop(uap);
1131}
1132
1133static void pl011_enable_ms(struct uart_port *port)
1134{
1135 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1136
1137 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1138 writew(uap->im, uap->port.membase + UART011_IMSC);
1139}
1140
1141static void pl011_rx_chars(struct uart_amba_port *uap)
1142{
1143 struct tty_struct *tty = uap->port.state->port.tty;
1144
1145 pl011_fifo_to_tty(uap);
1146
1147 spin_unlock(&uap->port.lock);
1148 tty_flip_buffer_push(tty);
1149 /*
1150 * If we were temporarily out of DMA mode for a while,
1151 * attempt to switch back to DMA mode again.
1152 */
1153 if (pl011_dma_rx_available(uap)) {
1154 if (pl011_dma_rx_trigger_dma(uap)) {
1155 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1156 "fall back to interrupt mode again\n");
1157 uap->im |= UART011_RXIM;
1158 } else
1159 uap->im &= ~UART011_RXIM;
1160 writew(uap->im, uap->port.membase + UART011_IMSC);
1161 }
1162 spin_lock(&uap->port.lock);
1163}
1164
1165static void pl011_tx_chars(struct uart_amba_port *uap)
1166{
1167 struct circ_buf *xmit = &uap->port.state->xmit;
1168 int count;
1169
1170 if (uap->port.x_char) {
1171 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1172 uap->port.icount.tx++;
1173 uap->port.x_char = 0;
1174 return;
1175 }
1176 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1177 pl011_stop_tx(&uap->port);
1178 return;
1179 }
1180
1181 /* If we are using DMA mode, try to send some characters. */
1182 if (pl011_dma_tx_irq(uap))
1183 return;
1184
1185 count = uap->fifosize >> 1;
1186 do {
1187 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1188 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1189 uap->port.icount.tx++;
1190 if (uart_circ_empty(xmit))
1191 break;
1192 } while (--count > 0);
1193
1194 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1195 uart_write_wakeup(&uap->port);
1196
1197 if (uart_circ_empty(xmit))
1198 pl011_stop_tx(&uap->port);
1199}
1200
1201static void pl011_modem_status(struct uart_amba_port *uap)
1202{
1203 unsigned int status, delta;
1204
1205 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1206
1207 delta = status ^ uap->old_status;
1208 uap->old_status = status;
1209
1210 if (!delta)
1211 return;
1212
1213 if (delta & UART01x_FR_DCD)
1214 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1215
1216 if (delta & UART01x_FR_DSR)
1217 uap->port.icount.dsr++;
1218
1219 if (delta & UART01x_FR_CTS)
1220 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1221
1222 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1223}
1224
1225static irqreturn_t pl011_int(int irq, void *dev_id)
1226{
1227 struct uart_amba_port *uap = dev_id;
1228 unsigned long flags;
1229 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1230 int handled = 0;
1231
1232 spin_lock_irqsave(&uap->port.lock, flags);
1233
1234 status = readw(uap->port.membase + UART011_MIS);
1235 if (status) {
1236 do {
1237 writew(status & ~(UART011_TXIS|UART011_RTIS|
1238 UART011_RXIS),
1239 uap->port.membase + UART011_ICR);
1240
1241 if (status & (UART011_RTIS|UART011_RXIS)) {
1242 if (pl011_dma_rx_running(uap))
1243 pl011_dma_rx_irq(uap);
1244 else
1245 pl011_rx_chars(uap);
1246 }
1247 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1248 UART011_CTSMIS|UART011_RIMIS))
1249 pl011_modem_status(uap);
1250 if (status & UART011_TXIS)
1251 pl011_tx_chars(uap);
1252
1253 if (pass_counter-- == 0) {
1254 if (uap->interrupt_may_hang)
1255 tasklet_schedule(&pl011_lockup_tlet);
1256 break;
1257 }
1258
1259 status = readw(uap->port.membase + UART011_MIS);
1260 } while (status != 0);
1261 handled = 1;
1262 }
1263
1264 spin_unlock_irqrestore(&uap->port.lock, flags);
1265
1266 return IRQ_RETVAL(handled);
1267}
1268
1269static unsigned int pl01x_tx_empty(struct uart_port *port)
1270{
1271 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1272 unsigned int status = readw(uap->port.membase + UART01x_FR);
1273 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1274}
1275
1276static unsigned int pl01x_get_mctrl(struct uart_port *port)
1277{
1278 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1279 unsigned int result = 0;
1280 unsigned int status = readw(uap->port.membase + UART01x_FR);
1281
1282#define TIOCMBIT(uartbit, tiocmbit) \
1283 if (status & uartbit) \
1284 result |= tiocmbit
1285
1286 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1287 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1288 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1289 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1290#undef TIOCMBIT
1291 return result;
1292}
1293
1294static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1295{
1296 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1297 unsigned int cr;
1298
1299 cr = readw(uap->port.membase + UART011_CR);
1300
1301#define TIOCMBIT(tiocmbit, uartbit) \
1302 if (mctrl & tiocmbit) \
1303 cr |= uartbit; \
1304 else \
1305 cr &= ~uartbit
1306
1307 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1308 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1309 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1310 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1311 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1312
1313 if (uap->autorts) {
1314 /* We need to disable auto-RTS if we want to turn RTS off */
1315 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1316 }
1317#undef TIOCMBIT
1318
1319 writew(cr, uap->port.membase + UART011_CR);
1320}
1321
1322static void pl011_break_ctl(struct uart_port *port, int break_state)
1323{
1324 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1325 unsigned long flags;
1326 unsigned int lcr_h;
1327
1328 spin_lock_irqsave(&uap->port.lock, flags);
1329 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1330 if (break_state == -1)
1331 lcr_h |= UART01x_LCRH_BRK;
1332 else
1333 lcr_h &= ~UART01x_LCRH_BRK;
1334 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1335 spin_unlock_irqrestore(&uap->port.lock, flags);
1336}
1337
1338#ifdef CONFIG_CONSOLE_POLL
1339static int pl010_get_poll_char(struct uart_port *port)
1340{
1341 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1342 unsigned int status;
1343
1344 status = readw(uap->port.membase + UART01x_FR);
1345 if (status & UART01x_FR_RXFE)
1346 return NO_POLL_CHAR;
1347
1348 return readw(uap->port.membase + UART01x_DR);
1349}
1350
1351static void pl010_put_poll_char(struct uart_port *port,
1352 unsigned char ch)
1353{
1354 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1355
1356 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1357 barrier();
1358
1359 writew(ch, uap->port.membase + UART01x_DR);
1360}
1361
1362#endif /* CONFIG_CONSOLE_POLL */
1363
1364static int pl011_startup(struct uart_port *port)
1365{
1366 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1367 unsigned int cr;
1368 int retval;
1369
1370 /*
1371 * Try to enable the clock producer.
1372 */
1373 retval = clk_enable(uap->clk);
1374 if (retval)
1375 goto out;
1376
1377 uap->port.uartclk = clk_get_rate(uap->clk);
1378
1379 /*
1380 * Allocate the IRQ
1381 */
1382 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1383 if (retval)
1384 goto clk_dis;
1385
1386 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1387
1388 /*
1389 * Provoke TX FIFO interrupt into asserting.
1390 */
1391 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1392 writew(cr, uap->port.membase + UART011_CR);
1393 writew(0, uap->port.membase + UART011_FBRD);
1394 writew(1, uap->port.membase + UART011_IBRD);
1395 writew(0, uap->port.membase + uap->lcrh_rx);
1396 if (uap->lcrh_tx != uap->lcrh_rx) {
1397 int i;
1398 /*
1399 * Wait 10 PCLKs before writing LCRH_TX register,
1400 * to get this delay write read only register 10 times
1401 */
1402 for (i = 0; i < 10; ++i)
1403 writew(0xff, uap->port.membase + UART011_MIS);
1404 writew(0, uap->port.membase + uap->lcrh_tx);
1405 }
1406 writew(0, uap->port.membase + UART01x_DR);
1407 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1408 barrier();
1409
1410 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1411 writew(cr, uap->port.membase + UART011_CR);
1412
1413 /* Clear pending error interrupts */
1414 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
1415 uap->port.membase + UART011_ICR);
1416
1417 /*
1418 * initialise the old status of the modem signals
1419 */
1420 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1421
1422 /* Startup DMA */
1423 pl011_dma_startup(uap);
1424
1425 /*
1426 * Finally, enable interrupts, only timeouts when using DMA
1427 * if initial RX DMA job failed, start in interrupt mode
1428 * as well.
1429 */
1430 spin_lock_irq(&uap->port.lock);
1431 uap->im = UART011_RTIM;
1432 if (!pl011_dma_rx_running(uap))
1433 uap->im |= UART011_RXIM;
1434 writew(uap->im, uap->port.membase + UART011_IMSC);
1435 spin_unlock_irq(&uap->port.lock);
1436
1437 if (uap->port.dev->platform_data) {
1438 struct amba_pl011_data *plat;
1439
1440 plat = uap->port.dev->platform_data;
1441 if (plat->init)
1442 plat->init();
1443 }
1444
1445 return 0;
1446
1447 clk_dis:
1448 clk_disable(uap->clk);
1449 out:
1450 return retval;
1451}
1452
1453static void pl011_shutdown_channel(struct uart_amba_port *uap,
1454 unsigned int lcrh)
1455{
1456 unsigned long val;
1457
1458 val = readw(uap->port.membase + lcrh);
1459 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1460 writew(val, uap->port.membase + lcrh);
1461}
1462
1463static void pl011_shutdown(struct uart_port *port)
1464{
1465 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1466
1467 /*
1468 * disable all interrupts
1469 */
1470 spin_lock_irq(&uap->port.lock);
1471 uap->im = 0;
1472 writew(uap->im, uap->port.membase + UART011_IMSC);
1473 writew(0xffff, uap->port.membase + UART011_ICR);
1474 spin_unlock_irq(&uap->port.lock);
1475
1476 pl011_dma_shutdown(uap);
1477
1478 /*
1479 * Free the interrupt
1480 */
1481 free_irq(uap->port.irq, uap);
1482
1483 /*
1484 * disable the port
1485 */
1486 uap->autorts = false;
1487 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
1488
1489 /*
1490 * disable break condition and fifos
1491 */
1492 pl011_shutdown_channel(uap, uap->lcrh_rx);
1493 if (uap->lcrh_rx != uap->lcrh_tx)
1494 pl011_shutdown_channel(uap, uap->lcrh_tx);
1495
1496 /*
1497 * Shut down the clock producer
1498 */
1499 clk_disable(uap->clk);
1500
1501 if (uap->port.dev->platform_data) {
1502 struct amba_pl011_data *plat;
1503
1504 plat = uap->port.dev->platform_data;
1505 if (plat->exit)
1506 plat->exit();
1507 }
1508
1509}
1510
1511static void
1512pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1513 struct ktermios *old)
1514{
1515 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1516 unsigned int lcr_h, old_cr;
1517 unsigned long flags;
1518 unsigned int baud, quot, clkdiv;
1519
1520 if (uap->vendor->oversampling)
1521 clkdiv = 8;
1522 else
1523 clkdiv = 16;
1524
1525 /*
1526 * Ask the core to calculate the divisor for us.
1527 */
1528 baud = uart_get_baud_rate(port, termios, old, 0,
1529 port->uartclk / clkdiv);
1530
1531 if (baud > port->uartclk/16)
1532 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1533 else
1534 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1535
1536 switch (termios->c_cflag & CSIZE) {
1537 case CS5:
1538 lcr_h = UART01x_LCRH_WLEN_5;
1539 break;
1540 case CS6:
1541 lcr_h = UART01x_LCRH_WLEN_6;
1542 break;
1543 case CS7:
1544 lcr_h = UART01x_LCRH_WLEN_7;
1545 break;
1546 default: // CS8
1547 lcr_h = UART01x_LCRH_WLEN_8;
1548 break;
1549 }
1550 if (termios->c_cflag & CSTOPB)
1551 lcr_h |= UART01x_LCRH_STP2;
1552 if (termios->c_cflag & PARENB) {
1553 lcr_h |= UART01x_LCRH_PEN;
1554 if (!(termios->c_cflag & PARODD))
1555 lcr_h |= UART01x_LCRH_EPS;
1556 }
1557 if (uap->fifosize > 1)
1558 lcr_h |= UART01x_LCRH_FEN;
1559
1560 spin_lock_irqsave(&port->lock, flags);
1561
1562 /*
1563 * Update the per-port timeout.
1564 */
1565 uart_update_timeout(port, termios->c_cflag, baud);
1566
1567 port->read_status_mask = UART011_DR_OE | 255;
1568 if (termios->c_iflag & INPCK)
1569 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1570 if (termios->c_iflag & (BRKINT | PARMRK))
1571 port->read_status_mask |= UART011_DR_BE;
1572
1573 /*
1574 * Characters to ignore
1575 */
1576 port->ignore_status_mask = 0;
1577 if (termios->c_iflag & IGNPAR)
1578 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1579 if (termios->c_iflag & IGNBRK) {
1580 port->ignore_status_mask |= UART011_DR_BE;
1581 /*
1582 * If we're ignoring parity and break indicators,
1583 * ignore overruns too (for real raw support).
1584 */
1585 if (termios->c_iflag & IGNPAR)
1586 port->ignore_status_mask |= UART011_DR_OE;
1587 }
1588
1589 /*
1590 * Ignore all characters if CREAD is not set.
1591 */
1592 if ((termios->c_cflag & CREAD) == 0)
1593 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1594
1595 if (UART_ENABLE_MS(port, termios->c_cflag))
1596 pl011_enable_ms(port);
1597
1598 /* first, disable everything */
1599 old_cr = readw(port->membase + UART011_CR);
1600 writew(0, port->membase + UART011_CR);
1601
1602 if (termios->c_cflag & CRTSCTS) {
1603 if (old_cr & UART011_CR_RTS)
1604 old_cr |= UART011_CR_RTSEN;
1605
1606 old_cr |= UART011_CR_CTSEN;
1607 uap->autorts = true;
1608 } else {
1609 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1610 uap->autorts = false;
1611 }
1612
1613 if (uap->vendor->oversampling) {
1614 if (baud > port->uartclk / 16)
1615 old_cr |= ST_UART011_CR_OVSFACT;
1616 else
1617 old_cr &= ~ST_UART011_CR_OVSFACT;
1618 }
1619
1620 /* Set baud rate */
1621 writew(quot & 0x3f, port->membase + UART011_FBRD);
1622 writew(quot >> 6, port->membase + UART011_IBRD);
1623
1624 /*
1625 * ----------v----------v----------v----------v-----
1626 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
1627 * ----------^----------^----------^----------^-----
1628 */
1629 writew(lcr_h, port->membase + uap->lcrh_rx);
1630 if (uap->lcrh_rx != uap->lcrh_tx) {
1631 int i;
1632 /*
1633 * Wait 10 PCLKs before writing LCRH_TX register,
1634 * to get this delay write read only register 10 times
1635 */
1636 for (i = 0; i < 10; ++i)
1637 writew(0xff, uap->port.membase + UART011_MIS);
1638 writew(lcr_h, port->membase + uap->lcrh_tx);
1639 }
1640 writew(old_cr, port->membase + UART011_CR);
1641
1642 spin_unlock_irqrestore(&port->lock, flags);
1643}
1644
1645static const char *pl011_type(struct uart_port *port)
1646{
1647 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1648 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1649}
1650
1651/*
1652 * Release the memory region(s) being used by 'port'
1653 */
1654static void pl010_release_port(struct uart_port *port)
1655{
1656 release_mem_region(port->mapbase, SZ_4K);
1657}
1658
1659/*
1660 * Request the memory region(s) being used by 'port'
1661 */
1662static int pl010_request_port(struct uart_port *port)
1663{
1664 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1665 != NULL ? 0 : -EBUSY;
1666}
1667
1668/*
1669 * Configure/autoconfigure the port.
1670 */
1671static void pl010_config_port(struct uart_port *port, int flags)
1672{
1673 if (flags & UART_CONFIG_TYPE) {
1674 port->type = PORT_AMBA;
1675 pl010_request_port(port);
1676 }
1677}
1678
1679/*
1680 * verify the new serial_struct (for TIOCSSERIAL).
1681 */
1682static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
1683{
1684 int ret = 0;
1685 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1686 ret = -EINVAL;
1687 if (ser->irq < 0 || ser->irq >= nr_irqs)
1688 ret = -EINVAL;
1689 if (ser->baud_base < 9600)
1690 ret = -EINVAL;
1691 return ret;
1692}
1693
1694static struct uart_ops amba_pl011_pops = {
1695 .tx_empty = pl01x_tx_empty,
1696 .set_mctrl = pl011_set_mctrl,
1697 .get_mctrl = pl01x_get_mctrl,
1698 .stop_tx = pl011_stop_tx,
1699 .start_tx = pl011_start_tx,
1700 .stop_rx = pl011_stop_rx,
1701 .enable_ms = pl011_enable_ms,
1702 .break_ctl = pl011_break_ctl,
1703 .startup = pl011_startup,
1704 .shutdown = pl011_shutdown,
1705 .flush_buffer = pl011_dma_flush_buffer,
1706 .set_termios = pl011_set_termios,
1707 .type = pl011_type,
1708 .release_port = pl010_release_port,
1709 .request_port = pl010_request_port,
1710 .config_port = pl010_config_port,
1711 .verify_port = pl010_verify_port,
1712#ifdef CONFIG_CONSOLE_POLL
1713 .poll_get_char = pl010_get_poll_char,
1714 .poll_put_char = pl010_put_poll_char,
1715#endif
1716};
1717
1718static struct uart_amba_port *amba_ports[UART_NR];
1719
1720#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1721
1722static void pl011_console_putchar(struct uart_port *port, int ch)
1723{
1724 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1725
1726 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1727 barrier();
1728 writew(ch, uap->port.membase + UART01x_DR);
1729}
1730
1731static void
1732pl011_console_write(struct console *co, const char *s, unsigned int count)
1733{
1734 struct uart_amba_port *uap = amba_ports[co->index];
1735 unsigned int status, old_cr, new_cr;
1736
1737 clk_enable(uap->clk);
1738
1739 /*
1740 * First save the CR then disable the interrupts
1741 */
1742 old_cr = readw(uap->port.membase + UART011_CR);
1743 new_cr = old_cr & ~UART011_CR_CTSEN;
1744 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1745 writew(new_cr, uap->port.membase + UART011_CR);
1746
1747 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1748
1749 /*
1750 * Finally, wait for transmitter to become empty
1751 * and restore the TCR
1752 */
1753 do {
1754 status = readw(uap->port.membase + UART01x_FR);
1755 } while (status & UART01x_FR_BUSY);
1756 writew(old_cr, uap->port.membase + UART011_CR);
1757
1758 clk_disable(uap->clk);
1759}
1760
1761static void __init
1762pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1763 int *parity, int *bits)
1764{
1765 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1766 unsigned int lcr_h, ibrd, fbrd;
1767
1768 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1769
1770 *parity = 'n';
1771 if (lcr_h & UART01x_LCRH_PEN) {
1772 if (lcr_h & UART01x_LCRH_EPS)
1773 *parity = 'e';
1774 else
1775 *parity = 'o';
1776 }
1777
1778 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1779 *bits = 7;
1780 else
1781 *bits = 8;
1782
1783 ibrd = readw(uap->port.membase + UART011_IBRD);
1784 fbrd = readw(uap->port.membase + UART011_FBRD);
1785
1786 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1787
1788 if (uap->vendor->oversampling) {
1789 if (readw(uap->port.membase + UART011_CR)
1790 & ST_UART011_CR_OVSFACT)
1791 *baud *= 2;
1792 }
1793 }
1794}
1795
1796static int __init pl011_console_setup(struct console *co, char *options)
1797{
1798 struct uart_amba_port *uap;
1799 int baud = 38400;
1800 int bits = 8;
1801 int parity = 'n';
1802 int flow = 'n';
1803
1804 /*
1805 * Check whether an invalid uart number has been specified, and
1806 * if so, search for the first available port that does have
1807 * console support.
1808 */
1809 if (co->index >= UART_NR)
1810 co->index = 0;
1811 uap = amba_ports[co->index];
1812 if (!uap)
1813 return -ENODEV;
1814
1815 if (uap->port.dev->platform_data) {
1816 struct amba_pl011_data *plat;
1817
1818 plat = uap->port.dev->platform_data;
1819 if (plat->init)
1820 plat->init();
1821 }
1822
1823 uap->port.uartclk = clk_get_rate(uap->clk);
1824
1825 if (options)
1826 uart_parse_options(options, &baud, &parity, &bits, &flow);
1827 else
1828 pl011_console_get_options(uap, &baud, &parity, &bits);
1829
1830 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1831}
1832
1833static struct uart_driver amba_reg;
1834static struct console amba_console = {
1835 .name = "ttyAMA",
1836 .write = pl011_console_write,
1837 .device = uart_console_device,
1838 .setup = pl011_console_setup,
1839 .flags = CON_PRINTBUFFER,
1840 .index = -1,
1841 .data = &amba_reg,
1842};
1843
1844#define AMBA_CONSOLE (&amba_console)
1845#else
1846#define AMBA_CONSOLE NULL
1847#endif
1848
1849static struct uart_driver amba_reg = {
1850 .owner = THIS_MODULE,
1851 .driver_name = "ttyAMA",
1852 .dev_name = "ttyAMA",
1853 .major = SERIAL_AMBA_MAJOR,
1854 .minor = SERIAL_AMBA_MINOR,
1855 .nr = UART_NR,
1856 .cons = AMBA_CONSOLE,
1857};
1858
1859static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1860{
1861 struct uart_amba_port *uap;
1862 struct vendor_data *vendor = id->data;
1863 void __iomem *base;
1864 int i, ret;
1865
1866 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1867 if (amba_ports[i] == NULL)
1868 break;
1869
1870 if (i == ARRAY_SIZE(amba_ports)) {
1871 ret = -EBUSY;
1872 goto out;
1873 }
1874
1875 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1876 if (uap == NULL) {
1877 ret = -ENOMEM;
1878 goto out;
1879 }
1880
1881 base = ioremap(dev->res.start, resource_size(&dev->res));
1882 if (!base) {
1883 ret = -ENOMEM;
1884 goto free;
1885 }
1886
1887 uap->clk = clk_get(&dev->dev, NULL);
1888 if (IS_ERR(uap->clk)) {
1889 ret = PTR_ERR(uap->clk);
1890 goto unmap;
1891 }
1892
1893 uap->vendor = vendor;
1894 uap->lcrh_rx = vendor->lcrh_rx;
1895 uap->lcrh_tx = vendor->lcrh_tx;
1896 uap->fifosize = vendor->fifosize;
1897 uap->interrupt_may_hang = vendor->interrupt_may_hang;
1898 uap->port.dev = &dev->dev;
1899 uap->port.mapbase = dev->res.start;
1900 uap->port.membase = base;
1901 uap->port.iotype = UPIO_MEM;
1902 uap->port.irq = dev->irq[0];
1903 uap->port.fifosize = uap->fifosize;
1904 uap->port.ops = &amba_pl011_pops;
1905 uap->port.flags = UPF_BOOT_AUTOCONF;
1906 uap->port.line = i;
1907 pl011_dma_probe(uap);
1908
1909 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
1910
1911 amba_ports[i] = uap;
1912
1913 amba_set_drvdata(dev, uap);
1914 ret = uart_add_one_port(&amba_reg, &uap->port);
1915 if (ret) {
1916 amba_set_drvdata(dev, NULL);
1917 amba_ports[i] = NULL;
1918 pl011_dma_remove(uap);
1919 clk_put(uap->clk);
1920 unmap:
1921 iounmap(base);
1922 free:
1923 kfree(uap);
1924 }
1925 out:
1926 return ret;
1927}
1928
1929static int pl011_remove(struct amba_device *dev)
1930{
1931 struct uart_amba_port *uap = amba_get_drvdata(dev);
1932 int i;
1933
1934 amba_set_drvdata(dev, NULL);
1935
1936 uart_remove_one_port(&amba_reg, &uap->port);
1937
1938 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1939 if (amba_ports[i] == uap)
1940 amba_ports[i] = NULL;
1941
1942 pl011_dma_remove(uap);
1943 iounmap(uap->port.membase);
1944 clk_put(uap->clk);
1945 kfree(uap);
1946 return 0;
1947}
1948
1949#ifdef CONFIG_PM
1950static int pl011_suspend(struct amba_device *dev, pm_message_t state)
1951{
1952 struct uart_amba_port *uap = amba_get_drvdata(dev);
1953
1954 if (!uap)
1955 return -EINVAL;
1956
1957 return uart_suspend_port(&amba_reg, &uap->port);
1958}
1959
1960static int pl011_resume(struct amba_device *dev)
1961{
1962 struct uart_amba_port *uap = amba_get_drvdata(dev);
1963
1964 if (!uap)
1965 return -EINVAL;
1966
1967 return uart_resume_port(&amba_reg, &uap->port);
1968}
1969#endif
1970
1971static struct amba_id pl011_ids[] = {
1972 {
1973 .id = 0x00041011,
1974 .mask = 0x000fffff,
1975 .data = &vendor_arm,
1976 },
1977 {
1978 .id = 0x00380802,
1979 .mask = 0x00ffffff,
1980 .data = &vendor_st,
1981 },
1982 { 0, 0 },
1983};
1984
1985static struct amba_driver pl011_driver = {
1986 .drv = {
1987 .name = "uart-pl011",
1988 },
1989 .id_table = pl011_ids,
1990 .probe = pl011_probe,
1991 .remove = pl011_remove,
1992#ifdef CONFIG_PM
1993 .suspend = pl011_suspend,
1994 .resume = pl011_resume,
1995#endif
1996};
1997
1998static int __init pl011_init(void)
1999{
2000 int ret;
2001 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2002
2003 ret = uart_register_driver(&amba_reg);
2004 if (ret == 0) {
2005 ret = amba_driver_register(&pl011_driver);
2006 if (ret)
2007 uart_unregister_driver(&amba_reg);
2008 }
2009 return ret;
2010}
2011
2012static void __exit pl011_exit(void)
2013{
2014 amba_driver_unregister(&pl011_driver);
2015 uart_unregister_driver(&amba_reg);
2016}
2017
2018/*
2019 * While this can be a module, if builtin it's most likely the console
2020 * So let's leave module_exit but move module_init to an earlier place
2021 */
2022arch_initcall(pl011_init);
2023module_exit(pl011_exit);
2024
2025MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2026MODULE_DESCRIPTION("ARM AMBA serial port driver");
2027MODULE_LICENSE("GPL");
1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32
33#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
47#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
49#include <linux/clk.h>
50#include <linux/slab.h>
51#include <linux/dmaengine.h>
52#include <linux/dma-mapping.h>
53#include <linux/scatterlist.h>
54#include <linux/delay.h>
55#include <linux/types.h>
56#include <linux/of.h>
57#include <linux/of_device.h>
58#include <linux/pinctrl/consumer.h>
59#include <linux/sizes.h>
60#include <linux/io.h>
61#include <linux/acpi.h>
62
63#include "amba-pl011.h"
64
65#define UART_NR 14
66
67#define SERIAL_AMBA_MAJOR 204
68#define SERIAL_AMBA_MINOR 64
69#define SERIAL_AMBA_NR UART_NR
70
71#define AMBA_ISR_PASS_LIMIT 256
72
73#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74#define UART_DUMMY_DR_RX (1 << 16)
75
76static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
77 [REG_DR] = UART01x_DR,
78 [REG_FR] = UART01x_FR,
79 [REG_LCRH_RX] = UART011_LCRH,
80 [REG_LCRH_TX] = UART011_LCRH,
81 [REG_IBRD] = UART011_IBRD,
82 [REG_FBRD] = UART011_FBRD,
83 [REG_CR] = UART011_CR,
84 [REG_IFLS] = UART011_IFLS,
85 [REG_IMSC] = UART011_IMSC,
86 [REG_RIS] = UART011_RIS,
87 [REG_MIS] = UART011_MIS,
88 [REG_ICR] = UART011_ICR,
89 [REG_DMACR] = UART011_DMACR,
90};
91
92/* There is by now at least one vendor with differing details, so handle it */
93struct vendor_data {
94 const u16 *reg_offset;
95 unsigned int ifls;
96 bool access_32b;
97 bool oversampling;
98 bool dma_threshold;
99 bool cts_event_workaround;
100 bool always_enabled;
101 bool fixed_options;
102
103 unsigned int (*get_fifosize)(struct amba_device *dev);
104};
105
106static unsigned int get_fifosize_arm(struct amba_device *dev)
107{
108 return amba_rev(dev) < 3 ? 16 : 32;
109}
110
111static struct vendor_data vendor_arm = {
112 .reg_offset = pl011_std_offsets,
113 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
114 .oversampling = false,
115 .dma_threshold = false,
116 .cts_event_workaround = false,
117 .always_enabled = false,
118 .fixed_options = false,
119 .get_fifosize = get_fifosize_arm,
120};
121
122static struct vendor_data vendor_sbsa = {
123 .reg_offset = pl011_std_offsets,
124 .oversampling = false,
125 .dma_threshold = false,
126 .cts_event_workaround = false,
127 .always_enabled = true,
128 .fixed_options = true,
129};
130
131static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
132 [REG_DR] = UART01x_DR,
133 [REG_ST_DMAWM] = ST_UART011_DMAWM,
134 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
135 [REG_FR] = UART01x_FR,
136 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
137 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
138 [REG_IBRD] = UART011_IBRD,
139 [REG_FBRD] = UART011_FBRD,
140 [REG_CR] = UART011_CR,
141 [REG_IFLS] = UART011_IFLS,
142 [REG_IMSC] = UART011_IMSC,
143 [REG_RIS] = UART011_RIS,
144 [REG_MIS] = UART011_MIS,
145 [REG_ICR] = UART011_ICR,
146 [REG_DMACR] = UART011_DMACR,
147 [REG_ST_XFCR] = ST_UART011_XFCR,
148 [REG_ST_XON1] = ST_UART011_XON1,
149 [REG_ST_XON2] = ST_UART011_XON2,
150 [REG_ST_XOFF1] = ST_UART011_XOFF1,
151 [REG_ST_XOFF2] = ST_UART011_XOFF2,
152 [REG_ST_ITCR] = ST_UART011_ITCR,
153 [REG_ST_ITIP] = ST_UART011_ITIP,
154 [REG_ST_ABCR] = ST_UART011_ABCR,
155 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
156};
157
158static unsigned int get_fifosize_st(struct amba_device *dev)
159{
160 return 64;
161}
162
163static struct vendor_data vendor_st = {
164 .reg_offset = pl011_st_offsets,
165 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
166 .oversampling = true,
167 .dma_threshold = true,
168 .cts_event_workaround = true,
169 .always_enabled = false,
170 .fixed_options = false,
171 .get_fifosize = get_fifosize_st,
172};
173
174static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
175 [REG_DR] = ZX_UART011_DR,
176 [REG_FR] = ZX_UART011_FR,
177 [REG_LCRH_RX] = ZX_UART011_LCRH,
178 [REG_LCRH_TX] = ZX_UART011_LCRH,
179 [REG_IBRD] = ZX_UART011_IBRD,
180 [REG_FBRD] = ZX_UART011_FBRD,
181 [REG_CR] = ZX_UART011_CR,
182 [REG_IFLS] = ZX_UART011_IFLS,
183 [REG_IMSC] = ZX_UART011_IMSC,
184 [REG_RIS] = ZX_UART011_RIS,
185 [REG_MIS] = ZX_UART011_MIS,
186 [REG_ICR] = ZX_UART011_ICR,
187 [REG_DMACR] = ZX_UART011_DMACR,
188};
189
190static struct vendor_data vendor_zte __maybe_unused = {
191 .reg_offset = pl011_zte_offsets,
192 .access_32b = true,
193 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
194 .get_fifosize = get_fifosize_arm,
195};
196
197/* Deals with DMA transactions */
198
199struct pl011_sgbuf {
200 struct scatterlist sg;
201 char *buf;
202};
203
204struct pl011_dmarx_data {
205 struct dma_chan *chan;
206 struct completion complete;
207 bool use_buf_b;
208 struct pl011_sgbuf sgbuf_a;
209 struct pl011_sgbuf sgbuf_b;
210 dma_cookie_t cookie;
211 bool running;
212 struct timer_list timer;
213 unsigned int last_residue;
214 unsigned long last_jiffies;
215 bool auto_poll_rate;
216 unsigned int poll_rate;
217 unsigned int poll_timeout;
218};
219
220struct pl011_dmatx_data {
221 struct dma_chan *chan;
222 struct scatterlist sg;
223 char *buf;
224 bool queued;
225};
226
227/*
228 * We wrap our port structure around the generic uart_port.
229 */
230struct uart_amba_port {
231 struct uart_port port;
232 const u16 *reg_offset;
233 struct clk *clk;
234 const struct vendor_data *vendor;
235 unsigned int dmacr; /* dma control reg */
236 unsigned int im; /* interrupt mask */
237 unsigned int old_status;
238 unsigned int fifosize; /* vendor-specific */
239 unsigned int old_cr; /* state during shutdown */
240 bool autorts;
241 unsigned int fixed_baud; /* vendor-set fixed baud rate */
242 char type[12];
243#ifdef CONFIG_DMA_ENGINE
244 /* DMA stuff */
245 bool using_tx_dma;
246 bool using_rx_dma;
247 struct pl011_dmarx_data dmarx;
248 struct pl011_dmatx_data dmatx;
249 bool dma_probed;
250#endif
251};
252
253static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
254 unsigned int reg)
255{
256 return uap->reg_offset[reg];
257}
258
259static unsigned int pl011_read(const struct uart_amba_port *uap,
260 unsigned int reg)
261{
262 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
263
264 return (uap->port.iotype == UPIO_MEM32) ?
265 readl_relaxed(addr) : readw_relaxed(addr);
266}
267
268static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
269 unsigned int reg)
270{
271 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
272
273 if (uap->port.iotype == UPIO_MEM32)
274 writel_relaxed(val, addr);
275 else
276 writew_relaxed(val, addr);
277}
278
279/*
280 * Reads up to 256 characters from the FIFO or until it's empty and
281 * inserts them into the TTY layer. Returns the number of characters
282 * read from the FIFO.
283 */
284static int pl011_fifo_to_tty(struct uart_amba_port *uap)
285{
286 u16 status;
287 unsigned int ch, flag, max_count = 256;
288 int fifotaken = 0;
289
290 while (max_count--) {
291 status = pl011_read(uap, REG_FR);
292 if (status & UART01x_FR_RXFE)
293 break;
294
295 /* Take chars from the FIFO and update status */
296 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
297 flag = TTY_NORMAL;
298 uap->port.icount.rx++;
299 fifotaken++;
300
301 if (unlikely(ch & UART_DR_ERROR)) {
302 if (ch & UART011_DR_BE) {
303 ch &= ~(UART011_DR_FE | UART011_DR_PE);
304 uap->port.icount.brk++;
305 if (uart_handle_break(&uap->port))
306 continue;
307 } else if (ch & UART011_DR_PE)
308 uap->port.icount.parity++;
309 else if (ch & UART011_DR_FE)
310 uap->port.icount.frame++;
311 if (ch & UART011_DR_OE)
312 uap->port.icount.overrun++;
313
314 ch &= uap->port.read_status_mask;
315
316 if (ch & UART011_DR_BE)
317 flag = TTY_BREAK;
318 else if (ch & UART011_DR_PE)
319 flag = TTY_PARITY;
320 else if (ch & UART011_DR_FE)
321 flag = TTY_FRAME;
322 }
323
324 if (uart_handle_sysrq_char(&uap->port, ch & 255))
325 continue;
326
327 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
328 }
329
330 return fifotaken;
331}
332
333
334/*
335 * All the DMA operation mode stuff goes inside this ifdef.
336 * This assumes that you have a generic DMA device interface,
337 * no custom DMA interfaces are supported.
338 */
339#ifdef CONFIG_DMA_ENGINE
340
341#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
342
343static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
344 enum dma_data_direction dir)
345{
346 dma_addr_t dma_addr;
347
348 sg->buf = dma_alloc_coherent(chan->device->dev,
349 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
350 if (!sg->buf)
351 return -ENOMEM;
352
353 sg_init_table(&sg->sg, 1);
354 sg_set_page(&sg->sg, phys_to_page(dma_addr),
355 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
356 sg_dma_address(&sg->sg) = dma_addr;
357 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
358
359 return 0;
360}
361
362static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
363 enum dma_data_direction dir)
364{
365 if (sg->buf) {
366 dma_free_coherent(chan->device->dev,
367 PL011_DMA_BUFFER_SIZE, sg->buf,
368 sg_dma_address(&sg->sg));
369 }
370}
371
372static void pl011_dma_probe(struct uart_amba_port *uap)
373{
374 /* DMA is the sole user of the platform data right now */
375 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
376 struct device *dev = uap->port.dev;
377 struct dma_slave_config tx_conf = {
378 .dst_addr = uap->port.mapbase +
379 pl011_reg_to_offset(uap, REG_DR),
380 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
381 .direction = DMA_MEM_TO_DEV,
382 .dst_maxburst = uap->fifosize >> 1,
383 .device_fc = false,
384 };
385 struct dma_chan *chan;
386 dma_cap_mask_t mask;
387
388 uap->dma_probed = true;
389 chan = dma_request_slave_channel_reason(dev, "tx");
390 if (IS_ERR(chan)) {
391 if (PTR_ERR(chan) == -EPROBE_DEFER) {
392 uap->dma_probed = false;
393 return;
394 }
395
396 /* We need platform data */
397 if (!plat || !plat->dma_filter) {
398 dev_info(uap->port.dev, "no DMA platform data\n");
399 return;
400 }
401
402 /* Try to acquire a generic DMA engine slave TX channel */
403 dma_cap_zero(mask);
404 dma_cap_set(DMA_SLAVE, mask);
405
406 chan = dma_request_channel(mask, plat->dma_filter,
407 plat->dma_tx_param);
408 if (!chan) {
409 dev_err(uap->port.dev, "no TX DMA channel!\n");
410 return;
411 }
412 }
413
414 dmaengine_slave_config(chan, &tx_conf);
415 uap->dmatx.chan = chan;
416
417 dev_info(uap->port.dev, "DMA channel TX %s\n",
418 dma_chan_name(uap->dmatx.chan));
419
420 /* Optionally make use of an RX channel as well */
421 chan = dma_request_slave_channel(dev, "rx");
422
423 if (!chan && plat && plat->dma_rx_param) {
424 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
425
426 if (!chan) {
427 dev_err(uap->port.dev, "no RX DMA channel!\n");
428 return;
429 }
430 }
431
432 if (chan) {
433 struct dma_slave_config rx_conf = {
434 .src_addr = uap->port.mapbase +
435 pl011_reg_to_offset(uap, REG_DR),
436 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
437 .direction = DMA_DEV_TO_MEM,
438 .src_maxburst = uap->fifosize >> 2,
439 .device_fc = false,
440 };
441 struct dma_slave_caps caps;
442
443 /*
444 * Some DMA controllers provide information on their capabilities.
445 * If the controller does, check for suitable residue processing
446 * otherwise assime all is well.
447 */
448 if (0 == dma_get_slave_caps(chan, &caps)) {
449 if (caps.residue_granularity ==
450 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
451 dma_release_channel(chan);
452 dev_info(uap->port.dev,
453 "RX DMA disabled - no residue processing\n");
454 return;
455 }
456 }
457 dmaengine_slave_config(chan, &rx_conf);
458 uap->dmarx.chan = chan;
459
460 uap->dmarx.auto_poll_rate = false;
461 if (plat && plat->dma_rx_poll_enable) {
462 /* Set poll rate if specified. */
463 if (plat->dma_rx_poll_rate) {
464 uap->dmarx.auto_poll_rate = false;
465 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
466 } else {
467 /*
468 * 100 ms defaults to poll rate if not
469 * specified. This will be adjusted with
470 * the baud rate at set_termios.
471 */
472 uap->dmarx.auto_poll_rate = true;
473 uap->dmarx.poll_rate = 100;
474 }
475 /* 3 secs defaults poll_timeout if not specified. */
476 if (plat->dma_rx_poll_timeout)
477 uap->dmarx.poll_timeout =
478 plat->dma_rx_poll_timeout;
479 else
480 uap->dmarx.poll_timeout = 3000;
481 } else if (!plat && dev->of_node) {
482 uap->dmarx.auto_poll_rate = of_property_read_bool(
483 dev->of_node, "auto-poll");
484 if (uap->dmarx.auto_poll_rate) {
485 u32 x;
486
487 if (0 == of_property_read_u32(dev->of_node,
488 "poll-rate-ms", &x))
489 uap->dmarx.poll_rate = x;
490 else
491 uap->dmarx.poll_rate = 100;
492 if (0 == of_property_read_u32(dev->of_node,
493 "poll-timeout-ms", &x))
494 uap->dmarx.poll_timeout = x;
495 else
496 uap->dmarx.poll_timeout = 3000;
497 }
498 }
499 dev_info(uap->port.dev, "DMA channel RX %s\n",
500 dma_chan_name(uap->dmarx.chan));
501 }
502}
503
504static void pl011_dma_remove(struct uart_amba_port *uap)
505{
506 if (uap->dmatx.chan)
507 dma_release_channel(uap->dmatx.chan);
508 if (uap->dmarx.chan)
509 dma_release_channel(uap->dmarx.chan);
510}
511
512/* Forward declare these for the refill routine */
513static int pl011_dma_tx_refill(struct uart_amba_port *uap);
514static void pl011_start_tx_pio(struct uart_amba_port *uap);
515
516/*
517 * The current DMA TX buffer has been sent.
518 * Try to queue up another DMA buffer.
519 */
520static void pl011_dma_tx_callback(void *data)
521{
522 struct uart_amba_port *uap = data;
523 struct pl011_dmatx_data *dmatx = &uap->dmatx;
524 unsigned long flags;
525 u16 dmacr;
526
527 spin_lock_irqsave(&uap->port.lock, flags);
528 if (uap->dmatx.queued)
529 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
530 DMA_TO_DEVICE);
531
532 dmacr = uap->dmacr;
533 uap->dmacr = dmacr & ~UART011_TXDMAE;
534 pl011_write(uap->dmacr, uap, REG_DMACR);
535
536 /*
537 * If TX DMA was disabled, it means that we've stopped the DMA for
538 * some reason (eg, XOFF received, or we want to send an X-char.)
539 *
540 * Note: we need to be careful here of a potential race between DMA
541 * and the rest of the driver - if the driver disables TX DMA while
542 * a TX buffer completing, we must update the tx queued status to
543 * get further refills (hence we check dmacr).
544 */
545 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
546 uart_circ_empty(&uap->port.state->xmit)) {
547 uap->dmatx.queued = false;
548 spin_unlock_irqrestore(&uap->port.lock, flags);
549 return;
550 }
551
552 if (pl011_dma_tx_refill(uap) <= 0)
553 /*
554 * We didn't queue a DMA buffer for some reason, but we
555 * have data pending to be sent. Re-enable the TX IRQ.
556 */
557 pl011_start_tx_pio(uap);
558
559 spin_unlock_irqrestore(&uap->port.lock, flags);
560}
561
562/*
563 * Try to refill the TX DMA buffer.
564 * Locking: called with port lock held and IRQs disabled.
565 * Returns:
566 * 1 if we queued up a TX DMA buffer.
567 * 0 if we didn't want to handle this by DMA
568 * <0 on error
569 */
570static int pl011_dma_tx_refill(struct uart_amba_port *uap)
571{
572 struct pl011_dmatx_data *dmatx = &uap->dmatx;
573 struct dma_chan *chan = dmatx->chan;
574 struct dma_device *dma_dev = chan->device;
575 struct dma_async_tx_descriptor *desc;
576 struct circ_buf *xmit = &uap->port.state->xmit;
577 unsigned int count;
578
579 /*
580 * Try to avoid the overhead involved in using DMA if the
581 * transaction fits in the first half of the FIFO, by using
582 * the standard interrupt handling. This ensures that we
583 * issue a uart_write_wakeup() at the appropriate time.
584 */
585 count = uart_circ_chars_pending(xmit);
586 if (count < (uap->fifosize >> 1)) {
587 uap->dmatx.queued = false;
588 return 0;
589 }
590
591 /*
592 * Bodge: don't send the last character by DMA, as this
593 * will prevent XON from notifying us to restart DMA.
594 */
595 count -= 1;
596
597 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
598 if (count > PL011_DMA_BUFFER_SIZE)
599 count = PL011_DMA_BUFFER_SIZE;
600
601 if (xmit->tail < xmit->head)
602 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
603 else {
604 size_t first = UART_XMIT_SIZE - xmit->tail;
605 size_t second;
606
607 if (first > count)
608 first = count;
609 second = count - first;
610
611 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
612 if (second)
613 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
614 }
615
616 dmatx->sg.length = count;
617
618 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
619 uap->dmatx.queued = false;
620 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
621 return -EBUSY;
622 }
623
624 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
625 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
626 if (!desc) {
627 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
628 uap->dmatx.queued = false;
629 /*
630 * If DMA cannot be used right now, we complete this
631 * transaction via IRQ and let the TTY layer retry.
632 */
633 dev_dbg(uap->port.dev, "TX DMA busy\n");
634 return -EBUSY;
635 }
636
637 /* Some data to go along to the callback */
638 desc->callback = pl011_dma_tx_callback;
639 desc->callback_param = uap;
640
641 /* All errors should happen at prepare time */
642 dmaengine_submit(desc);
643
644 /* Fire the DMA transaction */
645 dma_dev->device_issue_pending(chan);
646
647 uap->dmacr |= UART011_TXDMAE;
648 pl011_write(uap->dmacr, uap, REG_DMACR);
649 uap->dmatx.queued = true;
650
651 /*
652 * Now we know that DMA will fire, so advance the ring buffer
653 * with the stuff we just dispatched.
654 */
655 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
656 uap->port.icount.tx += count;
657
658 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
659 uart_write_wakeup(&uap->port);
660
661 return 1;
662}
663
664/*
665 * We received a transmit interrupt without a pending X-char but with
666 * pending characters.
667 * Locking: called with port lock held and IRQs disabled.
668 * Returns:
669 * false if we want to use PIO to transmit
670 * true if we queued a DMA buffer
671 */
672static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
673{
674 if (!uap->using_tx_dma)
675 return false;
676
677 /*
678 * If we already have a TX buffer queued, but received a
679 * TX interrupt, it will be because we've just sent an X-char.
680 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
681 */
682 if (uap->dmatx.queued) {
683 uap->dmacr |= UART011_TXDMAE;
684 pl011_write(uap->dmacr, uap, REG_DMACR);
685 uap->im &= ~UART011_TXIM;
686 pl011_write(uap->im, uap, REG_IMSC);
687 return true;
688 }
689
690 /*
691 * We don't have a TX buffer queued, so try to queue one.
692 * If we successfully queued a buffer, mask the TX IRQ.
693 */
694 if (pl011_dma_tx_refill(uap) > 0) {
695 uap->im &= ~UART011_TXIM;
696 pl011_write(uap->im, uap, REG_IMSC);
697 return true;
698 }
699 return false;
700}
701
702/*
703 * Stop the DMA transmit (eg, due to received XOFF).
704 * Locking: called with port lock held and IRQs disabled.
705 */
706static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
707{
708 if (uap->dmatx.queued) {
709 uap->dmacr &= ~UART011_TXDMAE;
710 pl011_write(uap->dmacr, uap, REG_DMACR);
711 }
712}
713
714/*
715 * Try to start a DMA transmit, or in the case of an XON/OFF
716 * character queued for send, try to get that character out ASAP.
717 * Locking: called with port lock held and IRQs disabled.
718 * Returns:
719 * false if we want the TX IRQ to be enabled
720 * true if we have a buffer queued
721 */
722static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
723{
724 u16 dmacr;
725
726 if (!uap->using_tx_dma)
727 return false;
728
729 if (!uap->port.x_char) {
730 /* no X-char, try to push chars out in DMA mode */
731 bool ret = true;
732
733 if (!uap->dmatx.queued) {
734 if (pl011_dma_tx_refill(uap) > 0) {
735 uap->im &= ~UART011_TXIM;
736 pl011_write(uap->im, uap, REG_IMSC);
737 } else
738 ret = false;
739 } else if (!(uap->dmacr & UART011_TXDMAE)) {
740 uap->dmacr |= UART011_TXDMAE;
741 pl011_write(uap->dmacr, uap, REG_DMACR);
742 }
743 return ret;
744 }
745
746 /*
747 * We have an X-char to send. Disable DMA to prevent it loading
748 * the TX fifo, and then see if we can stuff it into the FIFO.
749 */
750 dmacr = uap->dmacr;
751 uap->dmacr &= ~UART011_TXDMAE;
752 pl011_write(uap->dmacr, uap, REG_DMACR);
753
754 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
755 /*
756 * No space in the FIFO, so enable the transmit interrupt
757 * so we know when there is space. Note that once we've
758 * loaded the character, we should just re-enable DMA.
759 */
760 return false;
761 }
762
763 pl011_write(uap->port.x_char, uap, REG_DR);
764 uap->port.icount.tx++;
765 uap->port.x_char = 0;
766
767 /* Success - restore the DMA state */
768 uap->dmacr = dmacr;
769 pl011_write(dmacr, uap, REG_DMACR);
770
771 return true;
772}
773
774/*
775 * Flush the transmit buffer.
776 * Locking: called with port lock held and IRQs disabled.
777 */
778static void pl011_dma_flush_buffer(struct uart_port *port)
779__releases(&uap->port.lock)
780__acquires(&uap->port.lock)
781{
782 struct uart_amba_port *uap =
783 container_of(port, struct uart_amba_port, port);
784
785 if (!uap->using_tx_dma)
786 return;
787
788 /* Avoid deadlock with the DMA engine callback */
789 spin_unlock(&uap->port.lock);
790 dmaengine_terminate_all(uap->dmatx.chan);
791 spin_lock(&uap->port.lock);
792 if (uap->dmatx.queued) {
793 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
794 DMA_TO_DEVICE);
795 uap->dmatx.queued = false;
796 uap->dmacr &= ~UART011_TXDMAE;
797 pl011_write(uap->dmacr, uap, REG_DMACR);
798 }
799}
800
801static void pl011_dma_rx_callback(void *data);
802
803static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
804{
805 struct dma_chan *rxchan = uap->dmarx.chan;
806 struct pl011_dmarx_data *dmarx = &uap->dmarx;
807 struct dma_async_tx_descriptor *desc;
808 struct pl011_sgbuf *sgbuf;
809
810 if (!rxchan)
811 return -EIO;
812
813 /* Start the RX DMA job */
814 sgbuf = uap->dmarx.use_buf_b ?
815 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
816 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
817 DMA_DEV_TO_MEM,
818 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
819 /*
820 * If the DMA engine is busy and cannot prepare a
821 * channel, no big deal, the driver will fall back
822 * to interrupt mode as a result of this error code.
823 */
824 if (!desc) {
825 uap->dmarx.running = false;
826 dmaengine_terminate_all(rxchan);
827 return -EBUSY;
828 }
829
830 /* Some data to go along to the callback */
831 desc->callback = pl011_dma_rx_callback;
832 desc->callback_param = uap;
833 dmarx->cookie = dmaengine_submit(desc);
834 dma_async_issue_pending(rxchan);
835
836 uap->dmacr |= UART011_RXDMAE;
837 pl011_write(uap->dmacr, uap, REG_DMACR);
838 uap->dmarx.running = true;
839
840 uap->im &= ~UART011_RXIM;
841 pl011_write(uap->im, uap, REG_IMSC);
842
843 return 0;
844}
845
846/*
847 * This is called when either the DMA job is complete, or
848 * the FIFO timeout interrupt occurred. This must be called
849 * with the port spinlock uap->port.lock held.
850 */
851static void pl011_dma_rx_chars(struct uart_amba_port *uap,
852 u32 pending, bool use_buf_b,
853 bool readfifo)
854{
855 struct tty_port *port = &uap->port.state->port;
856 struct pl011_sgbuf *sgbuf = use_buf_b ?
857 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
858 int dma_count = 0;
859 u32 fifotaken = 0; /* only used for vdbg() */
860
861 struct pl011_dmarx_data *dmarx = &uap->dmarx;
862 int dmataken = 0;
863
864 if (uap->dmarx.poll_rate) {
865 /* The data can be taken by polling */
866 dmataken = sgbuf->sg.length - dmarx->last_residue;
867 /* Recalculate the pending size */
868 if (pending >= dmataken)
869 pending -= dmataken;
870 }
871
872 /* Pick the remain data from the DMA */
873 if (pending) {
874
875 /*
876 * First take all chars in the DMA pipe, then look in the FIFO.
877 * Note that tty_insert_flip_buf() tries to take as many chars
878 * as it can.
879 */
880 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
881 pending);
882
883 uap->port.icount.rx += dma_count;
884 if (dma_count < pending)
885 dev_warn(uap->port.dev,
886 "couldn't insert all characters (TTY is full?)\n");
887 }
888
889 /* Reset the last_residue for Rx DMA poll */
890 if (uap->dmarx.poll_rate)
891 dmarx->last_residue = sgbuf->sg.length;
892
893 /*
894 * Only continue with trying to read the FIFO if all DMA chars have
895 * been taken first.
896 */
897 if (dma_count == pending && readfifo) {
898 /* Clear any error flags */
899 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
900 UART011_FEIS, uap, REG_ICR);
901
902 /*
903 * If we read all the DMA'd characters, and we had an
904 * incomplete buffer, that could be due to an rx error, or
905 * maybe we just timed out. Read any pending chars and check
906 * the error status.
907 *
908 * Error conditions will only occur in the FIFO, these will
909 * trigger an immediate interrupt and stop the DMA job, so we
910 * will always find the error in the FIFO, never in the DMA
911 * buffer.
912 */
913 fifotaken = pl011_fifo_to_tty(uap);
914 }
915
916 spin_unlock(&uap->port.lock);
917 dev_vdbg(uap->port.dev,
918 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
919 dma_count, fifotaken);
920 tty_flip_buffer_push(port);
921 spin_lock(&uap->port.lock);
922}
923
924static void pl011_dma_rx_irq(struct uart_amba_port *uap)
925{
926 struct pl011_dmarx_data *dmarx = &uap->dmarx;
927 struct dma_chan *rxchan = dmarx->chan;
928 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
929 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
930 size_t pending;
931 struct dma_tx_state state;
932 enum dma_status dmastat;
933
934 /*
935 * Pause the transfer so we can trust the current counter,
936 * do this before we pause the PL011 block, else we may
937 * overflow the FIFO.
938 */
939 if (dmaengine_pause(rxchan))
940 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
941 dmastat = rxchan->device->device_tx_status(rxchan,
942 dmarx->cookie, &state);
943 if (dmastat != DMA_PAUSED)
944 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
945
946 /* Disable RX DMA - incoming data will wait in the FIFO */
947 uap->dmacr &= ~UART011_RXDMAE;
948 pl011_write(uap->dmacr, uap, REG_DMACR);
949 uap->dmarx.running = false;
950
951 pending = sgbuf->sg.length - state.residue;
952 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
953 /* Then we terminate the transfer - we now know our residue */
954 dmaengine_terminate_all(rxchan);
955
956 /*
957 * This will take the chars we have so far and insert
958 * into the framework.
959 */
960 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
961
962 /* Switch buffer & re-trigger DMA job */
963 dmarx->use_buf_b = !dmarx->use_buf_b;
964 if (pl011_dma_rx_trigger_dma(uap)) {
965 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
966 "fall back to interrupt mode\n");
967 uap->im |= UART011_RXIM;
968 pl011_write(uap->im, uap, REG_IMSC);
969 }
970}
971
972static void pl011_dma_rx_callback(void *data)
973{
974 struct uart_amba_port *uap = data;
975 struct pl011_dmarx_data *dmarx = &uap->dmarx;
976 struct dma_chan *rxchan = dmarx->chan;
977 bool lastbuf = dmarx->use_buf_b;
978 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
979 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
980 size_t pending;
981 struct dma_tx_state state;
982 int ret;
983
984 /*
985 * This completion interrupt occurs typically when the
986 * RX buffer is totally stuffed but no timeout has yet
987 * occurred. When that happens, we just want the RX
988 * routine to flush out the secondary DMA buffer while
989 * we immediately trigger the next DMA job.
990 */
991 spin_lock_irq(&uap->port.lock);
992 /*
993 * Rx data can be taken by the UART interrupts during
994 * the DMA irq handler. So we check the residue here.
995 */
996 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
997 pending = sgbuf->sg.length - state.residue;
998 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
999 /* Then we terminate the transfer - we now know our residue */
1000 dmaengine_terminate_all(rxchan);
1001
1002 uap->dmarx.running = false;
1003 dmarx->use_buf_b = !lastbuf;
1004 ret = pl011_dma_rx_trigger_dma(uap);
1005
1006 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1007 spin_unlock_irq(&uap->port.lock);
1008 /*
1009 * Do this check after we picked the DMA chars so we don't
1010 * get some IRQ immediately from RX.
1011 */
1012 if (ret) {
1013 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1014 "fall back to interrupt mode\n");
1015 uap->im |= UART011_RXIM;
1016 pl011_write(uap->im, uap, REG_IMSC);
1017 }
1018}
1019
1020/*
1021 * Stop accepting received characters, when we're shutting down or
1022 * suspending this port.
1023 * Locking: called with port lock held and IRQs disabled.
1024 */
1025static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1026{
1027 /* FIXME. Just disable the DMA enable */
1028 uap->dmacr &= ~UART011_RXDMAE;
1029 pl011_write(uap->dmacr, uap, REG_DMACR);
1030}
1031
1032/*
1033 * Timer handler for Rx DMA polling.
1034 * Every polling, It checks the residue in the dma buffer and transfer
1035 * data to the tty. Also, last_residue is updated for the next polling.
1036 */
1037static void pl011_dma_rx_poll(unsigned long args)
1038{
1039 struct uart_amba_port *uap = (struct uart_amba_port *)args;
1040 struct tty_port *port = &uap->port.state->port;
1041 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1042 struct dma_chan *rxchan = uap->dmarx.chan;
1043 unsigned long flags = 0;
1044 unsigned int dmataken = 0;
1045 unsigned int size = 0;
1046 struct pl011_sgbuf *sgbuf;
1047 int dma_count;
1048 struct dma_tx_state state;
1049
1050 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1051 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1052 if (likely(state.residue < dmarx->last_residue)) {
1053 dmataken = sgbuf->sg.length - dmarx->last_residue;
1054 size = dmarx->last_residue - state.residue;
1055 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1056 size);
1057 if (dma_count == size)
1058 dmarx->last_residue = state.residue;
1059 dmarx->last_jiffies = jiffies;
1060 }
1061 tty_flip_buffer_push(port);
1062
1063 /*
1064 * If no data is received in poll_timeout, the driver will fall back
1065 * to interrupt mode. We will retrigger DMA at the first interrupt.
1066 */
1067 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1068 > uap->dmarx.poll_timeout) {
1069
1070 spin_lock_irqsave(&uap->port.lock, flags);
1071 pl011_dma_rx_stop(uap);
1072 uap->im |= UART011_RXIM;
1073 pl011_write(uap->im, uap, REG_IMSC);
1074 spin_unlock_irqrestore(&uap->port.lock, flags);
1075
1076 uap->dmarx.running = false;
1077 dmaengine_terminate_all(rxchan);
1078 del_timer(&uap->dmarx.timer);
1079 } else {
1080 mod_timer(&uap->dmarx.timer,
1081 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1082 }
1083}
1084
1085static void pl011_dma_startup(struct uart_amba_port *uap)
1086{
1087 int ret;
1088
1089 if (!uap->dma_probed)
1090 pl011_dma_probe(uap);
1091
1092 if (!uap->dmatx.chan)
1093 return;
1094
1095 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1096 if (!uap->dmatx.buf) {
1097 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1098 uap->port.fifosize = uap->fifosize;
1099 return;
1100 }
1101
1102 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1103
1104 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1105 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1106 uap->using_tx_dma = true;
1107
1108 if (!uap->dmarx.chan)
1109 goto skip_rx;
1110
1111 /* Allocate and map DMA RX buffers */
1112 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1113 DMA_FROM_DEVICE);
1114 if (ret) {
1115 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1116 "RX buffer A", ret);
1117 goto skip_rx;
1118 }
1119
1120 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1121 DMA_FROM_DEVICE);
1122 if (ret) {
1123 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1124 "RX buffer B", ret);
1125 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1126 DMA_FROM_DEVICE);
1127 goto skip_rx;
1128 }
1129
1130 uap->using_rx_dma = true;
1131
1132skip_rx:
1133 /* Turn on DMA error (RX/TX will be enabled on demand) */
1134 uap->dmacr |= UART011_DMAONERR;
1135 pl011_write(uap->dmacr, uap, REG_DMACR);
1136
1137 /*
1138 * ST Micro variants has some specific dma burst threshold
1139 * compensation. Set this to 16 bytes, so burst will only
1140 * be issued above/below 16 bytes.
1141 */
1142 if (uap->vendor->dma_threshold)
1143 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1144 uap, REG_ST_DMAWM);
1145
1146 if (uap->using_rx_dma) {
1147 if (pl011_dma_rx_trigger_dma(uap))
1148 dev_dbg(uap->port.dev, "could not trigger initial "
1149 "RX DMA job, fall back to interrupt mode\n");
1150 if (uap->dmarx.poll_rate) {
1151 init_timer(&(uap->dmarx.timer));
1152 uap->dmarx.timer.function = pl011_dma_rx_poll;
1153 uap->dmarx.timer.data = (unsigned long)uap;
1154 mod_timer(&uap->dmarx.timer,
1155 jiffies +
1156 msecs_to_jiffies(uap->dmarx.poll_rate));
1157 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1158 uap->dmarx.last_jiffies = jiffies;
1159 }
1160 }
1161}
1162
1163static void pl011_dma_shutdown(struct uart_amba_port *uap)
1164{
1165 if (!(uap->using_tx_dma || uap->using_rx_dma))
1166 return;
1167
1168 /* Disable RX and TX DMA */
1169 while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY)
1170 cpu_relax();
1171
1172 spin_lock_irq(&uap->port.lock);
1173 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1174 pl011_write(uap->dmacr, uap, REG_DMACR);
1175 spin_unlock_irq(&uap->port.lock);
1176
1177 if (uap->using_tx_dma) {
1178 /* In theory, this should already be done by pl011_dma_flush_buffer */
1179 dmaengine_terminate_all(uap->dmatx.chan);
1180 if (uap->dmatx.queued) {
1181 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1182 DMA_TO_DEVICE);
1183 uap->dmatx.queued = false;
1184 }
1185
1186 kfree(uap->dmatx.buf);
1187 uap->using_tx_dma = false;
1188 }
1189
1190 if (uap->using_rx_dma) {
1191 dmaengine_terminate_all(uap->dmarx.chan);
1192 /* Clean up the RX DMA */
1193 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1194 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1195 if (uap->dmarx.poll_rate)
1196 del_timer_sync(&uap->dmarx.timer);
1197 uap->using_rx_dma = false;
1198 }
1199}
1200
1201static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1202{
1203 return uap->using_rx_dma;
1204}
1205
1206static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1207{
1208 return uap->using_rx_dma && uap->dmarx.running;
1209}
1210
1211#else
1212/* Blank functions if the DMA engine is not available */
1213static inline void pl011_dma_probe(struct uart_amba_port *uap)
1214{
1215}
1216
1217static inline void pl011_dma_remove(struct uart_amba_port *uap)
1218{
1219}
1220
1221static inline void pl011_dma_startup(struct uart_amba_port *uap)
1222{
1223}
1224
1225static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1226{
1227}
1228
1229static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1230{
1231 return false;
1232}
1233
1234static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1235{
1236}
1237
1238static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1239{
1240 return false;
1241}
1242
1243static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1244{
1245}
1246
1247static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1248{
1249}
1250
1251static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1252{
1253 return -EIO;
1254}
1255
1256static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1257{
1258 return false;
1259}
1260
1261static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1262{
1263 return false;
1264}
1265
1266#define pl011_dma_flush_buffer NULL
1267#endif
1268
1269static void pl011_stop_tx(struct uart_port *port)
1270{
1271 struct uart_amba_port *uap =
1272 container_of(port, struct uart_amba_port, port);
1273
1274 uap->im &= ~UART011_TXIM;
1275 pl011_write(uap->im, uap, REG_IMSC);
1276 pl011_dma_tx_stop(uap);
1277}
1278
1279static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1280
1281/* Start TX with programmed I/O only (no DMA) */
1282static void pl011_start_tx_pio(struct uart_amba_port *uap)
1283{
1284 uap->im |= UART011_TXIM;
1285 pl011_write(uap->im, uap, REG_IMSC);
1286 pl011_tx_chars(uap, false);
1287}
1288
1289static void pl011_start_tx(struct uart_port *port)
1290{
1291 struct uart_amba_port *uap =
1292 container_of(port, struct uart_amba_port, port);
1293
1294 if (!pl011_dma_tx_start(uap))
1295 pl011_start_tx_pio(uap);
1296}
1297
1298static void pl011_stop_rx(struct uart_port *port)
1299{
1300 struct uart_amba_port *uap =
1301 container_of(port, struct uart_amba_port, port);
1302
1303 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1304 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1305 pl011_write(uap->im, uap, REG_IMSC);
1306
1307 pl011_dma_rx_stop(uap);
1308}
1309
1310static void pl011_enable_ms(struct uart_port *port)
1311{
1312 struct uart_amba_port *uap =
1313 container_of(port, struct uart_amba_port, port);
1314
1315 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1316 pl011_write(uap->im, uap, REG_IMSC);
1317}
1318
1319static void pl011_rx_chars(struct uart_amba_port *uap)
1320__releases(&uap->port.lock)
1321__acquires(&uap->port.lock)
1322{
1323 pl011_fifo_to_tty(uap);
1324
1325 spin_unlock(&uap->port.lock);
1326 tty_flip_buffer_push(&uap->port.state->port);
1327 /*
1328 * If we were temporarily out of DMA mode for a while,
1329 * attempt to switch back to DMA mode again.
1330 */
1331 if (pl011_dma_rx_available(uap)) {
1332 if (pl011_dma_rx_trigger_dma(uap)) {
1333 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1334 "fall back to interrupt mode again\n");
1335 uap->im |= UART011_RXIM;
1336 pl011_write(uap->im, uap, REG_IMSC);
1337 } else {
1338#ifdef CONFIG_DMA_ENGINE
1339 /* Start Rx DMA poll */
1340 if (uap->dmarx.poll_rate) {
1341 uap->dmarx.last_jiffies = jiffies;
1342 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1343 mod_timer(&uap->dmarx.timer,
1344 jiffies +
1345 msecs_to_jiffies(uap->dmarx.poll_rate));
1346 }
1347#endif
1348 }
1349 }
1350 spin_lock(&uap->port.lock);
1351}
1352
1353static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1354 bool from_irq)
1355{
1356 if (unlikely(!from_irq) &&
1357 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1358 return false; /* unable to transmit character */
1359
1360 pl011_write(c, uap, REG_DR);
1361 uap->port.icount.tx++;
1362
1363 return true;
1364}
1365
1366static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1367{
1368 struct circ_buf *xmit = &uap->port.state->xmit;
1369 int count = uap->fifosize >> 1;
1370
1371 if (uap->port.x_char) {
1372 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1373 return;
1374 uap->port.x_char = 0;
1375 --count;
1376 }
1377 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1378 pl011_stop_tx(&uap->port);
1379 return;
1380 }
1381
1382 /* If we are using DMA mode, try to send some characters. */
1383 if (pl011_dma_tx_irq(uap))
1384 return;
1385
1386 do {
1387 if (likely(from_irq) && count-- == 0)
1388 break;
1389
1390 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1391 break;
1392
1393 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1394 } while (!uart_circ_empty(xmit));
1395
1396 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1397 uart_write_wakeup(&uap->port);
1398
1399 if (uart_circ_empty(xmit))
1400 pl011_stop_tx(&uap->port);
1401}
1402
1403static void pl011_modem_status(struct uart_amba_port *uap)
1404{
1405 unsigned int status, delta;
1406
1407 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1408
1409 delta = status ^ uap->old_status;
1410 uap->old_status = status;
1411
1412 if (!delta)
1413 return;
1414
1415 if (delta & UART01x_FR_DCD)
1416 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1417
1418 if (delta & UART01x_FR_DSR)
1419 uap->port.icount.dsr++;
1420
1421 if (delta & UART01x_FR_CTS)
1422 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1423
1424 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1425}
1426
1427static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1428{
1429 unsigned int dummy_read;
1430
1431 if (!uap->vendor->cts_event_workaround)
1432 return;
1433
1434 /* workaround to make sure that all bits are unlocked.. */
1435 pl011_write(0x00, uap, REG_ICR);
1436
1437 /*
1438 * WA: introduce 26ns(1 uart clk) delay before W1C;
1439 * single apb access will incur 2 pclk(133.12Mhz) delay,
1440 * so add 2 dummy reads
1441 */
1442 dummy_read = pl011_read(uap, REG_ICR);
1443 dummy_read = pl011_read(uap, REG_ICR);
1444}
1445
1446static irqreturn_t pl011_int(int irq, void *dev_id)
1447{
1448 struct uart_amba_port *uap = dev_id;
1449 unsigned long flags;
1450 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1451 u16 imsc;
1452 int handled = 0;
1453
1454 spin_lock_irqsave(&uap->port.lock, flags);
1455 imsc = pl011_read(uap, REG_IMSC);
1456 status = pl011_read(uap, REG_RIS) & imsc;
1457 if (status) {
1458 do {
1459 check_apply_cts_event_workaround(uap);
1460
1461 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1462 UART011_RXIS),
1463 uap, REG_ICR);
1464
1465 if (status & (UART011_RTIS|UART011_RXIS)) {
1466 if (pl011_dma_rx_running(uap))
1467 pl011_dma_rx_irq(uap);
1468 else
1469 pl011_rx_chars(uap);
1470 }
1471 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1472 UART011_CTSMIS|UART011_RIMIS))
1473 pl011_modem_status(uap);
1474 if (status & UART011_TXIS)
1475 pl011_tx_chars(uap, true);
1476
1477 if (pass_counter-- == 0)
1478 break;
1479
1480 status = pl011_read(uap, REG_RIS) & imsc;
1481 } while (status != 0);
1482 handled = 1;
1483 }
1484
1485 spin_unlock_irqrestore(&uap->port.lock, flags);
1486
1487 return IRQ_RETVAL(handled);
1488}
1489
1490static unsigned int pl011_tx_empty(struct uart_port *port)
1491{
1492 struct uart_amba_port *uap =
1493 container_of(port, struct uart_amba_port, port);
1494 unsigned int status = pl011_read(uap, REG_FR);
1495 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1496}
1497
1498static unsigned int pl011_get_mctrl(struct uart_port *port)
1499{
1500 struct uart_amba_port *uap =
1501 container_of(port, struct uart_amba_port, port);
1502 unsigned int result = 0;
1503 unsigned int status = pl011_read(uap, REG_FR);
1504
1505#define TIOCMBIT(uartbit, tiocmbit) \
1506 if (status & uartbit) \
1507 result |= tiocmbit
1508
1509 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1510 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1511 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1512 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1513#undef TIOCMBIT
1514 return result;
1515}
1516
1517static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1518{
1519 struct uart_amba_port *uap =
1520 container_of(port, struct uart_amba_port, port);
1521 unsigned int cr;
1522
1523 cr = pl011_read(uap, REG_CR);
1524
1525#define TIOCMBIT(tiocmbit, uartbit) \
1526 if (mctrl & tiocmbit) \
1527 cr |= uartbit; \
1528 else \
1529 cr &= ~uartbit
1530
1531 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1532 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1533 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1534 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1535 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1536
1537 if (uap->autorts) {
1538 /* We need to disable auto-RTS if we want to turn RTS off */
1539 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1540 }
1541#undef TIOCMBIT
1542
1543 pl011_write(cr, uap, REG_CR);
1544}
1545
1546static void pl011_break_ctl(struct uart_port *port, int break_state)
1547{
1548 struct uart_amba_port *uap =
1549 container_of(port, struct uart_amba_port, port);
1550 unsigned long flags;
1551 unsigned int lcr_h;
1552
1553 spin_lock_irqsave(&uap->port.lock, flags);
1554 lcr_h = pl011_read(uap, REG_LCRH_TX);
1555 if (break_state == -1)
1556 lcr_h |= UART01x_LCRH_BRK;
1557 else
1558 lcr_h &= ~UART01x_LCRH_BRK;
1559 pl011_write(lcr_h, uap, REG_LCRH_TX);
1560 spin_unlock_irqrestore(&uap->port.lock, flags);
1561}
1562
1563#ifdef CONFIG_CONSOLE_POLL
1564
1565static void pl011_quiesce_irqs(struct uart_port *port)
1566{
1567 struct uart_amba_port *uap =
1568 container_of(port, struct uart_amba_port, port);
1569
1570 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1571 /*
1572 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1573 * we simply mask it. start_tx() will unmask it.
1574 *
1575 * Note we can race with start_tx(), and if the race happens, the
1576 * polling user might get another interrupt just after we clear it.
1577 * But it should be OK and can happen even w/o the race, e.g.
1578 * controller immediately got some new data and raised the IRQ.
1579 *
1580 * And whoever uses polling routines assumes that it manages the device
1581 * (including tx queue), so we're also fine with start_tx()'s caller
1582 * side.
1583 */
1584 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1585 REG_IMSC);
1586}
1587
1588static int pl011_get_poll_char(struct uart_port *port)
1589{
1590 struct uart_amba_port *uap =
1591 container_of(port, struct uart_amba_port, port);
1592 unsigned int status;
1593
1594 /*
1595 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1596 * debugger.
1597 */
1598 pl011_quiesce_irqs(port);
1599
1600 status = pl011_read(uap, REG_FR);
1601 if (status & UART01x_FR_RXFE)
1602 return NO_POLL_CHAR;
1603
1604 return pl011_read(uap, REG_DR);
1605}
1606
1607static void pl011_put_poll_char(struct uart_port *port,
1608 unsigned char ch)
1609{
1610 struct uart_amba_port *uap =
1611 container_of(port, struct uart_amba_port, port);
1612
1613 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1614 cpu_relax();
1615
1616 pl011_write(ch, uap, REG_DR);
1617}
1618
1619#endif /* CONFIG_CONSOLE_POLL */
1620
1621static int pl011_hwinit(struct uart_port *port)
1622{
1623 struct uart_amba_port *uap =
1624 container_of(port, struct uart_amba_port, port);
1625 int retval;
1626
1627 /* Optionaly enable pins to be muxed in and configured */
1628 pinctrl_pm_select_default_state(port->dev);
1629
1630 /*
1631 * Try to enable the clock producer.
1632 */
1633 retval = clk_prepare_enable(uap->clk);
1634 if (retval)
1635 return retval;
1636
1637 uap->port.uartclk = clk_get_rate(uap->clk);
1638
1639 /* Clear pending error and receive interrupts */
1640 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1641 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1642 uap, REG_ICR);
1643
1644 /*
1645 * Save interrupts enable mask, and enable RX interrupts in case if
1646 * the interrupt is used for NMI entry.
1647 */
1648 uap->im = pl011_read(uap, REG_IMSC);
1649 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1650
1651 if (dev_get_platdata(uap->port.dev)) {
1652 struct amba_pl011_data *plat;
1653
1654 plat = dev_get_platdata(uap->port.dev);
1655 if (plat->init)
1656 plat->init();
1657 }
1658 return 0;
1659}
1660
1661static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1662{
1663 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1664 pl011_reg_to_offset(uap, REG_LCRH_TX);
1665}
1666
1667static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1668{
1669 pl011_write(lcr_h, uap, REG_LCRH_RX);
1670 if (pl011_split_lcrh(uap)) {
1671 int i;
1672 /*
1673 * Wait 10 PCLKs before writing LCRH_TX register,
1674 * to get this delay write read only register 10 times
1675 */
1676 for (i = 0; i < 10; ++i)
1677 pl011_write(0xff, uap, REG_MIS);
1678 pl011_write(lcr_h, uap, REG_LCRH_TX);
1679 }
1680}
1681
1682static int pl011_allocate_irq(struct uart_amba_port *uap)
1683{
1684 pl011_write(uap->im, uap, REG_IMSC);
1685
1686 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1687}
1688
1689/*
1690 * Enable interrupts, only timeouts when using DMA
1691 * if initial RX DMA job failed, start in interrupt mode
1692 * as well.
1693 */
1694static void pl011_enable_interrupts(struct uart_amba_port *uap)
1695{
1696 spin_lock_irq(&uap->port.lock);
1697
1698 /* Clear out any spuriously appearing RX interrupts */
1699 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1700 uap->im = UART011_RTIM;
1701 if (!pl011_dma_rx_running(uap))
1702 uap->im |= UART011_RXIM;
1703 pl011_write(uap->im, uap, REG_IMSC);
1704 spin_unlock_irq(&uap->port.lock);
1705}
1706
1707static int pl011_startup(struct uart_port *port)
1708{
1709 struct uart_amba_port *uap =
1710 container_of(port, struct uart_amba_port, port);
1711 unsigned int cr;
1712 int retval;
1713
1714 retval = pl011_hwinit(port);
1715 if (retval)
1716 goto clk_dis;
1717
1718 retval = pl011_allocate_irq(uap);
1719 if (retval)
1720 goto clk_dis;
1721
1722 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1723
1724 spin_lock_irq(&uap->port.lock);
1725
1726 /* restore RTS and DTR */
1727 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1728 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1729 pl011_write(cr, uap, REG_CR);
1730
1731 spin_unlock_irq(&uap->port.lock);
1732
1733 /*
1734 * initialise the old status of the modem signals
1735 */
1736 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1737
1738 /* Startup DMA */
1739 pl011_dma_startup(uap);
1740
1741 pl011_enable_interrupts(uap);
1742
1743 return 0;
1744
1745 clk_dis:
1746 clk_disable_unprepare(uap->clk);
1747 return retval;
1748}
1749
1750static int sbsa_uart_startup(struct uart_port *port)
1751{
1752 struct uart_amba_port *uap =
1753 container_of(port, struct uart_amba_port, port);
1754 int retval;
1755
1756 retval = pl011_hwinit(port);
1757 if (retval)
1758 return retval;
1759
1760 retval = pl011_allocate_irq(uap);
1761 if (retval)
1762 return retval;
1763
1764 /* The SBSA UART does not support any modem status lines. */
1765 uap->old_status = 0;
1766
1767 pl011_enable_interrupts(uap);
1768
1769 return 0;
1770}
1771
1772static void pl011_shutdown_channel(struct uart_amba_port *uap,
1773 unsigned int lcrh)
1774{
1775 unsigned long val;
1776
1777 val = pl011_read(uap, lcrh);
1778 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1779 pl011_write(val, uap, lcrh);
1780}
1781
1782/*
1783 * disable the port. It should not disable RTS and DTR.
1784 * Also RTS and DTR state should be preserved to restore
1785 * it during startup().
1786 */
1787static void pl011_disable_uart(struct uart_amba_port *uap)
1788{
1789 unsigned int cr;
1790
1791 uap->autorts = false;
1792 spin_lock_irq(&uap->port.lock);
1793 cr = pl011_read(uap, REG_CR);
1794 uap->old_cr = cr;
1795 cr &= UART011_CR_RTS | UART011_CR_DTR;
1796 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1797 pl011_write(cr, uap, REG_CR);
1798 spin_unlock_irq(&uap->port.lock);
1799
1800 /*
1801 * disable break condition and fifos
1802 */
1803 pl011_shutdown_channel(uap, REG_LCRH_RX);
1804 if (pl011_split_lcrh(uap))
1805 pl011_shutdown_channel(uap, REG_LCRH_TX);
1806}
1807
1808static void pl011_disable_interrupts(struct uart_amba_port *uap)
1809{
1810 spin_lock_irq(&uap->port.lock);
1811
1812 /* mask all interrupts and clear all pending ones */
1813 uap->im = 0;
1814 pl011_write(uap->im, uap, REG_IMSC);
1815 pl011_write(0xffff, uap, REG_ICR);
1816
1817 spin_unlock_irq(&uap->port.lock);
1818}
1819
1820static void pl011_shutdown(struct uart_port *port)
1821{
1822 struct uart_amba_port *uap =
1823 container_of(port, struct uart_amba_port, port);
1824
1825 pl011_disable_interrupts(uap);
1826
1827 pl011_dma_shutdown(uap);
1828
1829 free_irq(uap->port.irq, uap);
1830
1831 pl011_disable_uart(uap);
1832
1833 /*
1834 * Shut down the clock producer
1835 */
1836 clk_disable_unprepare(uap->clk);
1837 /* Optionally let pins go into sleep states */
1838 pinctrl_pm_select_sleep_state(port->dev);
1839
1840 if (dev_get_platdata(uap->port.dev)) {
1841 struct amba_pl011_data *plat;
1842
1843 plat = dev_get_platdata(uap->port.dev);
1844 if (plat->exit)
1845 plat->exit();
1846 }
1847
1848 if (uap->port.ops->flush_buffer)
1849 uap->port.ops->flush_buffer(port);
1850}
1851
1852static void sbsa_uart_shutdown(struct uart_port *port)
1853{
1854 struct uart_amba_port *uap =
1855 container_of(port, struct uart_amba_port, port);
1856
1857 pl011_disable_interrupts(uap);
1858
1859 free_irq(uap->port.irq, uap);
1860
1861 if (uap->port.ops->flush_buffer)
1862 uap->port.ops->flush_buffer(port);
1863}
1864
1865static void
1866pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1867{
1868 port->read_status_mask = UART011_DR_OE | 255;
1869 if (termios->c_iflag & INPCK)
1870 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1871 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1872 port->read_status_mask |= UART011_DR_BE;
1873
1874 /*
1875 * Characters to ignore
1876 */
1877 port->ignore_status_mask = 0;
1878 if (termios->c_iflag & IGNPAR)
1879 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1880 if (termios->c_iflag & IGNBRK) {
1881 port->ignore_status_mask |= UART011_DR_BE;
1882 /*
1883 * If we're ignoring parity and break indicators,
1884 * ignore overruns too (for real raw support).
1885 */
1886 if (termios->c_iflag & IGNPAR)
1887 port->ignore_status_mask |= UART011_DR_OE;
1888 }
1889
1890 /*
1891 * Ignore all characters if CREAD is not set.
1892 */
1893 if ((termios->c_cflag & CREAD) == 0)
1894 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1895}
1896
1897static void
1898pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1899 struct ktermios *old)
1900{
1901 struct uart_amba_port *uap =
1902 container_of(port, struct uart_amba_port, port);
1903 unsigned int lcr_h, old_cr;
1904 unsigned long flags;
1905 unsigned int baud, quot, clkdiv;
1906
1907 if (uap->vendor->oversampling)
1908 clkdiv = 8;
1909 else
1910 clkdiv = 16;
1911
1912 /*
1913 * Ask the core to calculate the divisor for us.
1914 */
1915 baud = uart_get_baud_rate(port, termios, old, 0,
1916 port->uartclk / clkdiv);
1917#ifdef CONFIG_DMA_ENGINE
1918 /*
1919 * Adjust RX DMA polling rate with baud rate if not specified.
1920 */
1921 if (uap->dmarx.auto_poll_rate)
1922 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1923#endif
1924
1925 if (baud > port->uartclk/16)
1926 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1927 else
1928 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1929
1930 switch (termios->c_cflag & CSIZE) {
1931 case CS5:
1932 lcr_h = UART01x_LCRH_WLEN_5;
1933 break;
1934 case CS6:
1935 lcr_h = UART01x_LCRH_WLEN_6;
1936 break;
1937 case CS7:
1938 lcr_h = UART01x_LCRH_WLEN_7;
1939 break;
1940 default: // CS8
1941 lcr_h = UART01x_LCRH_WLEN_8;
1942 break;
1943 }
1944 if (termios->c_cflag & CSTOPB)
1945 lcr_h |= UART01x_LCRH_STP2;
1946 if (termios->c_cflag & PARENB) {
1947 lcr_h |= UART01x_LCRH_PEN;
1948 if (!(termios->c_cflag & PARODD))
1949 lcr_h |= UART01x_LCRH_EPS;
1950 if (termios->c_cflag & CMSPAR)
1951 lcr_h |= UART011_LCRH_SPS;
1952 }
1953 if (uap->fifosize > 1)
1954 lcr_h |= UART01x_LCRH_FEN;
1955
1956 spin_lock_irqsave(&port->lock, flags);
1957
1958 /*
1959 * Update the per-port timeout.
1960 */
1961 uart_update_timeout(port, termios->c_cflag, baud);
1962
1963 pl011_setup_status_masks(port, termios);
1964
1965 if (UART_ENABLE_MS(port, termios->c_cflag))
1966 pl011_enable_ms(port);
1967
1968 /* first, disable everything */
1969 old_cr = pl011_read(uap, REG_CR);
1970 pl011_write(0, uap, REG_CR);
1971
1972 if (termios->c_cflag & CRTSCTS) {
1973 if (old_cr & UART011_CR_RTS)
1974 old_cr |= UART011_CR_RTSEN;
1975
1976 old_cr |= UART011_CR_CTSEN;
1977 uap->autorts = true;
1978 } else {
1979 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1980 uap->autorts = false;
1981 }
1982
1983 if (uap->vendor->oversampling) {
1984 if (baud > port->uartclk / 16)
1985 old_cr |= ST_UART011_CR_OVSFACT;
1986 else
1987 old_cr &= ~ST_UART011_CR_OVSFACT;
1988 }
1989
1990 /*
1991 * Workaround for the ST Micro oversampling variants to
1992 * increase the bitrate slightly, by lowering the divisor,
1993 * to avoid delayed sampling of start bit at high speeds,
1994 * else we see data corruption.
1995 */
1996 if (uap->vendor->oversampling) {
1997 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1998 quot -= 1;
1999 else if ((baud > 3250000) && (quot > 2))
2000 quot -= 2;
2001 }
2002 /* Set baud rate */
2003 pl011_write(quot & 0x3f, uap, REG_FBRD);
2004 pl011_write(quot >> 6, uap, REG_IBRD);
2005
2006 /*
2007 * ----------v----------v----------v----------v-----
2008 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2009 * REG_FBRD & REG_IBRD.
2010 * ----------^----------^----------^----------^-----
2011 */
2012 pl011_write_lcr_h(uap, lcr_h);
2013 pl011_write(old_cr, uap, REG_CR);
2014
2015 spin_unlock_irqrestore(&port->lock, flags);
2016}
2017
2018static void
2019sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2020 struct ktermios *old)
2021{
2022 struct uart_amba_port *uap =
2023 container_of(port, struct uart_amba_port, port);
2024 unsigned long flags;
2025
2026 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2027
2028 /* The SBSA UART only supports 8n1 without hardware flow control. */
2029 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2030 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2031 termios->c_cflag |= CS8 | CLOCAL;
2032
2033 spin_lock_irqsave(&port->lock, flags);
2034 uart_update_timeout(port, CS8, uap->fixed_baud);
2035 pl011_setup_status_masks(port, termios);
2036 spin_unlock_irqrestore(&port->lock, flags);
2037}
2038
2039static const char *pl011_type(struct uart_port *port)
2040{
2041 struct uart_amba_port *uap =
2042 container_of(port, struct uart_amba_port, port);
2043 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2044}
2045
2046/*
2047 * Release the memory region(s) being used by 'port'
2048 */
2049static void pl011_release_port(struct uart_port *port)
2050{
2051 release_mem_region(port->mapbase, SZ_4K);
2052}
2053
2054/*
2055 * Request the memory region(s) being used by 'port'
2056 */
2057static int pl011_request_port(struct uart_port *port)
2058{
2059 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2060 != NULL ? 0 : -EBUSY;
2061}
2062
2063/*
2064 * Configure/autoconfigure the port.
2065 */
2066static void pl011_config_port(struct uart_port *port, int flags)
2067{
2068 if (flags & UART_CONFIG_TYPE) {
2069 port->type = PORT_AMBA;
2070 pl011_request_port(port);
2071 }
2072}
2073
2074/*
2075 * verify the new serial_struct (for TIOCSSERIAL).
2076 */
2077static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2078{
2079 int ret = 0;
2080 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2081 ret = -EINVAL;
2082 if (ser->irq < 0 || ser->irq >= nr_irqs)
2083 ret = -EINVAL;
2084 if (ser->baud_base < 9600)
2085 ret = -EINVAL;
2086 return ret;
2087}
2088
2089static struct uart_ops amba_pl011_pops = {
2090 .tx_empty = pl011_tx_empty,
2091 .set_mctrl = pl011_set_mctrl,
2092 .get_mctrl = pl011_get_mctrl,
2093 .stop_tx = pl011_stop_tx,
2094 .start_tx = pl011_start_tx,
2095 .stop_rx = pl011_stop_rx,
2096 .enable_ms = pl011_enable_ms,
2097 .break_ctl = pl011_break_ctl,
2098 .startup = pl011_startup,
2099 .shutdown = pl011_shutdown,
2100 .flush_buffer = pl011_dma_flush_buffer,
2101 .set_termios = pl011_set_termios,
2102 .type = pl011_type,
2103 .release_port = pl011_release_port,
2104 .request_port = pl011_request_port,
2105 .config_port = pl011_config_port,
2106 .verify_port = pl011_verify_port,
2107#ifdef CONFIG_CONSOLE_POLL
2108 .poll_init = pl011_hwinit,
2109 .poll_get_char = pl011_get_poll_char,
2110 .poll_put_char = pl011_put_poll_char,
2111#endif
2112};
2113
2114static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2115{
2116}
2117
2118static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2119{
2120 return 0;
2121}
2122
2123static const struct uart_ops sbsa_uart_pops = {
2124 .tx_empty = pl011_tx_empty,
2125 .set_mctrl = sbsa_uart_set_mctrl,
2126 .get_mctrl = sbsa_uart_get_mctrl,
2127 .stop_tx = pl011_stop_tx,
2128 .start_tx = pl011_start_tx,
2129 .stop_rx = pl011_stop_rx,
2130 .startup = sbsa_uart_startup,
2131 .shutdown = sbsa_uart_shutdown,
2132 .set_termios = sbsa_uart_set_termios,
2133 .type = pl011_type,
2134 .release_port = pl011_release_port,
2135 .request_port = pl011_request_port,
2136 .config_port = pl011_config_port,
2137 .verify_port = pl011_verify_port,
2138#ifdef CONFIG_CONSOLE_POLL
2139 .poll_init = pl011_hwinit,
2140 .poll_get_char = pl011_get_poll_char,
2141 .poll_put_char = pl011_put_poll_char,
2142#endif
2143};
2144
2145static struct uart_amba_port *amba_ports[UART_NR];
2146
2147#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2148
2149static void pl011_console_putchar(struct uart_port *port, int ch)
2150{
2151 struct uart_amba_port *uap =
2152 container_of(port, struct uart_amba_port, port);
2153
2154 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2155 cpu_relax();
2156 pl011_write(ch, uap, REG_DR);
2157}
2158
2159static void
2160pl011_console_write(struct console *co, const char *s, unsigned int count)
2161{
2162 struct uart_amba_port *uap = amba_ports[co->index];
2163 unsigned int old_cr = 0, new_cr;
2164 unsigned long flags;
2165 int locked = 1;
2166
2167 clk_enable(uap->clk);
2168
2169 local_irq_save(flags);
2170 if (uap->port.sysrq)
2171 locked = 0;
2172 else if (oops_in_progress)
2173 locked = spin_trylock(&uap->port.lock);
2174 else
2175 spin_lock(&uap->port.lock);
2176
2177 /*
2178 * First save the CR then disable the interrupts
2179 */
2180 if (!uap->vendor->always_enabled) {
2181 old_cr = pl011_read(uap, REG_CR);
2182 new_cr = old_cr & ~UART011_CR_CTSEN;
2183 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2184 pl011_write(new_cr, uap, REG_CR);
2185 }
2186
2187 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2188
2189 /*
2190 * Finally, wait for transmitter to become empty
2191 * and restore the TCR
2192 */
2193 while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY)
2194 cpu_relax();
2195 if (!uap->vendor->always_enabled)
2196 pl011_write(old_cr, uap, REG_CR);
2197
2198 if (locked)
2199 spin_unlock(&uap->port.lock);
2200 local_irq_restore(flags);
2201
2202 clk_disable(uap->clk);
2203}
2204
2205static void __init
2206pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2207 int *parity, int *bits)
2208{
2209 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2210 unsigned int lcr_h, ibrd, fbrd;
2211
2212 lcr_h = pl011_read(uap, REG_LCRH_TX);
2213
2214 *parity = 'n';
2215 if (lcr_h & UART01x_LCRH_PEN) {
2216 if (lcr_h & UART01x_LCRH_EPS)
2217 *parity = 'e';
2218 else
2219 *parity = 'o';
2220 }
2221
2222 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2223 *bits = 7;
2224 else
2225 *bits = 8;
2226
2227 ibrd = pl011_read(uap, REG_IBRD);
2228 fbrd = pl011_read(uap, REG_FBRD);
2229
2230 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2231
2232 if (uap->vendor->oversampling) {
2233 if (pl011_read(uap, REG_CR)
2234 & ST_UART011_CR_OVSFACT)
2235 *baud *= 2;
2236 }
2237 }
2238}
2239
2240static int __init pl011_console_setup(struct console *co, char *options)
2241{
2242 struct uart_amba_port *uap;
2243 int baud = 38400;
2244 int bits = 8;
2245 int parity = 'n';
2246 int flow = 'n';
2247 int ret;
2248
2249 /*
2250 * Check whether an invalid uart number has been specified, and
2251 * if so, search for the first available port that does have
2252 * console support.
2253 */
2254 if (co->index >= UART_NR)
2255 co->index = 0;
2256 uap = amba_ports[co->index];
2257 if (!uap)
2258 return -ENODEV;
2259
2260 /* Allow pins to be muxed in and configured */
2261 pinctrl_pm_select_default_state(uap->port.dev);
2262
2263 ret = clk_prepare(uap->clk);
2264 if (ret)
2265 return ret;
2266
2267 if (dev_get_platdata(uap->port.dev)) {
2268 struct amba_pl011_data *plat;
2269
2270 plat = dev_get_platdata(uap->port.dev);
2271 if (plat->init)
2272 plat->init();
2273 }
2274
2275 uap->port.uartclk = clk_get_rate(uap->clk);
2276
2277 if (uap->vendor->fixed_options) {
2278 baud = uap->fixed_baud;
2279 } else {
2280 if (options)
2281 uart_parse_options(options,
2282 &baud, &parity, &bits, &flow);
2283 else
2284 pl011_console_get_options(uap, &baud, &parity, &bits);
2285 }
2286
2287 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2288}
2289
2290static struct uart_driver amba_reg;
2291static struct console amba_console = {
2292 .name = "ttyAMA",
2293 .write = pl011_console_write,
2294 .device = uart_console_device,
2295 .setup = pl011_console_setup,
2296 .flags = CON_PRINTBUFFER,
2297 .index = -1,
2298 .data = &amba_reg,
2299};
2300
2301#define AMBA_CONSOLE (&amba_console)
2302
2303static void pl011_putc(struct uart_port *port, int c)
2304{
2305 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2306 cpu_relax();
2307 if (port->iotype == UPIO_MEM32)
2308 writel(c, port->membase + UART01x_DR);
2309 else
2310 writeb(c, port->membase + UART01x_DR);
2311 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2312 cpu_relax();
2313}
2314
2315static void pl011_early_write(struct console *con, const char *s, unsigned n)
2316{
2317 struct earlycon_device *dev = con->data;
2318
2319 uart_console_write(&dev->port, s, n, pl011_putc);
2320}
2321
2322static int __init pl011_early_console_setup(struct earlycon_device *device,
2323 const char *opt)
2324{
2325 if (!device->port.membase)
2326 return -ENODEV;
2327
2328 device->con->write = pl011_early_write;
2329 return 0;
2330}
2331OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2332
2333#else
2334#define AMBA_CONSOLE NULL
2335#endif
2336
2337static struct uart_driver amba_reg = {
2338 .owner = THIS_MODULE,
2339 .driver_name = "ttyAMA",
2340 .dev_name = "ttyAMA",
2341 .major = SERIAL_AMBA_MAJOR,
2342 .minor = SERIAL_AMBA_MINOR,
2343 .nr = UART_NR,
2344 .cons = AMBA_CONSOLE,
2345};
2346
2347static int pl011_probe_dt_alias(int index, struct device *dev)
2348{
2349 struct device_node *np;
2350 static bool seen_dev_with_alias = false;
2351 static bool seen_dev_without_alias = false;
2352 int ret = index;
2353
2354 if (!IS_ENABLED(CONFIG_OF))
2355 return ret;
2356
2357 np = dev->of_node;
2358 if (!np)
2359 return ret;
2360
2361 ret = of_alias_get_id(np, "serial");
2362 if (IS_ERR_VALUE(ret)) {
2363 seen_dev_without_alias = true;
2364 ret = index;
2365 } else {
2366 seen_dev_with_alias = true;
2367 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2368 dev_warn(dev, "requested serial port %d not available.\n", ret);
2369 ret = index;
2370 }
2371 }
2372
2373 if (seen_dev_with_alias && seen_dev_without_alias)
2374 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2375
2376 return ret;
2377}
2378
2379/* unregisters the driver also if no more ports are left */
2380static void pl011_unregister_port(struct uart_amba_port *uap)
2381{
2382 int i;
2383 bool busy = false;
2384
2385 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2386 if (amba_ports[i] == uap)
2387 amba_ports[i] = NULL;
2388 else if (amba_ports[i])
2389 busy = true;
2390 }
2391 pl011_dma_remove(uap);
2392 if (!busy)
2393 uart_unregister_driver(&amba_reg);
2394}
2395
2396static int pl011_find_free_port(void)
2397{
2398 int i;
2399
2400 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2401 if (amba_ports[i] == NULL)
2402 return i;
2403
2404 return -EBUSY;
2405}
2406
2407static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2408 struct resource *mmiobase, int index)
2409{
2410 void __iomem *base;
2411
2412 base = devm_ioremap_resource(dev, mmiobase);
2413 if (IS_ERR(base))
2414 return PTR_ERR(base);
2415
2416 index = pl011_probe_dt_alias(index, dev);
2417
2418 uap->old_cr = 0;
2419 uap->port.dev = dev;
2420 uap->port.mapbase = mmiobase->start;
2421 uap->port.membase = base;
2422 uap->port.fifosize = uap->fifosize;
2423 uap->port.flags = UPF_BOOT_AUTOCONF;
2424 uap->port.line = index;
2425
2426 amba_ports[index] = uap;
2427
2428 return 0;
2429}
2430
2431static int pl011_register_port(struct uart_amba_port *uap)
2432{
2433 int ret;
2434
2435 /* Ensure interrupts from this UART are masked and cleared */
2436 pl011_write(0, uap, REG_IMSC);
2437 pl011_write(0xffff, uap, REG_ICR);
2438
2439 if (!amba_reg.state) {
2440 ret = uart_register_driver(&amba_reg);
2441 if (ret < 0) {
2442 dev_err(uap->port.dev,
2443 "Failed to register AMBA-PL011 driver\n");
2444 return ret;
2445 }
2446 }
2447
2448 ret = uart_add_one_port(&amba_reg, &uap->port);
2449 if (ret)
2450 pl011_unregister_port(uap);
2451
2452 return ret;
2453}
2454
2455static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2456{
2457 struct uart_amba_port *uap;
2458 struct vendor_data *vendor = id->data;
2459 int portnr, ret;
2460
2461 portnr = pl011_find_free_port();
2462 if (portnr < 0)
2463 return portnr;
2464
2465 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2466 GFP_KERNEL);
2467 if (!uap)
2468 return -ENOMEM;
2469
2470 uap->clk = devm_clk_get(&dev->dev, NULL);
2471 if (IS_ERR(uap->clk))
2472 return PTR_ERR(uap->clk);
2473
2474 uap->reg_offset = vendor->reg_offset;
2475 uap->vendor = vendor;
2476 uap->fifosize = vendor->get_fifosize(dev);
2477 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2478 uap->port.irq = dev->irq[0];
2479 uap->port.ops = &amba_pl011_pops;
2480
2481 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2482
2483 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2484 if (ret)
2485 return ret;
2486
2487 amba_set_drvdata(dev, uap);
2488
2489 return pl011_register_port(uap);
2490}
2491
2492static int pl011_remove(struct amba_device *dev)
2493{
2494 struct uart_amba_port *uap = amba_get_drvdata(dev);
2495
2496 uart_remove_one_port(&amba_reg, &uap->port);
2497 pl011_unregister_port(uap);
2498 return 0;
2499}
2500
2501#ifdef CONFIG_PM_SLEEP
2502static int pl011_suspend(struct device *dev)
2503{
2504 struct uart_amba_port *uap = dev_get_drvdata(dev);
2505
2506 if (!uap)
2507 return -EINVAL;
2508
2509 return uart_suspend_port(&amba_reg, &uap->port);
2510}
2511
2512static int pl011_resume(struct device *dev)
2513{
2514 struct uart_amba_port *uap = dev_get_drvdata(dev);
2515
2516 if (!uap)
2517 return -EINVAL;
2518
2519 return uart_resume_port(&amba_reg, &uap->port);
2520}
2521#endif
2522
2523static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2524
2525static int sbsa_uart_probe(struct platform_device *pdev)
2526{
2527 struct uart_amba_port *uap;
2528 struct resource *r;
2529 int portnr, ret;
2530 int baudrate;
2531
2532 /*
2533 * Check the mandatory baud rate parameter in the DT node early
2534 * so that we can easily exit with the error.
2535 */
2536 if (pdev->dev.of_node) {
2537 struct device_node *np = pdev->dev.of_node;
2538
2539 ret = of_property_read_u32(np, "current-speed", &baudrate);
2540 if (ret)
2541 return ret;
2542 } else {
2543 baudrate = 115200;
2544 }
2545
2546 portnr = pl011_find_free_port();
2547 if (portnr < 0)
2548 return portnr;
2549
2550 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2551 GFP_KERNEL);
2552 if (!uap)
2553 return -ENOMEM;
2554
2555 uap->reg_offset = vendor_sbsa.reg_offset;
2556 uap->vendor = &vendor_sbsa;
2557 uap->fifosize = 32;
2558 uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM;
2559 uap->port.irq = platform_get_irq(pdev, 0);
2560 uap->port.ops = &sbsa_uart_pops;
2561 uap->fixed_baud = baudrate;
2562
2563 snprintf(uap->type, sizeof(uap->type), "SBSA");
2564
2565 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2566
2567 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2568 if (ret)
2569 return ret;
2570
2571 platform_set_drvdata(pdev, uap);
2572
2573 return pl011_register_port(uap);
2574}
2575
2576static int sbsa_uart_remove(struct platform_device *pdev)
2577{
2578 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2579
2580 uart_remove_one_port(&amba_reg, &uap->port);
2581 pl011_unregister_port(uap);
2582 return 0;
2583}
2584
2585static const struct of_device_id sbsa_uart_of_match[] = {
2586 { .compatible = "arm,sbsa-uart", },
2587 {},
2588};
2589MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2590
2591static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2592 { "ARMH0011", 0 },
2593 {},
2594};
2595MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2596
2597static struct platform_driver arm_sbsa_uart_platform_driver = {
2598 .probe = sbsa_uart_probe,
2599 .remove = sbsa_uart_remove,
2600 .driver = {
2601 .name = "sbsa-uart",
2602 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2603 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2604 },
2605};
2606
2607static struct amba_id pl011_ids[] = {
2608 {
2609 .id = 0x00041011,
2610 .mask = 0x000fffff,
2611 .data = &vendor_arm,
2612 },
2613 {
2614 .id = 0x00380802,
2615 .mask = 0x00ffffff,
2616 .data = &vendor_st,
2617 },
2618 { 0, 0 },
2619};
2620
2621MODULE_DEVICE_TABLE(amba, pl011_ids);
2622
2623static struct amba_driver pl011_driver = {
2624 .drv = {
2625 .name = "uart-pl011",
2626 .pm = &pl011_dev_pm_ops,
2627 },
2628 .id_table = pl011_ids,
2629 .probe = pl011_probe,
2630 .remove = pl011_remove,
2631};
2632
2633static int __init pl011_init(void)
2634{
2635 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2636
2637 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2638 pr_warn("could not register SBSA UART platform driver\n");
2639 return amba_driver_register(&pl011_driver);
2640}
2641
2642static void __exit pl011_exit(void)
2643{
2644 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2645 amba_driver_unregister(&pl011_driver);
2646}
2647
2648/*
2649 * While this can be a module, if builtin it's most likely the console
2650 * So let's leave module_exit but move module_init to an earlier place
2651 */
2652arch_initcall(pl011_init);
2653module_exit(pl011_exit);
2654
2655MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2656MODULE_DESCRIPTION("ARM AMBA serial port driver");
2657MODULE_LICENSE("GPL");