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1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/acpi.h>
24#include <linux/kallsyms.h>
25#include <linux/dmi.h>
26#include <linux/pci-aspm.h>
27#include <linux/ioport.h>
28#include <asm/dma.h> /* isa_dma_bridge_buggy */
29#include "pci.h"
30
31/*
32 * This quirk function disables memory decoding and releases memory resources
33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
34 * It also rounds up size to specified alignment.
35 * Later on, the kernel will assign page-aligned memory resource back
36 * to the device.
37 */
38static void __devinit quirk_resource_alignment(struct pci_dev *dev)
39{
40 int i;
41 struct resource *r;
42 resource_size_t align, size;
43 u16 command;
44
45 if (!pci_is_reassigndev(dev))
46 return;
47
48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
50 dev_warn(&dev->dev,
51 "Can't reassign resources to host bridge.\n");
52 return;
53 }
54
55 dev_info(&dev->dev,
56 "Disabling memory decoding and releasing memory resources.\n");
57 pci_read_config_word(dev, PCI_COMMAND, &command);
58 command &= ~PCI_COMMAND_MEMORY;
59 pci_write_config_word(dev, PCI_COMMAND, command);
60
61 align = pci_specified_resource_alignment(dev);
62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
63 r = &dev->resource[i];
64 if (!(r->flags & IORESOURCE_MEM))
65 continue;
66 size = resource_size(r);
67 if (size < align) {
68 size = align;
69 dev_info(&dev->dev,
70 "Rounding up size of resource #%d to %#llx.\n",
71 i, (unsigned long long)size);
72 }
73 r->end = size - 1;
74 r->start = 0;
75 }
76 /* Need to disable bridge's resource window,
77 * to enable the kernel to reassign new resource
78 * window later on.
79 */
80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
83 r = &dev->resource[i];
84 if (!(r->flags & IORESOURCE_MEM))
85 continue;
86 r->end = resource_size(r) - 1;
87 r->start = 0;
88 }
89 pci_disable_bridge_window(dev);
90 }
91}
92DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
93
94/*
95 * Decoding should be disabled for a PCI device during BAR sizing to avoid
96 * conflict. But doing so may cause problems on host bridge and perhaps other
97 * key system devices. For devices that need to have mmio decoding always-on,
98 * we need to set the dev->mmio_always_on bit.
99 */
100static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
101{
102 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
103 dev->mmio_always_on = 1;
104}
105DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on);
106
107/* The Mellanox Tavor device gives false positive parity errors
108 * Mark this device with a broken_parity_status, to allow
109 * PCI scanning code to "skip" this now blacklisted device.
110 */
111static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
112{
113 dev->broken_parity_status = 1; /* This device gives false positives */
114}
115DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
117
118/* Deal with broken BIOS'es that neglect to enable passive release,
119 which can cause problems in combination with the 82441FX/PPro MTRRs */
120static void quirk_passive_release(struct pci_dev *dev)
121{
122 struct pci_dev *d = NULL;
123 unsigned char dlc;
124
125 /* We have to make sure a particular bit is set in the PIIX3
126 ISA bridge, so we have to go out and find it. */
127 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
128 pci_read_config_byte(d, 0x82, &dlc);
129 if (!(dlc & 1<<1)) {
130 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
131 dlc |= 1<<1;
132 pci_write_config_byte(d, 0x82, dlc);
133 }
134 }
135}
136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
137DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
138
139/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
140 but VIA don't answer queries. If you happen to have good contacts at VIA
141 ask them for me please -- Alan
142
143 This appears to be BIOS not version dependent. So presumably there is a
144 chipset level fix */
145
146static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
147{
148 if (!isa_dma_bridge_buggy) {
149 isa_dma_bridge_buggy=1;
150 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
151 }
152}
153 /*
154 * Its not totally clear which chipsets are the problematic ones
155 * We know 82C586 and 82C596 variants are affected.
156 */
157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
164
165/*
166 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
167 * for some HT machines to use C4 w/o hanging.
168 */
169static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
170{
171 u32 pmbase;
172 u16 pm1a;
173
174 pci_read_config_dword(dev, 0x40, &pmbase);
175 pmbase = pmbase & 0xff80;
176 pm1a = inw(pmbase);
177
178 if (pm1a & 0x10) {
179 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
180 outw(0x10, pmbase);
181 }
182}
183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
184
185/*
186 * Chipsets where PCI->PCI transfers vanish or hang
187 */
188static void __devinit quirk_nopcipci(struct pci_dev *dev)
189{
190 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
191 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
192 pci_pci_problems |= PCIPCI_FAIL;
193 }
194}
195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
197
198static void __devinit quirk_nopciamd(struct pci_dev *dev)
199{
200 u8 rev;
201 pci_read_config_byte(dev, 0x08, &rev);
202 if (rev == 0x13) {
203 /* Erratum 24 */
204 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
205 pci_pci_problems |= PCIAGP_FAIL;
206 }
207}
208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
209
210/*
211 * Triton requires workarounds to be used by the drivers
212 */
213static void __devinit quirk_triton(struct pci_dev *dev)
214{
215 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
216 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
217 pci_pci_problems |= PCIPCI_TRITON;
218 }
219}
220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
224
225/*
226 * VIA Apollo KT133 needs PCI latency patch
227 * Made according to a windows driver based patch by George E. Breese
228 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
229 * and http://www.georgebreese.com/net/software/#PCI
230 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
231 * the info on which Mr Breese based his work.
232 *
233 * Updated based on further information from the site and also on
234 * information provided by VIA
235 */
236static void quirk_vialatency(struct pci_dev *dev)
237{
238 struct pci_dev *p;
239 u8 busarb;
240 /* Ok we have a potential problem chipset here. Now see if we have
241 a buggy southbridge */
242
243 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
244 if (p!=NULL) {
245 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
246 /* Check for buggy part revisions */
247 if (p->revision < 0x40 || p->revision > 0x42)
248 goto exit;
249 } else {
250 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
251 if (p==NULL) /* No problem parts */
252 goto exit;
253 /* Check for buggy part revisions */
254 if (p->revision < 0x10 || p->revision > 0x12)
255 goto exit;
256 }
257
258 /*
259 * Ok we have the problem. Now set the PCI master grant to
260 * occur every master grant. The apparent bug is that under high
261 * PCI load (quite common in Linux of course) you can get data
262 * loss when the CPU is held off the bus for 3 bus master requests
263 * This happens to include the IDE controllers....
264 *
265 * VIA only apply this fix when an SB Live! is present but under
266 * both Linux and Windows this isn't enough, and we have seen
267 * corruption without SB Live! but with things like 3 UDMA IDE
268 * controllers. So we ignore that bit of the VIA recommendation..
269 */
270
271 pci_read_config_byte(dev, 0x76, &busarb);
272 /* Set bit 4 and bi 5 of byte 76 to 0x01
273 "Master priority rotation on every PCI master grant */
274 busarb &= ~(1<<5);
275 busarb |= (1<<4);
276 pci_write_config_byte(dev, 0x76, busarb);
277 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
278exit:
279 pci_dev_put(p);
280}
281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
283DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
284/* Must restore this on a resume from RAM */
285DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
286DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
287DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
288
289/*
290 * VIA Apollo VP3 needs ETBF on BT848/878
291 */
292static void __devinit quirk_viaetbf(struct pci_dev *dev)
293{
294 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
295 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
296 pci_pci_problems |= PCIPCI_VIAETBF;
297 }
298}
299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
300
301static void __devinit quirk_vsfx(struct pci_dev *dev)
302{
303 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
304 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
305 pci_pci_problems |= PCIPCI_VSFX;
306 }
307}
308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
309
310/*
311 * Ali Magik requires workarounds to be used by the drivers
312 * that DMA to AGP space. Latency must be set to 0xA and triton
313 * workaround applied too
314 * [Info kindly provided by ALi]
315 */
316static void __init quirk_alimagik(struct pci_dev *dev)
317{
318 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
319 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
320 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
321 }
322}
323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
325
326/*
327 * Natoma has some interesting boundary conditions with Zoran stuff
328 * at least
329 */
330static void __devinit quirk_natoma(struct pci_dev *dev)
331{
332 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
333 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
334 pci_pci_problems |= PCIPCI_NATOMA;
335 }
336}
337DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
342DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
343
344/*
345 * This chip can cause PCI parity errors if config register 0xA0 is read
346 * while DMAs are occurring.
347 */
348static void __devinit quirk_citrine(struct pci_dev *dev)
349{
350 dev->cfg_size = 0xA0;
351}
352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
353
354/*
355 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
356 * If it's needed, re-allocate the region.
357 */
358static void __devinit quirk_s3_64M(struct pci_dev *dev)
359{
360 struct resource *r = &dev->resource[0];
361
362 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
363 r->start = 0;
364 r->end = 0x3ffffff;
365 }
366}
367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
369
370/*
371 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
372 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
373 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
374 * (which conflicts w/ BAR1's memory range).
375 */
376static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
377{
378 if (pci_resource_len(dev, 0) != 8) {
379 struct resource *res = &dev->resource[0];
380 res->end = res->start + 8 - 1;
381 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
382 "(incorrect header); workaround applied.\n");
383 }
384}
385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
386
387static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
388 unsigned size, int nr, const char *name)
389{
390 region &= ~(size-1);
391 if (region) {
392 struct pci_bus_region bus_region;
393 struct resource *res = dev->resource + nr;
394
395 res->name = pci_name(dev);
396 res->start = region;
397 res->end = region + size - 1;
398 res->flags = IORESOURCE_IO;
399
400 /* Convert from PCI bus to resource space. */
401 bus_region.start = res->start;
402 bus_region.end = res->end;
403 pcibios_bus_to_resource(dev, res, &bus_region);
404
405 if (pci_claim_resource(dev, nr) == 0)
406 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
407 res, name);
408 }
409}
410
411/*
412 * ATI Northbridge setups MCE the processor if you even
413 * read somewhere between 0x3b0->0x3bb or read 0x3d3
414 */
415static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
416{
417 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
418 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
419 request_region(0x3b0, 0x0C, "RadeonIGP");
420 request_region(0x3d3, 0x01, "RadeonIGP");
421}
422DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
423
424/*
425 * Let's make the southbridge information explicit instead
426 * of having to worry about people probing the ACPI areas,
427 * for example.. (Yes, it happens, and if you read the wrong
428 * ACPI register it will put the machine to sleep with no
429 * way of waking it up again. Bummer).
430 *
431 * ALI M7101: Two IO regions pointed to by words at
432 * 0xE0 (64 bytes of ACPI registers)
433 * 0xE2 (32 bytes of SMB registers)
434 */
435static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
436{
437 u16 region;
438
439 pci_read_config_word(dev, 0xE0, ®ion);
440 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
441 pci_read_config_word(dev, 0xE2, ®ion);
442 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
443}
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
445
446static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
447{
448 u32 devres;
449 u32 mask, size, base;
450
451 pci_read_config_dword(dev, port, &devres);
452 if ((devres & enable) != enable)
453 return;
454 mask = (devres >> 16) & 15;
455 base = devres & 0xffff;
456 size = 16;
457 for (;;) {
458 unsigned bit = size >> 1;
459 if ((bit & mask) == bit)
460 break;
461 size = bit;
462 }
463 /*
464 * For now we only print it out. Eventually we'll want to
465 * reserve it (at least if it's in the 0x1000+ range), but
466 * let's get enough confirmation reports first.
467 */
468 base &= -size;
469 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
470}
471
472static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
473{
474 u32 devres;
475 u32 mask, size, base;
476
477 pci_read_config_dword(dev, port, &devres);
478 if ((devres & enable) != enable)
479 return;
480 base = devres & 0xffff0000;
481 mask = (devres & 0x3f) << 16;
482 size = 128 << 16;
483 for (;;) {
484 unsigned bit = size >> 1;
485 if ((bit & mask) == bit)
486 break;
487 size = bit;
488 }
489 /*
490 * For now we only print it out. Eventually we'll want to
491 * reserve it, but let's get enough confirmation reports first.
492 */
493 base &= -size;
494 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
495}
496
497/*
498 * PIIX4 ACPI: Two IO regions pointed to by longwords at
499 * 0x40 (64 bytes of ACPI registers)
500 * 0x90 (16 bytes of SMB registers)
501 * and a few strange programmable PIIX4 device resources.
502 */
503static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
504{
505 u32 region, res_a;
506
507 pci_read_config_dword(dev, 0x40, ®ion);
508 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
509 pci_read_config_dword(dev, 0x90, ®ion);
510 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
511
512 /* Device resource A has enables for some of the other ones */
513 pci_read_config_dword(dev, 0x5c, &res_a);
514
515 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
516 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
517
518 /* Device resource D is just bitfields for static resources */
519
520 /* Device 12 enabled? */
521 if (res_a & (1 << 29)) {
522 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
523 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
524 }
525 /* Device 13 enabled? */
526 if (res_a & (1 << 30)) {
527 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
528 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
529 }
530 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
531 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
532}
533DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
534DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
535
536#define ICH_PMBASE 0x40
537#define ICH_ACPI_CNTL 0x44
538#define ICH4_ACPI_EN 0x10
539#define ICH6_ACPI_EN 0x80
540#define ICH4_GPIOBASE 0x58
541#define ICH4_GPIO_CNTL 0x5c
542#define ICH4_GPIO_EN 0x10
543#define ICH6_GPIOBASE 0x48
544#define ICH6_GPIO_CNTL 0x4c
545#define ICH6_GPIO_EN 0x10
546
547/*
548 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
549 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
550 * 0x58 (64 bytes of GPIO I/O space)
551 */
552static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
553{
554 u32 region;
555 u8 enable;
556
557 /*
558 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
559 * with low legacy (and fixed) ports. We don't know the decoding
560 * priority and can't tell whether the legacy device or the one created
561 * here is really at that address. This happens on boards with broken
562 * BIOSes.
563 */
564
565 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
566 if (enable & ICH4_ACPI_EN) {
567 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
568 region &= PCI_BASE_ADDRESS_IO_MASK;
569 if (region >= PCIBIOS_MIN_IO)
570 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
571 "ICH4 ACPI/GPIO/TCO");
572 }
573
574 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
575 if (enable & ICH4_GPIO_EN) {
576 pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion);
577 region &= PCI_BASE_ADDRESS_IO_MASK;
578 if (region >= PCIBIOS_MIN_IO)
579 quirk_io_region(dev, region, 64,
580 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
581 }
582}
583DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
584DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
585DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
587DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
588DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
590DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
593
594static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
595{
596 u32 region;
597 u8 enable;
598
599 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
600 if (enable & ICH6_ACPI_EN) {
601 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
602 region &= PCI_BASE_ADDRESS_IO_MASK;
603 if (region >= PCIBIOS_MIN_IO)
604 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
605 "ICH6 ACPI/GPIO/TCO");
606 }
607
608 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
609 if (enable & ICH6_GPIO_EN) {
610 pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion);
611 region &= PCI_BASE_ADDRESS_IO_MASK;
612 if (region >= PCIBIOS_MIN_IO)
613 quirk_io_region(dev, region, 64,
614 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
615 }
616}
617
618static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
619{
620 u32 val;
621 u32 size, base;
622
623 pci_read_config_dword(dev, reg, &val);
624
625 /* Enabled? */
626 if (!(val & 1))
627 return;
628 base = val & 0xfffc;
629 if (dynsize) {
630 /*
631 * This is not correct. It is 16, 32 or 64 bytes depending on
632 * register D31:F0:ADh bits 5:4.
633 *
634 * But this gets us at least _part_ of it.
635 */
636 size = 16;
637 } else {
638 size = 128;
639 }
640 base &= ~(size-1);
641
642 /* Just print it out for now. We should reserve it after more debugging */
643 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
644}
645
646static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
647{
648 /* Shared ACPI/GPIO decode with all ICH6+ */
649 ich6_lpc_acpi_gpio(dev);
650
651 /* ICH6-specific generic IO decode */
652 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
653 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
654}
655DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
657
658static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
659{
660 u32 val;
661 u32 mask, base;
662
663 pci_read_config_dword(dev, reg, &val);
664
665 /* Enabled? */
666 if (!(val & 1))
667 return;
668
669 /*
670 * IO base in bits 15:2, mask in bits 23:18, both
671 * are dword-based
672 */
673 base = val & 0xfffc;
674 mask = (val >> 16) & 0xfc;
675 mask |= 3;
676
677 /* Just print it out for now. We should reserve it after more debugging */
678 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
679}
680
681/* ICH7-10 has the same common LPC generic IO decode registers */
682static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
683{
684 /* We share the common ACPI/GPIO decode with ICH6 */
685 ich6_lpc_acpi_gpio(dev);
686
687 /* And have 4 ICH7+ generic decodes */
688 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
689 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
690 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
691 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
692}
693DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
694DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
706
707/*
708 * VIA ACPI: One IO region pointed to by longword at
709 * 0x48 or 0x20 (256 bytes of ACPI registers)
710 */
711static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
712{
713 u32 region;
714
715 if (dev->revision & 0x10) {
716 pci_read_config_dword(dev, 0x48, ®ion);
717 region &= PCI_BASE_ADDRESS_IO_MASK;
718 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
719 }
720}
721DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
722
723/*
724 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
725 * 0x48 (256 bytes of ACPI registers)
726 * 0x70 (128 bytes of hardware monitoring register)
727 * 0x90 (16 bytes of SMB registers)
728 */
729static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
730{
731 u16 hm;
732 u32 smb;
733
734 quirk_vt82c586_acpi(dev);
735
736 pci_read_config_word(dev, 0x70, &hm);
737 hm &= PCI_BASE_ADDRESS_IO_MASK;
738 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
739
740 pci_read_config_dword(dev, 0x90, &smb);
741 smb &= PCI_BASE_ADDRESS_IO_MASK;
742 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
743}
744DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
745
746/*
747 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
748 * 0x88 (128 bytes of power management registers)
749 * 0xd0 (16 bytes of SMB registers)
750 */
751static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
752{
753 u16 pm, smb;
754
755 pci_read_config_word(dev, 0x88, &pm);
756 pm &= PCI_BASE_ADDRESS_IO_MASK;
757 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
758
759 pci_read_config_word(dev, 0xd0, &smb);
760 smb &= PCI_BASE_ADDRESS_IO_MASK;
761 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
762}
763DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
764
765/*
766 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
767 * Disable fast back-to-back on the secondary bus segment
768 */
769static void __devinit quirk_xio2000a(struct pci_dev *dev)
770{
771 struct pci_dev *pdev;
772 u16 command;
773
774 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
775 "secondary bus fast back-to-back transfers disabled\n");
776 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
777 pci_read_config_word(pdev, PCI_COMMAND, &command);
778 if (command & PCI_COMMAND_FAST_BACK)
779 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
780 }
781}
782DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
783 quirk_xio2000a);
784
785#ifdef CONFIG_X86_IO_APIC
786
787#include <asm/io_apic.h>
788
789/*
790 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
791 * devices to the external APIC.
792 *
793 * TODO: When we have device-specific interrupt routers,
794 * this code will go away from quirks.
795 */
796static void quirk_via_ioapic(struct pci_dev *dev)
797{
798 u8 tmp;
799
800 if (nr_ioapics < 1)
801 tmp = 0; /* nothing routed to external APIC */
802 else
803 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
804
805 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
806 tmp == 0 ? "Disa" : "Ena");
807
808 /* Offset 0x58: External APIC IRQ output control */
809 pci_write_config_byte (dev, 0x58, tmp);
810}
811DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
812DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
813
814/*
815 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
816 * This leads to doubled level interrupt rates.
817 * Set this bit to get rid of cycle wastage.
818 * Otherwise uncritical.
819 */
820static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
821{
822 u8 misc_control2;
823#define BYPASS_APIC_DEASSERT 8
824
825 pci_read_config_byte(dev, 0x5B, &misc_control2);
826 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
827 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
828 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
829 }
830}
831DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
832DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
833
834/*
835 * The AMD io apic can hang the box when an apic irq is masked.
836 * We check all revs >= B0 (yet not in the pre production!) as the bug
837 * is currently marked NoFix
838 *
839 * We have multiple reports of hangs with this chipset that went away with
840 * noapic specified. For the moment we assume it's the erratum. We may be wrong
841 * of course. However the advice is demonstrably good even if so..
842 */
843static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
844{
845 if (dev->revision >= 0x02) {
846 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
847 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
848 }
849}
850DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
851
852static void __init quirk_ioapic_rmw(struct pci_dev *dev)
853{
854 if (dev->devfn == 0 && dev->bus->number == 0)
855 sis_apic_bug = 1;
856}
857DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
858#endif /* CONFIG_X86_IO_APIC */
859
860/*
861 * Some settings of MMRBC can lead to data corruption so block changes.
862 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
863 */
864static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
865{
866 if (dev->subordinate && dev->revision <= 0x12) {
867 dev_info(&dev->dev, "AMD8131 rev %x detected; "
868 "disabling PCI-X MMRBC\n", dev->revision);
869 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
870 }
871}
872DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
873
874/*
875 * FIXME: it is questionable that quirk_via_acpi
876 * is needed. It shows up as an ISA bridge, and does not
877 * support the PCI_INTERRUPT_LINE register at all. Therefore
878 * it seems like setting the pci_dev's 'irq' to the
879 * value of the ACPI SCI interrupt is only done for convenience.
880 * -jgarzik
881 */
882static void __devinit quirk_via_acpi(struct pci_dev *d)
883{
884 /*
885 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
886 */
887 u8 irq;
888 pci_read_config_byte(d, 0x42, &irq);
889 irq &= 0xf;
890 if (irq && (irq != 2))
891 d->irq = irq;
892}
893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
895
896
897/*
898 * VIA bridges which have VLink
899 */
900
901static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
902
903static void quirk_via_bridge(struct pci_dev *dev)
904{
905 /* See what bridge we have and find the device ranges */
906 switch (dev->device) {
907 case PCI_DEVICE_ID_VIA_82C686:
908 /* The VT82C686 is special, it attaches to PCI and can have
909 any device number. All its subdevices are functions of
910 that single device. */
911 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
912 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
913 break;
914 case PCI_DEVICE_ID_VIA_8237:
915 case PCI_DEVICE_ID_VIA_8237A:
916 via_vlink_dev_lo = 15;
917 break;
918 case PCI_DEVICE_ID_VIA_8235:
919 via_vlink_dev_lo = 16;
920 break;
921 case PCI_DEVICE_ID_VIA_8231:
922 case PCI_DEVICE_ID_VIA_8233_0:
923 case PCI_DEVICE_ID_VIA_8233A:
924 case PCI_DEVICE_ID_VIA_8233C_0:
925 via_vlink_dev_lo = 17;
926 break;
927 }
928}
929DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
930DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
931DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
932DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
936DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
937
938/**
939 * quirk_via_vlink - VIA VLink IRQ number update
940 * @dev: PCI device
941 *
942 * If the device we are dealing with is on a PIC IRQ we need to
943 * ensure that the IRQ line register which usually is not relevant
944 * for PCI cards, is actually written so that interrupts get sent
945 * to the right place.
946 * We only do this on systems where a VIA south bridge was detected,
947 * and only for VIA devices on the motherboard (see quirk_via_bridge
948 * above).
949 */
950
951static void quirk_via_vlink(struct pci_dev *dev)
952{
953 u8 irq, new_irq;
954
955 /* Check if we have VLink at all */
956 if (via_vlink_dev_lo == -1)
957 return;
958
959 new_irq = dev->irq;
960
961 /* Don't quirk interrupts outside the legacy IRQ range */
962 if (!new_irq || new_irq > 15)
963 return;
964
965 /* Internal device ? */
966 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
967 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
968 return;
969
970 /* This is an internal VLink device on a PIC interrupt. The BIOS
971 ought to have set this but may not have, so we redo it */
972
973 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
974 if (new_irq != irq) {
975 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
976 irq, new_irq);
977 udelay(15); /* unknown if delay really needed */
978 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
979 }
980}
981DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
982
983/*
984 * VIA VT82C598 has its device ID settable and many BIOSes
985 * set it to the ID of VT82C597 for backward compatibility.
986 * We need to switch it off to be able to recognize the real
987 * type of the chip.
988 */
989static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
990{
991 pci_write_config_byte(dev, 0xfc, 0);
992 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
993}
994DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
995
996/*
997 * CardBus controllers have a legacy base address that enables them
998 * to respond as i82365 pcmcia controllers. We don't want them to
999 * do this even if the Linux CardBus driver is not loaded, because
1000 * the Linux i82365 driver does not (and should not) handle CardBus.
1001 */
1002static void quirk_cardbus_legacy(struct pci_dev *dev)
1003{
1004 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
1005 return;
1006 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1007}
1008DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1009DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1010
1011/*
1012 * Following the PCI ordering rules is optional on the AMD762. I'm not
1013 * sure what the designers were smoking but let's not inhale...
1014 *
1015 * To be fair to AMD, it follows the spec by default, its BIOS people
1016 * who turn it off!
1017 */
1018static void quirk_amd_ordering(struct pci_dev *dev)
1019{
1020 u32 pcic;
1021 pci_read_config_dword(dev, 0x4C, &pcic);
1022 if ((pcic&6)!=6) {
1023 pcic |= 6;
1024 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1025 pci_write_config_dword(dev, 0x4C, pcic);
1026 pci_read_config_dword(dev, 0x84, &pcic);
1027 pcic |= (1<<23); /* Required in this mode */
1028 pci_write_config_dword(dev, 0x84, pcic);
1029 }
1030}
1031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1032DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1033
1034/*
1035 * DreamWorks provided workaround for Dunord I-3000 problem
1036 *
1037 * This card decodes and responds to addresses not apparently
1038 * assigned to it. We force a larger allocation to ensure that
1039 * nothing gets put too close to it.
1040 */
1041static void __devinit quirk_dunord ( struct pci_dev * dev )
1042{
1043 struct resource *r = &dev->resource [1];
1044 r->start = 0;
1045 r->end = 0xffffff;
1046}
1047DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1048
1049/*
1050 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1051 * is subtractive decoding (transparent), and does indicate this
1052 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1053 * instead of 0x01.
1054 */
1055static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
1056{
1057 dev->transparent = 1;
1058}
1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1060DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1061
1062/*
1063 * Common misconfiguration of the MediaGX/Geode PCI master that will
1064 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1065 * datasheets found at http://www.national.com/analog for info on what
1066 * these bits do. <christer@weinigel.se>
1067 */
1068static void quirk_mediagx_master(struct pci_dev *dev)
1069{
1070 u8 reg;
1071 pci_read_config_byte(dev, 0x41, ®);
1072 if (reg & 2) {
1073 reg &= ~2;
1074 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1075 pci_write_config_byte(dev, 0x41, reg);
1076 }
1077}
1078DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1079DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1080
1081/*
1082 * Ensure C0 rev restreaming is off. This is normally done by
1083 * the BIOS but in the odd case it is not the results are corruption
1084 * hence the presence of a Linux check
1085 */
1086static void quirk_disable_pxb(struct pci_dev *pdev)
1087{
1088 u16 config;
1089
1090 if (pdev->revision != 0x04) /* Only C0 requires this */
1091 return;
1092 pci_read_config_word(pdev, 0x40, &config);
1093 if (config & (1<<6)) {
1094 config &= ~(1<<6);
1095 pci_write_config_word(pdev, 0x40, config);
1096 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1097 }
1098}
1099DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1100DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1101
1102static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1103{
1104 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1105 u8 tmp;
1106
1107 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1108 if (tmp == 0x01) {
1109 pci_read_config_byte(pdev, 0x40, &tmp);
1110 pci_write_config_byte(pdev, 0x40, tmp|1);
1111 pci_write_config_byte(pdev, 0x9, 1);
1112 pci_write_config_byte(pdev, 0xa, 6);
1113 pci_write_config_byte(pdev, 0x40, tmp);
1114
1115 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1116 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1117 }
1118}
1119DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1120DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1121DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1122DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1124DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1125
1126/*
1127 * Serverworks CSB5 IDE does not fully support native mode
1128 */
1129static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1130{
1131 u8 prog;
1132 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1133 if (prog & 5) {
1134 prog &= ~5;
1135 pdev->class &= ~5;
1136 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1137 /* PCI layer will sort out resources */
1138 }
1139}
1140DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1141
1142/*
1143 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1144 */
1145static void __init quirk_ide_samemode(struct pci_dev *pdev)
1146{
1147 u8 prog;
1148
1149 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1150
1151 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1152 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1153 prog &= ~5;
1154 pdev->class &= ~5;
1155 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1156 }
1157}
1158DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1159
1160/*
1161 * Some ATA devices break if put into D3
1162 */
1163
1164static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1165{
1166 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1167 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1168 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1169}
1170DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1171DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1172/* ALi loses some register settings that we cannot then restore */
1173DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1174/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1175 occur when mode detecting */
1176DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
1177
1178/* This was originally an Alpha specific thing, but it really fits here.
1179 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1180 */
1181static void __init quirk_eisa_bridge(struct pci_dev *dev)
1182{
1183 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1184}
1185DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1186
1187
1188/*
1189 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1190 * is not activated. The myth is that Asus said that they do not want the
1191 * users to be irritated by just another PCI Device in the Win98 device
1192 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1193 * package 2.7.0 for details)
1194 *
1195 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1196 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1197 * becomes necessary to do this tweak in two steps -- the chosen trigger
1198 * is either the Host bridge (preferred) or on-board VGA controller.
1199 *
1200 * Note that we used to unhide the SMBus that way on Toshiba laptops
1201 * (Satellite A40 and Tecra M2) but then found that the thermal management
1202 * was done by SMM code, which could cause unsynchronized concurrent
1203 * accesses to the SMBus registers, with potentially bad effects. Thus you
1204 * should be very careful when adding new entries: if SMM is accessing the
1205 * Intel SMBus, this is a very good reason to leave it hidden.
1206 *
1207 * Likewise, many recent laptops use ACPI for thermal management. If the
1208 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1209 * natively, and keeping the SMBus hidden is the right thing to do. If you
1210 * are about to add an entry in the table below, please first disassemble
1211 * the DSDT and double-check that there is no code accessing the SMBus.
1212 */
1213static int asus_hides_smbus;
1214
1215static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1216{
1217 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1218 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1219 switch(dev->subsystem_device) {
1220 case 0x8025: /* P4B-LX */
1221 case 0x8070: /* P4B */
1222 case 0x8088: /* P4B533 */
1223 case 0x1626: /* L3C notebook */
1224 asus_hides_smbus = 1;
1225 }
1226 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1227 switch(dev->subsystem_device) {
1228 case 0x80b1: /* P4GE-V */
1229 case 0x80b2: /* P4PE */
1230 case 0x8093: /* P4B533-V */
1231 asus_hides_smbus = 1;
1232 }
1233 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1234 switch(dev->subsystem_device) {
1235 case 0x8030: /* P4T533 */
1236 asus_hides_smbus = 1;
1237 }
1238 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1239 switch (dev->subsystem_device) {
1240 case 0x8070: /* P4G8X Deluxe */
1241 asus_hides_smbus = 1;
1242 }
1243 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1244 switch (dev->subsystem_device) {
1245 case 0x80c9: /* PU-DLS */
1246 asus_hides_smbus = 1;
1247 }
1248 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1249 switch (dev->subsystem_device) {
1250 case 0x1751: /* M2N notebook */
1251 case 0x1821: /* M5N notebook */
1252 case 0x1897: /* A6L notebook */
1253 asus_hides_smbus = 1;
1254 }
1255 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1256 switch (dev->subsystem_device) {
1257 case 0x184b: /* W1N notebook */
1258 case 0x186a: /* M6Ne notebook */
1259 asus_hides_smbus = 1;
1260 }
1261 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1262 switch (dev->subsystem_device) {
1263 case 0x80f2: /* P4P800-X */
1264 asus_hides_smbus = 1;
1265 }
1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1267 switch (dev->subsystem_device) {
1268 case 0x1882: /* M6V notebook */
1269 case 0x1977: /* A6VA notebook */
1270 asus_hides_smbus = 1;
1271 }
1272 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1273 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1274 switch(dev->subsystem_device) {
1275 case 0x088C: /* HP Compaq nc8000 */
1276 case 0x0890: /* HP Compaq nc6000 */
1277 asus_hides_smbus = 1;
1278 }
1279 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1280 switch (dev->subsystem_device) {
1281 case 0x12bc: /* HP D330L */
1282 case 0x12bd: /* HP D530 */
1283 case 0x006a: /* HP Compaq nx9500 */
1284 asus_hides_smbus = 1;
1285 }
1286 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1287 switch (dev->subsystem_device) {
1288 case 0x12bf: /* HP xw4100 */
1289 asus_hides_smbus = 1;
1290 }
1291 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1292 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1293 switch(dev->subsystem_device) {
1294 case 0xC00C: /* Samsung P35 notebook */
1295 asus_hides_smbus = 1;
1296 }
1297 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1298 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1299 switch(dev->subsystem_device) {
1300 case 0x0058: /* Compaq Evo N620c */
1301 asus_hides_smbus = 1;
1302 }
1303 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1304 switch(dev->subsystem_device) {
1305 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1306 /* Motherboard doesn't have Host bridge
1307 * subvendor/subdevice IDs, therefore checking
1308 * its on-board VGA controller */
1309 asus_hides_smbus = 1;
1310 }
1311 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1312 switch(dev->subsystem_device) {
1313 case 0x00b8: /* Compaq Evo D510 CMT */
1314 case 0x00b9: /* Compaq Evo D510 SFF */
1315 case 0x00ba: /* Compaq Evo D510 USDT */
1316 /* Motherboard doesn't have Host bridge
1317 * subvendor/subdevice IDs and on-board VGA
1318 * controller is disabled if an AGP card is
1319 * inserted, therefore checking USB UHCI
1320 * Controller #1 */
1321 asus_hides_smbus = 1;
1322 }
1323 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1324 switch (dev->subsystem_device) {
1325 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1326 /* Motherboard doesn't have host bridge
1327 * subvendor/subdevice IDs, therefore checking
1328 * its on-board VGA controller */
1329 asus_hides_smbus = 1;
1330 }
1331 }
1332}
1333DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1341DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1343
1344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1347
1348static void asus_hides_smbus_lpc(struct pci_dev *dev)
1349{
1350 u16 val;
1351
1352 if (likely(!asus_hides_smbus))
1353 return;
1354
1355 pci_read_config_word(dev, 0xF2, &val);
1356 if (val & 0x8) {
1357 pci_write_config_word(dev, 0xF2, val & (~0x8));
1358 pci_read_config_word(dev, 0xF2, &val);
1359 if (val & 0x8)
1360 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1361 else
1362 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1363 }
1364}
1365DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1369DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1371DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1372DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1373DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1374DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1375DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1376DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1377DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1378DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1379
1380/* It appears we just have one such device. If not, we have a warning */
1381static void __iomem *asus_rcba_base;
1382static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1383{
1384 u32 rcba;
1385
1386 if (likely(!asus_hides_smbus))
1387 return;
1388 WARN_ON(asus_rcba_base);
1389
1390 pci_read_config_dword(dev, 0xF0, &rcba);
1391 /* use bits 31:14, 16 kB aligned */
1392 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1393 if (asus_rcba_base == NULL)
1394 return;
1395}
1396
1397static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1398{
1399 u32 val;
1400
1401 if (likely(!asus_hides_smbus || !asus_rcba_base))
1402 return;
1403 /* read the Function Disable register, dword mode only */
1404 val = readl(asus_rcba_base + 0x3418);
1405 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1406}
1407
1408static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1409{
1410 if (likely(!asus_hides_smbus || !asus_rcba_base))
1411 return;
1412 iounmap(asus_rcba_base);
1413 asus_rcba_base = NULL;
1414 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1415}
1416
1417static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1418{
1419 asus_hides_smbus_lpc_ich6_suspend(dev);
1420 asus_hides_smbus_lpc_ich6_resume_early(dev);
1421 asus_hides_smbus_lpc_ich6_resume(dev);
1422}
1423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1424DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1425DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1426DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1427
1428/*
1429 * SiS 96x south bridge: BIOS typically hides SMBus device...
1430 */
1431static void quirk_sis_96x_smbus(struct pci_dev *dev)
1432{
1433 u8 val = 0;
1434 pci_read_config_byte(dev, 0x77, &val);
1435 if (val & 0x10) {
1436 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1437 pci_write_config_byte(dev, 0x77, val & ~0x10);
1438 }
1439}
1440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1444DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1445DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1446DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1447DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1448
1449/*
1450 * ... This is further complicated by the fact that some SiS96x south
1451 * bridges pretend to be 85C503/5513 instead. In that case see if we
1452 * spotted a compatible north bridge to make sure.
1453 * (pci_find_device doesn't work yet)
1454 *
1455 * We can also enable the sis96x bit in the discovery register..
1456 */
1457#define SIS_DETECT_REGISTER 0x40
1458
1459static void quirk_sis_503(struct pci_dev *dev)
1460{
1461 u8 reg;
1462 u16 devid;
1463
1464 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1465 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1466 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1467 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1468 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1469 return;
1470 }
1471
1472 /*
1473 * Ok, it now shows up as a 96x.. run the 96x quirk by
1474 * hand in case it has already been processed.
1475 * (depends on link order, which is apparently not guaranteed)
1476 */
1477 dev->device = devid;
1478 quirk_sis_96x_smbus(dev);
1479}
1480DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1481DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1482
1483
1484/*
1485 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1486 * and MC97 modem controller are disabled when a second PCI soundcard is
1487 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1488 * -- bjd
1489 */
1490static void asus_hides_ac97_lpc(struct pci_dev *dev)
1491{
1492 u8 val;
1493 int asus_hides_ac97 = 0;
1494
1495 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1496 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1497 asus_hides_ac97 = 1;
1498 }
1499
1500 if (!asus_hides_ac97)
1501 return;
1502
1503 pci_read_config_byte(dev, 0x50, &val);
1504 if (val & 0xc0) {
1505 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1506 pci_read_config_byte(dev, 0x50, &val);
1507 if (val & 0xc0)
1508 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1509 else
1510 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1511 }
1512}
1513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1514DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1515
1516#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1517
1518/*
1519 * If we are using libata we can drive this chip properly but must
1520 * do this early on to make the additional device appear during
1521 * the PCI scanning.
1522 */
1523static void quirk_jmicron_ata(struct pci_dev *pdev)
1524{
1525 u32 conf1, conf5, class;
1526 u8 hdr;
1527
1528 /* Only poke fn 0 */
1529 if (PCI_FUNC(pdev->devfn))
1530 return;
1531
1532 pci_read_config_dword(pdev, 0x40, &conf1);
1533 pci_read_config_dword(pdev, 0x80, &conf5);
1534
1535 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1536 conf5 &= ~(1 << 24); /* Clear bit 24 */
1537
1538 switch (pdev->device) {
1539 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1540 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1541 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1542 /* The controller should be in single function ahci mode */
1543 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1544 break;
1545
1546 case PCI_DEVICE_ID_JMICRON_JMB365:
1547 case PCI_DEVICE_ID_JMICRON_JMB366:
1548 /* Redirect IDE second PATA port to the right spot */
1549 conf5 |= (1 << 24);
1550 /* Fall through */
1551 case PCI_DEVICE_ID_JMICRON_JMB361:
1552 case PCI_DEVICE_ID_JMICRON_JMB363:
1553 case PCI_DEVICE_ID_JMICRON_JMB369:
1554 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1555 /* Set the class codes correctly and then direct IDE 0 */
1556 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1557 break;
1558
1559 case PCI_DEVICE_ID_JMICRON_JMB368:
1560 /* The controller should be in single function IDE mode */
1561 conf1 |= 0x00C00000; /* Set 22, 23 */
1562 break;
1563 }
1564
1565 pci_write_config_dword(pdev, 0x40, conf1);
1566 pci_write_config_dword(pdev, 0x80, conf5);
1567
1568 /* Update pdev accordingly */
1569 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1570 pdev->hdr_type = hdr & 0x7f;
1571 pdev->multifunction = !!(hdr & 0x80);
1572
1573 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1574 pdev->class = class >> 8;
1575}
1576DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1577DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1578DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1579DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1580DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1581DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1582DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1583DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1585DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1586DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1587DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1588DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1589DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1590DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1591DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1592DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1593DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1594
1595#endif
1596
1597#ifdef CONFIG_X86_IO_APIC
1598static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1599{
1600 int i;
1601
1602 if ((pdev->class >> 8) != 0xff00)
1603 return;
1604
1605 /* the first BAR is the location of the IO APIC...we must
1606 * not touch this (and it's already covered by the fixmap), so
1607 * forcibly insert it into the resource tree */
1608 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1609 insert_resource(&iomem_resource, &pdev->resource[0]);
1610
1611 /* The next five BARs all seem to be rubbish, so just clean
1612 * them out */
1613 for (i=1; i < 6; i++) {
1614 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1615 }
1616
1617}
1618DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1619#endif
1620
1621static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1622{
1623 pci_msi_off(pdev);
1624 pdev->no_msi = 1;
1625}
1626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1629
1630
1631/*
1632 * It's possible for the MSI to get corrupted if shpc and acpi
1633 * are used together on certain PXH-based systems.
1634 */
1635static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1636{
1637 pci_msi_off(dev);
1638 dev->no_msi = 1;
1639 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1640}
1641DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1642DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1643DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1644DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1645DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1646
1647/*
1648 * Some Intel PCI Express chipsets have trouble with downstream
1649 * device power management.
1650 */
1651static void quirk_intel_pcie_pm(struct pci_dev * dev)
1652{
1653 pci_pm_d3_delay = 120;
1654 dev->no_d1d2 = 1;
1655}
1656
1657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1677DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1678
1679#ifdef CONFIG_X86_IO_APIC
1680/*
1681 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1682 * remap the original interrupt in the linux kernel to the boot interrupt, so
1683 * that a PCI device's interrupt handler is installed on the boot interrupt
1684 * line instead.
1685 */
1686static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1687{
1688 if (noioapicquirk || noioapicreroute)
1689 return;
1690
1691 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1692 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1693 dev->vendor, dev->device);
1694}
1695DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1697DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1699DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1700DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1701DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1703DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1704DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1705DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1706DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1707DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1708DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1709DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1710DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1711
1712/*
1713 * On some chipsets we can disable the generation of legacy INTx boot
1714 * interrupts.
1715 */
1716
1717/*
1718 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1719 * 300641-004US, section 5.7.3.
1720 */
1721#define INTEL_6300_IOAPIC_ABAR 0x40
1722#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1723
1724static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1725{
1726 u16 pci_config_word;
1727
1728 if (noioapicquirk)
1729 return;
1730
1731 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1732 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1733 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1734
1735 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1736 dev->vendor, dev->device);
1737}
1738DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1739DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1740
1741/*
1742 * disable boot interrupts on HT-1000
1743 */
1744#define BC_HT1000_FEATURE_REG 0x64
1745#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1746#define BC_HT1000_MAP_IDX 0xC00
1747#define BC_HT1000_MAP_DATA 0xC01
1748
1749static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1750{
1751 u32 pci_config_dword;
1752 u8 irq;
1753
1754 if (noioapicquirk)
1755 return;
1756
1757 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1758 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1759 BC_HT1000_PIC_REGS_ENABLE);
1760
1761 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1762 outb(irq, BC_HT1000_MAP_IDX);
1763 outb(0x00, BC_HT1000_MAP_DATA);
1764 }
1765
1766 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1767
1768 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1769 dev->vendor, dev->device);
1770}
1771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1772DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1773
1774/*
1775 * disable boot interrupts on AMD and ATI chipsets
1776 */
1777/*
1778 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1779 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1780 * (due to an erratum).
1781 */
1782#define AMD_813X_MISC 0x40
1783#define AMD_813X_NOIOAMODE (1<<0)
1784#define AMD_813X_REV_B1 0x12
1785#define AMD_813X_REV_B2 0x13
1786
1787static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1788{
1789 u32 pci_config_dword;
1790
1791 if (noioapicquirk)
1792 return;
1793 if ((dev->revision == AMD_813X_REV_B1) ||
1794 (dev->revision == AMD_813X_REV_B2))
1795 return;
1796
1797 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1798 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1799 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1800
1801 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1802 dev->vendor, dev->device);
1803}
1804DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1805DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1806DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1807DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1808
1809#define AMD_8111_PCI_IRQ_ROUTING 0x56
1810
1811static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1812{
1813 u16 pci_config_word;
1814
1815 if (noioapicquirk)
1816 return;
1817
1818 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1819 if (!pci_config_word) {
1820 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1821 "already disabled\n", dev->vendor, dev->device);
1822 return;
1823 }
1824 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1825 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1826 dev->vendor, dev->device);
1827}
1828DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1829DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1830#endif /* CONFIG_X86_IO_APIC */
1831
1832/*
1833 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1834 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1835 * Re-allocate the region if needed...
1836 */
1837static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1838{
1839 struct resource *r = &dev->resource[0];
1840
1841 if (r->start & 0x8) {
1842 r->start = 0;
1843 r->end = 0xf;
1844 }
1845}
1846DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1847 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1848 quirk_tc86c001_ide);
1849
1850static void __devinit quirk_netmos(struct pci_dev *dev)
1851{
1852 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1853 unsigned int num_serial = dev->subsystem_device & 0xf;
1854
1855 /*
1856 * These Netmos parts are multiport serial devices with optional
1857 * parallel ports. Even when parallel ports are present, they
1858 * are identified as class SERIAL, which means the serial driver
1859 * will claim them. To prevent this, mark them as class OTHER.
1860 * These combo devices should be claimed by parport_serial.
1861 *
1862 * The subdevice ID is of the form 0x00PS, where <P> is the number
1863 * of parallel ports and <S> is the number of serial ports.
1864 */
1865 switch (dev->device) {
1866 case PCI_DEVICE_ID_NETMOS_9835:
1867 /* Well, this rule doesn't hold for the following 9835 device */
1868 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1869 dev->subsystem_device == 0x0299)
1870 return;
1871 case PCI_DEVICE_ID_NETMOS_9735:
1872 case PCI_DEVICE_ID_NETMOS_9745:
1873 case PCI_DEVICE_ID_NETMOS_9845:
1874 case PCI_DEVICE_ID_NETMOS_9855:
1875 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1876 num_parallel) {
1877 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1878 "%u serial); changing class SERIAL to OTHER "
1879 "(use parport_serial)\n",
1880 dev->device, num_parallel, num_serial);
1881 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1882 (dev->class & 0xff);
1883 }
1884 }
1885}
1886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1887
1888static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1889{
1890 u16 command, pmcsr;
1891 u8 __iomem *csr;
1892 u8 cmd_hi;
1893 int pm;
1894
1895 switch (dev->device) {
1896 /* PCI IDs taken from drivers/net/e100.c */
1897 case 0x1029:
1898 case 0x1030 ... 0x1034:
1899 case 0x1038 ... 0x103E:
1900 case 0x1050 ... 0x1057:
1901 case 0x1059:
1902 case 0x1064 ... 0x106B:
1903 case 0x1091 ... 0x1095:
1904 case 0x1209:
1905 case 0x1229:
1906 case 0x2449:
1907 case 0x2459:
1908 case 0x245D:
1909 case 0x27DC:
1910 break;
1911 default:
1912 return;
1913 }
1914
1915 /*
1916 * Some firmware hands off the e100 with interrupts enabled,
1917 * which can cause a flood of interrupts if packets are
1918 * received before the driver attaches to the device. So
1919 * disable all e100 interrupts here. The driver will
1920 * re-enable them when it's ready.
1921 */
1922 pci_read_config_word(dev, PCI_COMMAND, &command);
1923
1924 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1925 return;
1926
1927 /*
1928 * Check that the device is in the D0 power state. If it's not,
1929 * there is no point to look any further.
1930 */
1931 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1932 if (pm) {
1933 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1934 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1935 return;
1936 }
1937
1938 /* Convert from PCI bus to resource space. */
1939 csr = ioremap(pci_resource_start(dev, 0), 8);
1940 if (!csr) {
1941 dev_warn(&dev->dev, "Can't map e100 registers\n");
1942 return;
1943 }
1944
1945 cmd_hi = readb(csr + 3);
1946 if (cmd_hi == 0) {
1947 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1948 "disabling\n");
1949 writeb(1, csr + 3);
1950 }
1951
1952 iounmap(csr);
1953}
1954DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1955
1956/*
1957 * The 82575 and 82598 may experience data corruption issues when transitioning
1958 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1959 */
1960static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1961{
1962 dev_info(&dev->dev, "Disabling L0s\n");
1963 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1964}
1965DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1966DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1967DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1968DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1969DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1970DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1971DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1972DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1973DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1974DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1975DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1976DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1977DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1979
1980static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1981{
1982 /* rev 1 ncr53c810 chips don't set the class at all which means
1983 * they don't get their resources remapped. Fix that here.
1984 */
1985
1986 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1987 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1988 dev->class = PCI_CLASS_STORAGE_SCSI;
1989 }
1990}
1991DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1992
1993/* Enable 1k I/O space granularity on the Intel P64H2 */
1994static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1995{
1996 u16 en1k;
1997 u8 io_base_lo, io_limit_lo;
1998 unsigned long base, limit;
1999 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2000
2001 pci_read_config_word(dev, 0x40, &en1k);
2002
2003 if (en1k & 0x200) {
2004 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2005
2006 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
2007 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
2008 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2009 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2010
2011 if (base <= limit) {
2012 res->start = base;
2013 res->end = limit + 0x3ff;
2014 }
2015 }
2016}
2017DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2018
2019/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
2020 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
2021 * in drivers/pci/setup-bus.c
2022 */
2023static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
2024{
2025 u16 en1k, iobl_adr, iobl_adr_1k;
2026 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2027
2028 pci_read_config_word(dev, 0x40, &en1k);
2029
2030 if (en1k & 0x200) {
2031 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
2032
2033 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
2034
2035 if (iobl_adr != iobl_adr_1k) {
2036 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
2037 iobl_adr,iobl_adr_1k);
2038 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
2039 }
2040 }
2041}
2042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
2043
2044/* Under some circumstances, AER is not linked with extended capabilities.
2045 * Force it to be linked by setting the corresponding control bit in the
2046 * config space.
2047 */
2048static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2049{
2050 uint8_t b;
2051 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2052 if (!(b & 0x20)) {
2053 pci_write_config_byte(dev, 0xf41, b | 0x20);
2054 dev_info(&dev->dev,
2055 "Linking AER extended capability\n");
2056 }
2057 }
2058}
2059DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2060 quirk_nvidia_ck804_pcie_aer_ext_cap);
2061DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2062 quirk_nvidia_ck804_pcie_aer_ext_cap);
2063
2064static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2065{
2066 /*
2067 * Disable PCI Bus Parking and PCI Master read caching on CX700
2068 * which causes unspecified timing errors with a VT6212L on the PCI
2069 * bus leading to USB2.0 packet loss.
2070 *
2071 * This quirk is only enabled if a second (on the external PCI bus)
2072 * VT6212L is found -- the CX700 core itself also contains a USB
2073 * host controller with the same PCI ID as the VT6212L.
2074 */
2075
2076 /* Count VT6212L instances */
2077 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2078 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2079 uint8_t b;
2080
2081 /* p should contain the first (internal) VT6212L -- see if we have
2082 an external one by searching again */
2083 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2084 if (!p)
2085 return;
2086 pci_dev_put(p);
2087
2088 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2089 if (b & 0x40) {
2090 /* Turn off PCI Bus Parking */
2091 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2092
2093 dev_info(&dev->dev,
2094 "Disabling VIA CX700 PCI parking\n");
2095 }
2096 }
2097
2098 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2099 if (b != 0) {
2100 /* Turn off PCI Master read caching */
2101 pci_write_config_byte(dev, 0x72, 0x0);
2102
2103 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2104 pci_write_config_byte(dev, 0x75, 0x1);
2105
2106 /* Disable "Read FIFO Timer" */
2107 pci_write_config_byte(dev, 0x77, 0x0);
2108
2109 dev_info(&dev->dev,
2110 "Disabling VIA CX700 PCI caching\n");
2111 }
2112 }
2113}
2114DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2115
2116/*
2117 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2118 * VPD end tag will hang the device. This problem was initially
2119 * observed when a vpd entry was created in sysfs
2120 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2121 * will dump 32k of data. Reading a full 32k will cause an access
2122 * beyond the VPD end tag causing the device to hang. Once the device
2123 * is hung, the bnx2 driver will not be able to reset the device.
2124 * We believe that it is legal to read beyond the end tag and
2125 * therefore the solution is to limit the read/write length.
2126 */
2127static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2128{
2129 /*
2130 * Only disable the VPD capability for 5706, 5706S, 5708,
2131 * 5708S and 5709 rev. A
2132 */
2133 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2134 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2135 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2136 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2137 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2138 (dev->revision & 0xf0) == 0x0)) {
2139 if (dev->vpd)
2140 dev->vpd->len = 0x80;
2141 }
2142}
2143
2144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2145 PCI_DEVICE_ID_NX2_5706,
2146 quirk_brcm_570x_limit_vpd);
2147DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2148 PCI_DEVICE_ID_NX2_5706S,
2149 quirk_brcm_570x_limit_vpd);
2150DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2151 PCI_DEVICE_ID_NX2_5708,
2152 quirk_brcm_570x_limit_vpd);
2153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2154 PCI_DEVICE_ID_NX2_5708S,
2155 quirk_brcm_570x_limit_vpd);
2156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2157 PCI_DEVICE_ID_NX2_5709,
2158 quirk_brcm_570x_limit_vpd);
2159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2160 PCI_DEVICE_ID_NX2_5709S,
2161 quirk_brcm_570x_limit_vpd);
2162
2163/* Originally in EDAC sources for i82875P:
2164 * Intel tells BIOS developers to hide device 6 which
2165 * configures the overflow device access containing
2166 * the DRBs - this is where we expose device 6.
2167 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2168 */
2169static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2170{
2171 u8 reg;
2172
2173 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2174 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2175 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2176 }
2177}
2178
2179DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2180 quirk_unhide_mch_dev6);
2181DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2182 quirk_unhide_mch_dev6);
2183
2184#ifdef CONFIG_TILE
2185/*
2186 * The Tilera TILEmpower platform needs to set the link speed
2187 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2188 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2189 * capability register of the PEX8624 PCIe switch. The switch
2190 * supports link speed auto negotiation, but falsely sets
2191 * the link speed to 5GT/s.
2192 */
2193static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2194{
2195 if (tile_plx_gen1) {
2196 pci_write_config_dword(dev, 0x98, 0x1);
2197 mdelay(50);
2198 }
2199}
2200DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2201#endif /* CONFIG_TILE */
2202
2203#ifdef CONFIG_PCI_MSI
2204/* Some chipsets do not support MSI. We cannot easily rely on setting
2205 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2206 * some other busses controlled by the chipset even if Linux is not
2207 * aware of it. Instead of setting the flag on all busses in the
2208 * machine, simply disable MSI globally.
2209 */
2210static void __init quirk_disable_all_msi(struct pci_dev *dev)
2211{
2212 pci_no_msi();
2213 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2214}
2215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2222
2223/* Disable MSI on chipsets that are known to not support it */
2224static void __devinit quirk_disable_msi(struct pci_dev *dev)
2225{
2226 if (dev->subordinate) {
2227 dev_warn(&dev->dev, "MSI quirk detected; "
2228 "subordinate MSI disabled\n");
2229 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2230 }
2231}
2232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2233DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2235
2236/*
2237 * The APC bridge device in AMD 780 family northbridges has some random
2238 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2239 * we use the possible vendor/device IDs of the host bridge for the
2240 * declared quirk, and search for the APC bridge by slot number.
2241 */
2242static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2243{
2244 struct pci_dev *apc_bridge;
2245
2246 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2247 if (apc_bridge) {
2248 if (apc_bridge->device == 0x9602)
2249 quirk_disable_msi(apc_bridge);
2250 pci_dev_put(apc_bridge);
2251 }
2252}
2253DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2255
2256/* Go through the list of Hypertransport capabilities and
2257 * return 1 if a HT MSI capability is found and enabled */
2258static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2259{
2260 int pos, ttl = 48;
2261
2262 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2263 while (pos && ttl--) {
2264 u8 flags;
2265
2266 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2267 &flags) == 0)
2268 {
2269 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2270 flags & HT_MSI_FLAGS_ENABLE ?
2271 "enabled" : "disabled");
2272 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2273 }
2274
2275 pos = pci_find_next_ht_capability(dev, pos,
2276 HT_CAPTYPE_MSI_MAPPING);
2277 }
2278 return 0;
2279}
2280
2281/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2282static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2283{
2284 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2285 dev_warn(&dev->dev, "MSI quirk detected; "
2286 "subordinate MSI disabled\n");
2287 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2288 }
2289}
2290DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2291 quirk_msi_ht_cap);
2292
2293/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2294 * MSI are supported if the MSI capability set in any of these mappings.
2295 */
2296static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2297{
2298 struct pci_dev *pdev;
2299
2300 if (!dev->subordinate)
2301 return;
2302
2303 /* check HT MSI cap on this chipset and the root one.
2304 * a single one having MSI is enough to be sure that MSI are supported.
2305 */
2306 pdev = pci_get_slot(dev->bus, 0);
2307 if (!pdev)
2308 return;
2309 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2310 dev_warn(&dev->dev, "MSI quirk detected; "
2311 "subordinate MSI disabled\n");
2312 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2313 }
2314 pci_dev_put(pdev);
2315}
2316DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2317 quirk_nvidia_ck804_msi_ht_cap);
2318
2319/* Force enable MSI mapping capability on HT bridges */
2320static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2321{
2322 int pos, ttl = 48;
2323
2324 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2325 while (pos && ttl--) {
2326 u8 flags;
2327
2328 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2329 &flags) == 0) {
2330 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2331
2332 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2333 flags | HT_MSI_FLAGS_ENABLE);
2334 }
2335 pos = pci_find_next_ht_capability(dev, pos,
2336 HT_CAPTYPE_MSI_MAPPING);
2337 }
2338}
2339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2340 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2341 ht_enable_msi_mapping);
2342
2343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2344 ht_enable_msi_mapping);
2345
2346/* The P5N32-SLI motherboards from Asus have a problem with msi
2347 * for the MCP55 NIC. It is not yet determined whether the msi problem
2348 * also affects other devices. As for now, turn off msi for this device.
2349 */
2350static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2351{
2352 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2353
2354 if (board_name &&
2355 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2356 strstr(board_name, "P5N32-E SLI"))) {
2357 dev_info(&dev->dev,
2358 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2359 dev->no_msi = 1;
2360 }
2361}
2362DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2363 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2364 nvenet_msi_disable);
2365
2366/*
2367 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2368 * config register. This register controls the routing of legacy interrupts
2369 * from devices that route through the MCP55. If this register is misprogramed
2370 * interrupts are only sent to the bsp, unlike conventional systems where the
2371 * irq is broadxast to all online cpus. Not having this register set
2372 * properly prevents kdump from booting up properly, so lets make sure that
2373 * we have it set correctly.
2374 * Note this is an undocumented register.
2375 */
2376static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2377{
2378 u32 cfg;
2379
2380 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2381 return;
2382
2383 pci_read_config_dword(dev, 0x74, &cfg);
2384
2385 if (cfg & ((1 << 2) | (1 << 15))) {
2386 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2387 cfg &= ~((1 << 2) | (1 << 15));
2388 pci_write_config_dword(dev, 0x74, cfg);
2389 }
2390}
2391
2392DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2393 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2394 nvbridge_check_legacy_irq_routing);
2395
2396DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2397 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2398 nvbridge_check_legacy_irq_routing);
2399
2400static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2401{
2402 int pos, ttl = 48;
2403 int found = 0;
2404
2405 /* check if there is HT MSI cap or enabled on this device */
2406 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2407 while (pos && ttl--) {
2408 u8 flags;
2409
2410 if (found < 1)
2411 found = 1;
2412 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2413 &flags) == 0) {
2414 if (flags & HT_MSI_FLAGS_ENABLE) {
2415 if (found < 2) {
2416 found = 2;
2417 break;
2418 }
2419 }
2420 }
2421 pos = pci_find_next_ht_capability(dev, pos,
2422 HT_CAPTYPE_MSI_MAPPING);
2423 }
2424
2425 return found;
2426}
2427
2428static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2429{
2430 struct pci_dev *dev;
2431 int pos;
2432 int i, dev_no;
2433 int found = 0;
2434
2435 dev_no = host_bridge->devfn >> 3;
2436 for (i = dev_no + 1; i < 0x20; i++) {
2437 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2438 if (!dev)
2439 continue;
2440
2441 /* found next host bridge ?*/
2442 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2443 if (pos != 0) {
2444 pci_dev_put(dev);
2445 break;
2446 }
2447
2448 if (ht_check_msi_mapping(dev)) {
2449 found = 1;
2450 pci_dev_put(dev);
2451 break;
2452 }
2453 pci_dev_put(dev);
2454 }
2455
2456 return found;
2457}
2458
2459#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2460#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2461
2462static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2463{
2464 int pos, ctrl_off;
2465 int end = 0;
2466 u16 flags, ctrl;
2467
2468 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2469
2470 if (!pos)
2471 goto out;
2472
2473 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2474
2475 ctrl_off = ((flags >> 10) & 1) ?
2476 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2477 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2478
2479 if (ctrl & (1 << 6))
2480 end = 1;
2481
2482out:
2483 return end;
2484}
2485
2486static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2487{
2488 struct pci_dev *host_bridge;
2489 int pos;
2490 int i, dev_no;
2491 int found = 0;
2492
2493 dev_no = dev->devfn >> 3;
2494 for (i = dev_no; i >= 0; i--) {
2495 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2496 if (!host_bridge)
2497 continue;
2498
2499 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2500 if (pos != 0) {
2501 found = 1;
2502 break;
2503 }
2504 pci_dev_put(host_bridge);
2505 }
2506
2507 if (!found)
2508 return;
2509
2510 /* don't enable end_device/host_bridge with leaf directly here */
2511 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2512 host_bridge_with_leaf(host_bridge))
2513 goto out;
2514
2515 /* root did that ! */
2516 if (msi_ht_cap_enabled(host_bridge))
2517 goto out;
2518
2519 ht_enable_msi_mapping(dev);
2520
2521out:
2522 pci_dev_put(host_bridge);
2523}
2524
2525static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2526{
2527 int pos, ttl = 48;
2528
2529 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2530 while (pos && ttl--) {
2531 u8 flags;
2532
2533 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2534 &flags) == 0) {
2535 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2536
2537 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2538 flags & ~HT_MSI_FLAGS_ENABLE);
2539 }
2540 pos = pci_find_next_ht_capability(dev, pos,
2541 HT_CAPTYPE_MSI_MAPPING);
2542 }
2543}
2544
2545static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2546{
2547 struct pci_dev *host_bridge;
2548 int pos;
2549 int found;
2550
2551 if (!pci_msi_enabled())
2552 return;
2553
2554 /* check if there is HT MSI cap or enabled on this device */
2555 found = ht_check_msi_mapping(dev);
2556
2557 /* no HT MSI CAP */
2558 if (found == 0)
2559 return;
2560
2561 /*
2562 * HT MSI mapping should be disabled on devices that are below
2563 * a non-Hypertransport host bridge. Locate the host bridge...
2564 */
2565 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2566 if (host_bridge == NULL) {
2567 dev_warn(&dev->dev,
2568 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2569 return;
2570 }
2571
2572 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2573 if (pos != 0) {
2574 /* Host bridge is to HT */
2575 if (found == 1) {
2576 /* it is not enabled, try to enable it */
2577 if (all)
2578 ht_enable_msi_mapping(dev);
2579 else
2580 nv_ht_enable_msi_mapping(dev);
2581 }
2582 return;
2583 }
2584
2585 /* HT MSI is not enabled */
2586 if (found == 1)
2587 return;
2588
2589 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2590 ht_disable_msi_mapping(dev);
2591}
2592
2593static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2594{
2595 return __nv_msi_ht_cap_quirk(dev, 1);
2596}
2597
2598static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2599{
2600 return __nv_msi_ht_cap_quirk(dev, 0);
2601}
2602
2603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2604DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2605
2606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2607DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2608
2609static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2610{
2611 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2612}
2613static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2614{
2615 struct pci_dev *p;
2616
2617 /* SB700 MSI issue will be fixed at HW level from revision A21,
2618 * we need check PCI REVISION ID of SMBus controller to get SB700
2619 * revision.
2620 */
2621 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2622 NULL);
2623 if (!p)
2624 return;
2625
2626 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2627 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2628 pci_dev_put(p);
2629}
2630DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2631 PCI_DEVICE_ID_TIGON3_5780,
2632 quirk_msi_intx_disable_bug);
2633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2634 PCI_DEVICE_ID_TIGON3_5780S,
2635 quirk_msi_intx_disable_bug);
2636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2637 PCI_DEVICE_ID_TIGON3_5714,
2638 quirk_msi_intx_disable_bug);
2639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2640 PCI_DEVICE_ID_TIGON3_5714S,
2641 quirk_msi_intx_disable_bug);
2642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2643 PCI_DEVICE_ID_TIGON3_5715,
2644 quirk_msi_intx_disable_bug);
2645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2646 PCI_DEVICE_ID_TIGON3_5715S,
2647 quirk_msi_intx_disable_bug);
2648
2649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2650 quirk_msi_intx_disable_ati_bug);
2651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2652 quirk_msi_intx_disable_ati_bug);
2653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2654 quirk_msi_intx_disable_ati_bug);
2655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2656 quirk_msi_intx_disable_ati_bug);
2657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2658 quirk_msi_intx_disable_ati_bug);
2659
2660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2661 quirk_msi_intx_disable_bug);
2662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2663 quirk_msi_intx_disable_bug);
2664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2665 quirk_msi_intx_disable_bug);
2666
2667#endif /* CONFIG_PCI_MSI */
2668
2669/* Allow manual resource allocation for PCI hotplug bridges
2670 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2671 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2672 * kernel fails to allocate resources when hotplug device is
2673 * inserted and PCI bus is rescanned.
2674 */
2675static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2676{
2677 dev->is_hotplug_bridge = 1;
2678}
2679
2680DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2681
2682/*
2683 * This is a quirk for the Ricoh MMC controller found as a part of
2684 * some mulifunction chips.
2685
2686 * This is very similar and based on the ricoh_mmc driver written by
2687 * Philip Langdale. Thank you for these magic sequences.
2688 *
2689 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2690 * and one or both of cardbus or firewire.
2691 *
2692 * It happens that they implement SD and MMC
2693 * support as separate controllers (and PCI functions). The linux SDHCI
2694 * driver supports MMC cards but the chip detects MMC cards in hardware
2695 * and directs them to the MMC controller - so the SDHCI driver never sees
2696 * them.
2697 *
2698 * To get around this, we must disable the useless MMC controller.
2699 * At that point, the SDHCI controller will start seeing them
2700 * It seems to be the case that the relevant PCI registers to deactivate the
2701 * MMC controller live on PCI function 0, which might be the cardbus controller
2702 * or the firewire controller, depending on the particular chip in question
2703 *
2704 * This has to be done early, because as soon as we disable the MMC controller
2705 * other pci functions shift up one level, e.g. function #2 becomes function
2706 * #1, and this will confuse the pci core.
2707 */
2708
2709#ifdef CONFIG_MMC_RICOH_MMC
2710static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2711{
2712 /* disable via cardbus interface */
2713 u8 write_enable;
2714 u8 write_target;
2715 u8 disable;
2716
2717 /* disable must be done via function #0 */
2718 if (PCI_FUNC(dev->devfn))
2719 return;
2720
2721 pci_read_config_byte(dev, 0xB7, &disable);
2722 if (disable & 0x02)
2723 return;
2724
2725 pci_read_config_byte(dev, 0x8E, &write_enable);
2726 pci_write_config_byte(dev, 0x8E, 0xAA);
2727 pci_read_config_byte(dev, 0x8D, &write_target);
2728 pci_write_config_byte(dev, 0x8D, 0xB7);
2729 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2730 pci_write_config_byte(dev, 0x8E, write_enable);
2731 pci_write_config_byte(dev, 0x8D, write_target);
2732
2733 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2734 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2735}
2736DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2737DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2738
2739static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2740{
2741 /* disable via firewire interface */
2742 u8 write_enable;
2743 u8 disable;
2744
2745 /* disable must be done via function #0 */
2746 if (PCI_FUNC(dev->devfn))
2747 return;
2748
2749 pci_read_config_byte(dev, 0xCB, &disable);
2750
2751 if (disable & 0x02)
2752 return;
2753
2754 pci_read_config_byte(dev, 0xCA, &write_enable);
2755 pci_write_config_byte(dev, 0xCA, 0x57);
2756 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2757 pci_write_config_byte(dev, 0xCA, write_enable);
2758
2759 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2760 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2761
2762 /*
2763 * RICOH 0xe823 SD/MMC card reader fails to recognize
2764 * certain types of SD/MMC cards. Lowering the SD base
2765 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2766 *
2767 * 0x150 - SD2.0 mode enable for changing base clock
2768 * frequency to 50Mhz
2769 * 0xe1 - Base clock frequency
2770 * 0x32 - 50Mhz new clock frequency
2771 * 0xf9 - Key register for 0x150
2772 * 0xfc - key register for 0xe1
2773 */
2774 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2775 pci_write_config_byte(dev, 0xf9, 0xfc);
2776 pci_write_config_byte(dev, 0x150, 0x10);
2777 pci_write_config_byte(dev, 0xf9, 0x00);
2778 pci_write_config_byte(dev, 0xfc, 0x01);
2779 pci_write_config_byte(dev, 0xe1, 0x32);
2780 pci_write_config_byte(dev, 0xfc, 0x00);
2781
2782 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2783 }
2784}
2785DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2786DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2787DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2788DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2789#endif /*CONFIG_MMC_RICOH_MMC*/
2790
2791#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
2792#define VTUNCERRMSK_REG 0x1ac
2793#define VTD_MSK_SPEC_ERRORS (1 << 31)
2794/*
2795 * This is a quirk for masking vt-d spec defined errors to platform error
2796 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2797 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2798 * on the RAS config settings of the platform) when a vt-d fault happens.
2799 * The resulting SMI caused the system to hang.
2800 *
2801 * VT-d spec related errors are already handled by the VT-d OS code, so no
2802 * need to report the same error through other channels.
2803 */
2804static void vtd_mask_spec_errors(struct pci_dev *dev)
2805{
2806 u32 word;
2807
2808 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2809 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2810}
2811DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2812DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2813#endif
2814
2815static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2816{
2817 /* TI 816x devices do not have class code set when in PCIe boot mode */
2818 if (dev->class == PCI_CLASS_NOT_DEFINED) {
2819 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2820 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2821 }
2822}
2823DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class);
2824
2825static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2826 struct pci_fixup *end)
2827{
2828 while (f < end) {
2829 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
2830 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
2831 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2832 f->hook(dev);
2833 }
2834 f++;
2835 }
2836}
2837
2838extern struct pci_fixup __start_pci_fixups_early[];
2839extern struct pci_fixup __end_pci_fixups_early[];
2840extern struct pci_fixup __start_pci_fixups_header[];
2841extern struct pci_fixup __end_pci_fixups_header[];
2842extern struct pci_fixup __start_pci_fixups_final[];
2843extern struct pci_fixup __end_pci_fixups_final[];
2844extern struct pci_fixup __start_pci_fixups_enable[];
2845extern struct pci_fixup __end_pci_fixups_enable[];
2846extern struct pci_fixup __start_pci_fixups_resume[];
2847extern struct pci_fixup __end_pci_fixups_resume[];
2848extern struct pci_fixup __start_pci_fixups_resume_early[];
2849extern struct pci_fixup __end_pci_fixups_resume_early[];
2850extern struct pci_fixup __start_pci_fixups_suspend[];
2851extern struct pci_fixup __end_pci_fixups_suspend[];
2852
2853
2854void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2855{
2856 struct pci_fixup *start, *end;
2857
2858 switch(pass) {
2859 case pci_fixup_early:
2860 start = __start_pci_fixups_early;
2861 end = __end_pci_fixups_early;
2862 break;
2863
2864 case pci_fixup_header:
2865 start = __start_pci_fixups_header;
2866 end = __end_pci_fixups_header;
2867 break;
2868
2869 case pci_fixup_final:
2870 start = __start_pci_fixups_final;
2871 end = __end_pci_fixups_final;
2872 break;
2873
2874 case pci_fixup_enable:
2875 start = __start_pci_fixups_enable;
2876 end = __end_pci_fixups_enable;
2877 break;
2878
2879 case pci_fixup_resume:
2880 start = __start_pci_fixups_resume;
2881 end = __end_pci_fixups_resume;
2882 break;
2883
2884 case pci_fixup_resume_early:
2885 start = __start_pci_fixups_resume_early;
2886 end = __end_pci_fixups_resume_early;
2887 break;
2888
2889 case pci_fixup_suspend:
2890 start = __start_pci_fixups_suspend;
2891 end = __end_pci_fixups_suspend;
2892 break;
2893
2894 default:
2895 /* stupid compiler warning, you would think with an enum... */
2896 return;
2897 }
2898 pci_do_fixups(dev, start, end);
2899}
2900EXPORT_SYMBOL(pci_fixup_device);
2901
2902static int __init pci_apply_final_quirks(void)
2903{
2904 struct pci_dev *dev = NULL;
2905 u8 cls = 0;
2906 u8 tmp;
2907
2908 if (pci_cache_line_size)
2909 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2910 pci_cache_line_size << 2);
2911
2912 for_each_pci_dev(dev) {
2913 pci_fixup_device(pci_fixup_final, dev);
2914 /*
2915 * If arch hasn't set it explicitly yet, use the CLS
2916 * value shared by all PCI devices. If there's a
2917 * mismatch, fall back to the default value.
2918 */
2919 if (!pci_cache_line_size) {
2920 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
2921 if (!cls)
2922 cls = tmp;
2923 if (!tmp || cls == tmp)
2924 continue;
2925
2926 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
2927 "using %u bytes\n", cls << 2, tmp << 2,
2928 pci_dfl_cache_line_size << 2);
2929 pci_cache_line_size = pci_dfl_cache_line_size;
2930 }
2931 }
2932 if (!pci_cache_line_size) {
2933 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
2934 cls << 2, pci_dfl_cache_line_size << 2);
2935 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
2936 }
2937
2938 return 0;
2939}
2940
2941fs_initcall_sync(pci_apply_final_quirks);
2942
2943/*
2944 * Followings are device-specific reset methods which can be used to
2945 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
2946 * not available.
2947 */
2948static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
2949{
2950 int pos;
2951
2952 /* only implement PCI_CLASS_SERIAL_USB at present */
2953 if (dev->class == PCI_CLASS_SERIAL_USB) {
2954 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
2955 if (!pos)
2956 return -ENOTTY;
2957
2958 if (probe)
2959 return 0;
2960
2961 pci_write_config_byte(dev, pos + 0x4, 1);
2962 msleep(100);
2963
2964 return 0;
2965 } else {
2966 return -ENOTTY;
2967 }
2968}
2969
2970static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
2971{
2972 int pos;
2973
2974 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2975 if (!pos)
2976 return -ENOTTY;
2977
2978 if (probe)
2979 return 0;
2980
2981 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2982 PCI_EXP_DEVCTL_BCR_FLR);
2983 msleep(100);
2984
2985 return 0;
2986}
2987
2988#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
2989
2990static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
2991 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
2992 reset_intel_82599_sfp_virtfn },
2993 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2994 reset_intel_generic_dev },
2995 { 0 }
2996};
2997
2998int pci_dev_specific_reset(struct pci_dev *dev, int probe)
2999{
3000 const struct pci_dev_reset_methods *i;
3001
3002 for (i = pci_dev_reset_methods; i->reset; i++) {
3003 if ((i->vendor == dev->vendor ||
3004 i->vendor == (u16)PCI_ANY_ID) &&
3005 (i->device == dev->device ||
3006 i->device == (u16)PCI_ANY_ID))
3007 return i->reset(dev, probe);
3008 }
3009
3010 return -ENOTTY;
3011}
1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 */
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/export.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/acpi.h>
21#include <linux/kallsyms.h>
22#include <linux/dmi.h>
23#include <linux/pci-aspm.h>
24#include <linux/ioport.h>
25#include <linux/sched.h>
26#include <linux/ktime.h>
27#include <linux/mm.h>
28#include <asm/dma.h> /* isa_dma_bridge_buggy */
29#include "pci.h"
30
31/*
32 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
36 */
37static void quirk_mmio_always_on(struct pci_dev *dev)
38{
39 dev->mmio_always_on = 1;
40}
41DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
43
44/* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
47 */
48static void quirk_mellanox_tavor(struct pci_dev *dev)
49{
50 dev->broken_parity_status = 1; /* This device gives false positives */
51}
52DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
53DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
54
55/* Deal with broken BIOSes that neglect to enable passive release,
56 which can cause problems in combination with the 82441FX/PPro MTRRs */
57static void quirk_passive_release(struct pci_dev *dev)
58{
59 struct pci_dev *d = NULL;
60 unsigned char dlc;
61
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
66 if (!(dlc & 1<<1)) {
67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
68 dlc |= 1<<1;
69 pci_write_config_byte(d, 0x82, dlc);
70 }
71 }
72}
73DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
75
76/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
78 ask them for me please -- Alan
79
80 This appears to be BIOS not version dependent. So presumably there is a
81 chipset level fix */
82
83static void quirk_isa_dma_hangs(struct pci_dev *dev)
84{
85 if (!isa_dma_bridge_buggy) {
86 isa_dma_bridge_buggy = 1;
87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
88 }
89}
90 /*
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
93 */
94DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
101
102/*
103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
105 */
106static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
107{
108 u32 pmbase;
109 u16 pm1a;
110
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
113 pm1a = inw(pmbase);
114
115 if (pm1a & 0x10) {
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
117 outw(0x10, pmbase);
118 }
119}
120DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
121
122/*
123 * Chipsets where PCI->PCI transfers vanish or hang
124 */
125static void quirk_nopcipci(struct pci_dev *dev)
126{
127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
129 pci_pci_problems |= PCIPCI_FAIL;
130 }
131}
132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
134
135static void quirk_nopciamd(struct pci_dev *dev)
136{
137 u8 rev;
138 pci_read_config_byte(dev, 0x08, &rev);
139 if (rev == 0x13) {
140 /* Erratum 24 */
141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
142 pci_pci_problems |= PCIAGP_FAIL;
143 }
144}
145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
146
147/*
148 * Triton requires workarounds to be used by the drivers
149 */
150static void quirk_triton(struct pci_dev *dev)
151{
152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
154 pci_pci_problems |= PCIPCI_TRITON;
155 }
156}
157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
161
162/*
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
168 *
169 * Updated based on further information from the site and also on
170 * information provided by VIA
171 */
172static void quirk_vialatency(struct pci_dev *dev)
173{
174 struct pci_dev *p;
175 u8 busarb;
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
178
179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
180 if (p != NULL) {
181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
183 if (p->revision < 0x40 || p->revision > 0x42)
184 goto exit;
185 } else {
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
187 if (p == NULL) /* No problem parts */
188 goto exit;
189 /* Check for buggy part revisions */
190 if (p->revision < 0x10 || p->revision > 0x12)
191 goto exit;
192 }
193
194 /*
195 * Ok we have the problem. Now set the PCI master grant to
196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
200 *
201 * VIA only apply this fix when an SB Live! is present but under
202 * both Linux and Windows this isn't enough, and we have seen
203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
205 */
206
207 pci_read_config_byte(dev, 0x76, &busarb);
208 /* Set bit 4 and bi 5 of byte 76 to 0x01
209 "Master priority rotation on every PCI master grant */
210 busarb &= ~(1<<5);
211 busarb |= (1<<4);
212 pci_write_config_byte(dev, 0x76, busarb);
213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
214exit:
215 pci_dev_put(p);
216}
217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
220/* Must restore this on a resume from RAM */
221DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224
225/*
226 * VIA Apollo VP3 needs ETBF on BT848/878
227 */
228static void quirk_viaetbf(struct pci_dev *dev)
229{
230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
232 pci_pci_problems |= PCIPCI_VIAETBF;
233 }
234}
235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
236
237static void quirk_vsfx(struct pci_dev *dev)
238{
239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
241 pci_pci_problems |= PCIPCI_VSFX;
242 }
243}
244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
245
246/*
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
251 */
252static void quirk_alimagik(struct pci_dev *dev)
253{
254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
257 }
258}
259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
261
262/*
263 * Natoma has some interesting boundary conditions with Zoran stuff
264 * at least
265 */
266static void quirk_natoma(struct pci_dev *dev)
267{
268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
270 pci_pci_problems |= PCIPCI_NATOMA;
271 }
272}
273DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
279
280/*
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
283 */
284static void quirk_citrine(struct pci_dev *dev)
285{
286 dev->cfg_size = 0xA0;
287}
288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
289
290/*
291 * This chip can cause bus lockups if config addresses above 0x600
292 * are read or written.
293 */
294static void quirk_nfp6000(struct pci_dev *dev)
295{
296 dev->cfg_size = 0x600;
297}
298DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
301
302/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
303static void quirk_extend_bar_to_page(struct pci_dev *dev)
304{
305 int i;
306
307 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
308 struct resource *r = &dev->resource[i];
309
310 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
311 r->end = PAGE_SIZE - 1;
312 r->start = 0;
313 r->flags |= IORESOURCE_UNSET;
314 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
315 i, r);
316 }
317 }
318}
319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
320
321/*
322 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
323 * If it's needed, re-allocate the region.
324 */
325static void quirk_s3_64M(struct pci_dev *dev)
326{
327 struct resource *r = &dev->resource[0];
328
329 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
330 r->flags |= IORESOURCE_UNSET;
331 r->start = 0;
332 r->end = 0x3ffffff;
333 }
334}
335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
337
338static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
339 const char *name)
340{
341 u32 region;
342 struct pci_bus_region bus_region;
343 struct resource *res = dev->resource + pos;
344
345 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
346
347 if (!region)
348 return;
349
350 res->name = pci_name(dev);
351 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
352 res->flags |=
353 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
354 region &= ~(size - 1);
355
356 /* Convert from PCI bus to resource space */
357 bus_region.start = region;
358 bus_region.end = region + size - 1;
359 pcibios_bus_to_resource(dev->bus, res, &bus_region);
360
361 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
362 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
363}
364
365/*
366 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
367 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
368 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
369 * (which conflicts w/ BAR1's memory range).
370 *
371 * CS553x's ISA PCI BARs may also be read-only (ref:
372 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
373 */
374static void quirk_cs5536_vsa(struct pci_dev *dev)
375{
376 static char *name = "CS5536 ISA bridge";
377
378 if (pci_resource_len(dev, 0) != 8) {
379 quirk_io(dev, 0, 8, name); /* SMB */
380 quirk_io(dev, 1, 256, name); /* GPIO */
381 quirk_io(dev, 2, 64, name); /* MFGPT */
382 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
383 name);
384 }
385}
386DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
387
388static void quirk_io_region(struct pci_dev *dev, int port,
389 unsigned size, int nr, const char *name)
390{
391 u16 region;
392 struct pci_bus_region bus_region;
393 struct resource *res = dev->resource + nr;
394
395 pci_read_config_word(dev, port, ®ion);
396 region &= ~(size - 1);
397
398 if (!region)
399 return;
400
401 res->name = pci_name(dev);
402 res->flags = IORESOURCE_IO;
403
404 /* Convert from PCI bus to resource space */
405 bus_region.start = region;
406 bus_region.end = region + size - 1;
407 pcibios_bus_to_resource(dev->bus, res, &bus_region);
408
409 if (!pci_claim_resource(dev, nr))
410 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
411}
412
413/*
414 * ATI Northbridge setups MCE the processor if you even
415 * read somewhere between 0x3b0->0x3bb or read 0x3d3
416 */
417static void quirk_ati_exploding_mce(struct pci_dev *dev)
418{
419 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
420 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
421 request_region(0x3b0, 0x0C, "RadeonIGP");
422 request_region(0x3d3, 0x01, "RadeonIGP");
423}
424DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
425
426/*
427 * In the AMD NL platform, this device ([1022:7912]) has a class code of
428 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
429 * claim it.
430 * But the dwc3 driver is a more specific driver for this device, and we'd
431 * prefer to use it instead of xhci. To prevent xhci from claiming the
432 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
433 * defines as "USB device (not host controller)". The dwc3 driver can then
434 * claim it based on its Vendor and Device ID.
435 */
436static void quirk_amd_nl_class(struct pci_dev *pdev)
437{
438 u32 class = pdev->class;
439
440 /* Use "USB Device (not host controller)" class */
441 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
442 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
443 class, pdev->class);
444}
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
446 quirk_amd_nl_class);
447
448/*
449 * Let's make the southbridge information explicit instead
450 * of having to worry about people probing the ACPI areas,
451 * for example.. (Yes, it happens, and if you read the wrong
452 * ACPI register it will put the machine to sleep with no
453 * way of waking it up again. Bummer).
454 *
455 * ALI M7101: Two IO regions pointed to by words at
456 * 0xE0 (64 bytes of ACPI registers)
457 * 0xE2 (32 bytes of SMB registers)
458 */
459static void quirk_ali7101_acpi(struct pci_dev *dev)
460{
461 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
462 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
463}
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
465
466static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
467{
468 u32 devres;
469 u32 mask, size, base;
470
471 pci_read_config_dword(dev, port, &devres);
472 if ((devres & enable) != enable)
473 return;
474 mask = (devres >> 16) & 15;
475 base = devres & 0xffff;
476 size = 16;
477 for (;;) {
478 unsigned bit = size >> 1;
479 if ((bit & mask) == bit)
480 break;
481 size = bit;
482 }
483 /*
484 * For now we only print it out. Eventually we'll want to
485 * reserve it (at least if it's in the 0x1000+ range), but
486 * let's get enough confirmation reports first.
487 */
488 base &= -size;
489 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
490 base + size - 1);
491}
492
493static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
494{
495 u32 devres;
496 u32 mask, size, base;
497
498 pci_read_config_dword(dev, port, &devres);
499 if ((devres & enable) != enable)
500 return;
501 base = devres & 0xffff0000;
502 mask = (devres & 0x3f) << 16;
503 size = 128 << 16;
504 for (;;) {
505 unsigned bit = size >> 1;
506 if ((bit & mask) == bit)
507 break;
508 size = bit;
509 }
510 /*
511 * For now we only print it out. Eventually we'll want to
512 * reserve it, but let's get enough confirmation reports first.
513 */
514 base &= -size;
515 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
516 base + size - 1);
517}
518
519/*
520 * PIIX4 ACPI: Two IO regions pointed to by longwords at
521 * 0x40 (64 bytes of ACPI registers)
522 * 0x90 (16 bytes of SMB registers)
523 * and a few strange programmable PIIX4 device resources.
524 */
525static void quirk_piix4_acpi(struct pci_dev *dev)
526{
527 u32 res_a;
528
529 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
530 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
531
532 /* Device resource A has enables for some of the other ones */
533 pci_read_config_dword(dev, 0x5c, &res_a);
534
535 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
536 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
537
538 /* Device resource D is just bitfields for static resources */
539
540 /* Device 12 enabled? */
541 if (res_a & (1 << 29)) {
542 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
543 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
544 }
545 /* Device 13 enabled? */
546 if (res_a & (1 << 30)) {
547 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
548 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
549 }
550 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
551 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
552}
553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
554DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
555
556#define ICH_PMBASE 0x40
557#define ICH_ACPI_CNTL 0x44
558#define ICH4_ACPI_EN 0x10
559#define ICH6_ACPI_EN 0x80
560#define ICH4_GPIOBASE 0x58
561#define ICH4_GPIO_CNTL 0x5c
562#define ICH4_GPIO_EN 0x10
563#define ICH6_GPIOBASE 0x48
564#define ICH6_GPIO_CNTL 0x4c
565#define ICH6_GPIO_EN 0x10
566
567/*
568 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
569 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
570 * 0x58 (64 bytes of GPIO I/O space)
571 */
572static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
573{
574 u8 enable;
575
576 /*
577 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
578 * with low legacy (and fixed) ports. We don't know the decoding
579 * priority and can't tell whether the legacy device or the one created
580 * here is really at that address. This happens on boards with broken
581 * BIOSes.
582 */
583
584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
585 if (enable & ICH4_ACPI_EN)
586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
587 "ICH4 ACPI/GPIO/TCO");
588
589 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
590 if (enable & ICH4_GPIO_EN)
591 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
592 "ICH4 GPIO");
593}
594DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
597DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
598DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
599DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
600DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
604
605static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
606{
607 u8 enable;
608
609 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
610 if (enable & ICH6_ACPI_EN)
611 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
612 "ICH6 ACPI/GPIO/TCO");
613
614 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
615 if (enable & ICH6_GPIO_EN)
616 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
617 "ICH6 GPIO");
618}
619
620static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
621{
622 u32 val;
623 u32 size, base;
624
625 pci_read_config_dword(dev, reg, &val);
626
627 /* Enabled? */
628 if (!(val & 1))
629 return;
630 base = val & 0xfffc;
631 if (dynsize) {
632 /*
633 * This is not correct. It is 16, 32 or 64 bytes depending on
634 * register D31:F0:ADh bits 5:4.
635 *
636 * But this gets us at least _part_ of it.
637 */
638 size = 16;
639 } else {
640 size = 128;
641 }
642 base &= ~(size-1);
643
644 /* Just print it out for now. We should reserve it after more debugging */
645 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
646}
647
648static void quirk_ich6_lpc(struct pci_dev *dev)
649{
650 /* Shared ACPI/GPIO decode with all ICH6+ */
651 ich6_lpc_acpi_gpio(dev);
652
653 /* ICH6-specific generic IO decode */
654 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
655 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
656}
657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
659
660static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
661{
662 u32 val;
663 u32 mask, base;
664
665 pci_read_config_dword(dev, reg, &val);
666
667 /* Enabled? */
668 if (!(val & 1))
669 return;
670
671 /*
672 * IO base in bits 15:2, mask in bits 23:18, both
673 * are dword-based
674 */
675 base = val & 0xfffc;
676 mask = (val >> 16) & 0xfc;
677 mask |= 3;
678
679 /* Just print it out for now. We should reserve it after more debugging */
680 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
681}
682
683/* ICH7-10 has the same common LPC generic IO decode registers */
684static void quirk_ich7_lpc(struct pci_dev *dev)
685{
686 /* We share the common ACPI/GPIO decode with ICH6 */
687 ich6_lpc_acpi_gpio(dev);
688
689 /* And have 4 ICH7+ generic decodes */
690 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
691 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
692 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
693 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
694}
695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
708
709/*
710 * VIA ACPI: One IO region pointed to by longword at
711 * 0x48 or 0x20 (256 bytes of ACPI registers)
712 */
713static void quirk_vt82c586_acpi(struct pci_dev *dev)
714{
715 if (dev->revision & 0x10)
716 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
717 "vt82c586 ACPI");
718}
719DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
720
721/*
722 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
723 * 0x48 (256 bytes of ACPI registers)
724 * 0x70 (128 bytes of hardware monitoring register)
725 * 0x90 (16 bytes of SMB registers)
726 */
727static void quirk_vt82c686_acpi(struct pci_dev *dev)
728{
729 quirk_vt82c586_acpi(dev);
730
731 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
732 "vt82c686 HW-mon");
733
734 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
735}
736DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
737
738/*
739 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
740 * 0x88 (128 bytes of power management registers)
741 * 0xd0 (16 bytes of SMB registers)
742 */
743static void quirk_vt8235_acpi(struct pci_dev *dev)
744{
745 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
746 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
747}
748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
749
750/*
751 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
752 * Disable fast back-to-back on the secondary bus segment
753 */
754static void quirk_xio2000a(struct pci_dev *dev)
755{
756 struct pci_dev *pdev;
757 u16 command;
758
759 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
760 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
761 pci_read_config_word(pdev, PCI_COMMAND, &command);
762 if (command & PCI_COMMAND_FAST_BACK)
763 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
764 }
765}
766DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
767 quirk_xio2000a);
768
769#ifdef CONFIG_X86_IO_APIC
770
771#include <asm/io_apic.h>
772
773/*
774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
775 * devices to the external APIC.
776 *
777 * TODO: When we have device-specific interrupt routers,
778 * this code will go away from quirks.
779 */
780static void quirk_via_ioapic(struct pci_dev *dev)
781{
782 u8 tmp;
783
784 if (nr_ioapics < 1)
785 tmp = 0; /* nothing routed to external APIC */
786 else
787 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
788
789 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
790 tmp == 0 ? "Disa" : "Ena");
791
792 /* Offset 0x58: External APIC IRQ output control */
793 pci_write_config_byte(dev, 0x58, tmp);
794}
795DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
796DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
797
798/*
799 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
800 * This leads to doubled level interrupt rates.
801 * Set this bit to get rid of cycle wastage.
802 * Otherwise uncritical.
803 */
804static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
805{
806 u8 misc_control2;
807#define BYPASS_APIC_DEASSERT 8
808
809 pci_read_config_byte(dev, 0x5B, &misc_control2);
810 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
811 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
812 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
813 }
814}
815DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
816DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
817
818/*
819 * The AMD io apic can hang the box when an apic irq is masked.
820 * We check all revs >= B0 (yet not in the pre production!) as the bug
821 * is currently marked NoFix
822 *
823 * We have multiple reports of hangs with this chipset that went away with
824 * noapic specified. For the moment we assume it's the erratum. We may be wrong
825 * of course. However the advice is demonstrably good even if so..
826 */
827static void quirk_amd_ioapic(struct pci_dev *dev)
828{
829 if (dev->revision >= 0x02) {
830 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
831 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
832 }
833}
834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
835#endif /* CONFIG_X86_IO_APIC */
836
837/*
838 * Some settings of MMRBC can lead to data corruption so block changes.
839 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
840 */
841static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
842{
843 if (dev->subordinate && dev->revision <= 0x12) {
844 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
845 dev->revision);
846 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
847 }
848}
849DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
850
851/*
852 * FIXME: it is questionable that quirk_via_acpi
853 * is needed. It shows up as an ISA bridge, and does not
854 * support the PCI_INTERRUPT_LINE register at all. Therefore
855 * it seems like setting the pci_dev's 'irq' to the
856 * value of the ACPI SCI interrupt is only done for convenience.
857 * -jgarzik
858 */
859static void quirk_via_acpi(struct pci_dev *d)
860{
861 /*
862 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
863 */
864 u8 irq;
865 pci_read_config_byte(d, 0x42, &irq);
866 irq &= 0xf;
867 if (irq && (irq != 2))
868 d->irq = irq;
869}
870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
871DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
872
873
874/*
875 * VIA bridges which have VLink
876 */
877
878static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
879
880static void quirk_via_bridge(struct pci_dev *dev)
881{
882 /* See what bridge we have and find the device ranges */
883 switch (dev->device) {
884 case PCI_DEVICE_ID_VIA_82C686:
885 /* The VT82C686 is special, it attaches to PCI and can have
886 any device number. All its subdevices are functions of
887 that single device. */
888 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
889 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
890 break;
891 case PCI_DEVICE_ID_VIA_8237:
892 case PCI_DEVICE_ID_VIA_8237A:
893 via_vlink_dev_lo = 15;
894 break;
895 case PCI_DEVICE_ID_VIA_8235:
896 via_vlink_dev_lo = 16;
897 break;
898 case PCI_DEVICE_ID_VIA_8231:
899 case PCI_DEVICE_ID_VIA_8233_0:
900 case PCI_DEVICE_ID_VIA_8233A:
901 case PCI_DEVICE_ID_VIA_8233C_0:
902 via_vlink_dev_lo = 17;
903 break;
904 }
905}
906DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
907DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
908DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
909DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
910DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
911DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
912DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
913DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
914
915/**
916 * quirk_via_vlink - VIA VLink IRQ number update
917 * @dev: PCI device
918 *
919 * If the device we are dealing with is on a PIC IRQ we need to
920 * ensure that the IRQ line register which usually is not relevant
921 * for PCI cards, is actually written so that interrupts get sent
922 * to the right place.
923 * We only do this on systems where a VIA south bridge was detected,
924 * and only for VIA devices on the motherboard (see quirk_via_bridge
925 * above).
926 */
927
928static void quirk_via_vlink(struct pci_dev *dev)
929{
930 u8 irq, new_irq;
931
932 /* Check if we have VLink at all */
933 if (via_vlink_dev_lo == -1)
934 return;
935
936 new_irq = dev->irq;
937
938 /* Don't quirk interrupts outside the legacy IRQ range */
939 if (!new_irq || new_irq > 15)
940 return;
941
942 /* Internal device ? */
943 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
944 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
945 return;
946
947 /* This is an internal VLink device on a PIC interrupt. The BIOS
948 ought to have set this but may not have, so we redo it */
949
950 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
951 if (new_irq != irq) {
952 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
953 irq, new_irq);
954 udelay(15); /* unknown if delay really needed */
955 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
956 }
957}
958DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
959
960/*
961 * VIA VT82C598 has its device ID settable and many BIOSes
962 * set it to the ID of VT82C597 for backward compatibility.
963 * We need to switch it off to be able to recognize the real
964 * type of the chip.
965 */
966static void quirk_vt82c598_id(struct pci_dev *dev)
967{
968 pci_write_config_byte(dev, 0xfc, 0);
969 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
970}
971DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
972
973/*
974 * CardBus controllers have a legacy base address that enables them
975 * to respond as i82365 pcmcia controllers. We don't want them to
976 * do this even if the Linux CardBus driver is not loaded, because
977 * the Linux i82365 driver does not (and should not) handle CardBus.
978 */
979static void quirk_cardbus_legacy(struct pci_dev *dev)
980{
981 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
982}
983DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
984 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
985DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
986 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
987
988/*
989 * Following the PCI ordering rules is optional on the AMD762. I'm not
990 * sure what the designers were smoking but let's not inhale...
991 *
992 * To be fair to AMD, it follows the spec by default, its BIOS people
993 * who turn it off!
994 */
995static void quirk_amd_ordering(struct pci_dev *dev)
996{
997 u32 pcic;
998 pci_read_config_dword(dev, 0x4C, &pcic);
999 if ((pcic & 6) != 6) {
1000 pcic |= 6;
1001 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1002 pci_write_config_dword(dev, 0x4C, pcic);
1003 pci_read_config_dword(dev, 0x84, &pcic);
1004 pcic |= (1 << 23); /* Required in this mode */
1005 pci_write_config_dword(dev, 0x84, pcic);
1006 }
1007}
1008DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1009DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1010
1011/*
1012 * DreamWorks provided workaround for Dunord I-3000 problem
1013 *
1014 * This card decodes and responds to addresses not apparently
1015 * assigned to it. We force a larger allocation to ensure that
1016 * nothing gets put too close to it.
1017 */
1018static void quirk_dunord(struct pci_dev *dev)
1019{
1020 struct resource *r = &dev->resource[1];
1021
1022 r->flags |= IORESOURCE_UNSET;
1023 r->start = 0;
1024 r->end = 0xffffff;
1025}
1026DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1027
1028/*
1029 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1030 * is subtractive decoding (transparent), and does indicate this
1031 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1032 * instead of 0x01.
1033 */
1034static void quirk_transparent_bridge(struct pci_dev *dev)
1035{
1036 dev->transparent = 1;
1037}
1038DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1039DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1040
1041/*
1042 * Common misconfiguration of the MediaGX/Geode PCI master that will
1043 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1044 * datasheets found at http://www.national.com/analog for info on what
1045 * these bits do. <christer@weinigel.se>
1046 */
1047static void quirk_mediagx_master(struct pci_dev *dev)
1048{
1049 u8 reg;
1050
1051 pci_read_config_byte(dev, 0x41, ®);
1052 if (reg & 2) {
1053 reg &= ~2;
1054 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1055 reg);
1056 pci_write_config_byte(dev, 0x41, reg);
1057 }
1058}
1059DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1060DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1061
1062/*
1063 * Ensure C0 rev restreaming is off. This is normally done by
1064 * the BIOS but in the odd case it is not the results are corruption
1065 * hence the presence of a Linux check
1066 */
1067static void quirk_disable_pxb(struct pci_dev *pdev)
1068{
1069 u16 config;
1070
1071 if (pdev->revision != 0x04) /* Only C0 requires this */
1072 return;
1073 pci_read_config_word(pdev, 0x40, &config);
1074 if (config & (1<<6)) {
1075 config &= ~(1<<6);
1076 pci_write_config_word(pdev, 0x40, config);
1077 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1078 }
1079}
1080DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1081DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1082
1083static void quirk_amd_ide_mode(struct pci_dev *pdev)
1084{
1085 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1086 u8 tmp;
1087
1088 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1089 if (tmp == 0x01) {
1090 pci_read_config_byte(pdev, 0x40, &tmp);
1091 pci_write_config_byte(pdev, 0x40, tmp|1);
1092 pci_write_config_byte(pdev, 0x9, 1);
1093 pci_write_config_byte(pdev, 0xa, 6);
1094 pci_write_config_byte(pdev, 0x40, tmp);
1095
1096 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1097 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1098 }
1099}
1100DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1101DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1102DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1103DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1104DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1105DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1107DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1108
1109/*
1110 * Serverworks CSB5 IDE does not fully support native mode
1111 */
1112static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1113{
1114 u8 prog;
1115 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1116 if (prog & 5) {
1117 prog &= ~5;
1118 pdev->class &= ~5;
1119 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1120 /* PCI layer will sort out resources */
1121 }
1122}
1123DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1124
1125/*
1126 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1127 */
1128static void quirk_ide_samemode(struct pci_dev *pdev)
1129{
1130 u8 prog;
1131
1132 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1133
1134 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1135 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1136 prog &= ~5;
1137 pdev->class &= ~5;
1138 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1139 }
1140}
1141DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1142
1143/*
1144 * Some ATA devices break if put into D3
1145 */
1146
1147static void quirk_no_ata_d3(struct pci_dev *pdev)
1148{
1149 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1150}
1151/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1152DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1153 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1154DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1155 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1156/* ALi loses some register settings that we cannot then restore */
1157DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1158 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1159/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1160 occur when mode detecting */
1161DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1162 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1163
1164/* This was originally an Alpha specific thing, but it really fits here.
1165 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1166 */
1167static void quirk_eisa_bridge(struct pci_dev *dev)
1168{
1169 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1170}
1171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1172
1173
1174/*
1175 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1176 * is not activated. The myth is that Asus said that they do not want the
1177 * users to be irritated by just another PCI Device in the Win98 device
1178 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1179 * package 2.7.0 for details)
1180 *
1181 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1182 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1183 * becomes necessary to do this tweak in two steps -- the chosen trigger
1184 * is either the Host bridge (preferred) or on-board VGA controller.
1185 *
1186 * Note that we used to unhide the SMBus that way on Toshiba laptops
1187 * (Satellite A40 and Tecra M2) but then found that the thermal management
1188 * was done by SMM code, which could cause unsynchronized concurrent
1189 * accesses to the SMBus registers, with potentially bad effects. Thus you
1190 * should be very careful when adding new entries: if SMM is accessing the
1191 * Intel SMBus, this is a very good reason to leave it hidden.
1192 *
1193 * Likewise, many recent laptops use ACPI for thermal management. If the
1194 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1195 * natively, and keeping the SMBus hidden is the right thing to do. If you
1196 * are about to add an entry in the table below, please first disassemble
1197 * the DSDT and double-check that there is no code accessing the SMBus.
1198 */
1199static int asus_hides_smbus;
1200
1201static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1202{
1203 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1204 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1205 switch (dev->subsystem_device) {
1206 case 0x8025: /* P4B-LX */
1207 case 0x8070: /* P4B */
1208 case 0x8088: /* P4B533 */
1209 case 0x1626: /* L3C notebook */
1210 asus_hides_smbus = 1;
1211 }
1212 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1213 switch (dev->subsystem_device) {
1214 case 0x80b1: /* P4GE-V */
1215 case 0x80b2: /* P4PE */
1216 case 0x8093: /* P4B533-V */
1217 asus_hides_smbus = 1;
1218 }
1219 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1220 switch (dev->subsystem_device) {
1221 case 0x8030: /* P4T533 */
1222 asus_hides_smbus = 1;
1223 }
1224 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1225 switch (dev->subsystem_device) {
1226 case 0x8070: /* P4G8X Deluxe */
1227 asus_hides_smbus = 1;
1228 }
1229 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1230 switch (dev->subsystem_device) {
1231 case 0x80c9: /* PU-DLS */
1232 asus_hides_smbus = 1;
1233 }
1234 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1235 switch (dev->subsystem_device) {
1236 case 0x1751: /* M2N notebook */
1237 case 0x1821: /* M5N notebook */
1238 case 0x1897: /* A6L notebook */
1239 asus_hides_smbus = 1;
1240 }
1241 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1242 switch (dev->subsystem_device) {
1243 case 0x184b: /* W1N notebook */
1244 case 0x186a: /* M6Ne notebook */
1245 asus_hides_smbus = 1;
1246 }
1247 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1248 switch (dev->subsystem_device) {
1249 case 0x80f2: /* P4P800-X */
1250 asus_hides_smbus = 1;
1251 }
1252 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1253 switch (dev->subsystem_device) {
1254 case 0x1882: /* M6V notebook */
1255 case 0x1977: /* A6VA notebook */
1256 asus_hides_smbus = 1;
1257 }
1258 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1259 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1260 switch (dev->subsystem_device) {
1261 case 0x088C: /* HP Compaq nc8000 */
1262 case 0x0890: /* HP Compaq nc6000 */
1263 asus_hides_smbus = 1;
1264 }
1265 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1266 switch (dev->subsystem_device) {
1267 case 0x12bc: /* HP D330L */
1268 case 0x12bd: /* HP D530 */
1269 case 0x006a: /* HP Compaq nx9500 */
1270 asus_hides_smbus = 1;
1271 }
1272 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1273 switch (dev->subsystem_device) {
1274 case 0x12bf: /* HP xw4100 */
1275 asus_hides_smbus = 1;
1276 }
1277 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1278 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1279 switch (dev->subsystem_device) {
1280 case 0xC00C: /* Samsung P35 notebook */
1281 asus_hides_smbus = 1;
1282 }
1283 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1284 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1285 switch (dev->subsystem_device) {
1286 case 0x0058: /* Compaq Evo N620c */
1287 asus_hides_smbus = 1;
1288 }
1289 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1290 switch (dev->subsystem_device) {
1291 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1292 /* Motherboard doesn't have Host bridge
1293 * subvendor/subdevice IDs, therefore checking
1294 * its on-board VGA controller */
1295 asus_hides_smbus = 1;
1296 }
1297 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1298 switch (dev->subsystem_device) {
1299 case 0x00b8: /* Compaq Evo D510 CMT */
1300 case 0x00b9: /* Compaq Evo D510 SFF */
1301 case 0x00ba: /* Compaq Evo D510 USDT */
1302 /* Motherboard doesn't have Host bridge
1303 * subvendor/subdevice IDs and on-board VGA
1304 * controller is disabled if an AGP card is
1305 * inserted, therefore checking USB UHCI
1306 * Controller #1 */
1307 asus_hides_smbus = 1;
1308 }
1309 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1310 switch (dev->subsystem_device) {
1311 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1312 /* Motherboard doesn't have host bridge
1313 * subvendor/subdevice IDs, therefore checking
1314 * its on-board VGA controller */
1315 asus_hides_smbus = 1;
1316 }
1317 }
1318}
1319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1327DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1328DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1329
1330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1332DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1333
1334static void asus_hides_smbus_lpc(struct pci_dev *dev)
1335{
1336 u16 val;
1337
1338 if (likely(!asus_hides_smbus))
1339 return;
1340
1341 pci_read_config_word(dev, 0xF2, &val);
1342 if (val & 0x8) {
1343 pci_write_config_word(dev, 0xF2, val & (~0x8));
1344 pci_read_config_word(dev, 0xF2, &val);
1345 if (val & 0x8)
1346 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1347 val);
1348 else
1349 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1350 }
1351}
1352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1353DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1354DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1355DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1356DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1357DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1358DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1359DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1360DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1361DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1362DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1363DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1364DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1365DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1366
1367/* It appears we just have one such device. If not, we have a warning */
1368static void __iomem *asus_rcba_base;
1369static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1370{
1371 u32 rcba;
1372
1373 if (likely(!asus_hides_smbus))
1374 return;
1375 WARN_ON(asus_rcba_base);
1376
1377 pci_read_config_dword(dev, 0xF0, &rcba);
1378 /* use bits 31:14, 16 kB aligned */
1379 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1380 if (asus_rcba_base == NULL)
1381 return;
1382}
1383
1384static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1385{
1386 u32 val;
1387
1388 if (likely(!asus_hides_smbus || !asus_rcba_base))
1389 return;
1390 /* read the Function Disable register, dword mode only */
1391 val = readl(asus_rcba_base + 0x3418);
1392 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1393}
1394
1395static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1396{
1397 if (likely(!asus_hides_smbus || !asus_rcba_base))
1398 return;
1399 iounmap(asus_rcba_base);
1400 asus_rcba_base = NULL;
1401 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1402}
1403
1404static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1405{
1406 asus_hides_smbus_lpc_ich6_suspend(dev);
1407 asus_hides_smbus_lpc_ich6_resume_early(dev);
1408 asus_hides_smbus_lpc_ich6_resume(dev);
1409}
1410DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1411DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1412DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1413DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1414
1415/*
1416 * SiS 96x south bridge: BIOS typically hides SMBus device...
1417 */
1418static void quirk_sis_96x_smbus(struct pci_dev *dev)
1419{
1420 u8 val = 0;
1421 pci_read_config_byte(dev, 0x77, &val);
1422 if (val & 0x10) {
1423 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1424 pci_write_config_byte(dev, 0x77, val & ~0x10);
1425 }
1426}
1427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1428DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1430DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1431DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1432DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1433DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1434DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1435
1436/*
1437 * ... This is further complicated by the fact that some SiS96x south
1438 * bridges pretend to be 85C503/5513 instead. In that case see if we
1439 * spotted a compatible north bridge to make sure.
1440 * (pci_find_device doesn't work yet)
1441 *
1442 * We can also enable the sis96x bit in the discovery register..
1443 */
1444#define SIS_DETECT_REGISTER 0x40
1445
1446static void quirk_sis_503(struct pci_dev *dev)
1447{
1448 u8 reg;
1449 u16 devid;
1450
1451 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1452 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1453 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1454 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1455 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1456 return;
1457 }
1458
1459 /*
1460 * Ok, it now shows up as a 96x.. run the 96x quirk by
1461 * hand in case it has already been processed.
1462 * (depends on link order, which is apparently not guaranteed)
1463 */
1464 dev->device = devid;
1465 quirk_sis_96x_smbus(dev);
1466}
1467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1468DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1469
1470
1471/*
1472 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1473 * and MC97 modem controller are disabled when a second PCI soundcard is
1474 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1475 * -- bjd
1476 */
1477static void asus_hides_ac97_lpc(struct pci_dev *dev)
1478{
1479 u8 val;
1480 int asus_hides_ac97 = 0;
1481
1482 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1483 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1484 asus_hides_ac97 = 1;
1485 }
1486
1487 if (!asus_hides_ac97)
1488 return;
1489
1490 pci_read_config_byte(dev, 0x50, &val);
1491 if (val & 0xc0) {
1492 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1493 pci_read_config_byte(dev, 0x50, &val);
1494 if (val & 0xc0)
1495 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1496 val);
1497 else
1498 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1499 }
1500}
1501DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1502DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1503
1504#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1505
1506/*
1507 * If we are using libata we can drive this chip properly but must
1508 * do this early on to make the additional device appear during
1509 * the PCI scanning.
1510 */
1511static void quirk_jmicron_ata(struct pci_dev *pdev)
1512{
1513 u32 conf1, conf5, class;
1514 u8 hdr;
1515
1516 /* Only poke fn 0 */
1517 if (PCI_FUNC(pdev->devfn))
1518 return;
1519
1520 pci_read_config_dword(pdev, 0x40, &conf1);
1521 pci_read_config_dword(pdev, 0x80, &conf5);
1522
1523 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1524 conf5 &= ~(1 << 24); /* Clear bit 24 */
1525
1526 switch (pdev->device) {
1527 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1528 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1529 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1530 /* The controller should be in single function ahci mode */
1531 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1532 break;
1533
1534 case PCI_DEVICE_ID_JMICRON_JMB365:
1535 case PCI_DEVICE_ID_JMICRON_JMB366:
1536 /* Redirect IDE second PATA port to the right spot */
1537 conf5 |= (1 << 24);
1538 /* Fall through */
1539 case PCI_DEVICE_ID_JMICRON_JMB361:
1540 case PCI_DEVICE_ID_JMICRON_JMB363:
1541 case PCI_DEVICE_ID_JMICRON_JMB369:
1542 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1543 /* Set the class codes correctly and then direct IDE 0 */
1544 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1545 break;
1546
1547 case PCI_DEVICE_ID_JMICRON_JMB368:
1548 /* The controller should be in single function IDE mode */
1549 conf1 |= 0x00C00000; /* Set 22, 23 */
1550 break;
1551 }
1552
1553 pci_write_config_dword(pdev, 0x40, conf1);
1554 pci_write_config_dword(pdev, 0x80, conf5);
1555
1556 /* Update pdev accordingly */
1557 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1558 pdev->hdr_type = hdr & 0x7f;
1559 pdev->multifunction = !!(hdr & 0x80);
1560
1561 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1562 pdev->class = class >> 8;
1563}
1564DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1565DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1566DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1567DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1568DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1569DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1570DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1571DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1572DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1573DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1574DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1575DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1576DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1577DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1578DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1579DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1580DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1581DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1582
1583#endif
1584
1585static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1586{
1587 if (dev->multifunction) {
1588 device_disable_async_suspend(&dev->dev);
1589 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1590 }
1591}
1592DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1593DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1596
1597#ifdef CONFIG_X86_IO_APIC
1598static void quirk_alder_ioapic(struct pci_dev *pdev)
1599{
1600 int i;
1601
1602 if ((pdev->class >> 8) != 0xff00)
1603 return;
1604
1605 /* the first BAR is the location of the IO APIC...we must
1606 * not touch this (and it's already covered by the fixmap), so
1607 * forcibly insert it into the resource tree */
1608 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1609 insert_resource(&iomem_resource, &pdev->resource[0]);
1610
1611 /* The next five BARs all seem to be rubbish, so just clean
1612 * them out */
1613 for (i = 1; i < 6; i++)
1614 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1615}
1616DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1617#endif
1618
1619static void quirk_pcie_mch(struct pci_dev *pdev)
1620{
1621 pdev->no_msi = 1;
1622}
1623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1626
1627
1628/*
1629 * It's possible for the MSI to get corrupted if shpc and acpi
1630 * are used together on certain PXH-based systems.
1631 */
1632static void quirk_pcie_pxh(struct pci_dev *dev)
1633{
1634 dev->no_msi = 1;
1635 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1636}
1637DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1638DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1639DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1640DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1641DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1642
1643/*
1644 * Some Intel PCI Express chipsets have trouble with downstream
1645 * device power management.
1646 */
1647static void quirk_intel_pcie_pm(struct pci_dev *dev)
1648{
1649 pci_pm_d3_delay = 120;
1650 dev->no_d1d2 = 1;
1651}
1652
1653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1674
1675#ifdef CONFIG_X86_IO_APIC
1676/*
1677 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1678 * remap the original interrupt in the linux kernel to the boot interrupt, so
1679 * that a PCI device's interrupt handler is installed on the boot interrupt
1680 * line instead.
1681 */
1682static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1683{
1684 if (noioapicquirk || noioapicreroute)
1685 return;
1686
1687 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1688 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1689 dev->vendor, dev->device);
1690}
1691DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1692DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1693DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1694DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1695DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1697DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1699DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1700DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1701DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1702DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1703DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1704DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1705DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1706DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1707
1708/*
1709 * On some chipsets we can disable the generation of legacy INTx boot
1710 * interrupts.
1711 */
1712
1713/*
1714 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1715 * 300641-004US, section 5.7.3.
1716 */
1717#define INTEL_6300_IOAPIC_ABAR 0x40
1718#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1719
1720static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1721{
1722 u16 pci_config_word;
1723
1724 if (noioapicquirk)
1725 return;
1726
1727 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1728 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1729 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1730
1731 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1732 dev->vendor, dev->device);
1733}
1734DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1735DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1736
1737/*
1738 * disable boot interrupts on HT-1000
1739 */
1740#define BC_HT1000_FEATURE_REG 0x64
1741#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1742#define BC_HT1000_MAP_IDX 0xC00
1743#define BC_HT1000_MAP_DATA 0xC01
1744
1745static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1746{
1747 u32 pci_config_dword;
1748 u8 irq;
1749
1750 if (noioapicquirk)
1751 return;
1752
1753 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1754 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1755 BC_HT1000_PIC_REGS_ENABLE);
1756
1757 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1758 outb(irq, BC_HT1000_MAP_IDX);
1759 outb(0x00, BC_HT1000_MAP_DATA);
1760 }
1761
1762 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1763
1764 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1765 dev->vendor, dev->device);
1766}
1767DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1768DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1769
1770/*
1771 * disable boot interrupts on AMD and ATI chipsets
1772 */
1773/*
1774 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1775 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1776 * (due to an erratum).
1777 */
1778#define AMD_813X_MISC 0x40
1779#define AMD_813X_NOIOAMODE (1<<0)
1780#define AMD_813X_REV_B1 0x12
1781#define AMD_813X_REV_B2 0x13
1782
1783static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1784{
1785 u32 pci_config_dword;
1786
1787 if (noioapicquirk)
1788 return;
1789 if ((dev->revision == AMD_813X_REV_B1) ||
1790 (dev->revision == AMD_813X_REV_B2))
1791 return;
1792
1793 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1794 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1795 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1796
1797 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1798 dev->vendor, dev->device);
1799}
1800DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1801DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1802DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1803DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1804
1805#define AMD_8111_PCI_IRQ_ROUTING 0x56
1806
1807static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1808{
1809 u16 pci_config_word;
1810
1811 if (noioapicquirk)
1812 return;
1813
1814 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1815 if (!pci_config_word) {
1816 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1817 dev->vendor, dev->device);
1818 return;
1819 }
1820 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1821 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1822 dev->vendor, dev->device);
1823}
1824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1825DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1826#endif /* CONFIG_X86_IO_APIC */
1827
1828/*
1829 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1830 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1831 * Re-allocate the region if needed...
1832 */
1833static void quirk_tc86c001_ide(struct pci_dev *dev)
1834{
1835 struct resource *r = &dev->resource[0];
1836
1837 if (r->start & 0x8) {
1838 r->flags |= IORESOURCE_UNSET;
1839 r->start = 0;
1840 r->end = 0xf;
1841 }
1842}
1843DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1844 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1845 quirk_tc86c001_ide);
1846
1847/*
1848 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1849 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1850 * being read correctly if bit 7 of the base address is set.
1851 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1852 * Re-allocate the regions to a 256-byte boundary if necessary.
1853 */
1854static void quirk_plx_pci9050(struct pci_dev *dev)
1855{
1856 unsigned int bar;
1857
1858 /* Fixed in revision 2 (PCI 9052). */
1859 if (dev->revision >= 2)
1860 return;
1861 for (bar = 0; bar <= 1; bar++)
1862 if (pci_resource_len(dev, bar) == 0x80 &&
1863 (pci_resource_start(dev, bar) & 0x80)) {
1864 struct resource *r = &dev->resource[bar];
1865 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1866 bar);
1867 r->flags |= IORESOURCE_UNSET;
1868 r->start = 0;
1869 r->end = 0xff;
1870 }
1871}
1872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1873 quirk_plx_pci9050);
1874/*
1875 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1876 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1877 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1878 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1879 *
1880 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1881 * driver.
1882 */
1883DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1884DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1885
1886static void quirk_netmos(struct pci_dev *dev)
1887{
1888 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1889 unsigned int num_serial = dev->subsystem_device & 0xf;
1890
1891 /*
1892 * These Netmos parts are multiport serial devices with optional
1893 * parallel ports. Even when parallel ports are present, they
1894 * are identified as class SERIAL, which means the serial driver
1895 * will claim them. To prevent this, mark them as class OTHER.
1896 * These combo devices should be claimed by parport_serial.
1897 *
1898 * The subdevice ID is of the form 0x00PS, where <P> is the number
1899 * of parallel ports and <S> is the number of serial ports.
1900 */
1901 switch (dev->device) {
1902 case PCI_DEVICE_ID_NETMOS_9835:
1903 /* Well, this rule doesn't hold for the following 9835 device */
1904 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1905 dev->subsystem_device == 0x0299)
1906 return;
1907 case PCI_DEVICE_ID_NETMOS_9735:
1908 case PCI_DEVICE_ID_NETMOS_9745:
1909 case PCI_DEVICE_ID_NETMOS_9845:
1910 case PCI_DEVICE_ID_NETMOS_9855:
1911 if (num_parallel) {
1912 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1913 dev->device, num_parallel, num_serial);
1914 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1915 (dev->class & 0xff);
1916 }
1917 }
1918}
1919DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1920 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1921
1922/*
1923 * Quirk non-zero PCI functions to route VPD access through function 0 for
1924 * devices that share VPD resources between functions. The functions are
1925 * expected to be identical devices.
1926 */
1927static void quirk_f0_vpd_link(struct pci_dev *dev)
1928{
1929 struct pci_dev *f0;
1930
1931 if (!PCI_FUNC(dev->devfn))
1932 return;
1933
1934 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1935 if (!f0)
1936 return;
1937
1938 if (f0->vpd && dev->class == f0->class &&
1939 dev->vendor == f0->vendor && dev->device == f0->device)
1940 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1941
1942 pci_dev_put(f0);
1943}
1944DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1945 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1946
1947static void quirk_e100_interrupt(struct pci_dev *dev)
1948{
1949 u16 command, pmcsr;
1950 u8 __iomem *csr;
1951 u8 cmd_hi;
1952
1953 switch (dev->device) {
1954 /* PCI IDs taken from drivers/net/e100.c */
1955 case 0x1029:
1956 case 0x1030 ... 0x1034:
1957 case 0x1038 ... 0x103E:
1958 case 0x1050 ... 0x1057:
1959 case 0x1059:
1960 case 0x1064 ... 0x106B:
1961 case 0x1091 ... 0x1095:
1962 case 0x1209:
1963 case 0x1229:
1964 case 0x2449:
1965 case 0x2459:
1966 case 0x245D:
1967 case 0x27DC:
1968 break;
1969 default:
1970 return;
1971 }
1972
1973 /*
1974 * Some firmware hands off the e100 with interrupts enabled,
1975 * which can cause a flood of interrupts if packets are
1976 * received before the driver attaches to the device. So
1977 * disable all e100 interrupts here. The driver will
1978 * re-enable them when it's ready.
1979 */
1980 pci_read_config_word(dev, PCI_COMMAND, &command);
1981
1982 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1983 return;
1984
1985 /*
1986 * Check that the device is in the D0 power state. If it's not,
1987 * there is no point to look any further.
1988 */
1989 if (dev->pm_cap) {
1990 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1991 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1992 return;
1993 }
1994
1995 /* Convert from PCI bus to resource space. */
1996 csr = ioremap(pci_resource_start(dev, 0), 8);
1997 if (!csr) {
1998 dev_warn(&dev->dev, "Can't map e100 registers\n");
1999 return;
2000 }
2001
2002 cmd_hi = readb(csr + 3);
2003 if (cmd_hi == 0) {
2004 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2005 writeb(1, csr + 3);
2006 }
2007
2008 iounmap(csr);
2009}
2010DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2011 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2012
2013/*
2014 * The 82575 and 82598 may experience data corruption issues when transitioning
2015 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2016 */
2017static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2018{
2019 dev_info(&dev->dev, "Disabling L0s\n");
2020 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2021}
2022DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2023DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2024DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2025DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2026DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2027DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2028DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2029DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2030DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2033DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2036
2037static void fixup_rev1_53c810(struct pci_dev *dev)
2038{
2039 u32 class = dev->class;
2040
2041 /*
2042 * rev 1 ncr53c810 chips don't set the class at all which means
2043 * they don't get their resources remapped. Fix that here.
2044 */
2045 if (class)
2046 return;
2047
2048 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2049 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2050 class, dev->class);
2051}
2052DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2053
2054/* Enable 1k I/O space granularity on the Intel P64H2 */
2055static void quirk_p64h2_1k_io(struct pci_dev *dev)
2056{
2057 u16 en1k;
2058
2059 pci_read_config_word(dev, 0x40, &en1k);
2060
2061 if (en1k & 0x200) {
2062 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2063 dev->io_window_1k = 1;
2064 }
2065}
2066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2067
2068/* Under some circumstances, AER is not linked with extended capabilities.
2069 * Force it to be linked by setting the corresponding control bit in the
2070 * config space.
2071 */
2072static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2073{
2074 uint8_t b;
2075 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2076 if (!(b & 0x20)) {
2077 pci_write_config_byte(dev, 0xf41, b | 0x20);
2078 dev_info(&dev->dev, "Linking AER extended capability\n");
2079 }
2080 }
2081}
2082DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2083 quirk_nvidia_ck804_pcie_aer_ext_cap);
2084DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2085 quirk_nvidia_ck804_pcie_aer_ext_cap);
2086
2087static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2088{
2089 /*
2090 * Disable PCI Bus Parking and PCI Master read caching on CX700
2091 * which causes unspecified timing errors with a VT6212L on the PCI
2092 * bus leading to USB2.0 packet loss.
2093 *
2094 * This quirk is only enabled if a second (on the external PCI bus)
2095 * VT6212L is found -- the CX700 core itself also contains a USB
2096 * host controller with the same PCI ID as the VT6212L.
2097 */
2098
2099 /* Count VT6212L instances */
2100 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2101 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2102 uint8_t b;
2103
2104 /* p should contain the first (internal) VT6212L -- see if we have
2105 an external one by searching again */
2106 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2107 if (!p)
2108 return;
2109 pci_dev_put(p);
2110
2111 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2112 if (b & 0x40) {
2113 /* Turn off PCI Bus Parking */
2114 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2115
2116 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2117 }
2118 }
2119
2120 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2121 if (b != 0) {
2122 /* Turn off PCI Master read caching */
2123 pci_write_config_byte(dev, 0x72, 0x0);
2124
2125 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2126 pci_write_config_byte(dev, 0x75, 0x1);
2127
2128 /* Disable "Read FIFO Timer" */
2129 pci_write_config_byte(dev, 0x77, 0x0);
2130
2131 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2132 }
2133 }
2134}
2135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2136
2137/*
2138 * If a device follows the VPD format spec, the PCI core will not read or
2139 * write past the VPD End Tag. But some vendors do not follow the VPD
2140 * format spec, so we can't tell how much data is safe to access. Devices
2141 * may behave unpredictably if we access too much. Blacklist these devices
2142 * so we don't touch VPD at all.
2143 */
2144static void quirk_blacklist_vpd(struct pci_dev *dev)
2145{
2146 if (dev->vpd) {
2147 dev->vpd->len = 0;
2148 dev_warn(&dev->dev, FW_BUG "VPD access disabled\n");
2149 }
2150}
2151
2152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2154DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2155DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2164 quirk_blacklist_vpd);
2165
2166/*
2167 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2168 * VPD end tag will hang the device. This problem was initially
2169 * observed when a vpd entry was created in sysfs
2170 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2171 * will dump 32k of data. Reading a full 32k will cause an access
2172 * beyond the VPD end tag causing the device to hang. Once the device
2173 * is hung, the bnx2 driver will not be able to reset the device.
2174 * We believe that it is legal to read beyond the end tag and
2175 * therefore the solution is to limit the read/write length.
2176 */
2177static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2178{
2179 /*
2180 * Only disable the VPD capability for 5706, 5706S, 5708,
2181 * 5708S and 5709 rev. A
2182 */
2183 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2184 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2185 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2186 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2187 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2188 (dev->revision & 0xf0) == 0x0)) {
2189 if (dev->vpd)
2190 dev->vpd->len = 0x80;
2191 }
2192}
2193
2194DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2195 PCI_DEVICE_ID_NX2_5706,
2196 quirk_brcm_570x_limit_vpd);
2197DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2198 PCI_DEVICE_ID_NX2_5706S,
2199 quirk_brcm_570x_limit_vpd);
2200DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2201 PCI_DEVICE_ID_NX2_5708,
2202 quirk_brcm_570x_limit_vpd);
2203DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2204 PCI_DEVICE_ID_NX2_5708S,
2205 quirk_brcm_570x_limit_vpd);
2206DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2207 PCI_DEVICE_ID_NX2_5709,
2208 quirk_brcm_570x_limit_vpd);
2209DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2210 PCI_DEVICE_ID_NX2_5709S,
2211 quirk_brcm_570x_limit_vpd);
2212
2213static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2214{
2215 u32 rev;
2216
2217 pci_read_config_dword(dev, 0xf4, &rev);
2218
2219 /* Only CAP the MRRS if the device is a 5719 A0 */
2220 if (rev == 0x05719000) {
2221 int readrq = pcie_get_readrq(dev);
2222 if (readrq > 2048)
2223 pcie_set_readrq(dev, 2048);
2224 }
2225}
2226
2227DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2228 PCI_DEVICE_ID_TIGON3_5719,
2229 quirk_brcm_5719_limit_mrrs);
2230
2231/* Originally in EDAC sources for i82875P:
2232 * Intel tells BIOS developers to hide device 6 which
2233 * configures the overflow device access containing
2234 * the DRBs - this is where we expose device 6.
2235 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2236 */
2237static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2238{
2239 u8 reg;
2240
2241 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2242 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2243 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2244 }
2245}
2246
2247DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2248 quirk_unhide_mch_dev6);
2249DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2250 quirk_unhide_mch_dev6);
2251
2252#ifdef CONFIG_TILEPRO
2253/*
2254 * The Tilera TILEmpower tilepro platform needs to set the link speed
2255 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2256 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2257 * capability register of the PEX8624 PCIe switch. The switch
2258 * supports link speed auto negotiation, but falsely sets
2259 * the link speed to 5GT/s.
2260 */
2261static void quirk_tile_plx_gen1(struct pci_dev *dev)
2262{
2263 if (tile_plx_gen1) {
2264 pci_write_config_dword(dev, 0x98, 0x1);
2265 mdelay(50);
2266 }
2267}
2268DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2269#endif /* CONFIG_TILEPRO */
2270
2271#ifdef CONFIG_PCI_MSI
2272/* Some chipsets do not support MSI. We cannot easily rely on setting
2273 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2274 * some other buses controlled by the chipset even if Linux is not
2275 * aware of it. Instead of setting the flag on all buses in the
2276 * machine, simply disable MSI globally.
2277 */
2278static void quirk_disable_all_msi(struct pci_dev *dev)
2279{
2280 pci_no_msi();
2281 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2282}
2283DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2284DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2285DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2286DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2287DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2288DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2289DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2290DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2291
2292/* Disable MSI on chipsets that are known to not support it */
2293static void quirk_disable_msi(struct pci_dev *dev)
2294{
2295 if (dev->subordinate) {
2296 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2297 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2298 }
2299}
2300DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2301DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2302DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2303
2304/*
2305 * The APC bridge device in AMD 780 family northbridges has some random
2306 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2307 * we use the possible vendor/device IDs of the host bridge for the
2308 * declared quirk, and search for the APC bridge by slot number.
2309 */
2310static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2311{
2312 struct pci_dev *apc_bridge;
2313
2314 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2315 if (apc_bridge) {
2316 if (apc_bridge->device == 0x9602)
2317 quirk_disable_msi(apc_bridge);
2318 pci_dev_put(apc_bridge);
2319 }
2320}
2321DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2323
2324/* Go through the list of Hypertransport capabilities and
2325 * return 1 if a HT MSI capability is found and enabled */
2326static int msi_ht_cap_enabled(struct pci_dev *dev)
2327{
2328 int pos, ttl = PCI_FIND_CAP_TTL;
2329
2330 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2331 while (pos && ttl--) {
2332 u8 flags;
2333
2334 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2335 &flags) == 0) {
2336 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2337 flags & HT_MSI_FLAGS_ENABLE ?
2338 "enabled" : "disabled");
2339 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2340 }
2341
2342 pos = pci_find_next_ht_capability(dev, pos,
2343 HT_CAPTYPE_MSI_MAPPING);
2344 }
2345 return 0;
2346}
2347
2348/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2349static void quirk_msi_ht_cap(struct pci_dev *dev)
2350{
2351 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2352 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2353 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2354 }
2355}
2356DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2357 quirk_msi_ht_cap);
2358
2359/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2360 * MSI are supported if the MSI capability set in any of these mappings.
2361 */
2362static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2363{
2364 struct pci_dev *pdev;
2365
2366 if (!dev->subordinate)
2367 return;
2368
2369 /* check HT MSI cap on this chipset and the root one.
2370 * a single one having MSI is enough to be sure that MSI are supported.
2371 */
2372 pdev = pci_get_slot(dev->bus, 0);
2373 if (!pdev)
2374 return;
2375 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2376 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2377 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2378 }
2379 pci_dev_put(pdev);
2380}
2381DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2382 quirk_nvidia_ck804_msi_ht_cap);
2383
2384/* Force enable MSI mapping capability on HT bridges */
2385static void ht_enable_msi_mapping(struct pci_dev *dev)
2386{
2387 int pos, ttl = PCI_FIND_CAP_TTL;
2388
2389 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2390 while (pos && ttl--) {
2391 u8 flags;
2392
2393 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2394 &flags) == 0) {
2395 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2396
2397 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2398 flags | HT_MSI_FLAGS_ENABLE);
2399 }
2400 pos = pci_find_next_ht_capability(dev, pos,
2401 HT_CAPTYPE_MSI_MAPPING);
2402 }
2403}
2404DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2405 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2406 ht_enable_msi_mapping);
2407
2408DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2409 ht_enable_msi_mapping);
2410
2411/* The P5N32-SLI motherboards from Asus have a problem with msi
2412 * for the MCP55 NIC. It is not yet determined whether the msi problem
2413 * also affects other devices. As for now, turn off msi for this device.
2414 */
2415static void nvenet_msi_disable(struct pci_dev *dev)
2416{
2417 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2418
2419 if (board_name &&
2420 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2421 strstr(board_name, "P5N32-E SLI"))) {
2422 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2423 dev->no_msi = 1;
2424 }
2425}
2426DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2427 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2428 nvenet_msi_disable);
2429
2430/*
2431 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2432 * config register. This register controls the routing of legacy
2433 * interrupts from devices that route through the MCP55. If this register
2434 * is misprogrammed, interrupts are only sent to the BSP, unlike
2435 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2436 * having this register set properly prevents kdump from booting up
2437 * properly, so let's make sure that we have it set correctly.
2438 * Note that this is an undocumented register.
2439 */
2440static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2441{
2442 u32 cfg;
2443
2444 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2445 return;
2446
2447 pci_read_config_dword(dev, 0x74, &cfg);
2448
2449 if (cfg & ((1 << 2) | (1 << 15))) {
2450 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2451 cfg &= ~((1 << 2) | (1 << 15));
2452 pci_write_config_dword(dev, 0x74, cfg);
2453 }
2454}
2455
2456DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2457 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2458 nvbridge_check_legacy_irq_routing);
2459
2460DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2461 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2462 nvbridge_check_legacy_irq_routing);
2463
2464static int ht_check_msi_mapping(struct pci_dev *dev)
2465{
2466 int pos, ttl = PCI_FIND_CAP_TTL;
2467 int found = 0;
2468
2469 /* check if there is HT MSI cap or enabled on this device */
2470 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2471 while (pos && ttl--) {
2472 u8 flags;
2473
2474 if (found < 1)
2475 found = 1;
2476 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2477 &flags) == 0) {
2478 if (flags & HT_MSI_FLAGS_ENABLE) {
2479 if (found < 2) {
2480 found = 2;
2481 break;
2482 }
2483 }
2484 }
2485 pos = pci_find_next_ht_capability(dev, pos,
2486 HT_CAPTYPE_MSI_MAPPING);
2487 }
2488
2489 return found;
2490}
2491
2492static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2493{
2494 struct pci_dev *dev;
2495 int pos;
2496 int i, dev_no;
2497 int found = 0;
2498
2499 dev_no = host_bridge->devfn >> 3;
2500 for (i = dev_no + 1; i < 0x20; i++) {
2501 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2502 if (!dev)
2503 continue;
2504
2505 /* found next host bridge ?*/
2506 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2507 if (pos != 0) {
2508 pci_dev_put(dev);
2509 break;
2510 }
2511
2512 if (ht_check_msi_mapping(dev)) {
2513 found = 1;
2514 pci_dev_put(dev);
2515 break;
2516 }
2517 pci_dev_put(dev);
2518 }
2519
2520 return found;
2521}
2522
2523#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2524#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2525
2526static int is_end_of_ht_chain(struct pci_dev *dev)
2527{
2528 int pos, ctrl_off;
2529 int end = 0;
2530 u16 flags, ctrl;
2531
2532 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2533
2534 if (!pos)
2535 goto out;
2536
2537 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2538
2539 ctrl_off = ((flags >> 10) & 1) ?
2540 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2541 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2542
2543 if (ctrl & (1 << 6))
2544 end = 1;
2545
2546out:
2547 return end;
2548}
2549
2550static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2551{
2552 struct pci_dev *host_bridge;
2553 int pos;
2554 int i, dev_no;
2555 int found = 0;
2556
2557 dev_no = dev->devfn >> 3;
2558 for (i = dev_no; i >= 0; i--) {
2559 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2560 if (!host_bridge)
2561 continue;
2562
2563 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2564 if (pos != 0) {
2565 found = 1;
2566 break;
2567 }
2568 pci_dev_put(host_bridge);
2569 }
2570
2571 if (!found)
2572 return;
2573
2574 /* don't enable end_device/host_bridge with leaf directly here */
2575 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2576 host_bridge_with_leaf(host_bridge))
2577 goto out;
2578
2579 /* root did that ! */
2580 if (msi_ht_cap_enabled(host_bridge))
2581 goto out;
2582
2583 ht_enable_msi_mapping(dev);
2584
2585out:
2586 pci_dev_put(host_bridge);
2587}
2588
2589static void ht_disable_msi_mapping(struct pci_dev *dev)
2590{
2591 int pos, ttl = PCI_FIND_CAP_TTL;
2592
2593 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2594 while (pos && ttl--) {
2595 u8 flags;
2596
2597 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2598 &flags) == 0) {
2599 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2600
2601 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2602 flags & ~HT_MSI_FLAGS_ENABLE);
2603 }
2604 pos = pci_find_next_ht_capability(dev, pos,
2605 HT_CAPTYPE_MSI_MAPPING);
2606 }
2607}
2608
2609static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2610{
2611 struct pci_dev *host_bridge;
2612 int pos;
2613 int found;
2614
2615 if (!pci_msi_enabled())
2616 return;
2617
2618 /* check if there is HT MSI cap or enabled on this device */
2619 found = ht_check_msi_mapping(dev);
2620
2621 /* no HT MSI CAP */
2622 if (found == 0)
2623 return;
2624
2625 /*
2626 * HT MSI mapping should be disabled on devices that are below
2627 * a non-Hypertransport host bridge. Locate the host bridge...
2628 */
2629 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2630 if (host_bridge == NULL) {
2631 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2632 return;
2633 }
2634
2635 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2636 if (pos != 0) {
2637 /* Host bridge is to HT */
2638 if (found == 1) {
2639 /* it is not enabled, try to enable it */
2640 if (all)
2641 ht_enable_msi_mapping(dev);
2642 else
2643 nv_ht_enable_msi_mapping(dev);
2644 }
2645 goto out;
2646 }
2647
2648 /* HT MSI is not enabled */
2649 if (found == 1)
2650 goto out;
2651
2652 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2653 ht_disable_msi_mapping(dev);
2654
2655out:
2656 pci_dev_put(host_bridge);
2657}
2658
2659static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2660{
2661 return __nv_msi_ht_cap_quirk(dev, 1);
2662}
2663
2664static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2665{
2666 return __nv_msi_ht_cap_quirk(dev, 0);
2667}
2668
2669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2670DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2671
2672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2673DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2674
2675static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2676{
2677 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2678}
2679static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2680{
2681 struct pci_dev *p;
2682
2683 /* SB700 MSI issue will be fixed at HW level from revision A21,
2684 * we need check PCI REVISION ID of SMBus controller to get SB700
2685 * revision.
2686 */
2687 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2688 NULL);
2689 if (!p)
2690 return;
2691
2692 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2693 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2694 pci_dev_put(p);
2695}
2696static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2697{
2698 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2699 if (dev->revision < 0x18) {
2700 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2701 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2702 }
2703}
2704DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2705 PCI_DEVICE_ID_TIGON3_5780,
2706 quirk_msi_intx_disable_bug);
2707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2708 PCI_DEVICE_ID_TIGON3_5780S,
2709 quirk_msi_intx_disable_bug);
2710DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2711 PCI_DEVICE_ID_TIGON3_5714,
2712 quirk_msi_intx_disable_bug);
2713DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2714 PCI_DEVICE_ID_TIGON3_5714S,
2715 quirk_msi_intx_disable_bug);
2716DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2717 PCI_DEVICE_ID_TIGON3_5715,
2718 quirk_msi_intx_disable_bug);
2719DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2720 PCI_DEVICE_ID_TIGON3_5715S,
2721 quirk_msi_intx_disable_bug);
2722
2723DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2724 quirk_msi_intx_disable_ati_bug);
2725DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2726 quirk_msi_intx_disable_ati_bug);
2727DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2728 quirk_msi_intx_disable_ati_bug);
2729DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2730 quirk_msi_intx_disable_ati_bug);
2731DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2732 quirk_msi_intx_disable_ati_bug);
2733
2734DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2735 quirk_msi_intx_disable_bug);
2736DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2737 quirk_msi_intx_disable_bug);
2738DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2739 quirk_msi_intx_disable_bug);
2740
2741DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2742 quirk_msi_intx_disable_bug);
2743DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2744 quirk_msi_intx_disable_bug);
2745DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2746 quirk_msi_intx_disable_bug);
2747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2748 quirk_msi_intx_disable_bug);
2749DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2750 quirk_msi_intx_disable_bug);
2751DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2752 quirk_msi_intx_disable_bug);
2753DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2754 quirk_msi_intx_disable_qca_bug);
2755DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2756 quirk_msi_intx_disable_qca_bug);
2757DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2758 quirk_msi_intx_disable_qca_bug);
2759DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2760 quirk_msi_intx_disable_qca_bug);
2761DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2762 quirk_msi_intx_disable_qca_bug);
2763#endif /* CONFIG_PCI_MSI */
2764
2765/* Allow manual resource allocation for PCI hotplug bridges
2766 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2767 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2768 * kernel fails to allocate resources when hotplug device is
2769 * inserted and PCI bus is rescanned.
2770 */
2771static void quirk_hotplug_bridge(struct pci_dev *dev)
2772{
2773 dev->is_hotplug_bridge = 1;
2774}
2775
2776DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2777
2778/*
2779 * This is a quirk for the Ricoh MMC controller found as a part of
2780 * some mulifunction chips.
2781
2782 * This is very similar and based on the ricoh_mmc driver written by
2783 * Philip Langdale. Thank you for these magic sequences.
2784 *
2785 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2786 * and one or both of cardbus or firewire.
2787 *
2788 * It happens that they implement SD and MMC
2789 * support as separate controllers (and PCI functions). The linux SDHCI
2790 * driver supports MMC cards but the chip detects MMC cards in hardware
2791 * and directs them to the MMC controller - so the SDHCI driver never sees
2792 * them.
2793 *
2794 * To get around this, we must disable the useless MMC controller.
2795 * At that point, the SDHCI controller will start seeing them
2796 * It seems to be the case that the relevant PCI registers to deactivate the
2797 * MMC controller live on PCI function 0, which might be the cardbus controller
2798 * or the firewire controller, depending on the particular chip in question
2799 *
2800 * This has to be done early, because as soon as we disable the MMC controller
2801 * other pci functions shift up one level, e.g. function #2 becomes function
2802 * #1, and this will confuse the pci core.
2803 */
2804
2805#ifdef CONFIG_MMC_RICOH_MMC
2806static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2807{
2808 /* disable via cardbus interface */
2809 u8 write_enable;
2810 u8 write_target;
2811 u8 disable;
2812
2813 /* disable must be done via function #0 */
2814 if (PCI_FUNC(dev->devfn))
2815 return;
2816
2817 pci_read_config_byte(dev, 0xB7, &disable);
2818 if (disable & 0x02)
2819 return;
2820
2821 pci_read_config_byte(dev, 0x8E, &write_enable);
2822 pci_write_config_byte(dev, 0x8E, 0xAA);
2823 pci_read_config_byte(dev, 0x8D, &write_target);
2824 pci_write_config_byte(dev, 0x8D, 0xB7);
2825 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2826 pci_write_config_byte(dev, 0x8E, write_enable);
2827 pci_write_config_byte(dev, 0x8D, write_target);
2828
2829 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2830 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2831}
2832DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2833DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2834
2835static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2836{
2837 /* disable via firewire interface */
2838 u8 write_enable;
2839 u8 disable;
2840
2841 /* disable must be done via function #0 */
2842 if (PCI_FUNC(dev->devfn))
2843 return;
2844 /*
2845 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2846 * certain types of SD/MMC cards. Lowering the SD base
2847 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2848 *
2849 * 0x150 - SD2.0 mode enable for changing base clock
2850 * frequency to 50Mhz
2851 * 0xe1 - Base clock frequency
2852 * 0x32 - 50Mhz new clock frequency
2853 * 0xf9 - Key register for 0x150
2854 * 0xfc - key register for 0xe1
2855 */
2856 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2857 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2858 pci_write_config_byte(dev, 0xf9, 0xfc);
2859 pci_write_config_byte(dev, 0x150, 0x10);
2860 pci_write_config_byte(dev, 0xf9, 0x00);
2861 pci_write_config_byte(dev, 0xfc, 0x01);
2862 pci_write_config_byte(dev, 0xe1, 0x32);
2863 pci_write_config_byte(dev, 0xfc, 0x00);
2864
2865 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2866 }
2867
2868 pci_read_config_byte(dev, 0xCB, &disable);
2869
2870 if (disable & 0x02)
2871 return;
2872
2873 pci_read_config_byte(dev, 0xCA, &write_enable);
2874 pci_write_config_byte(dev, 0xCA, 0x57);
2875 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2876 pci_write_config_byte(dev, 0xCA, write_enable);
2877
2878 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2879 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2880
2881}
2882DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2883DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2884DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2885DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2886DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2887DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2888#endif /*CONFIG_MMC_RICOH_MMC*/
2889
2890#ifdef CONFIG_DMAR_TABLE
2891#define VTUNCERRMSK_REG 0x1ac
2892#define VTD_MSK_SPEC_ERRORS (1 << 31)
2893/*
2894 * This is a quirk for masking vt-d spec defined errors to platform error
2895 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2896 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2897 * on the RAS config settings of the platform) when a vt-d fault happens.
2898 * The resulting SMI caused the system to hang.
2899 *
2900 * VT-d spec related errors are already handled by the VT-d OS code, so no
2901 * need to report the same error through other channels.
2902 */
2903static void vtd_mask_spec_errors(struct pci_dev *dev)
2904{
2905 u32 word;
2906
2907 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2908 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2909}
2910DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2911DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2912#endif
2913
2914static void fixup_ti816x_class(struct pci_dev *dev)
2915{
2916 u32 class = dev->class;
2917
2918 /* TI 816x devices do not have class code set when in PCIe boot mode */
2919 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2920 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2921 class, dev->class);
2922}
2923DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2924 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2925
2926/* Some PCIe devices do not work reliably with the claimed maximum
2927 * payload size supported.
2928 */
2929static void fixup_mpss_256(struct pci_dev *dev)
2930{
2931 dev->pcie_mpss = 1; /* 256 bytes */
2932}
2933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2934 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2936 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2937DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2938 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2939
2940/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2941 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2942 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2943 * until all of the devices are discovered and buses walked, read completion
2944 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2945 * it is possible to hotplug a device with MPS of 256B.
2946 */
2947static void quirk_intel_mc_errata(struct pci_dev *dev)
2948{
2949 int err;
2950 u16 rcc;
2951
2952 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2953 pcie_bus_config == PCIE_BUS_DEFAULT)
2954 return;
2955
2956 /* Intel errata specifies bits to change but does not say what they are.
2957 * Keeping them magical until such time as the registers and values can
2958 * be explained.
2959 */
2960 err = pci_read_config_word(dev, 0x48, &rcc);
2961 if (err) {
2962 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
2963 return;
2964 }
2965
2966 if (!(rcc & (1 << 10)))
2967 return;
2968
2969 rcc &= ~(1 << 10);
2970
2971 err = pci_write_config_word(dev, 0x48, rcc);
2972 if (err) {
2973 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
2974 return;
2975 }
2976
2977 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
2978}
2979/* Intel 5000 series memory controllers and ports 2-7 */
2980DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2981DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2983DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2984DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2985DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2986DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2987DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2988DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2989DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2990DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2991DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2992DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2993DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2994/* Intel 5100 series memory controllers and ports 2-7 */
2995DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2996DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2997DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2998DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2999DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3000DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3001DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3002DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3003DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3004DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3005DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3006
3007
3008/*
3009 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3010 * work around this, query the size it should be configured to by the device and
3011 * modify the resource end to correspond to this new size.
3012 */
3013static void quirk_intel_ntb(struct pci_dev *dev)
3014{
3015 int rc;
3016 u8 val;
3017
3018 rc = pci_read_config_byte(dev, 0x00D0, &val);
3019 if (rc)
3020 return;
3021
3022 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3023
3024 rc = pci_read_config_byte(dev, 0x00D1, &val);
3025 if (rc)
3026 return;
3027
3028 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3029}
3030DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3031DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3032
3033static ktime_t fixup_debug_start(struct pci_dev *dev,
3034 void (*fn)(struct pci_dev *dev))
3035{
3036 ktime_t calltime = ktime_set(0, 0);
3037
3038 dev_dbg(&dev->dev, "calling %pF\n", fn);
3039 if (initcall_debug) {
3040 pr_debug("calling %pF @ %i for %s\n",
3041 fn, task_pid_nr(current), dev_name(&dev->dev));
3042 calltime = ktime_get();
3043 }
3044
3045 return calltime;
3046}
3047
3048static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3049 void (*fn)(struct pci_dev *dev))
3050{
3051 ktime_t delta, rettime;
3052 unsigned long long duration;
3053
3054 if (initcall_debug) {
3055 rettime = ktime_get();
3056 delta = ktime_sub(rettime, calltime);
3057 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3058 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3059 fn, duration, dev_name(&dev->dev));
3060 }
3061}
3062
3063/*
3064 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3065 * even though no one is handling them (f.e. i915 driver is never loaded).
3066 * Additionally the interrupt destination is not set up properly
3067 * and the interrupt ends up -somewhere-.
3068 *
3069 * These spurious interrupts are "sticky" and the kernel disables
3070 * the (shared) interrupt line after 100.000+ generated interrupts.
3071 *
3072 * Fix it by disabling the still enabled interrupts.
3073 * This resolves crashes often seen on monitor unplug.
3074 */
3075#define I915_DEIER_REG 0x4400c
3076static void disable_igfx_irq(struct pci_dev *dev)
3077{
3078 void __iomem *regs = pci_iomap(dev, 0, 0);
3079 if (regs == NULL) {
3080 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3081 return;
3082 }
3083
3084 /* Check if any interrupt line is still enabled */
3085 if (readl(regs + I915_DEIER_REG) != 0) {
3086 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3087
3088 writel(0, regs + I915_DEIER_REG);
3089 }
3090
3091 pci_iounmap(dev, regs);
3092}
3093DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3095DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3096
3097/*
3098 * PCI devices which are on Intel chips can skip the 10ms delay
3099 * before entering D3 mode.
3100 */
3101static void quirk_remove_d3_delay(struct pci_dev *dev)
3102{
3103 dev->d3_delay = 0;
3104}
3105DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3106DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3107DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3108DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3109DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3111DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3113DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3114DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3115DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3117DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3118DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3119/* Intel Cherrytrail devices do not need 10ms d3_delay */
3120DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3121DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3122DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3123DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3129/*
3130 * Some devices may pass our check in pci_intx_mask_supported if
3131 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3132 * support this feature.
3133 */
3134static void quirk_broken_intx_masking(struct pci_dev *dev)
3135{
3136 dev->broken_intx_masking = 1;
3137}
3138DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
3139 quirk_broken_intx_masking);
3140DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3141 quirk_broken_intx_masking);
3142/*
3143 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3144 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3145 *
3146 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3147 */
3148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169,
3149 quirk_broken_intx_masking);
3150DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3151 quirk_broken_intx_masking);
3152
3153static void quirk_no_bus_reset(struct pci_dev *dev)
3154{
3155 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3156}
3157
3158/*
3159 * Atheros AR93xx chips do not behave after a bus reset. The device will
3160 * throw a Link Down error on AER-capable systems and regardless of AER,
3161 * config space of the device is never accessible again and typically
3162 * causes the system to hang or reset when access is attempted.
3163 * http://www.spinics.net/lists/linux-pci/msg34797.html
3164 */
3165DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3166
3167static void quirk_no_pm_reset(struct pci_dev *dev)
3168{
3169 /*
3170 * We can't do a bus reset on root bus devices, but an ineffective
3171 * PM reset may be better than nothing.
3172 */
3173 if (!pci_is_root_bus(dev->bus))
3174 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3175}
3176
3177/*
3178 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3179 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3180 * to have no effect on the device: it retains the framebuffer contents and
3181 * monitor sync. Advertising this support makes other layers, like VFIO,
3182 * assume pci_reset_function() is viable for this device. Mark it as
3183 * unavailable to skip it when testing reset methods.
3184 */
3185DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3186 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3187
3188#ifdef CONFIG_ACPI
3189/*
3190 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3191 *
3192 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3193 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3194 * be present after resume if a device was plugged in before suspend.
3195 *
3196 * The thunderbolt controller consists of a pcie switch with downstream
3197 * bridges leading to the NHI and to the tunnel pci bridges.
3198 *
3199 * This quirk cuts power to the whole chip. Therefore we have to apply it
3200 * during suspend_noirq of the upstream bridge.
3201 *
3202 * Power is automagically restored before resume. No action is needed.
3203 */
3204static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3205{
3206 acpi_handle bridge, SXIO, SXFP, SXLV;
3207
3208 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3209 return;
3210 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3211 return;
3212 bridge = ACPI_HANDLE(&dev->dev);
3213 if (!bridge)
3214 return;
3215 /*
3216 * SXIO and SXLV are present only on machines requiring this quirk.
3217 * TB bridges in external devices might have the same device id as those
3218 * on the host, but they will not have the associated ACPI methods. This
3219 * implicitly checks that we are at the right bridge.
3220 */
3221 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3222 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3223 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3224 return;
3225 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3226
3227 /* magic sequence */
3228 acpi_execute_simple_method(SXIO, NULL, 1);
3229 acpi_execute_simple_method(SXFP, NULL, 0);
3230 msleep(300);
3231 acpi_execute_simple_method(SXLV, NULL, 0);
3232 acpi_execute_simple_method(SXIO, NULL, 0);
3233 acpi_execute_simple_method(SXLV, NULL, 0);
3234}
3235DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 0x1547,
3236 quirk_apple_poweroff_thunderbolt);
3237
3238/*
3239 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3240 *
3241 * During suspend the thunderbolt controller is reset and all pci
3242 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3243 * during resume. We have to manually wait for the NHI since there is
3244 * no parent child relationship between the NHI and the tunneled
3245 * bridges.
3246 */
3247static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3248{
3249 struct pci_dev *sibling = NULL;
3250 struct pci_dev *nhi = NULL;
3251
3252 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3253 return;
3254 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3255 return;
3256 /*
3257 * Find the NHI and confirm that we are a bridge on the tb host
3258 * controller and not on a tb endpoint.
3259 */
3260 sibling = pci_get_slot(dev->bus, 0x0);
3261 if (sibling == dev)
3262 goto out; /* we are the downstream bridge to the NHI */
3263 if (!sibling || !sibling->subordinate)
3264 goto out;
3265 nhi = pci_get_slot(sibling->subordinate, 0x0);
3266 if (!nhi)
3267 goto out;
3268 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3269 || (nhi->device != 0x1547 && nhi->device != 0x156c)
3270 || nhi->subsystem_vendor != 0x2222
3271 || nhi->subsystem_device != 0x1111)
3272 goto out;
3273 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3274 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3275out:
3276 pci_dev_put(nhi);
3277 pci_dev_put(sibling);
3278}
3279DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x1547,
3280 quirk_apple_wait_for_thunderbolt);
3281DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, 0x156d,
3282 quirk_apple_wait_for_thunderbolt);
3283#endif
3284
3285static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3286 struct pci_fixup *end)
3287{
3288 ktime_t calltime;
3289
3290 for (; f < end; f++)
3291 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3292 f->class == (u32) PCI_ANY_ID) &&
3293 (f->vendor == dev->vendor ||
3294 f->vendor == (u16) PCI_ANY_ID) &&
3295 (f->device == dev->device ||
3296 f->device == (u16) PCI_ANY_ID)) {
3297 calltime = fixup_debug_start(dev, f->hook);
3298 f->hook(dev);
3299 fixup_debug_report(dev, calltime, f->hook);
3300 }
3301}
3302
3303extern struct pci_fixup __start_pci_fixups_early[];
3304extern struct pci_fixup __end_pci_fixups_early[];
3305extern struct pci_fixup __start_pci_fixups_header[];
3306extern struct pci_fixup __end_pci_fixups_header[];
3307extern struct pci_fixup __start_pci_fixups_final[];
3308extern struct pci_fixup __end_pci_fixups_final[];
3309extern struct pci_fixup __start_pci_fixups_enable[];
3310extern struct pci_fixup __end_pci_fixups_enable[];
3311extern struct pci_fixup __start_pci_fixups_resume[];
3312extern struct pci_fixup __end_pci_fixups_resume[];
3313extern struct pci_fixup __start_pci_fixups_resume_early[];
3314extern struct pci_fixup __end_pci_fixups_resume_early[];
3315extern struct pci_fixup __start_pci_fixups_suspend[];
3316extern struct pci_fixup __end_pci_fixups_suspend[];
3317extern struct pci_fixup __start_pci_fixups_suspend_late[];
3318extern struct pci_fixup __end_pci_fixups_suspend_late[];
3319
3320static bool pci_apply_fixup_final_quirks;
3321
3322void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3323{
3324 struct pci_fixup *start, *end;
3325
3326 switch (pass) {
3327 case pci_fixup_early:
3328 start = __start_pci_fixups_early;
3329 end = __end_pci_fixups_early;
3330 break;
3331
3332 case pci_fixup_header:
3333 start = __start_pci_fixups_header;
3334 end = __end_pci_fixups_header;
3335 break;
3336
3337 case pci_fixup_final:
3338 if (!pci_apply_fixup_final_quirks)
3339 return;
3340 start = __start_pci_fixups_final;
3341 end = __end_pci_fixups_final;
3342 break;
3343
3344 case pci_fixup_enable:
3345 start = __start_pci_fixups_enable;
3346 end = __end_pci_fixups_enable;
3347 break;
3348
3349 case pci_fixup_resume:
3350 start = __start_pci_fixups_resume;
3351 end = __end_pci_fixups_resume;
3352 break;
3353
3354 case pci_fixup_resume_early:
3355 start = __start_pci_fixups_resume_early;
3356 end = __end_pci_fixups_resume_early;
3357 break;
3358
3359 case pci_fixup_suspend:
3360 start = __start_pci_fixups_suspend;
3361 end = __end_pci_fixups_suspend;
3362 break;
3363
3364 case pci_fixup_suspend_late:
3365 start = __start_pci_fixups_suspend_late;
3366 end = __end_pci_fixups_suspend_late;
3367 break;
3368
3369 default:
3370 /* stupid compiler warning, you would think with an enum... */
3371 return;
3372 }
3373 pci_do_fixups(dev, start, end);
3374}
3375EXPORT_SYMBOL(pci_fixup_device);
3376
3377
3378static int __init pci_apply_final_quirks(void)
3379{
3380 struct pci_dev *dev = NULL;
3381 u8 cls = 0;
3382 u8 tmp;
3383
3384 if (pci_cache_line_size)
3385 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3386 pci_cache_line_size << 2);
3387
3388 pci_apply_fixup_final_quirks = true;
3389 for_each_pci_dev(dev) {
3390 pci_fixup_device(pci_fixup_final, dev);
3391 /*
3392 * If arch hasn't set it explicitly yet, use the CLS
3393 * value shared by all PCI devices. If there's a
3394 * mismatch, fall back to the default value.
3395 */
3396 if (!pci_cache_line_size) {
3397 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3398 if (!cls)
3399 cls = tmp;
3400 if (!tmp || cls == tmp)
3401 continue;
3402
3403 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3404 cls << 2, tmp << 2,
3405 pci_dfl_cache_line_size << 2);
3406 pci_cache_line_size = pci_dfl_cache_line_size;
3407 }
3408 }
3409
3410 if (!pci_cache_line_size) {
3411 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3412 cls << 2, pci_dfl_cache_line_size << 2);
3413 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3414 }
3415
3416 return 0;
3417}
3418
3419fs_initcall_sync(pci_apply_final_quirks);
3420
3421/*
3422 * Followings are device-specific reset methods which can be used to
3423 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3424 * not available.
3425 */
3426static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3427{
3428 /*
3429 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3430 *
3431 * The 82599 supports FLR on VFs, but FLR support is reported only
3432 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3433 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3434 */
3435
3436 if (probe)
3437 return 0;
3438
3439 if (!pci_wait_for_pending_transaction(dev))
3440 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3441
3442 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3443
3444 msleep(100);
3445
3446 return 0;
3447}
3448
3449#define SOUTH_CHICKEN2 0xc2004
3450#define PCH_PP_STATUS 0xc7200
3451#define PCH_PP_CONTROL 0xc7204
3452#define MSG_CTL 0x45010
3453#define NSDE_PWR_STATE 0xd0100
3454#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3455
3456static int reset_ivb_igd(struct pci_dev *dev, int probe)
3457{
3458 void __iomem *mmio_base;
3459 unsigned long timeout;
3460 u32 val;
3461
3462 if (probe)
3463 return 0;
3464
3465 mmio_base = pci_iomap(dev, 0, 0);
3466 if (!mmio_base)
3467 return -ENOMEM;
3468
3469 iowrite32(0x00000002, mmio_base + MSG_CTL);
3470
3471 /*
3472 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3473 * driver loaded sets the right bits. However, this's a reset and
3474 * the bits have been set by i915 previously, so we clobber
3475 * SOUTH_CHICKEN2 register directly here.
3476 */
3477 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3478
3479 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3480 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3481
3482 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3483 do {
3484 val = ioread32(mmio_base + PCH_PP_STATUS);
3485 if ((val & 0xb0000000) == 0)
3486 goto reset_complete;
3487 msleep(10);
3488 } while (time_before(jiffies, timeout));
3489 dev_warn(&dev->dev, "timeout during reset\n");
3490
3491reset_complete:
3492 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3493
3494 pci_iounmap(dev, mmio_base);
3495 return 0;
3496}
3497
3498/*
3499 * Device-specific reset method for Chelsio T4-based adapters.
3500 */
3501static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3502{
3503 u16 old_command;
3504 u16 msix_flags;
3505
3506 /*
3507 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3508 * that we have no device-specific reset method.
3509 */
3510 if ((dev->device & 0xf000) != 0x4000)
3511 return -ENOTTY;
3512
3513 /*
3514 * If this is the "probe" phase, return 0 indicating that we can
3515 * reset this device.
3516 */
3517 if (probe)
3518 return 0;
3519
3520 /*
3521 * T4 can wedge if there are DMAs in flight within the chip and Bus
3522 * Master has been disabled. We need to have it on till the Function
3523 * Level Reset completes. (BUS_MASTER is disabled in
3524 * pci_reset_function()).
3525 */
3526 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3527 pci_write_config_word(dev, PCI_COMMAND,
3528 old_command | PCI_COMMAND_MASTER);
3529
3530 /*
3531 * Perform the actual device function reset, saving and restoring
3532 * configuration information around the reset.
3533 */
3534 pci_save_state(dev);
3535
3536 /*
3537 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3538 * are disabled when an MSI-X interrupt message needs to be delivered.
3539 * So we briefly re-enable MSI-X interrupts for the duration of the
3540 * FLR. The pci_restore_state() below will restore the original
3541 * MSI-X state.
3542 */
3543 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3544 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3545 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3546 msix_flags |
3547 PCI_MSIX_FLAGS_ENABLE |
3548 PCI_MSIX_FLAGS_MASKALL);
3549
3550 /*
3551 * Start of pcie_flr() code sequence. This reset code is a copy of
3552 * the guts of pcie_flr() because that's not an exported function.
3553 */
3554
3555 if (!pci_wait_for_pending_transaction(dev))
3556 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3557
3558 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3559 msleep(100);
3560
3561 /*
3562 * End of pcie_flr() code sequence.
3563 */
3564
3565 /*
3566 * Restore the configuration information (BAR values, etc.) including
3567 * the original PCI Configuration Space Command word, and return
3568 * success.
3569 */
3570 pci_restore_state(dev);
3571 pci_write_config_word(dev, PCI_COMMAND, old_command);
3572 return 0;
3573}
3574
3575#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3576#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3577#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3578
3579static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3580 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3581 reset_intel_82599_sfp_virtfn },
3582 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3583 reset_ivb_igd },
3584 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3585 reset_ivb_igd },
3586 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3587 reset_chelsio_generic_dev },
3588 { 0 }
3589};
3590
3591/*
3592 * These device-specific reset methods are here rather than in a driver
3593 * because when a host assigns a device to a guest VM, the host may need
3594 * to reset the device but probably doesn't have a driver for it.
3595 */
3596int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3597{
3598 const struct pci_dev_reset_methods *i;
3599
3600 for (i = pci_dev_reset_methods; i->reset; i++) {
3601 if ((i->vendor == dev->vendor ||
3602 i->vendor == (u16)PCI_ANY_ID) &&
3603 (i->device == dev->device ||
3604 i->device == (u16)PCI_ANY_ID))
3605 return i->reset(dev, probe);
3606 }
3607
3608 return -ENOTTY;
3609}
3610
3611static void quirk_dma_func0_alias(struct pci_dev *dev)
3612{
3613 if (PCI_FUNC(dev->devfn) != 0) {
3614 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
3615 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3616 }
3617}
3618
3619/*
3620 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3621 *
3622 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3623 */
3624DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3625DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3626
3627static void quirk_dma_func1_alias(struct pci_dev *dev)
3628{
3629 if (PCI_FUNC(dev->devfn) != 1) {
3630 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1);
3631 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3632 }
3633}
3634
3635/*
3636 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3637 * SKUs function 1 is present and is a legacy IDE controller, in other
3638 * SKUs this function is not present, making this a ghost requester.
3639 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3640 */
3641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3642 quirk_dma_func1_alias);
3643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3644 quirk_dma_func1_alias);
3645/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3646DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3647 quirk_dma_func1_alias);
3648/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3649DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3650 quirk_dma_func1_alias);
3651/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3652DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3653 quirk_dma_func1_alias);
3654/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3655DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3656 quirk_dma_func1_alias);
3657/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3659 quirk_dma_func1_alias);
3660DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3661 quirk_dma_func1_alias);
3662/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3664 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3665 quirk_dma_func1_alias);
3666/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3667DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3668 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3669 quirk_dma_func1_alias);
3670
3671/*
3672 * Some devices DMA with the wrong devfn, not just the wrong function.
3673 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3674 * the alias is "fixed" and independent of the device devfn.
3675 *
3676 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3677 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3678 * single device on the secondary bus. In reality, the single exposed
3679 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3680 * that provides a bridge to the internal bus of the I/O processor. The
3681 * controller supports private devices, which can be hidden from PCI config
3682 * space. In the case of the Adaptec 3405, a private device at 01.0
3683 * appears to be the DMA engine, which therefore needs to become a DMA
3684 * alias for the device.
3685 */
3686static const struct pci_device_id fixed_dma_alias_tbl[] = {
3687 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3688 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3689 .driver_data = PCI_DEVFN(1, 0) },
3690 { 0 }
3691};
3692
3693static void quirk_fixed_dma_alias(struct pci_dev *dev)
3694{
3695 const struct pci_device_id *id;
3696
3697 id = pci_match_id(fixed_dma_alias_tbl, dev);
3698 if (id) {
3699 dev->dma_alias_devfn = id->driver_data;
3700 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3701 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
3702 PCI_SLOT(dev->dma_alias_devfn),
3703 PCI_FUNC(dev->dma_alias_devfn));
3704 }
3705}
3706
3707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3708
3709/*
3710 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3711 * using the wrong DMA alias for the device. Some of these devices can be
3712 * used as either forward or reverse bridges, so we need to test whether the
3713 * device is operating in the correct mode. We could probably apply this
3714 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3715 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3716 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3717 */
3718static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3719{
3720 if (!pci_is_root_bus(pdev->bus) &&
3721 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3722 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3723 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3724 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3725}
3726/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3727DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3728 quirk_use_pcie_bridge_dma_alias);
3729/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3730DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3731/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3732DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3733/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3734DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3735
3736/*
3737 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3738 * class code. Fix it.
3739 */
3740static void quirk_tw686x_class(struct pci_dev *pdev)
3741{
3742 u32 class = pdev->class;
3743
3744 /* Use "Multimedia controller" class */
3745 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3746 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3747 class, pdev->class);
3748}
3749DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
3750 quirk_tw686x_class);
3751DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
3752 quirk_tw686x_class);
3753DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
3754 quirk_tw686x_class);
3755DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3756 quirk_tw686x_class);
3757
3758/*
3759 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
3760 * values for the Attribute as were supplied in the header of the
3761 * corresponding Request, except as explicitly allowed when IDO is used."
3762 *
3763 * If a non-compliant device generates a completion with a different
3764 * attribute than the request, the receiver may accept it (which itself
3765 * seems non-compliant based on sec 2.3.2), or it may handle it as a
3766 * Malformed TLP or an Unexpected Completion, which will probably lead to a
3767 * device access timeout.
3768 *
3769 * If the non-compliant device generates completions with zero attributes
3770 * (instead of copying the attributes from the request), we can work around
3771 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
3772 * upstream devices so they always generate requests with zero attributes.
3773 *
3774 * This affects other devices under the same Root Port, but since these
3775 * attributes are performance hints, there should be no functional problem.
3776 *
3777 * Note that Configuration Space accesses are never supposed to have TLP
3778 * Attributes, so we're safe waiting till after any Configuration Space
3779 * accesses to do the Root Port fixup.
3780 */
3781static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
3782{
3783 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
3784
3785 if (!root_port) {
3786 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
3787 return;
3788 }
3789
3790 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
3791 dev_name(&pdev->dev));
3792 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
3793 PCI_EXP_DEVCTL_RELAX_EN |
3794 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
3795}
3796
3797/*
3798 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
3799 * Completion it generates.
3800 */
3801static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
3802{
3803 /*
3804 * This mask/compare operation selects for Physical Function 4 on a
3805 * T5. We only need to fix up the Root Port once for any of the
3806 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
3807 * 0x54xx so we use that one,
3808 */
3809 if ((pdev->device & 0xff00) == 0x5400)
3810 quirk_disable_root_port_attributes(pdev);
3811}
3812DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3813 quirk_chelsio_T5_disable_root_port_attributes);
3814
3815/*
3816 * AMD has indicated that the devices below do not support peer-to-peer
3817 * in any system where they are found in the southbridge with an AMD
3818 * IOMMU in the system. Multifunction devices that do not support
3819 * peer-to-peer between functions can claim to support a subset of ACS.
3820 * Such devices effectively enable request redirect (RR) and completion
3821 * redirect (CR) since all transactions are redirected to the upstream
3822 * root complex.
3823 *
3824 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3825 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3826 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3827 *
3828 * 1002:4385 SBx00 SMBus Controller
3829 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3830 * 1002:4383 SBx00 Azalia (Intel HDA)
3831 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3832 * 1002:4384 SBx00 PCI to PCI Bridge
3833 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3834 *
3835 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
3836 *
3837 * 1022:780f [AMD] FCH PCI Bridge
3838 * 1022:7809 [AMD] FCH USB OHCI Controller
3839 */
3840static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3841{
3842#ifdef CONFIG_ACPI
3843 struct acpi_table_header *header = NULL;
3844 acpi_status status;
3845
3846 /* Targeting multifunction devices on the SB (appears on root bus) */
3847 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3848 return -ENODEV;
3849
3850 /* The IVRS table describes the AMD IOMMU */
3851 status = acpi_get_table("IVRS", 0, &header);
3852 if (ACPI_FAILURE(status))
3853 return -ENODEV;
3854
3855 /* Filter out flags not applicable to multifunction */
3856 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3857
3858 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3859#else
3860 return -ENODEV;
3861#endif
3862}
3863
3864static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
3865{
3866 /*
3867 * Cavium devices matching this quirk do not perform peer-to-peer
3868 * with other functions, allowing masking out these bits as if they
3869 * were unimplemented in the ACS capability.
3870 */
3871 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
3872 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
3873
3874 return acs_flags ? 0 : 1;
3875}
3876
3877/*
3878 * Many Intel PCH root ports do provide ACS-like features to disable peer
3879 * transactions and validate bus numbers in requests, but do not provide an
3880 * actual PCIe ACS capability. This is the list of device IDs known to fall
3881 * into that category as provided by Intel in Red Hat bugzilla 1037684.
3882 */
3883static const u16 pci_quirk_intel_pch_acs_ids[] = {
3884 /* Ibexpeak PCH */
3885 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
3886 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
3887 /* Cougarpoint PCH */
3888 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
3889 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
3890 /* Pantherpoint PCH */
3891 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
3892 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
3893 /* Lynxpoint-H PCH */
3894 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
3895 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
3896 /* Lynxpoint-LP PCH */
3897 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
3898 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
3899 /* Wildcat PCH */
3900 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3901 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
3902 /* Patsburg (X79) PCH */
3903 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
3904 /* Wellsburg (X99) PCH */
3905 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
3906 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
3907 /* Lynx Point (9 series) PCH */
3908 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
3909};
3910
3911static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
3912{
3913 int i;
3914
3915 /* Filter out a few obvious non-matches first */
3916 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
3917 return false;
3918
3919 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
3920 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
3921 return true;
3922
3923 return false;
3924}
3925
3926#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
3927
3928static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
3929{
3930 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
3931 INTEL_PCH_ACS_FLAGS : 0;
3932
3933 if (!pci_quirk_intel_pch_acs_match(dev))
3934 return -ENOTTY;
3935
3936 return acs_flags & ~flags ? 0 : 1;
3937}
3938
3939static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
3940{
3941 /*
3942 * SV, TB, and UF are not relevant to multifunction endpoints.
3943 *
3944 * Multifunction devices are only required to implement RR, CR, and DT
3945 * in their ACS capability if they support peer-to-peer transactions.
3946 * Devices matching this quirk have been verified by the vendor to not
3947 * perform peer-to-peer with other functions, allowing us to mask out
3948 * these bits as if they were unimplemented in the ACS capability.
3949 */
3950 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
3951 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
3952
3953 return acs_flags ? 0 : 1;
3954}
3955
3956static const struct pci_dev_acs_enabled {
3957 u16 vendor;
3958 u16 device;
3959 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3960} pci_dev_acs_enabled[] = {
3961 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3962 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3963 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3964 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3965 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3966 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
3967 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
3968 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
3969 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
3970 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
3971 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
3972 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
3973 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
3974 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
3975 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
3976 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
3977 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
3978 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
3979 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
3980 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
3981 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
3982 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
3983 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
3984 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
3985 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
3986 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
3987 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
3988 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
3989 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
3990 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
3991 /* 82580 */
3992 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
3993 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
3994 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
3995 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
3996 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
3997 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
3998 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
3999 /* 82576 */
4000 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4001 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4002 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4003 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4004 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4005 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4006 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4007 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4008 /* 82575 */
4009 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4010 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4011 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4012 /* I350 */
4013 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4014 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4015 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4016 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4017 /* 82571 (Quads omitted due to non-ACS switch) */
4018 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4019 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4020 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4021 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4022 /* I219 */
4023 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4024 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4025 /* Intel PCH root ports */
4026 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4027 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4028 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4029 /* Cavium ThunderX */
4030 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4031 { 0 }
4032};
4033
4034int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4035{
4036 const struct pci_dev_acs_enabled *i;
4037 int ret;
4038
4039 /*
4040 * Allow devices that do not expose standard PCIe ACS capabilities
4041 * or control to indicate their support here. Multi-function express
4042 * devices which do not allow internal peer-to-peer between functions,
4043 * but do not implement PCIe ACS may wish to return true here.
4044 */
4045 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4046 if ((i->vendor == dev->vendor ||
4047 i->vendor == (u16)PCI_ANY_ID) &&
4048 (i->device == dev->device ||
4049 i->device == (u16)PCI_ANY_ID)) {
4050 ret = i->acs_enabled(dev, acs_flags);
4051 if (ret >= 0)
4052 return ret;
4053 }
4054 }
4055
4056 return -ENOTTY;
4057}
4058
4059/* Config space offset of Root Complex Base Address register */
4060#define INTEL_LPC_RCBA_REG 0xf0
4061/* 31:14 RCBA address */
4062#define INTEL_LPC_RCBA_MASK 0xffffc000
4063/* RCBA Enable */
4064#define INTEL_LPC_RCBA_ENABLE (1 << 0)
4065
4066/* Backbone Scratch Pad Register */
4067#define INTEL_BSPR_REG 0x1104
4068/* Backbone Peer Non-Posted Disable */
4069#define INTEL_BSPR_REG_BPNPD (1 << 8)
4070/* Backbone Peer Posted Disable */
4071#define INTEL_BSPR_REG_BPPD (1 << 9)
4072
4073/* Upstream Peer Decode Configuration Register */
4074#define INTEL_UPDCR_REG 0x1114
4075/* 5:0 Peer Decode Enable bits */
4076#define INTEL_UPDCR_REG_MASK 0x3f
4077
4078static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4079{
4080 u32 rcba, bspr, updcr;
4081 void __iomem *rcba_mem;
4082
4083 /*
4084 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4085 * are D28:F* and therefore get probed before LPC, thus we can't
4086 * use pci_get_slot/pci_read_config_dword here.
4087 */
4088 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4089 INTEL_LPC_RCBA_REG, &rcba);
4090 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4091 return -EINVAL;
4092
4093 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4094 PAGE_ALIGN(INTEL_UPDCR_REG));
4095 if (!rcba_mem)
4096 return -ENOMEM;
4097
4098 /*
4099 * The BSPR can disallow peer cycles, but it's set by soft strap and
4100 * therefore read-only. If both posted and non-posted peer cycles are
4101 * disallowed, we're ok. If either are allowed, then we need to use
4102 * the UPDCR to disable peer decodes for each port. This provides the
4103 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4104 */
4105 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4106 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4107 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4108 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4109 if (updcr & INTEL_UPDCR_REG_MASK) {
4110 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4111 updcr &= ~INTEL_UPDCR_REG_MASK;
4112 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4113 }
4114 }
4115
4116 iounmap(rcba_mem);
4117 return 0;
4118}
4119
4120/* Miscellaneous Port Configuration register */
4121#define INTEL_MPC_REG 0xd8
4122/* MPC: Invalid Receive Bus Number Check Enable */
4123#define INTEL_MPC_REG_IRBNCE (1 << 26)
4124
4125static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4126{
4127 u32 mpc;
4128
4129 /*
4130 * When enabled, the IRBNCE bit of the MPC register enables the
4131 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4132 * ensures that requester IDs fall within the bus number range
4133 * of the bridge. Enable if not already.
4134 */
4135 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4136 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4137 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4138 mpc |= INTEL_MPC_REG_IRBNCE;
4139 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4140 }
4141}
4142
4143static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4144{
4145 if (!pci_quirk_intel_pch_acs_match(dev))
4146 return -ENOTTY;
4147
4148 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4149 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4150 return 0;
4151 }
4152
4153 pci_quirk_enable_intel_rp_mpc_acs(dev);
4154
4155 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4156
4157 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4158
4159 return 0;
4160}
4161
4162static const struct pci_dev_enable_acs {
4163 u16 vendor;
4164 u16 device;
4165 int (*enable_acs)(struct pci_dev *dev);
4166} pci_dev_enable_acs[] = {
4167 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4168 { 0 }
4169};
4170
4171void pci_dev_specific_enable_acs(struct pci_dev *dev)
4172{
4173 const struct pci_dev_enable_acs *i;
4174 int ret;
4175
4176 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4177 if ((i->vendor == dev->vendor ||
4178 i->vendor == (u16)PCI_ANY_ID) &&
4179 (i->device == dev->device ||
4180 i->device == (u16)PCI_ANY_ID)) {
4181 ret = i->enable_acs(dev);
4182 if (ret >= 0)
4183 return;
4184 }
4185 }
4186}
4187
4188/*
4189 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4190 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4191 * Next Capability pointer in the MSI Capability Structure should point to
4192 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4193 * the list.
4194 */
4195static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4196{
4197 int pos, i = 0;
4198 u8 next_cap;
4199 u16 reg16, *cap;
4200 struct pci_cap_saved_state *state;
4201
4202 /* Bail if the hardware bug is fixed */
4203 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4204 return;
4205
4206 /* Bail if MSI Capability Structure is not found for some reason */
4207 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4208 if (!pos)
4209 return;
4210
4211 /*
4212 * Bail if Next Capability pointer in the MSI Capability Structure
4213 * is not the expected incorrect 0x00.
4214 */
4215 pci_read_config_byte(pdev, pos + 1, &next_cap);
4216 if (next_cap)
4217 return;
4218
4219 /*
4220 * PCIe Capability Structure is expected to be at 0x50 and should
4221 * terminate the list (Next Capability pointer is 0x00). Verify
4222 * Capability Id and Next Capability pointer is as expected.
4223 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4224 * to correctly set kernel data structures which have already been
4225 * set incorrectly due to the hardware bug.
4226 */
4227 pos = 0x50;
4228 pci_read_config_word(pdev, pos, ®16);
4229 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4230 u32 status;
4231#ifndef PCI_EXP_SAVE_REGS
4232#define PCI_EXP_SAVE_REGS 7
4233#endif
4234 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4235
4236 pdev->pcie_cap = pos;
4237 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
4238 pdev->pcie_flags_reg = reg16;
4239 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
4240 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4241
4242 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4243 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4244 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4245 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4246
4247 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4248 return;
4249
4250 /*
4251 * Save PCIE cap
4252 */
4253 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4254 if (!state)
4255 return;
4256
4257 state->cap.cap_nr = PCI_CAP_ID_EXP;
4258 state->cap.cap_extended = 0;
4259 state->cap.size = size;
4260 cap = (u16 *)&state->cap.data[0];
4261 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4262 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4263 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4264 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4265 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4266 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4267 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4268 hlist_add_head(&state->next, &pdev->saved_cap_space);
4269 }
4270}
4271DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);