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1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/acpi.h>
24#include <linux/kallsyms.h>
25#include <linux/dmi.h>
26#include <linux/pci-aspm.h>
27#include <linux/ioport.h>
28#include <asm/dma.h> /* isa_dma_bridge_buggy */
29#include "pci.h"
30
31/*
32 * This quirk function disables memory decoding and releases memory resources
33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
34 * It also rounds up size to specified alignment.
35 * Later on, the kernel will assign page-aligned memory resource back
36 * to the device.
37 */
38static void __devinit quirk_resource_alignment(struct pci_dev *dev)
39{
40 int i;
41 struct resource *r;
42 resource_size_t align, size;
43 u16 command;
44
45 if (!pci_is_reassigndev(dev))
46 return;
47
48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
50 dev_warn(&dev->dev,
51 "Can't reassign resources to host bridge.\n");
52 return;
53 }
54
55 dev_info(&dev->dev,
56 "Disabling memory decoding and releasing memory resources.\n");
57 pci_read_config_word(dev, PCI_COMMAND, &command);
58 command &= ~PCI_COMMAND_MEMORY;
59 pci_write_config_word(dev, PCI_COMMAND, command);
60
61 align = pci_specified_resource_alignment(dev);
62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
63 r = &dev->resource[i];
64 if (!(r->flags & IORESOURCE_MEM))
65 continue;
66 size = resource_size(r);
67 if (size < align) {
68 size = align;
69 dev_info(&dev->dev,
70 "Rounding up size of resource #%d to %#llx.\n",
71 i, (unsigned long long)size);
72 }
73 r->end = size - 1;
74 r->start = 0;
75 }
76 /* Need to disable bridge's resource window,
77 * to enable the kernel to reassign new resource
78 * window later on.
79 */
80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
83 r = &dev->resource[i];
84 if (!(r->flags & IORESOURCE_MEM))
85 continue;
86 r->end = resource_size(r) - 1;
87 r->start = 0;
88 }
89 pci_disable_bridge_window(dev);
90 }
91}
92DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
93
94/*
95 * Decoding should be disabled for a PCI device during BAR sizing to avoid
96 * conflict. But doing so may cause problems on host bridge and perhaps other
97 * key system devices. For devices that need to have mmio decoding always-on,
98 * we need to set the dev->mmio_always_on bit.
99 */
100static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
101{
102 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
103 dev->mmio_always_on = 1;
104}
105DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on);
106
107/* The Mellanox Tavor device gives false positive parity errors
108 * Mark this device with a broken_parity_status, to allow
109 * PCI scanning code to "skip" this now blacklisted device.
110 */
111static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
112{
113 dev->broken_parity_status = 1; /* This device gives false positives */
114}
115DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
117
118/* Deal with broken BIOS'es that neglect to enable passive release,
119 which can cause problems in combination with the 82441FX/PPro MTRRs */
120static void quirk_passive_release(struct pci_dev *dev)
121{
122 struct pci_dev *d = NULL;
123 unsigned char dlc;
124
125 /* We have to make sure a particular bit is set in the PIIX3
126 ISA bridge, so we have to go out and find it. */
127 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
128 pci_read_config_byte(d, 0x82, &dlc);
129 if (!(dlc & 1<<1)) {
130 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
131 dlc |= 1<<1;
132 pci_write_config_byte(d, 0x82, dlc);
133 }
134 }
135}
136DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
137DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
138
139/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
140 but VIA don't answer queries. If you happen to have good contacts at VIA
141 ask them for me please -- Alan
142
143 This appears to be BIOS not version dependent. So presumably there is a
144 chipset level fix */
145
146static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
147{
148 if (!isa_dma_bridge_buggy) {
149 isa_dma_bridge_buggy=1;
150 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
151 }
152}
153 /*
154 * Its not totally clear which chipsets are the problematic ones
155 * We know 82C586 and 82C596 variants are affected.
156 */
157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
164
165/*
166 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
167 * for some HT machines to use C4 w/o hanging.
168 */
169static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
170{
171 u32 pmbase;
172 u16 pm1a;
173
174 pci_read_config_dword(dev, 0x40, &pmbase);
175 pmbase = pmbase & 0xff80;
176 pm1a = inw(pmbase);
177
178 if (pm1a & 0x10) {
179 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
180 outw(0x10, pmbase);
181 }
182}
183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
184
185/*
186 * Chipsets where PCI->PCI transfers vanish or hang
187 */
188static void __devinit quirk_nopcipci(struct pci_dev *dev)
189{
190 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
191 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
192 pci_pci_problems |= PCIPCI_FAIL;
193 }
194}
195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
197
198static void __devinit quirk_nopciamd(struct pci_dev *dev)
199{
200 u8 rev;
201 pci_read_config_byte(dev, 0x08, &rev);
202 if (rev == 0x13) {
203 /* Erratum 24 */
204 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
205 pci_pci_problems |= PCIAGP_FAIL;
206 }
207}
208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
209
210/*
211 * Triton requires workarounds to be used by the drivers
212 */
213static void __devinit quirk_triton(struct pci_dev *dev)
214{
215 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
216 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
217 pci_pci_problems |= PCIPCI_TRITON;
218 }
219}
220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
224
225/*
226 * VIA Apollo KT133 needs PCI latency patch
227 * Made according to a windows driver based patch by George E. Breese
228 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
229 * and http://www.georgebreese.com/net/software/#PCI
230 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
231 * the info on which Mr Breese based his work.
232 *
233 * Updated based on further information from the site and also on
234 * information provided by VIA
235 */
236static void quirk_vialatency(struct pci_dev *dev)
237{
238 struct pci_dev *p;
239 u8 busarb;
240 /* Ok we have a potential problem chipset here. Now see if we have
241 a buggy southbridge */
242
243 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
244 if (p!=NULL) {
245 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
246 /* Check for buggy part revisions */
247 if (p->revision < 0x40 || p->revision > 0x42)
248 goto exit;
249 } else {
250 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
251 if (p==NULL) /* No problem parts */
252 goto exit;
253 /* Check for buggy part revisions */
254 if (p->revision < 0x10 || p->revision > 0x12)
255 goto exit;
256 }
257
258 /*
259 * Ok we have the problem. Now set the PCI master grant to
260 * occur every master grant. The apparent bug is that under high
261 * PCI load (quite common in Linux of course) you can get data
262 * loss when the CPU is held off the bus for 3 bus master requests
263 * This happens to include the IDE controllers....
264 *
265 * VIA only apply this fix when an SB Live! is present but under
266 * both Linux and Windows this isn't enough, and we have seen
267 * corruption without SB Live! but with things like 3 UDMA IDE
268 * controllers. So we ignore that bit of the VIA recommendation..
269 */
270
271 pci_read_config_byte(dev, 0x76, &busarb);
272 /* Set bit 4 and bi 5 of byte 76 to 0x01
273 "Master priority rotation on every PCI master grant */
274 busarb &= ~(1<<5);
275 busarb |= (1<<4);
276 pci_write_config_byte(dev, 0x76, busarb);
277 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
278exit:
279 pci_dev_put(p);
280}
281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
283DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
284/* Must restore this on a resume from RAM */
285DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
286DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
287DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
288
289/*
290 * VIA Apollo VP3 needs ETBF on BT848/878
291 */
292static void __devinit quirk_viaetbf(struct pci_dev *dev)
293{
294 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
295 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
296 pci_pci_problems |= PCIPCI_VIAETBF;
297 }
298}
299DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
300
301static void __devinit quirk_vsfx(struct pci_dev *dev)
302{
303 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
304 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
305 pci_pci_problems |= PCIPCI_VSFX;
306 }
307}
308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
309
310/*
311 * Ali Magik requires workarounds to be used by the drivers
312 * that DMA to AGP space. Latency must be set to 0xA and triton
313 * workaround applied too
314 * [Info kindly provided by ALi]
315 */
316static void __init quirk_alimagik(struct pci_dev *dev)
317{
318 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
319 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
320 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
321 }
322}
323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
325
326/*
327 * Natoma has some interesting boundary conditions with Zoran stuff
328 * at least
329 */
330static void __devinit quirk_natoma(struct pci_dev *dev)
331{
332 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
333 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
334 pci_pci_problems |= PCIPCI_NATOMA;
335 }
336}
337DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
342DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
343
344/*
345 * This chip can cause PCI parity errors if config register 0xA0 is read
346 * while DMAs are occurring.
347 */
348static void __devinit quirk_citrine(struct pci_dev *dev)
349{
350 dev->cfg_size = 0xA0;
351}
352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
353
354/*
355 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
356 * If it's needed, re-allocate the region.
357 */
358static void __devinit quirk_s3_64M(struct pci_dev *dev)
359{
360 struct resource *r = &dev->resource[0];
361
362 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
363 r->start = 0;
364 r->end = 0x3ffffff;
365 }
366}
367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
369
370/*
371 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
372 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
373 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
374 * (which conflicts w/ BAR1's memory range).
375 */
376static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
377{
378 if (pci_resource_len(dev, 0) != 8) {
379 struct resource *res = &dev->resource[0];
380 res->end = res->start + 8 - 1;
381 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
382 "(incorrect header); workaround applied.\n");
383 }
384}
385DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
386
387static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
388 unsigned size, int nr, const char *name)
389{
390 region &= ~(size-1);
391 if (region) {
392 struct pci_bus_region bus_region;
393 struct resource *res = dev->resource + nr;
394
395 res->name = pci_name(dev);
396 res->start = region;
397 res->end = region + size - 1;
398 res->flags = IORESOURCE_IO;
399
400 /* Convert from PCI bus to resource space. */
401 bus_region.start = res->start;
402 bus_region.end = res->end;
403 pcibios_bus_to_resource(dev, res, &bus_region);
404
405 if (pci_claim_resource(dev, nr) == 0)
406 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
407 res, name);
408 }
409}
410
411/*
412 * ATI Northbridge setups MCE the processor if you even
413 * read somewhere between 0x3b0->0x3bb or read 0x3d3
414 */
415static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
416{
417 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
418 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
419 request_region(0x3b0, 0x0C, "RadeonIGP");
420 request_region(0x3d3, 0x01, "RadeonIGP");
421}
422DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
423
424/*
425 * Let's make the southbridge information explicit instead
426 * of having to worry about people probing the ACPI areas,
427 * for example.. (Yes, it happens, and if you read the wrong
428 * ACPI register it will put the machine to sleep with no
429 * way of waking it up again. Bummer).
430 *
431 * ALI M7101: Two IO regions pointed to by words at
432 * 0xE0 (64 bytes of ACPI registers)
433 * 0xE2 (32 bytes of SMB registers)
434 */
435static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
436{
437 u16 region;
438
439 pci_read_config_word(dev, 0xE0, ®ion);
440 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
441 pci_read_config_word(dev, 0xE2, ®ion);
442 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
443}
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
445
446static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
447{
448 u32 devres;
449 u32 mask, size, base;
450
451 pci_read_config_dword(dev, port, &devres);
452 if ((devres & enable) != enable)
453 return;
454 mask = (devres >> 16) & 15;
455 base = devres & 0xffff;
456 size = 16;
457 for (;;) {
458 unsigned bit = size >> 1;
459 if ((bit & mask) == bit)
460 break;
461 size = bit;
462 }
463 /*
464 * For now we only print it out. Eventually we'll want to
465 * reserve it (at least if it's in the 0x1000+ range), but
466 * let's get enough confirmation reports first.
467 */
468 base &= -size;
469 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
470}
471
472static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
473{
474 u32 devres;
475 u32 mask, size, base;
476
477 pci_read_config_dword(dev, port, &devres);
478 if ((devres & enable) != enable)
479 return;
480 base = devres & 0xffff0000;
481 mask = (devres & 0x3f) << 16;
482 size = 128 << 16;
483 for (;;) {
484 unsigned bit = size >> 1;
485 if ((bit & mask) == bit)
486 break;
487 size = bit;
488 }
489 /*
490 * For now we only print it out. Eventually we'll want to
491 * reserve it, but let's get enough confirmation reports first.
492 */
493 base &= -size;
494 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
495}
496
497/*
498 * PIIX4 ACPI: Two IO regions pointed to by longwords at
499 * 0x40 (64 bytes of ACPI registers)
500 * 0x90 (16 bytes of SMB registers)
501 * and a few strange programmable PIIX4 device resources.
502 */
503static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
504{
505 u32 region, res_a;
506
507 pci_read_config_dword(dev, 0x40, ®ion);
508 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
509 pci_read_config_dword(dev, 0x90, ®ion);
510 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
511
512 /* Device resource A has enables for some of the other ones */
513 pci_read_config_dword(dev, 0x5c, &res_a);
514
515 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
516 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
517
518 /* Device resource D is just bitfields for static resources */
519
520 /* Device 12 enabled? */
521 if (res_a & (1 << 29)) {
522 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
523 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
524 }
525 /* Device 13 enabled? */
526 if (res_a & (1 << 30)) {
527 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
528 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
529 }
530 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
531 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
532}
533DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
534DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
535
536#define ICH_PMBASE 0x40
537#define ICH_ACPI_CNTL 0x44
538#define ICH4_ACPI_EN 0x10
539#define ICH6_ACPI_EN 0x80
540#define ICH4_GPIOBASE 0x58
541#define ICH4_GPIO_CNTL 0x5c
542#define ICH4_GPIO_EN 0x10
543#define ICH6_GPIOBASE 0x48
544#define ICH6_GPIO_CNTL 0x4c
545#define ICH6_GPIO_EN 0x10
546
547/*
548 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
549 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
550 * 0x58 (64 bytes of GPIO I/O space)
551 */
552static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
553{
554 u32 region;
555 u8 enable;
556
557 /*
558 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
559 * with low legacy (and fixed) ports. We don't know the decoding
560 * priority and can't tell whether the legacy device or the one created
561 * here is really at that address. This happens on boards with broken
562 * BIOSes.
563 */
564
565 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
566 if (enable & ICH4_ACPI_EN) {
567 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
568 region &= PCI_BASE_ADDRESS_IO_MASK;
569 if (region >= PCIBIOS_MIN_IO)
570 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
571 "ICH4 ACPI/GPIO/TCO");
572 }
573
574 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
575 if (enable & ICH4_GPIO_EN) {
576 pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion);
577 region &= PCI_BASE_ADDRESS_IO_MASK;
578 if (region >= PCIBIOS_MIN_IO)
579 quirk_io_region(dev, region, 64,
580 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
581 }
582}
583DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
584DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
585DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
587DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
588DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
590DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
593
594static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
595{
596 u32 region;
597 u8 enable;
598
599 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
600 if (enable & ICH6_ACPI_EN) {
601 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
602 region &= PCI_BASE_ADDRESS_IO_MASK;
603 if (region >= PCIBIOS_MIN_IO)
604 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
605 "ICH6 ACPI/GPIO/TCO");
606 }
607
608 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
609 if (enable & ICH6_GPIO_EN) {
610 pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion);
611 region &= PCI_BASE_ADDRESS_IO_MASK;
612 if (region >= PCIBIOS_MIN_IO)
613 quirk_io_region(dev, region, 64,
614 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
615 }
616}
617
618static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
619{
620 u32 val;
621 u32 size, base;
622
623 pci_read_config_dword(dev, reg, &val);
624
625 /* Enabled? */
626 if (!(val & 1))
627 return;
628 base = val & 0xfffc;
629 if (dynsize) {
630 /*
631 * This is not correct. It is 16, 32 or 64 bytes depending on
632 * register D31:F0:ADh bits 5:4.
633 *
634 * But this gets us at least _part_ of it.
635 */
636 size = 16;
637 } else {
638 size = 128;
639 }
640 base &= ~(size-1);
641
642 /* Just print it out for now. We should reserve it after more debugging */
643 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
644}
645
646static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
647{
648 /* Shared ACPI/GPIO decode with all ICH6+ */
649 ich6_lpc_acpi_gpio(dev);
650
651 /* ICH6-specific generic IO decode */
652 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
653 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
654}
655DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
657
658static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
659{
660 u32 val;
661 u32 mask, base;
662
663 pci_read_config_dword(dev, reg, &val);
664
665 /* Enabled? */
666 if (!(val & 1))
667 return;
668
669 /*
670 * IO base in bits 15:2, mask in bits 23:18, both
671 * are dword-based
672 */
673 base = val & 0xfffc;
674 mask = (val >> 16) & 0xfc;
675 mask |= 3;
676
677 /* Just print it out for now. We should reserve it after more debugging */
678 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
679}
680
681/* ICH7-10 has the same common LPC generic IO decode registers */
682static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
683{
684 /* We share the common ACPI/GPIO decode with ICH6 */
685 ich6_lpc_acpi_gpio(dev);
686
687 /* And have 4 ICH7+ generic decodes */
688 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
689 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
690 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
691 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
692}
693DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
694DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
706
707/*
708 * VIA ACPI: One IO region pointed to by longword at
709 * 0x48 or 0x20 (256 bytes of ACPI registers)
710 */
711static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
712{
713 u32 region;
714
715 if (dev->revision & 0x10) {
716 pci_read_config_dword(dev, 0x48, ®ion);
717 region &= PCI_BASE_ADDRESS_IO_MASK;
718 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
719 }
720}
721DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
722
723/*
724 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
725 * 0x48 (256 bytes of ACPI registers)
726 * 0x70 (128 bytes of hardware monitoring register)
727 * 0x90 (16 bytes of SMB registers)
728 */
729static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
730{
731 u16 hm;
732 u32 smb;
733
734 quirk_vt82c586_acpi(dev);
735
736 pci_read_config_word(dev, 0x70, &hm);
737 hm &= PCI_BASE_ADDRESS_IO_MASK;
738 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
739
740 pci_read_config_dword(dev, 0x90, &smb);
741 smb &= PCI_BASE_ADDRESS_IO_MASK;
742 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
743}
744DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
745
746/*
747 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
748 * 0x88 (128 bytes of power management registers)
749 * 0xd0 (16 bytes of SMB registers)
750 */
751static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
752{
753 u16 pm, smb;
754
755 pci_read_config_word(dev, 0x88, &pm);
756 pm &= PCI_BASE_ADDRESS_IO_MASK;
757 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
758
759 pci_read_config_word(dev, 0xd0, &smb);
760 smb &= PCI_BASE_ADDRESS_IO_MASK;
761 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
762}
763DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
764
765/*
766 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
767 * Disable fast back-to-back on the secondary bus segment
768 */
769static void __devinit quirk_xio2000a(struct pci_dev *dev)
770{
771 struct pci_dev *pdev;
772 u16 command;
773
774 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
775 "secondary bus fast back-to-back transfers disabled\n");
776 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
777 pci_read_config_word(pdev, PCI_COMMAND, &command);
778 if (command & PCI_COMMAND_FAST_BACK)
779 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
780 }
781}
782DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
783 quirk_xio2000a);
784
785#ifdef CONFIG_X86_IO_APIC
786
787#include <asm/io_apic.h>
788
789/*
790 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
791 * devices to the external APIC.
792 *
793 * TODO: When we have device-specific interrupt routers,
794 * this code will go away from quirks.
795 */
796static void quirk_via_ioapic(struct pci_dev *dev)
797{
798 u8 tmp;
799
800 if (nr_ioapics < 1)
801 tmp = 0; /* nothing routed to external APIC */
802 else
803 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
804
805 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
806 tmp == 0 ? "Disa" : "Ena");
807
808 /* Offset 0x58: External APIC IRQ output control */
809 pci_write_config_byte (dev, 0x58, tmp);
810}
811DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
812DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
813
814/*
815 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
816 * This leads to doubled level interrupt rates.
817 * Set this bit to get rid of cycle wastage.
818 * Otherwise uncritical.
819 */
820static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
821{
822 u8 misc_control2;
823#define BYPASS_APIC_DEASSERT 8
824
825 pci_read_config_byte(dev, 0x5B, &misc_control2);
826 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
827 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
828 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
829 }
830}
831DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
832DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
833
834/*
835 * The AMD io apic can hang the box when an apic irq is masked.
836 * We check all revs >= B0 (yet not in the pre production!) as the bug
837 * is currently marked NoFix
838 *
839 * We have multiple reports of hangs with this chipset that went away with
840 * noapic specified. For the moment we assume it's the erratum. We may be wrong
841 * of course. However the advice is demonstrably good even if so..
842 */
843static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
844{
845 if (dev->revision >= 0x02) {
846 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
847 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
848 }
849}
850DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
851
852static void __init quirk_ioapic_rmw(struct pci_dev *dev)
853{
854 if (dev->devfn == 0 && dev->bus->number == 0)
855 sis_apic_bug = 1;
856}
857DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
858#endif /* CONFIG_X86_IO_APIC */
859
860/*
861 * Some settings of MMRBC can lead to data corruption so block changes.
862 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
863 */
864static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
865{
866 if (dev->subordinate && dev->revision <= 0x12) {
867 dev_info(&dev->dev, "AMD8131 rev %x detected; "
868 "disabling PCI-X MMRBC\n", dev->revision);
869 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
870 }
871}
872DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
873
874/*
875 * FIXME: it is questionable that quirk_via_acpi
876 * is needed. It shows up as an ISA bridge, and does not
877 * support the PCI_INTERRUPT_LINE register at all. Therefore
878 * it seems like setting the pci_dev's 'irq' to the
879 * value of the ACPI SCI interrupt is only done for convenience.
880 * -jgarzik
881 */
882static void __devinit quirk_via_acpi(struct pci_dev *d)
883{
884 /*
885 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
886 */
887 u8 irq;
888 pci_read_config_byte(d, 0x42, &irq);
889 irq &= 0xf;
890 if (irq && (irq != 2))
891 d->irq = irq;
892}
893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
895
896
897/*
898 * VIA bridges which have VLink
899 */
900
901static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
902
903static void quirk_via_bridge(struct pci_dev *dev)
904{
905 /* See what bridge we have and find the device ranges */
906 switch (dev->device) {
907 case PCI_DEVICE_ID_VIA_82C686:
908 /* The VT82C686 is special, it attaches to PCI and can have
909 any device number. All its subdevices are functions of
910 that single device. */
911 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
912 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
913 break;
914 case PCI_DEVICE_ID_VIA_8237:
915 case PCI_DEVICE_ID_VIA_8237A:
916 via_vlink_dev_lo = 15;
917 break;
918 case PCI_DEVICE_ID_VIA_8235:
919 via_vlink_dev_lo = 16;
920 break;
921 case PCI_DEVICE_ID_VIA_8231:
922 case PCI_DEVICE_ID_VIA_8233_0:
923 case PCI_DEVICE_ID_VIA_8233A:
924 case PCI_DEVICE_ID_VIA_8233C_0:
925 via_vlink_dev_lo = 17;
926 break;
927 }
928}
929DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
930DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
931DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
932DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
936DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
937
938/**
939 * quirk_via_vlink - VIA VLink IRQ number update
940 * @dev: PCI device
941 *
942 * If the device we are dealing with is on a PIC IRQ we need to
943 * ensure that the IRQ line register which usually is not relevant
944 * for PCI cards, is actually written so that interrupts get sent
945 * to the right place.
946 * We only do this on systems where a VIA south bridge was detected,
947 * and only for VIA devices on the motherboard (see quirk_via_bridge
948 * above).
949 */
950
951static void quirk_via_vlink(struct pci_dev *dev)
952{
953 u8 irq, new_irq;
954
955 /* Check if we have VLink at all */
956 if (via_vlink_dev_lo == -1)
957 return;
958
959 new_irq = dev->irq;
960
961 /* Don't quirk interrupts outside the legacy IRQ range */
962 if (!new_irq || new_irq > 15)
963 return;
964
965 /* Internal device ? */
966 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
967 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
968 return;
969
970 /* This is an internal VLink device on a PIC interrupt. The BIOS
971 ought to have set this but may not have, so we redo it */
972
973 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
974 if (new_irq != irq) {
975 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
976 irq, new_irq);
977 udelay(15); /* unknown if delay really needed */
978 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
979 }
980}
981DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
982
983/*
984 * VIA VT82C598 has its device ID settable and many BIOSes
985 * set it to the ID of VT82C597 for backward compatibility.
986 * We need to switch it off to be able to recognize the real
987 * type of the chip.
988 */
989static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
990{
991 pci_write_config_byte(dev, 0xfc, 0);
992 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
993}
994DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
995
996/*
997 * CardBus controllers have a legacy base address that enables them
998 * to respond as i82365 pcmcia controllers. We don't want them to
999 * do this even if the Linux CardBus driver is not loaded, because
1000 * the Linux i82365 driver does not (and should not) handle CardBus.
1001 */
1002static void quirk_cardbus_legacy(struct pci_dev *dev)
1003{
1004 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
1005 return;
1006 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1007}
1008DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1009DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1010
1011/*
1012 * Following the PCI ordering rules is optional on the AMD762. I'm not
1013 * sure what the designers were smoking but let's not inhale...
1014 *
1015 * To be fair to AMD, it follows the spec by default, its BIOS people
1016 * who turn it off!
1017 */
1018static void quirk_amd_ordering(struct pci_dev *dev)
1019{
1020 u32 pcic;
1021 pci_read_config_dword(dev, 0x4C, &pcic);
1022 if ((pcic&6)!=6) {
1023 pcic |= 6;
1024 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1025 pci_write_config_dword(dev, 0x4C, pcic);
1026 pci_read_config_dword(dev, 0x84, &pcic);
1027 pcic |= (1<<23); /* Required in this mode */
1028 pci_write_config_dword(dev, 0x84, pcic);
1029 }
1030}
1031DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1032DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1033
1034/*
1035 * DreamWorks provided workaround for Dunord I-3000 problem
1036 *
1037 * This card decodes and responds to addresses not apparently
1038 * assigned to it. We force a larger allocation to ensure that
1039 * nothing gets put too close to it.
1040 */
1041static void __devinit quirk_dunord ( struct pci_dev * dev )
1042{
1043 struct resource *r = &dev->resource [1];
1044 r->start = 0;
1045 r->end = 0xffffff;
1046}
1047DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1048
1049/*
1050 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1051 * is subtractive decoding (transparent), and does indicate this
1052 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1053 * instead of 0x01.
1054 */
1055static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
1056{
1057 dev->transparent = 1;
1058}
1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1060DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1061
1062/*
1063 * Common misconfiguration of the MediaGX/Geode PCI master that will
1064 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1065 * datasheets found at http://www.national.com/analog for info on what
1066 * these bits do. <christer@weinigel.se>
1067 */
1068static void quirk_mediagx_master(struct pci_dev *dev)
1069{
1070 u8 reg;
1071 pci_read_config_byte(dev, 0x41, ®);
1072 if (reg & 2) {
1073 reg &= ~2;
1074 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1075 pci_write_config_byte(dev, 0x41, reg);
1076 }
1077}
1078DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1079DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1080
1081/*
1082 * Ensure C0 rev restreaming is off. This is normally done by
1083 * the BIOS but in the odd case it is not the results are corruption
1084 * hence the presence of a Linux check
1085 */
1086static void quirk_disable_pxb(struct pci_dev *pdev)
1087{
1088 u16 config;
1089
1090 if (pdev->revision != 0x04) /* Only C0 requires this */
1091 return;
1092 pci_read_config_word(pdev, 0x40, &config);
1093 if (config & (1<<6)) {
1094 config &= ~(1<<6);
1095 pci_write_config_word(pdev, 0x40, config);
1096 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1097 }
1098}
1099DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1100DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1101
1102static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1103{
1104 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1105 u8 tmp;
1106
1107 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1108 if (tmp == 0x01) {
1109 pci_read_config_byte(pdev, 0x40, &tmp);
1110 pci_write_config_byte(pdev, 0x40, tmp|1);
1111 pci_write_config_byte(pdev, 0x9, 1);
1112 pci_write_config_byte(pdev, 0xa, 6);
1113 pci_write_config_byte(pdev, 0x40, tmp);
1114
1115 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1116 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1117 }
1118}
1119DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1120DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1121DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1122DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1124DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1125
1126/*
1127 * Serverworks CSB5 IDE does not fully support native mode
1128 */
1129static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1130{
1131 u8 prog;
1132 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1133 if (prog & 5) {
1134 prog &= ~5;
1135 pdev->class &= ~5;
1136 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1137 /* PCI layer will sort out resources */
1138 }
1139}
1140DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1141
1142/*
1143 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1144 */
1145static void __init quirk_ide_samemode(struct pci_dev *pdev)
1146{
1147 u8 prog;
1148
1149 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1150
1151 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1152 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1153 prog &= ~5;
1154 pdev->class &= ~5;
1155 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1156 }
1157}
1158DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1159
1160/*
1161 * Some ATA devices break if put into D3
1162 */
1163
1164static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1165{
1166 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1167 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1168 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1169}
1170DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1171DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1172/* ALi loses some register settings that we cannot then restore */
1173DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1174/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1175 occur when mode detecting */
1176DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
1177
1178/* This was originally an Alpha specific thing, but it really fits here.
1179 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1180 */
1181static void __init quirk_eisa_bridge(struct pci_dev *dev)
1182{
1183 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1184}
1185DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1186
1187
1188/*
1189 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1190 * is not activated. The myth is that Asus said that they do not want the
1191 * users to be irritated by just another PCI Device in the Win98 device
1192 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1193 * package 2.7.0 for details)
1194 *
1195 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1196 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1197 * becomes necessary to do this tweak in two steps -- the chosen trigger
1198 * is either the Host bridge (preferred) or on-board VGA controller.
1199 *
1200 * Note that we used to unhide the SMBus that way on Toshiba laptops
1201 * (Satellite A40 and Tecra M2) but then found that the thermal management
1202 * was done by SMM code, which could cause unsynchronized concurrent
1203 * accesses to the SMBus registers, with potentially bad effects. Thus you
1204 * should be very careful when adding new entries: if SMM is accessing the
1205 * Intel SMBus, this is a very good reason to leave it hidden.
1206 *
1207 * Likewise, many recent laptops use ACPI for thermal management. If the
1208 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1209 * natively, and keeping the SMBus hidden is the right thing to do. If you
1210 * are about to add an entry in the table below, please first disassemble
1211 * the DSDT and double-check that there is no code accessing the SMBus.
1212 */
1213static int asus_hides_smbus;
1214
1215static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1216{
1217 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1218 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1219 switch(dev->subsystem_device) {
1220 case 0x8025: /* P4B-LX */
1221 case 0x8070: /* P4B */
1222 case 0x8088: /* P4B533 */
1223 case 0x1626: /* L3C notebook */
1224 asus_hides_smbus = 1;
1225 }
1226 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1227 switch(dev->subsystem_device) {
1228 case 0x80b1: /* P4GE-V */
1229 case 0x80b2: /* P4PE */
1230 case 0x8093: /* P4B533-V */
1231 asus_hides_smbus = 1;
1232 }
1233 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1234 switch(dev->subsystem_device) {
1235 case 0x8030: /* P4T533 */
1236 asus_hides_smbus = 1;
1237 }
1238 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1239 switch (dev->subsystem_device) {
1240 case 0x8070: /* P4G8X Deluxe */
1241 asus_hides_smbus = 1;
1242 }
1243 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1244 switch (dev->subsystem_device) {
1245 case 0x80c9: /* PU-DLS */
1246 asus_hides_smbus = 1;
1247 }
1248 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1249 switch (dev->subsystem_device) {
1250 case 0x1751: /* M2N notebook */
1251 case 0x1821: /* M5N notebook */
1252 case 0x1897: /* A6L notebook */
1253 asus_hides_smbus = 1;
1254 }
1255 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1256 switch (dev->subsystem_device) {
1257 case 0x184b: /* W1N notebook */
1258 case 0x186a: /* M6Ne notebook */
1259 asus_hides_smbus = 1;
1260 }
1261 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1262 switch (dev->subsystem_device) {
1263 case 0x80f2: /* P4P800-X */
1264 asus_hides_smbus = 1;
1265 }
1266 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1267 switch (dev->subsystem_device) {
1268 case 0x1882: /* M6V notebook */
1269 case 0x1977: /* A6VA notebook */
1270 asus_hides_smbus = 1;
1271 }
1272 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1273 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1274 switch(dev->subsystem_device) {
1275 case 0x088C: /* HP Compaq nc8000 */
1276 case 0x0890: /* HP Compaq nc6000 */
1277 asus_hides_smbus = 1;
1278 }
1279 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1280 switch (dev->subsystem_device) {
1281 case 0x12bc: /* HP D330L */
1282 case 0x12bd: /* HP D530 */
1283 case 0x006a: /* HP Compaq nx9500 */
1284 asus_hides_smbus = 1;
1285 }
1286 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1287 switch (dev->subsystem_device) {
1288 case 0x12bf: /* HP xw4100 */
1289 asus_hides_smbus = 1;
1290 }
1291 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1292 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1293 switch(dev->subsystem_device) {
1294 case 0xC00C: /* Samsung P35 notebook */
1295 asus_hides_smbus = 1;
1296 }
1297 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1298 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1299 switch(dev->subsystem_device) {
1300 case 0x0058: /* Compaq Evo N620c */
1301 asus_hides_smbus = 1;
1302 }
1303 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1304 switch(dev->subsystem_device) {
1305 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1306 /* Motherboard doesn't have Host bridge
1307 * subvendor/subdevice IDs, therefore checking
1308 * its on-board VGA controller */
1309 asus_hides_smbus = 1;
1310 }
1311 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1312 switch(dev->subsystem_device) {
1313 case 0x00b8: /* Compaq Evo D510 CMT */
1314 case 0x00b9: /* Compaq Evo D510 SFF */
1315 case 0x00ba: /* Compaq Evo D510 USDT */
1316 /* Motherboard doesn't have Host bridge
1317 * subvendor/subdevice IDs and on-board VGA
1318 * controller is disabled if an AGP card is
1319 * inserted, therefore checking USB UHCI
1320 * Controller #1 */
1321 asus_hides_smbus = 1;
1322 }
1323 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1324 switch (dev->subsystem_device) {
1325 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1326 /* Motherboard doesn't have host bridge
1327 * subvendor/subdevice IDs, therefore checking
1328 * its on-board VGA controller */
1329 asus_hides_smbus = 1;
1330 }
1331 }
1332}
1333DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1341DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1343
1344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1347
1348static void asus_hides_smbus_lpc(struct pci_dev *dev)
1349{
1350 u16 val;
1351
1352 if (likely(!asus_hides_smbus))
1353 return;
1354
1355 pci_read_config_word(dev, 0xF2, &val);
1356 if (val & 0x8) {
1357 pci_write_config_word(dev, 0xF2, val & (~0x8));
1358 pci_read_config_word(dev, 0xF2, &val);
1359 if (val & 0x8)
1360 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1361 else
1362 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1363 }
1364}
1365DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1369DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1371DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1372DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1373DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1374DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1375DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1376DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1377DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1378DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1379
1380/* It appears we just have one such device. If not, we have a warning */
1381static void __iomem *asus_rcba_base;
1382static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1383{
1384 u32 rcba;
1385
1386 if (likely(!asus_hides_smbus))
1387 return;
1388 WARN_ON(asus_rcba_base);
1389
1390 pci_read_config_dword(dev, 0xF0, &rcba);
1391 /* use bits 31:14, 16 kB aligned */
1392 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1393 if (asus_rcba_base == NULL)
1394 return;
1395}
1396
1397static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1398{
1399 u32 val;
1400
1401 if (likely(!asus_hides_smbus || !asus_rcba_base))
1402 return;
1403 /* read the Function Disable register, dword mode only */
1404 val = readl(asus_rcba_base + 0x3418);
1405 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1406}
1407
1408static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1409{
1410 if (likely(!asus_hides_smbus || !asus_rcba_base))
1411 return;
1412 iounmap(asus_rcba_base);
1413 asus_rcba_base = NULL;
1414 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1415}
1416
1417static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1418{
1419 asus_hides_smbus_lpc_ich6_suspend(dev);
1420 asus_hides_smbus_lpc_ich6_resume_early(dev);
1421 asus_hides_smbus_lpc_ich6_resume(dev);
1422}
1423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1424DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1425DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1426DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1427
1428/*
1429 * SiS 96x south bridge: BIOS typically hides SMBus device...
1430 */
1431static void quirk_sis_96x_smbus(struct pci_dev *dev)
1432{
1433 u8 val = 0;
1434 pci_read_config_byte(dev, 0x77, &val);
1435 if (val & 0x10) {
1436 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1437 pci_write_config_byte(dev, 0x77, val & ~0x10);
1438 }
1439}
1440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1444DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1445DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1446DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1447DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1448
1449/*
1450 * ... This is further complicated by the fact that some SiS96x south
1451 * bridges pretend to be 85C503/5513 instead. In that case see if we
1452 * spotted a compatible north bridge to make sure.
1453 * (pci_find_device doesn't work yet)
1454 *
1455 * We can also enable the sis96x bit in the discovery register..
1456 */
1457#define SIS_DETECT_REGISTER 0x40
1458
1459static void quirk_sis_503(struct pci_dev *dev)
1460{
1461 u8 reg;
1462 u16 devid;
1463
1464 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1465 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1466 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1467 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1468 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1469 return;
1470 }
1471
1472 /*
1473 * Ok, it now shows up as a 96x.. run the 96x quirk by
1474 * hand in case it has already been processed.
1475 * (depends on link order, which is apparently not guaranteed)
1476 */
1477 dev->device = devid;
1478 quirk_sis_96x_smbus(dev);
1479}
1480DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1481DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1482
1483
1484/*
1485 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1486 * and MC97 modem controller are disabled when a second PCI soundcard is
1487 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1488 * -- bjd
1489 */
1490static void asus_hides_ac97_lpc(struct pci_dev *dev)
1491{
1492 u8 val;
1493 int asus_hides_ac97 = 0;
1494
1495 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1496 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1497 asus_hides_ac97 = 1;
1498 }
1499
1500 if (!asus_hides_ac97)
1501 return;
1502
1503 pci_read_config_byte(dev, 0x50, &val);
1504 if (val & 0xc0) {
1505 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1506 pci_read_config_byte(dev, 0x50, &val);
1507 if (val & 0xc0)
1508 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1509 else
1510 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1511 }
1512}
1513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1514DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1515
1516#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1517
1518/*
1519 * If we are using libata we can drive this chip properly but must
1520 * do this early on to make the additional device appear during
1521 * the PCI scanning.
1522 */
1523static void quirk_jmicron_ata(struct pci_dev *pdev)
1524{
1525 u32 conf1, conf5, class;
1526 u8 hdr;
1527
1528 /* Only poke fn 0 */
1529 if (PCI_FUNC(pdev->devfn))
1530 return;
1531
1532 pci_read_config_dword(pdev, 0x40, &conf1);
1533 pci_read_config_dword(pdev, 0x80, &conf5);
1534
1535 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1536 conf5 &= ~(1 << 24); /* Clear bit 24 */
1537
1538 switch (pdev->device) {
1539 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1540 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1541 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1542 /* The controller should be in single function ahci mode */
1543 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1544 break;
1545
1546 case PCI_DEVICE_ID_JMICRON_JMB365:
1547 case PCI_DEVICE_ID_JMICRON_JMB366:
1548 /* Redirect IDE second PATA port to the right spot */
1549 conf5 |= (1 << 24);
1550 /* Fall through */
1551 case PCI_DEVICE_ID_JMICRON_JMB361:
1552 case PCI_DEVICE_ID_JMICRON_JMB363:
1553 case PCI_DEVICE_ID_JMICRON_JMB369:
1554 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1555 /* Set the class codes correctly and then direct IDE 0 */
1556 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1557 break;
1558
1559 case PCI_DEVICE_ID_JMICRON_JMB368:
1560 /* The controller should be in single function IDE mode */
1561 conf1 |= 0x00C00000; /* Set 22, 23 */
1562 break;
1563 }
1564
1565 pci_write_config_dword(pdev, 0x40, conf1);
1566 pci_write_config_dword(pdev, 0x80, conf5);
1567
1568 /* Update pdev accordingly */
1569 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1570 pdev->hdr_type = hdr & 0x7f;
1571 pdev->multifunction = !!(hdr & 0x80);
1572
1573 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1574 pdev->class = class >> 8;
1575}
1576DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1577DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1578DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1579DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1580DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1581DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1582DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1583DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1585DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1586DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1587DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1588DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1589DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1590DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1591DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1592DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1593DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1594
1595#endif
1596
1597#ifdef CONFIG_X86_IO_APIC
1598static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1599{
1600 int i;
1601
1602 if ((pdev->class >> 8) != 0xff00)
1603 return;
1604
1605 /* the first BAR is the location of the IO APIC...we must
1606 * not touch this (and it's already covered by the fixmap), so
1607 * forcibly insert it into the resource tree */
1608 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1609 insert_resource(&iomem_resource, &pdev->resource[0]);
1610
1611 /* The next five BARs all seem to be rubbish, so just clean
1612 * them out */
1613 for (i=1; i < 6; i++) {
1614 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1615 }
1616
1617}
1618DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1619#endif
1620
1621static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1622{
1623 pci_msi_off(pdev);
1624 pdev->no_msi = 1;
1625}
1626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1629
1630
1631/*
1632 * It's possible for the MSI to get corrupted if shpc and acpi
1633 * are used together on certain PXH-based systems.
1634 */
1635static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1636{
1637 pci_msi_off(dev);
1638 dev->no_msi = 1;
1639 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1640}
1641DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1642DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1643DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1644DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1645DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1646
1647/*
1648 * Some Intel PCI Express chipsets have trouble with downstream
1649 * device power management.
1650 */
1651static void quirk_intel_pcie_pm(struct pci_dev * dev)
1652{
1653 pci_pm_d3_delay = 120;
1654 dev->no_d1d2 = 1;
1655}
1656
1657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1677DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1678
1679#ifdef CONFIG_X86_IO_APIC
1680/*
1681 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1682 * remap the original interrupt in the linux kernel to the boot interrupt, so
1683 * that a PCI device's interrupt handler is installed on the boot interrupt
1684 * line instead.
1685 */
1686static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1687{
1688 if (noioapicquirk || noioapicreroute)
1689 return;
1690
1691 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1692 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1693 dev->vendor, dev->device);
1694}
1695DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1697DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1699DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1700DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1701DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1703DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1704DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1705DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1706DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1707DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1708DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1709DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1710DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1711
1712/*
1713 * On some chipsets we can disable the generation of legacy INTx boot
1714 * interrupts.
1715 */
1716
1717/*
1718 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1719 * 300641-004US, section 5.7.3.
1720 */
1721#define INTEL_6300_IOAPIC_ABAR 0x40
1722#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1723
1724static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1725{
1726 u16 pci_config_word;
1727
1728 if (noioapicquirk)
1729 return;
1730
1731 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1732 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1733 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1734
1735 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1736 dev->vendor, dev->device);
1737}
1738DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1739DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1740
1741/*
1742 * disable boot interrupts on HT-1000
1743 */
1744#define BC_HT1000_FEATURE_REG 0x64
1745#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1746#define BC_HT1000_MAP_IDX 0xC00
1747#define BC_HT1000_MAP_DATA 0xC01
1748
1749static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1750{
1751 u32 pci_config_dword;
1752 u8 irq;
1753
1754 if (noioapicquirk)
1755 return;
1756
1757 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1758 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1759 BC_HT1000_PIC_REGS_ENABLE);
1760
1761 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1762 outb(irq, BC_HT1000_MAP_IDX);
1763 outb(0x00, BC_HT1000_MAP_DATA);
1764 }
1765
1766 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1767
1768 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1769 dev->vendor, dev->device);
1770}
1771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1772DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1773
1774/*
1775 * disable boot interrupts on AMD and ATI chipsets
1776 */
1777/*
1778 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1779 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1780 * (due to an erratum).
1781 */
1782#define AMD_813X_MISC 0x40
1783#define AMD_813X_NOIOAMODE (1<<0)
1784#define AMD_813X_REV_B1 0x12
1785#define AMD_813X_REV_B2 0x13
1786
1787static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1788{
1789 u32 pci_config_dword;
1790
1791 if (noioapicquirk)
1792 return;
1793 if ((dev->revision == AMD_813X_REV_B1) ||
1794 (dev->revision == AMD_813X_REV_B2))
1795 return;
1796
1797 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1798 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1799 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1800
1801 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1802 dev->vendor, dev->device);
1803}
1804DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1805DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1806DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1807DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1808
1809#define AMD_8111_PCI_IRQ_ROUTING 0x56
1810
1811static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1812{
1813 u16 pci_config_word;
1814
1815 if (noioapicquirk)
1816 return;
1817
1818 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1819 if (!pci_config_word) {
1820 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1821 "already disabled\n", dev->vendor, dev->device);
1822 return;
1823 }
1824 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1825 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1826 dev->vendor, dev->device);
1827}
1828DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1829DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1830#endif /* CONFIG_X86_IO_APIC */
1831
1832/*
1833 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1834 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1835 * Re-allocate the region if needed...
1836 */
1837static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1838{
1839 struct resource *r = &dev->resource[0];
1840
1841 if (r->start & 0x8) {
1842 r->start = 0;
1843 r->end = 0xf;
1844 }
1845}
1846DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1847 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1848 quirk_tc86c001_ide);
1849
1850static void __devinit quirk_netmos(struct pci_dev *dev)
1851{
1852 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1853 unsigned int num_serial = dev->subsystem_device & 0xf;
1854
1855 /*
1856 * These Netmos parts are multiport serial devices with optional
1857 * parallel ports. Even when parallel ports are present, they
1858 * are identified as class SERIAL, which means the serial driver
1859 * will claim them. To prevent this, mark them as class OTHER.
1860 * These combo devices should be claimed by parport_serial.
1861 *
1862 * The subdevice ID is of the form 0x00PS, where <P> is the number
1863 * of parallel ports and <S> is the number of serial ports.
1864 */
1865 switch (dev->device) {
1866 case PCI_DEVICE_ID_NETMOS_9835:
1867 /* Well, this rule doesn't hold for the following 9835 device */
1868 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1869 dev->subsystem_device == 0x0299)
1870 return;
1871 case PCI_DEVICE_ID_NETMOS_9735:
1872 case PCI_DEVICE_ID_NETMOS_9745:
1873 case PCI_DEVICE_ID_NETMOS_9845:
1874 case PCI_DEVICE_ID_NETMOS_9855:
1875 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1876 num_parallel) {
1877 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1878 "%u serial); changing class SERIAL to OTHER "
1879 "(use parport_serial)\n",
1880 dev->device, num_parallel, num_serial);
1881 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1882 (dev->class & 0xff);
1883 }
1884 }
1885}
1886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1887
1888static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1889{
1890 u16 command, pmcsr;
1891 u8 __iomem *csr;
1892 u8 cmd_hi;
1893 int pm;
1894
1895 switch (dev->device) {
1896 /* PCI IDs taken from drivers/net/e100.c */
1897 case 0x1029:
1898 case 0x1030 ... 0x1034:
1899 case 0x1038 ... 0x103E:
1900 case 0x1050 ... 0x1057:
1901 case 0x1059:
1902 case 0x1064 ... 0x106B:
1903 case 0x1091 ... 0x1095:
1904 case 0x1209:
1905 case 0x1229:
1906 case 0x2449:
1907 case 0x2459:
1908 case 0x245D:
1909 case 0x27DC:
1910 break;
1911 default:
1912 return;
1913 }
1914
1915 /*
1916 * Some firmware hands off the e100 with interrupts enabled,
1917 * which can cause a flood of interrupts if packets are
1918 * received before the driver attaches to the device. So
1919 * disable all e100 interrupts here. The driver will
1920 * re-enable them when it's ready.
1921 */
1922 pci_read_config_word(dev, PCI_COMMAND, &command);
1923
1924 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1925 return;
1926
1927 /*
1928 * Check that the device is in the D0 power state. If it's not,
1929 * there is no point to look any further.
1930 */
1931 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1932 if (pm) {
1933 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1934 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1935 return;
1936 }
1937
1938 /* Convert from PCI bus to resource space. */
1939 csr = ioremap(pci_resource_start(dev, 0), 8);
1940 if (!csr) {
1941 dev_warn(&dev->dev, "Can't map e100 registers\n");
1942 return;
1943 }
1944
1945 cmd_hi = readb(csr + 3);
1946 if (cmd_hi == 0) {
1947 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1948 "disabling\n");
1949 writeb(1, csr + 3);
1950 }
1951
1952 iounmap(csr);
1953}
1954DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1955
1956/*
1957 * The 82575 and 82598 may experience data corruption issues when transitioning
1958 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1959 */
1960static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1961{
1962 dev_info(&dev->dev, "Disabling L0s\n");
1963 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1964}
1965DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1966DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1967DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1968DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1969DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1970DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1971DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1972DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1973DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1974DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1975DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1976DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1977DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1979
1980static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1981{
1982 /* rev 1 ncr53c810 chips don't set the class at all which means
1983 * they don't get their resources remapped. Fix that here.
1984 */
1985
1986 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1987 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1988 dev->class = PCI_CLASS_STORAGE_SCSI;
1989 }
1990}
1991DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1992
1993/* Enable 1k I/O space granularity on the Intel P64H2 */
1994static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1995{
1996 u16 en1k;
1997 u8 io_base_lo, io_limit_lo;
1998 unsigned long base, limit;
1999 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2000
2001 pci_read_config_word(dev, 0x40, &en1k);
2002
2003 if (en1k & 0x200) {
2004 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2005
2006 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
2007 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
2008 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2009 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2010
2011 if (base <= limit) {
2012 res->start = base;
2013 res->end = limit + 0x3ff;
2014 }
2015 }
2016}
2017DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2018
2019/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
2020 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
2021 * in drivers/pci/setup-bus.c
2022 */
2023static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
2024{
2025 u16 en1k, iobl_adr, iobl_adr_1k;
2026 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2027
2028 pci_read_config_word(dev, 0x40, &en1k);
2029
2030 if (en1k & 0x200) {
2031 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
2032
2033 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
2034
2035 if (iobl_adr != iobl_adr_1k) {
2036 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
2037 iobl_adr,iobl_adr_1k);
2038 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
2039 }
2040 }
2041}
2042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
2043
2044/* Under some circumstances, AER is not linked with extended capabilities.
2045 * Force it to be linked by setting the corresponding control bit in the
2046 * config space.
2047 */
2048static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2049{
2050 uint8_t b;
2051 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2052 if (!(b & 0x20)) {
2053 pci_write_config_byte(dev, 0xf41, b | 0x20);
2054 dev_info(&dev->dev,
2055 "Linking AER extended capability\n");
2056 }
2057 }
2058}
2059DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2060 quirk_nvidia_ck804_pcie_aer_ext_cap);
2061DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2062 quirk_nvidia_ck804_pcie_aer_ext_cap);
2063
2064static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2065{
2066 /*
2067 * Disable PCI Bus Parking and PCI Master read caching on CX700
2068 * which causes unspecified timing errors with a VT6212L on the PCI
2069 * bus leading to USB2.0 packet loss.
2070 *
2071 * This quirk is only enabled if a second (on the external PCI bus)
2072 * VT6212L is found -- the CX700 core itself also contains a USB
2073 * host controller with the same PCI ID as the VT6212L.
2074 */
2075
2076 /* Count VT6212L instances */
2077 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2078 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2079 uint8_t b;
2080
2081 /* p should contain the first (internal) VT6212L -- see if we have
2082 an external one by searching again */
2083 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2084 if (!p)
2085 return;
2086 pci_dev_put(p);
2087
2088 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2089 if (b & 0x40) {
2090 /* Turn off PCI Bus Parking */
2091 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2092
2093 dev_info(&dev->dev,
2094 "Disabling VIA CX700 PCI parking\n");
2095 }
2096 }
2097
2098 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2099 if (b != 0) {
2100 /* Turn off PCI Master read caching */
2101 pci_write_config_byte(dev, 0x72, 0x0);
2102
2103 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2104 pci_write_config_byte(dev, 0x75, 0x1);
2105
2106 /* Disable "Read FIFO Timer" */
2107 pci_write_config_byte(dev, 0x77, 0x0);
2108
2109 dev_info(&dev->dev,
2110 "Disabling VIA CX700 PCI caching\n");
2111 }
2112 }
2113}
2114DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2115
2116/*
2117 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2118 * VPD end tag will hang the device. This problem was initially
2119 * observed when a vpd entry was created in sysfs
2120 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2121 * will dump 32k of data. Reading a full 32k will cause an access
2122 * beyond the VPD end tag causing the device to hang. Once the device
2123 * is hung, the bnx2 driver will not be able to reset the device.
2124 * We believe that it is legal to read beyond the end tag and
2125 * therefore the solution is to limit the read/write length.
2126 */
2127static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2128{
2129 /*
2130 * Only disable the VPD capability for 5706, 5706S, 5708,
2131 * 5708S and 5709 rev. A
2132 */
2133 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2134 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2135 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2136 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2137 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2138 (dev->revision & 0xf0) == 0x0)) {
2139 if (dev->vpd)
2140 dev->vpd->len = 0x80;
2141 }
2142}
2143
2144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2145 PCI_DEVICE_ID_NX2_5706,
2146 quirk_brcm_570x_limit_vpd);
2147DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2148 PCI_DEVICE_ID_NX2_5706S,
2149 quirk_brcm_570x_limit_vpd);
2150DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2151 PCI_DEVICE_ID_NX2_5708,
2152 quirk_brcm_570x_limit_vpd);
2153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2154 PCI_DEVICE_ID_NX2_5708S,
2155 quirk_brcm_570x_limit_vpd);
2156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2157 PCI_DEVICE_ID_NX2_5709,
2158 quirk_brcm_570x_limit_vpd);
2159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2160 PCI_DEVICE_ID_NX2_5709S,
2161 quirk_brcm_570x_limit_vpd);
2162
2163/* Originally in EDAC sources for i82875P:
2164 * Intel tells BIOS developers to hide device 6 which
2165 * configures the overflow device access containing
2166 * the DRBs - this is where we expose device 6.
2167 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2168 */
2169static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2170{
2171 u8 reg;
2172
2173 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2174 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2175 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2176 }
2177}
2178
2179DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2180 quirk_unhide_mch_dev6);
2181DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2182 quirk_unhide_mch_dev6);
2183
2184#ifdef CONFIG_TILE
2185/*
2186 * The Tilera TILEmpower platform needs to set the link speed
2187 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2188 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2189 * capability register of the PEX8624 PCIe switch. The switch
2190 * supports link speed auto negotiation, but falsely sets
2191 * the link speed to 5GT/s.
2192 */
2193static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2194{
2195 if (tile_plx_gen1) {
2196 pci_write_config_dword(dev, 0x98, 0x1);
2197 mdelay(50);
2198 }
2199}
2200DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2201#endif /* CONFIG_TILE */
2202
2203#ifdef CONFIG_PCI_MSI
2204/* Some chipsets do not support MSI. We cannot easily rely on setting
2205 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2206 * some other busses controlled by the chipset even if Linux is not
2207 * aware of it. Instead of setting the flag on all busses in the
2208 * machine, simply disable MSI globally.
2209 */
2210static void __init quirk_disable_all_msi(struct pci_dev *dev)
2211{
2212 pci_no_msi();
2213 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2214}
2215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2222
2223/* Disable MSI on chipsets that are known to not support it */
2224static void __devinit quirk_disable_msi(struct pci_dev *dev)
2225{
2226 if (dev->subordinate) {
2227 dev_warn(&dev->dev, "MSI quirk detected; "
2228 "subordinate MSI disabled\n");
2229 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2230 }
2231}
2232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2233DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2235
2236/*
2237 * The APC bridge device in AMD 780 family northbridges has some random
2238 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2239 * we use the possible vendor/device IDs of the host bridge for the
2240 * declared quirk, and search for the APC bridge by slot number.
2241 */
2242static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2243{
2244 struct pci_dev *apc_bridge;
2245
2246 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2247 if (apc_bridge) {
2248 if (apc_bridge->device == 0x9602)
2249 quirk_disable_msi(apc_bridge);
2250 pci_dev_put(apc_bridge);
2251 }
2252}
2253DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2255
2256/* Go through the list of Hypertransport capabilities and
2257 * return 1 if a HT MSI capability is found and enabled */
2258static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2259{
2260 int pos, ttl = 48;
2261
2262 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2263 while (pos && ttl--) {
2264 u8 flags;
2265
2266 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2267 &flags) == 0)
2268 {
2269 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2270 flags & HT_MSI_FLAGS_ENABLE ?
2271 "enabled" : "disabled");
2272 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2273 }
2274
2275 pos = pci_find_next_ht_capability(dev, pos,
2276 HT_CAPTYPE_MSI_MAPPING);
2277 }
2278 return 0;
2279}
2280
2281/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2282static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2283{
2284 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2285 dev_warn(&dev->dev, "MSI quirk detected; "
2286 "subordinate MSI disabled\n");
2287 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2288 }
2289}
2290DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2291 quirk_msi_ht_cap);
2292
2293/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2294 * MSI are supported if the MSI capability set in any of these mappings.
2295 */
2296static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2297{
2298 struct pci_dev *pdev;
2299
2300 if (!dev->subordinate)
2301 return;
2302
2303 /* check HT MSI cap on this chipset and the root one.
2304 * a single one having MSI is enough to be sure that MSI are supported.
2305 */
2306 pdev = pci_get_slot(dev->bus, 0);
2307 if (!pdev)
2308 return;
2309 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2310 dev_warn(&dev->dev, "MSI quirk detected; "
2311 "subordinate MSI disabled\n");
2312 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2313 }
2314 pci_dev_put(pdev);
2315}
2316DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2317 quirk_nvidia_ck804_msi_ht_cap);
2318
2319/* Force enable MSI mapping capability on HT bridges */
2320static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2321{
2322 int pos, ttl = 48;
2323
2324 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2325 while (pos && ttl--) {
2326 u8 flags;
2327
2328 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2329 &flags) == 0) {
2330 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2331
2332 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2333 flags | HT_MSI_FLAGS_ENABLE);
2334 }
2335 pos = pci_find_next_ht_capability(dev, pos,
2336 HT_CAPTYPE_MSI_MAPPING);
2337 }
2338}
2339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2340 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2341 ht_enable_msi_mapping);
2342
2343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2344 ht_enable_msi_mapping);
2345
2346/* The P5N32-SLI motherboards from Asus have a problem with msi
2347 * for the MCP55 NIC. It is not yet determined whether the msi problem
2348 * also affects other devices. As for now, turn off msi for this device.
2349 */
2350static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2351{
2352 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2353
2354 if (board_name &&
2355 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2356 strstr(board_name, "P5N32-E SLI"))) {
2357 dev_info(&dev->dev,
2358 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2359 dev->no_msi = 1;
2360 }
2361}
2362DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2363 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2364 nvenet_msi_disable);
2365
2366/*
2367 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2368 * config register. This register controls the routing of legacy interrupts
2369 * from devices that route through the MCP55. If this register is misprogramed
2370 * interrupts are only sent to the bsp, unlike conventional systems where the
2371 * irq is broadxast to all online cpus. Not having this register set
2372 * properly prevents kdump from booting up properly, so lets make sure that
2373 * we have it set correctly.
2374 * Note this is an undocumented register.
2375 */
2376static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2377{
2378 u32 cfg;
2379
2380 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2381 return;
2382
2383 pci_read_config_dword(dev, 0x74, &cfg);
2384
2385 if (cfg & ((1 << 2) | (1 << 15))) {
2386 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2387 cfg &= ~((1 << 2) | (1 << 15));
2388 pci_write_config_dword(dev, 0x74, cfg);
2389 }
2390}
2391
2392DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2393 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2394 nvbridge_check_legacy_irq_routing);
2395
2396DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2397 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2398 nvbridge_check_legacy_irq_routing);
2399
2400static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2401{
2402 int pos, ttl = 48;
2403 int found = 0;
2404
2405 /* check if there is HT MSI cap or enabled on this device */
2406 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2407 while (pos && ttl--) {
2408 u8 flags;
2409
2410 if (found < 1)
2411 found = 1;
2412 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2413 &flags) == 0) {
2414 if (flags & HT_MSI_FLAGS_ENABLE) {
2415 if (found < 2) {
2416 found = 2;
2417 break;
2418 }
2419 }
2420 }
2421 pos = pci_find_next_ht_capability(dev, pos,
2422 HT_CAPTYPE_MSI_MAPPING);
2423 }
2424
2425 return found;
2426}
2427
2428static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2429{
2430 struct pci_dev *dev;
2431 int pos;
2432 int i, dev_no;
2433 int found = 0;
2434
2435 dev_no = host_bridge->devfn >> 3;
2436 for (i = dev_no + 1; i < 0x20; i++) {
2437 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2438 if (!dev)
2439 continue;
2440
2441 /* found next host bridge ?*/
2442 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2443 if (pos != 0) {
2444 pci_dev_put(dev);
2445 break;
2446 }
2447
2448 if (ht_check_msi_mapping(dev)) {
2449 found = 1;
2450 pci_dev_put(dev);
2451 break;
2452 }
2453 pci_dev_put(dev);
2454 }
2455
2456 return found;
2457}
2458
2459#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2460#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2461
2462static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2463{
2464 int pos, ctrl_off;
2465 int end = 0;
2466 u16 flags, ctrl;
2467
2468 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2469
2470 if (!pos)
2471 goto out;
2472
2473 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2474
2475 ctrl_off = ((flags >> 10) & 1) ?
2476 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2477 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2478
2479 if (ctrl & (1 << 6))
2480 end = 1;
2481
2482out:
2483 return end;
2484}
2485
2486static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2487{
2488 struct pci_dev *host_bridge;
2489 int pos;
2490 int i, dev_no;
2491 int found = 0;
2492
2493 dev_no = dev->devfn >> 3;
2494 for (i = dev_no; i >= 0; i--) {
2495 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2496 if (!host_bridge)
2497 continue;
2498
2499 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2500 if (pos != 0) {
2501 found = 1;
2502 break;
2503 }
2504 pci_dev_put(host_bridge);
2505 }
2506
2507 if (!found)
2508 return;
2509
2510 /* don't enable end_device/host_bridge with leaf directly here */
2511 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2512 host_bridge_with_leaf(host_bridge))
2513 goto out;
2514
2515 /* root did that ! */
2516 if (msi_ht_cap_enabled(host_bridge))
2517 goto out;
2518
2519 ht_enable_msi_mapping(dev);
2520
2521out:
2522 pci_dev_put(host_bridge);
2523}
2524
2525static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2526{
2527 int pos, ttl = 48;
2528
2529 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2530 while (pos && ttl--) {
2531 u8 flags;
2532
2533 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2534 &flags) == 0) {
2535 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2536
2537 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2538 flags & ~HT_MSI_FLAGS_ENABLE);
2539 }
2540 pos = pci_find_next_ht_capability(dev, pos,
2541 HT_CAPTYPE_MSI_MAPPING);
2542 }
2543}
2544
2545static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2546{
2547 struct pci_dev *host_bridge;
2548 int pos;
2549 int found;
2550
2551 if (!pci_msi_enabled())
2552 return;
2553
2554 /* check if there is HT MSI cap or enabled on this device */
2555 found = ht_check_msi_mapping(dev);
2556
2557 /* no HT MSI CAP */
2558 if (found == 0)
2559 return;
2560
2561 /*
2562 * HT MSI mapping should be disabled on devices that are below
2563 * a non-Hypertransport host bridge. Locate the host bridge...
2564 */
2565 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2566 if (host_bridge == NULL) {
2567 dev_warn(&dev->dev,
2568 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2569 return;
2570 }
2571
2572 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2573 if (pos != 0) {
2574 /* Host bridge is to HT */
2575 if (found == 1) {
2576 /* it is not enabled, try to enable it */
2577 if (all)
2578 ht_enable_msi_mapping(dev);
2579 else
2580 nv_ht_enable_msi_mapping(dev);
2581 }
2582 return;
2583 }
2584
2585 /* HT MSI is not enabled */
2586 if (found == 1)
2587 return;
2588
2589 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2590 ht_disable_msi_mapping(dev);
2591}
2592
2593static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2594{
2595 return __nv_msi_ht_cap_quirk(dev, 1);
2596}
2597
2598static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2599{
2600 return __nv_msi_ht_cap_quirk(dev, 0);
2601}
2602
2603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2604DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2605
2606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2607DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2608
2609static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2610{
2611 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2612}
2613static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2614{
2615 struct pci_dev *p;
2616
2617 /* SB700 MSI issue will be fixed at HW level from revision A21,
2618 * we need check PCI REVISION ID of SMBus controller to get SB700
2619 * revision.
2620 */
2621 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2622 NULL);
2623 if (!p)
2624 return;
2625
2626 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2627 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2628 pci_dev_put(p);
2629}
2630DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2631 PCI_DEVICE_ID_TIGON3_5780,
2632 quirk_msi_intx_disable_bug);
2633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2634 PCI_DEVICE_ID_TIGON3_5780S,
2635 quirk_msi_intx_disable_bug);
2636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2637 PCI_DEVICE_ID_TIGON3_5714,
2638 quirk_msi_intx_disable_bug);
2639DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2640 PCI_DEVICE_ID_TIGON3_5714S,
2641 quirk_msi_intx_disable_bug);
2642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2643 PCI_DEVICE_ID_TIGON3_5715,
2644 quirk_msi_intx_disable_bug);
2645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2646 PCI_DEVICE_ID_TIGON3_5715S,
2647 quirk_msi_intx_disable_bug);
2648
2649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2650 quirk_msi_intx_disable_ati_bug);
2651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2652 quirk_msi_intx_disable_ati_bug);
2653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2654 quirk_msi_intx_disable_ati_bug);
2655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2656 quirk_msi_intx_disable_ati_bug);
2657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2658 quirk_msi_intx_disable_ati_bug);
2659
2660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2661 quirk_msi_intx_disable_bug);
2662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2663 quirk_msi_intx_disable_bug);
2664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2665 quirk_msi_intx_disable_bug);
2666
2667#endif /* CONFIG_PCI_MSI */
2668
2669/* Allow manual resource allocation for PCI hotplug bridges
2670 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2671 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2672 * kernel fails to allocate resources when hotplug device is
2673 * inserted and PCI bus is rescanned.
2674 */
2675static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2676{
2677 dev->is_hotplug_bridge = 1;
2678}
2679
2680DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2681
2682/*
2683 * This is a quirk for the Ricoh MMC controller found as a part of
2684 * some mulifunction chips.
2685
2686 * This is very similar and based on the ricoh_mmc driver written by
2687 * Philip Langdale. Thank you for these magic sequences.
2688 *
2689 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2690 * and one or both of cardbus or firewire.
2691 *
2692 * It happens that they implement SD and MMC
2693 * support as separate controllers (and PCI functions). The linux SDHCI
2694 * driver supports MMC cards but the chip detects MMC cards in hardware
2695 * and directs them to the MMC controller - so the SDHCI driver never sees
2696 * them.
2697 *
2698 * To get around this, we must disable the useless MMC controller.
2699 * At that point, the SDHCI controller will start seeing them
2700 * It seems to be the case that the relevant PCI registers to deactivate the
2701 * MMC controller live on PCI function 0, which might be the cardbus controller
2702 * or the firewire controller, depending on the particular chip in question
2703 *
2704 * This has to be done early, because as soon as we disable the MMC controller
2705 * other pci functions shift up one level, e.g. function #2 becomes function
2706 * #1, and this will confuse the pci core.
2707 */
2708
2709#ifdef CONFIG_MMC_RICOH_MMC
2710static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2711{
2712 /* disable via cardbus interface */
2713 u8 write_enable;
2714 u8 write_target;
2715 u8 disable;
2716
2717 /* disable must be done via function #0 */
2718 if (PCI_FUNC(dev->devfn))
2719 return;
2720
2721 pci_read_config_byte(dev, 0xB7, &disable);
2722 if (disable & 0x02)
2723 return;
2724
2725 pci_read_config_byte(dev, 0x8E, &write_enable);
2726 pci_write_config_byte(dev, 0x8E, 0xAA);
2727 pci_read_config_byte(dev, 0x8D, &write_target);
2728 pci_write_config_byte(dev, 0x8D, 0xB7);
2729 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2730 pci_write_config_byte(dev, 0x8E, write_enable);
2731 pci_write_config_byte(dev, 0x8D, write_target);
2732
2733 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2734 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2735}
2736DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2737DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2738
2739static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2740{
2741 /* disable via firewire interface */
2742 u8 write_enable;
2743 u8 disable;
2744
2745 /* disable must be done via function #0 */
2746 if (PCI_FUNC(dev->devfn))
2747 return;
2748
2749 pci_read_config_byte(dev, 0xCB, &disable);
2750
2751 if (disable & 0x02)
2752 return;
2753
2754 pci_read_config_byte(dev, 0xCA, &write_enable);
2755 pci_write_config_byte(dev, 0xCA, 0x57);
2756 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2757 pci_write_config_byte(dev, 0xCA, write_enable);
2758
2759 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2760 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2761
2762 /*
2763 * RICOH 0xe823 SD/MMC card reader fails to recognize
2764 * certain types of SD/MMC cards. Lowering the SD base
2765 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2766 *
2767 * 0x150 - SD2.0 mode enable for changing base clock
2768 * frequency to 50Mhz
2769 * 0xe1 - Base clock frequency
2770 * 0x32 - 50Mhz new clock frequency
2771 * 0xf9 - Key register for 0x150
2772 * 0xfc - key register for 0xe1
2773 */
2774 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2775 pci_write_config_byte(dev, 0xf9, 0xfc);
2776 pci_write_config_byte(dev, 0x150, 0x10);
2777 pci_write_config_byte(dev, 0xf9, 0x00);
2778 pci_write_config_byte(dev, 0xfc, 0x01);
2779 pci_write_config_byte(dev, 0xe1, 0x32);
2780 pci_write_config_byte(dev, 0xfc, 0x00);
2781
2782 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2783 }
2784}
2785DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2786DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2787DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2788DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2789#endif /*CONFIG_MMC_RICOH_MMC*/
2790
2791#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
2792#define VTUNCERRMSK_REG 0x1ac
2793#define VTD_MSK_SPEC_ERRORS (1 << 31)
2794/*
2795 * This is a quirk for masking vt-d spec defined errors to platform error
2796 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2797 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2798 * on the RAS config settings of the platform) when a vt-d fault happens.
2799 * The resulting SMI caused the system to hang.
2800 *
2801 * VT-d spec related errors are already handled by the VT-d OS code, so no
2802 * need to report the same error through other channels.
2803 */
2804static void vtd_mask_spec_errors(struct pci_dev *dev)
2805{
2806 u32 word;
2807
2808 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2809 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2810}
2811DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2812DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2813#endif
2814
2815static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2816{
2817 /* TI 816x devices do not have class code set when in PCIe boot mode */
2818 if (dev->class == PCI_CLASS_NOT_DEFINED) {
2819 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2820 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2821 }
2822}
2823DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class);
2824
2825static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2826 struct pci_fixup *end)
2827{
2828 while (f < end) {
2829 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
2830 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
2831 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
2832 f->hook(dev);
2833 }
2834 f++;
2835 }
2836}
2837
2838extern struct pci_fixup __start_pci_fixups_early[];
2839extern struct pci_fixup __end_pci_fixups_early[];
2840extern struct pci_fixup __start_pci_fixups_header[];
2841extern struct pci_fixup __end_pci_fixups_header[];
2842extern struct pci_fixup __start_pci_fixups_final[];
2843extern struct pci_fixup __end_pci_fixups_final[];
2844extern struct pci_fixup __start_pci_fixups_enable[];
2845extern struct pci_fixup __end_pci_fixups_enable[];
2846extern struct pci_fixup __start_pci_fixups_resume[];
2847extern struct pci_fixup __end_pci_fixups_resume[];
2848extern struct pci_fixup __start_pci_fixups_resume_early[];
2849extern struct pci_fixup __end_pci_fixups_resume_early[];
2850extern struct pci_fixup __start_pci_fixups_suspend[];
2851extern struct pci_fixup __end_pci_fixups_suspend[];
2852
2853
2854void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2855{
2856 struct pci_fixup *start, *end;
2857
2858 switch(pass) {
2859 case pci_fixup_early:
2860 start = __start_pci_fixups_early;
2861 end = __end_pci_fixups_early;
2862 break;
2863
2864 case pci_fixup_header:
2865 start = __start_pci_fixups_header;
2866 end = __end_pci_fixups_header;
2867 break;
2868
2869 case pci_fixup_final:
2870 start = __start_pci_fixups_final;
2871 end = __end_pci_fixups_final;
2872 break;
2873
2874 case pci_fixup_enable:
2875 start = __start_pci_fixups_enable;
2876 end = __end_pci_fixups_enable;
2877 break;
2878
2879 case pci_fixup_resume:
2880 start = __start_pci_fixups_resume;
2881 end = __end_pci_fixups_resume;
2882 break;
2883
2884 case pci_fixup_resume_early:
2885 start = __start_pci_fixups_resume_early;
2886 end = __end_pci_fixups_resume_early;
2887 break;
2888
2889 case pci_fixup_suspend:
2890 start = __start_pci_fixups_suspend;
2891 end = __end_pci_fixups_suspend;
2892 break;
2893
2894 default:
2895 /* stupid compiler warning, you would think with an enum... */
2896 return;
2897 }
2898 pci_do_fixups(dev, start, end);
2899}
2900EXPORT_SYMBOL(pci_fixup_device);
2901
2902static int __init pci_apply_final_quirks(void)
2903{
2904 struct pci_dev *dev = NULL;
2905 u8 cls = 0;
2906 u8 tmp;
2907
2908 if (pci_cache_line_size)
2909 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2910 pci_cache_line_size << 2);
2911
2912 for_each_pci_dev(dev) {
2913 pci_fixup_device(pci_fixup_final, dev);
2914 /*
2915 * If arch hasn't set it explicitly yet, use the CLS
2916 * value shared by all PCI devices. If there's a
2917 * mismatch, fall back to the default value.
2918 */
2919 if (!pci_cache_line_size) {
2920 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
2921 if (!cls)
2922 cls = tmp;
2923 if (!tmp || cls == tmp)
2924 continue;
2925
2926 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
2927 "using %u bytes\n", cls << 2, tmp << 2,
2928 pci_dfl_cache_line_size << 2);
2929 pci_cache_line_size = pci_dfl_cache_line_size;
2930 }
2931 }
2932 if (!pci_cache_line_size) {
2933 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
2934 cls << 2, pci_dfl_cache_line_size << 2);
2935 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
2936 }
2937
2938 return 0;
2939}
2940
2941fs_initcall_sync(pci_apply_final_quirks);
2942
2943/*
2944 * Followings are device-specific reset methods which can be used to
2945 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
2946 * not available.
2947 */
2948static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
2949{
2950 int pos;
2951
2952 /* only implement PCI_CLASS_SERIAL_USB at present */
2953 if (dev->class == PCI_CLASS_SERIAL_USB) {
2954 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
2955 if (!pos)
2956 return -ENOTTY;
2957
2958 if (probe)
2959 return 0;
2960
2961 pci_write_config_byte(dev, pos + 0x4, 1);
2962 msleep(100);
2963
2964 return 0;
2965 } else {
2966 return -ENOTTY;
2967 }
2968}
2969
2970static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
2971{
2972 int pos;
2973
2974 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2975 if (!pos)
2976 return -ENOTTY;
2977
2978 if (probe)
2979 return 0;
2980
2981 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2982 PCI_EXP_DEVCTL_BCR_FLR);
2983 msleep(100);
2984
2985 return 0;
2986}
2987
2988#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
2989
2990static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
2991 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
2992 reset_intel_82599_sfp_virtfn },
2993 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2994 reset_intel_generic_dev },
2995 { 0 }
2996};
2997
2998int pci_dev_specific_reset(struct pci_dev *dev, int probe)
2999{
3000 const struct pci_dev_reset_methods *i;
3001
3002 for (i = pci_dev_reset_methods; i->reset; i++) {
3003 if ((i->vendor == dev->vendor ||
3004 i->vendor == (u16)PCI_ANY_ID) &&
3005 (i->device == dev->device ||
3006 i->device == (u16)PCI_ANY_ID))
3007 return i->reset(dev, probe);
3008 }
3009
3010 return -ENOTTY;
3011}
1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 */
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/export.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/acpi.h>
21#include <linux/kallsyms.h>
22#include <linux/dmi.h>
23#include <linux/pci-aspm.h>
24#include <linux/ioport.h>
25#include <linux/sched.h>
26#include <linux/ktime.h>
27#include <asm/dma.h> /* isa_dma_bridge_buggy */
28#include "pci.h"
29
30/*
31 * Decoding should be disabled for a PCI device during BAR sizing to avoid
32 * conflict. But doing so may cause problems on host bridge and perhaps other
33 * key system devices. For devices that need to have mmio decoding always-on,
34 * we need to set the dev->mmio_always_on bit.
35 */
36static void quirk_mmio_always_on(struct pci_dev *dev)
37{
38 dev->mmio_always_on = 1;
39}
40DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
41 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
42
43/* The Mellanox Tavor device gives false positive parity errors
44 * Mark this device with a broken_parity_status, to allow
45 * PCI scanning code to "skip" this now blacklisted device.
46 */
47static void quirk_mellanox_tavor(struct pci_dev *dev)
48{
49 dev->broken_parity_status = 1; /* This device gives false positives */
50}
51DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
52DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
53
54/* Deal with broken BIOSes that neglect to enable passive release,
55 which can cause problems in combination with the 82441FX/PPro MTRRs */
56static void quirk_passive_release(struct pci_dev *dev)
57{
58 struct pci_dev *d = NULL;
59 unsigned char dlc;
60
61 /* We have to make sure a particular bit is set in the PIIX3
62 ISA bridge, so we have to go out and find it. */
63 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
64 pci_read_config_byte(d, 0x82, &dlc);
65 if (!(dlc & 1<<1)) {
66 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
67 dlc |= 1<<1;
68 pci_write_config_byte(d, 0x82, dlc);
69 }
70 }
71}
72DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
73DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74
75/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
76 but VIA don't answer queries. If you happen to have good contacts at VIA
77 ask them for me please -- Alan
78
79 This appears to be BIOS not version dependent. So presumably there is a
80 chipset level fix */
81
82static void quirk_isa_dma_hangs(struct pci_dev *dev)
83{
84 if (!isa_dma_bridge_buggy) {
85 isa_dma_bridge_buggy=1;
86 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
87 }
88}
89 /*
90 * Its not totally clear which chipsets are the problematic ones
91 * We know 82C586 and 82C596 variants are affected.
92 */
93DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
94DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
95DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
100
101/*
102 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
103 * for some HT machines to use C4 w/o hanging.
104 */
105static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
106{
107 u32 pmbase;
108 u16 pm1a;
109
110 pci_read_config_dword(dev, 0x40, &pmbase);
111 pmbase = pmbase & 0xff80;
112 pm1a = inw(pmbase);
113
114 if (pm1a & 0x10) {
115 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
116 outw(0x10, pmbase);
117 }
118}
119DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
120
121/*
122 * Chipsets where PCI->PCI transfers vanish or hang
123 */
124static void quirk_nopcipci(struct pci_dev *dev)
125{
126 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
127 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
128 pci_pci_problems |= PCIPCI_FAIL;
129 }
130}
131DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
133
134static void quirk_nopciamd(struct pci_dev *dev)
135{
136 u8 rev;
137 pci_read_config_byte(dev, 0x08, &rev);
138 if (rev == 0x13) {
139 /* Erratum 24 */
140 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
141 pci_pci_problems |= PCIAGP_FAIL;
142 }
143}
144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
145
146/*
147 * Triton requires workarounds to be used by the drivers
148 */
149static void quirk_triton(struct pci_dev *dev)
150{
151 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
152 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
153 pci_pci_problems |= PCIPCI_TRITON;
154 }
155}
156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
160
161/*
162 * VIA Apollo KT133 needs PCI latency patch
163 * Made according to a windows driver based patch by George E. Breese
164 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
165 * and http://www.georgebreese.com/net/software/#PCI
166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
168 *
169 * Updated based on further information from the site and also on
170 * information provided by VIA
171 */
172static void quirk_vialatency(struct pci_dev *dev)
173{
174 struct pci_dev *p;
175 u8 busarb;
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
178
179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
180 if (p!=NULL) {
181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
183 if (p->revision < 0x40 || p->revision > 0x42)
184 goto exit;
185 } else {
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
187 if (p==NULL) /* No problem parts */
188 goto exit;
189 /* Check for buggy part revisions */
190 if (p->revision < 0x10 || p->revision > 0x12)
191 goto exit;
192 }
193
194 /*
195 * Ok we have the problem. Now set the PCI master grant to
196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
200 *
201 * VIA only apply this fix when an SB Live! is present but under
202 * both Linux and Windows this isn't enough, and we have seen
203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
205 */
206
207 pci_read_config_byte(dev, 0x76, &busarb);
208 /* Set bit 4 and bi 5 of byte 76 to 0x01
209 "Master priority rotation on every PCI master grant */
210 busarb &= ~(1<<5);
211 busarb |= (1<<4);
212 pci_write_config_byte(dev, 0x76, busarb);
213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
214exit:
215 pci_dev_put(p);
216}
217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
220/* Must restore this on a resume from RAM */
221DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224
225/*
226 * VIA Apollo VP3 needs ETBF on BT848/878
227 */
228static void quirk_viaetbf(struct pci_dev *dev)
229{
230 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
232 pci_pci_problems |= PCIPCI_VIAETBF;
233 }
234}
235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
236
237static void quirk_vsfx(struct pci_dev *dev)
238{
239 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
241 pci_pci_problems |= PCIPCI_VSFX;
242 }
243}
244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
245
246/*
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
251 */
252static void quirk_alimagik(struct pci_dev *dev)
253{
254 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
257 }
258}
259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
261
262/*
263 * Natoma has some interesting boundary conditions with Zoran stuff
264 * at least
265 */
266static void quirk_natoma(struct pci_dev *dev)
267{
268 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
270 pci_pci_problems |= PCIPCI_NATOMA;
271 }
272}
273DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
279
280/*
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
283 */
284static void quirk_citrine(struct pci_dev *dev)
285{
286 dev->cfg_size = 0xA0;
287}
288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
289
290/*
291 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
292 * If it's needed, re-allocate the region.
293 */
294static void quirk_s3_64M(struct pci_dev *dev)
295{
296 struct resource *r = &dev->resource[0];
297
298 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
299 r->flags |= IORESOURCE_UNSET;
300 r->start = 0;
301 r->end = 0x3ffffff;
302 }
303}
304DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
305DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
306
307/*
308 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
309 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
310 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
311 * (which conflicts w/ BAR1's memory range).
312 */
313static void quirk_cs5536_vsa(struct pci_dev *dev)
314{
315 if (pci_resource_len(dev, 0) != 8) {
316 struct resource *res = &dev->resource[0];
317 res->end = res->start + 8 - 1;
318 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
319 "(incorrect header); workaround applied.\n");
320 }
321}
322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
323
324static void quirk_io_region(struct pci_dev *dev, int port,
325 unsigned size, int nr, const char *name)
326{
327 u16 region;
328 struct pci_bus_region bus_region;
329 struct resource *res = dev->resource + nr;
330
331 pci_read_config_word(dev, port, ®ion);
332 region &= ~(size - 1);
333
334 if (!region)
335 return;
336
337 res->name = pci_name(dev);
338 res->flags = IORESOURCE_IO;
339
340 /* Convert from PCI bus to resource space */
341 bus_region.start = region;
342 bus_region.end = region + size - 1;
343 pcibios_bus_to_resource(dev->bus, res, &bus_region);
344
345 if (!pci_claim_resource(dev, nr))
346 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
347}
348
349/*
350 * ATI Northbridge setups MCE the processor if you even
351 * read somewhere between 0x3b0->0x3bb or read 0x3d3
352 */
353static void quirk_ati_exploding_mce(struct pci_dev *dev)
354{
355 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
356 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
357 request_region(0x3b0, 0x0C, "RadeonIGP");
358 request_region(0x3d3, 0x01, "RadeonIGP");
359}
360DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
361
362/*
363 * Let's make the southbridge information explicit instead
364 * of having to worry about people probing the ACPI areas,
365 * for example.. (Yes, it happens, and if you read the wrong
366 * ACPI register it will put the machine to sleep with no
367 * way of waking it up again. Bummer).
368 *
369 * ALI M7101: Two IO regions pointed to by words at
370 * 0xE0 (64 bytes of ACPI registers)
371 * 0xE2 (32 bytes of SMB registers)
372 */
373static void quirk_ali7101_acpi(struct pci_dev *dev)
374{
375 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
376 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
377}
378DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
379
380static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
381{
382 u32 devres;
383 u32 mask, size, base;
384
385 pci_read_config_dword(dev, port, &devres);
386 if ((devres & enable) != enable)
387 return;
388 mask = (devres >> 16) & 15;
389 base = devres & 0xffff;
390 size = 16;
391 for (;;) {
392 unsigned bit = size >> 1;
393 if ((bit & mask) == bit)
394 break;
395 size = bit;
396 }
397 /*
398 * For now we only print it out. Eventually we'll want to
399 * reserve it (at least if it's in the 0x1000+ range), but
400 * let's get enough confirmation reports first.
401 */
402 base &= -size;
403 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
404}
405
406static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
407{
408 u32 devres;
409 u32 mask, size, base;
410
411 pci_read_config_dword(dev, port, &devres);
412 if ((devres & enable) != enable)
413 return;
414 base = devres & 0xffff0000;
415 mask = (devres & 0x3f) << 16;
416 size = 128 << 16;
417 for (;;) {
418 unsigned bit = size >> 1;
419 if ((bit & mask) == bit)
420 break;
421 size = bit;
422 }
423 /*
424 * For now we only print it out. Eventually we'll want to
425 * reserve it, but let's get enough confirmation reports first.
426 */
427 base &= -size;
428 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
429}
430
431/*
432 * PIIX4 ACPI: Two IO regions pointed to by longwords at
433 * 0x40 (64 bytes of ACPI registers)
434 * 0x90 (16 bytes of SMB registers)
435 * and a few strange programmable PIIX4 device resources.
436 */
437static void quirk_piix4_acpi(struct pci_dev *dev)
438{
439 u32 res_a;
440
441 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
442 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
443
444 /* Device resource A has enables for some of the other ones */
445 pci_read_config_dword(dev, 0x5c, &res_a);
446
447 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
448 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
449
450 /* Device resource D is just bitfields for static resources */
451
452 /* Device 12 enabled? */
453 if (res_a & (1 << 29)) {
454 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
455 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
456 }
457 /* Device 13 enabled? */
458 if (res_a & (1 << 30)) {
459 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
460 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
461 }
462 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
463 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
464}
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
467
468#define ICH_PMBASE 0x40
469#define ICH_ACPI_CNTL 0x44
470#define ICH4_ACPI_EN 0x10
471#define ICH6_ACPI_EN 0x80
472#define ICH4_GPIOBASE 0x58
473#define ICH4_GPIO_CNTL 0x5c
474#define ICH4_GPIO_EN 0x10
475#define ICH6_GPIOBASE 0x48
476#define ICH6_GPIO_CNTL 0x4c
477#define ICH6_GPIO_EN 0x10
478
479/*
480 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
481 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
482 * 0x58 (64 bytes of GPIO I/O space)
483 */
484static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
485{
486 u8 enable;
487
488 /*
489 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
490 * with low legacy (and fixed) ports. We don't know the decoding
491 * priority and can't tell whether the legacy device or the one created
492 * here is really at that address. This happens on boards with broken
493 * BIOSes.
494 */
495
496 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
497 if (enable & ICH4_ACPI_EN)
498 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
499 "ICH4 ACPI/GPIO/TCO");
500
501 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
502 if (enable & ICH4_GPIO_EN)
503 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
504 "ICH4 GPIO");
505}
506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
509DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
516
517static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
518{
519 u8 enable;
520
521 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
522 if (enable & ICH6_ACPI_EN)
523 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
524 "ICH6 ACPI/GPIO/TCO");
525
526 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
527 if (enable & ICH6_GPIO_EN)
528 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
529 "ICH6 GPIO");
530}
531
532static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
533{
534 u32 val;
535 u32 size, base;
536
537 pci_read_config_dword(dev, reg, &val);
538
539 /* Enabled? */
540 if (!(val & 1))
541 return;
542 base = val & 0xfffc;
543 if (dynsize) {
544 /*
545 * This is not correct. It is 16, 32 or 64 bytes depending on
546 * register D31:F0:ADh bits 5:4.
547 *
548 * But this gets us at least _part_ of it.
549 */
550 size = 16;
551 } else {
552 size = 128;
553 }
554 base &= ~(size-1);
555
556 /* Just print it out for now. We should reserve it after more debugging */
557 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
558}
559
560static void quirk_ich6_lpc(struct pci_dev *dev)
561{
562 /* Shared ACPI/GPIO decode with all ICH6+ */
563 ich6_lpc_acpi_gpio(dev);
564
565 /* ICH6-specific generic IO decode */
566 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
567 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
568}
569DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
570DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
571
572static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
573{
574 u32 val;
575 u32 mask, base;
576
577 pci_read_config_dword(dev, reg, &val);
578
579 /* Enabled? */
580 if (!(val & 1))
581 return;
582
583 /*
584 * IO base in bits 15:2, mask in bits 23:18, both
585 * are dword-based
586 */
587 base = val & 0xfffc;
588 mask = (val >> 16) & 0xfc;
589 mask |= 3;
590
591 /* Just print it out for now. We should reserve it after more debugging */
592 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
593}
594
595/* ICH7-10 has the same common LPC generic IO decode registers */
596static void quirk_ich7_lpc(struct pci_dev *dev)
597{
598 /* We share the common ACPI/GPIO decode with ICH6 */
599 ich6_lpc_acpi_gpio(dev);
600
601 /* And have 4 ICH7+ generic decodes */
602 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
603 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
604 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
605 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
606}
607DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
608DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
609DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
610DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
611DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
612DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
613DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
614DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
616DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
617DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
618DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
619DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
620
621/*
622 * VIA ACPI: One IO region pointed to by longword at
623 * 0x48 or 0x20 (256 bytes of ACPI registers)
624 */
625static void quirk_vt82c586_acpi(struct pci_dev *dev)
626{
627 if (dev->revision & 0x10)
628 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
629 "vt82c586 ACPI");
630}
631DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
632
633/*
634 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
635 * 0x48 (256 bytes of ACPI registers)
636 * 0x70 (128 bytes of hardware monitoring register)
637 * 0x90 (16 bytes of SMB registers)
638 */
639static void quirk_vt82c686_acpi(struct pci_dev *dev)
640{
641 quirk_vt82c586_acpi(dev);
642
643 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
644 "vt82c686 HW-mon");
645
646 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
647}
648DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
649
650/*
651 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
652 * 0x88 (128 bytes of power management registers)
653 * 0xd0 (16 bytes of SMB registers)
654 */
655static void quirk_vt8235_acpi(struct pci_dev *dev)
656{
657 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
658 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
659}
660DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
661
662/*
663 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
664 * Disable fast back-to-back on the secondary bus segment
665 */
666static void quirk_xio2000a(struct pci_dev *dev)
667{
668 struct pci_dev *pdev;
669 u16 command;
670
671 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
672 "secondary bus fast back-to-back transfers disabled\n");
673 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
674 pci_read_config_word(pdev, PCI_COMMAND, &command);
675 if (command & PCI_COMMAND_FAST_BACK)
676 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
677 }
678}
679DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
680 quirk_xio2000a);
681
682#ifdef CONFIG_X86_IO_APIC
683
684#include <asm/io_apic.h>
685
686/*
687 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
688 * devices to the external APIC.
689 *
690 * TODO: When we have device-specific interrupt routers,
691 * this code will go away from quirks.
692 */
693static void quirk_via_ioapic(struct pci_dev *dev)
694{
695 u8 tmp;
696
697 if (nr_ioapics < 1)
698 tmp = 0; /* nothing routed to external APIC */
699 else
700 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
701
702 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
703 tmp == 0 ? "Disa" : "Ena");
704
705 /* Offset 0x58: External APIC IRQ output control */
706 pci_write_config_byte (dev, 0x58, tmp);
707}
708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
709DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
710
711/*
712 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
713 * This leads to doubled level interrupt rates.
714 * Set this bit to get rid of cycle wastage.
715 * Otherwise uncritical.
716 */
717static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
718{
719 u8 misc_control2;
720#define BYPASS_APIC_DEASSERT 8
721
722 pci_read_config_byte(dev, 0x5B, &misc_control2);
723 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
724 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
725 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
726 }
727}
728DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
729DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
730
731/*
732 * The AMD io apic can hang the box when an apic irq is masked.
733 * We check all revs >= B0 (yet not in the pre production!) as the bug
734 * is currently marked NoFix
735 *
736 * We have multiple reports of hangs with this chipset that went away with
737 * noapic specified. For the moment we assume it's the erratum. We may be wrong
738 * of course. However the advice is demonstrably good even if so..
739 */
740static void quirk_amd_ioapic(struct pci_dev *dev)
741{
742 if (dev->revision >= 0x02) {
743 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
744 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
745 }
746}
747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
748
749static void quirk_ioapic_rmw(struct pci_dev *dev)
750{
751 if (dev->devfn == 0 && dev->bus->number == 0)
752 sis_apic_bug = 1;
753}
754DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
755#endif /* CONFIG_X86_IO_APIC */
756
757/*
758 * Some settings of MMRBC can lead to data corruption so block changes.
759 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
760 */
761static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
762{
763 if (dev->subordinate && dev->revision <= 0x12) {
764 dev_info(&dev->dev, "AMD8131 rev %x detected; "
765 "disabling PCI-X MMRBC\n", dev->revision);
766 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
767 }
768}
769DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
770
771/*
772 * FIXME: it is questionable that quirk_via_acpi
773 * is needed. It shows up as an ISA bridge, and does not
774 * support the PCI_INTERRUPT_LINE register at all. Therefore
775 * it seems like setting the pci_dev's 'irq' to the
776 * value of the ACPI SCI interrupt is only done for convenience.
777 * -jgarzik
778 */
779static void quirk_via_acpi(struct pci_dev *d)
780{
781 /*
782 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
783 */
784 u8 irq;
785 pci_read_config_byte(d, 0x42, &irq);
786 irq &= 0xf;
787 if (irq && (irq != 2))
788 d->irq = irq;
789}
790DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
791DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
792
793
794/*
795 * VIA bridges which have VLink
796 */
797
798static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
799
800static void quirk_via_bridge(struct pci_dev *dev)
801{
802 /* See what bridge we have and find the device ranges */
803 switch (dev->device) {
804 case PCI_DEVICE_ID_VIA_82C686:
805 /* The VT82C686 is special, it attaches to PCI and can have
806 any device number. All its subdevices are functions of
807 that single device. */
808 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
809 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
810 break;
811 case PCI_DEVICE_ID_VIA_8237:
812 case PCI_DEVICE_ID_VIA_8237A:
813 via_vlink_dev_lo = 15;
814 break;
815 case PCI_DEVICE_ID_VIA_8235:
816 via_vlink_dev_lo = 16;
817 break;
818 case PCI_DEVICE_ID_VIA_8231:
819 case PCI_DEVICE_ID_VIA_8233_0:
820 case PCI_DEVICE_ID_VIA_8233A:
821 case PCI_DEVICE_ID_VIA_8233C_0:
822 via_vlink_dev_lo = 17;
823 break;
824 }
825}
826DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
829DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
830DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
831DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
832DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
833DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
834
835/**
836 * quirk_via_vlink - VIA VLink IRQ number update
837 * @dev: PCI device
838 *
839 * If the device we are dealing with is on a PIC IRQ we need to
840 * ensure that the IRQ line register which usually is not relevant
841 * for PCI cards, is actually written so that interrupts get sent
842 * to the right place.
843 * We only do this on systems where a VIA south bridge was detected,
844 * and only for VIA devices on the motherboard (see quirk_via_bridge
845 * above).
846 */
847
848static void quirk_via_vlink(struct pci_dev *dev)
849{
850 u8 irq, new_irq;
851
852 /* Check if we have VLink at all */
853 if (via_vlink_dev_lo == -1)
854 return;
855
856 new_irq = dev->irq;
857
858 /* Don't quirk interrupts outside the legacy IRQ range */
859 if (!new_irq || new_irq > 15)
860 return;
861
862 /* Internal device ? */
863 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
864 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
865 return;
866
867 /* This is an internal VLink device on a PIC interrupt. The BIOS
868 ought to have set this but may not have, so we redo it */
869
870 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
871 if (new_irq != irq) {
872 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
873 irq, new_irq);
874 udelay(15); /* unknown if delay really needed */
875 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
876 }
877}
878DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
879
880/*
881 * VIA VT82C598 has its device ID settable and many BIOSes
882 * set it to the ID of VT82C597 for backward compatibility.
883 * We need to switch it off to be able to recognize the real
884 * type of the chip.
885 */
886static void quirk_vt82c598_id(struct pci_dev *dev)
887{
888 pci_write_config_byte(dev, 0xfc, 0);
889 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
890}
891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
892
893/*
894 * CardBus controllers have a legacy base address that enables them
895 * to respond as i82365 pcmcia controllers. We don't want them to
896 * do this even if the Linux CardBus driver is not loaded, because
897 * the Linux i82365 driver does not (and should not) handle CardBus.
898 */
899static void quirk_cardbus_legacy(struct pci_dev *dev)
900{
901 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
902}
903DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
904 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
905DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
906 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
907
908/*
909 * Following the PCI ordering rules is optional on the AMD762. I'm not
910 * sure what the designers were smoking but let's not inhale...
911 *
912 * To be fair to AMD, it follows the spec by default, its BIOS people
913 * who turn it off!
914 */
915static void quirk_amd_ordering(struct pci_dev *dev)
916{
917 u32 pcic;
918 pci_read_config_dword(dev, 0x4C, &pcic);
919 if ((pcic&6)!=6) {
920 pcic |= 6;
921 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
922 pci_write_config_dword(dev, 0x4C, pcic);
923 pci_read_config_dword(dev, 0x84, &pcic);
924 pcic |= (1<<23); /* Required in this mode */
925 pci_write_config_dword(dev, 0x84, pcic);
926 }
927}
928DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
929DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
930
931/*
932 * DreamWorks provided workaround for Dunord I-3000 problem
933 *
934 * This card decodes and responds to addresses not apparently
935 * assigned to it. We force a larger allocation to ensure that
936 * nothing gets put too close to it.
937 */
938static void quirk_dunord(struct pci_dev *dev)
939{
940 struct resource *r = &dev->resource [1];
941
942 r->flags |= IORESOURCE_UNSET;
943 r->start = 0;
944 r->end = 0xffffff;
945}
946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
947
948/*
949 * i82380FB mobile docking controller: its PCI-to-PCI bridge
950 * is subtractive decoding (transparent), and does indicate this
951 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
952 * instead of 0x01.
953 */
954static void quirk_transparent_bridge(struct pci_dev *dev)
955{
956 dev->transparent = 1;
957}
958DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
959DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
960
961/*
962 * Common misconfiguration of the MediaGX/Geode PCI master that will
963 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
964 * datasheets found at http://www.national.com/analog for info on what
965 * these bits do. <christer@weinigel.se>
966 */
967static void quirk_mediagx_master(struct pci_dev *dev)
968{
969 u8 reg;
970 pci_read_config_byte(dev, 0x41, ®);
971 if (reg & 2) {
972 reg &= ~2;
973 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
974 pci_write_config_byte(dev, 0x41, reg);
975 }
976}
977DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
978DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
979
980/*
981 * Ensure C0 rev restreaming is off. This is normally done by
982 * the BIOS but in the odd case it is not the results are corruption
983 * hence the presence of a Linux check
984 */
985static void quirk_disable_pxb(struct pci_dev *pdev)
986{
987 u16 config;
988
989 if (pdev->revision != 0x04) /* Only C0 requires this */
990 return;
991 pci_read_config_word(pdev, 0x40, &config);
992 if (config & (1<<6)) {
993 config &= ~(1<<6);
994 pci_write_config_word(pdev, 0x40, config);
995 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
996 }
997}
998DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
999DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1000
1001static void quirk_amd_ide_mode(struct pci_dev *pdev)
1002{
1003 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1004 u8 tmp;
1005
1006 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1007 if (tmp == 0x01) {
1008 pci_read_config_byte(pdev, 0x40, &tmp);
1009 pci_write_config_byte(pdev, 0x40, tmp|1);
1010 pci_write_config_byte(pdev, 0x9, 1);
1011 pci_write_config_byte(pdev, 0xa, 6);
1012 pci_write_config_byte(pdev, 0x40, tmp);
1013
1014 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1015 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1016 }
1017}
1018DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1019DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1020DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1021DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1022DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1023DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1024DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1025DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1026
1027/*
1028 * Serverworks CSB5 IDE does not fully support native mode
1029 */
1030static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1031{
1032 u8 prog;
1033 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1034 if (prog & 5) {
1035 prog &= ~5;
1036 pdev->class &= ~5;
1037 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1038 /* PCI layer will sort out resources */
1039 }
1040}
1041DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1042
1043/*
1044 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1045 */
1046static void quirk_ide_samemode(struct pci_dev *pdev)
1047{
1048 u8 prog;
1049
1050 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1051
1052 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1053 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1054 prog &= ~5;
1055 pdev->class &= ~5;
1056 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1057 }
1058}
1059DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1060
1061/*
1062 * Some ATA devices break if put into D3
1063 */
1064
1065static void quirk_no_ata_d3(struct pci_dev *pdev)
1066{
1067 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1068}
1069/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1070DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1071 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1072DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1073 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1074/* ALi loses some register settings that we cannot then restore */
1075DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1076 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1077/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1078 occur when mode detecting */
1079DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1080 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1081
1082/* This was originally an Alpha specific thing, but it really fits here.
1083 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1084 */
1085static void quirk_eisa_bridge(struct pci_dev *dev)
1086{
1087 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1088}
1089DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1090
1091
1092/*
1093 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1094 * is not activated. The myth is that Asus said that they do not want the
1095 * users to be irritated by just another PCI Device in the Win98 device
1096 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1097 * package 2.7.0 for details)
1098 *
1099 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1100 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1101 * becomes necessary to do this tweak in two steps -- the chosen trigger
1102 * is either the Host bridge (preferred) or on-board VGA controller.
1103 *
1104 * Note that we used to unhide the SMBus that way on Toshiba laptops
1105 * (Satellite A40 and Tecra M2) but then found that the thermal management
1106 * was done by SMM code, which could cause unsynchronized concurrent
1107 * accesses to the SMBus registers, with potentially bad effects. Thus you
1108 * should be very careful when adding new entries: if SMM is accessing the
1109 * Intel SMBus, this is a very good reason to leave it hidden.
1110 *
1111 * Likewise, many recent laptops use ACPI for thermal management. If the
1112 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1113 * natively, and keeping the SMBus hidden is the right thing to do. If you
1114 * are about to add an entry in the table below, please first disassemble
1115 * the DSDT and double-check that there is no code accessing the SMBus.
1116 */
1117static int asus_hides_smbus;
1118
1119static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1120{
1121 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1122 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1123 switch(dev->subsystem_device) {
1124 case 0x8025: /* P4B-LX */
1125 case 0x8070: /* P4B */
1126 case 0x8088: /* P4B533 */
1127 case 0x1626: /* L3C notebook */
1128 asus_hides_smbus = 1;
1129 }
1130 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1131 switch(dev->subsystem_device) {
1132 case 0x80b1: /* P4GE-V */
1133 case 0x80b2: /* P4PE */
1134 case 0x8093: /* P4B533-V */
1135 asus_hides_smbus = 1;
1136 }
1137 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1138 switch(dev->subsystem_device) {
1139 case 0x8030: /* P4T533 */
1140 asus_hides_smbus = 1;
1141 }
1142 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1143 switch (dev->subsystem_device) {
1144 case 0x8070: /* P4G8X Deluxe */
1145 asus_hides_smbus = 1;
1146 }
1147 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1148 switch (dev->subsystem_device) {
1149 case 0x80c9: /* PU-DLS */
1150 asus_hides_smbus = 1;
1151 }
1152 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1153 switch (dev->subsystem_device) {
1154 case 0x1751: /* M2N notebook */
1155 case 0x1821: /* M5N notebook */
1156 case 0x1897: /* A6L notebook */
1157 asus_hides_smbus = 1;
1158 }
1159 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1160 switch (dev->subsystem_device) {
1161 case 0x184b: /* W1N notebook */
1162 case 0x186a: /* M6Ne notebook */
1163 asus_hides_smbus = 1;
1164 }
1165 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1166 switch (dev->subsystem_device) {
1167 case 0x80f2: /* P4P800-X */
1168 asus_hides_smbus = 1;
1169 }
1170 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1171 switch (dev->subsystem_device) {
1172 case 0x1882: /* M6V notebook */
1173 case 0x1977: /* A6VA notebook */
1174 asus_hides_smbus = 1;
1175 }
1176 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1177 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1178 switch(dev->subsystem_device) {
1179 case 0x088C: /* HP Compaq nc8000 */
1180 case 0x0890: /* HP Compaq nc6000 */
1181 asus_hides_smbus = 1;
1182 }
1183 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1184 switch (dev->subsystem_device) {
1185 case 0x12bc: /* HP D330L */
1186 case 0x12bd: /* HP D530 */
1187 case 0x006a: /* HP Compaq nx9500 */
1188 asus_hides_smbus = 1;
1189 }
1190 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1191 switch (dev->subsystem_device) {
1192 case 0x12bf: /* HP xw4100 */
1193 asus_hides_smbus = 1;
1194 }
1195 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1196 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1197 switch(dev->subsystem_device) {
1198 case 0xC00C: /* Samsung P35 notebook */
1199 asus_hides_smbus = 1;
1200 }
1201 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1202 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1203 switch(dev->subsystem_device) {
1204 case 0x0058: /* Compaq Evo N620c */
1205 asus_hides_smbus = 1;
1206 }
1207 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1208 switch(dev->subsystem_device) {
1209 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1210 /* Motherboard doesn't have Host bridge
1211 * subvendor/subdevice IDs, therefore checking
1212 * its on-board VGA controller */
1213 asus_hides_smbus = 1;
1214 }
1215 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1216 switch(dev->subsystem_device) {
1217 case 0x00b8: /* Compaq Evo D510 CMT */
1218 case 0x00b9: /* Compaq Evo D510 SFF */
1219 case 0x00ba: /* Compaq Evo D510 USDT */
1220 /* Motherboard doesn't have Host bridge
1221 * subvendor/subdevice IDs and on-board VGA
1222 * controller is disabled if an AGP card is
1223 * inserted, therefore checking USB UHCI
1224 * Controller #1 */
1225 asus_hides_smbus = 1;
1226 }
1227 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1228 switch (dev->subsystem_device) {
1229 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1230 /* Motherboard doesn't have host bridge
1231 * subvendor/subdevice IDs, therefore checking
1232 * its on-board VGA controller */
1233 asus_hides_smbus = 1;
1234 }
1235 }
1236}
1237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1243DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1247
1248DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1250DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1251
1252static void asus_hides_smbus_lpc(struct pci_dev *dev)
1253{
1254 u16 val;
1255
1256 if (likely(!asus_hides_smbus))
1257 return;
1258
1259 pci_read_config_word(dev, 0xF2, &val);
1260 if (val & 0x8) {
1261 pci_write_config_word(dev, 0xF2, val & (~0x8));
1262 pci_read_config_word(dev, 0xF2, &val);
1263 if (val & 0x8)
1264 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1265 else
1266 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1267 }
1268}
1269DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1270DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1274DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1276DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1277DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1278DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1279DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1280DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1281DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1282DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1283
1284/* It appears we just have one such device. If not, we have a warning */
1285static void __iomem *asus_rcba_base;
1286static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1287{
1288 u32 rcba;
1289
1290 if (likely(!asus_hides_smbus))
1291 return;
1292 WARN_ON(asus_rcba_base);
1293
1294 pci_read_config_dword(dev, 0xF0, &rcba);
1295 /* use bits 31:14, 16 kB aligned */
1296 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1297 if (asus_rcba_base == NULL)
1298 return;
1299}
1300
1301static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1302{
1303 u32 val;
1304
1305 if (likely(!asus_hides_smbus || !asus_rcba_base))
1306 return;
1307 /* read the Function Disable register, dword mode only */
1308 val = readl(asus_rcba_base + 0x3418);
1309 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1310}
1311
1312static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1313{
1314 if (likely(!asus_hides_smbus || !asus_rcba_base))
1315 return;
1316 iounmap(asus_rcba_base);
1317 asus_rcba_base = NULL;
1318 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1319}
1320
1321static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1322{
1323 asus_hides_smbus_lpc_ich6_suspend(dev);
1324 asus_hides_smbus_lpc_ich6_resume_early(dev);
1325 asus_hides_smbus_lpc_ich6_resume(dev);
1326}
1327DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1328DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1329DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1330DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1331
1332/*
1333 * SiS 96x south bridge: BIOS typically hides SMBus device...
1334 */
1335static void quirk_sis_96x_smbus(struct pci_dev *dev)
1336{
1337 u8 val = 0;
1338 pci_read_config_byte(dev, 0x77, &val);
1339 if (val & 0x10) {
1340 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1341 pci_write_config_byte(dev, 0x77, val & ~0x10);
1342 }
1343}
1344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1348DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1349DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1350DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1351DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1352
1353/*
1354 * ... This is further complicated by the fact that some SiS96x south
1355 * bridges pretend to be 85C503/5513 instead. In that case see if we
1356 * spotted a compatible north bridge to make sure.
1357 * (pci_find_device doesn't work yet)
1358 *
1359 * We can also enable the sis96x bit in the discovery register..
1360 */
1361#define SIS_DETECT_REGISTER 0x40
1362
1363static void quirk_sis_503(struct pci_dev *dev)
1364{
1365 u8 reg;
1366 u16 devid;
1367
1368 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1369 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1370 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1371 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1372 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1373 return;
1374 }
1375
1376 /*
1377 * Ok, it now shows up as a 96x.. run the 96x quirk by
1378 * hand in case it has already been processed.
1379 * (depends on link order, which is apparently not guaranteed)
1380 */
1381 dev->device = devid;
1382 quirk_sis_96x_smbus(dev);
1383}
1384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1385DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1386
1387
1388/*
1389 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1390 * and MC97 modem controller are disabled when a second PCI soundcard is
1391 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1392 * -- bjd
1393 */
1394static void asus_hides_ac97_lpc(struct pci_dev *dev)
1395{
1396 u8 val;
1397 int asus_hides_ac97 = 0;
1398
1399 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1400 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1401 asus_hides_ac97 = 1;
1402 }
1403
1404 if (!asus_hides_ac97)
1405 return;
1406
1407 pci_read_config_byte(dev, 0x50, &val);
1408 if (val & 0xc0) {
1409 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1410 pci_read_config_byte(dev, 0x50, &val);
1411 if (val & 0xc0)
1412 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1413 else
1414 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1415 }
1416}
1417DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1418DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1419
1420#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1421
1422/*
1423 * If we are using libata we can drive this chip properly but must
1424 * do this early on to make the additional device appear during
1425 * the PCI scanning.
1426 */
1427static void quirk_jmicron_ata(struct pci_dev *pdev)
1428{
1429 u32 conf1, conf5, class;
1430 u8 hdr;
1431
1432 /* Only poke fn 0 */
1433 if (PCI_FUNC(pdev->devfn))
1434 return;
1435
1436 pci_read_config_dword(pdev, 0x40, &conf1);
1437 pci_read_config_dword(pdev, 0x80, &conf5);
1438
1439 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1440 conf5 &= ~(1 << 24); /* Clear bit 24 */
1441
1442 switch (pdev->device) {
1443 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1444 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1445 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1446 /* The controller should be in single function ahci mode */
1447 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1448 break;
1449
1450 case PCI_DEVICE_ID_JMICRON_JMB365:
1451 case PCI_DEVICE_ID_JMICRON_JMB366:
1452 /* Redirect IDE second PATA port to the right spot */
1453 conf5 |= (1 << 24);
1454 /* Fall through */
1455 case PCI_DEVICE_ID_JMICRON_JMB361:
1456 case PCI_DEVICE_ID_JMICRON_JMB363:
1457 case PCI_DEVICE_ID_JMICRON_JMB369:
1458 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1459 /* Set the class codes correctly and then direct IDE 0 */
1460 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1461 break;
1462
1463 case PCI_DEVICE_ID_JMICRON_JMB368:
1464 /* The controller should be in single function IDE mode */
1465 conf1 |= 0x00C00000; /* Set 22, 23 */
1466 break;
1467 }
1468
1469 pci_write_config_dword(pdev, 0x40, conf1);
1470 pci_write_config_dword(pdev, 0x80, conf5);
1471
1472 /* Update pdev accordingly */
1473 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1474 pdev->hdr_type = hdr & 0x7f;
1475 pdev->multifunction = !!(hdr & 0x80);
1476
1477 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1478 pdev->class = class >> 8;
1479}
1480DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1481DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1482DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1483DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1484DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1485DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1486DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1487DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1488DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1489DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1490DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1491DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1492DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1493DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1494DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1495DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1496DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1497DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1498
1499#endif
1500
1501#ifdef CONFIG_X86_IO_APIC
1502static void quirk_alder_ioapic(struct pci_dev *pdev)
1503{
1504 int i;
1505
1506 if ((pdev->class >> 8) != 0xff00)
1507 return;
1508
1509 /* the first BAR is the location of the IO APIC...we must
1510 * not touch this (and it's already covered by the fixmap), so
1511 * forcibly insert it into the resource tree */
1512 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1513 insert_resource(&iomem_resource, &pdev->resource[0]);
1514
1515 /* The next five BARs all seem to be rubbish, so just clean
1516 * them out */
1517 for (i=1; i < 6; i++) {
1518 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1519 }
1520
1521}
1522DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1523#endif
1524
1525static void quirk_pcie_mch(struct pci_dev *pdev)
1526{
1527 pci_msi_off(pdev);
1528 pdev->no_msi = 1;
1529}
1530DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1531DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1532DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1533
1534
1535/*
1536 * It's possible for the MSI to get corrupted if shpc and acpi
1537 * are used together on certain PXH-based systems.
1538 */
1539static void quirk_pcie_pxh(struct pci_dev *dev)
1540{
1541 pci_msi_off(dev);
1542 dev->no_msi = 1;
1543 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1544}
1545DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1546DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1547DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1548DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1549DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1550
1551/*
1552 * Some Intel PCI Express chipsets have trouble with downstream
1553 * device power management.
1554 */
1555static void quirk_intel_pcie_pm(struct pci_dev * dev)
1556{
1557 pci_pm_d3_delay = 120;
1558 dev->no_d1d2 = 1;
1559}
1560
1561DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1562DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1563DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1564DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1565DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1567DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1577DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1579DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1582
1583#ifdef CONFIG_X86_IO_APIC
1584/*
1585 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1586 * remap the original interrupt in the linux kernel to the boot interrupt, so
1587 * that a PCI device's interrupt handler is installed on the boot interrupt
1588 * line instead.
1589 */
1590static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1591{
1592 if (noioapicquirk || noioapicreroute)
1593 return;
1594
1595 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1596 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1597 dev->vendor, dev->device);
1598}
1599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1607DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1608DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1609DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1610DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1611DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1612DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1613DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1614DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1615
1616/*
1617 * On some chipsets we can disable the generation of legacy INTx boot
1618 * interrupts.
1619 */
1620
1621/*
1622 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1623 * 300641-004US, section 5.7.3.
1624 */
1625#define INTEL_6300_IOAPIC_ABAR 0x40
1626#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1627
1628static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1629{
1630 u16 pci_config_word;
1631
1632 if (noioapicquirk)
1633 return;
1634
1635 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1636 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1637 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1638
1639 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1640 dev->vendor, dev->device);
1641}
1642DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1643DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1644
1645/*
1646 * disable boot interrupts on HT-1000
1647 */
1648#define BC_HT1000_FEATURE_REG 0x64
1649#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1650#define BC_HT1000_MAP_IDX 0xC00
1651#define BC_HT1000_MAP_DATA 0xC01
1652
1653static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1654{
1655 u32 pci_config_dword;
1656 u8 irq;
1657
1658 if (noioapicquirk)
1659 return;
1660
1661 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1662 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1663 BC_HT1000_PIC_REGS_ENABLE);
1664
1665 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1666 outb(irq, BC_HT1000_MAP_IDX);
1667 outb(0x00, BC_HT1000_MAP_DATA);
1668 }
1669
1670 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1671
1672 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1673 dev->vendor, dev->device);
1674}
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1676DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1677
1678/*
1679 * disable boot interrupts on AMD and ATI chipsets
1680 */
1681/*
1682 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1683 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1684 * (due to an erratum).
1685 */
1686#define AMD_813X_MISC 0x40
1687#define AMD_813X_NOIOAMODE (1<<0)
1688#define AMD_813X_REV_B1 0x12
1689#define AMD_813X_REV_B2 0x13
1690
1691static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1692{
1693 u32 pci_config_dword;
1694
1695 if (noioapicquirk)
1696 return;
1697 if ((dev->revision == AMD_813X_REV_B1) ||
1698 (dev->revision == AMD_813X_REV_B2))
1699 return;
1700
1701 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1702 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1703 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1704
1705 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1706 dev->vendor, dev->device);
1707}
1708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1709DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1710DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1711DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1712
1713#define AMD_8111_PCI_IRQ_ROUTING 0x56
1714
1715static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1716{
1717 u16 pci_config_word;
1718
1719 if (noioapicquirk)
1720 return;
1721
1722 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1723 if (!pci_config_word) {
1724 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1725 "already disabled\n", dev->vendor, dev->device);
1726 return;
1727 }
1728 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1729 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1730 dev->vendor, dev->device);
1731}
1732DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1733DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1734#endif /* CONFIG_X86_IO_APIC */
1735
1736/*
1737 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1738 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1739 * Re-allocate the region if needed...
1740 */
1741static void quirk_tc86c001_ide(struct pci_dev *dev)
1742{
1743 struct resource *r = &dev->resource[0];
1744
1745 if (r->start & 0x8) {
1746 r->flags |= IORESOURCE_UNSET;
1747 r->start = 0;
1748 r->end = 0xf;
1749 }
1750}
1751DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1752 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1753 quirk_tc86c001_ide);
1754
1755/*
1756 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1757 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1758 * being read correctly if bit 7 of the base address is set.
1759 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1760 * Re-allocate the regions to a 256-byte boundary if necessary.
1761 */
1762static void quirk_plx_pci9050(struct pci_dev *dev)
1763{
1764 unsigned int bar;
1765
1766 /* Fixed in revision 2 (PCI 9052). */
1767 if (dev->revision >= 2)
1768 return;
1769 for (bar = 0; bar <= 1; bar++)
1770 if (pci_resource_len(dev, bar) == 0x80 &&
1771 (pci_resource_start(dev, bar) & 0x80)) {
1772 struct resource *r = &dev->resource[bar];
1773 dev_info(&dev->dev,
1774 "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1775 bar);
1776 r->flags |= IORESOURCE_UNSET;
1777 r->start = 0;
1778 r->end = 0xff;
1779 }
1780}
1781DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1782 quirk_plx_pci9050);
1783/*
1784 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1785 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1786 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1787 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1788 *
1789 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1790 * driver.
1791 */
1792DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1793DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1794
1795static void quirk_netmos(struct pci_dev *dev)
1796{
1797 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1798 unsigned int num_serial = dev->subsystem_device & 0xf;
1799
1800 /*
1801 * These Netmos parts are multiport serial devices with optional
1802 * parallel ports. Even when parallel ports are present, they
1803 * are identified as class SERIAL, which means the serial driver
1804 * will claim them. To prevent this, mark them as class OTHER.
1805 * These combo devices should be claimed by parport_serial.
1806 *
1807 * The subdevice ID is of the form 0x00PS, where <P> is the number
1808 * of parallel ports and <S> is the number of serial ports.
1809 */
1810 switch (dev->device) {
1811 case PCI_DEVICE_ID_NETMOS_9835:
1812 /* Well, this rule doesn't hold for the following 9835 device */
1813 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1814 dev->subsystem_device == 0x0299)
1815 return;
1816 case PCI_DEVICE_ID_NETMOS_9735:
1817 case PCI_DEVICE_ID_NETMOS_9745:
1818 case PCI_DEVICE_ID_NETMOS_9845:
1819 case PCI_DEVICE_ID_NETMOS_9855:
1820 if (num_parallel) {
1821 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1822 "%u serial); changing class SERIAL to OTHER "
1823 "(use parport_serial)\n",
1824 dev->device, num_parallel, num_serial);
1825 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1826 (dev->class & 0xff);
1827 }
1828 }
1829}
1830DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1831 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1832
1833static void quirk_e100_interrupt(struct pci_dev *dev)
1834{
1835 u16 command, pmcsr;
1836 u8 __iomem *csr;
1837 u8 cmd_hi;
1838
1839 switch (dev->device) {
1840 /* PCI IDs taken from drivers/net/e100.c */
1841 case 0x1029:
1842 case 0x1030 ... 0x1034:
1843 case 0x1038 ... 0x103E:
1844 case 0x1050 ... 0x1057:
1845 case 0x1059:
1846 case 0x1064 ... 0x106B:
1847 case 0x1091 ... 0x1095:
1848 case 0x1209:
1849 case 0x1229:
1850 case 0x2449:
1851 case 0x2459:
1852 case 0x245D:
1853 case 0x27DC:
1854 break;
1855 default:
1856 return;
1857 }
1858
1859 /*
1860 * Some firmware hands off the e100 with interrupts enabled,
1861 * which can cause a flood of interrupts if packets are
1862 * received before the driver attaches to the device. So
1863 * disable all e100 interrupts here. The driver will
1864 * re-enable them when it's ready.
1865 */
1866 pci_read_config_word(dev, PCI_COMMAND, &command);
1867
1868 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1869 return;
1870
1871 /*
1872 * Check that the device is in the D0 power state. If it's not,
1873 * there is no point to look any further.
1874 */
1875 if (dev->pm_cap) {
1876 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1877 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1878 return;
1879 }
1880
1881 /* Convert from PCI bus to resource space. */
1882 csr = ioremap(pci_resource_start(dev, 0), 8);
1883 if (!csr) {
1884 dev_warn(&dev->dev, "Can't map e100 registers\n");
1885 return;
1886 }
1887
1888 cmd_hi = readb(csr + 3);
1889 if (cmd_hi == 0) {
1890 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1891 "disabling\n");
1892 writeb(1, csr + 3);
1893 }
1894
1895 iounmap(csr);
1896}
1897DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1898 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1899
1900/*
1901 * The 82575 and 82598 may experience data corruption issues when transitioning
1902 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1903 */
1904static void quirk_disable_aspm_l0s(struct pci_dev *dev)
1905{
1906 dev_info(&dev->dev, "Disabling L0s\n");
1907 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1908}
1909DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1910DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1912DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1913DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1915DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1916DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1922DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1923
1924static void fixup_rev1_53c810(struct pci_dev *dev)
1925{
1926 /* rev 1 ncr53c810 chips don't set the class at all which means
1927 * they don't get their resources remapped. Fix that here.
1928 */
1929
1930 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1931 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1932 dev->class = PCI_CLASS_STORAGE_SCSI;
1933 }
1934}
1935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1936
1937/* Enable 1k I/O space granularity on the Intel P64H2 */
1938static void quirk_p64h2_1k_io(struct pci_dev *dev)
1939{
1940 u16 en1k;
1941
1942 pci_read_config_word(dev, 0x40, &en1k);
1943
1944 if (en1k & 0x200) {
1945 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1946 dev->io_window_1k = 1;
1947 }
1948}
1949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1950
1951/* Under some circumstances, AER is not linked with extended capabilities.
1952 * Force it to be linked by setting the corresponding control bit in the
1953 * config space.
1954 */
1955static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1956{
1957 uint8_t b;
1958 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1959 if (!(b & 0x20)) {
1960 pci_write_config_byte(dev, 0xf41, b | 0x20);
1961 dev_info(&dev->dev,
1962 "Linking AER extended capability\n");
1963 }
1964 }
1965}
1966DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1967 quirk_nvidia_ck804_pcie_aer_ext_cap);
1968DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1969 quirk_nvidia_ck804_pcie_aer_ext_cap);
1970
1971static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1972{
1973 /*
1974 * Disable PCI Bus Parking and PCI Master read caching on CX700
1975 * which causes unspecified timing errors with a VT6212L on the PCI
1976 * bus leading to USB2.0 packet loss.
1977 *
1978 * This quirk is only enabled if a second (on the external PCI bus)
1979 * VT6212L is found -- the CX700 core itself also contains a USB
1980 * host controller with the same PCI ID as the VT6212L.
1981 */
1982
1983 /* Count VT6212L instances */
1984 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
1985 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
1986 uint8_t b;
1987
1988 /* p should contain the first (internal) VT6212L -- see if we have
1989 an external one by searching again */
1990 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
1991 if (!p)
1992 return;
1993 pci_dev_put(p);
1994
1995 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1996 if (b & 0x40) {
1997 /* Turn off PCI Bus Parking */
1998 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1999
2000 dev_info(&dev->dev,
2001 "Disabling VIA CX700 PCI parking\n");
2002 }
2003 }
2004
2005 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2006 if (b != 0) {
2007 /* Turn off PCI Master read caching */
2008 pci_write_config_byte(dev, 0x72, 0x0);
2009
2010 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2011 pci_write_config_byte(dev, 0x75, 0x1);
2012
2013 /* Disable "Read FIFO Timer" */
2014 pci_write_config_byte(dev, 0x77, 0x0);
2015
2016 dev_info(&dev->dev,
2017 "Disabling VIA CX700 PCI caching\n");
2018 }
2019 }
2020}
2021DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2022
2023/*
2024 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2025 * VPD end tag will hang the device. This problem was initially
2026 * observed when a vpd entry was created in sysfs
2027 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2028 * will dump 32k of data. Reading a full 32k will cause an access
2029 * beyond the VPD end tag causing the device to hang. Once the device
2030 * is hung, the bnx2 driver will not be able to reset the device.
2031 * We believe that it is legal to read beyond the end tag and
2032 * therefore the solution is to limit the read/write length.
2033 */
2034static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2035{
2036 /*
2037 * Only disable the VPD capability for 5706, 5706S, 5708,
2038 * 5708S and 5709 rev. A
2039 */
2040 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2041 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2042 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2043 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2044 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2045 (dev->revision & 0xf0) == 0x0)) {
2046 if (dev->vpd)
2047 dev->vpd->len = 0x80;
2048 }
2049}
2050
2051DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2052 PCI_DEVICE_ID_NX2_5706,
2053 quirk_brcm_570x_limit_vpd);
2054DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2055 PCI_DEVICE_ID_NX2_5706S,
2056 quirk_brcm_570x_limit_vpd);
2057DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2058 PCI_DEVICE_ID_NX2_5708,
2059 quirk_brcm_570x_limit_vpd);
2060DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2061 PCI_DEVICE_ID_NX2_5708S,
2062 quirk_brcm_570x_limit_vpd);
2063DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2064 PCI_DEVICE_ID_NX2_5709,
2065 quirk_brcm_570x_limit_vpd);
2066DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2067 PCI_DEVICE_ID_NX2_5709S,
2068 quirk_brcm_570x_limit_vpd);
2069
2070static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2071{
2072 u32 rev;
2073
2074 pci_read_config_dword(dev, 0xf4, &rev);
2075
2076 /* Only CAP the MRRS if the device is a 5719 A0 */
2077 if (rev == 0x05719000) {
2078 int readrq = pcie_get_readrq(dev);
2079 if (readrq > 2048)
2080 pcie_set_readrq(dev, 2048);
2081 }
2082}
2083
2084DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2085 PCI_DEVICE_ID_TIGON3_5719,
2086 quirk_brcm_5719_limit_mrrs);
2087
2088/* Originally in EDAC sources for i82875P:
2089 * Intel tells BIOS developers to hide device 6 which
2090 * configures the overflow device access containing
2091 * the DRBs - this is where we expose device 6.
2092 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2093 */
2094static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2095{
2096 u8 reg;
2097
2098 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2099 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2100 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2101 }
2102}
2103
2104DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2105 quirk_unhide_mch_dev6);
2106DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2107 quirk_unhide_mch_dev6);
2108
2109#ifdef CONFIG_TILEPRO
2110/*
2111 * The Tilera TILEmpower tilepro platform needs to set the link speed
2112 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2113 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2114 * capability register of the PEX8624 PCIe switch. The switch
2115 * supports link speed auto negotiation, but falsely sets
2116 * the link speed to 5GT/s.
2117 */
2118static void quirk_tile_plx_gen1(struct pci_dev *dev)
2119{
2120 if (tile_plx_gen1) {
2121 pci_write_config_dword(dev, 0x98, 0x1);
2122 mdelay(50);
2123 }
2124}
2125DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2126#endif /* CONFIG_TILEPRO */
2127
2128#ifdef CONFIG_PCI_MSI
2129/* Some chipsets do not support MSI. We cannot easily rely on setting
2130 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2131 * some other buses controlled by the chipset even if Linux is not
2132 * aware of it. Instead of setting the flag on all buses in the
2133 * machine, simply disable MSI globally.
2134 */
2135static void quirk_disable_all_msi(struct pci_dev *dev)
2136{
2137 pci_no_msi();
2138 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2139}
2140DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2141DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2142DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2143DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2146DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2147
2148/* Disable MSI on chipsets that are known to not support it */
2149static void quirk_disable_msi(struct pci_dev *dev)
2150{
2151 if (dev->subordinate) {
2152 dev_warn(&dev->dev, "MSI quirk detected; "
2153 "subordinate MSI disabled\n");
2154 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2155 }
2156}
2157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2160
2161/*
2162 * The APC bridge device in AMD 780 family northbridges has some random
2163 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2164 * we use the possible vendor/device IDs of the host bridge for the
2165 * declared quirk, and search for the APC bridge by slot number.
2166 */
2167static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2168{
2169 struct pci_dev *apc_bridge;
2170
2171 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2172 if (apc_bridge) {
2173 if (apc_bridge->device == 0x9602)
2174 quirk_disable_msi(apc_bridge);
2175 pci_dev_put(apc_bridge);
2176 }
2177}
2178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2179DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2180
2181/* Go through the list of Hypertransport capabilities and
2182 * return 1 if a HT MSI capability is found and enabled */
2183static int msi_ht_cap_enabled(struct pci_dev *dev)
2184{
2185 int pos, ttl = 48;
2186
2187 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2188 while (pos && ttl--) {
2189 u8 flags;
2190
2191 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2192 &flags) == 0)
2193 {
2194 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2195 flags & HT_MSI_FLAGS_ENABLE ?
2196 "enabled" : "disabled");
2197 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2198 }
2199
2200 pos = pci_find_next_ht_capability(dev, pos,
2201 HT_CAPTYPE_MSI_MAPPING);
2202 }
2203 return 0;
2204}
2205
2206/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2207static void quirk_msi_ht_cap(struct pci_dev *dev)
2208{
2209 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2210 dev_warn(&dev->dev, "MSI quirk detected; "
2211 "subordinate MSI disabled\n");
2212 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2213 }
2214}
2215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2216 quirk_msi_ht_cap);
2217
2218/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2219 * MSI are supported if the MSI capability set in any of these mappings.
2220 */
2221static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2222{
2223 struct pci_dev *pdev;
2224
2225 if (!dev->subordinate)
2226 return;
2227
2228 /* check HT MSI cap on this chipset and the root one.
2229 * a single one having MSI is enough to be sure that MSI are supported.
2230 */
2231 pdev = pci_get_slot(dev->bus, 0);
2232 if (!pdev)
2233 return;
2234 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2235 dev_warn(&dev->dev, "MSI quirk detected; "
2236 "subordinate MSI disabled\n");
2237 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2238 }
2239 pci_dev_put(pdev);
2240}
2241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2242 quirk_nvidia_ck804_msi_ht_cap);
2243
2244/* Force enable MSI mapping capability on HT bridges */
2245static void ht_enable_msi_mapping(struct pci_dev *dev)
2246{
2247 int pos, ttl = 48;
2248
2249 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2250 while (pos && ttl--) {
2251 u8 flags;
2252
2253 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2254 &flags) == 0) {
2255 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2256
2257 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2258 flags | HT_MSI_FLAGS_ENABLE);
2259 }
2260 pos = pci_find_next_ht_capability(dev, pos,
2261 HT_CAPTYPE_MSI_MAPPING);
2262 }
2263}
2264DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2265 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2266 ht_enable_msi_mapping);
2267
2268DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2269 ht_enable_msi_mapping);
2270
2271/* The P5N32-SLI motherboards from Asus have a problem with msi
2272 * for the MCP55 NIC. It is not yet determined whether the msi problem
2273 * also affects other devices. As for now, turn off msi for this device.
2274 */
2275static void nvenet_msi_disable(struct pci_dev *dev)
2276{
2277 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2278
2279 if (board_name &&
2280 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2281 strstr(board_name, "P5N32-E SLI"))) {
2282 dev_info(&dev->dev,
2283 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2284 dev->no_msi = 1;
2285 }
2286}
2287DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2288 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2289 nvenet_msi_disable);
2290
2291/*
2292 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2293 * config register. This register controls the routing of legacy
2294 * interrupts from devices that route through the MCP55. If this register
2295 * is misprogrammed, interrupts are only sent to the BSP, unlike
2296 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2297 * having this register set properly prevents kdump from booting up
2298 * properly, so let's make sure that we have it set correctly.
2299 * Note that this is an undocumented register.
2300 */
2301static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2302{
2303 u32 cfg;
2304
2305 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2306 return;
2307
2308 pci_read_config_dword(dev, 0x74, &cfg);
2309
2310 if (cfg & ((1 << 2) | (1 << 15))) {
2311 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2312 cfg &= ~((1 << 2) | (1 << 15));
2313 pci_write_config_dword(dev, 0x74, cfg);
2314 }
2315}
2316
2317DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2318 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2319 nvbridge_check_legacy_irq_routing);
2320
2321DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2322 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2323 nvbridge_check_legacy_irq_routing);
2324
2325static int ht_check_msi_mapping(struct pci_dev *dev)
2326{
2327 int pos, ttl = 48;
2328 int found = 0;
2329
2330 /* check if there is HT MSI cap or enabled on this device */
2331 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2332 while (pos && ttl--) {
2333 u8 flags;
2334
2335 if (found < 1)
2336 found = 1;
2337 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2338 &flags) == 0) {
2339 if (flags & HT_MSI_FLAGS_ENABLE) {
2340 if (found < 2) {
2341 found = 2;
2342 break;
2343 }
2344 }
2345 }
2346 pos = pci_find_next_ht_capability(dev, pos,
2347 HT_CAPTYPE_MSI_MAPPING);
2348 }
2349
2350 return found;
2351}
2352
2353static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2354{
2355 struct pci_dev *dev;
2356 int pos;
2357 int i, dev_no;
2358 int found = 0;
2359
2360 dev_no = host_bridge->devfn >> 3;
2361 for (i = dev_no + 1; i < 0x20; i++) {
2362 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2363 if (!dev)
2364 continue;
2365
2366 /* found next host bridge ?*/
2367 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2368 if (pos != 0) {
2369 pci_dev_put(dev);
2370 break;
2371 }
2372
2373 if (ht_check_msi_mapping(dev)) {
2374 found = 1;
2375 pci_dev_put(dev);
2376 break;
2377 }
2378 pci_dev_put(dev);
2379 }
2380
2381 return found;
2382}
2383
2384#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2385#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2386
2387static int is_end_of_ht_chain(struct pci_dev *dev)
2388{
2389 int pos, ctrl_off;
2390 int end = 0;
2391 u16 flags, ctrl;
2392
2393 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2394
2395 if (!pos)
2396 goto out;
2397
2398 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2399
2400 ctrl_off = ((flags >> 10) & 1) ?
2401 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2402 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2403
2404 if (ctrl & (1 << 6))
2405 end = 1;
2406
2407out:
2408 return end;
2409}
2410
2411static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2412{
2413 struct pci_dev *host_bridge;
2414 int pos;
2415 int i, dev_no;
2416 int found = 0;
2417
2418 dev_no = dev->devfn >> 3;
2419 for (i = dev_no; i >= 0; i--) {
2420 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2421 if (!host_bridge)
2422 continue;
2423
2424 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2425 if (pos != 0) {
2426 found = 1;
2427 break;
2428 }
2429 pci_dev_put(host_bridge);
2430 }
2431
2432 if (!found)
2433 return;
2434
2435 /* don't enable end_device/host_bridge with leaf directly here */
2436 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2437 host_bridge_with_leaf(host_bridge))
2438 goto out;
2439
2440 /* root did that ! */
2441 if (msi_ht_cap_enabled(host_bridge))
2442 goto out;
2443
2444 ht_enable_msi_mapping(dev);
2445
2446out:
2447 pci_dev_put(host_bridge);
2448}
2449
2450static void ht_disable_msi_mapping(struct pci_dev *dev)
2451{
2452 int pos, ttl = 48;
2453
2454 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2455 while (pos && ttl--) {
2456 u8 flags;
2457
2458 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2459 &flags) == 0) {
2460 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2461
2462 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2463 flags & ~HT_MSI_FLAGS_ENABLE);
2464 }
2465 pos = pci_find_next_ht_capability(dev, pos,
2466 HT_CAPTYPE_MSI_MAPPING);
2467 }
2468}
2469
2470static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2471{
2472 struct pci_dev *host_bridge;
2473 int pos;
2474 int found;
2475
2476 if (!pci_msi_enabled())
2477 return;
2478
2479 /* check if there is HT MSI cap or enabled on this device */
2480 found = ht_check_msi_mapping(dev);
2481
2482 /* no HT MSI CAP */
2483 if (found == 0)
2484 return;
2485
2486 /*
2487 * HT MSI mapping should be disabled on devices that are below
2488 * a non-Hypertransport host bridge. Locate the host bridge...
2489 */
2490 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2491 if (host_bridge == NULL) {
2492 dev_warn(&dev->dev,
2493 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2494 return;
2495 }
2496
2497 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2498 if (pos != 0) {
2499 /* Host bridge is to HT */
2500 if (found == 1) {
2501 /* it is not enabled, try to enable it */
2502 if (all)
2503 ht_enable_msi_mapping(dev);
2504 else
2505 nv_ht_enable_msi_mapping(dev);
2506 }
2507 goto out;
2508 }
2509
2510 /* HT MSI is not enabled */
2511 if (found == 1)
2512 goto out;
2513
2514 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2515 ht_disable_msi_mapping(dev);
2516
2517out:
2518 pci_dev_put(host_bridge);
2519}
2520
2521static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2522{
2523 return __nv_msi_ht_cap_quirk(dev, 1);
2524}
2525
2526static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2527{
2528 return __nv_msi_ht_cap_quirk(dev, 0);
2529}
2530
2531DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2532DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2533
2534DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2535DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2536
2537static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2538{
2539 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2540}
2541static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2542{
2543 struct pci_dev *p;
2544
2545 /* SB700 MSI issue will be fixed at HW level from revision A21,
2546 * we need check PCI REVISION ID of SMBus controller to get SB700
2547 * revision.
2548 */
2549 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2550 NULL);
2551 if (!p)
2552 return;
2553
2554 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2555 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2556 pci_dev_put(p);
2557}
2558static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2559{
2560 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2561 if (dev->revision < 0x18) {
2562 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2563 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2564 }
2565}
2566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2567 PCI_DEVICE_ID_TIGON3_5780,
2568 quirk_msi_intx_disable_bug);
2569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2570 PCI_DEVICE_ID_TIGON3_5780S,
2571 quirk_msi_intx_disable_bug);
2572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2573 PCI_DEVICE_ID_TIGON3_5714,
2574 quirk_msi_intx_disable_bug);
2575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2576 PCI_DEVICE_ID_TIGON3_5714S,
2577 quirk_msi_intx_disable_bug);
2578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2579 PCI_DEVICE_ID_TIGON3_5715,
2580 quirk_msi_intx_disable_bug);
2581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2582 PCI_DEVICE_ID_TIGON3_5715S,
2583 quirk_msi_intx_disable_bug);
2584
2585DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2586 quirk_msi_intx_disable_ati_bug);
2587DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2588 quirk_msi_intx_disable_ati_bug);
2589DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2590 quirk_msi_intx_disable_ati_bug);
2591DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2592 quirk_msi_intx_disable_ati_bug);
2593DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2594 quirk_msi_intx_disable_ati_bug);
2595
2596DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2597 quirk_msi_intx_disable_bug);
2598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2599 quirk_msi_intx_disable_bug);
2600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2601 quirk_msi_intx_disable_bug);
2602
2603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2604 quirk_msi_intx_disable_bug);
2605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2606 quirk_msi_intx_disable_bug);
2607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2608 quirk_msi_intx_disable_bug);
2609DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2610 quirk_msi_intx_disable_bug);
2611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2612 quirk_msi_intx_disable_bug);
2613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2614 quirk_msi_intx_disable_bug);
2615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2616 quirk_msi_intx_disable_qca_bug);
2617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2618 quirk_msi_intx_disable_qca_bug);
2619DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2620 quirk_msi_intx_disable_qca_bug);
2621DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2622 quirk_msi_intx_disable_qca_bug);
2623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2624 quirk_msi_intx_disable_qca_bug);
2625#endif /* CONFIG_PCI_MSI */
2626
2627/* Allow manual resource allocation for PCI hotplug bridges
2628 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2629 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2630 * kernel fails to allocate resources when hotplug device is
2631 * inserted and PCI bus is rescanned.
2632 */
2633static void quirk_hotplug_bridge(struct pci_dev *dev)
2634{
2635 dev->is_hotplug_bridge = 1;
2636}
2637
2638DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2639
2640/*
2641 * This is a quirk for the Ricoh MMC controller found as a part of
2642 * some mulifunction chips.
2643
2644 * This is very similar and based on the ricoh_mmc driver written by
2645 * Philip Langdale. Thank you for these magic sequences.
2646 *
2647 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2648 * and one or both of cardbus or firewire.
2649 *
2650 * It happens that they implement SD and MMC
2651 * support as separate controllers (and PCI functions). The linux SDHCI
2652 * driver supports MMC cards but the chip detects MMC cards in hardware
2653 * and directs them to the MMC controller - so the SDHCI driver never sees
2654 * them.
2655 *
2656 * To get around this, we must disable the useless MMC controller.
2657 * At that point, the SDHCI controller will start seeing them
2658 * It seems to be the case that the relevant PCI registers to deactivate the
2659 * MMC controller live on PCI function 0, which might be the cardbus controller
2660 * or the firewire controller, depending on the particular chip in question
2661 *
2662 * This has to be done early, because as soon as we disable the MMC controller
2663 * other pci functions shift up one level, e.g. function #2 becomes function
2664 * #1, and this will confuse the pci core.
2665 */
2666
2667#ifdef CONFIG_MMC_RICOH_MMC
2668static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2669{
2670 /* disable via cardbus interface */
2671 u8 write_enable;
2672 u8 write_target;
2673 u8 disable;
2674
2675 /* disable must be done via function #0 */
2676 if (PCI_FUNC(dev->devfn))
2677 return;
2678
2679 pci_read_config_byte(dev, 0xB7, &disable);
2680 if (disable & 0x02)
2681 return;
2682
2683 pci_read_config_byte(dev, 0x8E, &write_enable);
2684 pci_write_config_byte(dev, 0x8E, 0xAA);
2685 pci_read_config_byte(dev, 0x8D, &write_target);
2686 pci_write_config_byte(dev, 0x8D, 0xB7);
2687 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2688 pci_write_config_byte(dev, 0x8E, write_enable);
2689 pci_write_config_byte(dev, 0x8D, write_target);
2690
2691 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2692 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2693}
2694DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2695DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2696
2697static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2698{
2699 /* disable via firewire interface */
2700 u8 write_enable;
2701 u8 disable;
2702
2703 /* disable must be done via function #0 */
2704 if (PCI_FUNC(dev->devfn))
2705 return;
2706 /*
2707 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2708 * certain types of SD/MMC cards. Lowering the SD base
2709 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2710 *
2711 * 0x150 - SD2.0 mode enable for changing base clock
2712 * frequency to 50Mhz
2713 * 0xe1 - Base clock frequency
2714 * 0x32 - 50Mhz new clock frequency
2715 * 0xf9 - Key register for 0x150
2716 * 0xfc - key register for 0xe1
2717 */
2718 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2719 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2720 pci_write_config_byte(dev, 0xf9, 0xfc);
2721 pci_write_config_byte(dev, 0x150, 0x10);
2722 pci_write_config_byte(dev, 0xf9, 0x00);
2723 pci_write_config_byte(dev, 0xfc, 0x01);
2724 pci_write_config_byte(dev, 0xe1, 0x32);
2725 pci_write_config_byte(dev, 0xfc, 0x00);
2726
2727 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2728 }
2729
2730 pci_read_config_byte(dev, 0xCB, &disable);
2731
2732 if (disable & 0x02)
2733 return;
2734
2735 pci_read_config_byte(dev, 0xCA, &write_enable);
2736 pci_write_config_byte(dev, 0xCA, 0x57);
2737 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2738 pci_write_config_byte(dev, 0xCA, write_enable);
2739
2740 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2741 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2742
2743}
2744DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2745DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2746DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2747DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2748DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2749DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2750#endif /*CONFIG_MMC_RICOH_MMC*/
2751
2752#ifdef CONFIG_DMAR_TABLE
2753#define VTUNCERRMSK_REG 0x1ac
2754#define VTD_MSK_SPEC_ERRORS (1 << 31)
2755/*
2756 * This is a quirk for masking vt-d spec defined errors to platform error
2757 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2758 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2759 * on the RAS config settings of the platform) when a vt-d fault happens.
2760 * The resulting SMI caused the system to hang.
2761 *
2762 * VT-d spec related errors are already handled by the VT-d OS code, so no
2763 * need to report the same error through other channels.
2764 */
2765static void vtd_mask_spec_errors(struct pci_dev *dev)
2766{
2767 u32 word;
2768
2769 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2770 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2771}
2772DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2773DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2774#endif
2775
2776static void fixup_ti816x_class(struct pci_dev *dev)
2777{
2778 /* TI 816x devices do not have class code set when in PCIe boot mode */
2779 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2780 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2781}
2782DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2783 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2784
2785/* Some PCIe devices do not work reliably with the claimed maximum
2786 * payload size supported.
2787 */
2788static void fixup_mpss_256(struct pci_dev *dev)
2789{
2790 dev->pcie_mpss = 1; /* 256 bytes */
2791}
2792DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2793 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2794DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2795 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2796DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2797 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2798
2799/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2800 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2801 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2802 * until all of the devices are discovered and buses walked, read completion
2803 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2804 * it is possible to hotplug a device with MPS of 256B.
2805 */
2806static void quirk_intel_mc_errata(struct pci_dev *dev)
2807{
2808 int err;
2809 u16 rcc;
2810
2811 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2812 return;
2813
2814 /* Intel errata specifies bits to change but does not say what they are.
2815 * Keeping them magical until such time as the registers and values can
2816 * be explained.
2817 */
2818 err = pci_read_config_word(dev, 0x48, &rcc);
2819 if (err) {
2820 dev_err(&dev->dev, "Error attempting to read the read "
2821 "completion coalescing register.\n");
2822 return;
2823 }
2824
2825 if (!(rcc & (1 << 10)))
2826 return;
2827
2828 rcc &= ~(1 << 10);
2829
2830 err = pci_write_config_word(dev, 0x48, rcc);
2831 if (err) {
2832 dev_err(&dev->dev, "Error attempting to write the read "
2833 "completion coalescing register.\n");
2834 return;
2835 }
2836
2837 pr_info_once("Read completion coalescing disabled due to hardware "
2838 "errata relating to 256B MPS.\n");
2839}
2840/* Intel 5000 series memory controllers and ports 2-7 */
2841DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2842DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2843DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2844DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2845DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2846DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2847DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2848DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2849DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2850DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2851DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2853DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2855/* Intel 5100 series memory controllers and ports 2-7 */
2856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2857DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2858DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2859DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2861DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2862DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2863DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2865DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2866DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2867
2868
2869/*
2870 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2871 * work around this, query the size it should be configured to by the device and
2872 * modify the resource end to correspond to this new size.
2873 */
2874static void quirk_intel_ntb(struct pci_dev *dev)
2875{
2876 int rc;
2877 u8 val;
2878
2879 rc = pci_read_config_byte(dev, 0x00D0, &val);
2880 if (rc)
2881 return;
2882
2883 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2884
2885 rc = pci_read_config_byte(dev, 0x00D1, &val);
2886 if (rc)
2887 return;
2888
2889 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
2890}
2891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
2892DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
2893
2894static ktime_t fixup_debug_start(struct pci_dev *dev,
2895 void (*fn)(struct pci_dev *dev))
2896{
2897 ktime_t calltime = ktime_set(0, 0);
2898
2899 dev_dbg(&dev->dev, "calling %pF\n", fn);
2900 if (initcall_debug) {
2901 pr_debug("calling %pF @ %i for %s\n",
2902 fn, task_pid_nr(current), dev_name(&dev->dev));
2903 calltime = ktime_get();
2904 }
2905
2906 return calltime;
2907}
2908
2909static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2910 void (*fn)(struct pci_dev *dev))
2911{
2912 ktime_t delta, rettime;
2913 unsigned long long duration;
2914
2915 if (initcall_debug) {
2916 rettime = ktime_get();
2917 delta = ktime_sub(rettime, calltime);
2918 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2919 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2920 fn, duration, dev_name(&dev->dev));
2921 }
2922}
2923
2924/*
2925 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2926 * even though no one is handling them (f.e. i915 driver is never loaded).
2927 * Additionally the interrupt destination is not set up properly
2928 * and the interrupt ends up -somewhere-.
2929 *
2930 * These spurious interrupts are "sticky" and the kernel disables
2931 * the (shared) interrupt line after 100.000+ generated interrupts.
2932 *
2933 * Fix it by disabling the still enabled interrupts.
2934 * This resolves crashes often seen on monitor unplug.
2935 */
2936#define I915_DEIER_REG 0x4400c
2937static void disable_igfx_irq(struct pci_dev *dev)
2938{
2939 void __iomem *regs = pci_iomap(dev, 0, 0);
2940 if (regs == NULL) {
2941 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2942 return;
2943 }
2944
2945 /* Check if any interrupt line is still enabled */
2946 if (readl(regs + I915_DEIER_REG) != 0) {
2947 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2948 "disabling\n");
2949
2950 writel(0, regs + I915_DEIER_REG);
2951 }
2952
2953 pci_iounmap(dev, regs);
2954}
2955DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2956DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2957
2958/*
2959 * PCI devices which are on Intel chips can skip the 10ms delay
2960 * before entering D3 mode.
2961 */
2962static void quirk_remove_d3_delay(struct pci_dev *dev)
2963{
2964 dev->d3_delay = 0;
2965}
2966DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
2967DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
2968DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
2969DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
2970DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
2971DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
2972DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
2973DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
2974DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
2975DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
2976DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
2977DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
2978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
2979DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
2980
2981/*
2982 * Some devices may pass our check in pci_intx_mask_supported if
2983 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
2984 * support this feature.
2985 */
2986static void quirk_broken_intx_masking(struct pci_dev *dev)
2987{
2988 dev->broken_intx_masking = 1;
2989}
2990DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
2991 quirk_broken_intx_masking);
2992DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2993 quirk_broken_intx_masking);
2994
2995static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2996 struct pci_fixup *end)
2997{
2998 ktime_t calltime;
2999
3000 for (; f < end; f++)
3001 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3002 f->class == (u32) PCI_ANY_ID) &&
3003 (f->vendor == dev->vendor ||
3004 f->vendor == (u16) PCI_ANY_ID) &&
3005 (f->device == dev->device ||
3006 f->device == (u16) PCI_ANY_ID)) {
3007 calltime = fixup_debug_start(dev, f->hook);
3008 f->hook(dev);
3009 fixup_debug_report(dev, calltime, f->hook);
3010 }
3011}
3012
3013extern struct pci_fixup __start_pci_fixups_early[];
3014extern struct pci_fixup __end_pci_fixups_early[];
3015extern struct pci_fixup __start_pci_fixups_header[];
3016extern struct pci_fixup __end_pci_fixups_header[];
3017extern struct pci_fixup __start_pci_fixups_final[];
3018extern struct pci_fixup __end_pci_fixups_final[];
3019extern struct pci_fixup __start_pci_fixups_enable[];
3020extern struct pci_fixup __end_pci_fixups_enable[];
3021extern struct pci_fixup __start_pci_fixups_resume[];
3022extern struct pci_fixup __end_pci_fixups_resume[];
3023extern struct pci_fixup __start_pci_fixups_resume_early[];
3024extern struct pci_fixup __end_pci_fixups_resume_early[];
3025extern struct pci_fixup __start_pci_fixups_suspend[];
3026extern struct pci_fixup __end_pci_fixups_suspend[];
3027
3028static bool pci_apply_fixup_final_quirks;
3029
3030void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3031{
3032 struct pci_fixup *start, *end;
3033
3034 switch(pass) {
3035 case pci_fixup_early:
3036 start = __start_pci_fixups_early;
3037 end = __end_pci_fixups_early;
3038 break;
3039
3040 case pci_fixup_header:
3041 start = __start_pci_fixups_header;
3042 end = __end_pci_fixups_header;
3043 break;
3044
3045 case pci_fixup_final:
3046 if (!pci_apply_fixup_final_quirks)
3047 return;
3048 start = __start_pci_fixups_final;
3049 end = __end_pci_fixups_final;
3050 break;
3051
3052 case pci_fixup_enable:
3053 start = __start_pci_fixups_enable;
3054 end = __end_pci_fixups_enable;
3055 break;
3056
3057 case pci_fixup_resume:
3058 start = __start_pci_fixups_resume;
3059 end = __end_pci_fixups_resume;
3060 break;
3061
3062 case pci_fixup_resume_early:
3063 start = __start_pci_fixups_resume_early;
3064 end = __end_pci_fixups_resume_early;
3065 break;
3066
3067 case pci_fixup_suspend:
3068 start = __start_pci_fixups_suspend;
3069 end = __end_pci_fixups_suspend;
3070 break;
3071
3072 default:
3073 /* stupid compiler warning, you would think with an enum... */
3074 return;
3075 }
3076 pci_do_fixups(dev, start, end);
3077}
3078EXPORT_SYMBOL(pci_fixup_device);
3079
3080
3081static int __init pci_apply_final_quirks(void)
3082{
3083 struct pci_dev *dev = NULL;
3084 u8 cls = 0;
3085 u8 tmp;
3086
3087 if (pci_cache_line_size)
3088 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3089 pci_cache_line_size << 2);
3090
3091 pci_apply_fixup_final_quirks = true;
3092 for_each_pci_dev(dev) {
3093 pci_fixup_device(pci_fixup_final, dev);
3094 /*
3095 * If arch hasn't set it explicitly yet, use the CLS
3096 * value shared by all PCI devices. If there's a
3097 * mismatch, fall back to the default value.
3098 */
3099 if (!pci_cache_line_size) {
3100 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3101 if (!cls)
3102 cls = tmp;
3103 if (!tmp || cls == tmp)
3104 continue;
3105
3106 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3107 "using %u bytes\n", cls << 2, tmp << 2,
3108 pci_dfl_cache_line_size << 2);
3109 pci_cache_line_size = pci_dfl_cache_line_size;
3110 }
3111 }
3112
3113 if (!pci_cache_line_size) {
3114 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3115 cls << 2, pci_dfl_cache_line_size << 2);
3116 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3117 }
3118
3119 return 0;
3120}
3121
3122fs_initcall_sync(pci_apply_final_quirks);
3123
3124/*
3125 * Followings are device-specific reset methods which can be used to
3126 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3127 * not available.
3128 */
3129static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3130{
3131 int pos;
3132
3133 /* only implement PCI_CLASS_SERIAL_USB at present */
3134 if (dev->class == PCI_CLASS_SERIAL_USB) {
3135 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3136 if (!pos)
3137 return -ENOTTY;
3138
3139 if (probe)
3140 return 0;
3141
3142 pci_write_config_byte(dev, pos + 0x4, 1);
3143 msleep(100);
3144
3145 return 0;
3146 } else {
3147 return -ENOTTY;
3148 }
3149}
3150
3151static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3152{
3153 /*
3154 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3155 *
3156 * The 82599 supports FLR on VFs, but FLR support is reported only
3157 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3158 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3159 */
3160
3161 if (probe)
3162 return 0;
3163
3164 if (!pci_wait_for_pending_transaction(dev))
3165 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3166
3167 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3168
3169 msleep(100);
3170
3171 return 0;
3172}
3173
3174#include "../gpu/drm/i915/i915_reg.h"
3175#define MSG_CTL 0x45010
3176#define NSDE_PWR_STATE 0xd0100
3177#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3178
3179static int reset_ivb_igd(struct pci_dev *dev, int probe)
3180{
3181 void __iomem *mmio_base;
3182 unsigned long timeout;
3183 u32 val;
3184
3185 if (probe)
3186 return 0;
3187
3188 mmio_base = pci_iomap(dev, 0, 0);
3189 if (!mmio_base)
3190 return -ENOMEM;
3191
3192 iowrite32(0x00000002, mmio_base + MSG_CTL);
3193
3194 /*
3195 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3196 * driver loaded sets the right bits. However, this's a reset and
3197 * the bits have been set by i915 previously, so we clobber
3198 * SOUTH_CHICKEN2 register directly here.
3199 */
3200 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3201
3202 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3203 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3204
3205 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3206 do {
3207 val = ioread32(mmio_base + PCH_PP_STATUS);
3208 if ((val & 0xb0000000) == 0)
3209 goto reset_complete;
3210 msleep(10);
3211 } while (time_before(jiffies, timeout));
3212 dev_warn(&dev->dev, "timeout during reset\n");
3213
3214reset_complete:
3215 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3216
3217 pci_iounmap(dev, mmio_base);
3218 return 0;
3219}
3220
3221/*
3222 * Device-specific reset method for Chelsio T4-based adapters.
3223 */
3224static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3225{
3226 u16 old_command;
3227 u16 msix_flags;
3228
3229 /*
3230 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3231 * that we have no device-specific reset method.
3232 */
3233 if ((dev->device & 0xf000) != 0x4000)
3234 return -ENOTTY;
3235
3236 /*
3237 * If this is the "probe" phase, return 0 indicating that we can
3238 * reset this device.
3239 */
3240 if (probe)
3241 return 0;
3242
3243 /*
3244 * T4 can wedge if there are DMAs in flight within the chip and Bus
3245 * Master has been disabled. We need to have it on till the Function
3246 * Level Reset completes. (BUS_MASTER is disabled in
3247 * pci_reset_function()).
3248 */
3249 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3250 pci_write_config_word(dev, PCI_COMMAND,
3251 old_command | PCI_COMMAND_MASTER);
3252
3253 /*
3254 * Perform the actual device function reset, saving and restoring
3255 * configuration information around the reset.
3256 */
3257 pci_save_state(dev);
3258
3259 /*
3260 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3261 * are disabled when an MSI-X interrupt message needs to be delivered.
3262 * So we briefly re-enable MSI-X interrupts for the duration of the
3263 * FLR. The pci_restore_state() below will restore the original
3264 * MSI-X state.
3265 */
3266 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3267 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3268 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3269 msix_flags |
3270 PCI_MSIX_FLAGS_ENABLE |
3271 PCI_MSIX_FLAGS_MASKALL);
3272
3273 /*
3274 * Start of pcie_flr() code sequence. This reset code is a copy of
3275 * the guts of pcie_flr() because that's not an exported function.
3276 */
3277
3278 if (!pci_wait_for_pending_transaction(dev))
3279 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3280
3281 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3282 msleep(100);
3283
3284 /*
3285 * End of pcie_flr() code sequence.
3286 */
3287
3288 /*
3289 * Restore the configuration information (BAR values, etc.) including
3290 * the original PCI Configuration Space Command word, and return
3291 * success.
3292 */
3293 pci_restore_state(dev);
3294 pci_write_config_word(dev, PCI_COMMAND, old_command);
3295 return 0;
3296}
3297
3298#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3299#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3300#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3301
3302static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3303 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3304 reset_intel_82599_sfp_virtfn },
3305 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3306 reset_ivb_igd },
3307 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3308 reset_ivb_igd },
3309 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3310 reset_intel_generic_dev },
3311 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3312 reset_chelsio_generic_dev },
3313 { 0 }
3314};
3315
3316/*
3317 * These device-specific reset methods are here rather than in a driver
3318 * because when a host assigns a device to a guest VM, the host may need
3319 * to reset the device but probably doesn't have a driver for it.
3320 */
3321int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3322{
3323 const struct pci_dev_reset_methods *i;
3324
3325 for (i = pci_dev_reset_methods; i->reset; i++) {
3326 if ((i->vendor == dev->vendor ||
3327 i->vendor == (u16)PCI_ANY_ID) &&
3328 (i->device == dev->device ||
3329 i->device == (u16)PCI_ANY_ID))
3330 return i->reset(dev, probe);
3331 }
3332
3333 return -ENOTTY;
3334}
3335
3336static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3337{
3338 if (!PCI_FUNC(dev->devfn))
3339 return pci_dev_get(dev);
3340
3341 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3342}
3343
3344static const struct pci_dev_dma_source {
3345 u16 vendor;
3346 u16 device;
3347 struct pci_dev *(*dma_source)(struct pci_dev *dev);
3348} pci_dev_dma_source[] = {
3349 /*
3350 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3351 *
3352 * Some Ricoh devices use the function 0 source ID for DMA on
3353 * other functions of a multifunction device. The DMA devices
3354 * is therefore function 0, which will have implications of the
3355 * iommu grouping of these devices.
3356 */
3357 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3358 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3359 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3360 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3361 { 0 }
3362};
3363
3364/*
3365 * IOMMUs with isolation capabilities need to be programmed with the
3366 * correct source ID of a device. In most cases, the source ID matches
3367 * the device doing the DMA, but sometimes hardware is broken and will
3368 * tag the DMA as being sourced from a different device. This function
3369 * allows that translation. Note that the reference count of the
3370 * returned device is incremented on all paths.
3371 */
3372struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3373{
3374 const struct pci_dev_dma_source *i;
3375
3376 for (i = pci_dev_dma_source; i->dma_source; i++) {
3377 if ((i->vendor == dev->vendor ||
3378 i->vendor == (u16)PCI_ANY_ID) &&
3379 (i->device == dev->device ||
3380 i->device == (u16)PCI_ANY_ID))
3381 return i->dma_source(dev);
3382 }
3383
3384 return pci_dev_get(dev);
3385}
3386
3387/*
3388 * AMD has indicated that the devices below do not support peer-to-peer
3389 * in any system where they are found in the southbridge with an AMD
3390 * IOMMU in the system. Multifunction devices that do not support
3391 * peer-to-peer between functions can claim to support a subset of ACS.
3392 * Such devices effectively enable request redirect (RR) and completion
3393 * redirect (CR) since all transactions are redirected to the upstream
3394 * root complex.
3395 *
3396 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3397 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3398 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3399 *
3400 * 1002:4385 SBx00 SMBus Controller
3401 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3402 * 1002:4383 SBx00 Azalia (Intel HDA)
3403 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3404 * 1002:4384 SBx00 PCI to PCI Bridge
3405 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3406 */
3407static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3408{
3409#ifdef CONFIG_ACPI
3410 struct acpi_table_header *header = NULL;
3411 acpi_status status;
3412
3413 /* Targeting multifunction devices on the SB (appears on root bus) */
3414 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3415 return -ENODEV;
3416
3417 /* The IVRS table describes the AMD IOMMU */
3418 status = acpi_get_table("IVRS", 0, &header);
3419 if (ACPI_FAILURE(status))
3420 return -ENODEV;
3421
3422 /* Filter out flags not applicable to multifunction */
3423 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3424
3425 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3426#else
3427 return -ENODEV;
3428#endif
3429}
3430
3431/*
3432 * Many Intel PCH root ports do provide ACS-like features to disable peer
3433 * transactions and validate bus numbers in requests, but do not provide an
3434 * actual PCIe ACS capability. This is the list of device IDs known to fall
3435 * into that category as provided by Intel in Red Hat bugzilla 1037684.
3436 */
3437static const u16 pci_quirk_intel_pch_acs_ids[] = {
3438 /* Ibexpeak PCH */
3439 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
3440 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
3441 /* Cougarpoint PCH */
3442 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
3443 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
3444 /* Pantherpoint PCH */
3445 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
3446 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
3447 /* Lynxpoint-H PCH */
3448 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
3449 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
3450 /* Lynxpoint-LP PCH */
3451 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
3452 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
3453 /* Wildcat PCH */
3454 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3455 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
3456};
3457
3458static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
3459{
3460 int i;
3461
3462 /* Filter out a few obvious non-matches first */
3463 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
3464 return false;
3465
3466 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
3467 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
3468 return true;
3469
3470 return false;
3471}
3472
3473#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
3474
3475static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
3476{
3477 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
3478 INTEL_PCH_ACS_FLAGS : 0;
3479
3480 if (!pci_quirk_intel_pch_acs_match(dev))
3481 return -ENOTTY;
3482
3483 return acs_flags & ~flags ? 0 : 1;
3484}
3485
3486static const struct pci_dev_acs_enabled {
3487 u16 vendor;
3488 u16 device;
3489 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3490} pci_dev_acs_enabled[] = {
3491 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3492 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3493 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3494 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3495 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3496 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
3497 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
3498 { 0 }
3499};
3500
3501int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3502{
3503 const struct pci_dev_acs_enabled *i;
3504 int ret;
3505
3506 /*
3507 * Allow devices that do not expose standard PCIe ACS capabilities
3508 * or control to indicate their support here. Multi-function express
3509 * devices which do not allow internal peer-to-peer between functions,
3510 * but do not implement PCIe ACS may wish to return true here.
3511 */
3512 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3513 if ((i->vendor == dev->vendor ||
3514 i->vendor == (u16)PCI_ANY_ID) &&
3515 (i->device == dev->device ||
3516 i->device == (u16)PCI_ANY_ID)) {
3517 ret = i->acs_enabled(dev, acs_flags);
3518 if (ret >= 0)
3519 return ret;
3520 }
3521 }
3522
3523 return -ENOTTY;
3524}
3525
3526/* Config space offset of Root Complex Base Address register */
3527#define INTEL_LPC_RCBA_REG 0xf0
3528/* 31:14 RCBA address */
3529#define INTEL_LPC_RCBA_MASK 0xffffc000
3530/* RCBA Enable */
3531#define INTEL_LPC_RCBA_ENABLE (1 << 0)
3532
3533/* Backbone Scratch Pad Register */
3534#define INTEL_BSPR_REG 0x1104
3535/* Backbone Peer Non-Posted Disable */
3536#define INTEL_BSPR_REG_BPNPD (1 << 8)
3537/* Backbone Peer Posted Disable */
3538#define INTEL_BSPR_REG_BPPD (1 << 9)
3539
3540/* Upstream Peer Decode Configuration Register */
3541#define INTEL_UPDCR_REG 0x1114
3542/* 5:0 Peer Decode Enable bits */
3543#define INTEL_UPDCR_REG_MASK 0x3f
3544
3545static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
3546{
3547 u32 rcba, bspr, updcr;
3548 void __iomem *rcba_mem;
3549
3550 /*
3551 * Read the RCBA register from the LPC (D31:F0). PCH root ports
3552 * are D28:F* and therefore get probed before LPC, thus we can't
3553 * use pci_get_slot/pci_read_config_dword here.
3554 */
3555 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
3556 INTEL_LPC_RCBA_REG, &rcba);
3557 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
3558 return -EINVAL;
3559
3560 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
3561 PAGE_ALIGN(INTEL_UPDCR_REG));
3562 if (!rcba_mem)
3563 return -ENOMEM;
3564
3565 /*
3566 * The BSPR can disallow peer cycles, but it's set by soft strap and
3567 * therefore read-only. If both posted and non-posted peer cycles are
3568 * disallowed, we're ok. If either are allowed, then we need to use
3569 * the UPDCR to disable peer decodes for each port. This provides the
3570 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
3571 */
3572 bspr = readl(rcba_mem + INTEL_BSPR_REG);
3573 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
3574 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
3575 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
3576 if (updcr & INTEL_UPDCR_REG_MASK) {
3577 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
3578 updcr &= ~INTEL_UPDCR_REG_MASK;
3579 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
3580 }
3581 }
3582
3583 iounmap(rcba_mem);
3584 return 0;
3585}
3586
3587/* Miscellaneous Port Configuration register */
3588#define INTEL_MPC_REG 0xd8
3589/* MPC: Invalid Receive Bus Number Check Enable */
3590#define INTEL_MPC_REG_IRBNCE (1 << 26)
3591
3592static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
3593{
3594 u32 mpc;
3595
3596 /*
3597 * When enabled, the IRBNCE bit of the MPC register enables the
3598 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
3599 * ensures that requester IDs fall within the bus number range
3600 * of the bridge. Enable if not already.
3601 */
3602 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
3603 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
3604 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
3605 mpc |= INTEL_MPC_REG_IRBNCE;
3606 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
3607 }
3608}
3609
3610static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
3611{
3612 if (!pci_quirk_intel_pch_acs_match(dev))
3613 return -ENOTTY;
3614
3615 if (pci_quirk_enable_intel_lpc_acs(dev)) {
3616 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
3617 return 0;
3618 }
3619
3620 pci_quirk_enable_intel_rp_mpc_acs(dev);
3621
3622 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
3623
3624 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
3625
3626 return 0;
3627}
3628
3629static const struct pci_dev_enable_acs {
3630 u16 vendor;
3631 u16 device;
3632 int (*enable_acs)(struct pci_dev *dev);
3633} pci_dev_enable_acs[] = {
3634 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
3635 { 0 }
3636};
3637
3638void pci_dev_specific_enable_acs(struct pci_dev *dev)
3639{
3640 const struct pci_dev_enable_acs *i;
3641 int ret;
3642
3643 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
3644 if ((i->vendor == dev->vendor ||
3645 i->vendor == (u16)PCI_ANY_ID) &&
3646 (i->device == dev->device ||
3647 i->device == (u16)PCI_ANY_ID)) {
3648 ret = i->enable_acs(dev);
3649 if (ret >= 0)
3650 return;
3651 }
3652 }
3653}