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1/*
2 * intel_pstate.c: Native P state management for Intel processors
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15#include <linux/kernel.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/ktime.h>
19#include <linux/hrtimer.h>
20#include <linux/tick.h>
21#include <linux/slab.h>
22#include <linux/sched/cpufreq.h>
23#include <linux/list.h>
24#include <linux/cpu.h>
25#include <linux/cpufreq.h>
26#include <linux/sysfs.h>
27#include <linux/types.h>
28#include <linux/fs.h>
29#include <linux/acpi.h>
30#include <linux/vmalloc.h>
31#include <trace/events/power.h>
32
33#include <asm/div64.h>
34#include <asm/msr.h>
35#include <asm/cpu_device_id.h>
36#include <asm/cpufeature.h>
37#include <asm/intel-family.h>
38
39#define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
40
41#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
42#define INTEL_CPUFREQ_TRANSITION_DELAY 500
43
44#ifdef CONFIG_ACPI
45#include <acpi/processor.h>
46#include <acpi/cppc_acpi.h>
47#endif
48
49#define FRAC_BITS 8
50#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51#define fp_toint(X) ((X) >> FRAC_BITS)
52
53#define EXT_BITS 6
54#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
55#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
56#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
57
58static inline int32_t mul_fp(int32_t x, int32_t y)
59{
60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
61}
62
63static inline int32_t div_fp(s64 x, s64 y)
64{
65 return div64_s64((int64_t)x << FRAC_BITS, y);
66}
67
68static inline int ceiling_fp(int32_t x)
69{
70 int mask, ret;
71
72 ret = fp_toint(x);
73 mask = (1 << FRAC_BITS) - 1;
74 if (x & mask)
75 ret += 1;
76 return ret;
77}
78
79static inline int32_t percent_fp(int percent)
80{
81 return div_fp(percent, 100);
82}
83
84static inline u64 mul_ext_fp(u64 x, u64 y)
85{
86 return (x * y) >> EXT_FRAC_BITS;
87}
88
89static inline u64 div_ext_fp(u64 x, u64 y)
90{
91 return div64_u64(x << EXT_FRAC_BITS, y);
92}
93
94static inline int32_t percent_ext_fp(int percent)
95{
96 return div_ext_fp(percent, 100);
97}
98
99/**
100 * struct sample - Store performance sample
101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
102 * performance during last sample period
103 * @busy_scaled: Scaled busy value which is used to calculate next
104 * P state. This can be different than core_avg_perf
105 * to account for cpu idle period
106 * @aperf: Difference of actual performance frequency clock count
107 * read from APERF MSR between last and current sample
108 * @mperf: Difference of maximum performance frequency clock count
109 * read from MPERF MSR between last and current sample
110 * @tsc: Difference of time stamp counter between last and
111 * current sample
112 * @time: Current time from scheduler
113 *
114 * This structure is used in the cpudata structure to store performance sample
115 * data for choosing next P State.
116 */
117struct sample {
118 int32_t core_avg_perf;
119 int32_t busy_scaled;
120 u64 aperf;
121 u64 mperf;
122 u64 tsc;
123 u64 time;
124};
125
126/**
127 * struct pstate_data - Store P state data
128 * @current_pstate: Current requested P state
129 * @min_pstate: Min P state possible for this platform
130 * @max_pstate: Max P state possible for this platform
131 * @max_pstate_physical:This is physical Max P state for a processor
132 * This can be higher than the max_pstate which can
133 * be limited by platform thermal design power limits
134 * @scaling: Scaling factor to convert frequency to cpufreq
135 * frequency units
136 * @turbo_pstate: Max Turbo P state possible for this platform
137 * @max_freq: @max_pstate frequency in cpufreq units
138 * @turbo_freq: @turbo_pstate frequency in cpufreq units
139 *
140 * Stores the per cpu model P state limits and current P state.
141 */
142struct pstate_data {
143 int current_pstate;
144 int min_pstate;
145 int max_pstate;
146 int max_pstate_physical;
147 int scaling;
148 int turbo_pstate;
149 unsigned int max_freq;
150 unsigned int turbo_freq;
151};
152
153/**
154 * struct vid_data - Stores voltage information data
155 * @min: VID data for this platform corresponding to
156 * the lowest P state
157 * @max: VID data corresponding to the highest P State.
158 * @turbo: VID data for turbo P state
159 * @ratio: Ratio of (vid max - vid min) /
160 * (max P state - Min P State)
161 *
162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
163 * This data is used in Atom platforms, where in addition to target P state,
164 * the voltage data needs to be specified to select next P State.
165 */
166struct vid_data {
167 int min;
168 int max;
169 int turbo;
170 int32_t ratio;
171};
172
173/**
174 * struct global_params - Global parameters, mostly tunable via sysfs.
175 * @no_turbo: Whether or not to use turbo P-states.
176 * @turbo_disabled: Whethet or not turbo P-states are available at all,
177 * based on the MSR_IA32_MISC_ENABLE value and whether or
178 * not the maximum reported turbo P-state is different from
179 * the maximum reported non-turbo one.
180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
181 * P-state capacity.
182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
183 * P-state capacity.
184 */
185struct global_params {
186 bool no_turbo;
187 bool turbo_disabled;
188 int max_perf_pct;
189 int min_perf_pct;
190};
191
192/**
193 * struct cpudata - Per CPU instance data storage
194 * @cpu: CPU number for this instance data
195 * @policy: CPUFreq policy value
196 * @update_util: CPUFreq utility callback information
197 * @update_util_set: CPUFreq utility callback is set
198 * @iowait_boost: iowait-related boost fraction
199 * @last_update: Time of the last update.
200 * @pstate: Stores P state limits for this CPU
201 * @vid: Stores VID limits for this CPU
202 * @last_sample_time: Last Sample time
203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
204 * This shift is a multiplier to mperf delta to
205 * calculate CPU busy.
206 * @prev_aperf: Last APERF value read from APERF MSR
207 * @prev_mperf: Last MPERF value read from MPERF MSR
208 * @prev_tsc: Last timestamp counter (TSC) value
209 * @prev_cummulative_iowait: IO Wait time difference from last and
210 * current sample
211 * @sample: Storage for storing last Sample data
212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
214 * @acpi_perf_data: Stores ACPI perf information read from _PSS
215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
216 * @epp_powersave: Last saved HWP energy performance preference
217 * (EPP) or energy performance bias (EPB),
218 * when policy switched to performance
219 * @epp_policy: Last saved policy used to set EPP/EPB
220 * @epp_default: Power on default HWP energy performance
221 * preference/bias
222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
223 * operation
224 *
225 * This structure stores per CPU instance data for all CPUs.
226 */
227struct cpudata {
228 int cpu;
229
230 unsigned int policy;
231 struct update_util_data update_util;
232 bool update_util_set;
233
234 struct pstate_data pstate;
235 struct vid_data vid;
236
237 u64 last_update;
238 u64 last_sample_time;
239 u64 aperf_mperf_shift;
240 u64 prev_aperf;
241 u64 prev_mperf;
242 u64 prev_tsc;
243 u64 prev_cummulative_iowait;
244 struct sample sample;
245 int32_t min_perf_ratio;
246 int32_t max_perf_ratio;
247#ifdef CONFIG_ACPI
248 struct acpi_processor_performance acpi_perf_data;
249 bool valid_pss_table;
250#endif
251 unsigned int iowait_boost;
252 s16 epp_powersave;
253 s16 epp_policy;
254 s16 epp_default;
255 s16 epp_saved;
256};
257
258static struct cpudata **all_cpu_data;
259
260/**
261 * struct pstate_funcs - Per CPU model specific callbacks
262 * @get_max: Callback to get maximum non turbo effective P state
263 * @get_max_physical: Callback to get maximum non turbo physical P state
264 * @get_min: Callback to get minimum P state
265 * @get_turbo: Callback to get turbo P state
266 * @get_scaling: Callback to get frequency scaling factor
267 * @get_val: Callback to convert P state to actual MSR write value
268 * @get_vid: Callback to get VID data for Atom platforms
269 *
270 * Core and Atom CPU models have different way to get P State limits. This
271 * structure is used to store those callbacks.
272 */
273struct pstate_funcs {
274 int (*get_max)(void);
275 int (*get_max_physical)(void);
276 int (*get_min)(void);
277 int (*get_turbo)(void);
278 int (*get_scaling)(void);
279 int (*get_aperf_mperf_shift)(void);
280 u64 (*get_val)(struct cpudata*, int pstate);
281 void (*get_vid)(struct cpudata *);
282};
283
284static struct pstate_funcs pstate_funcs __read_mostly;
285
286static int hwp_active __read_mostly;
287static bool per_cpu_limits __read_mostly;
288
289static struct cpufreq_driver *intel_pstate_driver __read_mostly;
290
291#ifdef CONFIG_ACPI
292static bool acpi_ppc;
293#endif
294
295static struct global_params global;
296
297static DEFINE_MUTEX(intel_pstate_driver_lock);
298static DEFINE_MUTEX(intel_pstate_limits_lock);
299
300#ifdef CONFIG_ACPI
301
302static bool intel_pstate_get_ppc_enable_status(void)
303{
304 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
305 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
306 return true;
307
308 return acpi_ppc;
309}
310
311#ifdef CONFIG_ACPI_CPPC_LIB
312
313/* The work item is needed to avoid CPU hotplug locking issues */
314static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
315{
316 sched_set_itmt_support();
317}
318
319static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
320
321static void intel_pstate_set_itmt_prio(int cpu)
322{
323 struct cppc_perf_caps cppc_perf;
324 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
325 int ret;
326
327 ret = cppc_get_perf_caps(cpu, &cppc_perf);
328 if (ret)
329 return;
330
331 /*
332 * The priorities can be set regardless of whether or not
333 * sched_set_itmt_support(true) has been called and it is valid to
334 * update them at any time after it has been called.
335 */
336 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
337
338 if (max_highest_perf <= min_highest_perf) {
339 if (cppc_perf.highest_perf > max_highest_perf)
340 max_highest_perf = cppc_perf.highest_perf;
341
342 if (cppc_perf.highest_perf < min_highest_perf)
343 min_highest_perf = cppc_perf.highest_perf;
344
345 if (max_highest_perf > min_highest_perf) {
346 /*
347 * This code can be run during CPU online under the
348 * CPU hotplug locks, so sched_set_itmt_support()
349 * cannot be called from here. Queue up a work item
350 * to invoke it.
351 */
352 schedule_work(&sched_itmt_work);
353 }
354 }
355}
356#else
357static void intel_pstate_set_itmt_prio(int cpu)
358{
359}
360#endif
361
362static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
363{
364 struct cpudata *cpu;
365 int ret;
366 int i;
367
368 if (hwp_active) {
369 intel_pstate_set_itmt_prio(policy->cpu);
370 return;
371 }
372
373 if (!intel_pstate_get_ppc_enable_status())
374 return;
375
376 cpu = all_cpu_data[policy->cpu];
377
378 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
379 policy->cpu);
380 if (ret)
381 return;
382
383 /*
384 * Check if the control value in _PSS is for PERF_CTL MSR, which should
385 * guarantee that the states returned by it map to the states in our
386 * list directly.
387 */
388 if (cpu->acpi_perf_data.control_register.space_id !=
389 ACPI_ADR_SPACE_FIXED_HARDWARE)
390 goto err;
391
392 /*
393 * If there is only one entry _PSS, simply ignore _PSS and continue as
394 * usual without taking _PSS into account
395 */
396 if (cpu->acpi_perf_data.state_count < 2)
397 goto err;
398
399 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
400 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
401 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
402 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
403 (u32) cpu->acpi_perf_data.states[i].core_frequency,
404 (u32) cpu->acpi_perf_data.states[i].power,
405 (u32) cpu->acpi_perf_data.states[i].control);
406 }
407
408 /*
409 * The _PSS table doesn't contain whole turbo frequency range.
410 * This just contains +1 MHZ above the max non turbo frequency,
411 * with control value corresponding to max turbo ratio. But
412 * when cpufreq set policy is called, it will call with this
413 * max frequency, which will cause a reduced performance as
414 * this driver uses real max turbo frequency as the max
415 * frequency. So correct this frequency in _PSS table to
416 * correct max turbo frequency based on the turbo state.
417 * Also need to convert to MHz as _PSS freq is in MHz.
418 */
419 if (!global.turbo_disabled)
420 cpu->acpi_perf_data.states[0].core_frequency =
421 policy->cpuinfo.max_freq / 1000;
422 cpu->valid_pss_table = true;
423 pr_debug("_PPC limits will be enforced\n");
424
425 return;
426
427 err:
428 cpu->valid_pss_table = false;
429 acpi_processor_unregister_performance(policy->cpu);
430}
431
432static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
433{
434 struct cpudata *cpu;
435
436 cpu = all_cpu_data[policy->cpu];
437 if (!cpu->valid_pss_table)
438 return;
439
440 acpi_processor_unregister_performance(policy->cpu);
441}
442#else
443static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
444{
445}
446
447static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
448{
449}
450#endif
451
452static inline void update_turbo_state(void)
453{
454 u64 misc_en;
455 struct cpudata *cpu;
456
457 cpu = all_cpu_data[0];
458 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
459 global.turbo_disabled =
460 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
461 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
462}
463
464static int min_perf_pct_min(void)
465{
466 struct cpudata *cpu = all_cpu_data[0];
467 int turbo_pstate = cpu->pstate.turbo_pstate;
468
469 return turbo_pstate ?
470 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
471}
472
473static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
474{
475 u64 epb;
476 int ret;
477
478 if (!static_cpu_has(X86_FEATURE_EPB))
479 return -ENXIO;
480
481 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
482 if (ret)
483 return (s16)ret;
484
485 return (s16)(epb & 0x0f);
486}
487
488static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
489{
490 s16 epp;
491
492 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
493 /*
494 * When hwp_req_data is 0, means that caller didn't read
495 * MSR_HWP_REQUEST, so need to read and get EPP.
496 */
497 if (!hwp_req_data) {
498 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
499 &hwp_req_data);
500 if (epp)
501 return epp;
502 }
503 epp = (hwp_req_data >> 24) & 0xff;
504 } else {
505 /* When there is no EPP present, HWP uses EPB settings */
506 epp = intel_pstate_get_epb(cpu_data);
507 }
508
509 return epp;
510}
511
512static int intel_pstate_set_epb(int cpu, s16 pref)
513{
514 u64 epb;
515 int ret;
516
517 if (!static_cpu_has(X86_FEATURE_EPB))
518 return -ENXIO;
519
520 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
521 if (ret)
522 return ret;
523
524 epb = (epb & ~0x0f) | pref;
525 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
526
527 return 0;
528}
529
530/*
531 * EPP/EPB display strings corresponding to EPP index in the
532 * energy_perf_strings[]
533 * index String
534 *-------------------------------------
535 * 0 default
536 * 1 performance
537 * 2 balance_performance
538 * 3 balance_power
539 * 4 power
540 */
541static const char * const energy_perf_strings[] = {
542 "default",
543 "performance",
544 "balance_performance",
545 "balance_power",
546 "power",
547 NULL
548};
549static const unsigned int epp_values[] = {
550 HWP_EPP_PERFORMANCE,
551 HWP_EPP_BALANCE_PERFORMANCE,
552 HWP_EPP_BALANCE_POWERSAVE,
553 HWP_EPP_POWERSAVE
554};
555
556static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
557{
558 s16 epp;
559 int index = -EINVAL;
560
561 epp = intel_pstate_get_epp(cpu_data, 0);
562 if (epp < 0)
563 return epp;
564
565 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
566 if (epp == HWP_EPP_PERFORMANCE)
567 return 1;
568 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
569 return 2;
570 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
571 return 3;
572 else
573 return 4;
574 } else if (static_cpu_has(X86_FEATURE_EPB)) {
575 /*
576 * Range:
577 * 0x00-0x03 : Performance
578 * 0x04-0x07 : Balance performance
579 * 0x08-0x0B : Balance power
580 * 0x0C-0x0F : Power
581 * The EPB is a 4 bit value, but our ranges restrict the
582 * value which can be set. Here only using top two bits
583 * effectively.
584 */
585 index = (epp >> 2) + 1;
586 }
587
588 return index;
589}
590
591static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
592 int pref_index)
593{
594 int epp = -EINVAL;
595 int ret;
596
597 if (!pref_index)
598 epp = cpu_data->epp_default;
599
600 mutex_lock(&intel_pstate_limits_lock);
601
602 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
603 u64 value;
604
605 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
606 if (ret)
607 goto return_pref;
608
609 value &= ~GENMASK_ULL(31, 24);
610
611 if (epp == -EINVAL)
612 epp = epp_values[pref_index - 1];
613
614 value |= (u64)epp << 24;
615 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
616 } else {
617 if (epp == -EINVAL)
618 epp = (pref_index - 1) << 2;
619 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
620 }
621return_pref:
622 mutex_unlock(&intel_pstate_limits_lock);
623
624 return ret;
625}
626
627static ssize_t show_energy_performance_available_preferences(
628 struct cpufreq_policy *policy, char *buf)
629{
630 int i = 0;
631 int ret = 0;
632
633 while (energy_perf_strings[i] != NULL)
634 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
635
636 ret += sprintf(&buf[ret], "\n");
637
638 return ret;
639}
640
641cpufreq_freq_attr_ro(energy_performance_available_preferences);
642
643static ssize_t store_energy_performance_preference(
644 struct cpufreq_policy *policy, const char *buf, size_t count)
645{
646 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
647 char str_preference[21];
648 int ret, i = 0;
649
650 ret = sscanf(buf, "%20s", str_preference);
651 if (ret != 1)
652 return -EINVAL;
653
654 while (energy_perf_strings[i] != NULL) {
655 if (!strcmp(str_preference, energy_perf_strings[i])) {
656 intel_pstate_set_energy_pref_index(cpu_data, i);
657 return count;
658 }
659 ++i;
660 }
661
662 return -EINVAL;
663}
664
665static ssize_t show_energy_performance_preference(
666 struct cpufreq_policy *policy, char *buf)
667{
668 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
669 int preference;
670
671 preference = intel_pstate_get_energy_pref_index(cpu_data);
672 if (preference < 0)
673 return preference;
674
675 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
676}
677
678cpufreq_freq_attr_rw(energy_performance_preference);
679
680static struct freq_attr *hwp_cpufreq_attrs[] = {
681 &energy_performance_preference,
682 &energy_performance_available_preferences,
683 NULL,
684};
685
686static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
687 int *current_max)
688{
689 u64 cap;
690
691 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
692 if (global.no_turbo)
693 *current_max = HWP_GUARANTEED_PERF(cap);
694 else
695 *current_max = HWP_HIGHEST_PERF(cap);
696
697 *phy_max = HWP_HIGHEST_PERF(cap);
698}
699
700static void intel_pstate_hwp_set(unsigned int cpu)
701{
702 struct cpudata *cpu_data = all_cpu_data[cpu];
703 int max, min;
704 u64 value;
705 s16 epp;
706
707 max = cpu_data->max_perf_ratio;
708 min = cpu_data->min_perf_ratio;
709
710 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
711 min = max;
712
713 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
714
715 value &= ~HWP_MIN_PERF(~0L);
716 value |= HWP_MIN_PERF(min);
717
718 value &= ~HWP_MAX_PERF(~0L);
719 value |= HWP_MAX_PERF(max);
720
721 if (cpu_data->epp_policy == cpu_data->policy)
722 goto skip_epp;
723
724 cpu_data->epp_policy = cpu_data->policy;
725
726 if (cpu_data->epp_saved >= 0) {
727 epp = cpu_data->epp_saved;
728 cpu_data->epp_saved = -EINVAL;
729 goto update_epp;
730 }
731
732 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
733 epp = intel_pstate_get_epp(cpu_data, value);
734 cpu_data->epp_powersave = epp;
735 /* If EPP read was failed, then don't try to write */
736 if (epp < 0)
737 goto skip_epp;
738
739 epp = 0;
740 } else {
741 /* skip setting EPP, when saved value is invalid */
742 if (cpu_data->epp_powersave < 0)
743 goto skip_epp;
744
745 /*
746 * No need to restore EPP when it is not zero. This
747 * means:
748 * - Policy is not changed
749 * - user has manually changed
750 * - Error reading EPB
751 */
752 epp = intel_pstate_get_epp(cpu_data, value);
753 if (epp)
754 goto skip_epp;
755
756 epp = cpu_data->epp_powersave;
757 }
758update_epp:
759 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
760 value &= ~GENMASK_ULL(31, 24);
761 value |= (u64)epp << 24;
762 } else {
763 intel_pstate_set_epb(cpu, epp);
764 }
765skip_epp:
766 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
767}
768
769static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
770{
771 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
772
773 if (!hwp_active)
774 return 0;
775
776 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
777
778 return 0;
779}
780
781static void intel_pstate_hwp_enable(struct cpudata *cpudata);
782
783static int intel_pstate_resume(struct cpufreq_policy *policy)
784{
785 if (!hwp_active)
786 return 0;
787
788 mutex_lock(&intel_pstate_limits_lock);
789
790 if (policy->cpu == 0)
791 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
792
793 all_cpu_data[policy->cpu]->epp_policy = 0;
794 intel_pstate_hwp_set(policy->cpu);
795
796 mutex_unlock(&intel_pstate_limits_lock);
797
798 return 0;
799}
800
801static void intel_pstate_update_policies(void)
802{
803 int cpu;
804
805 for_each_possible_cpu(cpu)
806 cpufreq_update_policy(cpu);
807}
808
809/************************** sysfs begin ************************/
810#define show_one(file_name, object) \
811 static ssize_t show_##file_name \
812 (struct kobject *kobj, struct attribute *attr, char *buf) \
813 { \
814 return sprintf(buf, "%u\n", global.object); \
815 }
816
817static ssize_t intel_pstate_show_status(char *buf);
818static int intel_pstate_update_status(const char *buf, size_t size);
819
820static ssize_t show_status(struct kobject *kobj,
821 struct attribute *attr, char *buf)
822{
823 ssize_t ret;
824
825 mutex_lock(&intel_pstate_driver_lock);
826 ret = intel_pstate_show_status(buf);
827 mutex_unlock(&intel_pstate_driver_lock);
828
829 return ret;
830}
831
832static ssize_t store_status(struct kobject *a, struct attribute *b,
833 const char *buf, size_t count)
834{
835 char *p = memchr(buf, '\n', count);
836 int ret;
837
838 mutex_lock(&intel_pstate_driver_lock);
839 ret = intel_pstate_update_status(buf, p ? p - buf : count);
840 mutex_unlock(&intel_pstate_driver_lock);
841
842 return ret < 0 ? ret : count;
843}
844
845static ssize_t show_turbo_pct(struct kobject *kobj,
846 struct attribute *attr, char *buf)
847{
848 struct cpudata *cpu;
849 int total, no_turbo, turbo_pct;
850 uint32_t turbo_fp;
851
852 mutex_lock(&intel_pstate_driver_lock);
853
854 if (!intel_pstate_driver) {
855 mutex_unlock(&intel_pstate_driver_lock);
856 return -EAGAIN;
857 }
858
859 cpu = all_cpu_data[0];
860
861 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
862 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
863 turbo_fp = div_fp(no_turbo, total);
864 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
865
866 mutex_unlock(&intel_pstate_driver_lock);
867
868 return sprintf(buf, "%u\n", turbo_pct);
869}
870
871static ssize_t show_num_pstates(struct kobject *kobj,
872 struct attribute *attr, char *buf)
873{
874 struct cpudata *cpu;
875 int total;
876
877 mutex_lock(&intel_pstate_driver_lock);
878
879 if (!intel_pstate_driver) {
880 mutex_unlock(&intel_pstate_driver_lock);
881 return -EAGAIN;
882 }
883
884 cpu = all_cpu_data[0];
885 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
886
887 mutex_unlock(&intel_pstate_driver_lock);
888
889 return sprintf(buf, "%u\n", total);
890}
891
892static ssize_t show_no_turbo(struct kobject *kobj,
893 struct attribute *attr, char *buf)
894{
895 ssize_t ret;
896
897 mutex_lock(&intel_pstate_driver_lock);
898
899 if (!intel_pstate_driver) {
900 mutex_unlock(&intel_pstate_driver_lock);
901 return -EAGAIN;
902 }
903
904 update_turbo_state();
905 if (global.turbo_disabled)
906 ret = sprintf(buf, "%u\n", global.turbo_disabled);
907 else
908 ret = sprintf(buf, "%u\n", global.no_turbo);
909
910 mutex_unlock(&intel_pstate_driver_lock);
911
912 return ret;
913}
914
915static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
916 const char *buf, size_t count)
917{
918 unsigned int input;
919 int ret;
920
921 ret = sscanf(buf, "%u", &input);
922 if (ret != 1)
923 return -EINVAL;
924
925 mutex_lock(&intel_pstate_driver_lock);
926
927 if (!intel_pstate_driver) {
928 mutex_unlock(&intel_pstate_driver_lock);
929 return -EAGAIN;
930 }
931
932 mutex_lock(&intel_pstate_limits_lock);
933
934 update_turbo_state();
935 if (global.turbo_disabled) {
936 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
937 mutex_unlock(&intel_pstate_limits_lock);
938 mutex_unlock(&intel_pstate_driver_lock);
939 return -EPERM;
940 }
941
942 global.no_turbo = clamp_t(int, input, 0, 1);
943
944 if (global.no_turbo) {
945 struct cpudata *cpu = all_cpu_data[0];
946 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
947
948 /* Squash the global minimum into the permitted range. */
949 if (global.min_perf_pct > pct)
950 global.min_perf_pct = pct;
951 }
952
953 mutex_unlock(&intel_pstate_limits_lock);
954
955 intel_pstate_update_policies();
956
957 mutex_unlock(&intel_pstate_driver_lock);
958
959 return count;
960}
961
962static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
963 const char *buf, size_t count)
964{
965 unsigned int input;
966 int ret;
967
968 ret = sscanf(buf, "%u", &input);
969 if (ret != 1)
970 return -EINVAL;
971
972 mutex_lock(&intel_pstate_driver_lock);
973
974 if (!intel_pstate_driver) {
975 mutex_unlock(&intel_pstate_driver_lock);
976 return -EAGAIN;
977 }
978
979 mutex_lock(&intel_pstate_limits_lock);
980
981 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
982
983 mutex_unlock(&intel_pstate_limits_lock);
984
985 intel_pstate_update_policies();
986
987 mutex_unlock(&intel_pstate_driver_lock);
988
989 return count;
990}
991
992static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
993 const char *buf, size_t count)
994{
995 unsigned int input;
996 int ret;
997
998 ret = sscanf(buf, "%u", &input);
999 if (ret != 1)
1000 return -EINVAL;
1001
1002 mutex_lock(&intel_pstate_driver_lock);
1003
1004 if (!intel_pstate_driver) {
1005 mutex_unlock(&intel_pstate_driver_lock);
1006 return -EAGAIN;
1007 }
1008
1009 mutex_lock(&intel_pstate_limits_lock);
1010
1011 global.min_perf_pct = clamp_t(int, input,
1012 min_perf_pct_min(), global.max_perf_pct);
1013
1014 mutex_unlock(&intel_pstate_limits_lock);
1015
1016 intel_pstate_update_policies();
1017
1018 mutex_unlock(&intel_pstate_driver_lock);
1019
1020 return count;
1021}
1022
1023show_one(max_perf_pct, max_perf_pct);
1024show_one(min_perf_pct, min_perf_pct);
1025
1026define_one_global_rw(status);
1027define_one_global_rw(no_turbo);
1028define_one_global_rw(max_perf_pct);
1029define_one_global_rw(min_perf_pct);
1030define_one_global_ro(turbo_pct);
1031define_one_global_ro(num_pstates);
1032
1033static struct attribute *intel_pstate_attributes[] = {
1034 &status.attr,
1035 &no_turbo.attr,
1036 &turbo_pct.attr,
1037 &num_pstates.attr,
1038 NULL
1039};
1040
1041static const struct attribute_group intel_pstate_attr_group = {
1042 .attrs = intel_pstate_attributes,
1043};
1044
1045static void __init intel_pstate_sysfs_expose_params(void)
1046{
1047 struct kobject *intel_pstate_kobject;
1048 int rc;
1049
1050 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1051 &cpu_subsys.dev_root->kobj);
1052 if (WARN_ON(!intel_pstate_kobject))
1053 return;
1054
1055 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1056 if (WARN_ON(rc))
1057 return;
1058
1059 /*
1060 * If per cpu limits are enforced there are no global limits, so
1061 * return without creating max/min_perf_pct attributes
1062 */
1063 if (per_cpu_limits)
1064 return;
1065
1066 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1067 WARN_ON(rc);
1068
1069 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1070 WARN_ON(rc);
1071
1072}
1073/************************** sysfs end ************************/
1074
1075static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1076{
1077 /* First disable HWP notification interrupt as we don't process them */
1078 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1079 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1080
1081 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1082 cpudata->epp_policy = 0;
1083 if (cpudata->epp_default == -EINVAL)
1084 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1085}
1086
1087#define MSR_IA32_POWER_CTL_BIT_EE 19
1088
1089/* Disable energy efficiency optimization */
1090static void intel_pstate_disable_ee(int cpu)
1091{
1092 u64 power_ctl;
1093 int ret;
1094
1095 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1096 if (ret)
1097 return;
1098
1099 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1100 pr_info("Disabling energy efficiency optimization\n");
1101 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1102 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1103 }
1104}
1105
1106static int atom_get_min_pstate(void)
1107{
1108 u64 value;
1109
1110 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1111 return (value >> 8) & 0x7F;
1112}
1113
1114static int atom_get_max_pstate(void)
1115{
1116 u64 value;
1117
1118 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1119 return (value >> 16) & 0x7F;
1120}
1121
1122static int atom_get_turbo_pstate(void)
1123{
1124 u64 value;
1125
1126 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1127 return value & 0x7F;
1128}
1129
1130static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1131{
1132 u64 val;
1133 int32_t vid_fp;
1134 u32 vid;
1135
1136 val = (u64)pstate << 8;
1137 if (global.no_turbo && !global.turbo_disabled)
1138 val |= (u64)1 << 32;
1139
1140 vid_fp = cpudata->vid.min + mul_fp(
1141 int_tofp(pstate - cpudata->pstate.min_pstate),
1142 cpudata->vid.ratio);
1143
1144 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1145 vid = ceiling_fp(vid_fp);
1146
1147 if (pstate > cpudata->pstate.max_pstate)
1148 vid = cpudata->vid.turbo;
1149
1150 return val | vid;
1151}
1152
1153static int silvermont_get_scaling(void)
1154{
1155 u64 value;
1156 int i;
1157 /* Defined in Table 35-6 from SDM (Sept 2015) */
1158 static int silvermont_freq_table[] = {
1159 83300, 100000, 133300, 116700, 80000};
1160
1161 rdmsrl(MSR_FSB_FREQ, value);
1162 i = value & 0x7;
1163 WARN_ON(i > 4);
1164
1165 return silvermont_freq_table[i];
1166}
1167
1168static int airmont_get_scaling(void)
1169{
1170 u64 value;
1171 int i;
1172 /* Defined in Table 35-10 from SDM (Sept 2015) */
1173 static int airmont_freq_table[] = {
1174 83300, 100000, 133300, 116700, 80000,
1175 93300, 90000, 88900, 87500};
1176
1177 rdmsrl(MSR_FSB_FREQ, value);
1178 i = value & 0xF;
1179 WARN_ON(i > 8);
1180
1181 return airmont_freq_table[i];
1182}
1183
1184static void atom_get_vid(struct cpudata *cpudata)
1185{
1186 u64 value;
1187
1188 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1189 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1190 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1191 cpudata->vid.ratio = div_fp(
1192 cpudata->vid.max - cpudata->vid.min,
1193 int_tofp(cpudata->pstate.max_pstate -
1194 cpudata->pstate.min_pstate));
1195
1196 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1197 cpudata->vid.turbo = value & 0x7f;
1198}
1199
1200static int core_get_min_pstate(void)
1201{
1202 u64 value;
1203
1204 rdmsrl(MSR_PLATFORM_INFO, value);
1205 return (value >> 40) & 0xFF;
1206}
1207
1208static int core_get_max_pstate_physical(void)
1209{
1210 u64 value;
1211
1212 rdmsrl(MSR_PLATFORM_INFO, value);
1213 return (value >> 8) & 0xFF;
1214}
1215
1216static int core_get_tdp_ratio(u64 plat_info)
1217{
1218 /* Check how many TDP levels present */
1219 if (plat_info & 0x600000000) {
1220 u64 tdp_ctrl;
1221 u64 tdp_ratio;
1222 int tdp_msr;
1223 int err;
1224
1225 /* Get the TDP level (0, 1, 2) to get ratios */
1226 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1227 if (err)
1228 return err;
1229
1230 /* TDP MSR are continuous starting at 0x648 */
1231 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1232 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1233 if (err)
1234 return err;
1235
1236 /* For level 1 and 2, bits[23:16] contain the ratio */
1237 if (tdp_ctrl & 0x03)
1238 tdp_ratio >>= 16;
1239
1240 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1241 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1242
1243 return (int)tdp_ratio;
1244 }
1245
1246 return -ENXIO;
1247}
1248
1249static int core_get_max_pstate(void)
1250{
1251 u64 tar;
1252 u64 plat_info;
1253 int max_pstate;
1254 int tdp_ratio;
1255 int err;
1256
1257 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1258 max_pstate = (plat_info >> 8) & 0xFF;
1259
1260 tdp_ratio = core_get_tdp_ratio(plat_info);
1261 if (tdp_ratio <= 0)
1262 return max_pstate;
1263
1264 if (hwp_active) {
1265 /* Turbo activation ratio is not used on HWP platforms */
1266 return tdp_ratio;
1267 }
1268
1269 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1270 if (!err) {
1271 int tar_levels;
1272
1273 /* Do some sanity checking for safety */
1274 tar_levels = tar & 0xff;
1275 if (tdp_ratio - 1 == tar_levels) {
1276 max_pstate = tar_levels;
1277 pr_debug("max_pstate=TAC %x\n", max_pstate);
1278 }
1279 }
1280
1281 return max_pstate;
1282}
1283
1284static int core_get_turbo_pstate(void)
1285{
1286 u64 value;
1287 int nont, ret;
1288
1289 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1290 nont = core_get_max_pstate();
1291 ret = (value) & 255;
1292 if (ret <= nont)
1293 ret = nont;
1294 return ret;
1295}
1296
1297static inline int core_get_scaling(void)
1298{
1299 return 100000;
1300}
1301
1302static u64 core_get_val(struct cpudata *cpudata, int pstate)
1303{
1304 u64 val;
1305
1306 val = (u64)pstate << 8;
1307 if (global.no_turbo && !global.turbo_disabled)
1308 val |= (u64)1 << 32;
1309
1310 return val;
1311}
1312
1313static int knl_get_aperf_mperf_shift(void)
1314{
1315 return 10;
1316}
1317
1318static int knl_get_turbo_pstate(void)
1319{
1320 u64 value;
1321 int nont, ret;
1322
1323 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1324 nont = core_get_max_pstate();
1325 ret = (((value) >> 8) & 0xFF);
1326 if (ret <= nont)
1327 ret = nont;
1328 return ret;
1329}
1330
1331static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1332{
1333 return global.no_turbo || global.turbo_disabled ?
1334 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1335}
1336
1337static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1338{
1339 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1340 cpu->pstate.current_pstate = pstate;
1341 /*
1342 * Generally, there is no guarantee that this code will always run on
1343 * the CPU being updated, so force the register update to run on the
1344 * right CPU.
1345 */
1346 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1347 pstate_funcs.get_val(cpu, pstate));
1348}
1349
1350static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1351{
1352 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1353}
1354
1355static void intel_pstate_max_within_limits(struct cpudata *cpu)
1356{
1357 int pstate;
1358
1359 update_turbo_state();
1360 pstate = intel_pstate_get_base_pstate(cpu);
1361 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1362 intel_pstate_set_pstate(cpu, pstate);
1363}
1364
1365static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1366{
1367 cpu->pstate.min_pstate = pstate_funcs.get_min();
1368 cpu->pstate.max_pstate = pstate_funcs.get_max();
1369 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1370 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1371 cpu->pstate.scaling = pstate_funcs.get_scaling();
1372 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1373 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1374
1375 if (pstate_funcs.get_aperf_mperf_shift)
1376 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1377
1378 if (pstate_funcs.get_vid)
1379 pstate_funcs.get_vid(cpu);
1380
1381 intel_pstate_set_min_pstate(cpu);
1382}
1383
1384static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1385{
1386 struct sample *sample = &cpu->sample;
1387
1388 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1389}
1390
1391static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1392{
1393 u64 aperf, mperf;
1394 unsigned long flags;
1395 u64 tsc;
1396
1397 local_irq_save(flags);
1398 rdmsrl(MSR_IA32_APERF, aperf);
1399 rdmsrl(MSR_IA32_MPERF, mperf);
1400 tsc = rdtsc();
1401 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1402 local_irq_restore(flags);
1403 return false;
1404 }
1405 local_irq_restore(flags);
1406
1407 cpu->last_sample_time = cpu->sample.time;
1408 cpu->sample.time = time;
1409 cpu->sample.aperf = aperf;
1410 cpu->sample.mperf = mperf;
1411 cpu->sample.tsc = tsc;
1412 cpu->sample.aperf -= cpu->prev_aperf;
1413 cpu->sample.mperf -= cpu->prev_mperf;
1414 cpu->sample.tsc -= cpu->prev_tsc;
1415
1416 cpu->prev_aperf = aperf;
1417 cpu->prev_mperf = mperf;
1418 cpu->prev_tsc = tsc;
1419 /*
1420 * First time this function is invoked in a given cycle, all of the
1421 * previous sample data fields are equal to zero or stale and they must
1422 * be populated with meaningful numbers for things to work, so assume
1423 * that sample.time will always be reset before setting the utilization
1424 * update hook and make the caller skip the sample then.
1425 */
1426 if (cpu->last_sample_time) {
1427 intel_pstate_calc_avg_perf(cpu);
1428 return true;
1429 }
1430 return false;
1431}
1432
1433static inline int32_t get_avg_frequency(struct cpudata *cpu)
1434{
1435 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1436}
1437
1438static inline int32_t get_avg_pstate(struct cpudata *cpu)
1439{
1440 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1441 cpu->sample.core_avg_perf);
1442}
1443
1444static inline int32_t get_target_pstate(struct cpudata *cpu)
1445{
1446 struct sample *sample = &cpu->sample;
1447 int32_t busy_frac, boost;
1448 int target, avg_pstate;
1449
1450 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1451 sample->tsc);
1452
1453 boost = cpu->iowait_boost;
1454 cpu->iowait_boost >>= 1;
1455
1456 if (busy_frac < boost)
1457 busy_frac = boost;
1458
1459 sample->busy_scaled = busy_frac * 100;
1460
1461 target = global.no_turbo || global.turbo_disabled ?
1462 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1463 target += target >> 2;
1464 target = mul_fp(target, busy_frac);
1465 if (target < cpu->pstate.min_pstate)
1466 target = cpu->pstate.min_pstate;
1467
1468 /*
1469 * If the average P-state during the previous cycle was higher than the
1470 * current target, add 50% of the difference to the target to reduce
1471 * possible performance oscillations and offset possible performance
1472 * loss related to moving the workload from one CPU to another within
1473 * a package/module.
1474 */
1475 avg_pstate = get_avg_pstate(cpu);
1476 if (avg_pstate > target)
1477 target += (avg_pstate - target) >> 1;
1478
1479 return target;
1480}
1481
1482static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1483{
1484 int max_pstate = intel_pstate_get_base_pstate(cpu);
1485 int min_pstate;
1486
1487 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1488 max_pstate = max(min_pstate, cpu->max_perf_ratio);
1489 return clamp_t(int, pstate, min_pstate, max_pstate);
1490}
1491
1492static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1493{
1494 if (pstate == cpu->pstate.current_pstate)
1495 return;
1496
1497 cpu->pstate.current_pstate = pstate;
1498 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1499}
1500
1501static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1502{
1503 int from = cpu->pstate.current_pstate;
1504 struct sample *sample;
1505 int target_pstate;
1506
1507 update_turbo_state();
1508
1509 target_pstate = get_target_pstate(cpu);
1510 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1511 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1512 intel_pstate_update_pstate(cpu, target_pstate);
1513
1514 sample = &cpu->sample;
1515 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1516 fp_toint(sample->busy_scaled),
1517 from,
1518 cpu->pstate.current_pstate,
1519 sample->mperf,
1520 sample->aperf,
1521 sample->tsc,
1522 get_avg_frequency(cpu),
1523 fp_toint(cpu->iowait_boost * 100));
1524}
1525
1526static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1527 unsigned int flags)
1528{
1529 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1530 u64 delta_ns;
1531
1532 /* Don't allow remote callbacks */
1533 if (smp_processor_id() != cpu->cpu)
1534 return;
1535
1536 if (flags & SCHED_CPUFREQ_IOWAIT) {
1537 cpu->iowait_boost = int_tofp(1);
1538 cpu->last_update = time;
1539 /*
1540 * The last time the busy was 100% so P-state was max anyway
1541 * so avoid overhead of computation.
1542 */
1543 if (fp_toint(cpu->sample.busy_scaled) == 100)
1544 return;
1545
1546 goto set_pstate;
1547 } else if (cpu->iowait_boost) {
1548 /* Clear iowait_boost if the CPU may have been idle. */
1549 delta_ns = time - cpu->last_update;
1550 if (delta_ns > TICK_NSEC)
1551 cpu->iowait_boost = 0;
1552 }
1553 cpu->last_update = time;
1554 delta_ns = time - cpu->sample.time;
1555 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1556 return;
1557
1558set_pstate:
1559 if (intel_pstate_sample(cpu, time))
1560 intel_pstate_adjust_pstate(cpu);
1561}
1562
1563static struct pstate_funcs core_funcs = {
1564 .get_max = core_get_max_pstate,
1565 .get_max_physical = core_get_max_pstate_physical,
1566 .get_min = core_get_min_pstate,
1567 .get_turbo = core_get_turbo_pstate,
1568 .get_scaling = core_get_scaling,
1569 .get_val = core_get_val,
1570};
1571
1572static const struct pstate_funcs silvermont_funcs = {
1573 .get_max = atom_get_max_pstate,
1574 .get_max_physical = atom_get_max_pstate,
1575 .get_min = atom_get_min_pstate,
1576 .get_turbo = atom_get_turbo_pstate,
1577 .get_val = atom_get_val,
1578 .get_scaling = silvermont_get_scaling,
1579 .get_vid = atom_get_vid,
1580};
1581
1582static const struct pstate_funcs airmont_funcs = {
1583 .get_max = atom_get_max_pstate,
1584 .get_max_physical = atom_get_max_pstate,
1585 .get_min = atom_get_min_pstate,
1586 .get_turbo = atom_get_turbo_pstate,
1587 .get_val = atom_get_val,
1588 .get_scaling = airmont_get_scaling,
1589 .get_vid = atom_get_vid,
1590};
1591
1592static const struct pstate_funcs knl_funcs = {
1593 .get_max = core_get_max_pstate,
1594 .get_max_physical = core_get_max_pstate_physical,
1595 .get_min = core_get_min_pstate,
1596 .get_turbo = knl_get_turbo_pstate,
1597 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1598 .get_scaling = core_get_scaling,
1599 .get_val = core_get_val,
1600};
1601
1602#define ICPU(model, policy) \
1603 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1604 (unsigned long)&policy }
1605
1606static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1607 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1608 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1609 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
1610 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1611 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1612 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1613 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1614 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1615 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1616 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1617 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1618 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1619 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1620 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1621 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1622 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1623 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1624 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1625 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
1626 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, core_funcs),
1627 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1628 {}
1629};
1630MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1631
1632static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1633 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1634 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1635 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1636 {}
1637};
1638
1639static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1640 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1641 {}
1642};
1643
1644static int intel_pstate_init_cpu(unsigned int cpunum)
1645{
1646 struct cpudata *cpu;
1647
1648 cpu = all_cpu_data[cpunum];
1649
1650 if (!cpu) {
1651 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1652 if (!cpu)
1653 return -ENOMEM;
1654
1655 all_cpu_data[cpunum] = cpu;
1656
1657 cpu->epp_default = -EINVAL;
1658 cpu->epp_powersave = -EINVAL;
1659 cpu->epp_saved = -EINVAL;
1660 }
1661
1662 cpu = all_cpu_data[cpunum];
1663
1664 cpu->cpu = cpunum;
1665
1666 if (hwp_active) {
1667 const struct x86_cpu_id *id;
1668
1669 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1670 if (id)
1671 intel_pstate_disable_ee(cpunum);
1672
1673 intel_pstate_hwp_enable(cpu);
1674 }
1675
1676 intel_pstate_get_cpu_pstates(cpu);
1677
1678 pr_debug("controlling: cpu %d\n", cpunum);
1679
1680 return 0;
1681}
1682
1683static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1684{
1685 struct cpudata *cpu = all_cpu_data[cpu_num];
1686
1687 if (hwp_active)
1688 return;
1689
1690 if (cpu->update_util_set)
1691 return;
1692
1693 /* Prevent intel_pstate_update_util() from using stale data. */
1694 cpu->sample.time = 0;
1695 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1696 intel_pstate_update_util);
1697 cpu->update_util_set = true;
1698}
1699
1700static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1701{
1702 struct cpudata *cpu_data = all_cpu_data[cpu];
1703
1704 if (!cpu_data->update_util_set)
1705 return;
1706
1707 cpufreq_remove_update_util_hook(cpu);
1708 cpu_data->update_util_set = false;
1709 synchronize_sched();
1710}
1711
1712static int intel_pstate_get_max_freq(struct cpudata *cpu)
1713{
1714 return global.turbo_disabled || global.no_turbo ?
1715 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1716}
1717
1718static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1719 struct cpudata *cpu)
1720{
1721 int max_freq = intel_pstate_get_max_freq(cpu);
1722 int32_t max_policy_perf, min_policy_perf;
1723 int max_state, turbo_max;
1724
1725 /*
1726 * HWP needs some special consideration, because on BDX the
1727 * HWP_REQUEST uses abstract value to represent performance
1728 * rather than pure ratios.
1729 */
1730 if (hwp_active) {
1731 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1732 } else {
1733 max_state = intel_pstate_get_base_pstate(cpu);
1734 turbo_max = cpu->pstate.turbo_pstate;
1735 }
1736
1737 max_policy_perf = max_state * policy->max / max_freq;
1738 if (policy->max == policy->min) {
1739 min_policy_perf = max_policy_perf;
1740 } else {
1741 min_policy_perf = max_state * policy->min / max_freq;
1742 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1743 0, max_policy_perf);
1744 }
1745
1746 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1747 policy->cpu, max_state,
1748 min_policy_perf, max_policy_perf);
1749
1750 /* Normalize user input to [min_perf, max_perf] */
1751 if (per_cpu_limits) {
1752 cpu->min_perf_ratio = min_policy_perf;
1753 cpu->max_perf_ratio = max_policy_perf;
1754 } else {
1755 int32_t global_min, global_max;
1756
1757 /* Global limits are in percent of the maximum turbo P-state. */
1758 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1759 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
1760 global_min = clamp_t(int32_t, global_min, 0, global_max);
1761
1762 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1763 global_min, global_max);
1764
1765 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1766 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
1767 cpu->max_perf_ratio = min(max_policy_perf, global_max);
1768 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
1769
1770 /* Make sure min_perf <= max_perf */
1771 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
1772 cpu->max_perf_ratio);
1773
1774 }
1775 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
1776 cpu->max_perf_ratio,
1777 cpu->min_perf_ratio);
1778}
1779
1780static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1781{
1782 struct cpudata *cpu;
1783
1784 if (!policy->cpuinfo.max_freq)
1785 return -ENODEV;
1786
1787 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1788 policy->cpuinfo.max_freq, policy->max);
1789
1790 cpu = all_cpu_data[policy->cpu];
1791 cpu->policy = policy->policy;
1792
1793 mutex_lock(&intel_pstate_limits_lock);
1794
1795 intel_pstate_update_perf_limits(policy, cpu);
1796
1797 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1798 /*
1799 * NOHZ_FULL CPUs need this as the governor callback may not
1800 * be invoked on them.
1801 */
1802 intel_pstate_clear_update_util_hook(policy->cpu);
1803 intel_pstate_max_within_limits(cpu);
1804 } else {
1805 intel_pstate_set_update_util_hook(policy->cpu);
1806 }
1807
1808 if (hwp_active)
1809 intel_pstate_hwp_set(policy->cpu);
1810
1811 mutex_unlock(&intel_pstate_limits_lock);
1812
1813 return 0;
1814}
1815
1816static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
1817 struct cpudata *cpu)
1818{
1819 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1820 policy->max < policy->cpuinfo.max_freq &&
1821 policy->max > cpu->pstate.max_freq) {
1822 pr_debug("policy->max > max non turbo frequency\n");
1823 policy->max = policy->cpuinfo.max_freq;
1824 }
1825}
1826
1827static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1828{
1829 struct cpudata *cpu = all_cpu_data[policy->cpu];
1830
1831 update_turbo_state();
1832 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1833 intel_pstate_get_max_freq(cpu));
1834
1835 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1836 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1837 return -EINVAL;
1838
1839 intel_pstate_adjust_policy_max(policy, cpu);
1840
1841 return 0;
1842}
1843
1844static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
1845{
1846 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
1847}
1848
1849static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
1850{
1851 pr_debug("CPU %d exiting\n", policy->cpu);
1852
1853 intel_pstate_clear_update_util_hook(policy->cpu);
1854 if (hwp_active)
1855 intel_pstate_hwp_save_state(policy);
1856 else
1857 intel_cpufreq_stop_cpu(policy);
1858}
1859
1860static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
1861{
1862 intel_pstate_exit_perf_limits(policy);
1863
1864 policy->fast_switch_possible = false;
1865
1866 return 0;
1867}
1868
1869static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
1870{
1871 struct cpudata *cpu;
1872 int rc;
1873
1874 rc = intel_pstate_init_cpu(policy->cpu);
1875 if (rc)
1876 return rc;
1877
1878 cpu = all_cpu_data[policy->cpu];
1879
1880 cpu->max_perf_ratio = 0xFF;
1881 cpu->min_perf_ratio = 0;
1882
1883 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1884 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1885
1886 /* cpuinfo and default policy values */
1887 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
1888 update_turbo_state();
1889 policy->cpuinfo.max_freq = global.turbo_disabled ?
1890 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1891 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
1892
1893 intel_pstate_init_acpi_perf_limits(policy);
1894
1895 policy->fast_switch_possible = true;
1896
1897 return 0;
1898}
1899
1900static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
1901{
1902 int ret = __intel_pstate_cpu_init(policy);
1903
1904 if (ret)
1905 return ret;
1906
1907 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
1908 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1909 else
1910 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1911
1912 return 0;
1913}
1914
1915static struct cpufreq_driver intel_pstate = {
1916 .flags = CPUFREQ_CONST_LOOPS,
1917 .verify = intel_pstate_verify_policy,
1918 .setpolicy = intel_pstate_set_policy,
1919 .suspend = intel_pstate_hwp_save_state,
1920 .resume = intel_pstate_resume,
1921 .init = intel_pstate_cpu_init,
1922 .exit = intel_pstate_cpu_exit,
1923 .stop_cpu = intel_pstate_stop_cpu,
1924 .name = "intel_pstate",
1925};
1926
1927static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
1928{
1929 struct cpudata *cpu = all_cpu_data[policy->cpu];
1930
1931 update_turbo_state();
1932 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
1933 intel_pstate_get_max_freq(cpu));
1934
1935 intel_pstate_adjust_policy_max(policy, cpu);
1936
1937 intel_pstate_update_perf_limits(policy, cpu);
1938
1939 return 0;
1940}
1941
1942static int intel_cpufreq_target(struct cpufreq_policy *policy,
1943 unsigned int target_freq,
1944 unsigned int relation)
1945{
1946 struct cpudata *cpu = all_cpu_data[policy->cpu];
1947 struct cpufreq_freqs freqs;
1948 int target_pstate;
1949
1950 update_turbo_state();
1951
1952 freqs.old = policy->cur;
1953 freqs.new = target_freq;
1954
1955 cpufreq_freq_transition_begin(policy, &freqs);
1956 switch (relation) {
1957 case CPUFREQ_RELATION_L:
1958 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
1959 break;
1960 case CPUFREQ_RELATION_H:
1961 target_pstate = freqs.new / cpu->pstate.scaling;
1962 break;
1963 default:
1964 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
1965 break;
1966 }
1967 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1968 if (target_pstate != cpu->pstate.current_pstate) {
1969 cpu->pstate.current_pstate = target_pstate;
1970 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
1971 pstate_funcs.get_val(cpu, target_pstate));
1972 }
1973 freqs.new = target_pstate * cpu->pstate.scaling;
1974 cpufreq_freq_transition_end(policy, &freqs, false);
1975
1976 return 0;
1977}
1978
1979static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
1980 unsigned int target_freq)
1981{
1982 struct cpudata *cpu = all_cpu_data[policy->cpu];
1983 int target_pstate;
1984
1985 update_turbo_state();
1986
1987 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
1988 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1989 intel_pstate_update_pstate(cpu, target_pstate);
1990 return target_pstate * cpu->pstate.scaling;
1991}
1992
1993static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
1994{
1995 int ret = __intel_pstate_cpu_init(policy);
1996
1997 if (ret)
1998 return ret;
1999
2000 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2001 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2002 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2003 policy->cur = policy->cpuinfo.min_freq;
2004
2005 return 0;
2006}
2007
2008static struct cpufreq_driver intel_cpufreq = {
2009 .flags = CPUFREQ_CONST_LOOPS,
2010 .verify = intel_cpufreq_verify_policy,
2011 .target = intel_cpufreq_target,
2012 .fast_switch = intel_cpufreq_fast_switch,
2013 .init = intel_cpufreq_cpu_init,
2014 .exit = intel_pstate_cpu_exit,
2015 .stop_cpu = intel_cpufreq_stop_cpu,
2016 .name = "intel_cpufreq",
2017};
2018
2019static struct cpufreq_driver *default_driver = &intel_pstate;
2020
2021static void intel_pstate_driver_cleanup(void)
2022{
2023 unsigned int cpu;
2024
2025 get_online_cpus();
2026 for_each_online_cpu(cpu) {
2027 if (all_cpu_data[cpu]) {
2028 if (intel_pstate_driver == &intel_pstate)
2029 intel_pstate_clear_update_util_hook(cpu);
2030
2031 kfree(all_cpu_data[cpu]);
2032 all_cpu_data[cpu] = NULL;
2033 }
2034 }
2035 put_online_cpus();
2036 intel_pstate_driver = NULL;
2037}
2038
2039static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2040{
2041 int ret;
2042
2043 memset(&global, 0, sizeof(global));
2044 global.max_perf_pct = 100;
2045
2046 intel_pstate_driver = driver;
2047 ret = cpufreq_register_driver(intel_pstate_driver);
2048 if (ret) {
2049 intel_pstate_driver_cleanup();
2050 return ret;
2051 }
2052
2053 global.min_perf_pct = min_perf_pct_min();
2054
2055 return 0;
2056}
2057
2058static int intel_pstate_unregister_driver(void)
2059{
2060 if (hwp_active)
2061 return -EBUSY;
2062
2063 cpufreq_unregister_driver(intel_pstate_driver);
2064 intel_pstate_driver_cleanup();
2065
2066 return 0;
2067}
2068
2069static ssize_t intel_pstate_show_status(char *buf)
2070{
2071 if (!intel_pstate_driver)
2072 return sprintf(buf, "off\n");
2073
2074 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2075 "active" : "passive");
2076}
2077
2078static int intel_pstate_update_status(const char *buf, size_t size)
2079{
2080 int ret;
2081
2082 if (size == 3 && !strncmp(buf, "off", size))
2083 return intel_pstate_driver ?
2084 intel_pstate_unregister_driver() : -EINVAL;
2085
2086 if (size == 6 && !strncmp(buf, "active", size)) {
2087 if (intel_pstate_driver) {
2088 if (intel_pstate_driver == &intel_pstate)
2089 return 0;
2090
2091 ret = intel_pstate_unregister_driver();
2092 if (ret)
2093 return ret;
2094 }
2095
2096 return intel_pstate_register_driver(&intel_pstate);
2097 }
2098
2099 if (size == 7 && !strncmp(buf, "passive", size)) {
2100 if (intel_pstate_driver) {
2101 if (intel_pstate_driver == &intel_cpufreq)
2102 return 0;
2103
2104 ret = intel_pstate_unregister_driver();
2105 if (ret)
2106 return ret;
2107 }
2108
2109 return intel_pstate_register_driver(&intel_cpufreq);
2110 }
2111
2112 return -EINVAL;
2113}
2114
2115static int no_load __initdata;
2116static int no_hwp __initdata;
2117static int hwp_only __initdata;
2118static unsigned int force_load __initdata;
2119
2120static int __init intel_pstate_msrs_not_valid(void)
2121{
2122 if (!pstate_funcs.get_max() ||
2123 !pstate_funcs.get_min() ||
2124 !pstate_funcs.get_turbo())
2125 return -ENODEV;
2126
2127 return 0;
2128}
2129
2130static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2131{
2132 pstate_funcs.get_max = funcs->get_max;
2133 pstate_funcs.get_max_physical = funcs->get_max_physical;
2134 pstate_funcs.get_min = funcs->get_min;
2135 pstate_funcs.get_turbo = funcs->get_turbo;
2136 pstate_funcs.get_scaling = funcs->get_scaling;
2137 pstate_funcs.get_val = funcs->get_val;
2138 pstate_funcs.get_vid = funcs->get_vid;
2139 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2140}
2141
2142#ifdef CONFIG_ACPI
2143
2144static bool __init intel_pstate_no_acpi_pss(void)
2145{
2146 int i;
2147
2148 for_each_possible_cpu(i) {
2149 acpi_status status;
2150 union acpi_object *pss;
2151 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2152 struct acpi_processor *pr = per_cpu(processors, i);
2153
2154 if (!pr)
2155 continue;
2156
2157 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2158 if (ACPI_FAILURE(status))
2159 continue;
2160
2161 pss = buffer.pointer;
2162 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2163 kfree(pss);
2164 return false;
2165 }
2166
2167 kfree(pss);
2168 }
2169
2170 return true;
2171}
2172
2173static bool __init intel_pstate_has_acpi_ppc(void)
2174{
2175 int i;
2176
2177 for_each_possible_cpu(i) {
2178 struct acpi_processor *pr = per_cpu(processors, i);
2179
2180 if (!pr)
2181 continue;
2182 if (acpi_has_method(pr->handle, "_PPC"))
2183 return true;
2184 }
2185 return false;
2186}
2187
2188enum {
2189 PSS,
2190 PPC,
2191};
2192
2193/* Hardware vendor-specific info that has its own power management modes */
2194static struct acpi_platform_list plat_info[] __initdata = {
2195 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2196 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2197 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2198 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2199 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2200 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2201 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2202 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2203 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2204 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2205 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2206 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2207 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2208 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2209 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2210 { } /* End */
2211};
2212
2213static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2214{
2215 const struct x86_cpu_id *id;
2216 u64 misc_pwr;
2217 int idx;
2218
2219 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2220 if (id) {
2221 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2222 if ( misc_pwr & (1 << 8))
2223 return true;
2224 }
2225
2226 idx = acpi_match_platform_list(plat_info);
2227 if (idx < 0)
2228 return false;
2229
2230 switch (plat_info[idx].data) {
2231 case PSS:
2232 return intel_pstate_no_acpi_pss();
2233 case PPC:
2234 return intel_pstate_has_acpi_ppc() && !force_load;
2235 }
2236
2237 return false;
2238}
2239
2240static void intel_pstate_request_control_from_smm(void)
2241{
2242 /*
2243 * It may be unsafe to request P-states control from SMM if _PPC support
2244 * has not been enabled.
2245 */
2246 if (acpi_ppc)
2247 acpi_processor_pstate_control();
2248}
2249#else /* CONFIG_ACPI not enabled */
2250static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2251static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2252static inline void intel_pstate_request_control_from_smm(void) {}
2253#endif /* CONFIG_ACPI */
2254
2255static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2256 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2257 {}
2258};
2259
2260static int __init intel_pstate_init(void)
2261{
2262 int rc;
2263
2264 if (no_load)
2265 return -ENODEV;
2266
2267 if (x86_match_cpu(hwp_support_ids)) {
2268 copy_cpu_funcs(&core_funcs);
2269 if (!no_hwp) {
2270 hwp_active++;
2271 intel_pstate.attr = hwp_cpufreq_attrs;
2272 goto hwp_cpu_matched;
2273 }
2274 } else {
2275 const struct x86_cpu_id *id;
2276
2277 id = x86_match_cpu(intel_pstate_cpu_ids);
2278 if (!id)
2279 return -ENODEV;
2280
2281 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2282 }
2283
2284 if (intel_pstate_msrs_not_valid())
2285 return -ENODEV;
2286
2287hwp_cpu_matched:
2288 /*
2289 * The Intel pstate driver will be ignored if the platform
2290 * firmware has its own power management modes.
2291 */
2292 if (intel_pstate_platform_pwr_mgmt_exists())
2293 return -ENODEV;
2294
2295 if (!hwp_active && hwp_only)
2296 return -ENOTSUPP;
2297
2298 pr_info("Intel P-state driver initializing\n");
2299
2300 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2301 if (!all_cpu_data)
2302 return -ENOMEM;
2303
2304 intel_pstate_request_control_from_smm();
2305
2306 intel_pstate_sysfs_expose_params();
2307
2308 mutex_lock(&intel_pstate_driver_lock);
2309 rc = intel_pstate_register_driver(default_driver);
2310 mutex_unlock(&intel_pstate_driver_lock);
2311 if (rc)
2312 return rc;
2313
2314 if (hwp_active)
2315 pr_info("HWP enabled\n");
2316
2317 return 0;
2318}
2319device_initcall(intel_pstate_init);
2320
2321static int __init intel_pstate_setup(char *str)
2322{
2323 if (!str)
2324 return -EINVAL;
2325
2326 if (!strcmp(str, "disable")) {
2327 no_load = 1;
2328 } else if (!strcmp(str, "passive")) {
2329 pr_info("Passive mode enabled\n");
2330 default_driver = &intel_cpufreq;
2331 no_hwp = 1;
2332 }
2333 if (!strcmp(str, "no_hwp")) {
2334 pr_info("HWP disabled\n");
2335 no_hwp = 1;
2336 }
2337 if (!strcmp(str, "force"))
2338 force_load = 1;
2339 if (!strcmp(str, "hwp_only"))
2340 hwp_only = 1;
2341 if (!strcmp(str, "per_cpu_perf_limits"))
2342 per_cpu_limits = true;
2343
2344#ifdef CONFIG_ACPI
2345 if (!strcmp(str, "support_acpi_ppc"))
2346 acpi_ppc = true;
2347#endif
2348
2349 return 0;
2350}
2351early_param("intel_pstate", intel_pstate_setup);
2352
2353MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2354MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2355MODULE_LICENSE("GPL");