Loading...
1/*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
21#include <linux/slab.h>
22
23#include <asm/io.h>
24#include <mach/board.h>
25#include <mach/gpio.h>
26#include <mach/cpu.h>
27
28/* SPI register offsets */
29#define SPI_CR 0x0000
30#define SPI_MR 0x0004
31#define SPI_RDR 0x0008
32#define SPI_TDR 0x000c
33#define SPI_SR 0x0010
34#define SPI_IER 0x0014
35#define SPI_IDR 0x0018
36#define SPI_IMR 0x001c
37#define SPI_CSR0 0x0030
38#define SPI_CSR1 0x0034
39#define SPI_CSR2 0x0038
40#define SPI_CSR3 0x003c
41#define SPI_RPR 0x0100
42#define SPI_RCR 0x0104
43#define SPI_TPR 0x0108
44#define SPI_TCR 0x010c
45#define SPI_RNPR 0x0110
46#define SPI_RNCR 0x0114
47#define SPI_TNPR 0x0118
48#define SPI_TNCR 0x011c
49#define SPI_PTCR 0x0120
50#define SPI_PTSR 0x0124
51
52/* Bitfields in CR */
53#define SPI_SPIEN_OFFSET 0
54#define SPI_SPIEN_SIZE 1
55#define SPI_SPIDIS_OFFSET 1
56#define SPI_SPIDIS_SIZE 1
57#define SPI_SWRST_OFFSET 7
58#define SPI_SWRST_SIZE 1
59#define SPI_LASTXFER_OFFSET 24
60#define SPI_LASTXFER_SIZE 1
61
62/* Bitfields in MR */
63#define SPI_MSTR_OFFSET 0
64#define SPI_MSTR_SIZE 1
65#define SPI_PS_OFFSET 1
66#define SPI_PS_SIZE 1
67#define SPI_PCSDEC_OFFSET 2
68#define SPI_PCSDEC_SIZE 1
69#define SPI_FDIV_OFFSET 3
70#define SPI_FDIV_SIZE 1
71#define SPI_MODFDIS_OFFSET 4
72#define SPI_MODFDIS_SIZE 1
73#define SPI_LLB_OFFSET 7
74#define SPI_LLB_SIZE 1
75#define SPI_PCS_OFFSET 16
76#define SPI_PCS_SIZE 4
77#define SPI_DLYBCS_OFFSET 24
78#define SPI_DLYBCS_SIZE 8
79
80/* Bitfields in RDR */
81#define SPI_RD_OFFSET 0
82#define SPI_RD_SIZE 16
83
84/* Bitfields in TDR */
85#define SPI_TD_OFFSET 0
86#define SPI_TD_SIZE 16
87
88/* Bitfields in SR */
89#define SPI_RDRF_OFFSET 0
90#define SPI_RDRF_SIZE 1
91#define SPI_TDRE_OFFSET 1
92#define SPI_TDRE_SIZE 1
93#define SPI_MODF_OFFSET 2
94#define SPI_MODF_SIZE 1
95#define SPI_OVRES_OFFSET 3
96#define SPI_OVRES_SIZE 1
97#define SPI_ENDRX_OFFSET 4
98#define SPI_ENDRX_SIZE 1
99#define SPI_ENDTX_OFFSET 5
100#define SPI_ENDTX_SIZE 1
101#define SPI_RXBUFF_OFFSET 6
102#define SPI_RXBUFF_SIZE 1
103#define SPI_TXBUFE_OFFSET 7
104#define SPI_TXBUFE_SIZE 1
105#define SPI_NSSR_OFFSET 8
106#define SPI_NSSR_SIZE 1
107#define SPI_TXEMPTY_OFFSET 9
108#define SPI_TXEMPTY_SIZE 1
109#define SPI_SPIENS_OFFSET 16
110#define SPI_SPIENS_SIZE 1
111
112/* Bitfields in CSR0 */
113#define SPI_CPOL_OFFSET 0
114#define SPI_CPOL_SIZE 1
115#define SPI_NCPHA_OFFSET 1
116#define SPI_NCPHA_SIZE 1
117#define SPI_CSAAT_OFFSET 3
118#define SPI_CSAAT_SIZE 1
119#define SPI_BITS_OFFSET 4
120#define SPI_BITS_SIZE 4
121#define SPI_SCBR_OFFSET 8
122#define SPI_SCBR_SIZE 8
123#define SPI_DLYBS_OFFSET 16
124#define SPI_DLYBS_SIZE 8
125#define SPI_DLYBCT_OFFSET 24
126#define SPI_DLYBCT_SIZE 8
127
128/* Bitfields in RCR */
129#define SPI_RXCTR_OFFSET 0
130#define SPI_RXCTR_SIZE 16
131
132/* Bitfields in TCR */
133#define SPI_TXCTR_OFFSET 0
134#define SPI_TXCTR_SIZE 16
135
136/* Bitfields in RNCR */
137#define SPI_RXNCR_OFFSET 0
138#define SPI_RXNCR_SIZE 16
139
140/* Bitfields in TNCR */
141#define SPI_TXNCR_OFFSET 0
142#define SPI_TXNCR_SIZE 16
143
144/* Bitfields in PTCR */
145#define SPI_RXTEN_OFFSET 0
146#define SPI_RXTEN_SIZE 1
147#define SPI_RXTDIS_OFFSET 1
148#define SPI_RXTDIS_SIZE 1
149#define SPI_TXTEN_OFFSET 8
150#define SPI_TXTEN_SIZE 1
151#define SPI_TXTDIS_OFFSET 9
152#define SPI_TXTDIS_SIZE 1
153
154/* Constants for BITS */
155#define SPI_BITS_8_BPT 0
156#define SPI_BITS_9_BPT 1
157#define SPI_BITS_10_BPT 2
158#define SPI_BITS_11_BPT 3
159#define SPI_BITS_12_BPT 4
160#define SPI_BITS_13_BPT 5
161#define SPI_BITS_14_BPT 6
162#define SPI_BITS_15_BPT 7
163#define SPI_BITS_16_BPT 8
164
165/* Bit manipulation macros */
166#define SPI_BIT(name) \
167 (1 << SPI_##name##_OFFSET)
168#define SPI_BF(name,value) \
169 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
170#define SPI_BFEXT(name,value) \
171 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
172#define SPI_BFINS(name,value,old) \
173 ( ((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
174 | SPI_BF(name,value))
175
176/* Register access macros */
177#define spi_readl(port,reg) \
178 __raw_readl((port)->regs + SPI_##reg)
179#define spi_writel(port,reg,value) \
180 __raw_writel((value), (port)->regs + SPI_##reg)
181
182
183/*
184 * The core SPI transfer engine just talks to a register bank to set up
185 * DMA transfers; transfer queue progress is driven by IRQs. The clock
186 * framework provides the base clock, subdivided for each spi_device.
187 */
188struct atmel_spi {
189 spinlock_t lock;
190
191 void __iomem *regs;
192 int irq;
193 struct clk *clk;
194 struct platform_device *pdev;
195 struct spi_device *stay;
196
197 u8 stopping;
198 struct list_head queue;
199 struct spi_transfer *current_transfer;
200 unsigned long current_remaining_bytes;
201 struct spi_transfer *next_transfer;
202 unsigned long next_remaining_bytes;
203
204 void *buffer;
205 dma_addr_t buffer_dma;
206};
207
208/* Controller-specific per-slave state */
209struct atmel_spi_device {
210 unsigned int npcs_pin;
211 u32 csr;
212};
213
214#define BUFFER_SIZE PAGE_SIZE
215#define INVALID_DMA_ADDRESS 0xffffffff
216
217/*
218 * Version 2 of the SPI controller has
219 * - CR.LASTXFER
220 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
221 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
222 * - SPI_CSRx.CSAAT
223 * - SPI_CSRx.SBCR allows faster clocking
224 *
225 * We can determine the controller version by reading the VERSION
226 * register, but I haven't checked that it exists on all chips, and
227 * this is cheaper anyway.
228 */
229static bool atmel_spi_is_v2(void)
230{
231 return !cpu_is_at91rm9200();
232}
233
234/*
235 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
236 * they assume that spi slave device state will not change on deselect, so
237 * that automagic deselection is OK. ("NPCSx rises if no data is to be
238 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
239 * controllers have CSAAT and friends.
240 *
241 * Since the CSAAT functionality is a bit weird on newer controllers as
242 * well, we use GPIO to control nCSx pins on all controllers, updating
243 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
244 * support active-high chipselects despite the controller's belief that
245 * only active-low devices/systems exists.
246 *
247 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
248 * right when driven with GPIO. ("Mode Fault does not allow more than one
249 * Master on Chip Select 0.") No workaround exists for that ... so for
250 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
251 * and (c) will trigger that first erratum in some cases.
252 *
253 * TODO: Test if the atmel_spi_is_v2() branch below works on
254 * AT91RM9200 if we use some other register than CSR0. However, don't
255 * do this unconditionally since AP7000 has an errata where the BITS
256 * field in CSR0 overrides all other CSRs.
257 */
258
259static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
260{
261 struct atmel_spi_device *asd = spi->controller_state;
262 unsigned active = spi->mode & SPI_CS_HIGH;
263 u32 mr;
264
265 if (atmel_spi_is_v2()) {
266 /*
267 * Always use CSR0. This ensures that the clock
268 * switches to the correct idle polarity before we
269 * toggle the CS.
270 */
271 spi_writel(as, CSR0, asd->csr);
272 spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
273 | SPI_BIT(MSTR));
274 mr = spi_readl(as, MR);
275 gpio_set_value(asd->npcs_pin, active);
276 } else {
277 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
278 int i;
279 u32 csr;
280
281 /* Make sure clock polarity is correct */
282 for (i = 0; i < spi->master->num_chipselect; i++) {
283 csr = spi_readl(as, CSR0 + 4 * i);
284 if ((csr ^ cpol) & SPI_BIT(CPOL))
285 spi_writel(as, CSR0 + 4 * i,
286 csr ^ SPI_BIT(CPOL));
287 }
288
289 mr = spi_readl(as, MR);
290 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
291 if (spi->chip_select != 0)
292 gpio_set_value(asd->npcs_pin, active);
293 spi_writel(as, MR, mr);
294 }
295
296 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
297 asd->npcs_pin, active ? " (high)" : "",
298 mr);
299}
300
301static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
302{
303 struct atmel_spi_device *asd = spi->controller_state;
304 unsigned active = spi->mode & SPI_CS_HIGH;
305 u32 mr;
306
307 /* only deactivate *this* device; sometimes transfers to
308 * another device may be active when this routine is called.
309 */
310 mr = spi_readl(as, MR);
311 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
312 mr = SPI_BFINS(PCS, 0xf, mr);
313 spi_writel(as, MR, mr);
314 }
315
316 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
317 asd->npcs_pin, active ? " (low)" : "",
318 mr);
319
320 if (atmel_spi_is_v2() || spi->chip_select != 0)
321 gpio_set_value(asd->npcs_pin, !active);
322}
323
324static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
325 struct spi_transfer *xfer)
326{
327 return msg->transfers.prev == &xfer->transfer_list;
328}
329
330static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
331{
332 return xfer->delay_usecs == 0 && !xfer->cs_change;
333}
334
335static void atmel_spi_next_xfer_data(struct spi_master *master,
336 struct spi_transfer *xfer,
337 dma_addr_t *tx_dma,
338 dma_addr_t *rx_dma,
339 u32 *plen)
340{
341 struct atmel_spi *as = spi_master_get_devdata(master);
342 u32 len = *plen;
343
344 /* use scratch buffer only when rx or tx data is unspecified */
345 if (xfer->rx_buf)
346 *rx_dma = xfer->rx_dma + xfer->len - *plen;
347 else {
348 *rx_dma = as->buffer_dma;
349 if (len > BUFFER_SIZE)
350 len = BUFFER_SIZE;
351 }
352 if (xfer->tx_buf)
353 *tx_dma = xfer->tx_dma + xfer->len - *plen;
354 else {
355 *tx_dma = as->buffer_dma;
356 if (len > BUFFER_SIZE)
357 len = BUFFER_SIZE;
358 memset(as->buffer, 0, len);
359 dma_sync_single_for_device(&as->pdev->dev,
360 as->buffer_dma, len, DMA_TO_DEVICE);
361 }
362
363 *plen = len;
364}
365
366/*
367 * Submit next transfer for DMA.
368 * lock is held, spi irq is blocked
369 */
370static void atmel_spi_next_xfer(struct spi_master *master,
371 struct spi_message *msg)
372{
373 struct atmel_spi *as = spi_master_get_devdata(master);
374 struct spi_transfer *xfer;
375 u32 len, remaining;
376 u32 ieval;
377 dma_addr_t tx_dma, rx_dma;
378
379 if (!as->current_transfer)
380 xfer = list_entry(msg->transfers.next,
381 struct spi_transfer, transfer_list);
382 else if (!as->next_transfer)
383 xfer = list_entry(as->current_transfer->transfer_list.next,
384 struct spi_transfer, transfer_list);
385 else
386 xfer = NULL;
387
388 if (xfer) {
389 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
390
391 len = xfer->len;
392 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
393 remaining = xfer->len - len;
394
395 spi_writel(as, RPR, rx_dma);
396 spi_writel(as, TPR, tx_dma);
397
398 if (msg->spi->bits_per_word > 8)
399 len >>= 1;
400 spi_writel(as, RCR, len);
401 spi_writel(as, TCR, len);
402
403 dev_dbg(&msg->spi->dev,
404 " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
405 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
406 xfer->rx_buf, xfer->rx_dma);
407 } else {
408 xfer = as->next_transfer;
409 remaining = as->next_remaining_bytes;
410 }
411
412 as->current_transfer = xfer;
413 as->current_remaining_bytes = remaining;
414
415 if (remaining > 0)
416 len = remaining;
417 else if (!atmel_spi_xfer_is_last(msg, xfer)
418 && atmel_spi_xfer_can_be_chained(xfer)) {
419 xfer = list_entry(xfer->transfer_list.next,
420 struct spi_transfer, transfer_list);
421 len = xfer->len;
422 } else
423 xfer = NULL;
424
425 as->next_transfer = xfer;
426
427 if (xfer) {
428 u32 total;
429
430 total = len;
431 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
432 as->next_remaining_bytes = total - len;
433
434 spi_writel(as, RNPR, rx_dma);
435 spi_writel(as, TNPR, tx_dma);
436
437 if (msg->spi->bits_per_word > 8)
438 len >>= 1;
439 spi_writel(as, RNCR, len);
440 spi_writel(as, TNCR, len);
441
442 dev_dbg(&msg->spi->dev,
443 " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
444 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
445 xfer->rx_buf, xfer->rx_dma);
446 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
447 } else {
448 spi_writel(as, RNCR, 0);
449 spi_writel(as, TNCR, 0);
450 ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
451 }
452
453 /* REVISIT: We're waiting for ENDRX before we start the next
454 * transfer because we need to handle some difficult timing
455 * issues otherwise. If we wait for ENDTX in one transfer and
456 * then starts waiting for ENDRX in the next, it's difficult
457 * to tell the difference between the ENDRX interrupt we're
458 * actually waiting for and the ENDRX interrupt of the
459 * previous transfer.
460 *
461 * It should be doable, though. Just not now...
462 */
463 spi_writel(as, IER, ieval);
464 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
465}
466
467static void atmel_spi_next_message(struct spi_master *master)
468{
469 struct atmel_spi *as = spi_master_get_devdata(master);
470 struct spi_message *msg;
471 struct spi_device *spi;
472
473 BUG_ON(as->current_transfer);
474
475 msg = list_entry(as->queue.next, struct spi_message, queue);
476 spi = msg->spi;
477
478 dev_dbg(master->dev.parent, "start message %p for %s\n",
479 msg, dev_name(&spi->dev));
480
481 /* select chip if it's not still active */
482 if (as->stay) {
483 if (as->stay != spi) {
484 cs_deactivate(as, as->stay);
485 cs_activate(as, spi);
486 }
487 as->stay = NULL;
488 } else
489 cs_activate(as, spi);
490
491 atmel_spi_next_xfer(master, msg);
492}
493
494/*
495 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
496 * - The buffer is either valid for CPU access, else NULL
497 * - If the buffer is valid, so is its DMA address
498 *
499 * This driver manages the dma address unless message->is_dma_mapped.
500 */
501static int
502atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
503{
504 struct device *dev = &as->pdev->dev;
505
506 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
507 if (xfer->tx_buf) {
508 /* tx_buf is a const void* where we need a void * for the dma
509 * mapping */
510 void *nonconst_tx = (void *)xfer->tx_buf;
511
512 xfer->tx_dma = dma_map_single(dev,
513 nonconst_tx, xfer->len,
514 DMA_TO_DEVICE);
515 if (dma_mapping_error(dev, xfer->tx_dma))
516 return -ENOMEM;
517 }
518 if (xfer->rx_buf) {
519 xfer->rx_dma = dma_map_single(dev,
520 xfer->rx_buf, xfer->len,
521 DMA_FROM_DEVICE);
522 if (dma_mapping_error(dev, xfer->rx_dma)) {
523 if (xfer->tx_buf)
524 dma_unmap_single(dev,
525 xfer->tx_dma, xfer->len,
526 DMA_TO_DEVICE);
527 return -ENOMEM;
528 }
529 }
530 return 0;
531}
532
533static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
534 struct spi_transfer *xfer)
535{
536 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
537 dma_unmap_single(master->dev.parent, xfer->tx_dma,
538 xfer->len, DMA_TO_DEVICE);
539 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
540 dma_unmap_single(master->dev.parent, xfer->rx_dma,
541 xfer->len, DMA_FROM_DEVICE);
542}
543
544static void
545atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
546 struct spi_message *msg, int status, int stay)
547{
548 if (!stay || status < 0)
549 cs_deactivate(as, msg->spi);
550 else
551 as->stay = msg->spi;
552
553 list_del(&msg->queue);
554 msg->status = status;
555
556 dev_dbg(master->dev.parent,
557 "xfer complete: %u bytes transferred\n",
558 msg->actual_length);
559
560 spin_unlock(&as->lock);
561 msg->complete(msg->context);
562 spin_lock(&as->lock);
563
564 as->current_transfer = NULL;
565 as->next_transfer = NULL;
566
567 /* continue if needed */
568 if (list_empty(&as->queue) || as->stopping)
569 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
570 else
571 atmel_spi_next_message(master);
572}
573
574static irqreturn_t
575atmel_spi_interrupt(int irq, void *dev_id)
576{
577 struct spi_master *master = dev_id;
578 struct atmel_spi *as = spi_master_get_devdata(master);
579 struct spi_message *msg;
580 struct spi_transfer *xfer;
581 u32 status, pending, imr;
582 int ret = IRQ_NONE;
583
584 spin_lock(&as->lock);
585
586 xfer = as->current_transfer;
587 msg = list_entry(as->queue.next, struct spi_message, queue);
588
589 imr = spi_readl(as, IMR);
590 status = spi_readl(as, SR);
591 pending = status & imr;
592
593 if (pending & SPI_BIT(OVRES)) {
594 int timeout;
595
596 ret = IRQ_HANDLED;
597
598 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
599 | SPI_BIT(OVRES)));
600
601 /*
602 * When we get an overrun, we disregard the current
603 * transfer. Data will not be copied back from any
604 * bounce buffer and msg->actual_len will not be
605 * updated with the last xfer.
606 *
607 * We will also not process any remaning transfers in
608 * the message.
609 *
610 * First, stop the transfer and unmap the DMA buffers.
611 */
612 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
613 if (!msg->is_dma_mapped)
614 atmel_spi_dma_unmap_xfer(master, xfer);
615
616 /* REVISIT: udelay in irq is unfriendly */
617 if (xfer->delay_usecs)
618 udelay(xfer->delay_usecs);
619
620 dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
621 spi_readl(as, TCR), spi_readl(as, RCR));
622
623 /*
624 * Clean up DMA registers and make sure the data
625 * registers are empty.
626 */
627 spi_writel(as, RNCR, 0);
628 spi_writel(as, TNCR, 0);
629 spi_writel(as, RCR, 0);
630 spi_writel(as, TCR, 0);
631 for (timeout = 1000; timeout; timeout--)
632 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
633 break;
634 if (!timeout)
635 dev_warn(master->dev.parent,
636 "timeout waiting for TXEMPTY");
637 while (spi_readl(as, SR) & SPI_BIT(RDRF))
638 spi_readl(as, RDR);
639
640 /* Clear any overrun happening while cleaning up */
641 spi_readl(as, SR);
642
643 atmel_spi_msg_done(master, as, msg, -EIO, 0);
644 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
645 ret = IRQ_HANDLED;
646
647 spi_writel(as, IDR, pending);
648
649 if (as->current_remaining_bytes == 0) {
650 msg->actual_length += xfer->len;
651
652 if (!msg->is_dma_mapped)
653 atmel_spi_dma_unmap_xfer(master, xfer);
654
655 /* REVISIT: udelay in irq is unfriendly */
656 if (xfer->delay_usecs)
657 udelay(xfer->delay_usecs);
658
659 if (atmel_spi_xfer_is_last(msg, xfer)) {
660 /* report completed message */
661 atmel_spi_msg_done(master, as, msg, 0,
662 xfer->cs_change);
663 } else {
664 if (xfer->cs_change) {
665 cs_deactivate(as, msg->spi);
666 udelay(1);
667 cs_activate(as, msg->spi);
668 }
669
670 /*
671 * Not done yet. Submit the next transfer.
672 *
673 * FIXME handle protocol options for xfer
674 */
675 atmel_spi_next_xfer(master, msg);
676 }
677 } else {
678 /*
679 * Keep going, we still have data to send in
680 * the current transfer.
681 */
682 atmel_spi_next_xfer(master, msg);
683 }
684 }
685
686 spin_unlock(&as->lock);
687
688 return ret;
689}
690
691static int atmel_spi_setup(struct spi_device *spi)
692{
693 struct atmel_spi *as;
694 struct atmel_spi_device *asd;
695 u32 scbr, csr;
696 unsigned int bits = spi->bits_per_word;
697 unsigned long bus_hz;
698 unsigned int npcs_pin;
699 int ret;
700
701 as = spi_master_get_devdata(spi->master);
702
703 if (as->stopping)
704 return -ESHUTDOWN;
705
706 if (spi->chip_select > spi->master->num_chipselect) {
707 dev_dbg(&spi->dev,
708 "setup: invalid chipselect %u (%u defined)\n",
709 spi->chip_select, spi->master->num_chipselect);
710 return -EINVAL;
711 }
712
713 if (bits < 8 || bits > 16) {
714 dev_dbg(&spi->dev,
715 "setup: invalid bits_per_word %u (8 to 16)\n",
716 bits);
717 return -EINVAL;
718 }
719
720 /* see notes above re chipselect */
721 if (!atmel_spi_is_v2()
722 && spi->chip_select == 0
723 && (spi->mode & SPI_CS_HIGH)) {
724 dev_dbg(&spi->dev, "setup: can't be active-high\n");
725 return -EINVAL;
726 }
727
728 /* v1 chips start out at half the peripheral bus speed. */
729 bus_hz = clk_get_rate(as->clk);
730 if (!atmel_spi_is_v2())
731 bus_hz /= 2;
732
733 if (spi->max_speed_hz) {
734 /*
735 * Calculate the lowest divider that satisfies the
736 * constraint, assuming div32/fdiv/mbz == 0.
737 */
738 scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
739
740 /*
741 * If the resulting divider doesn't fit into the
742 * register bitfield, we can't satisfy the constraint.
743 */
744 if (scbr >= (1 << SPI_SCBR_SIZE)) {
745 dev_dbg(&spi->dev,
746 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
747 spi->max_speed_hz, scbr, bus_hz/255);
748 return -EINVAL;
749 }
750 } else
751 /* speed zero means "as slow as possible" */
752 scbr = 0xff;
753
754 csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
755 if (spi->mode & SPI_CPOL)
756 csr |= SPI_BIT(CPOL);
757 if (!(spi->mode & SPI_CPHA))
758 csr |= SPI_BIT(NCPHA);
759
760 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
761 *
762 * DLYBCT would add delays between words, slowing down transfers.
763 * It could potentially be useful to cope with DMA bottlenecks, but
764 * in those cases it's probably best to just use a lower bitrate.
765 */
766 csr |= SPI_BF(DLYBS, 0);
767 csr |= SPI_BF(DLYBCT, 0);
768
769 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
770 npcs_pin = (unsigned int)spi->controller_data;
771 asd = spi->controller_state;
772 if (!asd) {
773 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
774 if (!asd)
775 return -ENOMEM;
776
777 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
778 if (ret) {
779 kfree(asd);
780 return ret;
781 }
782
783 asd->npcs_pin = npcs_pin;
784 spi->controller_state = asd;
785 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
786 } else {
787 unsigned long flags;
788
789 spin_lock_irqsave(&as->lock, flags);
790 if (as->stay == spi)
791 as->stay = NULL;
792 cs_deactivate(as, spi);
793 spin_unlock_irqrestore(&as->lock, flags);
794 }
795
796 asd->csr = csr;
797
798 dev_dbg(&spi->dev,
799 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
800 bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
801
802 if (!atmel_spi_is_v2())
803 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
804
805 return 0;
806}
807
808static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
809{
810 struct atmel_spi *as;
811 struct spi_transfer *xfer;
812 unsigned long flags;
813 struct device *controller = spi->master->dev.parent;
814 u8 bits;
815 struct atmel_spi_device *asd;
816
817 as = spi_master_get_devdata(spi->master);
818
819 dev_dbg(controller, "new message %p submitted for %s\n",
820 msg, dev_name(&spi->dev));
821
822 if (unlikely(list_empty(&msg->transfers)))
823 return -EINVAL;
824
825 if (as->stopping)
826 return -ESHUTDOWN;
827
828 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
829 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
830 dev_dbg(&spi->dev, "missing rx or tx buf\n");
831 return -EINVAL;
832 }
833
834 if (xfer->bits_per_word) {
835 asd = spi->controller_state;
836 bits = (asd->csr >> 4) & 0xf;
837 if (bits != xfer->bits_per_word - 8) {
838 dev_dbg(&spi->dev, "you can't yet change "
839 "bits_per_word in transfers\n");
840 return -ENOPROTOOPT;
841 }
842 }
843
844 /* FIXME implement these protocol options!! */
845 if (xfer->speed_hz) {
846 dev_dbg(&spi->dev, "no protocol options yet\n");
847 return -ENOPROTOOPT;
848 }
849
850 /*
851 * DMA map early, for performance (empties dcache ASAP) and
852 * better fault reporting. This is a DMA-only driver.
853 *
854 * NOTE that if dma_unmap_single() ever starts to do work on
855 * platforms supported by this driver, we would need to clean
856 * up mappings for previously-mapped transfers.
857 */
858 if (!msg->is_dma_mapped) {
859 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
860 return -ENOMEM;
861 }
862 }
863
864#ifdef VERBOSE
865 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
866 dev_dbg(controller,
867 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
868 xfer, xfer->len,
869 xfer->tx_buf, xfer->tx_dma,
870 xfer->rx_buf, xfer->rx_dma);
871 }
872#endif
873
874 msg->status = -EINPROGRESS;
875 msg->actual_length = 0;
876
877 spin_lock_irqsave(&as->lock, flags);
878 list_add_tail(&msg->queue, &as->queue);
879 if (!as->current_transfer)
880 atmel_spi_next_message(spi->master);
881 spin_unlock_irqrestore(&as->lock, flags);
882
883 return 0;
884}
885
886static void atmel_spi_cleanup(struct spi_device *spi)
887{
888 struct atmel_spi *as = spi_master_get_devdata(spi->master);
889 struct atmel_spi_device *asd = spi->controller_state;
890 unsigned gpio = (unsigned) spi->controller_data;
891 unsigned long flags;
892
893 if (!asd)
894 return;
895
896 spin_lock_irqsave(&as->lock, flags);
897 if (as->stay == spi) {
898 as->stay = NULL;
899 cs_deactivate(as, spi);
900 }
901 spin_unlock_irqrestore(&as->lock, flags);
902
903 spi->controller_state = NULL;
904 gpio_free(gpio);
905 kfree(asd);
906}
907
908/*-------------------------------------------------------------------------*/
909
910static int __init atmel_spi_probe(struct platform_device *pdev)
911{
912 struct resource *regs;
913 int irq;
914 struct clk *clk;
915 int ret;
916 struct spi_master *master;
917 struct atmel_spi *as;
918
919 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
920 if (!regs)
921 return -ENXIO;
922
923 irq = platform_get_irq(pdev, 0);
924 if (irq < 0)
925 return irq;
926
927 clk = clk_get(&pdev->dev, "spi_clk");
928 if (IS_ERR(clk))
929 return PTR_ERR(clk);
930
931 /* setup spi core then atmel-specific driver state */
932 ret = -ENOMEM;
933 master = spi_alloc_master(&pdev->dev, sizeof *as);
934 if (!master)
935 goto out_free;
936
937 /* the spi->mode bits understood by this driver: */
938 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
939
940 master->bus_num = pdev->id;
941 master->num_chipselect = 4;
942 master->setup = atmel_spi_setup;
943 master->transfer = atmel_spi_transfer;
944 master->cleanup = atmel_spi_cleanup;
945 platform_set_drvdata(pdev, master);
946
947 as = spi_master_get_devdata(master);
948
949 /*
950 * Scratch buffer is used for throwaway rx and tx data.
951 * It's coherent to minimize dcache pollution.
952 */
953 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
954 &as->buffer_dma, GFP_KERNEL);
955 if (!as->buffer)
956 goto out_free;
957
958 spin_lock_init(&as->lock);
959 INIT_LIST_HEAD(&as->queue);
960 as->pdev = pdev;
961 as->regs = ioremap(regs->start, resource_size(regs));
962 if (!as->regs)
963 goto out_free_buffer;
964 as->irq = irq;
965 as->clk = clk;
966
967 ret = request_irq(irq, atmel_spi_interrupt, 0,
968 dev_name(&pdev->dev), master);
969 if (ret)
970 goto out_unmap_regs;
971
972 /* Initialize the hardware */
973 clk_enable(clk);
974 spi_writel(as, CR, SPI_BIT(SWRST));
975 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
976 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
977 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
978 spi_writel(as, CR, SPI_BIT(SPIEN));
979
980 /* go! */
981 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
982 (unsigned long)regs->start, irq);
983
984 ret = spi_register_master(master);
985 if (ret)
986 goto out_reset_hw;
987
988 return 0;
989
990out_reset_hw:
991 spi_writel(as, CR, SPI_BIT(SWRST));
992 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
993 clk_disable(clk);
994 free_irq(irq, master);
995out_unmap_regs:
996 iounmap(as->regs);
997out_free_buffer:
998 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
999 as->buffer_dma);
1000out_free:
1001 clk_put(clk);
1002 spi_master_put(master);
1003 return ret;
1004}
1005
1006static int __exit atmel_spi_remove(struct platform_device *pdev)
1007{
1008 struct spi_master *master = platform_get_drvdata(pdev);
1009 struct atmel_spi *as = spi_master_get_devdata(master);
1010 struct spi_message *msg;
1011
1012 /* reset the hardware and block queue progress */
1013 spin_lock_irq(&as->lock);
1014 as->stopping = 1;
1015 spi_writel(as, CR, SPI_BIT(SWRST));
1016 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1017 spi_readl(as, SR);
1018 spin_unlock_irq(&as->lock);
1019
1020 /* Terminate remaining queued transfers */
1021 list_for_each_entry(msg, &as->queue, queue) {
1022 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
1023 * but we shouldn't depend on that...
1024 */
1025 msg->status = -ESHUTDOWN;
1026 msg->complete(msg->context);
1027 }
1028
1029 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1030 as->buffer_dma);
1031
1032 clk_disable(as->clk);
1033 clk_put(as->clk);
1034 free_irq(as->irq, master);
1035 iounmap(as->regs);
1036
1037 spi_unregister_master(master);
1038
1039 return 0;
1040}
1041
1042#ifdef CONFIG_PM
1043
1044static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
1045{
1046 struct spi_master *master = platform_get_drvdata(pdev);
1047 struct atmel_spi *as = spi_master_get_devdata(master);
1048
1049 clk_disable(as->clk);
1050 return 0;
1051}
1052
1053static int atmel_spi_resume(struct platform_device *pdev)
1054{
1055 struct spi_master *master = platform_get_drvdata(pdev);
1056 struct atmel_spi *as = spi_master_get_devdata(master);
1057
1058 clk_enable(as->clk);
1059 return 0;
1060}
1061
1062#else
1063#define atmel_spi_suspend NULL
1064#define atmel_spi_resume NULL
1065#endif
1066
1067
1068static struct platform_driver atmel_spi_driver = {
1069 .driver = {
1070 .name = "atmel_spi",
1071 .owner = THIS_MODULE,
1072 },
1073 .suspend = atmel_spi_suspend,
1074 .resume = atmel_spi_resume,
1075 .remove = __exit_p(atmel_spi_remove),
1076};
1077
1078static int __init atmel_spi_init(void)
1079{
1080 return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
1081}
1082module_init(atmel_spi_init);
1083
1084static void __exit atmel_spi_exit(void)
1085{
1086 platform_driver_unregister(&atmel_spi_driver);
1087}
1088module_exit(atmel_spi_exit);
1089
1090MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1091MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1092MODULE_LICENSE("GPL");
1093MODULE_ALIAS("platform:atmel_spi");
1/*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/delay.h>
16#include <linux/dma-mapping.h>
17#include <linux/dmaengine.h>
18#include <linux/err.h>
19#include <linux/interrupt.h>
20#include <linux/spi/spi.h>
21#include <linux/slab.h>
22#include <linux/platform_data/dma-atmel.h>
23#include <linux/of.h>
24
25#include <linux/io.h>
26#include <linux/gpio.h>
27#include <linux/of_gpio.h>
28#include <linux/pinctrl/consumer.h>
29#include <linux/pm_runtime.h>
30
31/* SPI register offsets */
32#define SPI_CR 0x0000
33#define SPI_MR 0x0004
34#define SPI_RDR 0x0008
35#define SPI_TDR 0x000c
36#define SPI_SR 0x0010
37#define SPI_IER 0x0014
38#define SPI_IDR 0x0018
39#define SPI_IMR 0x001c
40#define SPI_CSR0 0x0030
41#define SPI_CSR1 0x0034
42#define SPI_CSR2 0x0038
43#define SPI_CSR3 0x003c
44#define SPI_FMR 0x0040
45#define SPI_FLR 0x0044
46#define SPI_VERSION 0x00fc
47#define SPI_RPR 0x0100
48#define SPI_RCR 0x0104
49#define SPI_TPR 0x0108
50#define SPI_TCR 0x010c
51#define SPI_RNPR 0x0110
52#define SPI_RNCR 0x0114
53#define SPI_TNPR 0x0118
54#define SPI_TNCR 0x011c
55#define SPI_PTCR 0x0120
56#define SPI_PTSR 0x0124
57
58/* Bitfields in CR */
59#define SPI_SPIEN_OFFSET 0
60#define SPI_SPIEN_SIZE 1
61#define SPI_SPIDIS_OFFSET 1
62#define SPI_SPIDIS_SIZE 1
63#define SPI_SWRST_OFFSET 7
64#define SPI_SWRST_SIZE 1
65#define SPI_LASTXFER_OFFSET 24
66#define SPI_LASTXFER_SIZE 1
67#define SPI_TXFCLR_OFFSET 16
68#define SPI_TXFCLR_SIZE 1
69#define SPI_RXFCLR_OFFSET 17
70#define SPI_RXFCLR_SIZE 1
71#define SPI_FIFOEN_OFFSET 30
72#define SPI_FIFOEN_SIZE 1
73#define SPI_FIFODIS_OFFSET 31
74#define SPI_FIFODIS_SIZE 1
75
76/* Bitfields in MR */
77#define SPI_MSTR_OFFSET 0
78#define SPI_MSTR_SIZE 1
79#define SPI_PS_OFFSET 1
80#define SPI_PS_SIZE 1
81#define SPI_PCSDEC_OFFSET 2
82#define SPI_PCSDEC_SIZE 1
83#define SPI_FDIV_OFFSET 3
84#define SPI_FDIV_SIZE 1
85#define SPI_MODFDIS_OFFSET 4
86#define SPI_MODFDIS_SIZE 1
87#define SPI_WDRBT_OFFSET 5
88#define SPI_WDRBT_SIZE 1
89#define SPI_LLB_OFFSET 7
90#define SPI_LLB_SIZE 1
91#define SPI_PCS_OFFSET 16
92#define SPI_PCS_SIZE 4
93#define SPI_DLYBCS_OFFSET 24
94#define SPI_DLYBCS_SIZE 8
95
96/* Bitfields in RDR */
97#define SPI_RD_OFFSET 0
98#define SPI_RD_SIZE 16
99
100/* Bitfields in TDR */
101#define SPI_TD_OFFSET 0
102#define SPI_TD_SIZE 16
103
104/* Bitfields in SR */
105#define SPI_RDRF_OFFSET 0
106#define SPI_RDRF_SIZE 1
107#define SPI_TDRE_OFFSET 1
108#define SPI_TDRE_SIZE 1
109#define SPI_MODF_OFFSET 2
110#define SPI_MODF_SIZE 1
111#define SPI_OVRES_OFFSET 3
112#define SPI_OVRES_SIZE 1
113#define SPI_ENDRX_OFFSET 4
114#define SPI_ENDRX_SIZE 1
115#define SPI_ENDTX_OFFSET 5
116#define SPI_ENDTX_SIZE 1
117#define SPI_RXBUFF_OFFSET 6
118#define SPI_RXBUFF_SIZE 1
119#define SPI_TXBUFE_OFFSET 7
120#define SPI_TXBUFE_SIZE 1
121#define SPI_NSSR_OFFSET 8
122#define SPI_NSSR_SIZE 1
123#define SPI_TXEMPTY_OFFSET 9
124#define SPI_TXEMPTY_SIZE 1
125#define SPI_SPIENS_OFFSET 16
126#define SPI_SPIENS_SIZE 1
127#define SPI_TXFEF_OFFSET 24
128#define SPI_TXFEF_SIZE 1
129#define SPI_TXFFF_OFFSET 25
130#define SPI_TXFFF_SIZE 1
131#define SPI_TXFTHF_OFFSET 26
132#define SPI_TXFTHF_SIZE 1
133#define SPI_RXFEF_OFFSET 27
134#define SPI_RXFEF_SIZE 1
135#define SPI_RXFFF_OFFSET 28
136#define SPI_RXFFF_SIZE 1
137#define SPI_RXFTHF_OFFSET 29
138#define SPI_RXFTHF_SIZE 1
139#define SPI_TXFPTEF_OFFSET 30
140#define SPI_TXFPTEF_SIZE 1
141#define SPI_RXFPTEF_OFFSET 31
142#define SPI_RXFPTEF_SIZE 1
143
144/* Bitfields in CSR0 */
145#define SPI_CPOL_OFFSET 0
146#define SPI_CPOL_SIZE 1
147#define SPI_NCPHA_OFFSET 1
148#define SPI_NCPHA_SIZE 1
149#define SPI_CSAAT_OFFSET 3
150#define SPI_CSAAT_SIZE 1
151#define SPI_BITS_OFFSET 4
152#define SPI_BITS_SIZE 4
153#define SPI_SCBR_OFFSET 8
154#define SPI_SCBR_SIZE 8
155#define SPI_DLYBS_OFFSET 16
156#define SPI_DLYBS_SIZE 8
157#define SPI_DLYBCT_OFFSET 24
158#define SPI_DLYBCT_SIZE 8
159
160/* Bitfields in RCR */
161#define SPI_RXCTR_OFFSET 0
162#define SPI_RXCTR_SIZE 16
163
164/* Bitfields in TCR */
165#define SPI_TXCTR_OFFSET 0
166#define SPI_TXCTR_SIZE 16
167
168/* Bitfields in RNCR */
169#define SPI_RXNCR_OFFSET 0
170#define SPI_RXNCR_SIZE 16
171
172/* Bitfields in TNCR */
173#define SPI_TXNCR_OFFSET 0
174#define SPI_TXNCR_SIZE 16
175
176/* Bitfields in PTCR */
177#define SPI_RXTEN_OFFSET 0
178#define SPI_RXTEN_SIZE 1
179#define SPI_RXTDIS_OFFSET 1
180#define SPI_RXTDIS_SIZE 1
181#define SPI_TXTEN_OFFSET 8
182#define SPI_TXTEN_SIZE 1
183#define SPI_TXTDIS_OFFSET 9
184#define SPI_TXTDIS_SIZE 1
185
186/* Bitfields in FMR */
187#define SPI_TXRDYM_OFFSET 0
188#define SPI_TXRDYM_SIZE 2
189#define SPI_RXRDYM_OFFSET 4
190#define SPI_RXRDYM_SIZE 2
191#define SPI_TXFTHRES_OFFSET 16
192#define SPI_TXFTHRES_SIZE 6
193#define SPI_RXFTHRES_OFFSET 24
194#define SPI_RXFTHRES_SIZE 6
195
196/* Bitfields in FLR */
197#define SPI_TXFL_OFFSET 0
198#define SPI_TXFL_SIZE 6
199#define SPI_RXFL_OFFSET 16
200#define SPI_RXFL_SIZE 6
201
202/* Constants for BITS */
203#define SPI_BITS_8_BPT 0
204#define SPI_BITS_9_BPT 1
205#define SPI_BITS_10_BPT 2
206#define SPI_BITS_11_BPT 3
207#define SPI_BITS_12_BPT 4
208#define SPI_BITS_13_BPT 5
209#define SPI_BITS_14_BPT 6
210#define SPI_BITS_15_BPT 7
211#define SPI_BITS_16_BPT 8
212#define SPI_ONE_DATA 0
213#define SPI_TWO_DATA 1
214#define SPI_FOUR_DATA 2
215
216/* Bit manipulation macros */
217#define SPI_BIT(name) \
218 (1 << SPI_##name##_OFFSET)
219#define SPI_BF(name, value) \
220 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
221#define SPI_BFEXT(name, value) \
222 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
223#define SPI_BFINS(name, value, old) \
224 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
225 | SPI_BF(name, value))
226
227/* Register access macros */
228#ifdef CONFIG_AVR32
229#define spi_readl(port, reg) \
230 __raw_readl((port)->regs + SPI_##reg)
231#define spi_writel(port, reg, value) \
232 __raw_writel((value), (port)->regs + SPI_##reg)
233
234#define spi_readw(port, reg) \
235 __raw_readw((port)->regs + SPI_##reg)
236#define spi_writew(port, reg, value) \
237 __raw_writew((value), (port)->regs + SPI_##reg)
238
239#define spi_readb(port, reg) \
240 __raw_readb((port)->regs + SPI_##reg)
241#define spi_writeb(port, reg, value) \
242 __raw_writeb((value), (port)->regs + SPI_##reg)
243#else
244#define spi_readl(port, reg) \
245 readl_relaxed((port)->regs + SPI_##reg)
246#define spi_writel(port, reg, value) \
247 writel_relaxed((value), (port)->regs + SPI_##reg)
248
249#define spi_readw(port, reg) \
250 readw_relaxed((port)->regs + SPI_##reg)
251#define spi_writew(port, reg, value) \
252 writew_relaxed((value), (port)->regs + SPI_##reg)
253
254#define spi_readb(port, reg) \
255 readb_relaxed((port)->regs + SPI_##reg)
256#define spi_writeb(port, reg, value) \
257 writeb_relaxed((value), (port)->regs + SPI_##reg)
258#endif
259/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
260 * cache operations; better heuristics consider wordsize and bitrate.
261 */
262#define DMA_MIN_BYTES 16
263
264#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
265
266#define AUTOSUSPEND_TIMEOUT 2000
267
268struct atmel_spi_caps {
269 bool is_spi2;
270 bool has_wdrbt;
271 bool has_dma_support;
272};
273
274/*
275 * The core SPI transfer engine just talks to a register bank to set up
276 * DMA transfers; transfer queue progress is driven by IRQs. The clock
277 * framework provides the base clock, subdivided for each spi_device.
278 */
279struct atmel_spi {
280 spinlock_t lock;
281 unsigned long flags;
282
283 phys_addr_t phybase;
284 void __iomem *regs;
285 int irq;
286 struct clk *clk;
287 struct platform_device *pdev;
288 unsigned long spi_clk;
289
290 struct spi_transfer *current_transfer;
291 int current_remaining_bytes;
292 int done_status;
293
294 struct completion xfer_completion;
295
296 struct atmel_spi_caps caps;
297
298 bool use_dma;
299 bool use_pdc;
300 bool use_cs_gpios;
301
302 bool keep_cs;
303 bool cs_active;
304
305 u32 fifo_size;
306};
307
308/* Controller-specific per-slave state */
309struct atmel_spi_device {
310 unsigned int npcs_pin;
311 u32 csr;
312};
313
314#define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
315#define INVALID_DMA_ADDRESS 0xffffffff
316
317/*
318 * Version 2 of the SPI controller has
319 * - CR.LASTXFER
320 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
321 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
322 * - SPI_CSRx.CSAAT
323 * - SPI_CSRx.SBCR allows faster clocking
324 */
325static bool atmel_spi_is_v2(struct atmel_spi *as)
326{
327 return as->caps.is_spi2;
328}
329
330/*
331 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
332 * they assume that spi slave device state will not change on deselect, so
333 * that automagic deselection is OK. ("NPCSx rises if no data is to be
334 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
335 * controllers have CSAAT and friends.
336 *
337 * Since the CSAAT functionality is a bit weird on newer controllers as
338 * well, we use GPIO to control nCSx pins on all controllers, updating
339 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
340 * support active-high chipselects despite the controller's belief that
341 * only active-low devices/systems exists.
342 *
343 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
344 * right when driven with GPIO. ("Mode Fault does not allow more than one
345 * Master on Chip Select 0.") No workaround exists for that ... so for
346 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
347 * and (c) will trigger that first erratum in some cases.
348 */
349
350static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
351{
352 struct atmel_spi_device *asd = spi->controller_state;
353 unsigned active = spi->mode & SPI_CS_HIGH;
354 u32 mr;
355
356 if (atmel_spi_is_v2(as)) {
357 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
358 /* For the low SPI version, there is a issue that PDC transfer
359 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
360 */
361 spi_writel(as, CSR0, asd->csr);
362 if (as->caps.has_wdrbt) {
363 spi_writel(as, MR,
364 SPI_BF(PCS, ~(0x01 << spi->chip_select))
365 | SPI_BIT(WDRBT)
366 | SPI_BIT(MODFDIS)
367 | SPI_BIT(MSTR));
368 } else {
369 spi_writel(as, MR,
370 SPI_BF(PCS, ~(0x01 << spi->chip_select))
371 | SPI_BIT(MODFDIS)
372 | SPI_BIT(MSTR));
373 }
374
375 mr = spi_readl(as, MR);
376 if (as->use_cs_gpios)
377 gpio_set_value(asd->npcs_pin, active);
378 } else {
379 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
380 int i;
381 u32 csr;
382
383 /* Make sure clock polarity is correct */
384 for (i = 0; i < spi->master->num_chipselect; i++) {
385 csr = spi_readl(as, CSR0 + 4 * i);
386 if ((csr ^ cpol) & SPI_BIT(CPOL))
387 spi_writel(as, CSR0 + 4 * i,
388 csr ^ SPI_BIT(CPOL));
389 }
390
391 mr = spi_readl(as, MR);
392 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
393 if (as->use_cs_gpios && spi->chip_select != 0)
394 gpio_set_value(asd->npcs_pin, active);
395 spi_writel(as, MR, mr);
396 }
397
398 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
399 asd->npcs_pin, active ? " (high)" : "",
400 mr);
401}
402
403static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
404{
405 struct atmel_spi_device *asd = spi->controller_state;
406 unsigned active = spi->mode & SPI_CS_HIGH;
407 u32 mr;
408
409 /* only deactivate *this* device; sometimes transfers to
410 * another device may be active when this routine is called.
411 */
412 mr = spi_readl(as, MR);
413 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
414 mr = SPI_BFINS(PCS, 0xf, mr);
415 spi_writel(as, MR, mr);
416 }
417
418 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
419 asd->npcs_pin, active ? " (low)" : "",
420 mr);
421
422 if (!as->use_cs_gpios)
423 spi_writel(as, CR, SPI_BIT(LASTXFER));
424 else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
425 gpio_set_value(asd->npcs_pin, !active);
426}
427
428static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
429{
430 spin_lock_irqsave(&as->lock, as->flags);
431}
432
433static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
434{
435 spin_unlock_irqrestore(&as->lock, as->flags);
436}
437
438static inline bool atmel_spi_use_dma(struct atmel_spi *as,
439 struct spi_transfer *xfer)
440{
441 return as->use_dma && xfer->len >= DMA_MIN_BYTES;
442}
443
444static bool atmel_spi_can_dma(struct spi_master *master,
445 struct spi_device *spi,
446 struct spi_transfer *xfer)
447{
448 struct atmel_spi *as = spi_master_get_devdata(master);
449
450 return atmel_spi_use_dma(as, xfer);
451}
452
453static int atmel_spi_dma_slave_config(struct atmel_spi *as,
454 struct dma_slave_config *slave_config,
455 u8 bits_per_word)
456{
457 struct spi_master *master = platform_get_drvdata(as->pdev);
458 int err = 0;
459
460 if (bits_per_word > 8) {
461 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
462 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
463 } else {
464 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
465 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
466 }
467
468 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
469 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
470 slave_config->src_maxburst = 1;
471 slave_config->dst_maxburst = 1;
472 slave_config->device_fc = false;
473
474 /*
475 * This driver uses fixed peripheral select mode (PS bit set to '0' in
476 * the Mode Register).
477 * So according to the datasheet, when FIFOs are available (and
478 * enabled), the Transmit FIFO operates in Multiple Data Mode.
479 * In this mode, up to 2 data, not 4, can be written into the Transmit
480 * Data Register in a single access.
481 * However, the first data has to be written into the lowest 16 bits and
482 * the second data into the highest 16 bits of the Transmit
483 * Data Register. For 8bit data (the most frequent case), it would
484 * require to rework tx_buf so each data would actualy fit 16 bits.
485 * So we'd rather write only one data at the time. Hence the transmit
486 * path works the same whether FIFOs are available (and enabled) or not.
487 */
488 slave_config->direction = DMA_MEM_TO_DEV;
489 if (dmaengine_slave_config(master->dma_tx, slave_config)) {
490 dev_err(&as->pdev->dev,
491 "failed to configure tx dma channel\n");
492 err = -EINVAL;
493 }
494
495 /*
496 * This driver configures the spi controller for master mode (MSTR bit
497 * set to '1' in the Mode Register).
498 * So according to the datasheet, when FIFOs are available (and
499 * enabled), the Receive FIFO operates in Single Data Mode.
500 * So the receive path works the same whether FIFOs are available (and
501 * enabled) or not.
502 */
503 slave_config->direction = DMA_DEV_TO_MEM;
504 if (dmaengine_slave_config(master->dma_rx, slave_config)) {
505 dev_err(&as->pdev->dev,
506 "failed to configure rx dma channel\n");
507 err = -EINVAL;
508 }
509
510 return err;
511}
512
513static int atmel_spi_configure_dma(struct spi_master *master,
514 struct atmel_spi *as)
515{
516 struct dma_slave_config slave_config;
517 struct device *dev = &as->pdev->dev;
518 int err;
519
520 dma_cap_mask_t mask;
521 dma_cap_zero(mask);
522 dma_cap_set(DMA_SLAVE, mask);
523
524 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
525 if (IS_ERR(master->dma_tx)) {
526 err = PTR_ERR(master->dma_tx);
527 if (err == -EPROBE_DEFER) {
528 dev_warn(dev, "no DMA channel available at the moment\n");
529 goto error_clear;
530 }
531 dev_err(dev,
532 "DMA TX channel not available, SPI unable to use DMA\n");
533 err = -EBUSY;
534 goto error_clear;
535 }
536
537 /*
538 * No reason to check EPROBE_DEFER here since we have already requested
539 * tx channel. If it fails here, it's for another reason.
540 */
541 master->dma_rx = dma_request_slave_channel(dev, "rx");
542
543 if (!master->dma_rx) {
544 dev_err(dev,
545 "DMA RX channel not available, SPI unable to use DMA\n");
546 err = -EBUSY;
547 goto error;
548 }
549
550 err = atmel_spi_dma_slave_config(as, &slave_config, 8);
551 if (err)
552 goto error;
553
554 dev_info(&as->pdev->dev,
555 "Using %s (tx) and %s (rx) for DMA transfers\n",
556 dma_chan_name(master->dma_tx),
557 dma_chan_name(master->dma_rx));
558
559 return 0;
560error:
561 if (master->dma_rx)
562 dma_release_channel(master->dma_rx);
563 if (!IS_ERR(master->dma_tx))
564 dma_release_channel(master->dma_tx);
565error_clear:
566 master->dma_tx = master->dma_rx = NULL;
567 return err;
568}
569
570static void atmel_spi_stop_dma(struct spi_master *master)
571{
572 if (master->dma_rx)
573 dmaengine_terminate_all(master->dma_rx);
574 if (master->dma_tx)
575 dmaengine_terminate_all(master->dma_tx);
576}
577
578static void atmel_spi_release_dma(struct spi_master *master)
579{
580 if (master->dma_rx) {
581 dma_release_channel(master->dma_rx);
582 master->dma_rx = NULL;
583 }
584 if (master->dma_tx) {
585 dma_release_channel(master->dma_tx);
586 master->dma_tx = NULL;
587 }
588}
589
590/* This function is called by the DMA driver from tasklet context */
591static void dma_callback(void *data)
592{
593 struct spi_master *master = data;
594 struct atmel_spi *as = spi_master_get_devdata(master);
595
596 complete(&as->xfer_completion);
597}
598
599/*
600 * Next transfer using PIO without FIFO.
601 */
602static void atmel_spi_next_xfer_single(struct spi_master *master,
603 struct spi_transfer *xfer)
604{
605 struct atmel_spi *as = spi_master_get_devdata(master);
606 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
607
608 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
609
610 /* Make sure data is not remaining in RDR */
611 spi_readl(as, RDR);
612 while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
613 spi_readl(as, RDR);
614 cpu_relax();
615 }
616
617 if (xfer->bits_per_word > 8)
618 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
619 else
620 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
621
622 dev_dbg(master->dev.parent,
623 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
624 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
625 xfer->bits_per_word);
626
627 /* Enable relevant interrupts */
628 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
629}
630
631/*
632 * Next transfer using PIO with FIFO.
633 */
634static void atmel_spi_next_xfer_fifo(struct spi_master *master,
635 struct spi_transfer *xfer)
636{
637 struct atmel_spi *as = spi_master_get_devdata(master);
638 u32 current_remaining_data, num_data;
639 u32 offset = xfer->len - as->current_remaining_bytes;
640 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
641 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
642 u16 td0, td1;
643 u32 fifomr;
644
645 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
646
647 /* Compute the number of data to transfer in the current iteration */
648 current_remaining_data = ((xfer->bits_per_word > 8) ?
649 ((u32)as->current_remaining_bytes >> 1) :
650 (u32)as->current_remaining_bytes);
651 num_data = min(current_remaining_data, as->fifo_size);
652
653 /* Flush RX and TX FIFOs */
654 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
655 while (spi_readl(as, FLR))
656 cpu_relax();
657
658 /* Set RX FIFO Threshold to the number of data to transfer */
659 fifomr = spi_readl(as, FMR);
660 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
661
662 /* Clear FIFO flags in the Status Register, especially RXFTHF */
663 (void)spi_readl(as, SR);
664
665 /* Fill TX FIFO */
666 while (num_data >= 2) {
667 if (xfer->bits_per_word > 8) {
668 td0 = *words++;
669 td1 = *words++;
670 } else {
671 td0 = *bytes++;
672 td1 = *bytes++;
673 }
674
675 spi_writel(as, TDR, (td1 << 16) | td0);
676 num_data -= 2;
677 }
678
679 if (num_data) {
680 if (xfer->bits_per_word > 8)
681 td0 = *words++;
682 else
683 td0 = *bytes++;
684
685 spi_writew(as, TDR, td0);
686 num_data--;
687 }
688
689 dev_dbg(master->dev.parent,
690 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
691 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
692 xfer->bits_per_word);
693
694 /*
695 * Enable RX FIFO Threshold Flag interrupt to be notified about
696 * transfer completion.
697 */
698 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
699}
700
701/*
702 * Next transfer using PIO.
703 */
704static void atmel_spi_next_xfer_pio(struct spi_master *master,
705 struct spi_transfer *xfer)
706{
707 struct atmel_spi *as = spi_master_get_devdata(master);
708
709 if (as->fifo_size)
710 atmel_spi_next_xfer_fifo(master, xfer);
711 else
712 atmel_spi_next_xfer_single(master, xfer);
713}
714
715/*
716 * Submit next transfer for DMA.
717 */
718static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
719 struct spi_transfer *xfer,
720 u32 *plen)
721{
722 struct atmel_spi *as = spi_master_get_devdata(master);
723 struct dma_chan *rxchan = master->dma_rx;
724 struct dma_chan *txchan = master->dma_tx;
725 struct dma_async_tx_descriptor *rxdesc;
726 struct dma_async_tx_descriptor *txdesc;
727 struct dma_slave_config slave_config;
728 dma_cookie_t cookie;
729
730 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
731
732 /* Check that the channels are available */
733 if (!rxchan || !txchan)
734 return -ENODEV;
735
736 /* release lock for DMA operations */
737 atmel_spi_unlock(as);
738
739 *plen = xfer->len;
740
741 if (atmel_spi_dma_slave_config(as, &slave_config,
742 xfer->bits_per_word))
743 goto err_exit;
744
745 /* Send both scatterlists */
746 rxdesc = dmaengine_prep_slave_sg(rxchan,
747 xfer->rx_sg.sgl, xfer->rx_sg.nents,
748 DMA_FROM_DEVICE,
749 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
750 if (!rxdesc)
751 goto err_dma;
752
753 txdesc = dmaengine_prep_slave_sg(txchan,
754 xfer->tx_sg.sgl, xfer->tx_sg.nents,
755 DMA_TO_DEVICE,
756 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
757 if (!txdesc)
758 goto err_dma;
759
760 dev_dbg(master->dev.parent,
761 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
762 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
763 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
764
765 /* Enable relevant interrupts */
766 spi_writel(as, IER, SPI_BIT(OVRES));
767
768 /* Put the callback on the RX transfer only, that should finish last */
769 rxdesc->callback = dma_callback;
770 rxdesc->callback_param = master;
771
772 /* Submit and fire RX and TX with TX last so we're ready to read! */
773 cookie = rxdesc->tx_submit(rxdesc);
774 if (dma_submit_error(cookie))
775 goto err_dma;
776 cookie = txdesc->tx_submit(txdesc);
777 if (dma_submit_error(cookie))
778 goto err_dma;
779 rxchan->device->device_issue_pending(rxchan);
780 txchan->device->device_issue_pending(txchan);
781
782 /* take back lock */
783 atmel_spi_lock(as);
784 return 0;
785
786err_dma:
787 spi_writel(as, IDR, SPI_BIT(OVRES));
788 atmel_spi_stop_dma(master);
789err_exit:
790 atmel_spi_lock(as);
791 return -ENOMEM;
792}
793
794static void atmel_spi_next_xfer_data(struct spi_master *master,
795 struct spi_transfer *xfer,
796 dma_addr_t *tx_dma,
797 dma_addr_t *rx_dma,
798 u32 *plen)
799{
800 *rx_dma = xfer->rx_dma + xfer->len - *plen;
801 *tx_dma = xfer->tx_dma + xfer->len - *plen;
802 if (*plen > master->max_dma_len)
803 *plen = master->max_dma_len;
804}
805
806static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
807 struct spi_device *spi,
808 struct spi_transfer *xfer)
809{
810 u32 scbr, csr;
811 unsigned long bus_hz;
812
813 /* v1 chips start out at half the peripheral bus speed. */
814 bus_hz = as->spi_clk;
815 if (!atmel_spi_is_v2(as))
816 bus_hz /= 2;
817
818 /*
819 * Calculate the lowest divider that satisfies the
820 * constraint, assuming div32/fdiv/mbz == 0.
821 */
822 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
823
824 /*
825 * If the resulting divider doesn't fit into the
826 * register bitfield, we can't satisfy the constraint.
827 */
828 if (scbr >= (1 << SPI_SCBR_SIZE)) {
829 dev_err(&spi->dev,
830 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
831 xfer->speed_hz, scbr, bus_hz/255);
832 return -EINVAL;
833 }
834 if (scbr == 0) {
835 dev_err(&spi->dev,
836 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
837 xfer->speed_hz, scbr, bus_hz);
838 return -EINVAL;
839 }
840 csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
841 csr = SPI_BFINS(SCBR, scbr, csr);
842 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
843
844 return 0;
845}
846
847/*
848 * Submit next transfer for PDC.
849 * lock is held, spi irq is blocked
850 */
851static void atmel_spi_pdc_next_xfer(struct spi_master *master,
852 struct spi_message *msg,
853 struct spi_transfer *xfer)
854{
855 struct atmel_spi *as = spi_master_get_devdata(master);
856 u32 len;
857 dma_addr_t tx_dma, rx_dma;
858
859 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
860
861 len = as->current_remaining_bytes;
862 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
863 as->current_remaining_bytes -= len;
864
865 spi_writel(as, RPR, rx_dma);
866 spi_writel(as, TPR, tx_dma);
867
868 if (msg->spi->bits_per_word > 8)
869 len >>= 1;
870 spi_writel(as, RCR, len);
871 spi_writel(as, TCR, len);
872
873 dev_dbg(&msg->spi->dev,
874 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
875 xfer, xfer->len, xfer->tx_buf,
876 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
877 (unsigned long long)xfer->rx_dma);
878
879 if (as->current_remaining_bytes) {
880 len = as->current_remaining_bytes;
881 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
882 as->current_remaining_bytes -= len;
883
884 spi_writel(as, RNPR, rx_dma);
885 spi_writel(as, TNPR, tx_dma);
886
887 if (msg->spi->bits_per_word > 8)
888 len >>= 1;
889 spi_writel(as, RNCR, len);
890 spi_writel(as, TNCR, len);
891
892 dev_dbg(&msg->spi->dev,
893 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
894 xfer, xfer->len, xfer->tx_buf,
895 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
896 (unsigned long long)xfer->rx_dma);
897 }
898
899 /* REVISIT: We're waiting for RXBUFF before we start the next
900 * transfer because we need to handle some difficult timing
901 * issues otherwise. If we wait for TXBUFE in one transfer and
902 * then starts waiting for RXBUFF in the next, it's difficult
903 * to tell the difference between the RXBUFF interrupt we're
904 * actually waiting for and the RXBUFF interrupt of the
905 * previous transfer.
906 *
907 * It should be doable, though. Just not now...
908 */
909 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
910 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
911}
912
913/*
914 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
915 * - The buffer is either valid for CPU access, else NULL
916 * - If the buffer is valid, so is its DMA address
917 *
918 * This driver manages the dma address unless message->is_dma_mapped.
919 */
920static int
921atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
922{
923 struct device *dev = &as->pdev->dev;
924
925 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
926 if (xfer->tx_buf) {
927 /* tx_buf is a const void* where we need a void * for the dma
928 * mapping */
929 void *nonconst_tx = (void *)xfer->tx_buf;
930
931 xfer->tx_dma = dma_map_single(dev,
932 nonconst_tx, xfer->len,
933 DMA_TO_DEVICE);
934 if (dma_mapping_error(dev, xfer->tx_dma))
935 return -ENOMEM;
936 }
937 if (xfer->rx_buf) {
938 xfer->rx_dma = dma_map_single(dev,
939 xfer->rx_buf, xfer->len,
940 DMA_FROM_DEVICE);
941 if (dma_mapping_error(dev, xfer->rx_dma)) {
942 if (xfer->tx_buf)
943 dma_unmap_single(dev,
944 xfer->tx_dma, xfer->len,
945 DMA_TO_DEVICE);
946 return -ENOMEM;
947 }
948 }
949 return 0;
950}
951
952static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
953 struct spi_transfer *xfer)
954{
955 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
956 dma_unmap_single(master->dev.parent, xfer->tx_dma,
957 xfer->len, DMA_TO_DEVICE);
958 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
959 dma_unmap_single(master->dev.parent, xfer->rx_dma,
960 xfer->len, DMA_FROM_DEVICE);
961}
962
963static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
964{
965 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
966}
967
968static void
969atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
970{
971 u8 *rxp;
972 u16 *rxp16;
973 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
974
975 if (xfer->bits_per_word > 8) {
976 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
977 *rxp16 = spi_readl(as, RDR);
978 } else {
979 rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
980 *rxp = spi_readl(as, RDR);
981 }
982 if (xfer->bits_per_word > 8) {
983 if (as->current_remaining_bytes > 2)
984 as->current_remaining_bytes -= 2;
985 else
986 as->current_remaining_bytes = 0;
987 } else {
988 as->current_remaining_bytes--;
989 }
990}
991
992static void
993atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
994{
995 u32 fifolr = spi_readl(as, FLR);
996 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
997 u32 offset = xfer->len - as->current_remaining_bytes;
998 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
999 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
1000 u16 rd; /* RD field is the lowest 16 bits of RDR */
1001
1002 /* Update the number of remaining bytes to transfer */
1003 num_bytes = ((xfer->bits_per_word > 8) ?
1004 (num_data << 1) :
1005 num_data);
1006
1007 if (as->current_remaining_bytes > num_bytes)
1008 as->current_remaining_bytes -= num_bytes;
1009 else
1010 as->current_remaining_bytes = 0;
1011
1012 /* Handle odd number of bytes when data are more than 8bit width */
1013 if (xfer->bits_per_word > 8)
1014 as->current_remaining_bytes &= ~0x1;
1015
1016 /* Read data */
1017 while (num_data) {
1018 rd = spi_readl(as, RDR);
1019 if (xfer->bits_per_word > 8)
1020 *words++ = rd;
1021 else
1022 *bytes++ = rd;
1023 num_data--;
1024 }
1025}
1026
1027/* Called from IRQ
1028 *
1029 * Must update "current_remaining_bytes" to keep track of data
1030 * to transfer.
1031 */
1032static void
1033atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
1034{
1035 if (as->fifo_size)
1036 atmel_spi_pump_fifo_data(as, xfer);
1037 else
1038 atmel_spi_pump_single_data(as, xfer);
1039}
1040
1041/* Interrupt
1042 *
1043 * No need for locking in this Interrupt handler: done_status is the
1044 * only information modified.
1045 */
1046static irqreturn_t
1047atmel_spi_pio_interrupt(int irq, void *dev_id)
1048{
1049 struct spi_master *master = dev_id;
1050 struct atmel_spi *as = spi_master_get_devdata(master);
1051 u32 status, pending, imr;
1052 struct spi_transfer *xfer;
1053 int ret = IRQ_NONE;
1054
1055 imr = spi_readl(as, IMR);
1056 status = spi_readl(as, SR);
1057 pending = status & imr;
1058
1059 if (pending & SPI_BIT(OVRES)) {
1060 ret = IRQ_HANDLED;
1061 spi_writel(as, IDR, SPI_BIT(OVRES));
1062 dev_warn(master->dev.parent, "overrun\n");
1063
1064 /*
1065 * When we get an overrun, we disregard the current
1066 * transfer. Data will not be copied back from any
1067 * bounce buffer and msg->actual_len will not be
1068 * updated with the last xfer.
1069 *
1070 * We will also not process any remaning transfers in
1071 * the message.
1072 */
1073 as->done_status = -EIO;
1074 smp_wmb();
1075
1076 /* Clear any overrun happening while cleaning up */
1077 spi_readl(as, SR);
1078
1079 complete(&as->xfer_completion);
1080
1081 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
1082 atmel_spi_lock(as);
1083
1084 if (as->current_remaining_bytes) {
1085 ret = IRQ_HANDLED;
1086 xfer = as->current_transfer;
1087 atmel_spi_pump_pio_data(as, xfer);
1088 if (!as->current_remaining_bytes)
1089 spi_writel(as, IDR, pending);
1090
1091 complete(&as->xfer_completion);
1092 }
1093
1094 atmel_spi_unlock(as);
1095 } else {
1096 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
1097 ret = IRQ_HANDLED;
1098 spi_writel(as, IDR, pending);
1099 }
1100
1101 return ret;
1102}
1103
1104static irqreturn_t
1105atmel_spi_pdc_interrupt(int irq, void *dev_id)
1106{
1107 struct spi_master *master = dev_id;
1108 struct atmel_spi *as = spi_master_get_devdata(master);
1109 u32 status, pending, imr;
1110 int ret = IRQ_NONE;
1111
1112 imr = spi_readl(as, IMR);
1113 status = spi_readl(as, SR);
1114 pending = status & imr;
1115
1116 if (pending & SPI_BIT(OVRES)) {
1117
1118 ret = IRQ_HANDLED;
1119
1120 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
1121 | SPI_BIT(OVRES)));
1122
1123 /* Clear any overrun happening while cleaning up */
1124 spi_readl(as, SR);
1125
1126 as->done_status = -EIO;
1127
1128 complete(&as->xfer_completion);
1129
1130 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
1131 ret = IRQ_HANDLED;
1132
1133 spi_writel(as, IDR, pending);
1134
1135 complete(&as->xfer_completion);
1136 }
1137
1138 return ret;
1139}
1140
1141static int atmel_spi_setup(struct spi_device *spi)
1142{
1143 struct atmel_spi *as;
1144 struct atmel_spi_device *asd;
1145 u32 csr;
1146 unsigned int bits = spi->bits_per_word;
1147 unsigned int npcs_pin;
1148
1149 as = spi_master_get_devdata(spi->master);
1150
1151 /* see notes above re chipselect */
1152 if (!atmel_spi_is_v2(as)
1153 && spi->chip_select == 0
1154 && (spi->mode & SPI_CS_HIGH)) {
1155 dev_dbg(&spi->dev, "setup: can't be active-high\n");
1156 return -EINVAL;
1157 }
1158
1159 csr = SPI_BF(BITS, bits - 8);
1160 if (spi->mode & SPI_CPOL)
1161 csr |= SPI_BIT(CPOL);
1162 if (!(spi->mode & SPI_CPHA))
1163 csr |= SPI_BIT(NCPHA);
1164 if (!as->use_cs_gpios)
1165 csr |= SPI_BIT(CSAAT);
1166
1167 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1168 *
1169 * DLYBCT would add delays between words, slowing down transfers.
1170 * It could potentially be useful to cope with DMA bottlenecks, but
1171 * in those cases it's probably best to just use a lower bitrate.
1172 */
1173 csr |= SPI_BF(DLYBS, 0);
1174 csr |= SPI_BF(DLYBCT, 0);
1175
1176 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1177 npcs_pin = (unsigned long)spi->controller_data;
1178
1179 if (!as->use_cs_gpios)
1180 npcs_pin = spi->chip_select;
1181 else if (gpio_is_valid(spi->cs_gpio))
1182 npcs_pin = spi->cs_gpio;
1183
1184 asd = spi->controller_state;
1185 if (!asd) {
1186 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1187 if (!asd)
1188 return -ENOMEM;
1189
1190 if (as->use_cs_gpios)
1191 gpio_direction_output(npcs_pin,
1192 !(spi->mode & SPI_CS_HIGH));
1193
1194 asd->npcs_pin = npcs_pin;
1195 spi->controller_state = asd;
1196 }
1197
1198 asd->csr = csr;
1199
1200 dev_dbg(&spi->dev,
1201 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1202 bits, spi->mode, spi->chip_select, csr);
1203
1204 if (!atmel_spi_is_v2(as))
1205 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1206
1207 return 0;
1208}
1209
1210static int atmel_spi_one_transfer(struct spi_master *master,
1211 struct spi_message *msg,
1212 struct spi_transfer *xfer)
1213{
1214 struct atmel_spi *as;
1215 struct spi_device *spi = msg->spi;
1216 u8 bits;
1217 u32 len;
1218 struct atmel_spi_device *asd;
1219 int timeout;
1220 int ret;
1221 unsigned long dma_timeout;
1222
1223 as = spi_master_get_devdata(master);
1224
1225 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1226 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1227 return -EINVAL;
1228 }
1229
1230 asd = spi->controller_state;
1231 bits = (asd->csr >> 4) & 0xf;
1232 if (bits != xfer->bits_per_word - 8) {
1233 dev_dbg(&spi->dev,
1234 "you can't yet change bits_per_word in transfers\n");
1235 return -ENOPROTOOPT;
1236 }
1237
1238 /*
1239 * DMA map early, for performance (empties dcache ASAP) and
1240 * better fault reporting.
1241 */
1242 if ((!msg->is_dma_mapped)
1243 && as->use_pdc) {
1244 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1245 return -ENOMEM;
1246 }
1247
1248 atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1249
1250 as->done_status = 0;
1251 as->current_transfer = xfer;
1252 as->current_remaining_bytes = xfer->len;
1253 while (as->current_remaining_bytes) {
1254 reinit_completion(&as->xfer_completion);
1255
1256 if (as->use_pdc) {
1257 atmel_spi_pdc_next_xfer(master, msg, xfer);
1258 } else if (atmel_spi_use_dma(as, xfer)) {
1259 len = as->current_remaining_bytes;
1260 ret = atmel_spi_next_xfer_dma_submit(master,
1261 xfer, &len);
1262 if (ret) {
1263 dev_err(&spi->dev,
1264 "unable to use DMA, fallback to PIO\n");
1265 atmel_spi_next_xfer_pio(master, xfer);
1266 } else {
1267 as->current_remaining_bytes -= len;
1268 if (as->current_remaining_bytes < 0)
1269 as->current_remaining_bytes = 0;
1270 }
1271 } else {
1272 atmel_spi_next_xfer_pio(master, xfer);
1273 }
1274
1275 /* interrupts are disabled, so free the lock for schedule */
1276 atmel_spi_unlock(as);
1277 dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
1278 SPI_DMA_TIMEOUT);
1279 atmel_spi_lock(as);
1280 if (WARN_ON(dma_timeout == 0)) {
1281 dev_err(&spi->dev, "spi transfer timeout\n");
1282 as->done_status = -EIO;
1283 }
1284
1285 if (as->done_status)
1286 break;
1287 }
1288
1289 if (as->done_status) {
1290 if (as->use_pdc) {
1291 dev_warn(master->dev.parent,
1292 "overrun (%u/%u remaining)\n",
1293 spi_readl(as, TCR), spi_readl(as, RCR));
1294
1295 /*
1296 * Clean up DMA registers and make sure the data
1297 * registers are empty.
1298 */
1299 spi_writel(as, RNCR, 0);
1300 spi_writel(as, TNCR, 0);
1301 spi_writel(as, RCR, 0);
1302 spi_writel(as, TCR, 0);
1303 for (timeout = 1000; timeout; timeout--)
1304 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1305 break;
1306 if (!timeout)
1307 dev_warn(master->dev.parent,
1308 "timeout waiting for TXEMPTY");
1309 while (spi_readl(as, SR) & SPI_BIT(RDRF))
1310 spi_readl(as, RDR);
1311
1312 /* Clear any overrun happening while cleaning up */
1313 spi_readl(as, SR);
1314
1315 } else if (atmel_spi_use_dma(as, xfer)) {
1316 atmel_spi_stop_dma(master);
1317 }
1318
1319 if (!msg->is_dma_mapped
1320 && as->use_pdc)
1321 atmel_spi_dma_unmap_xfer(master, xfer);
1322
1323 return 0;
1324
1325 } else {
1326 /* only update length if no error */
1327 msg->actual_length += xfer->len;
1328 }
1329
1330 if (!msg->is_dma_mapped
1331 && as->use_pdc)
1332 atmel_spi_dma_unmap_xfer(master, xfer);
1333
1334 if (xfer->delay_usecs)
1335 udelay(xfer->delay_usecs);
1336
1337 if (xfer->cs_change) {
1338 if (list_is_last(&xfer->transfer_list,
1339 &msg->transfers)) {
1340 as->keep_cs = true;
1341 } else {
1342 as->cs_active = !as->cs_active;
1343 if (as->cs_active)
1344 cs_activate(as, msg->spi);
1345 else
1346 cs_deactivate(as, msg->spi);
1347 }
1348 }
1349
1350 return 0;
1351}
1352
1353static int atmel_spi_transfer_one_message(struct spi_master *master,
1354 struct spi_message *msg)
1355{
1356 struct atmel_spi *as;
1357 struct spi_transfer *xfer;
1358 struct spi_device *spi = msg->spi;
1359 int ret = 0;
1360
1361 as = spi_master_get_devdata(master);
1362
1363 dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1364 msg, dev_name(&spi->dev));
1365
1366 atmel_spi_lock(as);
1367 cs_activate(as, spi);
1368
1369 as->cs_active = true;
1370 as->keep_cs = false;
1371
1372 msg->status = 0;
1373 msg->actual_length = 0;
1374
1375 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1376 ret = atmel_spi_one_transfer(master, msg, xfer);
1377 if (ret)
1378 goto msg_done;
1379 }
1380
1381 if (as->use_pdc)
1382 atmel_spi_disable_pdc_transfer(as);
1383
1384 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1385 dev_dbg(&spi->dev,
1386 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1387 xfer, xfer->len,
1388 xfer->tx_buf, &xfer->tx_dma,
1389 xfer->rx_buf, &xfer->rx_dma);
1390 }
1391
1392msg_done:
1393 if (!as->keep_cs)
1394 cs_deactivate(as, msg->spi);
1395
1396 atmel_spi_unlock(as);
1397
1398 msg->status = as->done_status;
1399 spi_finalize_current_message(spi->master);
1400
1401 return ret;
1402}
1403
1404static void atmel_spi_cleanup(struct spi_device *spi)
1405{
1406 struct atmel_spi_device *asd = spi->controller_state;
1407
1408 if (!asd)
1409 return;
1410
1411 spi->controller_state = NULL;
1412 kfree(asd);
1413}
1414
1415static inline unsigned int atmel_get_version(struct atmel_spi *as)
1416{
1417 return spi_readl(as, VERSION) & 0x00000fff;
1418}
1419
1420static void atmel_get_caps(struct atmel_spi *as)
1421{
1422 unsigned int version;
1423
1424 version = atmel_get_version(as);
1425 dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1426
1427 as->caps.is_spi2 = version > 0x121;
1428 as->caps.has_wdrbt = version >= 0x210;
1429 as->caps.has_dma_support = version >= 0x212;
1430}
1431
1432/*-------------------------------------------------------------------------*/
1433static int atmel_spi_gpio_cs(struct platform_device *pdev)
1434{
1435 struct spi_master *master = platform_get_drvdata(pdev);
1436 struct atmel_spi *as = spi_master_get_devdata(master);
1437 struct device_node *np = master->dev.of_node;
1438 int i;
1439 int ret = 0;
1440 int nb = 0;
1441
1442 if (!as->use_cs_gpios)
1443 return 0;
1444
1445 if (!np)
1446 return 0;
1447
1448 nb = of_gpio_named_count(np, "cs-gpios");
1449 for (i = 0; i < nb; i++) {
1450 int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
1451 "cs-gpios", i);
1452
1453 if (cs_gpio == -EPROBE_DEFER)
1454 return cs_gpio;
1455
1456 if (gpio_is_valid(cs_gpio)) {
1457 ret = devm_gpio_request(&pdev->dev, cs_gpio,
1458 dev_name(&pdev->dev));
1459 if (ret)
1460 return ret;
1461 }
1462 }
1463
1464 return 0;
1465}
1466
1467static int atmel_spi_probe(struct platform_device *pdev)
1468{
1469 struct resource *regs;
1470 int irq;
1471 struct clk *clk;
1472 int ret;
1473 struct spi_master *master;
1474 struct atmel_spi *as;
1475
1476 /* Select default pin state */
1477 pinctrl_pm_select_default_state(&pdev->dev);
1478
1479 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1480 if (!regs)
1481 return -ENXIO;
1482
1483 irq = platform_get_irq(pdev, 0);
1484 if (irq < 0)
1485 return irq;
1486
1487 clk = devm_clk_get(&pdev->dev, "spi_clk");
1488 if (IS_ERR(clk))
1489 return PTR_ERR(clk);
1490
1491 /* setup spi core then atmel-specific driver state */
1492 ret = -ENOMEM;
1493 master = spi_alloc_master(&pdev->dev, sizeof(*as));
1494 if (!master)
1495 goto out_free;
1496
1497 /* the spi->mode bits understood by this driver: */
1498 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1499 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1500 master->dev.of_node = pdev->dev.of_node;
1501 master->bus_num = pdev->id;
1502 master->num_chipselect = master->dev.of_node ? 0 : 4;
1503 master->setup = atmel_spi_setup;
1504 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
1505 master->transfer_one_message = atmel_spi_transfer_one_message;
1506 master->cleanup = atmel_spi_cleanup;
1507 master->auto_runtime_pm = true;
1508 master->max_dma_len = SPI_MAX_DMA_XFER;
1509 master->can_dma = atmel_spi_can_dma;
1510 platform_set_drvdata(pdev, master);
1511
1512 as = spi_master_get_devdata(master);
1513
1514 spin_lock_init(&as->lock);
1515
1516 as->pdev = pdev;
1517 as->regs = devm_ioremap_resource(&pdev->dev, regs);
1518 if (IS_ERR(as->regs)) {
1519 ret = PTR_ERR(as->regs);
1520 goto out_unmap_regs;
1521 }
1522 as->phybase = regs->start;
1523 as->irq = irq;
1524 as->clk = clk;
1525
1526 init_completion(&as->xfer_completion);
1527
1528 atmel_get_caps(as);
1529
1530 as->use_cs_gpios = true;
1531 if (atmel_spi_is_v2(as) &&
1532 pdev->dev.of_node &&
1533 !of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
1534 as->use_cs_gpios = false;
1535 master->num_chipselect = 4;
1536 }
1537
1538 ret = atmel_spi_gpio_cs(pdev);
1539 if (ret)
1540 goto out_unmap_regs;
1541
1542 as->use_dma = false;
1543 as->use_pdc = false;
1544 if (as->caps.has_dma_support) {
1545 ret = atmel_spi_configure_dma(master, as);
1546 if (ret == 0) {
1547 as->use_dma = true;
1548 } else if (ret == -EPROBE_DEFER) {
1549 return ret;
1550 }
1551 } else {
1552 as->use_pdc = true;
1553 }
1554
1555 if (as->caps.has_dma_support && !as->use_dma)
1556 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1557
1558 if (as->use_pdc) {
1559 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1560 0, dev_name(&pdev->dev), master);
1561 } else {
1562 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1563 0, dev_name(&pdev->dev), master);
1564 }
1565 if (ret)
1566 goto out_unmap_regs;
1567
1568 /* Initialize the hardware */
1569 ret = clk_prepare_enable(clk);
1570 if (ret)
1571 goto out_free_irq;
1572
1573 as->spi_clk = clk_get_rate(clk);
1574
1575 spi_writel(as, CR, SPI_BIT(SWRST));
1576 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1577 if (as->caps.has_wdrbt) {
1578 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1579 | SPI_BIT(MSTR));
1580 } else {
1581 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1582 }
1583
1584 if (as->use_pdc)
1585 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1586 spi_writel(as, CR, SPI_BIT(SPIEN));
1587
1588 as->fifo_size = 0;
1589 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1590 &as->fifo_size)) {
1591 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
1592 spi_writel(as, CR, SPI_BIT(FIFOEN));
1593 }
1594
1595 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1596 pm_runtime_use_autosuspend(&pdev->dev);
1597 pm_runtime_set_active(&pdev->dev);
1598 pm_runtime_enable(&pdev->dev);
1599
1600 ret = devm_spi_register_master(&pdev->dev, master);
1601 if (ret)
1602 goto out_free_dma;
1603
1604 /* go! */
1605 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1606 (unsigned long)regs->start, irq);
1607
1608 return 0;
1609
1610out_free_dma:
1611 pm_runtime_disable(&pdev->dev);
1612 pm_runtime_set_suspended(&pdev->dev);
1613
1614 if (as->use_dma)
1615 atmel_spi_release_dma(master);
1616
1617 spi_writel(as, CR, SPI_BIT(SWRST));
1618 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1619 clk_disable_unprepare(clk);
1620out_free_irq:
1621out_unmap_regs:
1622out_free:
1623 spi_master_put(master);
1624 return ret;
1625}
1626
1627static int atmel_spi_remove(struct platform_device *pdev)
1628{
1629 struct spi_master *master = platform_get_drvdata(pdev);
1630 struct atmel_spi *as = spi_master_get_devdata(master);
1631
1632 pm_runtime_get_sync(&pdev->dev);
1633
1634 /* reset the hardware and block queue progress */
1635 spin_lock_irq(&as->lock);
1636 if (as->use_dma) {
1637 atmel_spi_stop_dma(master);
1638 atmel_spi_release_dma(master);
1639 }
1640
1641 spi_writel(as, CR, SPI_BIT(SWRST));
1642 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1643 spi_readl(as, SR);
1644 spin_unlock_irq(&as->lock);
1645
1646 clk_disable_unprepare(as->clk);
1647
1648 pm_runtime_put_noidle(&pdev->dev);
1649 pm_runtime_disable(&pdev->dev);
1650
1651 return 0;
1652}
1653
1654#ifdef CONFIG_PM
1655static int atmel_spi_runtime_suspend(struct device *dev)
1656{
1657 struct spi_master *master = dev_get_drvdata(dev);
1658 struct atmel_spi *as = spi_master_get_devdata(master);
1659
1660 clk_disable_unprepare(as->clk);
1661 pinctrl_pm_select_sleep_state(dev);
1662
1663 return 0;
1664}
1665
1666static int atmel_spi_runtime_resume(struct device *dev)
1667{
1668 struct spi_master *master = dev_get_drvdata(dev);
1669 struct atmel_spi *as = spi_master_get_devdata(master);
1670
1671 pinctrl_pm_select_default_state(dev);
1672
1673 return clk_prepare_enable(as->clk);
1674}
1675
1676#ifdef CONFIG_PM_SLEEP
1677static int atmel_spi_suspend(struct device *dev)
1678{
1679 struct spi_master *master = dev_get_drvdata(dev);
1680 int ret;
1681
1682 /* Stop the queue running */
1683 ret = spi_master_suspend(master);
1684 if (ret) {
1685 dev_warn(dev, "cannot suspend master\n");
1686 return ret;
1687 }
1688
1689 if (!pm_runtime_suspended(dev))
1690 atmel_spi_runtime_suspend(dev);
1691
1692 return 0;
1693}
1694
1695static int atmel_spi_resume(struct device *dev)
1696{
1697 struct spi_master *master = dev_get_drvdata(dev);
1698 int ret;
1699
1700 if (!pm_runtime_suspended(dev)) {
1701 ret = atmel_spi_runtime_resume(dev);
1702 if (ret)
1703 return ret;
1704 }
1705
1706 /* Start the queue running */
1707 ret = spi_master_resume(master);
1708 if (ret)
1709 dev_err(dev, "problem starting queue (%d)\n", ret);
1710
1711 return ret;
1712}
1713#endif
1714
1715static const struct dev_pm_ops atmel_spi_pm_ops = {
1716 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1717 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1718 atmel_spi_runtime_resume, NULL)
1719};
1720#define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1721#else
1722#define ATMEL_SPI_PM_OPS NULL
1723#endif
1724
1725#if defined(CONFIG_OF)
1726static const struct of_device_id atmel_spi_dt_ids[] = {
1727 { .compatible = "atmel,at91rm9200-spi" },
1728 { /* sentinel */ }
1729};
1730
1731MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1732#endif
1733
1734static struct platform_driver atmel_spi_driver = {
1735 .driver = {
1736 .name = "atmel_spi",
1737 .pm = ATMEL_SPI_PM_OPS,
1738 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1739 },
1740 .probe = atmel_spi_probe,
1741 .remove = atmel_spi_remove,
1742};
1743module_platform_driver(atmel_spi_driver);
1744
1745MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1746MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1747MODULE_LICENSE("GPL");
1748MODULE_ALIAS("platform:atmel_spi");