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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32#include "i915_trace.h"
33#include "intel_drv.h"
34#include <linux/shmem_fs.h>
35#include <linux/slab.h>
36#include <linux/swap.h>
37#include <linux/pci.h>
38
39static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
40static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
42static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
43 bool write);
44static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
45 uint64_t offset,
46 uint64_t size);
47static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
48static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
49 unsigned alignment,
50 bool map_and_fenceable);
51static void i915_gem_clear_fence_reg(struct drm_device *dev,
52 struct drm_i915_fence_reg *reg);
53static int i915_gem_phys_pwrite(struct drm_device *dev,
54 struct drm_i915_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file);
57static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
58
59static int i915_gem_inactive_shrink(struct shrinker *shrinker,
60 struct shrink_control *sc);
61
62/* some bookkeeping */
63static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
64 size_t size)
65{
66 dev_priv->mm.object_count++;
67 dev_priv->mm.object_memory += size;
68}
69
70static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
71 size_t size)
72{
73 dev_priv->mm.object_count--;
74 dev_priv->mm.object_memory -= size;
75}
76
77static int
78i915_gem_wait_for_error(struct drm_device *dev)
79{
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct completion *x = &dev_priv->error_completion;
82 unsigned long flags;
83 int ret;
84
85 if (!atomic_read(&dev_priv->mm.wedged))
86 return 0;
87
88 ret = wait_for_completion_interruptible(x);
89 if (ret)
90 return ret;
91
92 if (atomic_read(&dev_priv->mm.wedged)) {
93 /* GPU is hung, bump the completion count to account for
94 * the token we just consumed so that we never hit zero and
95 * end up waiting upon a subsequent completion event that
96 * will never happen.
97 */
98 spin_lock_irqsave(&x->wait.lock, flags);
99 x->done++;
100 spin_unlock_irqrestore(&x->wait.lock, flags);
101 }
102 return 0;
103}
104
105int i915_mutex_lock_interruptible(struct drm_device *dev)
106{
107 int ret;
108
109 ret = i915_gem_wait_for_error(dev);
110 if (ret)
111 return ret;
112
113 ret = mutex_lock_interruptible(&dev->struct_mutex);
114 if (ret)
115 return ret;
116
117 WARN_ON(i915_verify_lists(dev));
118 return 0;
119}
120
121static inline bool
122i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
123{
124 return obj->gtt_space && !obj->active && obj->pin_count == 0;
125}
126
127void i915_gem_do_init(struct drm_device *dev,
128 unsigned long start,
129 unsigned long mappable_end,
130 unsigned long end)
131{
132 drm_i915_private_t *dev_priv = dev->dev_private;
133
134 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
135
136 dev_priv->mm.gtt_start = start;
137 dev_priv->mm.gtt_mappable_end = mappable_end;
138 dev_priv->mm.gtt_end = end;
139 dev_priv->mm.gtt_total = end - start;
140 dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
141
142 /* Take over this portion of the GTT */
143 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
144}
145
146int
147i915_gem_init_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
149{
150 struct drm_i915_gem_init *args = data;
151
152 if (args->gtt_start >= args->gtt_end ||
153 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
154 return -EINVAL;
155
156 mutex_lock(&dev->struct_mutex);
157 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
158 mutex_unlock(&dev->struct_mutex);
159
160 return 0;
161}
162
163int
164i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
166{
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_get_aperture *args = data;
169 struct drm_i915_gem_object *obj;
170 size_t pinned;
171
172 if (!(dev->driver->driver_features & DRIVER_GEM))
173 return -ENODEV;
174
175 pinned = 0;
176 mutex_lock(&dev->struct_mutex);
177 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
178 pinned += obj->gtt_space->size;
179 mutex_unlock(&dev->struct_mutex);
180
181 args->aper_size = dev_priv->mm.gtt_total;
182 args->aper_available_size = args->aper_size -pinned;
183
184 return 0;
185}
186
187static int
188i915_gem_create(struct drm_file *file,
189 struct drm_device *dev,
190 uint64_t size,
191 uint32_t *handle_p)
192{
193 struct drm_i915_gem_object *obj;
194 int ret;
195 u32 handle;
196
197 size = roundup(size, PAGE_SIZE);
198
199 /* Allocate the new object */
200 obj = i915_gem_alloc_object(dev, size);
201 if (obj == NULL)
202 return -ENOMEM;
203
204 ret = drm_gem_handle_create(file, &obj->base, &handle);
205 if (ret) {
206 drm_gem_object_release(&obj->base);
207 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
208 kfree(obj);
209 return ret;
210 }
211
212 /* drop reference from allocate - handle holds it now */
213 drm_gem_object_unreference(&obj->base);
214 trace_i915_gem_object_create(obj);
215
216 *handle_p = handle;
217 return 0;
218}
219
220int
221i915_gem_dumb_create(struct drm_file *file,
222 struct drm_device *dev,
223 struct drm_mode_create_dumb *args)
224{
225 /* have to work out size/pitch and return them */
226 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
227 args->size = args->pitch * args->height;
228 return i915_gem_create(file, dev,
229 args->size, &args->handle);
230}
231
232int i915_gem_dumb_destroy(struct drm_file *file,
233 struct drm_device *dev,
234 uint32_t handle)
235{
236 return drm_gem_handle_delete(file, handle);
237}
238
239/**
240 * Creates a new mm object and returns a handle to it.
241 */
242int
243i915_gem_create_ioctl(struct drm_device *dev, void *data,
244 struct drm_file *file)
245{
246 struct drm_i915_gem_create *args = data;
247 return i915_gem_create(file, dev,
248 args->size, &args->handle);
249}
250
251static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
252{
253 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
254
255 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
256 obj->tiling_mode != I915_TILING_NONE;
257}
258
259static inline void
260slow_shmem_copy(struct page *dst_page,
261 int dst_offset,
262 struct page *src_page,
263 int src_offset,
264 int length)
265{
266 char *dst_vaddr, *src_vaddr;
267
268 dst_vaddr = kmap(dst_page);
269 src_vaddr = kmap(src_page);
270
271 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
272
273 kunmap(src_page);
274 kunmap(dst_page);
275}
276
277static inline void
278slow_shmem_bit17_copy(struct page *gpu_page,
279 int gpu_offset,
280 struct page *cpu_page,
281 int cpu_offset,
282 int length,
283 int is_read)
284{
285 char *gpu_vaddr, *cpu_vaddr;
286
287 /* Use the unswizzled path if this page isn't affected. */
288 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
289 if (is_read)
290 return slow_shmem_copy(cpu_page, cpu_offset,
291 gpu_page, gpu_offset, length);
292 else
293 return slow_shmem_copy(gpu_page, gpu_offset,
294 cpu_page, cpu_offset, length);
295 }
296
297 gpu_vaddr = kmap(gpu_page);
298 cpu_vaddr = kmap(cpu_page);
299
300 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
301 * XORing with the other bits (A9 for Y, A9 and A10 for X)
302 */
303 while (length > 0) {
304 int cacheline_end = ALIGN(gpu_offset + 1, 64);
305 int this_length = min(cacheline_end - gpu_offset, length);
306 int swizzled_gpu_offset = gpu_offset ^ 64;
307
308 if (is_read) {
309 memcpy(cpu_vaddr + cpu_offset,
310 gpu_vaddr + swizzled_gpu_offset,
311 this_length);
312 } else {
313 memcpy(gpu_vaddr + swizzled_gpu_offset,
314 cpu_vaddr + cpu_offset,
315 this_length);
316 }
317 cpu_offset += this_length;
318 gpu_offset += this_length;
319 length -= this_length;
320 }
321
322 kunmap(cpu_page);
323 kunmap(gpu_page);
324}
325
326/**
327 * This is the fast shmem pread path, which attempts to copy_from_user directly
328 * from the backing pages of the object to the user's address space. On a
329 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
330 */
331static int
332i915_gem_shmem_pread_fast(struct drm_device *dev,
333 struct drm_i915_gem_object *obj,
334 struct drm_i915_gem_pread *args,
335 struct drm_file *file)
336{
337 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
338 ssize_t remain;
339 loff_t offset;
340 char __user *user_data;
341 int page_offset, page_length;
342
343 user_data = (char __user *) (uintptr_t) args->data_ptr;
344 remain = args->size;
345
346 offset = args->offset;
347
348 while (remain > 0) {
349 struct page *page;
350 char *vaddr;
351 int ret;
352
353 /* Operation in this page
354 *
355 * page_offset = offset within page
356 * page_length = bytes to copy for this page
357 */
358 page_offset = offset_in_page(offset);
359 page_length = remain;
360 if ((page_offset + remain) > PAGE_SIZE)
361 page_length = PAGE_SIZE - page_offset;
362
363 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
364 if (IS_ERR(page))
365 return PTR_ERR(page);
366
367 vaddr = kmap_atomic(page);
368 ret = __copy_to_user_inatomic(user_data,
369 vaddr + page_offset,
370 page_length);
371 kunmap_atomic(vaddr);
372
373 mark_page_accessed(page);
374 page_cache_release(page);
375 if (ret)
376 return -EFAULT;
377
378 remain -= page_length;
379 user_data += page_length;
380 offset += page_length;
381 }
382
383 return 0;
384}
385
386/**
387 * This is the fallback shmem pread path, which allocates temporary storage
388 * in kernel space to copy_to_user into outside of the struct_mutex, so we
389 * can copy out of the object's backing pages while holding the struct mutex
390 * and not take page faults.
391 */
392static int
393i915_gem_shmem_pread_slow(struct drm_device *dev,
394 struct drm_i915_gem_object *obj,
395 struct drm_i915_gem_pread *args,
396 struct drm_file *file)
397{
398 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
399 struct mm_struct *mm = current->mm;
400 struct page **user_pages;
401 ssize_t remain;
402 loff_t offset, pinned_pages, i;
403 loff_t first_data_page, last_data_page, num_pages;
404 int shmem_page_offset;
405 int data_page_index, data_page_offset;
406 int page_length;
407 int ret;
408 uint64_t data_ptr = args->data_ptr;
409 int do_bit17_swizzling;
410
411 remain = args->size;
412
413 /* Pin the user pages containing the data. We can't fault while
414 * holding the struct mutex, yet we want to hold it while
415 * dereferencing the user data.
416 */
417 first_data_page = data_ptr / PAGE_SIZE;
418 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
419 num_pages = last_data_page - first_data_page + 1;
420
421 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
422 if (user_pages == NULL)
423 return -ENOMEM;
424
425 mutex_unlock(&dev->struct_mutex);
426 down_read(&mm->mmap_sem);
427 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
428 num_pages, 1, 0, user_pages, NULL);
429 up_read(&mm->mmap_sem);
430 mutex_lock(&dev->struct_mutex);
431 if (pinned_pages < num_pages) {
432 ret = -EFAULT;
433 goto out;
434 }
435
436 ret = i915_gem_object_set_cpu_read_domain_range(obj,
437 args->offset,
438 args->size);
439 if (ret)
440 goto out;
441
442 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
443
444 offset = args->offset;
445
446 while (remain > 0) {
447 struct page *page;
448
449 /* Operation in this page
450 *
451 * shmem_page_offset = offset within page in shmem file
452 * data_page_index = page number in get_user_pages return
453 * data_page_offset = offset with data_page_index page.
454 * page_length = bytes to copy for this page
455 */
456 shmem_page_offset = offset_in_page(offset);
457 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
458 data_page_offset = offset_in_page(data_ptr);
459
460 page_length = remain;
461 if ((shmem_page_offset + page_length) > PAGE_SIZE)
462 page_length = PAGE_SIZE - shmem_page_offset;
463 if ((data_page_offset + page_length) > PAGE_SIZE)
464 page_length = PAGE_SIZE - data_page_offset;
465
466 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
467 if (IS_ERR(page)) {
468 ret = PTR_ERR(page);
469 goto out;
470 }
471
472 if (do_bit17_swizzling) {
473 slow_shmem_bit17_copy(page,
474 shmem_page_offset,
475 user_pages[data_page_index],
476 data_page_offset,
477 page_length,
478 1);
479 } else {
480 slow_shmem_copy(user_pages[data_page_index],
481 data_page_offset,
482 page,
483 shmem_page_offset,
484 page_length);
485 }
486
487 mark_page_accessed(page);
488 page_cache_release(page);
489
490 remain -= page_length;
491 data_ptr += page_length;
492 offset += page_length;
493 }
494
495out:
496 for (i = 0; i < pinned_pages; i++) {
497 SetPageDirty(user_pages[i]);
498 mark_page_accessed(user_pages[i]);
499 page_cache_release(user_pages[i]);
500 }
501 drm_free_large(user_pages);
502
503 return ret;
504}
505
506/**
507 * Reads data from the object referenced by handle.
508 *
509 * On error, the contents of *data are undefined.
510 */
511int
512i915_gem_pread_ioctl(struct drm_device *dev, void *data,
513 struct drm_file *file)
514{
515 struct drm_i915_gem_pread *args = data;
516 struct drm_i915_gem_object *obj;
517 int ret = 0;
518
519 if (args->size == 0)
520 return 0;
521
522 if (!access_ok(VERIFY_WRITE,
523 (char __user *)(uintptr_t)args->data_ptr,
524 args->size))
525 return -EFAULT;
526
527 ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
528 args->size);
529 if (ret)
530 return -EFAULT;
531
532 ret = i915_mutex_lock_interruptible(dev);
533 if (ret)
534 return ret;
535
536 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
537 if (&obj->base == NULL) {
538 ret = -ENOENT;
539 goto unlock;
540 }
541
542 /* Bounds check source. */
543 if (args->offset > obj->base.size ||
544 args->size > obj->base.size - args->offset) {
545 ret = -EINVAL;
546 goto out;
547 }
548
549 trace_i915_gem_object_pread(obj, args->offset, args->size);
550
551 ret = i915_gem_object_set_cpu_read_domain_range(obj,
552 args->offset,
553 args->size);
554 if (ret)
555 goto out;
556
557 ret = -EFAULT;
558 if (!i915_gem_object_needs_bit17_swizzle(obj))
559 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
560 if (ret == -EFAULT)
561 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
562
563out:
564 drm_gem_object_unreference(&obj->base);
565unlock:
566 mutex_unlock(&dev->struct_mutex);
567 return ret;
568}
569
570/* This is the fast write path which cannot handle
571 * page faults in the source data
572 */
573
574static inline int
575fast_user_write(struct io_mapping *mapping,
576 loff_t page_base, int page_offset,
577 char __user *user_data,
578 int length)
579{
580 char *vaddr_atomic;
581 unsigned long unwritten;
582
583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
585 user_data, length);
586 io_mapping_unmap_atomic(vaddr_atomic);
587 return unwritten;
588}
589
590/* Here's the write path which can sleep for
591 * page faults
592 */
593
594static inline void
595slow_kernel_write(struct io_mapping *mapping,
596 loff_t gtt_base, int gtt_offset,
597 struct page *user_page, int user_offset,
598 int length)
599{
600 char __iomem *dst_vaddr;
601 char *src_vaddr;
602
603 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
604 src_vaddr = kmap(user_page);
605
606 memcpy_toio(dst_vaddr + gtt_offset,
607 src_vaddr + user_offset,
608 length);
609
610 kunmap(user_page);
611 io_mapping_unmap(dst_vaddr);
612}
613
614/**
615 * This is the fast pwrite path, where we copy the data directly from the
616 * user into the GTT, uncached.
617 */
618static int
619i915_gem_gtt_pwrite_fast(struct drm_device *dev,
620 struct drm_i915_gem_object *obj,
621 struct drm_i915_gem_pwrite *args,
622 struct drm_file *file)
623{
624 drm_i915_private_t *dev_priv = dev->dev_private;
625 ssize_t remain;
626 loff_t offset, page_base;
627 char __user *user_data;
628 int page_offset, page_length;
629
630 user_data = (char __user *) (uintptr_t) args->data_ptr;
631 remain = args->size;
632
633 offset = obj->gtt_offset + args->offset;
634
635 while (remain > 0) {
636 /* Operation in this page
637 *
638 * page_base = page offset within aperture
639 * page_offset = offset within page
640 * page_length = bytes to copy for this page
641 */
642 page_base = offset & PAGE_MASK;
643 page_offset = offset_in_page(offset);
644 page_length = remain;
645 if ((page_offset + remain) > PAGE_SIZE)
646 page_length = PAGE_SIZE - page_offset;
647
648 /* If we get a fault while copying data, then (presumably) our
649 * source page isn't available. Return the error and we'll
650 * retry in the slow path.
651 */
652 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
653 page_offset, user_data, page_length))
654 return -EFAULT;
655
656 remain -= page_length;
657 user_data += page_length;
658 offset += page_length;
659 }
660
661 return 0;
662}
663
664/**
665 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
666 * the memory and maps it using kmap_atomic for copying.
667 *
668 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
669 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
670 */
671static int
672i915_gem_gtt_pwrite_slow(struct drm_device *dev,
673 struct drm_i915_gem_object *obj,
674 struct drm_i915_gem_pwrite *args,
675 struct drm_file *file)
676{
677 drm_i915_private_t *dev_priv = dev->dev_private;
678 ssize_t remain;
679 loff_t gtt_page_base, offset;
680 loff_t first_data_page, last_data_page, num_pages;
681 loff_t pinned_pages, i;
682 struct page **user_pages;
683 struct mm_struct *mm = current->mm;
684 int gtt_page_offset, data_page_offset, data_page_index, page_length;
685 int ret;
686 uint64_t data_ptr = args->data_ptr;
687
688 remain = args->size;
689
690 /* Pin the user pages containing the data. We can't fault while
691 * holding the struct mutex, and all of the pwrite implementations
692 * want to hold it while dereferencing the user data.
693 */
694 first_data_page = data_ptr / PAGE_SIZE;
695 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
696 num_pages = last_data_page - first_data_page + 1;
697
698 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
699 if (user_pages == NULL)
700 return -ENOMEM;
701
702 mutex_unlock(&dev->struct_mutex);
703 down_read(&mm->mmap_sem);
704 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
705 num_pages, 0, 0, user_pages, NULL);
706 up_read(&mm->mmap_sem);
707 mutex_lock(&dev->struct_mutex);
708 if (pinned_pages < num_pages) {
709 ret = -EFAULT;
710 goto out_unpin_pages;
711 }
712
713 ret = i915_gem_object_set_to_gtt_domain(obj, true);
714 if (ret)
715 goto out_unpin_pages;
716
717 ret = i915_gem_object_put_fence(obj);
718 if (ret)
719 goto out_unpin_pages;
720
721 offset = obj->gtt_offset + args->offset;
722
723 while (remain > 0) {
724 /* Operation in this page
725 *
726 * gtt_page_base = page offset within aperture
727 * gtt_page_offset = offset within page in aperture
728 * data_page_index = page number in get_user_pages return
729 * data_page_offset = offset with data_page_index page.
730 * page_length = bytes to copy for this page
731 */
732 gtt_page_base = offset & PAGE_MASK;
733 gtt_page_offset = offset_in_page(offset);
734 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
735 data_page_offset = offset_in_page(data_ptr);
736
737 page_length = remain;
738 if ((gtt_page_offset + page_length) > PAGE_SIZE)
739 page_length = PAGE_SIZE - gtt_page_offset;
740 if ((data_page_offset + page_length) > PAGE_SIZE)
741 page_length = PAGE_SIZE - data_page_offset;
742
743 slow_kernel_write(dev_priv->mm.gtt_mapping,
744 gtt_page_base, gtt_page_offset,
745 user_pages[data_page_index],
746 data_page_offset,
747 page_length);
748
749 remain -= page_length;
750 offset += page_length;
751 data_ptr += page_length;
752 }
753
754out_unpin_pages:
755 for (i = 0; i < pinned_pages; i++)
756 page_cache_release(user_pages[i]);
757 drm_free_large(user_pages);
758
759 return ret;
760}
761
762/**
763 * This is the fast shmem pwrite path, which attempts to directly
764 * copy_from_user into the kmapped pages backing the object.
765 */
766static int
767i915_gem_shmem_pwrite_fast(struct drm_device *dev,
768 struct drm_i915_gem_object *obj,
769 struct drm_i915_gem_pwrite *args,
770 struct drm_file *file)
771{
772 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
773 ssize_t remain;
774 loff_t offset;
775 char __user *user_data;
776 int page_offset, page_length;
777
778 user_data = (char __user *) (uintptr_t) args->data_ptr;
779 remain = args->size;
780
781 offset = args->offset;
782 obj->dirty = 1;
783
784 while (remain > 0) {
785 struct page *page;
786 char *vaddr;
787 int ret;
788
789 /* Operation in this page
790 *
791 * page_offset = offset within page
792 * page_length = bytes to copy for this page
793 */
794 page_offset = offset_in_page(offset);
795 page_length = remain;
796 if ((page_offset + remain) > PAGE_SIZE)
797 page_length = PAGE_SIZE - page_offset;
798
799 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
800 if (IS_ERR(page))
801 return PTR_ERR(page);
802
803 vaddr = kmap_atomic(page, KM_USER0);
804 ret = __copy_from_user_inatomic(vaddr + page_offset,
805 user_data,
806 page_length);
807 kunmap_atomic(vaddr, KM_USER0);
808
809 set_page_dirty(page);
810 mark_page_accessed(page);
811 page_cache_release(page);
812
813 /* If we get a fault while copying data, then (presumably) our
814 * source page isn't available. Return the error and we'll
815 * retry in the slow path.
816 */
817 if (ret)
818 return -EFAULT;
819
820 remain -= page_length;
821 user_data += page_length;
822 offset += page_length;
823 }
824
825 return 0;
826}
827
828/**
829 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
830 * the memory and maps it using kmap_atomic for copying.
831 *
832 * This avoids taking mmap_sem for faulting on the user's address while the
833 * struct_mutex is held.
834 */
835static int
836i915_gem_shmem_pwrite_slow(struct drm_device *dev,
837 struct drm_i915_gem_object *obj,
838 struct drm_i915_gem_pwrite *args,
839 struct drm_file *file)
840{
841 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
842 struct mm_struct *mm = current->mm;
843 struct page **user_pages;
844 ssize_t remain;
845 loff_t offset, pinned_pages, i;
846 loff_t first_data_page, last_data_page, num_pages;
847 int shmem_page_offset;
848 int data_page_index, data_page_offset;
849 int page_length;
850 int ret;
851 uint64_t data_ptr = args->data_ptr;
852 int do_bit17_swizzling;
853
854 remain = args->size;
855
856 /* Pin the user pages containing the data. We can't fault while
857 * holding the struct mutex, and all of the pwrite implementations
858 * want to hold it while dereferencing the user data.
859 */
860 first_data_page = data_ptr / PAGE_SIZE;
861 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
862 num_pages = last_data_page - first_data_page + 1;
863
864 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
865 if (user_pages == NULL)
866 return -ENOMEM;
867
868 mutex_unlock(&dev->struct_mutex);
869 down_read(&mm->mmap_sem);
870 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
871 num_pages, 0, 0, user_pages, NULL);
872 up_read(&mm->mmap_sem);
873 mutex_lock(&dev->struct_mutex);
874 if (pinned_pages < num_pages) {
875 ret = -EFAULT;
876 goto out;
877 }
878
879 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
880 if (ret)
881 goto out;
882
883 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
884
885 offset = args->offset;
886 obj->dirty = 1;
887
888 while (remain > 0) {
889 struct page *page;
890
891 /* Operation in this page
892 *
893 * shmem_page_offset = offset within page in shmem file
894 * data_page_index = page number in get_user_pages return
895 * data_page_offset = offset with data_page_index page.
896 * page_length = bytes to copy for this page
897 */
898 shmem_page_offset = offset_in_page(offset);
899 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
900 data_page_offset = offset_in_page(data_ptr);
901
902 page_length = remain;
903 if ((shmem_page_offset + page_length) > PAGE_SIZE)
904 page_length = PAGE_SIZE - shmem_page_offset;
905 if ((data_page_offset + page_length) > PAGE_SIZE)
906 page_length = PAGE_SIZE - data_page_offset;
907
908 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
909 if (IS_ERR(page)) {
910 ret = PTR_ERR(page);
911 goto out;
912 }
913
914 if (do_bit17_swizzling) {
915 slow_shmem_bit17_copy(page,
916 shmem_page_offset,
917 user_pages[data_page_index],
918 data_page_offset,
919 page_length,
920 0);
921 } else {
922 slow_shmem_copy(page,
923 shmem_page_offset,
924 user_pages[data_page_index],
925 data_page_offset,
926 page_length);
927 }
928
929 set_page_dirty(page);
930 mark_page_accessed(page);
931 page_cache_release(page);
932
933 remain -= page_length;
934 data_ptr += page_length;
935 offset += page_length;
936 }
937
938out:
939 for (i = 0; i < pinned_pages; i++)
940 page_cache_release(user_pages[i]);
941 drm_free_large(user_pages);
942
943 return ret;
944}
945
946/**
947 * Writes data to the object referenced by handle.
948 *
949 * On error, the contents of the buffer that were to be modified are undefined.
950 */
951int
952i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
953 struct drm_file *file)
954{
955 struct drm_i915_gem_pwrite *args = data;
956 struct drm_i915_gem_object *obj;
957 int ret;
958
959 if (args->size == 0)
960 return 0;
961
962 if (!access_ok(VERIFY_READ,
963 (char __user *)(uintptr_t)args->data_ptr,
964 args->size))
965 return -EFAULT;
966
967 ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
968 args->size);
969 if (ret)
970 return -EFAULT;
971
972 ret = i915_mutex_lock_interruptible(dev);
973 if (ret)
974 return ret;
975
976 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
977 if (&obj->base == NULL) {
978 ret = -ENOENT;
979 goto unlock;
980 }
981
982 /* Bounds check destination. */
983 if (args->offset > obj->base.size ||
984 args->size > obj->base.size - args->offset) {
985 ret = -EINVAL;
986 goto out;
987 }
988
989 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
990
991 /* We can only do the GTT pwrite on untiled buffers, as otherwise
992 * it would end up going through the fenced access, and we'll get
993 * different detiling behavior between reading and writing.
994 * pread/pwrite currently are reading and writing from the CPU
995 * perspective, requiring manual detiling by the client.
996 */
997 if (obj->phys_obj)
998 ret = i915_gem_phys_pwrite(dev, obj, args, file);
999 else if (obj->gtt_space &&
1000 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1001 ret = i915_gem_object_pin(obj, 0, true);
1002 if (ret)
1003 goto out;
1004
1005 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1006 if (ret)
1007 goto out_unpin;
1008
1009 ret = i915_gem_object_put_fence(obj);
1010 if (ret)
1011 goto out_unpin;
1012
1013 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1014 if (ret == -EFAULT)
1015 ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1016
1017out_unpin:
1018 i915_gem_object_unpin(obj);
1019 } else {
1020 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1021 if (ret)
1022 goto out;
1023
1024 ret = -EFAULT;
1025 if (!i915_gem_object_needs_bit17_swizzle(obj))
1026 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1027 if (ret == -EFAULT)
1028 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1029 }
1030
1031out:
1032 drm_gem_object_unreference(&obj->base);
1033unlock:
1034 mutex_unlock(&dev->struct_mutex);
1035 return ret;
1036}
1037
1038/**
1039 * Called when user space prepares to use an object with the CPU, either
1040 * through the mmap ioctl's mapping or a GTT mapping.
1041 */
1042int
1043i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1044 struct drm_file *file)
1045{
1046 struct drm_i915_gem_set_domain *args = data;
1047 struct drm_i915_gem_object *obj;
1048 uint32_t read_domains = args->read_domains;
1049 uint32_t write_domain = args->write_domain;
1050 int ret;
1051
1052 if (!(dev->driver->driver_features & DRIVER_GEM))
1053 return -ENODEV;
1054
1055 /* Only handle setting domains to types used by the CPU. */
1056 if (write_domain & I915_GEM_GPU_DOMAINS)
1057 return -EINVAL;
1058
1059 if (read_domains & I915_GEM_GPU_DOMAINS)
1060 return -EINVAL;
1061
1062 /* Having something in the write domain implies it's in the read
1063 * domain, and only that read domain. Enforce that in the request.
1064 */
1065 if (write_domain != 0 && read_domains != write_domain)
1066 return -EINVAL;
1067
1068 ret = i915_mutex_lock_interruptible(dev);
1069 if (ret)
1070 return ret;
1071
1072 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1073 if (&obj->base == NULL) {
1074 ret = -ENOENT;
1075 goto unlock;
1076 }
1077
1078 if (read_domains & I915_GEM_DOMAIN_GTT) {
1079 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1080
1081 /* Silently promote "you're not bound, there was nothing to do"
1082 * to success, since the client was just asking us to
1083 * make sure everything was done.
1084 */
1085 if (ret == -EINVAL)
1086 ret = 0;
1087 } else {
1088 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1089 }
1090
1091 drm_gem_object_unreference(&obj->base);
1092unlock:
1093 mutex_unlock(&dev->struct_mutex);
1094 return ret;
1095}
1096
1097/**
1098 * Called when user space has done writes to this buffer
1099 */
1100int
1101i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1102 struct drm_file *file)
1103{
1104 struct drm_i915_gem_sw_finish *args = data;
1105 struct drm_i915_gem_object *obj;
1106 int ret = 0;
1107
1108 if (!(dev->driver->driver_features & DRIVER_GEM))
1109 return -ENODEV;
1110
1111 ret = i915_mutex_lock_interruptible(dev);
1112 if (ret)
1113 return ret;
1114
1115 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1116 if (&obj->base == NULL) {
1117 ret = -ENOENT;
1118 goto unlock;
1119 }
1120
1121 /* Pinned buffers may be scanout, so flush the cache */
1122 if (obj->pin_count)
1123 i915_gem_object_flush_cpu_write_domain(obj);
1124
1125 drm_gem_object_unreference(&obj->base);
1126unlock:
1127 mutex_unlock(&dev->struct_mutex);
1128 return ret;
1129}
1130
1131/**
1132 * Maps the contents of an object, returning the address it is mapped
1133 * into.
1134 *
1135 * While the mapping holds a reference on the contents of the object, it doesn't
1136 * imply a ref on the object itself.
1137 */
1138int
1139i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1140 struct drm_file *file)
1141{
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 struct drm_i915_gem_mmap *args = data;
1144 struct drm_gem_object *obj;
1145 unsigned long addr;
1146
1147 if (!(dev->driver->driver_features & DRIVER_GEM))
1148 return -ENODEV;
1149
1150 obj = drm_gem_object_lookup(dev, file, args->handle);
1151 if (obj == NULL)
1152 return -ENOENT;
1153
1154 if (obj->size > dev_priv->mm.gtt_mappable_end) {
1155 drm_gem_object_unreference_unlocked(obj);
1156 return -E2BIG;
1157 }
1158
1159 down_write(¤t->mm->mmap_sem);
1160 addr = do_mmap(obj->filp, 0, args->size,
1161 PROT_READ | PROT_WRITE, MAP_SHARED,
1162 args->offset);
1163 up_write(¤t->mm->mmap_sem);
1164 drm_gem_object_unreference_unlocked(obj);
1165 if (IS_ERR((void *)addr))
1166 return addr;
1167
1168 args->addr_ptr = (uint64_t) addr;
1169
1170 return 0;
1171}
1172
1173/**
1174 * i915_gem_fault - fault a page into the GTT
1175 * vma: VMA in question
1176 * vmf: fault info
1177 *
1178 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1179 * from userspace. The fault handler takes care of binding the object to
1180 * the GTT (if needed), allocating and programming a fence register (again,
1181 * only if needed based on whether the old reg is still valid or the object
1182 * is tiled) and inserting a new PTE into the faulting process.
1183 *
1184 * Note that the faulting process may involve evicting existing objects
1185 * from the GTT and/or fence registers to make room. So performance may
1186 * suffer if the GTT working set is large or there are few fence registers
1187 * left.
1188 */
1189int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1190{
1191 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1192 struct drm_device *dev = obj->base.dev;
1193 drm_i915_private_t *dev_priv = dev->dev_private;
1194 pgoff_t page_offset;
1195 unsigned long pfn;
1196 int ret = 0;
1197 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1198
1199 /* We don't use vmf->pgoff since that has the fake offset */
1200 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1201 PAGE_SHIFT;
1202
1203 ret = i915_mutex_lock_interruptible(dev);
1204 if (ret)
1205 goto out;
1206
1207 trace_i915_gem_object_fault(obj, page_offset, true, write);
1208
1209 /* Now bind it into the GTT if needed */
1210 if (!obj->map_and_fenceable) {
1211 ret = i915_gem_object_unbind(obj);
1212 if (ret)
1213 goto unlock;
1214 }
1215 if (!obj->gtt_space) {
1216 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1217 if (ret)
1218 goto unlock;
1219
1220 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1221 if (ret)
1222 goto unlock;
1223 }
1224
1225 if (obj->tiling_mode == I915_TILING_NONE)
1226 ret = i915_gem_object_put_fence(obj);
1227 else
1228 ret = i915_gem_object_get_fence(obj, NULL);
1229 if (ret)
1230 goto unlock;
1231
1232 if (i915_gem_object_is_inactive(obj))
1233 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1234
1235 obj->fault_mappable = true;
1236
1237 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1238 page_offset;
1239
1240 /* Finally, remap it using the new GTT offset */
1241 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1242unlock:
1243 mutex_unlock(&dev->struct_mutex);
1244out:
1245 switch (ret) {
1246 case -EIO:
1247 case -EAGAIN:
1248 /* Give the error handler a chance to run and move the
1249 * objects off the GPU active list. Next time we service the
1250 * fault, we should be able to transition the page into the
1251 * GTT without touching the GPU (and so avoid further
1252 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1253 * with coherency, just lost writes.
1254 */
1255 set_need_resched();
1256 case 0:
1257 case -ERESTARTSYS:
1258 case -EINTR:
1259 return VM_FAULT_NOPAGE;
1260 case -ENOMEM:
1261 return VM_FAULT_OOM;
1262 default:
1263 return VM_FAULT_SIGBUS;
1264 }
1265}
1266
1267/**
1268 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1269 * @obj: obj in question
1270 *
1271 * GEM memory mapping works by handing back to userspace a fake mmap offset
1272 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1273 * up the object based on the offset and sets up the various memory mapping
1274 * structures.
1275 *
1276 * This routine allocates and attaches a fake offset for @obj.
1277 */
1278static int
1279i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1280{
1281 struct drm_device *dev = obj->base.dev;
1282 struct drm_gem_mm *mm = dev->mm_private;
1283 struct drm_map_list *list;
1284 struct drm_local_map *map;
1285 int ret = 0;
1286
1287 /* Set the object up for mmap'ing */
1288 list = &obj->base.map_list;
1289 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1290 if (!list->map)
1291 return -ENOMEM;
1292
1293 map = list->map;
1294 map->type = _DRM_GEM;
1295 map->size = obj->base.size;
1296 map->handle = obj;
1297
1298 /* Get a DRM GEM mmap offset allocated... */
1299 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1300 obj->base.size / PAGE_SIZE,
1301 0, 0);
1302 if (!list->file_offset_node) {
1303 DRM_ERROR("failed to allocate offset for bo %d\n",
1304 obj->base.name);
1305 ret = -ENOSPC;
1306 goto out_free_list;
1307 }
1308
1309 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1310 obj->base.size / PAGE_SIZE,
1311 0);
1312 if (!list->file_offset_node) {
1313 ret = -ENOMEM;
1314 goto out_free_list;
1315 }
1316
1317 list->hash.key = list->file_offset_node->start;
1318 ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1319 if (ret) {
1320 DRM_ERROR("failed to add to map hash\n");
1321 goto out_free_mm;
1322 }
1323
1324 return 0;
1325
1326out_free_mm:
1327 drm_mm_put_block(list->file_offset_node);
1328out_free_list:
1329 kfree(list->map);
1330 list->map = NULL;
1331
1332 return ret;
1333}
1334
1335/**
1336 * i915_gem_release_mmap - remove physical page mappings
1337 * @obj: obj in question
1338 *
1339 * Preserve the reservation of the mmapping with the DRM core code, but
1340 * relinquish ownership of the pages back to the system.
1341 *
1342 * It is vital that we remove the page mapping if we have mapped a tiled
1343 * object through the GTT and then lose the fence register due to
1344 * resource pressure. Similarly if the object has been moved out of the
1345 * aperture, than pages mapped into userspace must be revoked. Removing the
1346 * mapping will then trigger a page fault on the next user access, allowing
1347 * fixup by i915_gem_fault().
1348 */
1349void
1350i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1351{
1352 if (!obj->fault_mappable)
1353 return;
1354
1355 if (obj->base.dev->dev_mapping)
1356 unmap_mapping_range(obj->base.dev->dev_mapping,
1357 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1358 obj->base.size, 1);
1359
1360 obj->fault_mappable = false;
1361}
1362
1363static void
1364i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1365{
1366 struct drm_device *dev = obj->base.dev;
1367 struct drm_gem_mm *mm = dev->mm_private;
1368 struct drm_map_list *list = &obj->base.map_list;
1369
1370 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1371 drm_mm_put_block(list->file_offset_node);
1372 kfree(list->map);
1373 list->map = NULL;
1374}
1375
1376static uint32_t
1377i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1378{
1379 uint32_t gtt_size;
1380
1381 if (INTEL_INFO(dev)->gen >= 4 ||
1382 tiling_mode == I915_TILING_NONE)
1383 return size;
1384
1385 /* Previous chips need a power-of-two fence region when tiling */
1386 if (INTEL_INFO(dev)->gen == 3)
1387 gtt_size = 1024*1024;
1388 else
1389 gtt_size = 512*1024;
1390
1391 while (gtt_size < size)
1392 gtt_size <<= 1;
1393
1394 return gtt_size;
1395}
1396
1397/**
1398 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1399 * @obj: object to check
1400 *
1401 * Return the required GTT alignment for an object, taking into account
1402 * potential fence register mapping.
1403 */
1404static uint32_t
1405i915_gem_get_gtt_alignment(struct drm_device *dev,
1406 uint32_t size,
1407 int tiling_mode)
1408{
1409 /*
1410 * Minimum alignment is 4k (GTT page size), but might be greater
1411 * if a fence register is needed for the object.
1412 */
1413 if (INTEL_INFO(dev)->gen >= 4 ||
1414 tiling_mode == I915_TILING_NONE)
1415 return 4096;
1416
1417 /*
1418 * Previous chips need to be aligned to the size of the smallest
1419 * fence register that can contain the object.
1420 */
1421 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1422}
1423
1424/**
1425 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1426 * unfenced object
1427 * @dev: the device
1428 * @size: size of the object
1429 * @tiling_mode: tiling mode of the object
1430 *
1431 * Return the required GTT alignment for an object, only taking into account
1432 * unfenced tiled surface requirements.
1433 */
1434uint32_t
1435i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1436 uint32_t size,
1437 int tiling_mode)
1438{
1439 /*
1440 * Minimum alignment is 4k (GTT page size) for sane hw.
1441 */
1442 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1443 tiling_mode == I915_TILING_NONE)
1444 return 4096;
1445
1446 /* Previous hardware however needs to be aligned to a power-of-two
1447 * tile height. The simplest method for determining this is to reuse
1448 * the power-of-tile object size.
1449 */
1450 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1451}
1452
1453int
1454i915_gem_mmap_gtt(struct drm_file *file,
1455 struct drm_device *dev,
1456 uint32_t handle,
1457 uint64_t *offset)
1458{
1459 struct drm_i915_private *dev_priv = dev->dev_private;
1460 struct drm_i915_gem_object *obj;
1461 int ret;
1462
1463 if (!(dev->driver->driver_features & DRIVER_GEM))
1464 return -ENODEV;
1465
1466 ret = i915_mutex_lock_interruptible(dev);
1467 if (ret)
1468 return ret;
1469
1470 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1471 if (&obj->base == NULL) {
1472 ret = -ENOENT;
1473 goto unlock;
1474 }
1475
1476 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1477 ret = -E2BIG;
1478 goto unlock;
1479 }
1480
1481 if (obj->madv != I915_MADV_WILLNEED) {
1482 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1483 ret = -EINVAL;
1484 goto out;
1485 }
1486
1487 if (!obj->base.map_list.map) {
1488 ret = i915_gem_create_mmap_offset(obj);
1489 if (ret)
1490 goto out;
1491 }
1492
1493 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1494
1495out:
1496 drm_gem_object_unreference(&obj->base);
1497unlock:
1498 mutex_unlock(&dev->struct_mutex);
1499 return ret;
1500}
1501
1502/**
1503 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1504 * @dev: DRM device
1505 * @data: GTT mapping ioctl data
1506 * @file: GEM object info
1507 *
1508 * Simply returns the fake offset to userspace so it can mmap it.
1509 * The mmap call will end up in drm_gem_mmap(), which will set things
1510 * up so we can get faults in the handler above.
1511 *
1512 * The fault handler will take care of binding the object into the GTT
1513 * (since it may have been evicted to make room for something), allocating
1514 * a fence register, and mapping the appropriate aperture address into
1515 * userspace.
1516 */
1517int
1518i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1519 struct drm_file *file)
1520{
1521 struct drm_i915_gem_mmap_gtt *args = data;
1522
1523 if (!(dev->driver->driver_features & DRIVER_GEM))
1524 return -ENODEV;
1525
1526 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1527}
1528
1529
1530static int
1531i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1532 gfp_t gfpmask)
1533{
1534 int page_count, i;
1535 struct address_space *mapping;
1536 struct inode *inode;
1537 struct page *page;
1538
1539 /* Get the list of pages out of our struct file. They'll be pinned
1540 * at this point until we release them.
1541 */
1542 page_count = obj->base.size / PAGE_SIZE;
1543 BUG_ON(obj->pages != NULL);
1544 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1545 if (obj->pages == NULL)
1546 return -ENOMEM;
1547
1548 inode = obj->base.filp->f_path.dentry->d_inode;
1549 mapping = inode->i_mapping;
1550 gfpmask |= mapping_gfp_mask(mapping);
1551
1552 for (i = 0; i < page_count; i++) {
1553 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1554 if (IS_ERR(page))
1555 goto err_pages;
1556
1557 obj->pages[i] = page;
1558 }
1559
1560 if (obj->tiling_mode != I915_TILING_NONE)
1561 i915_gem_object_do_bit_17_swizzle(obj);
1562
1563 return 0;
1564
1565err_pages:
1566 while (i--)
1567 page_cache_release(obj->pages[i]);
1568
1569 drm_free_large(obj->pages);
1570 obj->pages = NULL;
1571 return PTR_ERR(page);
1572}
1573
1574static void
1575i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1576{
1577 int page_count = obj->base.size / PAGE_SIZE;
1578 int i;
1579
1580 BUG_ON(obj->madv == __I915_MADV_PURGED);
1581
1582 if (obj->tiling_mode != I915_TILING_NONE)
1583 i915_gem_object_save_bit_17_swizzle(obj);
1584
1585 if (obj->madv == I915_MADV_DONTNEED)
1586 obj->dirty = 0;
1587
1588 for (i = 0; i < page_count; i++) {
1589 if (obj->dirty)
1590 set_page_dirty(obj->pages[i]);
1591
1592 if (obj->madv == I915_MADV_WILLNEED)
1593 mark_page_accessed(obj->pages[i]);
1594
1595 page_cache_release(obj->pages[i]);
1596 }
1597 obj->dirty = 0;
1598
1599 drm_free_large(obj->pages);
1600 obj->pages = NULL;
1601}
1602
1603void
1604i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1605 struct intel_ring_buffer *ring,
1606 u32 seqno)
1607{
1608 struct drm_device *dev = obj->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610
1611 BUG_ON(ring == NULL);
1612 obj->ring = ring;
1613
1614 /* Add a reference if we're newly entering the active list. */
1615 if (!obj->active) {
1616 drm_gem_object_reference(&obj->base);
1617 obj->active = 1;
1618 }
1619
1620 /* Move from whatever list we were on to the tail of execution. */
1621 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1622 list_move_tail(&obj->ring_list, &ring->active_list);
1623
1624 obj->last_rendering_seqno = seqno;
1625 if (obj->fenced_gpu_access) {
1626 struct drm_i915_fence_reg *reg;
1627
1628 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1629
1630 obj->last_fenced_seqno = seqno;
1631 obj->last_fenced_ring = ring;
1632
1633 reg = &dev_priv->fence_regs[obj->fence_reg];
1634 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
1635 }
1636}
1637
1638static void
1639i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1640{
1641 list_del_init(&obj->ring_list);
1642 obj->last_rendering_seqno = 0;
1643}
1644
1645static void
1646i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1647{
1648 struct drm_device *dev = obj->base.dev;
1649 drm_i915_private_t *dev_priv = dev->dev_private;
1650
1651 BUG_ON(!obj->active);
1652 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1653
1654 i915_gem_object_move_off_active(obj);
1655}
1656
1657static void
1658i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1659{
1660 struct drm_device *dev = obj->base.dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662
1663 if (obj->pin_count != 0)
1664 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1665 else
1666 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1667
1668 BUG_ON(!list_empty(&obj->gpu_write_list));
1669 BUG_ON(!obj->active);
1670 obj->ring = NULL;
1671
1672 i915_gem_object_move_off_active(obj);
1673 obj->fenced_gpu_access = false;
1674
1675 obj->active = 0;
1676 obj->pending_gpu_write = false;
1677 drm_gem_object_unreference(&obj->base);
1678
1679 WARN_ON(i915_verify_lists(dev));
1680}
1681
1682/* Immediately discard the backing storage */
1683static void
1684i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1685{
1686 struct inode *inode;
1687
1688 /* Our goal here is to return as much of the memory as
1689 * is possible back to the system as we are called from OOM.
1690 * To do this we must instruct the shmfs to drop all of its
1691 * backing pages, *now*.
1692 */
1693 inode = obj->base.filp->f_path.dentry->d_inode;
1694 shmem_truncate_range(inode, 0, (loff_t)-1);
1695
1696 obj->madv = __I915_MADV_PURGED;
1697}
1698
1699static inline int
1700i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1701{
1702 return obj->madv == I915_MADV_DONTNEED;
1703}
1704
1705static void
1706i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1707 uint32_t flush_domains)
1708{
1709 struct drm_i915_gem_object *obj, *next;
1710
1711 list_for_each_entry_safe(obj, next,
1712 &ring->gpu_write_list,
1713 gpu_write_list) {
1714 if (obj->base.write_domain & flush_domains) {
1715 uint32_t old_write_domain = obj->base.write_domain;
1716
1717 obj->base.write_domain = 0;
1718 list_del_init(&obj->gpu_write_list);
1719 i915_gem_object_move_to_active(obj, ring,
1720 i915_gem_next_request_seqno(ring));
1721
1722 trace_i915_gem_object_change_domain(obj,
1723 obj->base.read_domains,
1724 old_write_domain);
1725 }
1726 }
1727}
1728
1729int
1730i915_add_request(struct intel_ring_buffer *ring,
1731 struct drm_file *file,
1732 struct drm_i915_gem_request *request)
1733{
1734 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1735 uint32_t seqno;
1736 int was_empty;
1737 int ret;
1738
1739 BUG_ON(request == NULL);
1740
1741 ret = ring->add_request(ring, &seqno);
1742 if (ret)
1743 return ret;
1744
1745 trace_i915_gem_request_add(ring, seqno);
1746
1747 request->seqno = seqno;
1748 request->ring = ring;
1749 request->emitted_jiffies = jiffies;
1750 was_empty = list_empty(&ring->request_list);
1751 list_add_tail(&request->list, &ring->request_list);
1752
1753 if (file) {
1754 struct drm_i915_file_private *file_priv = file->driver_priv;
1755
1756 spin_lock(&file_priv->mm.lock);
1757 request->file_priv = file_priv;
1758 list_add_tail(&request->client_list,
1759 &file_priv->mm.request_list);
1760 spin_unlock(&file_priv->mm.lock);
1761 }
1762
1763 ring->outstanding_lazy_request = false;
1764
1765 if (!dev_priv->mm.suspended) {
1766 if (i915_enable_hangcheck) {
1767 mod_timer(&dev_priv->hangcheck_timer,
1768 jiffies +
1769 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1770 }
1771 if (was_empty)
1772 queue_delayed_work(dev_priv->wq,
1773 &dev_priv->mm.retire_work, HZ);
1774 }
1775 return 0;
1776}
1777
1778static inline void
1779i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1780{
1781 struct drm_i915_file_private *file_priv = request->file_priv;
1782
1783 if (!file_priv)
1784 return;
1785
1786 spin_lock(&file_priv->mm.lock);
1787 if (request->file_priv) {
1788 list_del(&request->client_list);
1789 request->file_priv = NULL;
1790 }
1791 spin_unlock(&file_priv->mm.lock);
1792}
1793
1794static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1795 struct intel_ring_buffer *ring)
1796{
1797 while (!list_empty(&ring->request_list)) {
1798 struct drm_i915_gem_request *request;
1799
1800 request = list_first_entry(&ring->request_list,
1801 struct drm_i915_gem_request,
1802 list);
1803
1804 list_del(&request->list);
1805 i915_gem_request_remove_from_client(request);
1806 kfree(request);
1807 }
1808
1809 while (!list_empty(&ring->active_list)) {
1810 struct drm_i915_gem_object *obj;
1811
1812 obj = list_first_entry(&ring->active_list,
1813 struct drm_i915_gem_object,
1814 ring_list);
1815
1816 obj->base.write_domain = 0;
1817 list_del_init(&obj->gpu_write_list);
1818 i915_gem_object_move_to_inactive(obj);
1819 }
1820}
1821
1822static void i915_gem_reset_fences(struct drm_device *dev)
1823{
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 int i;
1826
1827 for (i = 0; i < 16; i++) {
1828 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1829 struct drm_i915_gem_object *obj = reg->obj;
1830
1831 if (!obj)
1832 continue;
1833
1834 if (obj->tiling_mode)
1835 i915_gem_release_mmap(obj);
1836
1837 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1838 reg->obj->fenced_gpu_access = false;
1839 reg->obj->last_fenced_seqno = 0;
1840 reg->obj->last_fenced_ring = NULL;
1841 i915_gem_clear_fence_reg(dev, reg);
1842 }
1843}
1844
1845void i915_gem_reset(struct drm_device *dev)
1846{
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848 struct drm_i915_gem_object *obj;
1849 int i;
1850
1851 for (i = 0; i < I915_NUM_RINGS; i++)
1852 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1853
1854 /* Remove anything from the flushing lists. The GPU cache is likely
1855 * to be lost on reset along with the data, so simply move the
1856 * lost bo to the inactive list.
1857 */
1858 while (!list_empty(&dev_priv->mm.flushing_list)) {
1859 obj= list_first_entry(&dev_priv->mm.flushing_list,
1860 struct drm_i915_gem_object,
1861 mm_list);
1862
1863 obj->base.write_domain = 0;
1864 list_del_init(&obj->gpu_write_list);
1865 i915_gem_object_move_to_inactive(obj);
1866 }
1867
1868 /* Move everything out of the GPU domains to ensure we do any
1869 * necessary invalidation upon reuse.
1870 */
1871 list_for_each_entry(obj,
1872 &dev_priv->mm.inactive_list,
1873 mm_list)
1874 {
1875 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1876 }
1877
1878 /* The fence registers are invalidated so clear them out */
1879 i915_gem_reset_fences(dev);
1880}
1881
1882/**
1883 * This function clears the request list as sequence numbers are passed.
1884 */
1885static void
1886i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1887{
1888 uint32_t seqno;
1889 int i;
1890
1891 if (list_empty(&ring->request_list))
1892 return;
1893
1894 WARN_ON(i915_verify_lists(ring->dev));
1895
1896 seqno = ring->get_seqno(ring);
1897
1898 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1899 if (seqno >= ring->sync_seqno[i])
1900 ring->sync_seqno[i] = 0;
1901
1902 while (!list_empty(&ring->request_list)) {
1903 struct drm_i915_gem_request *request;
1904
1905 request = list_first_entry(&ring->request_list,
1906 struct drm_i915_gem_request,
1907 list);
1908
1909 if (!i915_seqno_passed(seqno, request->seqno))
1910 break;
1911
1912 trace_i915_gem_request_retire(ring, request->seqno);
1913
1914 list_del(&request->list);
1915 i915_gem_request_remove_from_client(request);
1916 kfree(request);
1917 }
1918
1919 /* Move any buffers on the active list that are no longer referenced
1920 * by the ringbuffer to the flushing/inactive lists as appropriate.
1921 */
1922 while (!list_empty(&ring->active_list)) {
1923 struct drm_i915_gem_object *obj;
1924
1925 obj= list_first_entry(&ring->active_list,
1926 struct drm_i915_gem_object,
1927 ring_list);
1928
1929 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1930 break;
1931
1932 if (obj->base.write_domain != 0)
1933 i915_gem_object_move_to_flushing(obj);
1934 else
1935 i915_gem_object_move_to_inactive(obj);
1936 }
1937
1938 if (unlikely(ring->trace_irq_seqno &&
1939 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1940 ring->irq_put(ring);
1941 ring->trace_irq_seqno = 0;
1942 }
1943
1944 WARN_ON(i915_verify_lists(ring->dev));
1945}
1946
1947void
1948i915_gem_retire_requests(struct drm_device *dev)
1949{
1950 drm_i915_private_t *dev_priv = dev->dev_private;
1951 int i;
1952
1953 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1954 struct drm_i915_gem_object *obj, *next;
1955
1956 /* We must be careful that during unbind() we do not
1957 * accidentally infinitely recurse into retire requests.
1958 * Currently:
1959 * retire -> free -> unbind -> wait -> retire_ring
1960 */
1961 list_for_each_entry_safe(obj, next,
1962 &dev_priv->mm.deferred_free_list,
1963 mm_list)
1964 i915_gem_free_object_tail(obj);
1965 }
1966
1967 for (i = 0; i < I915_NUM_RINGS; i++)
1968 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1969}
1970
1971static void
1972i915_gem_retire_work_handler(struct work_struct *work)
1973{
1974 drm_i915_private_t *dev_priv;
1975 struct drm_device *dev;
1976 bool idle;
1977 int i;
1978
1979 dev_priv = container_of(work, drm_i915_private_t,
1980 mm.retire_work.work);
1981 dev = dev_priv->dev;
1982
1983 /* Come back later if the device is busy... */
1984 if (!mutex_trylock(&dev->struct_mutex)) {
1985 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1986 return;
1987 }
1988
1989 i915_gem_retire_requests(dev);
1990
1991 /* Send a periodic flush down the ring so we don't hold onto GEM
1992 * objects indefinitely.
1993 */
1994 idle = true;
1995 for (i = 0; i < I915_NUM_RINGS; i++) {
1996 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1997
1998 if (!list_empty(&ring->gpu_write_list)) {
1999 struct drm_i915_gem_request *request;
2000 int ret;
2001
2002 ret = i915_gem_flush_ring(ring,
2003 0, I915_GEM_GPU_DOMAINS);
2004 request = kzalloc(sizeof(*request), GFP_KERNEL);
2005 if (ret || request == NULL ||
2006 i915_add_request(ring, NULL, request))
2007 kfree(request);
2008 }
2009
2010 idle &= list_empty(&ring->request_list);
2011 }
2012
2013 if (!dev_priv->mm.suspended && !idle)
2014 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2015
2016 mutex_unlock(&dev->struct_mutex);
2017}
2018
2019/**
2020 * Waits for a sequence number to be signaled, and cleans up the
2021 * request and object lists appropriately for that event.
2022 */
2023int
2024i915_wait_request(struct intel_ring_buffer *ring,
2025 uint32_t seqno)
2026{
2027 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2028 u32 ier;
2029 int ret = 0;
2030
2031 BUG_ON(seqno == 0);
2032
2033 if (atomic_read(&dev_priv->mm.wedged)) {
2034 struct completion *x = &dev_priv->error_completion;
2035 bool recovery_complete;
2036 unsigned long flags;
2037
2038 /* Give the error handler a chance to run. */
2039 spin_lock_irqsave(&x->wait.lock, flags);
2040 recovery_complete = x->done > 0;
2041 spin_unlock_irqrestore(&x->wait.lock, flags);
2042
2043 return recovery_complete ? -EIO : -EAGAIN;
2044 }
2045
2046 if (seqno == ring->outstanding_lazy_request) {
2047 struct drm_i915_gem_request *request;
2048
2049 request = kzalloc(sizeof(*request), GFP_KERNEL);
2050 if (request == NULL)
2051 return -ENOMEM;
2052
2053 ret = i915_add_request(ring, NULL, request);
2054 if (ret) {
2055 kfree(request);
2056 return ret;
2057 }
2058
2059 seqno = request->seqno;
2060 }
2061
2062 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2063 if (HAS_PCH_SPLIT(ring->dev))
2064 ier = I915_READ(DEIER) | I915_READ(GTIER);
2065 else
2066 ier = I915_READ(IER);
2067 if (!ier) {
2068 DRM_ERROR("something (likely vbetool) disabled "
2069 "interrupts, re-enabling\n");
2070 ring->dev->driver->irq_preinstall(ring->dev);
2071 ring->dev->driver->irq_postinstall(ring->dev);
2072 }
2073
2074 trace_i915_gem_request_wait_begin(ring, seqno);
2075
2076 ring->waiting_seqno = seqno;
2077 if (ring->irq_get(ring)) {
2078 if (dev_priv->mm.interruptible)
2079 ret = wait_event_interruptible(ring->irq_queue,
2080 i915_seqno_passed(ring->get_seqno(ring), seqno)
2081 || atomic_read(&dev_priv->mm.wedged));
2082 else
2083 wait_event(ring->irq_queue,
2084 i915_seqno_passed(ring->get_seqno(ring), seqno)
2085 || atomic_read(&dev_priv->mm.wedged));
2086
2087 ring->irq_put(ring);
2088 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2089 seqno) ||
2090 atomic_read(&dev_priv->mm.wedged), 3000))
2091 ret = -EBUSY;
2092 ring->waiting_seqno = 0;
2093
2094 trace_i915_gem_request_wait_end(ring, seqno);
2095 }
2096 if (atomic_read(&dev_priv->mm.wedged))
2097 ret = -EAGAIN;
2098
2099 if (ret && ret != -ERESTARTSYS)
2100 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2101 __func__, ret, seqno, ring->get_seqno(ring),
2102 dev_priv->next_seqno);
2103
2104 /* Directly dispatch request retiring. While we have the work queue
2105 * to handle this, the waiter on a request often wants an associated
2106 * buffer to have made it to the inactive list, and we would need
2107 * a separate wait queue to handle that.
2108 */
2109 if (ret == 0)
2110 i915_gem_retire_requests_ring(ring);
2111
2112 return ret;
2113}
2114
2115/**
2116 * Ensures that all rendering to the object has completed and the object is
2117 * safe to unbind from the GTT or access from the CPU.
2118 */
2119int
2120i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2121{
2122 int ret;
2123
2124 /* This function only exists to support waiting for existing rendering,
2125 * not for emitting required flushes.
2126 */
2127 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2128
2129 /* If there is rendering queued on the buffer being evicted, wait for
2130 * it.
2131 */
2132 if (obj->active) {
2133 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2134 if (ret)
2135 return ret;
2136 }
2137
2138 return 0;
2139}
2140
2141static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2142{
2143 u32 old_write_domain, old_read_domains;
2144
2145 /* Act a barrier for all accesses through the GTT */
2146 mb();
2147
2148 /* Force a pagefault for domain tracking on next user access */
2149 i915_gem_release_mmap(obj);
2150
2151 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2152 return;
2153
2154 old_read_domains = obj->base.read_domains;
2155 old_write_domain = obj->base.write_domain;
2156
2157 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2158 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2159
2160 trace_i915_gem_object_change_domain(obj,
2161 old_read_domains,
2162 old_write_domain);
2163}
2164
2165/**
2166 * Unbinds an object from the GTT aperture.
2167 */
2168int
2169i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2170{
2171 int ret = 0;
2172
2173 if (obj->gtt_space == NULL)
2174 return 0;
2175
2176 if (obj->pin_count != 0) {
2177 DRM_ERROR("Attempting to unbind pinned buffer\n");
2178 return -EINVAL;
2179 }
2180
2181 ret = i915_gem_object_finish_gpu(obj);
2182 if (ret == -ERESTARTSYS)
2183 return ret;
2184 /* Continue on if we fail due to EIO, the GPU is hung so we
2185 * should be safe and we need to cleanup or else we might
2186 * cause memory corruption through use-after-free.
2187 */
2188
2189 i915_gem_object_finish_gtt(obj);
2190
2191 /* Move the object to the CPU domain to ensure that
2192 * any possible CPU writes while it's not in the GTT
2193 * are flushed when we go to remap it.
2194 */
2195 if (ret == 0)
2196 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2197 if (ret == -ERESTARTSYS)
2198 return ret;
2199 if (ret) {
2200 /* In the event of a disaster, abandon all caches and
2201 * hope for the best.
2202 */
2203 i915_gem_clflush_object(obj);
2204 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2205 }
2206
2207 /* release the fence reg _after_ flushing */
2208 ret = i915_gem_object_put_fence(obj);
2209 if (ret == -ERESTARTSYS)
2210 return ret;
2211
2212 trace_i915_gem_object_unbind(obj);
2213
2214 i915_gem_gtt_unbind_object(obj);
2215 i915_gem_object_put_pages_gtt(obj);
2216
2217 list_del_init(&obj->gtt_list);
2218 list_del_init(&obj->mm_list);
2219 /* Avoid an unnecessary call to unbind on rebind. */
2220 obj->map_and_fenceable = true;
2221
2222 drm_mm_put_block(obj->gtt_space);
2223 obj->gtt_space = NULL;
2224 obj->gtt_offset = 0;
2225
2226 if (i915_gem_object_is_purgeable(obj))
2227 i915_gem_object_truncate(obj);
2228
2229 return ret;
2230}
2231
2232int
2233i915_gem_flush_ring(struct intel_ring_buffer *ring,
2234 uint32_t invalidate_domains,
2235 uint32_t flush_domains)
2236{
2237 int ret;
2238
2239 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2240 return 0;
2241
2242 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2243
2244 ret = ring->flush(ring, invalidate_domains, flush_domains);
2245 if (ret)
2246 return ret;
2247
2248 if (flush_domains & I915_GEM_GPU_DOMAINS)
2249 i915_gem_process_flushing_list(ring, flush_domains);
2250
2251 return 0;
2252}
2253
2254static int i915_ring_idle(struct intel_ring_buffer *ring)
2255{
2256 int ret;
2257
2258 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2259 return 0;
2260
2261 if (!list_empty(&ring->gpu_write_list)) {
2262 ret = i915_gem_flush_ring(ring,
2263 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2264 if (ret)
2265 return ret;
2266 }
2267
2268 return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2269}
2270
2271int
2272i915_gpu_idle(struct drm_device *dev)
2273{
2274 drm_i915_private_t *dev_priv = dev->dev_private;
2275 bool lists_empty;
2276 int ret, i;
2277
2278 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2279 list_empty(&dev_priv->mm.active_list));
2280 if (lists_empty)
2281 return 0;
2282
2283 /* Flush everything onto the inactive list. */
2284 for (i = 0; i < I915_NUM_RINGS; i++) {
2285 ret = i915_ring_idle(&dev_priv->ring[i]);
2286 if (ret)
2287 return ret;
2288 }
2289
2290 return 0;
2291}
2292
2293static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2294 struct intel_ring_buffer *pipelined)
2295{
2296 struct drm_device *dev = obj->base.dev;
2297 drm_i915_private_t *dev_priv = dev->dev_private;
2298 u32 size = obj->gtt_space->size;
2299 int regnum = obj->fence_reg;
2300 uint64_t val;
2301
2302 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2303 0xfffff000) << 32;
2304 val |= obj->gtt_offset & 0xfffff000;
2305 val |= (uint64_t)((obj->stride / 128) - 1) <<
2306 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2307
2308 if (obj->tiling_mode == I915_TILING_Y)
2309 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2310 val |= I965_FENCE_REG_VALID;
2311
2312 if (pipelined) {
2313 int ret = intel_ring_begin(pipelined, 6);
2314 if (ret)
2315 return ret;
2316
2317 intel_ring_emit(pipelined, MI_NOOP);
2318 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2319 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2320 intel_ring_emit(pipelined, (u32)val);
2321 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2322 intel_ring_emit(pipelined, (u32)(val >> 32));
2323 intel_ring_advance(pipelined);
2324 } else
2325 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2326
2327 return 0;
2328}
2329
2330static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2331 struct intel_ring_buffer *pipelined)
2332{
2333 struct drm_device *dev = obj->base.dev;
2334 drm_i915_private_t *dev_priv = dev->dev_private;
2335 u32 size = obj->gtt_space->size;
2336 int regnum = obj->fence_reg;
2337 uint64_t val;
2338
2339 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2340 0xfffff000) << 32;
2341 val |= obj->gtt_offset & 0xfffff000;
2342 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2343 if (obj->tiling_mode == I915_TILING_Y)
2344 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2345 val |= I965_FENCE_REG_VALID;
2346
2347 if (pipelined) {
2348 int ret = intel_ring_begin(pipelined, 6);
2349 if (ret)
2350 return ret;
2351
2352 intel_ring_emit(pipelined, MI_NOOP);
2353 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2354 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2355 intel_ring_emit(pipelined, (u32)val);
2356 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2357 intel_ring_emit(pipelined, (u32)(val >> 32));
2358 intel_ring_advance(pipelined);
2359 } else
2360 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2361
2362 return 0;
2363}
2364
2365static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2366 struct intel_ring_buffer *pipelined)
2367{
2368 struct drm_device *dev = obj->base.dev;
2369 drm_i915_private_t *dev_priv = dev->dev_private;
2370 u32 size = obj->gtt_space->size;
2371 u32 fence_reg, val, pitch_val;
2372 int tile_width;
2373
2374 if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2375 (size & -size) != size ||
2376 (obj->gtt_offset & (size - 1)),
2377 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2378 obj->gtt_offset, obj->map_and_fenceable, size))
2379 return -EINVAL;
2380
2381 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2382 tile_width = 128;
2383 else
2384 tile_width = 512;
2385
2386 /* Note: pitch better be a power of two tile widths */
2387 pitch_val = obj->stride / tile_width;
2388 pitch_val = ffs(pitch_val) - 1;
2389
2390 val = obj->gtt_offset;
2391 if (obj->tiling_mode == I915_TILING_Y)
2392 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2393 val |= I915_FENCE_SIZE_BITS(size);
2394 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2395 val |= I830_FENCE_REG_VALID;
2396
2397 fence_reg = obj->fence_reg;
2398 if (fence_reg < 8)
2399 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2400 else
2401 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2402
2403 if (pipelined) {
2404 int ret = intel_ring_begin(pipelined, 4);
2405 if (ret)
2406 return ret;
2407
2408 intel_ring_emit(pipelined, MI_NOOP);
2409 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2410 intel_ring_emit(pipelined, fence_reg);
2411 intel_ring_emit(pipelined, val);
2412 intel_ring_advance(pipelined);
2413 } else
2414 I915_WRITE(fence_reg, val);
2415
2416 return 0;
2417}
2418
2419static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2420 struct intel_ring_buffer *pipelined)
2421{
2422 struct drm_device *dev = obj->base.dev;
2423 drm_i915_private_t *dev_priv = dev->dev_private;
2424 u32 size = obj->gtt_space->size;
2425 int regnum = obj->fence_reg;
2426 uint32_t val;
2427 uint32_t pitch_val;
2428
2429 if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2430 (size & -size) != size ||
2431 (obj->gtt_offset & (size - 1)),
2432 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2433 obj->gtt_offset, size))
2434 return -EINVAL;
2435
2436 pitch_val = obj->stride / 128;
2437 pitch_val = ffs(pitch_val) - 1;
2438
2439 val = obj->gtt_offset;
2440 if (obj->tiling_mode == I915_TILING_Y)
2441 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2442 val |= I830_FENCE_SIZE_BITS(size);
2443 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2444 val |= I830_FENCE_REG_VALID;
2445
2446 if (pipelined) {
2447 int ret = intel_ring_begin(pipelined, 4);
2448 if (ret)
2449 return ret;
2450
2451 intel_ring_emit(pipelined, MI_NOOP);
2452 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2453 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2454 intel_ring_emit(pipelined, val);
2455 intel_ring_advance(pipelined);
2456 } else
2457 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2458
2459 return 0;
2460}
2461
2462static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2463{
2464 return i915_seqno_passed(ring->get_seqno(ring), seqno);
2465}
2466
2467static int
2468i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2469 struct intel_ring_buffer *pipelined)
2470{
2471 int ret;
2472
2473 if (obj->fenced_gpu_access) {
2474 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2475 ret = i915_gem_flush_ring(obj->last_fenced_ring,
2476 0, obj->base.write_domain);
2477 if (ret)
2478 return ret;
2479 }
2480
2481 obj->fenced_gpu_access = false;
2482 }
2483
2484 if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2485 if (!ring_passed_seqno(obj->last_fenced_ring,
2486 obj->last_fenced_seqno)) {
2487 ret = i915_wait_request(obj->last_fenced_ring,
2488 obj->last_fenced_seqno);
2489 if (ret)
2490 return ret;
2491 }
2492
2493 obj->last_fenced_seqno = 0;
2494 obj->last_fenced_ring = NULL;
2495 }
2496
2497 /* Ensure that all CPU reads are completed before installing a fence
2498 * and all writes before removing the fence.
2499 */
2500 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2501 mb();
2502
2503 return 0;
2504}
2505
2506int
2507i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2508{
2509 int ret;
2510
2511 if (obj->tiling_mode)
2512 i915_gem_release_mmap(obj);
2513
2514 ret = i915_gem_object_flush_fence(obj, NULL);
2515 if (ret)
2516 return ret;
2517
2518 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2519 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2520 i915_gem_clear_fence_reg(obj->base.dev,
2521 &dev_priv->fence_regs[obj->fence_reg]);
2522
2523 obj->fence_reg = I915_FENCE_REG_NONE;
2524 }
2525
2526 return 0;
2527}
2528
2529static struct drm_i915_fence_reg *
2530i915_find_fence_reg(struct drm_device *dev,
2531 struct intel_ring_buffer *pipelined)
2532{
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534 struct drm_i915_fence_reg *reg, *first, *avail;
2535 int i;
2536
2537 /* First try to find a free reg */
2538 avail = NULL;
2539 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2540 reg = &dev_priv->fence_regs[i];
2541 if (!reg->obj)
2542 return reg;
2543
2544 if (!reg->obj->pin_count)
2545 avail = reg;
2546 }
2547
2548 if (avail == NULL)
2549 return NULL;
2550
2551 /* None available, try to steal one or wait for a user to finish */
2552 avail = first = NULL;
2553 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2554 if (reg->obj->pin_count)
2555 continue;
2556
2557 if (first == NULL)
2558 first = reg;
2559
2560 if (!pipelined ||
2561 !reg->obj->last_fenced_ring ||
2562 reg->obj->last_fenced_ring == pipelined) {
2563 avail = reg;
2564 break;
2565 }
2566 }
2567
2568 if (avail == NULL)
2569 avail = first;
2570
2571 return avail;
2572}
2573
2574/**
2575 * i915_gem_object_get_fence - set up a fence reg for an object
2576 * @obj: object to map through a fence reg
2577 * @pipelined: ring on which to queue the change, or NULL for CPU access
2578 * @interruptible: must we wait uninterruptibly for the register to retire?
2579 *
2580 * When mapping objects through the GTT, userspace wants to be able to write
2581 * to them without having to worry about swizzling if the object is tiled.
2582 *
2583 * This function walks the fence regs looking for a free one for @obj,
2584 * stealing one if it can't find any.
2585 *
2586 * It then sets up the reg based on the object's properties: address, pitch
2587 * and tiling format.
2588 */
2589int
2590i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2591 struct intel_ring_buffer *pipelined)
2592{
2593 struct drm_device *dev = obj->base.dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct drm_i915_fence_reg *reg;
2596 int ret;
2597
2598 /* XXX disable pipelining. There are bugs. Shocking. */
2599 pipelined = NULL;
2600
2601 /* Just update our place in the LRU if our fence is getting reused. */
2602 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2603 reg = &dev_priv->fence_regs[obj->fence_reg];
2604 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2605
2606 if (obj->tiling_changed) {
2607 ret = i915_gem_object_flush_fence(obj, pipelined);
2608 if (ret)
2609 return ret;
2610
2611 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2612 pipelined = NULL;
2613
2614 if (pipelined) {
2615 reg->setup_seqno =
2616 i915_gem_next_request_seqno(pipelined);
2617 obj->last_fenced_seqno = reg->setup_seqno;
2618 obj->last_fenced_ring = pipelined;
2619 }
2620
2621 goto update;
2622 }
2623
2624 if (!pipelined) {
2625 if (reg->setup_seqno) {
2626 if (!ring_passed_seqno(obj->last_fenced_ring,
2627 reg->setup_seqno)) {
2628 ret = i915_wait_request(obj->last_fenced_ring,
2629 reg->setup_seqno);
2630 if (ret)
2631 return ret;
2632 }
2633
2634 reg->setup_seqno = 0;
2635 }
2636 } else if (obj->last_fenced_ring &&
2637 obj->last_fenced_ring != pipelined) {
2638 ret = i915_gem_object_flush_fence(obj, pipelined);
2639 if (ret)
2640 return ret;
2641 }
2642
2643 return 0;
2644 }
2645
2646 reg = i915_find_fence_reg(dev, pipelined);
2647 if (reg == NULL)
2648 return -ENOSPC;
2649
2650 ret = i915_gem_object_flush_fence(obj, pipelined);
2651 if (ret)
2652 return ret;
2653
2654 if (reg->obj) {
2655 struct drm_i915_gem_object *old = reg->obj;
2656
2657 drm_gem_object_reference(&old->base);
2658
2659 if (old->tiling_mode)
2660 i915_gem_release_mmap(old);
2661
2662 ret = i915_gem_object_flush_fence(old, pipelined);
2663 if (ret) {
2664 drm_gem_object_unreference(&old->base);
2665 return ret;
2666 }
2667
2668 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2669 pipelined = NULL;
2670
2671 old->fence_reg = I915_FENCE_REG_NONE;
2672 old->last_fenced_ring = pipelined;
2673 old->last_fenced_seqno =
2674 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2675
2676 drm_gem_object_unreference(&old->base);
2677 } else if (obj->last_fenced_seqno == 0)
2678 pipelined = NULL;
2679
2680 reg->obj = obj;
2681 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2682 obj->fence_reg = reg - dev_priv->fence_regs;
2683 obj->last_fenced_ring = pipelined;
2684
2685 reg->setup_seqno =
2686 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2687 obj->last_fenced_seqno = reg->setup_seqno;
2688
2689update:
2690 obj->tiling_changed = false;
2691 switch (INTEL_INFO(dev)->gen) {
2692 case 7:
2693 case 6:
2694 ret = sandybridge_write_fence_reg(obj, pipelined);
2695 break;
2696 case 5:
2697 case 4:
2698 ret = i965_write_fence_reg(obj, pipelined);
2699 break;
2700 case 3:
2701 ret = i915_write_fence_reg(obj, pipelined);
2702 break;
2703 case 2:
2704 ret = i830_write_fence_reg(obj, pipelined);
2705 break;
2706 }
2707
2708 return ret;
2709}
2710
2711/**
2712 * i915_gem_clear_fence_reg - clear out fence register info
2713 * @obj: object to clear
2714 *
2715 * Zeroes out the fence register itself and clears out the associated
2716 * data structures in dev_priv and obj.
2717 */
2718static void
2719i915_gem_clear_fence_reg(struct drm_device *dev,
2720 struct drm_i915_fence_reg *reg)
2721{
2722 drm_i915_private_t *dev_priv = dev->dev_private;
2723 uint32_t fence_reg = reg - dev_priv->fence_regs;
2724
2725 switch (INTEL_INFO(dev)->gen) {
2726 case 7:
2727 case 6:
2728 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2729 break;
2730 case 5:
2731 case 4:
2732 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2733 break;
2734 case 3:
2735 if (fence_reg >= 8)
2736 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2737 else
2738 case 2:
2739 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2740
2741 I915_WRITE(fence_reg, 0);
2742 break;
2743 }
2744
2745 list_del_init(®->lru_list);
2746 reg->obj = NULL;
2747 reg->setup_seqno = 0;
2748}
2749
2750/**
2751 * Finds free space in the GTT aperture and binds the object there.
2752 */
2753static int
2754i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2755 unsigned alignment,
2756 bool map_and_fenceable)
2757{
2758 struct drm_device *dev = obj->base.dev;
2759 drm_i915_private_t *dev_priv = dev->dev_private;
2760 struct drm_mm_node *free_space;
2761 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2762 u32 size, fence_size, fence_alignment, unfenced_alignment;
2763 bool mappable, fenceable;
2764 int ret;
2765
2766 if (obj->madv != I915_MADV_WILLNEED) {
2767 DRM_ERROR("Attempting to bind a purgeable object\n");
2768 return -EINVAL;
2769 }
2770
2771 fence_size = i915_gem_get_gtt_size(dev,
2772 obj->base.size,
2773 obj->tiling_mode);
2774 fence_alignment = i915_gem_get_gtt_alignment(dev,
2775 obj->base.size,
2776 obj->tiling_mode);
2777 unfenced_alignment =
2778 i915_gem_get_unfenced_gtt_alignment(dev,
2779 obj->base.size,
2780 obj->tiling_mode);
2781
2782 if (alignment == 0)
2783 alignment = map_and_fenceable ? fence_alignment :
2784 unfenced_alignment;
2785 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2786 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2787 return -EINVAL;
2788 }
2789
2790 size = map_and_fenceable ? fence_size : obj->base.size;
2791
2792 /* If the object is bigger than the entire aperture, reject it early
2793 * before evicting everything in a vain attempt to find space.
2794 */
2795 if (obj->base.size >
2796 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2797 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2798 return -E2BIG;
2799 }
2800
2801 search_free:
2802 if (map_and_fenceable)
2803 free_space =
2804 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2805 size, alignment, 0,
2806 dev_priv->mm.gtt_mappable_end,
2807 0);
2808 else
2809 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2810 size, alignment, 0);
2811
2812 if (free_space != NULL) {
2813 if (map_and_fenceable)
2814 obj->gtt_space =
2815 drm_mm_get_block_range_generic(free_space,
2816 size, alignment, 0,
2817 dev_priv->mm.gtt_mappable_end,
2818 0);
2819 else
2820 obj->gtt_space =
2821 drm_mm_get_block(free_space, size, alignment);
2822 }
2823 if (obj->gtt_space == NULL) {
2824 /* If the gtt is empty and we're still having trouble
2825 * fitting our object in, we're out of memory.
2826 */
2827 ret = i915_gem_evict_something(dev, size, alignment,
2828 map_and_fenceable);
2829 if (ret)
2830 return ret;
2831
2832 goto search_free;
2833 }
2834
2835 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2836 if (ret) {
2837 drm_mm_put_block(obj->gtt_space);
2838 obj->gtt_space = NULL;
2839
2840 if (ret == -ENOMEM) {
2841 /* first try to reclaim some memory by clearing the GTT */
2842 ret = i915_gem_evict_everything(dev, false);
2843 if (ret) {
2844 /* now try to shrink everyone else */
2845 if (gfpmask) {
2846 gfpmask = 0;
2847 goto search_free;
2848 }
2849
2850 return -ENOMEM;
2851 }
2852
2853 goto search_free;
2854 }
2855
2856 return ret;
2857 }
2858
2859 ret = i915_gem_gtt_bind_object(obj);
2860 if (ret) {
2861 i915_gem_object_put_pages_gtt(obj);
2862 drm_mm_put_block(obj->gtt_space);
2863 obj->gtt_space = NULL;
2864
2865 if (i915_gem_evict_everything(dev, false))
2866 return ret;
2867
2868 goto search_free;
2869 }
2870
2871 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2872 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2873
2874 /* Assert that the object is not currently in any GPU domain. As it
2875 * wasn't in the GTT, there shouldn't be any way it could have been in
2876 * a GPU cache
2877 */
2878 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2879 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2880
2881 obj->gtt_offset = obj->gtt_space->start;
2882
2883 fenceable =
2884 obj->gtt_space->size == fence_size &&
2885 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2886
2887 mappable =
2888 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2889
2890 obj->map_and_fenceable = mappable && fenceable;
2891
2892 trace_i915_gem_object_bind(obj, map_and_fenceable);
2893 return 0;
2894}
2895
2896void
2897i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2898{
2899 /* If we don't have a page list set up, then we're not pinned
2900 * to GPU, and we can ignore the cache flush because it'll happen
2901 * again at bind time.
2902 */
2903 if (obj->pages == NULL)
2904 return;
2905
2906 /* If the GPU is snooping the contents of the CPU cache,
2907 * we do not need to manually clear the CPU cache lines. However,
2908 * the caches are only snooped when the render cache is
2909 * flushed/invalidated. As we always have to emit invalidations
2910 * and flushes when moving into and out of the RENDER domain, correct
2911 * snooping behaviour occurs naturally as the result of our domain
2912 * tracking.
2913 */
2914 if (obj->cache_level != I915_CACHE_NONE)
2915 return;
2916
2917 trace_i915_gem_object_clflush(obj);
2918
2919 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2920}
2921
2922/** Flushes any GPU write domain for the object if it's dirty. */
2923static int
2924i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2925{
2926 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2927 return 0;
2928
2929 /* Queue the GPU write cache flushing we need. */
2930 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2931}
2932
2933/** Flushes the GTT write domain for the object if it's dirty. */
2934static void
2935i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2936{
2937 uint32_t old_write_domain;
2938
2939 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2940 return;
2941
2942 /* No actual flushing is required for the GTT write domain. Writes
2943 * to it immediately go to main memory as far as we know, so there's
2944 * no chipset flush. It also doesn't land in render cache.
2945 *
2946 * However, we do have to enforce the order so that all writes through
2947 * the GTT land before any writes to the device, such as updates to
2948 * the GATT itself.
2949 */
2950 wmb();
2951
2952 old_write_domain = obj->base.write_domain;
2953 obj->base.write_domain = 0;
2954
2955 trace_i915_gem_object_change_domain(obj,
2956 obj->base.read_domains,
2957 old_write_domain);
2958}
2959
2960/** Flushes the CPU write domain for the object if it's dirty. */
2961static void
2962i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2963{
2964 uint32_t old_write_domain;
2965
2966 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2967 return;
2968
2969 i915_gem_clflush_object(obj);
2970 intel_gtt_chipset_flush();
2971 old_write_domain = obj->base.write_domain;
2972 obj->base.write_domain = 0;
2973
2974 trace_i915_gem_object_change_domain(obj,
2975 obj->base.read_domains,
2976 old_write_domain);
2977}
2978
2979/**
2980 * Moves a single object to the GTT read, and possibly write domain.
2981 *
2982 * This function returns when the move is complete, including waiting on
2983 * flushes to occur.
2984 */
2985int
2986i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2987{
2988 uint32_t old_write_domain, old_read_domains;
2989 int ret;
2990
2991 /* Not valid to be called on unbound objects. */
2992 if (obj->gtt_space == NULL)
2993 return -EINVAL;
2994
2995 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2996 return 0;
2997
2998 ret = i915_gem_object_flush_gpu_write_domain(obj);
2999 if (ret)
3000 return ret;
3001
3002 if (obj->pending_gpu_write || write) {
3003 ret = i915_gem_object_wait_rendering(obj);
3004 if (ret)
3005 return ret;
3006 }
3007
3008 i915_gem_object_flush_cpu_write_domain(obj);
3009
3010 old_write_domain = obj->base.write_domain;
3011 old_read_domains = obj->base.read_domains;
3012
3013 /* It should now be out of any other write domains, and we can update
3014 * the domain values for our changes.
3015 */
3016 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3017 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3018 if (write) {
3019 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3020 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3021 obj->dirty = 1;
3022 }
3023
3024 trace_i915_gem_object_change_domain(obj,
3025 old_read_domains,
3026 old_write_domain);
3027
3028 return 0;
3029}
3030
3031int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3032 enum i915_cache_level cache_level)
3033{
3034 int ret;
3035
3036 if (obj->cache_level == cache_level)
3037 return 0;
3038
3039 if (obj->pin_count) {
3040 DRM_DEBUG("can not change the cache level of pinned objects\n");
3041 return -EBUSY;
3042 }
3043
3044 if (obj->gtt_space) {
3045 ret = i915_gem_object_finish_gpu(obj);
3046 if (ret)
3047 return ret;
3048
3049 i915_gem_object_finish_gtt(obj);
3050
3051 /* Before SandyBridge, you could not use tiling or fence
3052 * registers with snooped memory, so relinquish any fences
3053 * currently pointing to our region in the aperture.
3054 */
3055 if (INTEL_INFO(obj->base.dev)->gen < 6) {
3056 ret = i915_gem_object_put_fence(obj);
3057 if (ret)
3058 return ret;
3059 }
3060
3061 i915_gem_gtt_rebind_object(obj, cache_level);
3062 }
3063
3064 if (cache_level == I915_CACHE_NONE) {
3065 u32 old_read_domains, old_write_domain;
3066
3067 /* If we're coming from LLC cached, then we haven't
3068 * actually been tracking whether the data is in the
3069 * CPU cache or not, since we only allow one bit set
3070 * in obj->write_domain and have been skipping the clflushes.
3071 * Just set it to the CPU cache for now.
3072 */
3073 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3074 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3075
3076 old_read_domains = obj->base.read_domains;
3077 old_write_domain = obj->base.write_domain;
3078
3079 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3080 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3081
3082 trace_i915_gem_object_change_domain(obj,
3083 old_read_domains,
3084 old_write_domain);
3085 }
3086
3087 obj->cache_level = cache_level;
3088 return 0;
3089}
3090
3091/*
3092 * Prepare buffer for display plane (scanout, cursors, etc).
3093 * Can be called from an uninterruptible phase (modesetting) and allows
3094 * any flushes to be pipelined (for pageflips).
3095 *
3096 * For the display plane, we want to be in the GTT but out of any write
3097 * domains. So in many ways this looks like set_to_gtt_domain() apart from the
3098 * ability to pipeline the waits, pinning and any additional subtleties
3099 * that may differentiate the display plane from ordinary buffers.
3100 */
3101int
3102i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3103 u32 alignment,
3104 struct intel_ring_buffer *pipelined)
3105{
3106 u32 old_read_domains, old_write_domain;
3107 int ret;
3108
3109 ret = i915_gem_object_flush_gpu_write_domain(obj);
3110 if (ret)
3111 return ret;
3112
3113 if (pipelined != obj->ring) {
3114 ret = i915_gem_object_wait_rendering(obj);
3115 if (ret == -ERESTARTSYS)
3116 return ret;
3117 }
3118
3119 /* The display engine is not coherent with the LLC cache on gen6. As
3120 * a result, we make sure that the pinning that is about to occur is
3121 * done with uncached PTEs. This is lowest common denominator for all
3122 * chipsets.
3123 *
3124 * However for gen6+, we could do better by using the GFDT bit instead
3125 * of uncaching, which would allow us to flush all the LLC-cached data
3126 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3127 */
3128 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3129 if (ret)
3130 return ret;
3131
3132 /* As the user may map the buffer once pinned in the display plane
3133 * (e.g. libkms for the bootup splash), we have to ensure that we
3134 * always use map_and_fenceable for all scanout buffers.
3135 */
3136 ret = i915_gem_object_pin(obj, alignment, true);
3137 if (ret)
3138 return ret;
3139
3140 i915_gem_object_flush_cpu_write_domain(obj);
3141
3142 old_write_domain = obj->base.write_domain;
3143 old_read_domains = obj->base.read_domains;
3144
3145 /* It should now be out of any other write domains, and we can update
3146 * the domain values for our changes.
3147 */
3148 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3149 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3150
3151 trace_i915_gem_object_change_domain(obj,
3152 old_read_domains,
3153 old_write_domain);
3154
3155 return 0;
3156}
3157
3158int
3159i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3160{
3161 int ret;
3162
3163 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3164 return 0;
3165
3166 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3167 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3168 if (ret)
3169 return ret;
3170 }
3171
3172 /* Ensure that we invalidate the GPU's caches and TLBs. */
3173 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3174
3175 return i915_gem_object_wait_rendering(obj);
3176}
3177
3178/**
3179 * Moves a single object to the CPU read, and possibly write domain.
3180 *
3181 * This function returns when the move is complete, including waiting on
3182 * flushes to occur.
3183 */
3184static int
3185i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3186{
3187 uint32_t old_write_domain, old_read_domains;
3188 int ret;
3189
3190 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3191 return 0;
3192
3193 ret = i915_gem_object_flush_gpu_write_domain(obj);
3194 if (ret)
3195 return ret;
3196
3197 ret = i915_gem_object_wait_rendering(obj);
3198 if (ret)
3199 return ret;
3200
3201 i915_gem_object_flush_gtt_write_domain(obj);
3202
3203 /* If we have a partially-valid cache of the object in the CPU,
3204 * finish invalidating it and free the per-page flags.
3205 */
3206 i915_gem_object_set_to_full_cpu_read_domain(obj);
3207
3208 old_write_domain = obj->base.write_domain;
3209 old_read_domains = obj->base.read_domains;
3210
3211 /* Flush the CPU cache if it's still invalid. */
3212 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3213 i915_gem_clflush_object(obj);
3214
3215 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3216 }
3217
3218 /* It should now be out of any other write domains, and we can update
3219 * the domain values for our changes.
3220 */
3221 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3222
3223 /* If we're writing through the CPU, then the GPU read domains will
3224 * need to be invalidated at next use.
3225 */
3226 if (write) {
3227 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3228 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3229 }
3230
3231 trace_i915_gem_object_change_domain(obj,
3232 old_read_domains,
3233 old_write_domain);
3234
3235 return 0;
3236}
3237
3238/**
3239 * Moves the object from a partially CPU read to a full one.
3240 *
3241 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3242 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3243 */
3244static void
3245i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3246{
3247 if (!obj->page_cpu_valid)
3248 return;
3249
3250 /* If we're partially in the CPU read domain, finish moving it in.
3251 */
3252 if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3253 int i;
3254
3255 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3256 if (obj->page_cpu_valid[i])
3257 continue;
3258 drm_clflush_pages(obj->pages + i, 1);
3259 }
3260 }
3261
3262 /* Free the page_cpu_valid mappings which are now stale, whether
3263 * or not we've got I915_GEM_DOMAIN_CPU.
3264 */
3265 kfree(obj->page_cpu_valid);
3266 obj->page_cpu_valid = NULL;
3267}
3268
3269/**
3270 * Set the CPU read domain on a range of the object.
3271 *
3272 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3273 * not entirely valid. The page_cpu_valid member of the object flags which
3274 * pages have been flushed, and will be respected by
3275 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3276 * of the whole object.
3277 *
3278 * This function returns when the move is complete, including waiting on
3279 * flushes to occur.
3280 */
3281static int
3282i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3283 uint64_t offset, uint64_t size)
3284{
3285 uint32_t old_read_domains;
3286 int i, ret;
3287
3288 if (offset == 0 && size == obj->base.size)
3289 return i915_gem_object_set_to_cpu_domain(obj, 0);
3290
3291 ret = i915_gem_object_flush_gpu_write_domain(obj);
3292 if (ret)
3293 return ret;
3294
3295 ret = i915_gem_object_wait_rendering(obj);
3296 if (ret)
3297 return ret;
3298
3299 i915_gem_object_flush_gtt_write_domain(obj);
3300
3301 /* If we're already fully in the CPU read domain, we're done. */
3302 if (obj->page_cpu_valid == NULL &&
3303 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3304 return 0;
3305
3306 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3307 * newly adding I915_GEM_DOMAIN_CPU
3308 */
3309 if (obj->page_cpu_valid == NULL) {
3310 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3311 GFP_KERNEL);
3312 if (obj->page_cpu_valid == NULL)
3313 return -ENOMEM;
3314 } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3315 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3316
3317 /* Flush the cache on any pages that are still invalid from the CPU's
3318 * perspective.
3319 */
3320 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3321 i++) {
3322 if (obj->page_cpu_valid[i])
3323 continue;
3324
3325 drm_clflush_pages(obj->pages + i, 1);
3326
3327 obj->page_cpu_valid[i] = 1;
3328 }
3329
3330 /* It should now be out of any other write domains, and we can update
3331 * the domain values for our changes.
3332 */
3333 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3334
3335 old_read_domains = obj->base.read_domains;
3336 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3337
3338 trace_i915_gem_object_change_domain(obj,
3339 old_read_domains,
3340 obj->base.write_domain);
3341
3342 return 0;
3343}
3344
3345/* Throttle our rendering by waiting until the ring has completed our requests
3346 * emitted over 20 msec ago.
3347 *
3348 * Note that if we were to use the current jiffies each time around the loop,
3349 * we wouldn't escape the function with any frames outstanding if the time to
3350 * render a frame was over 20ms.
3351 *
3352 * This should get us reasonable parallelism between CPU and GPU but also
3353 * relatively low latency when blocking on a particular request to finish.
3354 */
3355static int
3356i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3357{
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 struct drm_i915_file_private *file_priv = file->driver_priv;
3360 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3361 struct drm_i915_gem_request *request;
3362 struct intel_ring_buffer *ring = NULL;
3363 u32 seqno = 0;
3364 int ret;
3365
3366 if (atomic_read(&dev_priv->mm.wedged))
3367 return -EIO;
3368
3369 spin_lock(&file_priv->mm.lock);
3370 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3371 if (time_after_eq(request->emitted_jiffies, recent_enough))
3372 break;
3373
3374 ring = request->ring;
3375 seqno = request->seqno;
3376 }
3377 spin_unlock(&file_priv->mm.lock);
3378
3379 if (seqno == 0)
3380 return 0;
3381
3382 ret = 0;
3383 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3384 /* And wait for the seqno passing without holding any locks and
3385 * causing extra latency for others. This is safe as the irq
3386 * generation is designed to be run atomically and so is
3387 * lockless.
3388 */
3389 if (ring->irq_get(ring)) {
3390 ret = wait_event_interruptible(ring->irq_queue,
3391 i915_seqno_passed(ring->get_seqno(ring), seqno)
3392 || atomic_read(&dev_priv->mm.wedged));
3393 ring->irq_put(ring);
3394
3395 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3396 ret = -EIO;
3397 }
3398 }
3399
3400 if (ret == 0)
3401 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3402
3403 return ret;
3404}
3405
3406int
3407i915_gem_object_pin(struct drm_i915_gem_object *obj,
3408 uint32_t alignment,
3409 bool map_and_fenceable)
3410{
3411 struct drm_device *dev = obj->base.dev;
3412 struct drm_i915_private *dev_priv = dev->dev_private;
3413 int ret;
3414
3415 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3416 WARN_ON(i915_verify_lists(dev));
3417
3418 if (obj->gtt_space != NULL) {
3419 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3420 (map_and_fenceable && !obj->map_and_fenceable)) {
3421 WARN(obj->pin_count,
3422 "bo is already pinned with incorrect alignment:"
3423 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3424 " obj->map_and_fenceable=%d\n",
3425 obj->gtt_offset, alignment,
3426 map_and_fenceable,
3427 obj->map_and_fenceable);
3428 ret = i915_gem_object_unbind(obj);
3429 if (ret)
3430 return ret;
3431 }
3432 }
3433
3434 if (obj->gtt_space == NULL) {
3435 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3436 map_and_fenceable);
3437 if (ret)
3438 return ret;
3439 }
3440
3441 if (obj->pin_count++ == 0) {
3442 if (!obj->active)
3443 list_move_tail(&obj->mm_list,
3444 &dev_priv->mm.pinned_list);
3445 }
3446 obj->pin_mappable |= map_and_fenceable;
3447
3448 WARN_ON(i915_verify_lists(dev));
3449 return 0;
3450}
3451
3452void
3453i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3454{
3455 struct drm_device *dev = obj->base.dev;
3456 drm_i915_private_t *dev_priv = dev->dev_private;
3457
3458 WARN_ON(i915_verify_lists(dev));
3459 BUG_ON(obj->pin_count == 0);
3460 BUG_ON(obj->gtt_space == NULL);
3461
3462 if (--obj->pin_count == 0) {
3463 if (!obj->active)
3464 list_move_tail(&obj->mm_list,
3465 &dev_priv->mm.inactive_list);
3466 obj->pin_mappable = false;
3467 }
3468 WARN_ON(i915_verify_lists(dev));
3469}
3470
3471int
3472i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3473 struct drm_file *file)
3474{
3475 struct drm_i915_gem_pin *args = data;
3476 struct drm_i915_gem_object *obj;
3477 int ret;
3478
3479 ret = i915_mutex_lock_interruptible(dev);
3480 if (ret)
3481 return ret;
3482
3483 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3484 if (&obj->base == NULL) {
3485 ret = -ENOENT;
3486 goto unlock;
3487 }
3488
3489 if (obj->madv != I915_MADV_WILLNEED) {
3490 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3491 ret = -EINVAL;
3492 goto out;
3493 }
3494
3495 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3496 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3497 args->handle);
3498 ret = -EINVAL;
3499 goto out;
3500 }
3501
3502 obj->user_pin_count++;
3503 obj->pin_filp = file;
3504 if (obj->user_pin_count == 1) {
3505 ret = i915_gem_object_pin(obj, args->alignment, true);
3506 if (ret)
3507 goto out;
3508 }
3509
3510 /* XXX - flush the CPU caches for pinned objects
3511 * as the X server doesn't manage domains yet
3512 */
3513 i915_gem_object_flush_cpu_write_domain(obj);
3514 args->offset = obj->gtt_offset;
3515out:
3516 drm_gem_object_unreference(&obj->base);
3517unlock:
3518 mutex_unlock(&dev->struct_mutex);
3519 return ret;
3520}
3521
3522int
3523i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3524 struct drm_file *file)
3525{
3526 struct drm_i915_gem_pin *args = data;
3527 struct drm_i915_gem_object *obj;
3528 int ret;
3529
3530 ret = i915_mutex_lock_interruptible(dev);
3531 if (ret)
3532 return ret;
3533
3534 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3535 if (&obj->base == NULL) {
3536 ret = -ENOENT;
3537 goto unlock;
3538 }
3539
3540 if (obj->pin_filp != file) {
3541 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3542 args->handle);
3543 ret = -EINVAL;
3544 goto out;
3545 }
3546 obj->user_pin_count--;
3547 if (obj->user_pin_count == 0) {
3548 obj->pin_filp = NULL;
3549 i915_gem_object_unpin(obj);
3550 }
3551
3552out:
3553 drm_gem_object_unreference(&obj->base);
3554unlock:
3555 mutex_unlock(&dev->struct_mutex);
3556 return ret;
3557}
3558
3559int
3560i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3561 struct drm_file *file)
3562{
3563 struct drm_i915_gem_busy *args = data;
3564 struct drm_i915_gem_object *obj;
3565 int ret;
3566
3567 ret = i915_mutex_lock_interruptible(dev);
3568 if (ret)
3569 return ret;
3570
3571 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3572 if (&obj->base == NULL) {
3573 ret = -ENOENT;
3574 goto unlock;
3575 }
3576
3577 /* Count all active objects as busy, even if they are currently not used
3578 * by the gpu. Users of this interface expect objects to eventually
3579 * become non-busy without any further actions, therefore emit any
3580 * necessary flushes here.
3581 */
3582 args->busy = obj->active;
3583 if (args->busy) {
3584 /* Unconditionally flush objects, even when the gpu still uses this
3585 * object. Userspace calling this function indicates that it wants to
3586 * use this buffer rather sooner than later, so issuing the required
3587 * flush earlier is beneficial.
3588 */
3589 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3590 ret = i915_gem_flush_ring(obj->ring,
3591 0, obj->base.write_domain);
3592 } else if (obj->ring->outstanding_lazy_request ==
3593 obj->last_rendering_seqno) {
3594 struct drm_i915_gem_request *request;
3595
3596 /* This ring is not being cleared by active usage,
3597 * so emit a request to do so.
3598 */
3599 request = kzalloc(sizeof(*request), GFP_KERNEL);
3600 if (request)
3601 ret = i915_add_request(obj->ring, NULL,request);
3602 else
3603 ret = -ENOMEM;
3604 }
3605
3606 /* Update the active list for the hardware's current position.
3607 * Otherwise this only updates on a delayed timer or when irqs
3608 * are actually unmasked, and our working set ends up being
3609 * larger than required.
3610 */
3611 i915_gem_retire_requests_ring(obj->ring);
3612
3613 args->busy = obj->active;
3614 }
3615
3616 drm_gem_object_unreference(&obj->base);
3617unlock:
3618 mutex_unlock(&dev->struct_mutex);
3619 return ret;
3620}
3621
3622int
3623i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3624 struct drm_file *file_priv)
3625{
3626 return i915_gem_ring_throttle(dev, file_priv);
3627}
3628
3629int
3630i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3631 struct drm_file *file_priv)
3632{
3633 struct drm_i915_gem_madvise *args = data;
3634 struct drm_i915_gem_object *obj;
3635 int ret;
3636
3637 switch (args->madv) {
3638 case I915_MADV_DONTNEED:
3639 case I915_MADV_WILLNEED:
3640 break;
3641 default:
3642 return -EINVAL;
3643 }
3644
3645 ret = i915_mutex_lock_interruptible(dev);
3646 if (ret)
3647 return ret;
3648
3649 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3650 if (&obj->base == NULL) {
3651 ret = -ENOENT;
3652 goto unlock;
3653 }
3654
3655 if (obj->pin_count) {
3656 ret = -EINVAL;
3657 goto out;
3658 }
3659
3660 if (obj->madv != __I915_MADV_PURGED)
3661 obj->madv = args->madv;
3662
3663 /* if the object is no longer bound, discard its backing storage */
3664 if (i915_gem_object_is_purgeable(obj) &&
3665 obj->gtt_space == NULL)
3666 i915_gem_object_truncate(obj);
3667
3668 args->retained = obj->madv != __I915_MADV_PURGED;
3669
3670out:
3671 drm_gem_object_unreference(&obj->base);
3672unlock:
3673 mutex_unlock(&dev->struct_mutex);
3674 return ret;
3675}
3676
3677struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3678 size_t size)
3679{
3680 struct drm_i915_private *dev_priv = dev->dev_private;
3681 struct drm_i915_gem_object *obj;
3682 struct address_space *mapping;
3683
3684 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3685 if (obj == NULL)
3686 return NULL;
3687
3688 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3689 kfree(obj);
3690 return NULL;
3691 }
3692
3693 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3694 mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
3695
3696 i915_gem_info_add_obj(dev_priv, size);
3697
3698 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3699 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3700
3701 if (IS_GEN6(dev)) {
3702 /* On Gen6, we can have the GPU use the LLC (the CPU
3703 * cache) for about a 10% performance improvement
3704 * compared to uncached. Graphics requests other than
3705 * display scanout are coherent with the CPU in
3706 * accessing this cache. This means in this mode we
3707 * don't need to clflush on the CPU side, and on the
3708 * GPU side we only need to flush internal caches to
3709 * get data visible to the CPU.
3710 *
3711 * However, we maintain the display planes as UC, and so
3712 * need to rebind when first used as such.
3713 */
3714 obj->cache_level = I915_CACHE_LLC;
3715 } else
3716 obj->cache_level = I915_CACHE_NONE;
3717
3718 obj->base.driver_private = NULL;
3719 obj->fence_reg = I915_FENCE_REG_NONE;
3720 INIT_LIST_HEAD(&obj->mm_list);
3721 INIT_LIST_HEAD(&obj->gtt_list);
3722 INIT_LIST_HEAD(&obj->ring_list);
3723 INIT_LIST_HEAD(&obj->exec_list);
3724 INIT_LIST_HEAD(&obj->gpu_write_list);
3725 obj->madv = I915_MADV_WILLNEED;
3726 /* Avoid an unnecessary call to unbind on the first bind. */
3727 obj->map_and_fenceable = true;
3728
3729 return obj;
3730}
3731
3732int i915_gem_init_object(struct drm_gem_object *obj)
3733{
3734 BUG();
3735
3736 return 0;
3737}
3738
3739static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3740{
3741 struct drm_device *dev = obj->base.dev;
3742 drm_i915_private_t *dev_priv = dev->dev_private;
3743 int ret;
3744
3745 ret = i915_gem_object_unbind(obj);
3746 if (ret == -ERESTARTSYS) {
3747 list_move(&obj->mm_list,
3748 &dev_priv->mm.deferred_free_list);
3749 return;
3750 }
3751
3752 trace_i915_gem_object_destroy(obj);
3753
3754 if (obj->base.map_list.map)
3755 i915_gem_free_mmap_offset(obj);
3756
3757 drm_gem_object_release(&obj->base);
3758 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3759
3760 kfree(obj->page_cpu_valid);
3761 kfree(obj->bit_17);
3762 kfree(obj);
3763}
3764
3765void i915_gem_free_object(struct drm_gem_object *gem_obj)
3766{
3767 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3768 struct drm_device *dev = obj->base.dev;
3769
3770 while (obj->pin_count > 0)
3771 i915_gem_object_unpin(obj);
3772
3773 if (obj->phys_obj)
3774 i915_gem_detach_phys_object(dev, obj);
3775
3776 i915_gem_free_object_tail(obj);
3777}
3778
3779int
3780i915_gem_idle(struct drm_device *dev)
3781{
3782 drm_i915_private_t *dev_priv = dev->dev_private;
3783 int ret;
3784
3785 mutex_lock(&dev->struct_mutex);
3786
3787 if (dev_priv->mm.suspended) {
3788 mutex_unlock(&dev->struct_mutex);
3789 return 0;
3790 }
3791
3792 ret = i915_gpu_idle(dev);
3793 if (ret) {
3794 mutex_unlock(&dev->struct_mutex);
3795 return ret;
3796 }
3797
3798 /* Under UMS, be paranoid and evict. */
3799 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3800 ret = i915_gem_evict_inactive(dev, false);
3801 if (ret) {
3802 mutex_unlock(&dev->struct_mutex);
3803 return ret;
3804 }
3805 }
3806
3807 i915_gem_reset_fences(dev);
3808
3809 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3810 * We need to replace this with a semaphore, or something.
3811 * And not confound mm.suspended!
3812 */
3813 dev_priv->mm.suspended = 1;
3814 del_timer_sync(&dev_priv->hangcheck_timer);
3815
3816 i915_kernel_lost_context(dev);
3817 i915_gem_cleanup_ringbuffer(dev);
3818
3819 mutex_unlock(&dev->struct_mutex);
3820
3821 /* Cancel the retire work handler, which should be idle now. */
3822 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3823
3824 return 0;
3825}
3826
3827int
3828i915_gem_init_ringbuffer(struct drm_device *dev)
3829{
3830 drm_i915_private_t *dev_priv = dev->dev_private;
3831 int ret;
3832
3833 ret = intel_init_render_ring_buffer(dev);
3834 if (ret)
3835 return ret;
3836
3837 if (HAS_BSD(dev)) {
3838 ret = intel_init_bsd_ring_buffer(dev);
3839 if (ret)
3840 goto cleanup_render_ring;
3841 }
3842
3843 if (HAS_BLT(dev)) {
3844 ret = intel_init_blt_ring_buffer(dev);
3845 if (ret)
3846 goto cleanup_bsd_ring;
3847 }
3848
3849 dev_priv->next_seqno = 1;
3850
3851 return 0;
3852
3853cleanup_bsd_ring:
3854 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3855cleanup_render_ring:
3856 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3857 return ret;
3858}
3859
3860void
3861i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3862{
3863 drm_i915_private_t *dev_priv = dev->dev_private;
3864 int i;
3865
3866 for (i = 0; i < I915_NUM_RINGS; i++)
3867 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3868}
3869
3870int
3871i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3872 struct drm_file *file_priv)
3873{
3874 drm_i915_private_t *dev_priv = dev->dev_private;
3875 int ret, i;
3876
3877 if (drm_core_check_feature(dev, DRIVER_MODESET))
3878 return 0;
3879
3880 if (atomic_read(&dev_priv->mm.wedged)) {
3881 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3882 atomic_set(&dev_priv->mm.wedged, 0);
3883 }
3884
3885 mutex_lock(&dev->struct_mutex);
3886 dev_priv->mm.suspended = 0;
3887
3888 ret = i915_gem_init_ringbuffer(dev);
3889 if (ret != 0) {
3890 mutex_unlock(&dev->struct_mutex);
3891 return ret;
3892 }
3893
3894 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3895 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3896 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3897 for (i = 0; i < I915_NUM_RINGS; i++) {
3898 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3899 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3900 }
3901 mutex_unlock(&dev->struct_mutex);
3902
3903 ret = drm_irq_install(dev);
3904 if (ret)
3905 goto cleanup_ringbuffer;
3906
3907 return 0;
3908
3909cleanup_ringbuffer:
3910 mutex_lock(&dev->struct_mutex);
3911 i915_gem_cleanup_ringbuffer(dev);
3912 dev_priv->mm.suspended = 1;
3913 mutex_unlock(&dev->struct_mutex);
3914
3915 return ret;
3916}
3917
3918int
3919i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3920 struct drm_file *file_priv)
3921{
3922 if (drm_core_check_feature(dev, DRIVER_MODESET))
3923 return 0;
3924
3925 drm_irq_uninstall(dev);
3926 return i915_gem_idle(dev);
3927}
3928
3929void
3930i915_gem_lastclose(struct drm_device *dev)
3931{
3932 int ret;
3933
3934 if (drm_core_check_feature(dev, DRIVER_MODESET))
3935 return;
3936
3937 ret = i915_gem_idle(dev);
3938 if (ret)
3939 DRM_ERROR("failed to idle hardware: %d\n", ret);
3940}
3941
3942static void
3943init_ring_lists(struct intel_ring_buffer *ring)
3944{
3945 INIT_LIST_HEAD(&ring->active_list);
3946 INIT_LIST_HEAD(&ring->request_list);
3947 INIT_LIST_HEAD(&ring->gpu_write_list);
3948}
3949
3950void
3951i915_gem_load(struct drm_device *dev)
3952{
3953 int i;
3954 drm_i915_private_t *dev_priv = dev->dev_private;
3955
3956 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3957 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3958 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3959 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3960 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3961 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3962 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3963 for (i = 0; i < I915_NUM_RINGS; i++)
3964 init_ring_lists(&dev_priv->ring[i]);
3965 for (i = 0; i < 16; i++)
3966 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3967 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3968 i915_gem_retire_work_handler);
3969 init_completion(&dev_priv->error_completion);
3970
3971 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3972 if (IS_GEN3(dev)) {
3973 u32 tmp = I915_READ(MI_ARB_STATE);
3974 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3975 /* arb state is a masked write, so set bit + bit in mask */
3976 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3977 I915_WRITE(MI_ARB_STATE, tmp);
3978 }
3979 }
3980
3981 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3982
3983 /* Old X drivers will take 0-2 for front, back, depth buffers */
3984 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3985 dev_priv->fence_reg_start = 3;
3986
3987 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3988 dev_priv->num_fence_regs = 16;
3989 else
3990 dev_priv->num_fence_regs = 8;
3991
3992 /* Initialize fence registers to zero */
3993 for (i = 0; i < dev_priv->num_fence_regs; i++) {
3994 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
3995 }
3996
3997 i915_gem_detect_bit_6_swizzle(dev);
3998 init_waitqueue_head(&dev_priv->pending_flip_queue);
3999
4000 dev_priv->mm.interruptible = true;
4001
4002 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4003 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4004 register_shrinker(&dev_priv->mm.inactive_shrinker);
4005}
4006
4007/*
4008 * Create a physically contiguous memory object for this object
4009 * e.g. for cursor + overlay regs
4010 */
4011static int i915_gem_init_phys_object(struct drm_device *dev,
4012 int id, int size, int align)
4013{
4014 drm_i915_private_t *dev_priv = dev->dev_private;
4015 struct drm_i915_gem_phys_object *phys_obj;
4016 int ret;
4017
4018 if (dev_priv->mm.phys_objs[id - 1] || !size)
4019 return 0;
4020
4021 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4022 if (!phys_obj)
4023 return -ENOMEM;
4024
4025 phys_obj->id = id;
4026
4027 phys_obj->handle = drm_pci_alloc(dev, size, align);
4028 if (!phys_obj->handle) {
4029 ret = -ENOMEM;
4030 goto kfree_obj;
4031 }
4032#ifdef CONFIG_X86
4033 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4034#endif
4035
4036 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4037
4038 return 0;
4039kfree_obj:
4040 kfree(phys_obj);
4041 return ret;
4042}
4043
4044static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4045{
4046 drm_i915_private_t *dev_priv = dev->dev_private;
4047 struct drm_i915_gem_phys_object *phys_obj;
4048
4049 if (!dev_priv->mm.phys_objs[id - 1])
4050 return;
4051
4052 phys_obj = dev_priv->mm.phys_objs[id - 1];
4053 if (phys_obj->cur_obj) {
4054 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4055 }
4056
4057#ifdef CONFIG_X86
4058 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4059#endif
4060 drm_pci_free(dev, phys_obj->handle);
4061 kfree(phys_obj);
4062 dev_priv->mm.phys_objs[id - 1] = NULL;
4063}
4064
4065void i915_gem_free_all_phys_object(struct drm_device *dev)
4066{
4067 int i;
4068
4069 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4070 i915_gem_free_phys_object(dev, i);
4071}
4072
4073void i915_gem_detach_phys_object(struct drm_device *dev,
4074 struct drm_i915_gem_object *obj)
4075{
4076 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4077 char *vaddr;
4078 int i;
4079 int page_count;
4080
4081 if (!obj->phys_obj)
4082 return;
4083 vaddr = obj->phys_obj->handle->vaddr;
4084
4085 page_count = obj->base.size / PAGE_SIZE;
4086 for (i = 0; i < page_count; i++) {
4087 struct page *page = shmem_read_mapping_page(mapping, i);
4088 if (!IS_ERR(page)) {
4089 char *dst = kmap_atomic(page);
4090 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4091 kunmap_atomic(dst);
4092
4093 drm_clflush_pages(&page, 1);
4094
4095 set_page_dirty(page);
4096 mark_page_accessed(page);
4097 page_cache_release(page);
4098 }
4099 }
4100 intel_gtt_chipset_flush();
4101
4102 obj->phys_obj->cur_obj = NULL;
4103 obj->phys_obj = NULL;
4104}
4105
4106int
4107i915_gem_attach_phys_object(struct drm_device *dev,
4108 struct drm_i915_gem_object *obj,
4109 int id,
4110 int align)
4111{
4112 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4113 drm_i915_private_t *dev_priv = dev->dev_private;
4114 int ret = 0;
4115 int page_count;
4116 int i;
4117
4118 if (id > I915_MAX_PHYS_OBJECT)
4119 return -EINVAL;
4120
4121 if (obj->phys_obj) {
4122 if (obj->phys_obj->id == id)
4123 return 0;
4124 i915_gem_detach_phys_object(dev, obj);
4125 }
4126
4127 /* create a new object */
4128 if (!dev_priv->mm.phys_objs[id - 1]) {
4129 ret = i915_gem_init_phys_object(dev, id,
4130 obj->base.size, align);
4131 if (ret) {
4132 DRM_ERROR("failed to init phys object %d size: %zu\n",
4133 id, obj->base.size);
4134 return ret;
4135 }
4136 }
4137
4138 /* bind to the object */
4139 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4140 obj->phys_obj->cur_obj = obj;
4141
4142 page_count = obj->base.size / PAGE_SIZE;
4143
4144 for (i = 0; i < page_count; i++) {
4145 struct page *page;
4146 char *dst, *src;
4147
4148 page = shmem_read_mapping_page(mapping, i);
4149 if (IS_ERR(page))
4150 return PTR_ERR(page);
4151
4152 src = kmap_atomic(page);
4153 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4154 memcpy(dst, src, PAGE_SIZE);
4155 kunmap_atomic(src);
4156
4157 mark_page_accessed(page);
4158 page_cache_release(page);
4159 }
4160
4161 return 0;
4162}
4163
4164static int
4165i915_gem_phys_pwrite(struct drm_device *dev,
4166 struct drm_i915_gem_object *obj,
4167 struct drm_i915_gem_pwrite *args,
4168 struct drm_file *file_priv)
4169{
4170 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4171 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4172
4173 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4174 unsigned long unwritten;
4175
4176 /* The physical object once assigned is fixed for the lifetime
4177 * of the obj, so we can safely drop the lock and continue
4178 * to access vaddr.
4179 */
4180 mutex_unlock(&dev->struct_mutex);
4181 unwritten = copy_from_user(vaddr, user_data, args->size);
4182 mutex_lock(&dev->struct_mutex);
4183 if (unwritten)
4184 return -EFAULT;
4185 }
4186
4187 intel_gtt_chipset_flush();
4188 return 0;
4189}
4190
4191void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4192{
4193 struct drm_i915_file_private *file_priv = file->driver_priv;
4194
4195 /* Clean up our request list when the client is going away, so that
4196 * later retire_requests won't dereference our soon-to-be-gone
4197 * file_priv.
4198 */
4199 spin_lock(&file_priv->mm.lock);
4200 while (!list_empty(&file_priv->mm.request_list)) {
4201 struct drm_i915_gem_request *request;
4202
4203 request = list_first_entry(&file_priv->mm.request_list,
4204 struct drm_i915_gem_request,
4205 client_list);
4206 list_del(&request->client_list);
4207 request->file_priv = NULL;
4208 }
4209 spin_unlock(&file_priv->mm.lock);
4210}
4211
4212static int
4213i915_gpu_is_active(struct drm_device *dev)
4214{
4215 drm_i915_private_t *dev_priv = dev->dev_private;
4216 int lists_empty;
4217
4218 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4219 list_empty(&dev_priv->mm.active_list);
4220
4221 return !lists_empty;
4222}
4223
4224static int
4225i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4226{
4227 struct drm_i915_private *dev_priv =
4228 container_of(shrinker,
4229 struct drm_i915_private,
4230 mm.inactive_shrinker);
4231 struct drm_device *dev = dev_priv->dev;
4232 struct drm_i915_gem_object *obj, *next;
4233 int nr_to_scan = sc->nr_to_scan;
4234 int cnt;
4235
4236 if (!mutex_trylock(&dev->struct_mutex))
4237 return 0;
4238
4239 /* "fast-path" to count number of available objects */
4240 if (nr_to_scan == 0) {
4241 cnt = 0;
4242 list_for_each_entry(obj,
4243 &dev_priv->mm.inactive_list,
4244 mm_list)
4245 cnt++;
4246 mutex_unlock(&dev->struct_mutex);
4247 return cnt / 100 * sysctl_vfs_cache_pressure;
4248 }
4249
4250rescan:
4251 /* first scan for clean buffers */
4252 i915_gem_retire_requests(dev);
4253
4254 list_for_each_entry_safe(obj, next,
4255 &dev_priv->mm.inactive_list,
4256 mm_list) {
4257 if (i915_gem_object_is_purgeable(obj)) {
4258 if (i915_gem_object_unbind(obj) == 0 &&
4259 --nr_to_scan == 0)
4260 break;
4261 }
4262 }
4263
4264 /* second pass, evict/count anything still on the inactive list */
4265 cnt = 0;
4266 list_for_each_entry_safe(obj, next,
4267 &dev_priv->mm.inactive_list,
4268 mm_list) {
4269 if (nr_to_scan &&
4270 i915_gem_object_unbind(obj) == 0)
4271 nr_to_scan--;
4272 else
4273 cnt++;
4274 }
4275
4276 if (nr_to_scan && i915_gpu_is_active(dev)) {
4277 /*
4278 * We are desperate for pages, so as a last resort, wait
4279 * for the GPU to finish and discard whatever we can.
4280 * This has a dramatic impact to reduce the number of
4281 * OOM-killer events whilst running the GPU aggressively.
4282 */
4283 if (i915_gpu_idle(dev) == 0)
4284 goto rescan;
4285 }
4286 mutex_unlock(&dev->struct_mutex);
4287 return cnt / 100 * sysctl_vfs_cache_pressure;
4288}
1/*
2 * Copyright © 2008-2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include <drm/drmP.h>
29#include <drm/drm_vma_manager.h>
30#include <drm/i915_drm.h>
31#include "i915_drv.h"
32#include "i915_vgpu.h"
33#include "i915_trace.h"
34#include "intel_drv.h"
35#include "intel_frontbuffer.h"
36#include "intel_mocs.h"
37#include <linux/dma-fence-array.h>
38#include <linux/reservation.h>
39#include <linux/shmem_fs.h>
40#include <linux/slab.h>
41#include <linux/swap.h>
42#include <linux/pci.h>
43#include <linux/dma-buf.h>
44
45static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
46static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
47static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
48
49static bool cpu_cache_is_coherent(struct drm_device *dev,
50 enum i915_cache_level level)
51{
52 return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;
53}
54
55static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
56{
57 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
58 return false;
59
60 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
61 return true;
62
63 return obj->pin_display;
64}
65
66static int
67insert_mappable_node(struct i915_ggtt *ggtt,
68 struct drm_mm_node *node, u32 size)
69{
70 memset(node, 0, sizeof(*node));
71 return drm_mm_insert_node_in_range_generic(&ggtt->base.mm, node,
72 size, 0, -1,
73 0, ggtt->mappable_end,
74 DRM_MM_SEARCH_DEFAULT,
75 DRM_MM_CREATE_DEFAULT);
76}
77
78static void
79remove_mappable_node(struct drm_mm_node *node)
80{
81 drm_mm_remove_node(node);
82}
83
84/* some bookkeeping */
85static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
86 u64 size)
87{
88 spin_lock(&dev_priv->mm.object_stat_lock);
89 dev_priv->mm.object_count++;
90 dev_priv->mm.object_memory += size;
91 spin_unlock(&dev_priv->mm.object_stat_lock);
92}
93
94static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
95 u64 size)
96{
97 spin_lock(&dev_priv->mm.object_stat_lock);
98 dev_priv->mm.object_count--;
99 dev_priv->mm.object_memory -= size;
100 spin_unlock(&dev_priv->mm.object_stat_lock);
101}
102
103static int
104i915_gem_wait_for_error(struct i915_gpu_error *error)
105{
106 int ret;
107
108 might_sleep();
109
110 if (!i915_reset_in_progress(error))
111 return 0;
112
113 /*
114 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
115 * userspace. If it takes that long something really bad is going on and
116 * we should simply try to bail out and fail as gracefully as possible.
117 */
118 ret = wait_event_interruptible_timeout(error->reset_queue,
119 !i915_reset_in_progress(error),
120 I915_RESET_TIMEOUT);
121 if (ret == 0) {
122 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
123 return -EIO;
124 } else if (ret < 0) {
125 return ret;
126 } else {
127 return 0;
128 }
129}
130
131int i915_mutex_lock_interruptible(struct drm_device *dev)
132{
133 struct drm_i915_private *dev_priv = to_i915(dev);
134 int ret;
135
136 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
137 if (ret)
138 return ret;
139
140 ret = mutex_lock_interruptible(&dev->struct_mutex);
141 if (ret)
142 return ret;
143
144 return 0;
145}
146
147int
148i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
149 struct drm_file *file)
150{
151 struct drm_i915_private *dev_priv = to_i915(dev);
152 struct i915_ggtt *ggtt = &dev_priv->ggtt;
153 struct drm_i915_gem_get_aperture *args = data;
154 struct i915_vma *vma;
155 size_t pinned;
156
157 pinned = 0;
158 mutex_lock(&dev->struct_mutex);
159 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
160 if (i915_vma_is_pinned(vma))
161 pinned += vma->node.size;
162 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
163 if (i915_vma_is_pinned(vma))
164 pinned += vma->node.size;
165 mutex_unlock(&dev->struct_mutex);
166
167 args->aper_size = ggtt->base.total;
168 args->aper_available_size = args->aper_size - pinned;
169
170 return 0;
171}
172
173static struct sg_table *
174i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
175{
176 struct address_space *mapping = obj->base.filp->f_mapping;
177 drm_dma_handle_t *phys;
178 struct sg_table *st;
179 struct scatterlist *sg;
180 char *vaddr;
181 int i;
182
183 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
184 return ERR_PTR(-EINVAL);
185
186 /* Always aligning to the object size, allows a single allocation
187 * to handle all possible callers, and given typical object sizes,
188 * the alignment of the buddy allocation will naturally match.
189 */
190 phys = drm_pci_alloc(obj->base.dev,
191 obj->base.size,
192 roundup_pow_of_two(obj->base.size));
193 if (!phys)
194 return ERR_PTR(-ENOMEM);
195
196 vaddr = phys->vaddr;
197 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
198 struct page *page;
199 char *src;
200
201 page = shmem_read_mapping_page(mapping, i);
202 if (IS_ERR(page)) {
203 st = ERR_CAST(page);
204 goto err_phys;
205 }
206
207 src = kmap_atomic(page);
208 memcpy(vaddr, src, PAGE_SIZE);
209 drm_clflush_virt_range(vaddr, PAGE_SIZE);
210 kunmap_atomic(src);
211
212 put_page(page);
213 vaddr += PAGE_SIZE;
214 }
215
216 i915_gem_chipset_flush(to_i915(obj->base.dev));
217
218 st = kmalloc(sizeof(*st), GFP_KERNEL);
219 if (!st) {
220 st = ERR_PTR(-ENOMEM);
221 goto err_phys;
222 }
223
224 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
225 kfree(st);
226 st = ERR_PTR(-ENOMEM);
227 goto err_phys;
228 }
229
230 sg = st->sgl;
231 sg->offset = 0;
232 sg->length = obj->base.size;
233
234 sg_dma_address(sg) = phys->busaddr;
235 sg_dma_len(sg) = obj->base.size;
236
237 obj->phys_handle = phys;
238 return st;
239
240err_phys:
241 drm_pci_free(obj->base.dev, phys);
242 return st;
243}
244
245static void
246__i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
247 struct sg_table *pages,
248 bool needs_clflush)
249{
250 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
251
252 if (obj->mm.madv == I915_MADV_DONTNEED)
253 obj->mm.dirty = false;
254
255 if (needs_clflush &&
256 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
257 !cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
258 drm_clflush_sg(pages);
259
260 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
261 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
262}
263
264static void
265i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
266 struct sg_table *pages)
267{
268 __i915_gem_object_release_shmem(obj, pages, false);
269
270 if (obj->mm.dirty) {
271 struct address_space *mapping = obj->base.filp->f_mapping;
272 char *vaddr = obj->phys_handle->vaddr;
273 int i;
274
275 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
276 struct page *page;
277 char *dst;
278
279 page = shmem_read_mapping_page(mapping, i);
280 if (IS_ERR(page))
281 continue;
282
283 dst = kmap_atomic(page);
284 drm_clflush_virt_range(vaddr, PAGE_SIZE);
285 memcpy(dst, vaddr, PAGE_SIZE);
286 kunmap_atomic(dst);
287
288 set_page_dirty(page);
289 if (obj->mm.madv == I915_MADV_WILLNEED)
290 mark_page_accessed(page);
291 put_page(page);
292 vaddr += PAGE_SIZE;
293 }
294 obj->mm.dirty = false;
295 }
296
297 sg_free_table(pages);
298 kfree(pages);
299
300 drm_pci_free(obj->base.dev, obj->phys_handle);
301}
302
303static void
304i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
305{
306 i915_gem_object_unpin_pages(obj);
307}
308
309static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
310 .get_pages = i915_gem_object_get_pages_phys,
311 .put_pages = i915_gem_object_put_pages_phys,
312 .release = i915_gem_object_release_phys,
313};
314
315int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
316{
317 struct i915_vma *vma;
318 LIST_HEAD(still_in_list);
319 int ret;
320
321 lockdep_assert_held(&obj->base.dev->struct_mutex);
322
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
327 */
328 ret = i915_gem_object_wait(obj,
329 I915_WAIT_INTERRUPTIBLE |
330 I915_WAIT_LOCKED |
331 I915_WAIT_ALL,
332 MAX_SCHEDULE_TIMEOUT,
333 NULL);
334 if (ret)
335 return ret;
336
337 i915_gem_retire_requests(to_i915(obj->base.dev));
338
339 while ((vma = list_first_entry_or_null(&obj->vma_list,
340 struct i915_vma,
341 obj_link))) {
342 list_move_tail(&vma->obj_link, &still_in_list);
343 ret = i915_vma_unbind(vma);
344 if (ret)
345 break;
346 }
347 list_splice(&still_in_list, &obj->vma_list);
348
349 return ret;
350}
351
352static long
353i915_gem_object_wait_fence(struct dma_fence *fence,
354 unsigned int flags,
355 long timeout,
356 struct intel_rps_client *rps)
357{
358 struct drm_i915_gem_request *rq;
359
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
361
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
363 return timeout;
364
365 if (!dma_fence_is_i915(fence))
366 return dma_fence_wait_timeout(fence,
367 flags & I915_WAIT_INTERRUPTIBLE,
368 timeout);
369
370 rq = to_request(fence);
371 if (i915_gem_request_completed(rq))
372 goto out;
373
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
388 */
389 if (rps) {
390 if (INTEL_GEN(rq->i915) >= 6)
391 gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
392 else
393 rps = NULL;
394 }
395
396 timeout = i915_wait_request(rq, flags, timeout);
397
398out:
399 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
400 i915_gem_request_retire_upto(rq);
401
402 if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) {
403 /* The GPU is now idle and this client has stalled.
404 * Since no other client has submitted a request in the
405 * meantime, assume that this client is the only one
406 * supplying work to the GPU but is unable to keep that
407 * work supplied because it is waiting. Since the GPU is
408 * then never kept fully busy, RPS autoclocking will
409 * keep the clocks relatively low, causing further delays.
410 * Compensate by giving the synchronous client credit for
411 * a waitboost next time.
412 */
413 spin_lock(&rq->i915->rps.client_lock);
414 list_del_init(&rps->link);
415 spin_unlock(&rq->i915->rps.client_lock);
416 }
417
418 return timeout;
419}
420
421static long
422i915_gem_object_wait_reservation(struct reservation_object *resv,
423 unsigned int flags,
424 long timeout,
425 struct intel_rps_client *rps)
426{
427 struct dma_fence *excl;
428
429 if (flags & I915_WAIT_ALL) {
430 struct dma_fence **shared;
431 unsigned int count, i;
432 int ret;
433
434 ret = reservation_object_get_fences_rcu(resv,
435 &excl, &count, &shared);
436 if (ret)
437 return ret;
438
439 for (i = 0; i < count; i++) {
440 timeout = i915_gem_object_wait_fence(shared[i],
441 flags, timeout,
442 rps);
443 if (timeout < 0)
444 break;
445
446 dma_fence_put(shared[i]);
447 }
448
449 for (; i < count; i++)
450 dma_fence_put(shared[i]);
451 kfree(shared);
452 } else {
453 excl = reservation_object_get_excl_rcu(resv);
454 }
455
456 if (excl && timeout >= 0)
457 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
458
459 dma_fence_put(excl);
460
461 return timeout;
462}
463
464static void __fence_set_priority(struct dma_fence *fence, int prio)
465{
466 struct drm_i915_gem_request *rq;
467 struct intel_engine_cs *engine;
468
469 if (!dma_fence_is_i915(fence))
470 return;
471
472 rq = to_request(fence);
473 engine = rq->engine;
474 if (!engine->schedule)
475 return;
476
477 engine->schedule(rq, prio);
478}
479
480static void fence_set_priority(struct dma_fence *fence, int prio)
481{
482 /* Recurse once into a fence-array */
483 if (dma_fence_is_array(fence)) {
484 struct dma_fence_array *array = to_dma_fence_array(fence);
485 int i;
486
487 for (i = 0; i < array->num_fences; i++)
488 __fence_set_priority(array->fences[i], prio);
489 } else {
490 __fence_set_priority(fence, prio);
491 }
492}
493
494int
495i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
496 unsigned int flags,
497 int prio)
498{
499 struct dma_fence *excl;
500
501 if (flags & I915_WAIT_ALL) {
502 struct dma_fence **shared;
503 unsigned int count, i;
504 int ret;
505
506 ret = reservation_object_get_fences_rcu(obj->resv,
507 &excl, &count, &shared);
508 if (ret)
509 return ret;
510
511 for (i = 0; i < count; i++) {
512 fence_set_priority(shared[i], prio);
513 dma_fence_put(shared[i]);
514 }
515
516 kfree(shared);
517 } else {
518 excl = reservation_object_get_excl_rcu(obj->resv);
519 }
520
521 if (excl) {
522 fence_set_priority(excl, prio);
523 dma_fence_put(excl);
524 }
525 return 0;
526}
527
528/**
529 * Waits for rendering to the object to be completed
530 * @obj: i915 gem object
531 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
532 * @timeout: how long to wait
533 * @rps: client (user process) to charge for any waitboosting
534 */
535int
536i915_gem_object_wait(struct drm_i915_gem_object *obj,
537 unsigned int flags,
538 long timeout,
539 struct intel_rps_client *rps)
540{
541 might_sleep();
542#if IS_ENABLED(CONFIG_LOCKDEP)
543 GEM_BUG_ON(debug_locks &&
544 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
545 !!(flags & I915_WAIT_LOCKED));
546#endif
547 GEM_BUG_ON(timeout < 0);
548
549 timeout = i915_gem_object_wait_reservation(obj->resv,
550 flags, timeout,
551 rps);
552 return timeout < 0 ? timeout : 0;
553}
554
555static struct intel_rps_client *to_rps_client(struct drm_file *file)
556{
557 struct drm_i915_file_private *fpriv = file->driver_priv;
558
559 return &fpriv->rps;
560}
561
562int
563i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
564 int align)
565{
566 int ret;
567
568 if (align > obj->base.size)
569 return -EINVAL;
570
571 if (obj->ops == &i915_gem_phys_ops)
572 return 0;
573
574 if (obj->mm.madv != I915_MADV_WILLNEED)
575 return -EFAULT;
576
577 if (obj->base.filp == NULL)
578 return -EINVAL;
579
580 ret = i915_gem_object_unbind(obj);
581 if (ret)
582 return ret;
583
584 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
585 if (obj->mm.pages)
586 return -EBUSY;
587
588 obj->ops = &i915_gem_phys_ops;
589
590 return i915_gem_object_pin_pages(obj);
591}
592
593static int
594i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
595 struct drm_i915_gem_pwrite *args,
596 struct drm_file *file)
597{
598 void *vaddr = obj->phys_handle->vaddr + args->offset;
599 char __user *user_data = u64_to_user_ptr(args->data_ptr);
600
601 /* We manually control the domain here and pretend that it
602 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
603 */
604 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
605 if (copy_from_user(vaddr, user_data, args->size))
606 return -EFAULT;
607
608 drm_clflush_virt_range(vaddr, args->size);
609 i915_gem_chipset_flush(to_i915(obj->base.dev));
610
611 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
612 return 0;
613}
614
615void *i915_gem_object_alloc(struct drm_device *dev)
616{
617 struct drm_i915_private *dev_priv = to_i915(dev);
618 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
619}
620
621void i915_gem_object_free(struct drm_i915_gem_object *obj)
622{
623 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
624 kmem_cache_free(dev_priv->objects, obj);
625}
626
627static int
628i915_gem_create(struct drm_file *file,
629 struct drm_device *dev,
630 uint64_t size,
631 uint32_t *handle_p)
632{
633 struct drm_i915_gem_object *obj;
634 int ret;
635 u32 handle;
636
637 size = roundup(size, PAGE_SIZE);
638 if (size == 0)
639 return -EINVAL;
640
641 /* Allocate the new object */
642 obj = i915_gem_object_create(dev, size);
643 if (IS_ERR(obj))
644 return PTR_ERR(obj);
645
646 ret = drm_gem_handle_create(file, &obj->base, &handle);
647 /* drop reference from allocate - handle holds it now */
648 i915_gem_object_put(obj);
649 if (ret)
650 return ret;
651
652 *handle_p = handle;
653 return 0;
654}
655
656int
657i915_gem_dumb_create(struct drm_file *file,
658 struct drm_device *dev,
659 struct drm_mode_create_dumb *args)
660{
661 /* have to work out size/pitch and return them */
662 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
663 args->size = args->pitch * args->height;
664 return i915_gem_create(file, dev,
665 args->size, &args->handle);
666}
667
668/**
669 * Creates a new mm object and returns a handle to it.
670 * @dev: drm device pointer
671 * @data: ioctl data blob
672 * @file: drm file pointer
673 */
674int
675i915_gem_create_ioctl(struct drm_device *dev, void *data,
676 struct drm_file *file)
677{
678 struct drm_i915_gem_create *args = data;
679
680 i915_gem_flush_free_objects(to_i915(dev));
681
682 return i915_gem_create(file, dev,
683 args->size, &args->handle);
684}
685
686static inline int
687__copy_to_user_swizzled(char __user *cpu_vaddr,
688 const char *gpu_vaddr, int gpu_offset,
689 int length)
690{
691 int ret, cpu_offset = 0;
692
693 while (length > 0) {
694 int cacheline_end = ALIGN(gpu_offset + 1, 64);
695 int this_length = min(cacheline_end - gpu_offset, length);
696 int swizzled_gpu_offset = gpu_offset ^ 64;
697
698 ret = __copy_to_user(cpu_vaddr + cpu_offset,
699 gpu_vaddr + swizzled_gpu_offset,
700 this_length);
701 if (ret)
702 return ret + length;
703
704 cpu_offset += this_length;
705 gpu_offset += this_length;
706 length -= this_length;
707 }
708
709 return 0;
710}
711
712static inline int
713__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
714 const char __user *cpu_vaddr,
715 int length)
716{
717 int ret, cpu_offset = 0;
718
719 while (length > 0) {
720 int cacheline_end = ALIGN(gpu_offset + 1, 64);
721 int this_length = min(cacheline_end - gpu_offset, length);
722 int swizzled_gpu_offset = gpu_offset ^ 64;
723
724 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
725 cpu_vaddr + cpu_offset,
726 this_length);
727 if (ret)
728 return ret + length;
729
730 cpu_offset += this_length;
731 gpu_offset += this_length;
732 length -= this_length;
733 }
734
735 return 0;
736}
737
738/*
739 * Pins the specified object's pages and synchronizes the object with
740 * GPU accesses. Sets needs_clflush to non-zero if the caller should
741 * flush the object from the CPU cache.
742 */
743int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
744 unsigned int *needs_clflush)
745{
746 int ret;
747
748 lockdep_assert_held(&obj->base.dev->struct_mutex);
749
750 *needs_clflush = 0;
751 if (!i915_gem_object_has_struct_page(obj))
752 return -ENODEV;
753
754 ret = i915_gem_object_wait(obj,
755 I915_WAIT_INTERRUPTIBLE |
756 I915_WAIT_LOCKED,
757 MAX_SCHEDULE_TIMEOUT,
758 NULL);
759 if (ret)
760 return ret;
761
762 ret = i915_gem_object_pin_pages(obj);
763 if (ret)
764 return ret;
765
766 i915_gem_object_flush_gtt_write_domain(obj);
767
768 /* If we're not in the cpu read domain, set ourself into the gtt
769 * read domain and manually flush cachelines (if required). This
770 * optimizes for the case when the gpu will dirty the data
771 * anyway again before the next pread happens.
772 */
773 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
774 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
775 obj->cache_level);
776
777 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
778 ret = i915_gem_object_set_to_cpu_domain(obj, false);
779 if (ret)
780 goto err_unpin;
781
782 *needs_clflush = 0;
783 }
784
785 /* return with the pages pinned */
786 return 0;
787
788err_unpin:
789 i915_gem_object_unpin_pages(obj);
790 return ret;
791}
792
793int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
794 unsigned int *needs_clflush)
795{
796 int ret;
797
798 lockdep_assert_held(&obj->base.dev->struct_mutex);
799
800 *needs_clflush = 0;
801 if (!i915_gem_object_has_struct_page(obj))
802 return -ENODEV;
803
804 ret = i915_gem_object_wait(obj,
805 I915_WAIT_INTERRUPTIBLE |
806 I915_WAIT_LOCKED |
807 I915_WAIT_ALL,
808 MAX_SCHEDULE_TIMEOUT,
809 NULL);
810 if (ret)
811 return ret;
812
813 ret = i915_gem_object_pin_pages(obj);
814 if (ret)
815 return ret;
816
817 i915_gem_object_flush_gtt_write_domain(obj);
818
819 /* If we're not in the cpu write domain, set ourself into the
820 * gtt write domain and manually flush cachelines (as required).
821 * This optimizes for the case when the gpu will use the data
822 * right away and we therefore have to clflush anyway.
823 */
824 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
825 *needs_clflush |= cpu_write_needs_clflush(obj) << 1;
826
827 /* Same trick applies to invalidate partially written cachelines read
828 * before writing.
829 */
830 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
831 *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev,
832 obj->cache_level);
833
834 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
835 ret = i915_gem_object_set_to_cpu_domain(obj, true);
836 if (ret)
837 goto err_unpin;
838
839 *needs_clflush = 0;
840 }
841
842 if ((*needs_clflush & CLFLUSH_AFTER) == 0)
843 obj->cache_dirty = true;
844
845 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
846 obj->mm.dirty = true;
847 /* return with the pages pinned */
848 return 0;
849
850err_unpin:
851 i915_gem_object_unpin_pages(obj);
852 return ret;
853}
854
855static void
856shmem_clflush_swizzled_range(char *addr, unsigned long length,
857 bool swizzled)
858{
859 if (unlikely(swizzled)) {
860 unsigned long start = (unsigned long) addr;
861 unsigned long end = (unsigned long) addr + length;
862
863 /* For swizzling simply ensure that we always flush both
864 * channels. Lame, but simple and it works. Swizzled
865 * pwrite/pread is far from a hotpath - current userspace
866 * doesn't use it at all. */
867 start = round_down(start, 128);
868 end = round_up(end, 128);
869
870 drm_clflush_virt_range((void *)start, end - start);
871 } else {
872 drm_clflush_virt_range(addr, length);
873 }
874
875}
876
877/* Only difference to the fast-path function is that this can handle bit17
878 * and uses non-atomic copy and kmap functions. */
879static int
880shmem_pread_slow(struct page *page, int offset, int length,
881 char __user *user_data,
882 bool page_do_bit17_swizzling, bool needs_clflush)
883{
884 char *vaddr;
885 int ret;
886
887 vaddr = kmap(page);
888 if (needs_clflush)
889 shmem_clflush_swizzled_range(vaddr + offset, length,
890 page_do_bit17_swizzling);
891
892 if (page_do_bit17_swizzling)
893 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
894 else
895 ret = __copy_to_user(user_data, vaddr + offset, length);
896 kunmap(page);
897
898 return ret ? - EFAULT : 0;
899}
900
901static int
902shmem_pread(struct page *page, int offset, int length, char __user *user_data,
903 bool page_do_bit17_swizzling, bool needs_clflush)
904{
905 int ret;
906
907 ret = -ENODEV;
908 if (!page_do_bit17_swizzling) {
909 char *vaddr = kmap_atomic(page);
910
911 if (needs_clflush)
912 drm_clflush_virt_range(vaddr + offset, length);
913 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
914 kunmap_atomic(vaddr);
915 }
916 if (ret == 0)
917 return 0;
918
919 return shmem_pread_slow(page, offset, length, user_data,
920 page_do_bit17_swizzling, needs_clflush);
921}
922
923static int
924i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
925 struct drm_i915_gem_pread *args)
926{
927 char __user *user_data;
928 u64 remain;
929 unsigned int obj_do_bit17_swizzling;
930 unsigned int needs_clflush;
931 unsigned int idx, offset;
932 int ret;
933
934 obj_do_bit17_swizzling = 0;
935 if (i915_gem_object_needs_bit17_swizzle(obj))
936 obj_do_bit17_swizzling = BIT(17);
937
938 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
939 if (ret)
940 return ret;
941
942 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
943 mutex_unlock(&obj->base.dev->struct_mutex);
944 if (ret)
945 return ret;
946
947 remain = args->size;
948 user_data = u64_to_user_ptr(args->data_ptr);
949 offset = offset_in_page(args->offset);
950 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
951 struct page *page = i915_gem_object_get_page(obj, idx);
952 int length;
953
954 length = remain;
955 if (offset + length > PAGE_SIZE)
956 length = PAGE_SIZE - offset;
957
958 ret = shmem_pread(page, offset, length, user_data,
959 page_to_phys(page) & obj_do_bit17_swizzling,
960 needs_clflush);
961 if (ret)
962 break;
963
964 remain -= length;
965 user_data += length;
966 offset = 0;
967 }
968
969 i915_gem_obj_finish_shmem_access(obj);
970 return ret;
971}
972
973static inline bool
974gtt_user_read(struct io_mapping *mapping,
975 loff_t base, int offset,
976 char __user *user_data, int length)
977{
978 void *vaddr;
979 unsigned long unwritten;
980
981 /* We can use the cpu mem copy function because this is X86. */
982 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
983 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
984 io_mapping_unmap_atomic(vaddr);
985 if (unwritten) {
986 vaddr = (void __force *)
987 io_mapping_map_wc(mapping, base, PAGE_SIZE);
988 unwritten = copy_to_user(user_data, vaddr + offset, length);
989 io_mapping_unmap(vaddr);
990 }
991 return unwritten;
992}
993
994static int
995i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
996 const struct drm_i915_gem_pread *args)
997{
998 struct drm_i915_private *i915 = to_i915(obj->base.dev);
999 struct i915_ggtt *ggtt = &i915->ggtt;
1000 struct drm_mm_node node;
1001 struct i915_vma *vma;
1002 void __user *user_data;
1003 u64 remain, offset;
1004 int ret;
1005
1006 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1007 if (ret)
1008 return ret;
1009
1010 intel_runtime_pm_get(i915);
1011 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1012 PIN_MAPPABLE | PIN_NONBLOCK);
1013 if (!IS_ERR(vma)) {
1014 node.start = i915_ggtt_offset(vma);
1015 node.allocated = false;
1016 ret = i915_vma_put_fence(vma);
1017 if (ret) {
1018 i915_vma_unpin(vma);
1019 vma = ERR_PTR(ret);
1020 }
1021 }
1022 if (IS_ERR(vma)) {
1023 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1024 if (ret)
1025 goto out_unlock;
1026 GEM_BUG_ON(!node.allocated);
1027 }
1028
1029 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1030 if (ret)
1031 goto out_unpin;
1032
1033 mutex_unlock(&i915->drm.struct_mutex);
1034
1035 user_data = u64_to_user_ptr(args->data_ptr);
1036 remain = args->size;
1037 offset = args->offset;
1038
1039 while (remain > 0) {
1040 /* Operation in this page
1041 *
1042 * page_base = page offset within aperture
1043 * page_offset = offset within page
1044 * page_length = bytes to copy for this page
1045 */
1046 u32 page_base = node.start;
1047 unsigned page_offset = offset_in_page(offset);
1048 unsigned page_length = PAGE_SIZE - page_offset;
1049 page_length = remain < page_length ? remain : page_length;
1050 if (node.allocated) {
1051 wmb();
1052 ggtt->base.insert_page(&ggtt->base,
1053 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1054 node.start, I915_CACHE_NONE, 0);
1055 wmb();
1056 } else {
1057 page_base += offset & PAGE_MASK;
1058 }
1059
1060 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1061 user_data, page_length)) {
1062 ret = -EFAULT;
1063 break;
1064 }
1065
1066 remain -= page_length;
1067 user_data += page_length;
1068 offset += page_length;
1069 }
1070
1071 mutex_lock(&i915->drm.struct_mutex);
1072out_unpin:
1073 if (node.allocated) {
1074 wmb();
1075 ggtt->base.clear_range(&ggtt->base,
1076 node.start, node.size);
1077 remove_mappable_node(&node);
1078 } else {
1079 i915_vma_unpin(vma);
1080 }
1081out_unlock:
1082 intel_runtime_pm_put(i915);
1083 mutex_unlock(&i915->drm.struct_mutex);
1084
1085 return ret;
1086}
1087
1088/**
1089 * Reads data from the object referenced by handle.
1090 * @dev: drm device pointer
1091 * @data: ioctl data blob
1092 * @file: drm file pointer
1093 *
1094 * On error, the contents of *data are undefined.
1095 */
1096int
1097i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1098 struct drm_file *file)
1099{
1100 struct drm_i915_gem_pread *args = data;
1101 struct drm_i915_gem_object *obj;
1102 int ret;
1103
1104 if (args->size == 0)
1105 return 0;
1106
1107 if (!access_ok(VERIFY_WRITE,
1108 u64_to_user_ptr(args->data_ptr),
1109 args->size))
1110 return -EFAULT;
1111
1112 obj = i915_gem_object_lookup(file, args->handle);
1113 if (!obj)
1114 return -ENOENT;
1115
1116 /* Bounds check source. */
1117 if (args->offset > obj->base.size ||
1118 args->size > obj->base.size - args->offset) {
1119 ret = -EINVAL;
1120 goto out;
1121 }
1122
1123 trace_i915_gem_object_pread(obj, args->offset, args->size);
1124
1125 ret = i915_gem_object_wait(obj,
1126 I915_WAIT_INTERRUPTIBLE,
1127 MAX_SCHEDULE_TIMEOUT,
1128 to_rps_client(file));
1129 if (ret)
1130 goto out;
1131
1132 ret = i915_gem_object_pin_pages(obj);
1133 if (ret)
1134 goto out;
1135
1136 ret = i915_gem_shmem_pread(obj, args);
1137 if (ret == -EFAULT || ret == -ENODEV)
1138 ret = i915_gem_gtt_pread(obj, args);
1139
1140 i915_gem_object_unpin_pages(obj);
1141out:
1142 i915_gem_object_put(obj);
1143 return ret;
1144}
1145
1146/* This is the fast write path which cannot handle
1147 * page faults in the source data
1148 */
1149
1150static inline bool
1151ggtt_write(struct io_mapping *mapping,
1152 loff_t base, int offset,
1153 char __user *user_data, int length)
1154{
1155 void *vaddr;
1156 unsigned long unwritten;
1157
1158 /* We can use the cpu mem copy function because this is X86. */
1159 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1160 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1161 user_data, length);
1162 io_mapping_unmap_atomic(vaddr);
1163 if (unwritten) {
1164 vaddr = (void __force *)
1165 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1166 unwritten = copy_from_user(vaddr + offset, user_data, length);
1167 io_mapping_unmap(vaddr);
1168 }
1169
1170 return unwritten;
1171}
1172
1173/**
1174 * This is the fast pwrite path, where we copy the data directly from the
1175 * user into the GTT, uncached.
1176 * @obj: i915 GEM object
1177 * @args: pwrite arguments structure
1178 */
1179static int
1180i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1181 const struct drm_i915_gem_pwrite *args)
1182{
1183 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1184 struct i915_ggtt *ggtt = &i915->ggtt;
1185 struct drm_mm_node node;
1186 struct i915_vma *vma;
1187 u64 remain, offset;
1188 void __user *user_data;
1189 int ret;
1190
1191 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1192 if (ret)
1193 return ret;
1194
1195 intel_runtime_pm_get(i915);
1196 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1197 PIN_MAPPABLE | PIN_NONBLOCK);
1198 if (!IS_ERR(vma)) {
1199 node.start = i915_ggtt_offset(vma);
1200 node.allocated = false;
1201 ret = i915_vma_put_fence(vma);
1202 if (ret) {
1203 i915_vma_unpin(vma);
1204 vma = ERR_PTR(ret);
1205 }
1206 }
1207 if (IS_ERR(vma)) {
1208 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1209 if (ret)
1210 goto out_unlock;
1211 GEM_BUG_ON(!node.allocated);
1212 }
1213
1214 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1215 if (ret)
1216 goto out_unpin;
1217
1218 mutex_unlock(&i915->drm.struct_mutex);
1219
1220 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1221
1222 user_data = u64_to_user_ptr(args->data_ptr);
1223 offset = args->offset;
1224 remain = args->size;
1225 while (remain) {
1226 /* Operation in this page
1227 *
1228 * page_base = page offset within aperture
1229 * page_offset = offset within page
1230 * page_length = bytes to copy for this page
1231 */
1232 u32 page_base = node.start;
1233 unsigned int page_offset = offset_in_page(offset);
1234 unsigned int page_length = PAGE_SIZE - page_offset;
1235 page_length = remain < page_length ? remain : page_length;
1236 if (node.allocated) {
1237 wmb(); /* flush the write before we modify the GGTT */
1238 ggtt->base.insert_page(&ggtt->base,
1239 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1240 node.start, I915_CACHE_NONE, 0);
1241 wmb(); /* flush modifications to the GGTT (insert_page) */
1242 } else {
1243 page_base += offset & PAGE_MASK;
1244 }
1245 /* If we get a fault while copying data, then (presumably) our
1246 * source page isn't available. Return the error and we'll
1247 * retry in the slow path.
1248 * If the object is non-shmem backed, we retry again with the
1249 * path that handles page fault.
1250 */
1251 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1252 user_data, page_length)) {
1253 ret = -EFAULT;
1254 break;
1255 }
1256
1257 remain -= page_length;
1258 user_data += page_length;
1259 offset += page_length;
1260 }
1261 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1262
1263 mutex_lock(&i915->drm.struct_mutex);
1264out_unpin:
1265 if (node.allocated) {
1266 wmb();
1267 ggtt->base.clear_range(&ggtt->base,
1268 node.start, node.size);
1269 remove_mappable_node(&node);
1270 } else {
1271 i915_vma_unpin(vma);
1272 }
1273out_unlock:
1274 intel_runtime_pm_put(i915);
1275 mutex_unlock(&i915->drm.struct_mutex);
1276 return ret;
1277}
1278
1279static int
1280shmem_pwrite_slow(struct page *page, int offset, int length,
1281 char __user *user_data,
1282 bool page_do_bit17_swizzling,
1283 bool needs_clflush_before,
1284 bool needs_clflush_after)
1285{
1286 char *vaddr;
1287 int ret;
1288
1289 vaddr = kmap(page);
1290 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1291 shmem_clflush_swizzled_range(vaddr + offset, length,
1292 page_do_bit17_swizzling);
1293 if (page_do_bit17_swizzling)
1294 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1295 length);
1296 else
1297 ret = __copy_from_user(vaddr + offset, user_data, length);
1298 if (needs_clflush_after)
1299 shmem_clflush_swizzled_range(vaddr + offset, length,
1300 page_do_bit17_swizzling);
1301 kunmap(page);
1302
1303 return ret ? -EFAULT : 0;
1304}
1305
1306/* Per-page copy function for the shmem pwrite fastpath.
1307 * Flushes invalid cachelines before writing to the target if
1308 * needs_clflush_before is set and flushes out any written cachelines after
1309 * writing if needs_clflush is set.
1310 */
1311static int
1312shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1313 bool page_do_bit17_swizzling,
1314 bool needs_clflush_before,
1315 bool needs_clflush_after)
1316{
1317 int ret;
1318
1319 ret = -ENODEV;
1320 if (!page_do_bit17_swizzling) {
1321 char *vaddr = kmap_atomic(page);
1322
1323 if (needs_clflush_before)
1324 drm_clflush_virt_range(vaddr + offset, len);
1325 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1326 if (needs_clflush_after)
1327 drm_clflush_virt_range(vaddr + offset, len);
1328
1329 kunmap_atomic(vaddr);
1330 }
1331 if (ret == 0)
1332 return ret;
1333
1334 return shmem_pwrite_slow(page, offset, len, user_data,
1335 page_do_bit17_swizzling,
1336 needs_clflush_before,
1337 needs_clflush_after);
1338}
1339
1340static int
1341i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1342 const struct drm_i915_gem_pwrite *args)
1343{
1344 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1345 void __user *user_data;
1346 u64 remain;
1347 unsigned int obj_do_bit17_swizzling;
1348 unsigned int partial_cacheline_write;
1349 unsigned int needs_clflush;
1350 unsigned int offset, idx;
1351 int ret;
1352
1353 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1354 if (ret)
1355 return ret;
1356
1357 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1358 mutex_unlock(&i915->drm.struct_mutex);
1359 if (ret)
1360 return ret;
1361
1362 obj_do_bit17_swizzling = 0;
1363 if (i915_gem_object_needs_bit17_swizzle(obj))
1364 obj_do_bit17_swizzling = BIT(17);
1365
1366 /* If we don't overwrite a cacheline completely we need to be
1367 * careful to have up-to-date data by first clflushing. Don't
1368 * overcomplicate things and flush the entire patch.
1369 */
1370 partial_cacheline_write = 0;
1371 if (needs_clflush & CLFLUSH_BEFORE)
1372 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1373
1374 user_data = u64_to_user_ptr(args->data_ptr);
1375 remain = args->size;
1376 offset = offset_in_page(args->offset);
1377 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1378 struct page *page = i915_gem_object_get_page(obj, idx);
1379 int length;
1380
1381 length = remain;
1382 if (offset + length > PAGE_SIZE)
1383 length = PAGE_SIZE - offset;
1384
1385 ret = shmem_pwrite(page, offset, length, user_data,
1386 page_to_phys(page) & obj_do_bit17_swizzling,
1387 (offset | length) & partial_cacheline_write,
1388 needs_clflush & CLFLUSH_AFTER);
1389 if (ret)
1390 break;
1391
1392 remain -= length;
1393 user_data += length;
1394 offset = 0;
1395 }
1396
1397 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1398 i915_gem_obj_finish_shmem_access(obj);
1399 return ret;
1400}
1401
1402/**
1403 * Writes data to the object referenced by handle.
1404 * @dev: drm device
1405 * @data: ioctl data blob
1406 * @file: drm file
1407 *
1408 * On error, the contents of the buffer that were to be modified are undefined.
1409 */
1410int
1411i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1412 struct drm_file *file)
1413{
1414 struct drm_i915_gem_pwrite *args = data;
1415 struct drm_i915_gem_object *obj;
1416 int ret;
1417
1418 if (args->size == 0)
1419 return 0;
1420
1421 if (!access_ok(VERIFY_READ,
1422 u64_to_user_ptr(args->data_ptr),
1423 args->size))
1424 return -EFAULT;
1425
1426 obj = i915_gem_object_lookup(file, args->handle);
1427 if (!obj)
1428 return -ENOENT;
1429
1430 /* Bounds check destination. */
1431 if (args->offset > obj->base.size ||
1432 args->size > obj->base.size - args->offset) {
1433 ret = -EINVAL;
1434 goto err;
1435 }
1436
1437 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1438
1439 ret = i915_gem_object_wait(obj,
1440 I915_WAIT_INTERRUPTIBLE |
1441 I915_WAIT_ALL,
1442 MAX_SCHEDULE_TIMEOUT,
1443 to_rps_client(file));
1444 if (ret)
1445 goto err;
1446
1447 ret = i915_gem_object_pin_pages(obj);
1448 if (ret)
1449 goto err;
1450
1451 ret = -EFAULT;
1452 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1453 * it would end up going through the fenced access, and we'll get
1454 * different detiling behavior between reading and writing.
1455 * pread/pwrite currently are reading and writing from the CPU
1456 * perspective, requiring manual detiling by the client.
1457 */
1458 if (!i915_gem_object_has_struct_page(obj) ||
1459 cpu_write_needs_clflush(obj))
1460 /* Note that the gtt paths might fail with non-page-backed user
1461 * pointers (e.g. gtt mappings when moving data between
1462 * textures). Fallback to the shmem path in that case.
1463 */
1464 ret = i915_gem_gtt_pwrite_fast(obj, args);
1465
1466 if (ret == -EFAULT || ret == -ENOSPC) {
1467 if (obj->phys_handle)
1468 ret = i915_gem_phys_pwrite(obj, args, file);
1469 else
1470 ret = i915_gem_shmem_pwrite(obj, args);
1471 }
1472
1473 i915_gem_object_unpin_pages(obj);
1474err:
1475 i915_gem_object_put(obj);
1476 return ret;
1477}
1478
1479static inline enum fb_op_origin
1480write_origin(struct drm_i915_gem_object *obj, unsigned domain)
1481{
1482 return (domain == I915_GEM_DOMAIN_GTT ?
1483 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
1484}
1485
1486static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1487{
1488 struct drm_i915_private *i915;
1489 struct list_head *list;
1490 struct i915_vma *vma;
1491
1492 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1493 if (!i915_vma_is_ggtt(vma))
1494 continue;
1495
1496 if (i915_vma_is_active(vma))
1497 continue;
1498
1499 if (!drm_mm_node_allocated(&vma->node))
1500 continue;
1501
1502 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1503 }
1504
1505 i915 = to_i915(obj->base.dev);
1506 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1507 list_move_tail(&obj->global_link, list);
1508}
1509
1510/**
1511 * Called when user space prepares to use an object with the CPU, either
1512 * through the mmap ioctl's mapping or a GTT mapping.
1513 * @dev: drm device
1514 * @data: ioctl data blob
1515 * @file: drm file
1516 */
1517int
1518i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1519 struct drm_file *file)
1520{
1521 struct drm_i915_gem_set_domain *args = data;
1522 struct drm_i915_gem_object *obj;
1523 uint32_t read_domains = args->read_domains;
1524 uint32_t write_domain = args->write_domain;
1525 int err;
1526
1527 /* Only handle setting domains to types used by the CPU. */
1528 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1529 return -EINVAL;
1530
1531 /* Having something in the write domain implies it's in the read
1532 * domain, and only that read domain. Enforce that in the request.
1533 */
1534 if (write_domain != 0 && read_domains != write_domain)
1535 return -EINVAL;
1536
1537 obj = i915_gem_object_lookup(file, args->handle);
1538 if (!obj)
1539 return -ENOENT;
1540
1541 /* Try to flush the object off the GPU without holding the lock.
1542 * We will repeat the flush holding the lock in the normal manner
1543 * to catch cases where we are gazumped.
1544 */
1545 err = i915_gem_object_wait(obj,
1546 I915_WAIT_INTERRUPTIBLE |
1547 (write_domain ? I915_WAIT_ALL : 0),
1548 MAX_SCHEDULE_TIMEOUT,
1549 to_rps_client(file));
1550 if (err)
1551 goto out;
1552
1553 /* Flush and acquire obj->pages so that we are coherent through
1554 * direct access in memory with previous cached writes through
1555 * shmemfs and that our cache domain tracking remains valid.
1556 * For example, if the obj->filp was moved to swap without us
1557 * being notified and releasing the pages, we would mistakenly
1558 * continue to assume that the obj remained out of the CPU cached
1559 * domain.
1560 */
1561 err = i915_gem_object_pin_pages(obj);
1562 if (err)
1563 goto out;
1564
1565 err = i915_mutex_lock_interruptible(dev);
1566 if (err)
1567 goto out_unpin;
1568
1569 if (read_domains & I915_GEM_DOMAIN_GTT)
1570 err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1571 else
1572 err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1573
1574 /* And bump the LRU for this access */
1575 i915_gem_object_bump_inactive_ggtt(obj);
1576
1577 mutex_unlock(&dev->struct_mutex);
1578
1579 if (write_domain != 0)
1580 intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1581
1582out_unpin:
1583 i915_gem_object_unpin_pages(obj);
1584out:
1585 i915_gem_object_put(obj);
1586 return err;
1587}
1588
1589/**
1590 * Called when user space has done writes to this buffer
1591 * @dev: drm device
1592 * @data: ioctl data blob
1593 * @file: drm file
1594 */
1595int
1596i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1597 struct drm_file *file)
1598{
1599 struct drm_i915_gem_sw_finish *args = data;
1600 struct drm_i915_gem_object *obj;
1601 int err = 0;
1602
1603 obj = i915_gem_object_lookup(file, args->handle);
1604 if (!obj)
1605 return -ENOENT;
1606
1607 /* Pinned buffers may be scanout, so flush the cache */
1608 if (READ_ONCE(obj->pin_display)) {
1609 err = i915_mutex_lock_interruptible(dev);
1610 if (!err) {
1611 i915_gem_object_flush_cpu_write_domain(obj);
1612 mutex_unlock(&dev->struct_mutex);
1613 }
1614 }
1615
1616 i915_gem_object_put(obj);
1617 return err;
1618}
1619
1620/**
1621 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1622 * it is mapped to.
1623 * @dev: drm device
1624 * @data: ioctl data blob
1625 * @file: drm file
1626 *
1627 * While the mapping holds a reference on the contents of the object, it doesn't
1628 * imply a ref on the object itself.
1629 *
1630 * IMPORTANT:
1631 *
1632 * DRM driver writers who look a this function as an example for how to do GEM
1633 * mmap support, please don't implement mmap support like here. The modern way
1634 * to implement DRM mmap support is with an mmap offset ioctl (like
1635 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1636 * That way debug tooling like valgrind will understand what's going on, hiding
1637 * the mmap call in a driver private ioctl will break that. The i915 driver only
1638 * does cpu mmaps this way because we didn't know better.
1639 */
1640int
1641i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1642 struct drm_file *file)
1643{
1644 struct drm_i915_gem_mmap *args = data;
1645 struct drm_i915_gem_object *obj;
1646 unsigned long addr;
1647
1648 if (args->flags & ~(I915_MMAP_WC))
1649 return -EINVAL;
1650
1651 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1652 return -ENODEV;
1653
1654 obj = i915_gem_object_lookup(file, args->handle);
1655 if (!obj)
1656 return -ENOENT;
1657
1658 /* prime objects have no backing filp to GEM mmap
1659 * pages from.
1660 */
1661 if (!obj->base.filp) {
1662 i915_gem_object_put(obj);
1663 return -EINVAL;
1664 }
1665
1666 addr = vm_mmap(obj->base.filp, 0, args->size,
1667 PROT_READ | PROT_WRITE, MAP_SHARED,
1668 args->offset);
1669 if (args->flags & I915_MMAP_WC) {
1670 struct mm_struct *mm = current->mm;
1671 struct vm_area_struct *vma;
1672
1673 if (down_write_killable(&mm->mmap_sem)) {
1674 i915_gem_object_put(obj);
1675 return -EINTR;
1676 }
1677 vma = find_vma(mm, addr);
1678 if (vma)
1679 vma->vm_page_prot =
1680 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1681 else
1682 addr = -ENOMEM;
1683 up_write(&mm->mmap_sem);
1684
1685 /* This may race, but that's ok, it only gets set */
1686 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1687 }
1688 i915_gem_object_put(obj);
1689 if (IS_ERR((void *)addr))
1690 return addr;
1691
1692 args->addr_ptr = (uint64_t) addr;
1693
1694 return 0;
1695}
1696
1697static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1698{
1699 u64 size;
1700
1701 size = i915_gem_object_get_stride(obj);
1702 size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8;
1703
1704 return size >> PAGE_SHIFT;
1705}
1706
1707/**
1708 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1709 *
1710 * A history of the GTT mmap interface:
1711 *
1712 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1713 * aligned and suitable for fencing, and still fit into the available
1714 * mappable space left by the pinned display objects. A classic problem
1715 * we called the page-fault-of-doom where we would ping-pong between
1716 * two objects that could not fit inside the GTT and so the memcpy
1717 * would page one object in at the expense of the other between every
1718 * single byte.
1719 *
1720 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1721 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1722 * object is too large for the available space (or simply too large
1723 * for the mappable aperture!), a view is created instead and faulted
1724 * into userspace. (This view is aligned and sized appropriately for
1725 * fenced access.)
1726 *
1727 * Restrictions:
1728 *
1729 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1730 * hangs on some architectures, corruption on others. An attempt to service
1731 * a GTT page fault from a snoopable object will generate a SIGBUS.
1732 *
1733 * * the object must be able to fit into RAM (physical memory, though no
1734 * limited to the mappable aperture).
1735 *
1736 *
1737 * Caveats:
1738 *
1739 * * a new GTT page fault will synchronize rendering from the GPU and flush
1740 * all data to system memory. Subsequent access will not be synchronized.
1741 *
1742 * * all mappings are revoked on runtime device suspend.
1743 *
1744 * * there are only 8, 16 or 32 fence registers to share between all users
1745 * (older machines require fence register for display and blitter access
1746 * as well). Contention of the fence registers will cause the previous users
1747 * to be unmapped and any new access will generate new page faults.
1748 *
1749 * * running out of memory while servicing a fault may generate a SIGBUS,
1750 * rather than the expected SIGSEGV.
1751 */
1752int i915_gem_mmap_gtt_version(void)
1753{
1754 return 1;
1755}
1756
1757/**
1758 * i915_gem_fault - fault a page into the GTT
1759 * @area: CPU VMA in question
1760 * @vmf: fault info
1761 *
1762 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1763 * from userspace. The fault handler takes care of binding the object to
1764 * the GTT (if needed), allocating and programming a fence register (again,
1765 * only if needed based on whether the old reg is still valid or the object
1766 * is tiled) and inserting a new PTE into the faulting process.
1767 *
1768 * Note that the faulting process may involve evicting existing objects
1769 * from the GTT and/or fence registers to make room. So performance may
1770 * suffer if the GTT working set is large or there are few fence registers
1771 * left.
1772 *
1773 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1774 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1775 */
1776int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf)
1777{
1778#define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1779 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1780 struct drm_device *dev = obj->base.dev;
1781 struct drm_i915_private *dev_priv = to_i915(dev);
1782 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1783 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1784 struct i915_vma *vma;
1785 pgoff_t page_offset;
1786 unsigned int flags;
1787 int ret;
1788
1789 /* We don't use vmf->pgoff since that has the fake offset */
1790 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
1791
1792 trace_i915_gem_object_fault(obj, page_offset, true, write);
1793
1794 /* Try to flush the object off the GPU first without holding the lock.
1795 * Upon acquiring the lock, we will perform our sanity checks and then
1796 * repeat the flush holding the lock in the normal manner to catch cases
1797 * where we are gazumped.
1798 */
1799 ret = i915_gem_object_wait(obj,
1800 I915_WAIT_INTERRUPTIBLE,
1801 MAX_SCHEDULE_TIMEOUT,
1802 NULL);
1803 if (ret)
1804 goto err;
1805
1806 ret = i915_gem_object_pin_pages(obj);
1807 if (ret)
1808 goto err;
1809
1810 intel_runtime_pm_get(dev_priv);
1811
1812 ret = i915_mutex_lock_interruptible(dev);
1813 if (ret)
1814 goto err_rpm;
1815
1816 /* Access to snoopable pages through the GTT is incoherent. */
1817 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1818 ret = -EFAULT;
1819 goto err_unlock;
1820 }
1821
1822 /* If the object is smaller than a couple of partial vma, it is
1823 * not worth only creating a single partial vma - we may as well
1824 * clear enough space for the full object.
1825 */
1826 flags = PIN_MAPPABLE;
1827 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1828 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1829
1830 /* Now pin it into the GTT as needed */
1831 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1832 if (IS_ERR(vma)) {
1833 struct i915_ggtt_view view;
1834 unsigned int chunk_size;
1835
1836 /* Use a partial view if it is bigger than available space */
1837 chunk_size = MIN_CHUNK_PAGES;
1838 if (i915_gem_object_is_tiled(obj))
1839 chunk_size = roundup(chunk_size, tile_row_pages(obj));
1840
1841 memset(&view, 0, sizeof(view));
1842 view.type = I915_GGTT_VIEW_PARTIAL;
1843 view.params.partial.offset = rounddown(page_offset, chunk_size);
1844 view.params.partial.size =
1845 min_t(unsigned int, chunk_size,
1846 vma_pages(area) - view.params.partial.offset);
1847
1848 /* If the partial covers the entire object, just create a
1849 * normal VMA.
1850 */
1851 if (chunk_size >= obj->base.size >> PAGE_SHIFT)
1852 view.type = I915_GGTT_VIEW_NORMAL;
1853
1854 /* Userspace is now writing through an untracked VMA, abandon
1855 * all hope that the hardware is able to track future writes.
1856 */
1857 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1858
1859 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1860 }
1861 if (IS_ERR(vma)) {
1862 ret = PTR_ERR(vma);
1863 goto err_unlock;
1864 }
1865
1866 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1867 if (ret)
1868 goto err_unpin;
1869
1870 ret = i915_vma_get_fence(vma);
1871 if (ret)
1872 goto err_unpin;
1873
1874 /* Mark as being mmapped into userspace for later revocation */
1875 assert_rpm_wakelock_held(dev_priv);
1876 if (list_empty(&obj->userfault_link))
1877 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1878
1879 /* Finally, remap it using the new GTT offset */
1880 ret = remap_io_mapping(area,
1881 area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT),
1882 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1883 min_t(u64, vma->size, area->vm_end - area->vm_start),
1884 &ggtt->mappable);
1885
1886err_unpin:
1887 __i915_vma_unpin(vma);
1888err_unlock:
1889 mutex_unlock(&dev->struct_mutex);
1890err_rpm:
1891 intel_runtime_pm_put(dev_priv);
1892 i915_gem_object_unpin_pages(obj);
1893err:
1894 switch (ret) {
1895 case -EIO:
1896 /*
1897 * We eat errors when the gpu is terminally wedged to avoid
1898 * userspace unduly crashing (gl has no provisions for mmaps to
1899 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1900 * and so needs to be reported.
1901 */
1902 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1903 ret = VM_FAULT_SIGBUS;
1904 break;
1905 }
1906 case -EAGAIN:
1907 /*
1908 * EAGAIN means the gpu is hung and we'll wait for the error
1909 * handler to reset everything when re-faulting in
1910 * i915_mutex_lock_interruptible.
1911 */
1912 case 0:
1913 case -ERESTARTSYS:
1914 case -EINTR:
1915 case -EBUSY:
1916 /*
1917 * EBUSY is ok: this just means that another thread
1918 * already did the job.
1919 */
1920 ret = VM_FAULT_NOPAGE;
1921 break;
1922 case -ENOMEM:
1923 ret = VM_FAULT_OOM;
1924 break;
1925 case -ENOSPC:
1926 case -EFAULT:
1927 ret = VM_FAULT_SIGBUS;
1928 break;
1929 default:
1930 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1931 ret = VM_FAULT_SIGBUS;
1932 break;
1933 }
1934 return ret;
1935}
1936
1937/**
1938 * i915_gem_release_mmap - remove physical page mappings
1939 * @obj: obj in question
1940 *
1941 * Preserve the reservation of the mmapping with the DRM core code, but
1942 * relinquish ownership of the pages back to the system.
1943 *
1944 * It is vital that we remove the page mapping if we have mapped a tiled
1945 * object through the GTT and then lose the fence register due to
1946 * resource pressure. Similarly if the object has been moved out of the
1947 * aperture, than pages mapped into userspace must be revoked. Removing the
1948 * mapping will then trigger a page fault on the next user access, allowing
1949 * fixup by i915_gem_fault().
1950 */
1951void
1952i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1953{
1954 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1955
1956 /* Serialisation between user GTT access and our code depends upon
1957 * revoking the CPU's PTE whilst the mutex is held. The next user
1958 * pagefault then has to wait until we release the mutex.
1959 *
1960 * Note that RPM complicates somewhat by adding an additional
1961 * requirement that operations to the GGTT be made holding the RPM
1962 * wakeref.
1963 */
1964 lockdep_assert_held(&i915->drm.struct_mutex);
1965 intel_runtime_pm_get(i915);
1966
1967 if (list_empty(&obj->userfault_link))
1968 goto out;
1969
1970 list_del_init(&obj->userfault_link);
1971 drm_vma_node_unmap(&obj->base.vma_node,
1972 obj->base.dev->anon_inode->i_mapping);
1973
1974 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1975 * memory transactions from userspace before we return. The TLB
1976 * flushing implied above by changing the PTE above *should* be
1977 * sufficient, an extra barrier here just provides us with a bit
1978 * of paranoid documentation about our requirement to serialise
1979 * memory writes before touching registers / GSM.
1980 */
1981 wmb();
1982
1983out:
1984 intel_runtime_pm_put(i915);
1985}
1986
1987void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
1988{
1989 struct drm_i915_gem_object *obj, *on;
1990 int i;
1991
1992 /*
1993 * Only called during RPM suspend. All users of the userfault_list
1994 * must be holding an RPM wakeref to ensure that this can not
1995 * run concurrently with themselves (and use the struct_mutex for
1996 * protection between themselves).
1997 */
1998
1999 list_for_each_entry_safe(obj, on,
2000 &dev_priv->mm.userfault_list, userfault_link) {
2001 list_del_init(&obj->userfault_link);
2002 drm_vma_node_unmap(&obj->base.vma_node,
2003 obj->base.dev->anon_inode->i_mapping);
2004 }
2005
2006 /* The fence will be lost when the device powers down. If any were
2007 * in use by hardware (i.e. they are pinned), we should not be powering
2008 * down! All other fences will be reacquired by the user upon waking.
2009 */
2010 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2011 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2012
2013 /* Ideally we want to assert that the fence register is not
2014 * live at this point (i.e. that no piece of code will be
2015 * trying to write through fence + GTT, as that both violates
2016 * our tracking of activity and associated locking/barriers,
2017 * but also is illegal given that the hw is powered down).
2018 *
2019 * Previously we used reg->pin_count as a "liveness" indicator.
2020 * That is not sufficient, and we need a more fine-grained
2021 * tool if we want to have a sanity check here.
2022 */
2023
2024 if (!reg->vma)
2025 continue;
2026
2027 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2028 reg->dirty = true;
2029 }
2030}
2031
2032/**
2033 * i915_gem_get_ggtt_size - return required global GTT size for an object
2034 * @dev_priv: i915 device
2035 * @size: object size
2036 * @tiling_mode: tiling mode
2037 *
2038 * Return the required global GTT size for an object, taking into account
2039 * potential fence register mapping.
2040 */
2041u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
2042 u64 size, int tiling_mode)
2043{
2044 u64 ggtt_size;
2045
2046 GEM_BUG_ON(size == 0);
2047
2048 if (INTEL_GEN(dev_priv) >= 4 ||
2049 tiling_mode == I915_TILING_NONE)
2050 return size;
2051
2052 /* Previous chips need a power-of-two fence region when tiling */
2053 if (IS_GEN3(dev_priv))
2054 ggtt_size = 1024*1024;
2055 else
2056 ggtt_size = 512*1024;
2057
2058 while (ggtt_size < size)
2059 ggtt_size <<= 1;
2060
2061 return ggtt_size;
2062}
2063
2064/**
2065 * i915_gem_get_ggtt_alignment - return required global GTT alignment
2066 * @dev_priv: i915 device
2067 * @size: object size
2068 * @tiling_mode: tiling mode
2069 * @fenced: is fenced alignment required or not
2070 *
2071 * Return the required global GTT alignment for an object, taking into account
2072 * potential fence register mapping.
2073 */
2074u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
2075 int tiling_mode, bool fenced)
2076{
2077 GEM_BUG_ON(size == 0);
2078
2079 /*
2080 * Minimum alignment is 4k (GTT page size), but might be greater
2081 * if a fence register is needed for the object.
2082 */
2083 if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) ||
2084 tiling_mode == I915_TILING_NONE)
2085 return 4096;
2086
2087 /*
2088 * Previous chips need to be aligned to the size of the smallest
2089 * fence register that can contain the object.
2090 */
2091 return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode);
2092}
2093
2094static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2095{
2096 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2097 int err;
2098
2099 err = drm_gem_create_mmap_offset(&obj->base);
2100 if (!err)
2101 return 0;
2102
2103 /* We can idle the GPU locklessly to flush stale objects, but in order
2104 * to claim that space for ourselves, we need to take the big
2105 * struct_mutex to free the requests+objects and allocate our slot.
2106 */
2107 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2108 if (err)
2109 return err;
2110
2111 err = i915_mutex_lock_interruptible(&dev_priv->drm);
2112 if (!err) {
2113 i915_gem_retire_requests(dev_priv);
2114 err = drm_gem_create_mmap_offset(&obj->base);
2115 mutex_unlock(&dev_priv->drm.struct_mutex);
2116 }
2117
2118 return err;
2119}
2120
2121static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2122{
2123 drm_gem_free_mmap_offset(&obj->base);
2124}
2125
2126int
2127i915_gem_mmap_gtt(struct drm_file *file,
2128 struct drm_device *dev,
2129 uint32_t handle,
2130 uint64_t *offset)
2131{
2132 struct drm_i915_gem_object *obj;
2133 int ret;
2134
2135 obj = i915_gem_object_lookup(file, handle);
2136 if (!obj)
2137 return -ENOENT;
2138
2139 ret = i915_gem_object_create_mmap_offset(obj);
2140 if (ret == 0)
2141 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2142
2143 i915_gem_object_put(obj);
2144 return ret;
2145}
2146
2147/**
2148 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2149 * @dev: DRM device
2150 * @data: GTT mapping ioctl data
2151 * @file: GEM object info
2152 *
2153 * Simply returns the fake offset to userspace so it can mmap it.
2154 * The mmap call will end up in drm_gem_mmap(), which will set things
2155 * up so we can get faults in the handler above.
2156 *
2157 * The fault handler will take care of binding the object into the GTT
2158 * (since it may have been evicted to make room for something), allocating
2159 * a fence register, and mapping the appropriate aperture address into
2160 * userspace.
2161 */
2162int
2163i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *file)
2165{
2166 struct drm_i915_gem_mmap_gtt *args = data;
2167
2168 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2169}
2170
2171/* Immediately discard the backing storage */
2172static void
2173i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2174{
2175 i915_gem_object_free_mmap_offset(obj);
2176
2177 if (obj->base.filp == NULL)
2178 return;
2179
2180 /* Our goal here is to return as much of the memory as
2181 * is possible back to the system as we are called from OOM.
2182 * To do this we must instruct the shmfs to drop all of its
2183 * backing pages, *now*.
2184 */
2185 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2186 obj->mm.madv = __I915_MADV_PURGED;
2187 obj->mm.pages = ERR_PTR(-EFAULT);
2188}
2189
2190/* Try to discard unwanted pages */
2191void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2192{
2193 struct address_space *mapping;
2194
2195 lockdep_assert_held(&obj->mm.lock);
2196 GEM_BUG_ON(obj->mm.pages);
2197
2198 switch (obj->mm.madv) {
2199 case I915_MADV_DONTNEED:
2200 i915_gem_object_truncate(obj);
2201 case __I915_MADV_PURGED:
2202 return;
2203 }
2204
2205 if (obj->base.filp == NULL)
2206 return;
2207
2208 mapping = obj->base.filp->f_mapping,
2209 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2210}
2211
2212static void
2213i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2214 struct sg_table *pages)
2215{
2216 struct sgt_iter sgt_iter;
2217 struct page *page;
2218
2219 __i915_gem_object_release_shmem(obj, pages, true);
2220
2221 i915_gem_gtt_finish_pages(obj, pages);
2222
2223 if (i915_gem_object_needs_bit17_swizzle(obj))
2224 i915_gem_object_save_bit_17_swizzle(obj, pages);
2225
2226 for_each_sgt_page(page, sgt_iter, pages) {
2227 if (obj->mm.dirty)
2228 set_page_dirty(page);
2229
2230 if (obj->mm.madv == I915_MADV_WILLNEED)
2231 mark_page_accessed(page);
2232
2233 put_page(page);
2234 }
2235 obj->mm.dirty = false;
2236
2237 sg_free_table(pages);
2238 kfree(pages);
2239}
2240
2241static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2242{
2243 struct radix_tree_iter iter;
2244 void **slot;
2245
2246 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2247 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2248}
2249
2250void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2251 enum i915_mm_subclass subclass)
2252{
2253 struct sg_table *pages;
2254
2255 if (i915_gem_object_has_pinned_pages(obj))
2256 return;
2257
2258 GEM_BUG_ON(obj->bind_count);
2259 if (!READ_ONCE(obj->mm.pages))
2260 return;
2261
2262 /* May be called by shrinker from within get_pages() (on another bo) */
2263 mutex_lock_nested(&obj->mm.lock, subclass);
2264 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2265 goto unlock;
2266
2267 /* ->put_pages might need to allocate memory for the bit17 swizzle
2268 * array, hence protect them from being reaped by removing them from gtt
2269 * lists early. */
2270 pages = fetch_and_zero(&obj->mm.pages);
2271 GEM_BUG_ON(!pages);
2272
2273 if (obj->mm.mapping) {
2274 void *ptr;
2275
2276 ptr = ptr_mask_bits(obj->mm.mapping);
2277 if (is_vmalloc_addr(ptr))
2278 vunmap(ptr);
2279 else
2280 kunmap(kmap_to_page(ptr));
2281
2282 obj->mm.mapping = NULL;
2283 }
2284
2285 __i915_gem_object_reset_page_iter(obj);
2286
2287 if (!IS_ERR(pages))
2288 obj->ops->put_pages(obj, pages);
2289
2290unlock:
2291 mutex_unlock(&obj->mm.lock);
2292}
2293
2294static void i915_sg_trim(struct sg_table *orig_st)
2295{
2296 struct sg_table new_st;
2297 struct scatterlist *sg, *new_sg;
2298 unsigned int i;
2299
2300 if (orig_st->nents == orig_st->orig_nents)
2301 return;
2302
2303 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2304 return;
2305
2306 new_sg = new_st.sgl;
2307 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2308 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2309 /* called before being DMA mapped, no need to copy sg->dma_* */
2310 new_sg = sg_next(new_sg);
2311 }
2312
2313 sg_free_table(orig_st);
2314
2315 *orig_st = new_st;
2316}
2317
2318static struct sg_table *
2319i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2320{
2321 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2322 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2323 unsigned long i;
2324 struct address_space *mapping;
2325 struct sg_table *st;
2326 struct scatterlist *sg;
2327 struct sgt_iter sgt_iter;
2328 struct page *page;
2329 unsigned long last_pfn = 0; /* suppress gcc warning */
2330 unsigned int max_segment;
2331 int ret;
2332 gfp_t gfp;
2333
2334 /* Assert that the object is not currently in any GPU domain. As it
2335 * wasn't in the GTT, there shouldn't be any way it could have been in
2336 * a GPU cache
2337 */
2338 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2339 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2340
2341 max_segment = swiotlb_max_segment();
2342 if (!max_segment)
2343 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2344
2345 st = kmalloc(sizeof(*st), GFP_KERNEL);
2346 if (st == NULL)
2347 return ERR_PTR(-ENOMEM);
2348
2349rebuild_st:
2350 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2351 kfree(st);
2352 return ERR_PTR(-ENOMEM);
2353 }
2354
2355 /* Get the list of pages out of our struct file. They'll be pinned
2356 * at this point until we release them.
2357 *
2358 * Fail silently without starting the shrinker
2359 */
2360 mapping = obj->base.filp->f_mapping;
2361 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2362 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2363 sg = st->sgl;
2364 st->nents = 0;
2365 for (i = 0; i < page_count; i++) {
2366 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2367 if (IS_ERR(page)) {
2368 i915_gem_shrink(dev_priv,
2369 page_count,
2370 I915_SHRINK_BOUND |
2371 I915_SHRINK_UNBOUND |
2372 I915_SHRINK_PURGEABLE);
2373 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2374 }
2375 if (IS_ERR(page)) {
2376 /* We've tried hard to allocate the memory by reaping
2377 * our own buffer, now let the real VM do its job and
2378 * go down in flames if truly OOM.
2379 */
2380 page = shmem_read_mapping_page(mapping, i);
2381 if (IS_ERR(page)) {
2382 ret = PTR_ERR(page);
2383 goto err_sg;
2384 }
2385 }
2386 if (!i ||
2387 sg->length >= max_segment ||
2388 page_to_pfn(page) != last_pfn + 1) {
2389 if (i)
2390 sg = sg_next(sg);
2391 st->nents++;
2392 sg_set_page(sg, page, PAGE_SIZE, 0);
2393 } else {
2394 sg->length += PAGE_SIZE;
2395 }
2396 last_pfn = page_to_pfn(page);
2397
2398 /* Check that the i965g/gm workaround works. */
2399 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2400 }
2401 if (sg) /* loop terminated early; short sg table */
2402 sg_mark_end(sg);
2403
2404 /* Trim unused sg entries to avoid wasting memory. */
2405 i915_sg_trim(st);
2406
2407 ret = i915_gem_gtt_prepare_pages(obj, st);
2408 if (ret) {
2409 /* DMA remapping failed? One possible cause is that
2410 * it could not reserve enough large entries, asking
2411 * for PAGE_SIZE chunks instead may be helpful.
2412 */
2413 if (max_segment > PAGE_SIZE) {
2414 for_each_sgt_page(page, sgt_iter, st)
2415 put_page(page);
2416 sg_free_table(st);
2417
2418 max_segment = PAGE_SIZE;
2419 goto rebuild_st;
2420 } else {
2421 dev_warn(&dev_priv->drm.pdev->dev,
2422 "Failed to DMA remap %lu pages\n",
2423 page_count);
2424 goto err_pages;
2425 }
2426 }
2427
2428 if (i915_gem_object_needs_bit17_swizzle(obj))
2429 i915_gem_object_do_bit_17_swizzle(obj, st);
2430
2431 return st;
2432
2433err_sg:
2434 sg_mark_end(sg);
2435err_pages:
2436 for_each_sgt_page(page, sgt_iter, st)
2437 put_page(page);
2438 sg_free_table(st);
2439 kfree(st);
2440
2441 /* shmemfs first checks if there is enough memory to allocate the page
2442 * and reports ENOSPC should there be insufficient, along with the usual
2443 * ENOMEM for a genuine allocation failure.
2444 *
2445 * We use ENOSPC in our driver to mean that we have run out of aperture
2446 * space and so want to translate the error from shmemfs back to our
2447 * usual understanding of ENOMEM.
2448 */
2449 if (ret == -ENOSPC)
2450 ret = -ENOMEM;
2451
2452 return ERR_PTR(ret);
2453}
2454
2455void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2456 struct sg_table *pages)
2457{
2458 lockdep_assert_held(&obj->mm.lock);
2459
2460 obj->mm.get_page.sg_pos = pages->sgl;
2461 obj->mm.get_page.sg_idx = 0;
2462
2463 obj->mm.pages = pages;
2464
2465 if (i915_gem_object_is_tiled(obj) &&
2466 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2467 GEM_BUG_ON(obj->mm.quirked);
2468 __i915_gem_object_pin_pages(obj);
2469 obj->mm.quirked = true;
2470 }
2471}
2472
2473static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2474{
2475 struct sg_table *pages;
2476
2477 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2478
2479 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2480 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2481 return -EFAULT;
2482 }
2483
2484 pages = obj->ops->get_pages(obj);
2485 if (unlikely(IS_ERR(pages)))
2486 return PTR_ERR(pages);
2487
2488 __i915_gem_object_set_pages(obj, pages);
2489 return 0;
2490}
2491
2492/* Ensure that the associated pages are gathered from the backing storage
2493 * and pinned into our object. i915_gem_object_pin_pages() may be called
2494 * multiple times before they are released by a single call to
2495 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2496 * either as a result of memory pressure (reaping pages under the shrinker)
2497 * or as the object is itself released.
2498 */
2499int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2500{
2501 int err;
2502
2503 err = mutex_lock_interruptible(&obj->mm.lock);
2504 if (err)
2505 return err;
2506
2507 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2508 err = ____i915_gem_object_get_pages(obj);
2509 if (err)
2510 goto unlock;
2511
2512 smp_mb__before_atomic();
2513 }
2514 atomic_inc(&obj->mm.pages_pin_count);
2515
2516unlock:
2517 mutex_unlock(&obj->mm.lock);
2518 return err;
2519}
2520
2521/* The 'mapping' part of i915_gem_object_pin_map() below */
2522static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2523 enum i915_map_type type)
2524{
2525 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2526 struct sg_table *sgt = obj->mm.pages;
2527 struct sgt_iter sgt_iter;
2528 struct page *page;
2529 struct page *stack_pages[32];
2530 struct page **pages = stack_pages;
2531 unsigned long i = 0;
2532 pgprot_t pgprot;
2533 void *addr;
2534
2535 /* A single page can always be kmapped */
2536 if (n_pages == 1 && type == I915_MAP_WB)
2537 return kmap(sg_page(sgt->sgl));
2538
2539 if (n_pages > ARRAY_SIZE(stack_pages)) {
2540 /* Too big for stack -- allocate temporary array instead */
2541 pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
2542 if (!pages)
2543 return NULL;
2544 }
2545
2546 for_each_sgt_page(page, sgt_iter, sgt)
2547 pages[i++] = page;
2548
2549 /* Check that we have the expected number of pages */
2550 GEM_BUG_ON(i != n_pages);
2551
2552 switch (type) {
2553 case I915_MAP_WB:
2554 pgprot = PAGE_KERNEL;
2555 break;
2556 case I915_MAP_WC:
2557 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2558 break;
2559 }
2560 addr = vmap(pages, n_pages, 0, pgprot);
2561
2562 if (pages != stack_pages)
2563 drm_free_large(pages);
2564
2565 return addr;
2566}
2567
2568/* get, pin, and map the pages of the object into kernel space */
2569void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2570 enum i915_map_type type)
2571{
2572 enum i915_map_type has_type;
2573 bool pinned;
2574 void *ptr;
2575 int ret;
2576
2577 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2578
2579 ret = mutex_lock_interruptible(&obj->mm.lock);
2580 if (ret)
2581 return ERR_PTR(ret);
2582
2583 pinned = true;
2584 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2585 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2586 ret = ____i915_gem_object_get_pages(obj);
2587 if (ret)
2588 goto err_unlock;
2589
2590 smp_mb__before_atomic();
2591 }
2592 atomic_inc(&obj->mm.pages_pin_count);
2593 pinned = false;
2594 }
2595 GEM_BUG_ON(!obj->mm.pages);
2596
2597 ptr = ptr_unpack_bits(obj->mm.mapping, has_type);
2598 if (ptr && has_type != type) {
2599 if (pinned) {
2600 ret = -EBUSY;
2601 goto err_unpin;
2602 }
2603
2604 if (is_vmalloc_addr(ptr))
2605 vunmap(ptr);
2606 else
2607 kunmap(kmap_to_page(ptr));
2608
2609 ptr = obj->mm.mapping = NULL;
2610 }
2611
2612 if (!ptr) {
2613 ptr = i915_gem_object_map(obj, type);
2614 if (!ptr) {
2615 ret = -ENOMEM;
2616 goto err_unpin;
2617 }
2618
2619 obj->mm.mapping = ptr_pack_bits(ptr, type);
2620 }
2621
2622out_unlock:
2623 mutex_unlock(&obj->mm.lock);
2624 return ptr;
2625
2626err_unpin:
2627 atomic_dec(&obj->mm.pages_pin_count);
2628err_unlock:
2629 ptr = ERR_PTR(ret);
2630 goto out_unlock;
2631}
2632
2633static bool i915_context_is_banned(const struct i915_gem_context *ctx)
2634{
2635 unsigned long elapsed;
2636
2637 if (ctx->hang_stats.banned)
2638 return true;
2639
2640 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2641 if (ctx->hang_stats.ban_period_seconds &&
2642 elapsed <= ctx->hang_stats.ban_period_seconds) {
2643 DRM_DEBUG("context hanging too fast, banning!\n");
2644 return true;
2645 }
2646
2647 return false;
2648}
2649
2650static void i915_set_reset_status(struct i915_gem_context *ctx,
2651 const bool guilty)
2652{
2653 struct i915_ctx_hang_stats *hs = &ctx->hang_stats;
2654
2655 if (guilty) {
2656 hs->banned = i915_context_is_banned(ctx);
2657 hs->batch_active++;
2658 hs->guilty_ts = get_seconds();
2659 } else {
2660 hs->batch_pending++;
2661 }
2662}
2663
2664struct drm_i915_gem_request *
2665i915_gem_find_active_request(struct intel_engine_cs *engine)
2666{
2667 struct drm_i915_gem_request *request;
2668
2669 /* We are called by the error capture and reset at a random
2670 * point in time. In particular, note that neither is crucially
2671 * ordered with an interrupt. After a hang, the GPU is dead and we
2672 * assume that no more writes can happen (we waited long enough for
2673 * all writes that were in transaction to be flushed) - adding an
2674 * extra delay for a recent interrupt is pointless. Hence, we do
2675 * not need an engine->irq_seqno_barrier() before the seqno reads.
2676 */
2677 list_for_each_entry(request, &engine->timeline->requests, link) {
2678 if (__i915_gem_request_completed(request))
2679 continue;
2680
2681 return request;
2682 }
2683
2684 return NULL;
2685}
2686
2687static void reset_request(struct drm_i915_gem_request *request)
2688{
2689 void *vaddr = request->ring->vaddr;
2690 u32 head;
2691
2692 /* As this request likely depends on state from the lost
2693 * context, clear out all the user operations leaving the
2694 * breadcrumb at the end (so we get the fence notifications).
2695 */
2696 head = request->head;
2697 if (request->postfix < head) {
2698 memset(vaddr + head, 0, request->ring->size - head);
2699 head = 0;
2700 }
2701 memset(vaddr + head, 0, request->postfix - head);
2702}
2703
2704static void i915_gem_reset_engine(struct intel_engine_cs *engine)
2705{
2706 struct drm_i915_gem_request *request;
2707 struct i915_gem_context *incomplete_ctx;
2708 struct intel_timeline *timeline;
2709 unsigned long flags;
2710 bool ring_hung;
2711
2712 if (engine->irq_seqno_barrier)
2713 engine->irq_seqno_barrier(engine);
2714
2715 request = i915_gem_find_active_request(engine);
2716 if (!request)
2717 return;
2718
2719 ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2720 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine))
2721 ring_hung = false;
2722
2723 i915_set_reset_status(request->ctx, ring_hung);
2724 if (!ring_hung)
2725 return;
2726
2727 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2728 engine->name, request->global_seqno);
2729
2730 /* Setup the CS to resume from the breadcrumb of the hung request */
2731 engine->reset_hw(engine, request);
2732
2733 /* Users of the default context do not rely on logical state
2734 * preserved between batches. They have to emit full state on
2735 * every batch and so it is safe to execute queued requests following
2736 * the hang.
2737 *
2738 * Other contexts preserve state, now corrupt. We want to skip all
2739 * queued requests that reference the corrupt context.
2740 */
2741 incomplete_ctx = request->ctx;
2742 if (i915_gem_context_is_default(incomplete_ctx))
2743 return;
2744
2745 timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine);
2746
2747 spin_lock_irqsave(&engine->timeline->lock, flags);
2748 spin_lock(&timeline->lock);
2749
2750 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2751 if (request->ctx == incomplete_ctx)
2752 reset_request(request);
2753
2754 list_for_each_entry(request, &timeline->requests, link)
2755 reset_request(request);
2756
2757 spin_unlock(&timeline->lock);
2758 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2759}
2760
2761void i915_gem_reset(struct drm_i915_private *dev_priv)
2762{
2763 struct intel_engine_cs *engine;
2764 enum intel_engine_id id;
2765
2766 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2767
2768 i915_gem_retire_requests(dev_priv);
2769
2770 for_each_engine(engine, dev_priv, id)
2771 i915_gem_reset_engine(engine);
2772
2773 i915_gem_restore_fences(dev_priv);
2774
2775 if (dev_priv->gt.awake) {
2776 intel_sanitize_gt_powersave(dev_priv);
2777 intel_enable_gt_powersave(dev_priv);
2778 if (INTEL_GEN(dev_priv) >= 6)
2779 gen6_rps_busy(dev_priv);
2780 }
2781}
2782
2783static void nop_submit_request(struct drm_i915_gem_request *request)
2784{
2785 i915_gem_request_submit(request);
2786 intel_engine_init_global_seqno(request->engine, request->global_seqno);
2787}
2788
2789static void i915_gem_cleanup_engine(struct intel_engine_cs *engine)
2790{
2791 engine->submit_request = nop_submit_request;
2792
2793 /* Mark all pending requests as complete so that any concurrent
2794 * (lockless) lookup doesn't try and wait upon the request as we
2795 * reset it.
2796 */
2797 intel_engine_init_global_seqno(engine,
2798 intel_engine_last_submit(engine));
2799
2800 /*
2801 * Clear the execlists queue up before freeing the requests, as those
2802 * are the ones that keep the context and ringbuffer backing objects
2803 * pinned in place.
2804 */
2805
2806 if (i915.enable_execlists) {
2807 unsigned long flags;
2808
2809 spin_lock_irqsave(&engine->timeline->lock, flags);
2810
2811 i915_gem_request_put(engine->execlist_port[0].request);
2812 i915_gem_request_put(engine->execlist_port[1].request);
2813 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
2814 engine->execlist_queue = RB_ROOT;
2815 engine->execlist_first = NULL;
2816
2817 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2818 }
2819}
2820
2821void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
2822{
2823 struct intel_engine_cs *engine;
2824 enum intel_engine_id id;
2825
2826 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2827 set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
2828
2829 i915_gem_context_lost(dev_priv);
2830 for_each_engine(engine, dev_priv, id)
2831 i915_gem_cleanup_engine(engine);
2832 mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
2833
2834 i915_gem_retire_requests(dev_priv);
2835}
2836
2837static void
2838i915_gem_retire_work_handler(struct work_struct *work)
2839{
2840 struct drm_i915_private *dev_priv =
2841 container_of(work, typeof(*dev_priv), gt.retire_work.work);
2842 struct drm_device *dev = &dev_priv->drm;
2843
2844 /* Come back later if the device is busy... */
2845 if (mutex_trylock(&dev->struct_mutex)) {
2846 i915_gem_retire_requests(dev_priv);
2847 mutex_unlock(&dev->struct_mutex);
2848 }
2849
2850 /* Keep the retire handler running until we are finally idle.
2851 * We do not need to do this test under locking as in the worst-case
2852 * we queue the retire worker once too often.
2853 */
2854 if (READ_ONCE(dev_priv->gt.awake)) {
2855 i915_queue_hangcheck(dev_priv);
2856 queue_delayed_work(dev_priv->wq,
2857 &dev_priv->gt.retire_work,
2858 round_jiffies_up_relative(HZ));
2859 }
2860}
2861
2862static void
2863i915_gem_idle_work_handler(struct work_struct *work)
2864{
2865 struct drm_i915_private *dev_priv =
2866 container_of(work, typeof(*dev_priv), gt.idle_work.work);
2867 struct drm_device *dev = &dev_priv->drm;
2868 struct intel_engine_cs *engine;
2869 enum intel_engine_id id;
2870 bool rearm_hangcheck;
2871
2872 if (!READ_ONCE(dev_priv->gt.awake))
2873 return;
2874
2875 /*
2876 * Wait for last execlists context complete, but bail out in case a
2877 * new request is submitted.
2878 */
2879 wait_for(READ_ONCE(dev_priv->gt.active_requests) ||
2880 intel_execlists_idle(dev_priv), 10);
2881
2882 if (READ_ONCE(dev_priv->gt.active_requests))
2883 return;
2884
2885 rearm_hangcheck =
2886 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
2887
2888 if (!mutex_trylock(&dev->struct_mutex)) {
2889 /* Currently busy, come back later */
2890 mod_delayed_work(dev_priv->wq,
2891 &dev_priv->gt.idle_work,
2892 msecs_to_jiffies(50));
2893 goto out_rearm;
2894 }
2895
2896 /*
2897 * New request retired after this work handler started, extend active
2898 * period until next instance of the work.
2899 */
2900 if (work_pending(work))
2901 goto out_unlock;
2902
2903 if (dev_priv->gt.active_requests)
2904 goto out_unlock;
2905
2906 if (wait_for(intel_execlists_idle(dev_priv), 10))
2907 DRM_ERROR("Timeout waiting for engines to idle\n");
2908
2909 for_each_engine(engine, dev_priv, id)
2910 i915_gem_batch_pool_fini(&engine->batch_pool);
2911
2912 GEM_BUG_ON(!dev_priv->gt.awake);
2913 dev_priv->gt.awake = false;
2914 rearm_hangcheck = false;
2915
2916 if (INTEL_GEN(dev_priv) >= 6)
2917 gen6_rps_idle(dev_priv);
2918 intel_runtime_pm_put(dev_priv);
2919out_unlock:
2920 mutex_unlock(&dev->struct_mutex);
2921
2922out_rearm:
2923 if (rearm_hangcheck) {
2924 GEM_BUG_ON(!dev_priv->gt.awake);
2925 i915_queue_hangcheck(dev_priv);
2926 }
2927}
2928
2929void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
2930{
2931 struct drm_i915_gem_object *obj = to_intel_bo(gem);
2932 struct drm_i915_file_private *fpriv = file->driver_priv;
2933 struct i915_vma *vma, *vn;
2934
2935 mutex_lock(&obj->base.dev->struct_mutex);
2936 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
2937 if (vma->vm->file == fpriv)
2938 i915_vma_close(vma);
2939
2940 if (i915_gem_object_is_active(obj) &&
2941 !i915_gem_object_has_active_reference(obj)) {
2942 i915_gem_object_set_active_reference(obj);
2943 i915_gem_object_get(obj);
2944 }
2945 mutex_unlock(&obj->base.dev->struct_mutex);
2946}
2947
2948static unsigned long to_wait_timeout(s64 timeout_ns)
2949{
2950 if (timeout_ns < 0)
2951 return MAX_SCHEDULE_TIMEOUT;
2952
2953 if (timeout_ns == 0)
2954 return 0;
2955
2956 return nsecs_to_jiffies_timeout(timeout_ns);
2957}
2958
2959/**
2960 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2961 * @dev: drm device pointer
2962 * @data: ioctl data blob
2963 * @file: drm file pointer
2964 *
2965 * Returns 0 if successful, else an error is returned with the remaining time in
2966 * the timeout parameter.
2967 * -ETIME: object is still busy after timeout
2968 * -ERESTARTSYS: signal interrupted the wait
2969 * -ENONENT: object doesn't exist
2970 * Also possible, but rare:
2971 * -EAGAIN: GPU wedged
2972 * -ENOMEM: damn
2973 * -ENODEV: Internal IRQ fail
2974 * -E?: The add request failed
2975 *
2976 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2977 * non-zero timeout parameter the wait ioctl will wait for the given number of
2978 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2979 * without holding struct_mutex the object may become re-busied before this
2980 * function completes. A similar but shorter * race condition exists in the busy
2981 * ioctl
2982 */
2983int
2984i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2985{
2986 struct drm_i915_gem_wait *args = data;
2987 struct drm_i915_gem_object *obj;
2988 ktime_t start;
2989 long ret;
2990
2991 if (args->flags != 0)
2992 return -EINVAL;
2993
2994 obj = i915_gem_object_lookup(file, args->bo_handle);
2995 if (!obj)
2996 return -ENOENT;
2997
2998 start = ktime_get();
2999
3000 ret = i915_gem_object_wait(obj,
3001 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3002 to_wait_timeout(args->timeout_ns),
3003 to_rps_client(file));
3004
3005 if (args->timeout_ns > 0) {
3006 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3007 if (args->timeout_ns < 0)
3008 args->timeout_ns = 0;
3009
3010 /*
3011 * Apparently ktime isn't accurate enough and occasionally has a
3012 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3013 * things up to make the test happy. We allow up to 1 jiffy.
3014 *
3015 * This is a regression from the timespec->ktime conversion.
3016 */
3017 if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3018 args->timeout_ns = 0;
3019 }
3020
3021 i915_gem_object_put(obj);
3022 return ret;
3023}
3024
3025static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3026{
3027 int ret, i;
3028
3029 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3030 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3031 if (ret)
3032 return ret;
3033 }
3034
3035 return 0;
3036}
3037
3038int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3039{
3040 int ret;
3041
3042 if (flags & I915_WAIT_LOCKED) {
3043 struct i915_gem_timeline *tl;
3044
3045 lockdep_assert_held(&i915->drm.struct_mutex);
3046
3047 list_for_each_entry(tl, &i915->gt.timelines, link) {
3048 ret = wait_for_timeline(tl, flags);
3049 if (ret)
3050 return ret;
3051 }
3052 } else {
3053 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3054 if (ret)
3055 return ret;
3056 }
3057
3058 return 0;
3059}
3060
3061void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3062 bool force)
3063{
3064 /* If we don't have a page list set up, then we're not pinned
3065 * to GPU, and we can ignore the cache flush because it'll happen
3066 * again at bind time.
3067 */
3068 if (!obj->mm.pages)
3069 return;
3070
3071 /*
3072 * Stolen memory is always coherent with the GPU as it is explicitly
3073 * marked as wc by the system, or the system is cache-coherent.
3074 */
3075 if (obj->stolen || obj->phys_handle)
3076 return;
3077
3078 /* If the GPU is snooping the contents of the CPU cache,
3079 * we do not need to manually clear the CPU cache lines. However,
3080 * the caches are only snooped when the render cache is
3081 * flushed/invalidated. As we always have to emit invalidations
3082 * and flushes when moving into and out of the RENDER domain, correct
3083 * snooping behaviour occurs naturally as the result of our domain
3084 * tracking.
3085 */
3086 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3087 obj->cache_dirty = true;
3088 return;
3089 }
3090
3091 trace_i915_gem_object_clflush(obj);
3092 drm_clflush_sg(obj->mm.pages);
3093 obj->cache_dirty = false;
3094}
3095
3096/** Flushes the GTT write domain for the object if it's dirty. */
3097static void
3098i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3099{
3100 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3101
3102 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3103 return;
3104
3105 /* No actual flushing is required for the GTT write domain. Writes
3106 * to it "immediately" go to main memory as far as we know, so there's
3107 * no chipset flush. It also doesn't land in render cache.
3108 *
3109 * However, we do have to enforce the order so that all writes through
3110 * the GTT land before any writes to the device, such as updates to
3111 * the GATT itself.
3112 *
3113 * We also have to wait a bit for the writes to land from the GTT.
3114 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3115 * timing. This issue has only been observed when switching quickly
3116 * between GTT writes and CPU reads from inside the kernel on recent hw,
3117 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3118 * system agents we cannot reproduce this behaviour).
3119 */
3120 wmb();
3121 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
3122 POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
3123
3124 intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));
3125
3126 obj->base.write_domain = 0;
3127 trace_i915_gem_object_change_domain(obj,
3128 obj->base.read_domains,
3129 I915_GEM_DOMAIN_GTT);
3130}
3131
3132/** Flushes the CPU write domain for the object if it's dirty. */
3133static void
3134i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3135{
3136 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3137 return;
3138
3139 i915_gem_clflush_object(obj, obj->pin_display);
3140 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3141
3142 obj->base.write_domain = 0;
3143 trace_i915_gem_object_change_domain(obj,
3144 obj->base.read_domains,
3145 I915_GEM_DOMAIN_CPU);
3146}
3147
3148/**
3149 * Moves a single object to the GTT read, and possibly write domain.
3150 * @obj: object to act on
3151 * @write: ask for write access or read only
3152 *
3153 * This function returns when the move is complete, including waiting on
3154 * flushes to occur.
3155 */
3156int
3157i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3158{
3159 uint32_t old_write_domain, old_read_domains;
3160 int ret;
3161
3162 lockdep_assert_held(&obj->base.dev->struct_mutex);
3163
3164 ret = i915_gem_object_wait(obj,
3165 I915_WAIT_INTERRUPTIBLE |
3166 I915_WAIT_LOCKED |
3167 (write ? I915_WAIT_ALL : 0),
3168 MAX_SCHEDULE_TIMEOUT,
3169 NULL);
3170 if (ret)
3171 return ret;
3172
3173 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3174 return 0;
3175
3176 /* Flush and acquire obj->pages so that we are coherent through
3177 * direct access in memory with previous cached writes through
3178 * shmemfs and that our cache domain tracking remains valid.
3179 * For example, if the obj->filp was moved to swap without us
3180 * being notified and releasing the pages, we would mistakenly
3181 * continue to assume that the obj remained out of the CPU cached
3182 * domain.
3183 */
3184 ret = i915_gem_object_pin_pages(obj);
3185 if (ret)
3186 return ret;
3187
3188 i915_gem_object_flush_cpu_write_domain(obj);
3189
3190 /* Serialise direct access to this object with the barriers for
3191 * coherent writes from the GPU, by effectively invalidating the
3192 * GTT domain upon first access.
3193 */
3194 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3195 mb();
3196
3197 old_write_domain = obj->base.write_domain;
3198 old_read_domains = obj->base.read_domains;
3199
3200 /* It should now be out of any other write domains, and we can update
3201 * the domain values for our changes.
3202 */
3203 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3204 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3205 if (write) {
3206 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3207 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3208 obj->mm.dirty = true;
3209 }
3210
3211 trace_i915_gem_object_change_domain(obj,
3212 old_read_domains,
3213 old_write_domain);
3214
3215 i915_gem_object_unpin_pages(obj);
3216 return 0;
3217}
3218
3219/**
3220 * Changes the cache-level of an object across all VMA.
3221 * @obj: object to act on
3222 * @cache_level: new cache level to set for the object
3223 *
3224 * After this function returns, the object will be in the new cache-level
3225 * across all GTT and the contents of the backing storage will be coherent,
3226 * with respect to the new cache-level. In order to keep the backing storage
3227 * coherent for all users, we only allow a single cache level to be set
3228 * globally on the object and prevent it from being changed whilst the
3229 * hardware is reading from the object. That is if the object is currently
3230 * on the scanout it will be set to uncached (or equivalent display
3231 * cache coherency) and all non-MOCS GPU access will also be uncached so
3232 * that all direct access to the scanout remains coherent.
3233 */
3234int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3235 enum i915_cache_level cache_level)
3236{
3237 struct i915_vma *vma;
3238 int ret;
3239
3240 lockdep_assert_held(&obj->base.dev->struct_mutex);
3241
3242 if (obj->cache_level == cache_level)
3243 return 0;
3244
3245 /* Inspect the list of currently bound VMA and unbind any that would
3246 * be invalid given the new cache-level. This is principally to
3247 * catch the issue of the CS prefetch crossing page boundaries and
3248 * reading an invalid PTE on older architectures.
3249 */
3250restart:
3251 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3252 if (!drm_mm_node_allocated(&vma->node))
3253 continue;
3254
3255 if (i915_vma_is_pinned(vma)) {
3256 DRM_DEBUG("can not change the cache level of pinned objects\n");
3257 return -EBUSY;
3258 }
3259
3260 if (i915_gem_valid_gtt_space(vma, cache_level))
3261 continue;
3262
3263 ret = i915_vma_unbind(vma);
3264 if (ret)
3265 return ret;
3266
3267 /* As unbinding may affect other elements in the
3268 * obj->vma_list (due to side-effects from retiring
3269 * an active vma), play safe and restart the iterator.
3270 */
3271 goto restart;
3272 }
3273
3274 /* We can reuse the existing drm_mm nodes but need to change the
3275 * cache-level on the PTE. We could simply unbind them all and
3276 * rebind with the correct cache-level on next use. However since
3277 * we already have a valid slot, dma mapping, pages etc, we may as
3278 * rewrite the PTE in the belief that doing so tramples upon less
3279 * state and so involves less work.
3280 */
3281 if (obj->bind_count) {
3282 /* Before we change the PTE, the GPU must not be accessing it.
3283 * If we wait upon the object, we know that all the bound
3284 * VMA are no longer active.
3285 */
3286 ret = i915_gem_object_wait(obj,
3287 I915_WAIT_INTERRUPTIBLE |
3288 I915_WAIT_LOCKED |
3289 I915_WAIT_ALL,
3290 MAX_SCHEDULE_TIMEOUT,
3291 NULL);
3292 if (ret)
3293 return ret;
3294
3295 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3296 cache_level != I915_CACHE_NONE) {
3297 /* Access to snoopable pages through the GTT is
3298 * incoherent and on some machines causes a hard
3299 * lockup. Relinquish the CPU mmaping to force
3300 * userspace to refault in the pages and we can
3301 * then double check if the GTT mapping is still
3302 * valid for that pointer access.
3303 */
3304 i915_gem_release_mmap(obj);
3305
3306 /* As we no longer need a fence for GTT access,
3307 * we can relinquish it now (and so prevent having
3308 * to steal a fence from someone else on the next
3309 * fence request). Note GPU activity would have
3310 * dropped the fence as all snoopable access is
3311 * supposed to be linear.
3312 */
3313 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3314 ret = i915_vma_put_fence(vma);
3315 if (ret)
3316 return ret;
3317 }
3318 } else {
3319 /* We either have incoherent backing store and
3320 * so no GTT access or the architecture is fully
3321 * coherent. In such cases, existing GTT mmaps
3322 * ignore the cache bit in the PTE and we can
3323 * rewrite it without confusing the GPU or having
3324 * to force userspace to fault back in its mmaps.
3325 */
3326 }
3327
3328 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3329 if (!drm_mm_node_allocated(&vma->node))
3330 continue;
3331
3332 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3333 if (ret)
3334 return ret;
3335 }
3336 }
3337
3338 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU &&
3339 cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3340 obj->cache_dirty = true;
3341
3342 list_for_each_entry(vma, &obj->vma_list, obj_link)
3343 vma->node.color = cache_level;
3344 obj->cache_level = cache_level;
3345
3346 return 0;
3347}
3348
3349int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3350 struct drm_file *file)
3351{
3352 struct drm_i915_gem_caching *args = data;
3353 struct drm_i915_gem_object *obj;
3354 int err = 0;
3355
3356 rcu_read_lock();
3357 obj = i915_gem_object_lookup_rcu(file, args->handle);
3358 if (!obj) {
3359 err = -ENOENT;
3360 goto out;
3361 }
3362
3363 switch (obj->cache_level) {
3364 case I915_CACHE_LLC:
3365 case I915_CACHE_L3_LLC:
3366 args->caching = I915_CACHING_CACHED;
3367 break;
3368
3369 case I915_CACHE_WT:
3370 args->caching = I915_CACHING_DISPLAY;
3371 break;
3372
3373 default:
3374 args->caching = I915_CACHING_NONE;
3375 break;
3376 }
3377out:
3378 rcu_read_unlock();
3379 return err;
3380}
3381
3382int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3383 struct drm_file *file)
3384{
3385 struct drm_i915_private *i915 = to_i915(dev);
3386 struct drm_i915_gem_caching *args = data;
3387 struct drm_i915_gem_object *obj;
3388 enum i915_cache_level level;
3389 int ret;
3390
3391 switch (args->caching) {
3392 case I915_CACHING_NONE:
3393 level = I915_CACHE_NONE;
3394 break;
3395 case I915_CACHING_CACHED:
3396 /*
3397 * Due to a HW issue on BXT A stepping, GPU stores via a
3398 * snooped mapping may leave stale data in a corresponding CPU
3399 * cacheline, whereas normally such cachelines would get
3400 * invalidated.
3401 */
3402 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3403 return -ENODEV;
3404
3405 level = I915_CACHE_LLC;
3406 break;
3407 case I915_CACHING_DISPLAY:
3408 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3409 break;
3410 default:
3411 return -EINVAL;
3412 }
3413
3414 ret = i915_mutex_lock_interruptible(dev);
3415 if (ret)
3416 return ret;
3417
3418 obj = i915_gem_object_lookup(file, args->handle);
3419 if (!obj) {
3420 ret = -ENOENT;
3421 goto unlock;
3422 }
3423
3424 ret = i915_gem_object_set_cache_level(obj, level);
3425 i915_gem_object_put(obj);
3426unlock:
3427 mutex_unlock(&dev->struct_mutex);
3428 return ret;
3429}
3430
3431/*
3432 * Prepare buffer for display plane (scanout, cursors, etc).
3433 * Can be called from an uninterruptible phase (modesetting) and allows
3434 * any flushes to be pipelined (for pageflips).
3435 */
3436struct i915_vma *
3437i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3438 u32 alignment,
3439 const struct i915_ggtt_view *view)
3440{
3441 struct i915_vma *vma;
3442 u32 old_read_domains, old_write_domain;
3443 int ret;
3444
3445 lockdep_assert_held(&obj->base.dev->struct_mutex);
3446
3447 /* Mark the pin_display early so that we account for the
3448 * display coherency whilst setting up the cache domains.
3449 */
3450 obj->pin_display++;
3451
3452 /* The display engine is not coherent with the LLC cache on gen6. As
3453 * a result, we make sure that the pinning that is about to occur is
3454 * done with uncached PTEs. This is lowest common denominator for all
3455 * chipsets.
3456 *
3457 * However for gen6+, we could do better by using the GFDT bit instead
3458 * of uncaching, which would allow us to flush all the LLC-cached data
3459 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3460 */
3461 ret = i915_gem_object_set_cache_level(obj,
3462 HAS_WT(to_i915(obj->base.dev)) ?
3463 I915_CACHE_WT : I915_CACHE_NONE);
3464 if (ret) {
3465 vma = ERR_PTR(ret);
3466 goto err_unpin_display;
3467 }
3468
3469 /* As the user may map the buffer once pinned in the display plane
3470 * (e.g. libkms for the bootup splash), we have to ensure that we
3471 * always use map_and_fenceable for all scanout buffers. However,
3472 * it may simply be too big to fit into mappable, in which case
3473 * put it anyway and hope that userspace can cope (but always first
3474 * try to preserve the existing ABI).
3475 */
3476 vma = ERR_PTR(-ENOSPC);
3477 if (view->type == I915_GGTT_VIEW_NORMAL)
3478 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3479 PIN_MAPPABLE | PIN_NONBLOCK);
3480 if (IS_ERR(vma)) {
3481 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3482 unsigned int flags;
3483
3484 /* Valleyview is definitely limited to scanning out the first
3485 * 512MiB. Lets presume this behaviour was inherited from the
3486 * g4x display engine and that all earlier gen are similarly
3487 * limited. Testing suggests that it is a little more
3488 * complicated than this. For example, Cherryview appears quite
3489 * happy to scanout from anywhere within its global aperture.
3490 */
3491 flags = 0;
3492 if (HAS_GMCH_DISPLAY(i915))
3493 flags = PIN_MAPPABLE;
3494 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3495 }
3496 if (IS_ERR(vma))
3497 goto err_unpin_display;
3498
3499 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3500
3501 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3502 if (obj->cache_dirty || obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
3503 i915_gem_clflush_object(obj, true);
3504 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
3505 }
3506
3507 old_write_domain = obj->base.write_domain;
3508 old_read_domains = obj->base.read_domains;
3509
3510 /* It should now be out of any other write domains, and we can update
3511 * the domain values for our changes.
3512 */
3513 obj->base.write_domain = 0;
3514 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3515
3516 trace_i915_gem_object_change_domain(obj,
3517 old_read_domains,
3518 old_write_domain);
3519
3520 return vma;
3521
3522err_unpin_display:
3523 obj->pin_display--;
3524 return vma;
3525}
3526
3527void
3528i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3529{
3530 lockdep_assert_held(&vma->vm->dev->struct_mutex);
3531
3532 if (WARN_ON(vma->obj->pin_display == 0))
3533 return;
3534
3535 if (--vma->obj->pin_display == 0)
3536 vma->display_alignment = 0;
3537
3538 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3539 if (!i915_vma_is_active(vma))
3540 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
3541
3542 i915_vma_unpin(vma);
3543}
3544
3545/**
3546 * Moves a single object to the CPU read, and possibly write domain.
3547 * @obj: object to act on
3548 * @write: requesting write or read-only access
3549 *
3550 * This function returns when the move is complete, including waiting on
3551 * flushes to occur.
3552 */
3553int
3554i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3555{
3556 uint32_t old_write_domain, old_read_domains;
3557 int ret;
3558
3559 lockdep_assert_held(&obj->base.dev->struct_mutex);
3560
3561 ret = i915_gem_object_wait(obj,
3562 I915_WAIT_INTERRUPTIBLE |
3563 I915_WAIT_LOCKED |
3564 (write ? I915_WAIT_ALL : 0),
3565 MAX_SCHEDULE_TIMEOUT,
3566 NULL);
3567 if (ret)
3568 return ret;
3569
3570 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3571 return 0;
3572
3573 i915_gem_object_flush_gtt_write_domain(obj);
3574
3575 old_write_domain = obj->base.write_domain;
3576 old_read_domains = obj->base.read_domains;
3577
3578 /* Flush the CPU cache if it's still invalid. */
3579 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3580 i915_gem_clflush_object(obj, false);
3581
3582 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3583 }
3584
3585 /* It should now be out of any other write domains, and we can update
3586 * the domain values for our changes.
3587 */
3588 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3589
3590 /* If we're writing through the CPU, then the GPU read domains will
3591 * need to be invalidated at next use.
3592 */
3593 if (write) {
3594 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3595 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3596 }
3597
3598 trace_i915_gem_object_change_domain(obj,
3599 old_read_domains,
3600 old_write_domain);
3601
3602 return 0;
3603}
3604
3605/* Throttle our rendering by waiting until the ring has completed our requests
3606 * emitted over 20 msec ago.
3607 *
3608 * Note that if we were to use the current jiffies each time around the loop,
3609 * we wouldn't escape the function with any frames outstanding if the time to
3610 * render a frame was over 20ms.
3611 *
3612 * This should get us reasonable parallelism between CPU and GPU but also
3613 * relatively low latency when blocking on a particular request to finish.
3614 */
3615static int
3616i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3617{
3618 struct drm_i915_private *dev_priv = to_i915(dev);
3619 struct drm_i915_file_private *file_priv = file->driver_priv;
3620 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3621 struct drm_i915_gem_request *request, *target = NULL;
3622 long ret;
3623
3624 /* ABI: return -EIO if already wedged */
3625 if (i915_terminally_wedged(&dev_priv->gpu_error))
3626 return -EIO;
3627
3628 spin_lock(&file_priv->mm.lock);
3629 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3630 if (time_after_eq(request->emitted_jiffies, recent_enough))
3631 break;
3632
3633 /*
3634 * Note that the request might not have been submitted yet.
3635 * In which case emitted_jiffies will be zero.
3636 */
3637 if (!request->emitted_jiffies)
3638 continue;
3639
3640 target = request;
3641 }
3642 if (target)
3643 i915_gem_request_get(target);
3644 spin_unlock(&file_priv->mm.lock);
3645
3646 if (target == NULL)
3647 return 0;
3648
3649 ret = i915_wait_request(target,
3650 I915_WAIT_INTERRUPTIBLE,
3651 MAX_SCHEDULE_TIMEOUT);
3652 i915_gem_request_put(target);
3653
3654 return ret < 0 ? ret : 0;
3655}
3656
3657struct i915_vma *
3658i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3659 const struct i915_ggtt_view *view,
3660 u64 size,
3661 u64 alignment,
3662 u64 flags)
3663{
3664 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3665 struct i915_address_space *vm = &dev_priv->ggtt.base;
3666 struct i915_vma *vma;
3667 int ret;
3668
3669 lockdep_assert_held(&obj->base.dev->struct_mutex);
3670
3671 vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view);
3672 if (IS_ERR(vma))
3673 return vma;
3674
3675 if (i915_vma_misplaced(vma, size, alignment, flags)) {
3676 if (flags & PIN_NONBLOCK &&
3677 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
3678 return ERR_PTR(-ENOSPC);
3679
3680 if (flags & PIN_MAPPABLE) {
3681 u32 fence_size;
3682
3683 fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,
3684 i915_gem_object_get_tiling(obj));
3685 /* If the required space is larger than the available
3686 * aperture, we will not able to find a slot for the
3687 * object and unbinding the object now will be in
3688 * vain. Worse, doing so may cause us to ping-pong
3689 * the object in and out of the Global GTT and
3690 * waste a lot of cycles under the mutex.
3691 */
3692 if (fence_size > dev_priv->ggtt.mappable_end)
3693 return ERR_PTR(-E2BIG);
3694
3695 /* If NONBLOCK is set the caller is optimistically
3696 * trying to cache the full object within the mappable
3697 * aperture, and *must* have a fallback in place for
3698 * situations where we cannot bind the object. We
3699 * can be a little more lax here and use the fallback
3700 * more often to avoid costly migrations of ourselves
3701 * and other objects within the aperture.
3702 *
3703 * Half-the-aperture is used as a simple heuristic.
3704 * More interesting would to do search for a free
3705 * block prior to making the commitment to unbind.
3706 * That caters for the self-harm case, and with a
3707 * little more heuristics (e.g. NOFAULT, NOEVICT)
3708 * we could try to minimise harm to others.
3709 */
3710 if (flags & PIN_NONBLOCK &&
3711 fence_size > dev_priv->ggtt.mappable_end / 2)
3712 return ERR_PTR(-ENOSPC);
3713 }
3714
3715 WARN(i915_vma_is_pinned(vma),
3716 "bo is already pinned in ggtt with incorrect alignment:"
3717 " offset=%08x, req.alignment=%llx,"
3718 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3719 i915_ggtt_offset(vma), alignment,
3720 !!(flags & PIN_MAPPABLE),
3721 i915_vma_is_map_and_fenceable(vma));
3722 ret = i915_vma_unbind(vma);
3723 if (ret)
3724 return ERR_PTR(ret);
3725 }
3726
3727 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
3728 if (ret)
3729 return ERR_PTR(ret);
3730
3731 return vma;
3732}
3733
3734static __always_inline unsigned int __busy_read_flag(unsigned int id)
3735{
3736 /* Note that we could alias engines in the execbuf API, but
3737 * that would be very unwise as it prevents userspace from
3738 * fine control over engine selection. Ahem.
3739 *
3740 * This should be something like EXEC_MAX_ENGINE instead of
3741 * I915_NUM_ENGINES.
3742 */
3743 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
3744 return 0x10000 << id;
3745}
3746
3747static __always_inline unsigned int __busy_write_id(unsigned int id)
3748{
3749 /* The uABI guarantees an active writer is also amongst the read
3750 * engines. This would be true if we accessed the activity tracking
3751 * under the lock, but as we perform the lookup of the object and
3752 * its activity locklessly we can not guarantee that the last_write
3753 * being active implies that we have set the same engine flag from
3754 * last_read - hence we always set both read and write busy for
3755 * last_write.
3756 */
3757 return id | __busy_read_flag(id);
3758}
3759
3760static __always_inline unsigned int
3761__busy_set_if_active(const struct dma_fence *fence,
3762 unsigned int (*flag)(unsigned int id))
3763{
3764 struct drm_i915_gem_request *rq;
3765
3766 /* We have to check the current hw status of the fence as the uABI
3767 * guarantees forward progress. We could rely on the idle worker
3768 * to eventually flush us, but to minimise latency just ask the
3769 * hardware.
3770 *
3771 * Note we only report on the status of native fences.
3772 */
3773 if (!dma_fence_is_i915(fence))
3774 return 0;
3775
3776 /* opencode to_request() in order to avoid const warnings */
3777 rq = container_of(fence, struct drm_i915_gem_request, fence);
3778 if (i915_gem_request_completed(rq))
3779 return 0;
3780
3781 return flag(rq->engine->exec_id);
3782}
3783
3784static __always_inline unsigned int
3785busy_check_reader(const struct dma_fence *fence)
3786{
3787 return __busy_set_if_active(fence, __busy_read_flag);
3788}
3789
3790static __always_inline unsigned int
3791busy_check_writer(const struct dma_fence *fence)
3792{
3793 if (!fence)
3794 return 0;
3795
3796 return __busy_set_if_active(fence, __busy_write_id);
3797}
3798
3799int
3800i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3801 struct drm_file *file)
3802{
3803 struct drm_i915_gem_busy *args = data;
3804 struct drm_i915_gem_object *obj;
3805 struct reservation_object_list *list;
3806 unsigned int seq;
3807 int err;
3808
3809 err = -ENOENT;
3810 rcu_read_lock();
3811 obj = i915_gem_object_lookup_rcu(file, args->handle);
3812 if (!obj)
3813 goto out;
3814
3815 /* A discrepancy here is that we do not report the status of
3816 * non-i915 fences, i.e. even though we may report the object as idle,
3817 * a call to set-domain may still stall waiting for foreign rendering.
3818 * This also means that wait-ioctl may report an object as busy,
3819 * where busy-ioctl considers it idle.
3820 *
3821 * We trade the ability to warn of foreign fences to report on which
3822 * i915 engines are active for the object.
3823 *
3824 * Alternatively, we can trade that extra information on read/write
3825 * activity with
3826 * args->busy =
3827 * !reservation_object_test_signaled_rcu(obj->resv, true);
3828 * to report the overall busyness. This is what the wait-ioctl does.
3829 *
3830 */
3831retry:
3832 seq = raw_read_seqcount(&obj->resv->seq);
3833
3834 /* Translate the exclusive fence to the READ *and* WRITE engine */
3835 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
3836
3837 /* Translate shared fences to READ set of engines */
3838 list = rcu_dereference(obj->resv->fence);
3839 if (list) {
3840 unsigned int shared_count = list->shared_count, i;
3841
3842 for (i = 0; i < shared_count; ++i) {
3843 struct dma_fence *fence =
3844 rcu_dereference(list->shared[i]);
3845
3846 args->busy |= busy_check_reader(fence);
3847 }
3848 }
3849
3850 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
3851 goto retry;
3852
3853 err = 0;
3854out:
3855 rcu_read_unlock();
3856 return err;
3857}
3858
3859int
3860i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3861 struct drm_file *file_priv)
3862{
3863 return i915_gem_ring_throttle(dev, file_priv);
3864}
3865
3866int
3867i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3868 struct drm_file *file_priv)
3869{
3870 struct drm_i915_private *dev_priv = to_i915(dev);
3871 struct drm_i915_gem_madvise *args = data;
3872 struct drm_i915_gem_object *obj;
3873 int err;
3874
3875 switch (args->madv) {
3876 case I915_MADV_DONTNEED:
3877 case I915_MADV_WILLNEED:
3878 break;
3879 default:
3880 return -EINVAL;
3881 }
3882
3883 obj = i915_gem_object_lookup(file_priv, args->handle);
3884 if (!obj)
3885 return -ENOENT;
3886
3887 err = mutex_lock_interruptible(&obj->mm.lock);
3888 if (err)
3889 goto out;
3890
3891 if (obj->mm.pages &&
3892 i915_gem_object_is_tiled(obj) &&
3893 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
3894 if (obj->mm.madv == I915_MADV_WILLNEED) {
3895 GEM_BUG_ON(!obj->mm.quirked);
3896 __i915_gem_object_unpin_pages(obj);
3897 obj->mm.quirked = false;
3898 }
3899 if (args->madv == I915_MADV_WILLNEED) {
3900 GEM_BUG_ON(obj->mm.quirked);
3901 __i915_gem_object_pin_pages(obj);
3902 obj->mm.quirked = true;
3903 }
3904 }
3905
3906 if (obj->mm.madv != __I915_MADV_PURGED)
3907 obj->mm.madv = args->madv;
3908
3909 /* if the object is no longer attached, discard its backing storage */
3910 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
3911 i915_gem_object_truncate(obj);
3912
3913 args->retained = obj->mm.madv != __I915_MADV_PURGED;
3914 mutex_unlock(&obj->mm.lock);
3915
3916out:
3917 i915_gem_object_put(obj);
3918 return err;
3919}
3920
3921static void
3922frontbuffer_retire(struct i915_gem_active *active,
3923 struct drm_i915_gem_request *request)
3924{
3925 struct drm_i915_gem_object *obj =
3926 container_of(active, typeof(*obj), frontbuffer_write);
3927
3928 intel_fb_obj_flush(obj, true, ORIGIN_CS);
3929}
3930
3931void i915_gem_object_init(struct drm_i915_gem_object *obj,
3932 const struct drm_i915_gem_object_ops *ops)
3933{
3934 mutex_init(&obj->mm.lock);
3935
3936 INIT_LIST_HEAD(&obj->global_link);
3937 INIT_LIST_HEAD(&obj->userfault_link);
3938 INIT_LIST_HEAD(&obj->obj_exec_link);
3939 INIT_LIST_HEAD(&obj->vma_list);
3940 INIT_LIST_HEAD(&obj->batch_pool_link);
3941
3942 obj->ops = ops;
3943
3944 reservation_object_init(&obj->__builtin_resv);
3945 obj->resv = &obj->__builtin_resv;
3946
3947 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
3948 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
3949
3950 obj->mm.madv = I915_MADV_WILLNEED;
3951 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
3952 mutex_init(&obj->mm.get_page.lock);
3953
3954 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
3955}
3956
3957static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3958 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
3959 I915_GEM_OBJECT_IS_SHRINKABLE,
3960 .get_pages = i915_gem_object_get_pages_gtt,
3961 .put_pages = i915_gem_object_put_pages_gtt,
3962};
3963
3964/* Note we don't consider signbits :| */
3965#define overflows_type(x, T) \
3966 (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
3967
3968struct drm_i915_gem_object *
3969i915_gem_object_create(struct drm_device *dev, u64 size)
3970{
3971 struct drm_i915_private *dev_priv = to_i915(dev);
3972 struct drm_i915_gem_object *obj;
3973 struct address_space *mapping;
3974 gfp_t mask;
3975 int ret;
3976
3977 /* There is a prevalence of the assumption that we fit the object's
3978 * page count inside a 32bit _signed_ variable. Let's document this and
3979 * catch if we ever need to fix it. In the meantime, if you do spot
3980 * such a local variable, please consider fixing!
3981 */
3982 if (WARN_ON(size >> PAGE_SHIFT > INT_MAX))
3983 return ERR_PTR(-E2BIG);
3984
3985 if (overflows_type(size, obj->base.size))
3986 return ERR_PTR(-E2BIG);
3987
3988 obj = i915_gem_object_alloc(dev);
3989 if (obj == NULL)
3990 return ERR_PTR(-ENOMEM);
3991
3992 ret = drm_gem_object_init(dev, &obj->base, size);
3993 if (ret)
3994 goto fail;
3995
3996 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3997 if (IS_CRESTLINE(dev_priv) || IS_BROADWATER(dev_priv)) {
3998 /* 965gm cannot relocate objects above 4GiB. */
3999 mask &= ~__GFP_HIGHMEM;
4000 mask |= __GFP_DMA32;
4001 }
4002
4003 mapping = obj->base.filp->f_mapping;
4004 mapping_set_gfp_mask(mapping, mask);
4005
4006 i915_gem_object_init(obj, &i915_gem_object_ops);
4007
4008 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4009 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4010
4011 if (HAS_LLC(dev_priv)) {
4012 /* On some devices, we can have the GPU use the LLC (the CPU
4013 * cache) for about a 10% performance improvement
4014 * compared to uncached. Graphics requests other than
4015 * display scanout are coherent with the CPU in
4016 * accessing this cache. This means in this mode we
4017 * don't need to clflush on the CPU side, and on the
4018 * GPU side we only need to flush internal caches to
4019 * get data visible to the CPU.
4020 *
4021 * However, we maintain the display planes as UC, and so
4022 * need to rebind when first used as such.
4023 */
4024 obj->cache_level = I915_CACHE_LLC;
4025 } else
4026 obj->cache_level = I915_CACHE_NONE;
4027
4028 trace_i915_gem_object_create(obj);
4029
4030 return obj;
4031
4032fail:
4033 i915_gem_object_free(obj);
4034 return ERR_PTR(ret);
4035}
4036
4037static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4038{
4039 /* If we are the last user of the backing storage (be it shmemfs
4040 * pages or stolen etc), we know that the pages are going to be
4041 * immediately released. In this case, we can then skip copying
4042 * back the contents from the GPU.
4043 */
4044
4045 if (obj->mm.madv != I915_MADV_WILLNEED)
4046 return false;
4047
4048 if (obj->base.filp == NULL)
4049 return true;
4050
4051 /* At first glance, this looks racy, but then again so would be
4052 * userspace racing mmap against close. However, the first external
4053 * reference to the filp can only be obtained through the
4054 * i915_gem_mmap_ioctl() which safeguards us against the user
4055 * acquiring such a reference whilst we are in the middle of
4056 * freeing the object.
4057 */
4058 return atomic_long_read(&obj->base.filp->f_count) == 1;
4059}
4060
4061static void __i915_gem_free_objects(struct drm_i915_private *i915,
4062 struct llist_node *freed)
4063{
4064 struct drm_i915_gem_object *obj, *on;
4065
4066 mutex_lock(&i915->drm.struct_mutex);
4067 intel_runtime_pm_get(i915);
4068 llist_for_each_entry(obj, freed, freed) {
4069 struct i915_vma *vma, *vn;
4070
4071 trace_i915_gem_object_destroy(obj);
4072
4073 GEM_BUG_ON(i915_gem_object_is_active(obj));
4074 list_for_each_entry_safe(vma, vn,
4075 &obj->vma_list, obj_link) {
4076 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
4077 GEM_BUG_ON(i915_vma_is_active(vma));
4078 vma->flags &= ~I915_VMA_PIN_MASK;
4079 i915_vma_close(vma);
4080 }
4081 GEM_BUG_ON(!list_empty(&obj->vma_list));
4082 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4083
4084 list_del(&obj->global_link);
4085 }
4086 intel_runtime_pm_put(i915);
4087 mutex_unlock(&i915->drm.struct_mutex);
4088
4089 llist_for_each_entry_safe(obj, on, freed, freed) {
4090 GEM_BUG_ON(obj->bind_count);
4091 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4092
4093 if (obj->ops->release)
4094 obj->ops->release(obj);
4095
4096 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4097 atomic_set(&obj->mm.pages_pin_count, 0);
4098 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4099 GEM_BUG_ON(obj->mm.pages);
4100
4101 if (obj->base.import_attach)
4102 drm_prime_gem_destroy(&obj->base, NULL);
4103
4104 reservation_object_fini(&obj->__builtin_resv);
4105 drm_gem_object_release(&obj->base);
4106 i915_gem_info_remove_obj(i915, obj->base.size);
4107
4108 kfree(obj->bit_17);
4109 i915_gem_object_free(obj);
4110 }
4111}
4112
4113static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4114{
4115 struct llist_node *freed;
4116
4117 freed = llist_del_all(&i915->mm.free_list);
4118 if (unlikely(freed))
4119 __i915_gem_free_objects(i915, freed);
4120}
4121
4122static void __i915_gem_free_work(struct work_struct *work)
4123{
4124 struct drm_i915_private *i915 =
4125 container_of(work, struct drm_i915_private, mm.free_work);
4126 struct llist_node *freed;
4127
4128 /* All file-owned VMA should have been released by this point through
4129 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4130 * However, the object may also be bound into the global GTT (e.g.
4131 * older GPUs without per-process support, or for direct access through
4132 * the GTT either for the user or for scanout). Those VMA still need to
4133 * unbound now.
4134 */
4135
4136 while ((freed = llist_del_all(&i915->mm.free_list)))
4137 __i915_gem_free_objects(i915, freed);
4138}
4139
4140static void __i915_gem_free_object_rcu(struct rcu_head *head)
4141{
4142 struct drm_i915_gem_object *obj =
4143 container_of(head, typeof(*obj), rcu);
4144 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4145
4146 /* We can't simply use call_rcu() from i915_gem_free_object()
4147 * as we need to block whilst unbinding, and the call_rcu
4148 * task may be called from softirq context. So we take a
4149 * detour through a worker.
4150 */
4151 if (llist_add(&obj->freed, &i915->mm.free_list))
4152 schedule_work(&i915->mm.free_work);
4153}
4154
4155void i915_gem_free_object(struct drm_gem_object *gem_obj)
4156{
4157 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4158
4159 if (obj->mm.quirked)
4160 __i915_gem_object_unpin_pages(obj);
4161
4162 if (discard_backing_storage(obj))
4163 obj->mm.madv = I915_MADV_DONTNEED;
4164
4165 /* Before we free the object, make sure any pure RCU-only
4166 * read-side critical sections are complete, e.g.
4167 * i915_gem_busy_ioctl(). For the corresponding synchronized
4168 * lookup see i915_gem_object_lookup_rcu().
4169 */
4170 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4171}
4172
4173void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4174{
4175 lockdep_assert_held(&obj->base.dev->struct_mutex);
4176
4177 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4178 if (i915_gem_object_is_active(obj))
4179 i915_gem_object_set_active_reference(obj);
4180 else
4181 i915_gem_object_put(obj);
4182}
4183
4184static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4185{
4186 struct intel_engine_cs *engine;
4187 enum intel_engine_id id;
4188
4189 for_each_engine(engine, dev_priv, id)
4190 GEM_BUG_ON(engine->last_context != dev_priv->kernel_context);
4191}
4192
4193int i915_gem_suspend(struct drm_device *dev)
4194{
4195 struct drm_i915_private *dev_priv = to_i915(dev);
4196 int ret;
4197
4198 intel_suspend_gt_powersave(dev_priv);
4199
4200 mutex_lock(&dev->struct_mutex);
4201
4202 /* We have to flush all the executing contexts to main memory so
4203 * that they can saved in the hibernation image. To ensure the last
4204 * context image is coherent, we have to switch away from it. That
4205 * leaves the dev_priv->kernel_context still active when
4206 * we actually suspend, and its image in memory may not match the GPU
4207 * state. Fortunately, the kernel_context is disposable and we do
4208 * not rely on its state.
4209 */
4210 ret = i915_gem_switch_to_kernel_context(dev_priv);
4211 if (ret)
4212 goto err;
4213
4214 ret = i915_gem_wait_for_idle(dev_priv,
4215 I915_WAIT_INTERRUPTIBLE |
4216 I915_WAIT_LOCKED);
4217 if (ret)
4218 goto err;
4219
4220 i915_gem_retire_requests(dev_priv);
4221 GEM_BUG_ON(dev_priv->gt.active_requests);
4222
4223 assert_kernel_context_is_current(dev_priv);
4224 i915_gem_context_lost(dev_priv);
4225 mutex_unlock(&dev->struct_mutex);
4226
4227 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4228 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4229 flush_delayed_work(&dev_priv->gt.idle_work);
4230 flush_work(&dev_priv->mm.free_work);
4231
4232 /* Assert that we sucessfully flushed all the work and
4233 * reset the GPU back to its idle, low power state.
4234 */
4235 WARN_ON(dev_priv->gt.awake);
4236 WARN_ON(!intel_execlists_idle(dev_priv));
4237
4238 /*
4239 * Neither the BIOS, ourselves or any other kernel
4240 * expects the system to be in execlists mode on startup,
4241 * so we need to reset the GPU back to legacy mode. And the only
4242 * known way to disable logical contexts is through a GPU reset.
4243 *
4244 * So in order to leave the system in a known default configuration,
4245 * always reset the GPU upon unload and suspend. Afterwards we then
4246 * clean up the GEM state tracking, flushing off the requests and
4247 * leaving the system in a known idle state.
4248 *
4249 * Note that is of the upmost importance that the GPU is idle and
4250 * all stray writes are flushed *before* we dismantle the backing
4251 * storage for the pinned objects.
4252 *
4253 * However, since we are uncertain that resetting the GPU on older
4254 * machines is a good idea, we don't - just in case it leaves the
4255 * machine in an unusable condition.
4256 */
4257 if (HAS_HW_CONTEXTS(dev_priv)) {
4258 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
4259 WARN_ON(reset && reset != -ENODEV);
4260 }
4261
4262 return 0;
4263
4264err:
4265 mutex_unlock(&dev->struct_mutex);
4266 return ret;
4267}
4268
4269void i915_gem_resume(struct drm_device *dev)
4270{
4271 struct drm_i915_private *dev_priv = to_i915(dev);
4272
4273 WARN_ON(dev_priv->gt.awake);
4274
4275 mutex_lock(&dev->struct_mutex);
4276 i915_gem_restore_gtt_mappings(dev_priv);
4277
4278 /* As we didn't flush the kernel context before suspend, we cannot
4279 * guarantee that the context image is complete. So let's just reset
4280 * it and start again.
4281 */
4282 dev_priv->gt.resume(dev_priv);
4283
4284 mutex_unlock(&dev->struct_mutex);
4285}
4286
4287void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4288{
4289 if (INTEL_GEN(dev_priv) < 5 ||
4290 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4291 return;
4292
4293 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4294 DISP_TILE_SURFACE_SWIZZLING);
4295
4296 if (IS_GEN5(dev_priv))
4297 return;
4298
4299 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4300 if (IS_GEN6(dev_priv))
4301 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4302 else if (IS_GEN7(dev_priv))
4303 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4304 else if (IS_GEN8(dev_priv))
4305 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4306 else
4307 BUG();
4308}
4309
4310static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4311{
4312 I915_WRITE(RING_CTL(base), 0);
4313 I915_WRITE(RING_HEAD(base), 0);
4314 I915_WRITE(RING_TAIL(base), 0);
4315 I915_WRITE(RING_START(base), 0);
4316}
4317
4318static void init_unused_rings(struct drm_i915_private *dev_priv)
4319{
4320 if (IS_I830(dev_priv)) {
4321 init_unused_ring(dev_priv, PRB1_BASE);
4322 init_unused_ring(dev_priv, SRB0_BASE);
4323 init_unused_ring(dev_priv, SRB1_BASE);
4324 init_unused_ring(dev_priv, SRB2_BASE);
4325 init_unused_ring(dev_priv, SRB3_BASE);
4326 } else if (IS_GEN2(dev_priv)) {
4327 init_unused_ring(dev_priv, SRB0_BASE);
4328 init_unused_ring(dev_priv, SRB1_BASE);
4329 } else if (IS_GEN3(dev_priv)) {
4330 init_unused_ring(dev_priv, PRB1_BASE);
4331 init_unused_ring(dev_priv, PRB2_BASE);
4332 }
4333}
4334
4335int
4336i915_gem_init_hw(struct drm_device *dev)
4337{
4338 struct drm_i915_private *dev_priv = to_i915(dev);
4339 struct intel_engine_cs *engine;
4340 enum intel_engine_id id;
4341 int ret;
4342
4343 dev_priv->gt.last_init_time = ktime_get();
4344
4345 /* Double layer security blanket, see i915_gem_init() */
4346 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4347
4348 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4349 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4350
4351 if (IS_HASWELL(dev_priv))
4352 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4353 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4354
4355 if (HAS_PCH_NOP(dev_priv)) {
4356 if (IS_IVYBRIDGE(dev_priv)) {
4357 u32 temp = I915_READ(GEN7_MSG_CTL);
4358 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4359 I915_WRITE(GEN7_MSG_CTL, temp);
4360 } else if (INTEL_GEN(dev_priv) >= 7) {
4361 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4362 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4363 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4364 }
4365 }
4366
4367 i915_gem_init_swizzling(dev_priv);
4368
4369 /*
4370 * At least 830 can leave some of the unused rings
4371 * "active" (ie. head != tail) after resume which
4372 * will prevent c3 entry. Makes sure all unused rings
4373 * are totally idle.
4374 */
4375 init_unused_rings(dev_priv);
4376
4377 BUG_ON(!dev_priv->kernel_context);
4378
4379 ret = i915_ppgtt_init_hw(dev_priv);
4380 if (ret) {
4381 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4382 goto out;
4383 }
4384
4385 /* Need to do basic initialisation of all rings first: */
4386 for_each_engine(engine, dev_priv, id) {
4387 ret = engine->init_hw(engine);
4388 if (ret)
4389 goto out;
4390 }
4391
4392 intel_mocs_init_l3cc_table(dev);
4393
4394 /* We can't enable contexts until all firmware is loaded */
4395 ret = intel_guc_setup(dev);
4396 if (ret)
4397 goto out;
4398
4399out:
4400 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4401 return ret;
4402}
4403
4404bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4405{
4406 if (INTEL_INFO(dev_priv)->gen < 6)
4407 return false;
4408
4409 /* TODO: make semaphores and Execlists play nicely together */
4410 if (i915.enable_execlists)
4411 return false;
4412
4413 if (value >= 0)
4414 return value;
4415
4416#ifdef CONFIG_INTEL_IOMMU
4417 /* Enable semaphores on SNB when IO remapping is off */
4418 if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
4419 return false;
4420#endif
4421
4422 return true;
4423}
4424
4425int i915_gem_init(struct drm_device *dev)
4426{
4427 struct drm_i915_private *dev_priv = to_i915(dev);
4428 int ret;
4429
4430 mutex_lock(&dev->struct_mutex);
4431
4432 if (!i915.enable_execlists) {
4433 dev_priv->gt.resume = intel_legacy_submission_resume;
4434 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4435 } else {
4436 dev_priv->gt.resume = intel_lr_context_resume;
4437 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4438 }
4439
4440 /* This is just a security blanket to placate dragons.
4441 * On some systems, we very sporadically observe that the first TLBs
4442 * used by the CS may be stale, despite us poking the TLB reset. If
4443 * we hold the forcewake during initialisation these problems
4444 * just magically go away.
4445 */
4446 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4447
4448 i915_gem_init_userptr(dev_priv);
4449
4450 ret = i915_gem_init_ggtt(dev_priv);
4451 if (ret)
4452 goto out_unlock;
4453
4454 ret = i915_gem_context_init(dev);
4455 if (ret)
4456 goto out_unlock;
4457
4458 ret = intel_engines_init(dev);
4459 if (ret)
4460 goto out_unlock;
4461
4462 ret = i915_gem_init_hw(dev);
4463 if (ret == -EIO) {
4464 /* Allow engine initialisation to fail by marking the GPU as
4465 * wedged. But we only want to do this where the GPU is angry,
4466 * for all other failure, such as an allocation failure, bail.
4467 */
4468 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4469 i915_gem_set_wedged(dev_priv);
4470 ret = 0;
4471 }
4472
4473out_unlock:
4474 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4475 mutex_unlock(&dev->struct_mutex);
4476
4477 return ret;
4478}
4479
4480void
4481i915_gem_cleanup_engines(struct drm_device *dev)
4482{
4483 struct drm_i915_private *dev_priv = to_i915(dev);
4484 struct intel_engine_cs *engine;
4485 enum intel_engine_id id;
4486
4487 for_each_engine(engine, dev_priv, id)
4488 dev_priv->gt.cleanup_engine(engine);
4489}
4490
4491void
4492i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4493{
4494 int i;
4495
4496 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4497 !IS_CHERRYVIEW(dev_priv))
4498 dev_priv->num_fence_regs = 32;
4499 else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
4500 IS_I945GM(dev_priv) || IS_G33(dev_priv))
4501 dev_priv->num_fence_regs = 16;
4502 else
4503 dev_priv->num_fence_regs = 8;
4504
4505 if (intel_vgpu_active(dev_priv))
4506 dev_priv->num_fence_regs =
4507 I915_READ(vgtif_reg(avail_rs.fence_num));
4508
4509 /* Initialize fence registers to zero */
4510 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4511 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4512
4513 fence->i915 = dev_priv;
4514 fence->id = i;
4515 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4516 }
4517 i915_gem_restore_fences(dev_priv);
4518
4519 i915_gem_detect_bit_6_swizzle(dev_priv);
4520}
4521
4522int
4523i915_gem_load_init(struct drm_device *dev)
4524{
4525 struct drm_i915_private *dev_priv = to_i915(dev);
4526 int err = -ENOMEM;
4527
4528 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4529 if (!dev_priv->objects)
4530 goto err_out;
4531
4532 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4533 if (!dev_priv->vmas)
4534 goto err_objects;
4535
4536 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4537 SLAB_HWCACHE_ALIGN |
4538 SLAB_RECLAIM_ACCOUNT |
4539 SLAB_DESTROY_BY_RCU);
4540 if (!dev_priv->requests)
4541 goto err_vmas;
4542
4543 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4544 SLAB_HWCACHE_ALIGN |
4545 SLAB_RECLAIM_ACCOUNT);
4546 if (!dev_priv->dependencies)
4547 goto err_requests;
4548
4549 mutex_lock(&dev_priv->drm.struct_mutex);
4550 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4551 err = i915_gem_timeline_init__global(dev_priv);
4552 mutex_unlock(&dev_priv->drm.struct_mutex);
4553 if (err)
4554 goto err_dependencies;
4555
4556 INIT_LIST_HEAD(&dev_priv->context_list);
4557 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4558 init_llist_head(&dev_priv->mm.free_list);
4559 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4560 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4561 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4562 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4563 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4564 i915_gem_retire_work_handler);
4565 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4566 i915_gem_idle_work_handler);
4567 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4568 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4569
4570 init_waitqueue_head(&dev_priv->pending_flip_queue);
4571
4572 dev_priv->mm.interruptible = true;
4573
4574 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4575
4576 spin_lock_init(&dev_priv->fb_tracking.lock);
4577
4578 return 0;
4579
4580err_dependencies:
4581 kmem_cache_destroy(dev_priv->dependencies);
4582err_requests:
4583 kmem_cache_destroy(dev_priv->requests);
4584err_vmas:
4585 kmem_cache_destroy(dev_priv->vmas);
4586err_objects:
4587 kmem_cache_destroy(dev_priv->objects);
4588err_out:
4589 return err;
4590}
4591
4592void i915_gem_load_cleanup(struct drm_device *dev)
4593{
4594 struct drm_i915_private *dev_priv = to_i915(dev);
4595
4596 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4597
4598 mutex_lock(&dev_priv->drm.struct_mutex);
4599 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4600 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4601 mutex_unlock(&dev_priv->drm.struct_mutex);
4602
4603 kmem_cache_destroy(dev_priv->dependencies);
4604 kmem_cache_destroy(dev_priv->requests);
4605 kmem_cache_destroy(dev_priv->vmas);
4606 kmem_cache_destroy(dev_priv->objects);
4607
4608 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4609 rcu_barrier();
4610}
4611
4612int i915_gem_freeze(struct drm_i915_private *dev_priv)
4613{
4614 intel_runtime_pm_get(dev_priv);
4615
4616 mutex_lock(&dev_priv->drm.struct_mutex);
4617 i915_gem_shrink_all(dev_priv);
4618 mutex_unlock(&dev_priv->drm.struct_mutex);
4619
4620 intel_runtime_pm_put(dev_priv);
4621
4622 return 0;
4623}
4624
4625int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4626{
4627 struct drm_i915_gem_object *obj;
4628 struct list_head *phases[] = {
4629 &dev_priv->mm.unbound_list,
4630 &dev_priv->mm.bound_list,
4631 NULL
4632 }, **p;
4633
4634 /* Called just before we write the hibernation image.
4635 *
4636 * We need to update the domain tracking to reflect that the CPU
4637 * will be accessing all the pages to create and restore from the
4638 * hibernation, and so upon restoration those pages will be in the
4639 * CPU domain.
4640 *
4641 * To make sure the hibernation image contains the latest state,
4642 * we update that state just before writing out the image.
4643 *
4644 * To try and reduce the hibernation image, we manually shrink
4645 * the objects as well.
4646 */
4647
4648 mutex_lock(&dev_priv->drm.struct_mutex);
4649 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
4650
4651 for (p = phases; *p; p++) {
4652 list_for_each_entry(obj, *p, global_link) {
4653 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4654 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4655 }
4656 }
4657 mutex_unlock(&dev_priv->drm.struct_mutex);
4658
4659 return 0;
4660}
4661
4662void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4663{
4664 struct drm_i915_file_private *file_priv = file->driver_priv;
4665 struct drm_i915_gem_request *request;
4666
4667 /* Clean up our request list when the client is going away, so that
4668 * later retire_requests won't dereference our soon-to-be-gone
4669 * file_priv.
4670 */
4671 spin_lock(&file_priv->mm.lock);
4672 list_for_each_entry(request, &file_priv->mm.request_list, client_list)
4673 request->file_priv = NULL;
4674 spin_unlock(&file_priv->mm.lock);
4675
4676 if (!list_empty(&file_priv->rps.link)) {
4677 spin_lock(&to_i915(dev)->rps.client_lock);
4678 list_del(&file_priv->rps.link);
4679 spin_unlock(&to_i915(dev)->rps.client_lock);
4680 }
4681}
4682
4683int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4684{
4685 struct drm_i915_file_private *file_priv;
4686 int ret;
4687
4688 DRM_DEBUG("\n");
4689
4690 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4691 if (!file_priv)
4692 return -ENOMEM;
4693
4694 file->driver_priv = file_priv;
4695 file_priv->dev_priv = to_i915(dev);
4696 file_priv->file = file;
4697 INIT_LIST_HEAD(&file_priv->rps.link);
4698
4699 spin_lock_init(&file_priv->mm.lock);
4700 INIT_LIST_HEAD(&file_priv->mm.request_list);
4701
4702 file_priv->bsd_engine = -1;
4703
4704 ret = i915_gem_context_open(dev, file);
4705 if (ret)
4706 kfree(file_priv);
4707
4708 return ret;
4709}
4710
4711/**
4712 * i915_gem_track_fb - update frontbuffer tracking
4713 * @old: current GEM buffer for the frontbuffer slots
4714 * @new: new GEM buffer for the frontbuffer slots
4715 * @frontbuffer_bits: bitmask of frontbuffer slots
4716 *
4717 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4718 * from @old and setting them in @new. Both @old and @new can be NULL.
4719 */
4720void i915_gem_track_fb(struct drm_i915_gem_object *old,
4721 struct drm_i915_gem_object *new,
4722 unsigned frontbuffer_bits)
4723{
4724 /* Control of individual bits within the mask are guarded by
4725 * the owning plane->mutex, i.e. we can never see concurrent
4726 * manipulation of individual bits. But since the bitfield as a whole
4727 * is updated using RMW, we need to use atomics in order to update
4728 * the bits.
4729 */
4730 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
4731 sizeof(atomic_t) * BITS_PER_BYTE);
4732
4733 if (old) {
4734 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
4735 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
4736 }
4737
4738 if (new) {
4739 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
4740 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
4741 }
4742}
4743
4744/* Allocate a new GEM object and fill it with the supplied data */
4745struct drm_i915_gem_object *
4746i915_gem_object_create_from_data(struct drm_device *dev,
4747 const void *data, size_t size)
4748{
4749 struct drm_i915_gem_object *obj;
4750 struct sg_table *sg;
4751 size_t bytes;
4752 int ret;
4753
4754 obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE));
4755 if (IS_ERR(obj))
4756 return obj;
4757
4758 ret = i915_gem_object_set_to_cpu_domain(obj, true);
4759 if (ret)
4760 goto fail;
4761
4762 ret = i915_gem_object_pin_pages(obj);
4763 if (ret)
4764 goto fail;
4765
4766 sg = obj->mm.pages;
4767 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
4768 obj->mm.dirty = true; /* Backing store is now out of date */
4769 i915_gem_object_unpin_pages(obj);
4770
4771 if (WARN_ON(bytes != size)) {
4772 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
4773 ret = -EFAULT;
4774 goto fail;
4775 }
4776
4777 return obj;
4778
4779fail:
4780 i915_gem_object_put(obj);
4781 return ERR_PTR(ret);
4782}
4783
4784struct scatterlist *
4785i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
4786 unsigned int n,
4787 unsigned int *offset)
4788{
4789 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
4790 struct scatterlist *sg;
4791 unsigned int idx, count;
4792
4793 might_sleep();
4794 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
4795 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
4796
4797 /* As we iterate forward through the sg, we record each entry in a
4798 * radixtree for quick repeated (backwards) lookups. If we have seen
4799 * this index previously, we will have an entry for it.
4800 *
4801 * Initial lookup is O(N), but this is amortized to O(1) for
4802 * sequential page access (where each new request is consecutive
4803 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4804 * i.e. O(1) with a large constant!
4805 */
4806 if (n < READ_ONCE(iter->sg_idx))
4807 goto lookup;
4808
4809 mutex_lock(&iter->lock);
4810
4811 /* We prefer to reuse the last sg so that repeated lookup of this
4812 * (or the subsequent) sg are fast - comparing against the last
4813 * sg is faster than going through the radixtree.
4814 */
4815
4816 sg = iter->sg_pos;
4817 idx = iter->sg_idx;
4818 count = __sg_page_count(sg);
4819
4820 while (idx + count <= n) {
4821 unsigned long exception, i;
4822 int ret;
4823
4824 /* If we cannot allocate and insert this entry, or the
4825 * individual pages from this range, cancel updating the
4826 * sg_idx so that on this lookup we are forced to linearly
4827 * scan onwards, but on future lookups we will try the
4828 * insertion again (in which case we need to be careful of
4829 * the error return reporting that we have already inserted
4830 * this index).
4831 */
4832 ret = radix_tree_insert(&iter->radix, idx, sg);
4833 if (ret && ret != -EEXIST)
4834 goto scan;
4835
4836 exception =
4837 RADIX_TREE_EXCEPTIONAL_ENTRY |
4838 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
4839 for (i = 1; i < count; i++) {
4840 ret = radix_tree_insert(&iter->radix, idx + i,
4841 (void *)exception);
4842 if (ret && ret != -EEXIST)
4843 goto scan;
4844 }
4845
4846 idx += count;
4847 sg = ____sg_next(sg);
4848 count = __sg_page_count(sg);
4849 }
4850
4851scan:
4852 iter->sg_pos = sg;
4853 iter->sg_idx = idx;
4854
4855 mutex_unlock(&iter->lock);
4856
4857 if (unlikely(n < idx)) /* insertion completed by another thread */
4858 goto lookup;
4859
4860 /* In case we failed to insert the entry into the radixtree, we need
4861 * to look beyond the current sg.
4862 */
4863 while (idx + count <= n) {
4864 idx += count;
4865 sg = ____sg_next(sg);
4866 count = __sg_page_count(sg);
4867 }
4868
4869 *offset = n - idx;
4870 return sg;
4871
4872lookup:
4873 rcu_read_lock();
4874
4875 sg = radix_tree_lookup(&iter->radix, n);
4876 GEM_BUG_ON(!sg);
4877
4878 /* If this index is in the middle of multi-page sg entry,
4879 * the radixtree will contain an exceptional entry that points
4880 * to the start of that range. We will return the pointer to
4881 * the base page and the offset of this page within the
4882 * sg entry's range.
4883 */
4884 *offset = 0;
4885 if (unlikely(radix_tree_exception(sg))) {
4886 unsigned long base =
4887 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
4888
4889 sg = radix_tree_lookup(&iter->radix, base);
4890 GEM_BUG_ON(!sg);
4891
4892 *offset = n - base;
4893 }
4894
4895 rcu_read_unlock();
4896
4897 return sg;
4898}
4899
4900struct page *
4901i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
4902{
4903 struct scatterlist *sg;
4904 unsigned int offset;
4905
4906 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
4907
4908 sg = i915_gem_object_get_sg(obj, n, &offset);
4909 return nth_page(sg_page(sg), offset);
4910}
4911
4912/* Like i915_gem_object_get_page(), but mark the returned page dirty */
4913struct page *
4914i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
4915 unsigned int n)
4916{
4917 struct page *page;
4918
4919 page = i915_gem_object_get_page(obj, n);
4920 if (!obj->mm.dirty)
4921 set_page_dirty(page);
4922
4923 return page;
4924}
4925
4926dma_addr_t
4927i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
4928 unsigned long n)
4929{
4930 struct scatterlist *sg;
4931 unsigned int offset;
4932
4933 sg = i915_gem_object_get_sg(obj, n, &offset);
4934 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
4935}