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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32#include "i915_trace.h"
33#include "intel_drv.h"
34#include <linux/shmem_fs.h>
35#include <linux/slab.h>
36#include <linux/swap.h>
37#include <linux/pci.h>
38
39static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
40static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
42static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
43 bool write);
44static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
45 uint64_t offset,
46 uint64_t size);
47static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
48static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
49 unsigned alignment,
50 bool map_and_fenceable);
51static void i915_gem_clear_fence_reg(struct drm_device *dev,
52 struct drm_i915_fence_reg *reg);
53static int i915_gem_phys_pwrite(struct drm_device *dev,
54 struct drm_i915_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file);
57static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
58
59static int i915_gem_inactive_shrink(struct shrinker *shrinker,
60 struct shrink_control *sc);
61
62/* some bookkeeping */
63static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
64 size_t size)
65{
66 dev_priv->mm.object_count++;
67 dev_priv->mm.object_memory += size;
68}
69
70static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
71 size_t size)
72{
73 dev_priv->mm.object_count--;
74 dev_priv->mm.object_memory -= size;
75}
76
77static int
78i915_gem_wait_for_error(struct drm_device *dev)
79{
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct completion *x = &dev_priv->error_completion;
82 unsigned long flags;
83 int ret;
84
85 if (!atomic_read(&dev_priv->mm.wedged))
86 return 0;
87
88 ret = wait_for_completion_interruptible(x);
89 if (ret)
90 return ret;
91
92 if (atomic_read(&dev_priv->mm.wedged)) {
93 /* GPU is hung, bump the completion count to account for
94 * the token we just consumed so that we never hit zero and
95 * end up waiting upon a subsequent completion event that
96 * will never happen.
97 */
98 spin_lock_irqsave(&x->wait.lock, flags);
99 x->done++;
100 spin_unlock_irqrestore(&x->wait.lock, flags);
101 }
102 return 0;
103}
104
105int i915_mutex_lock_interruptible(struct drm_device *dev)
106{
107 int ret;
108
109 ret = i915_gem_wait_for_error(dev);
110 if (ret)
111 return ret;
112
113 ret = mutex_lock_interruptible(&dev->struct_mutex);
114 if (ret)
115 return ret;
116
117 WARN_ON(i915_verify_lists(dev));
118 return 0;
119}
120
121static inline bool
122i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
123{
124 return obj->gtt_space && !obj->active && obj->pin_count == 0;
125}
126
127void i915_gem_do_init(struct drm_device *dev,
128 unsigned long start,
129 unsigned long mappable_end,
130 unsigned long end)
131{
132 drm_i915_private_t *dev_priv = dev->dev_private;
133
134 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
135
136 dev_priv->mm.gtt_start = start;
137 dev_priv->mm.gtt_mappable_end = mappable_end;
138 dev_priv->mm.gtt_end = end;
139 dev_priv->mm.gtt_total = end - start;
140 dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
141
142 /* Take over this portion of the GTT */
143 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
144}
145
146int
147i915_gem_init_ioctl(struct drm_device *dev, void *data,
148 struct drm_file *file)
149{
150 struct drm_i915_gem_init *args = data;
151
152 if (args->gtt_start >= args->gtt_end ||
153 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
154 return -EINVAL;
155
156 mutex_lock(&dev->struct_mutex);
157 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
158 mutex_unlock(&dev->struct_mutex);
159
160 return 0;
161}
162
163int
164i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
166{
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_get_aperture *args = data;
169 struct drm_i915_gem_object *obj;
170 size_t pinned;
171
172 if (!(dev->driver->driver_features & DRIVER_GEM))
173 return -ENODEV;
174
175 pinned = 0;
176 mutex_lock(&dev->struct_mutex);
177 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
178 pinned += obj->gtt_space->size;
179 mutex_unlock(&dev->struct_mutex);
180
181 args->aper_size = dev_priv->mm.gtt_total;
182 args->aper_available_size = args->aper_size -pinned;
183
184 return 0;
185}
186
187static int
188i915_gem_create(struct drm_file *file,
189 struct drm_device *dev,
190 uint64_t size,
191 uint32_t *handle_p)
192{
193 struct drm_i915_gem_object *obj;
194 int ret;
195 u32 handle;
196
197 size = roundup(size, PAGE_SIZE);
198
199 /* Allocate the new object */
200 obj = i915_gem_alloc_object(dev, size);
201 if (obj == NULL)
202 return -ENOMEM;
203
204 ret = drm_gem_handle_create(file, &obj->base, &handle);
205 if (ret) {
206 drm_gem_object_release(&obj->base);
207 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
208 kfree(obj);
209 return ret;
210 }
211
212 /* drop reference from allocate - handle holds it now */
213 drm_gem_object_unreference(&obj->base);
214 trace_i915_gem_object_create(obj);
215
216 *handle_p = handle;
217 return 0;
218}
219
220int
221i915_gem_dumb_create(struct drm_file *file,
222 struct drm_device *dev,
223 struct drm_mode_create_dumb *args)
224{
225 /* have to work out size/pitch and return them */
226 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
227 args->size = args->pitch * args->height;
228 return i915_gem_create(file, dev,
229 args->size, &args->handle);
230}
231
232int i915_gem_dumb_destroy(struct drm_file *file,
233 struct drm_device *dev,
234 uint32_t handle)
235{
236 return drm_gem_handle_delete(file, handle);
237}
238
239/**
240 * Creates a new mm object and returns a handle to it.
241 */
242int
243i915_gem_create_ioctl(struct drm_device *dev, void *data,
244 struct drm_file *file)
245{
246 struct drm_i915_gem_create *args = data;
247 return i915_gem_create(file, dev,
248 args->size, &args->handle);
249}
250
251static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
252{
253 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
254
255 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
256 obj->tiling_mode != I915_TILING_NONE;
257}
258
259static inline void
260slow_shmem_copy(struct page *dst_page,
261 int dst_offset,
262 struct page *src_page,
263 int src_offset,
264 int length)
265{
266 char *dst_vaddr, *src_vaddr;
267
268 dst_vaddr = kmap(dst_page);
269 src_vaddr = kmap(src_page);
270
271 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
272
273 kunmap(src_page);
274 kunmap(dst_page);
275}
276
277static inline void
278slow_shmem_bit17_copy(struct page *gpu_page,
279 int gpu_offset,
280 struct page *cpu_page,
281 int cpu_offset,
282 int length,
283 int is_read)
284{
285 char *gpu_vaddr, *cpu_vaddr;
286
287 /* Use the unswizzled path if this page isn't affected. */
288 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
289 if (is_read)
290 return slow_shmem_copy(cpu_page, cpu_offset,
291 gpu_page, gpu_offset, length);
292 else
293 return slow_shmem_copy(gpu_page, gpu_offset,
294 cpu_page, cpu_offset, length);
295 }
296
297 gpu_vaddr = kmap(gpu_page);
298 cpu_vaddr = kmap(cpu_page);
299
300 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
301 * XORing with the other bits (A9 for Y, A9 and A10 for X)
302 */
303 while (length > 0) {
304 int cacheline_end = ALIGN(gpu_offset + 1, 64);
305 int this_length = min(cacheline_end - gpu_offset, length);
306 int swizzled_gpu_offset = gpu_offset ^ 64;
307
308 if (is_read) {
309 memcpy(cpu_vaddr + cpu_offset,
310 gpu_vaddr + swizzled_gpu_offset,
311 this_length);
312 } else {
313 memcpy(gpu_vaddr + swizzled_gpu_offset,
314 cpu_vaddr + cpu_offset,
315 this_length);
316 }
317 cpu_offset += this_length;
318 gpu_offset += this_length;
319 length -= this_length;
320 }
321
322 kunmap(cpu_page);
323 kunmap(gpu_page);
324}
325
326/**
327 * This is the fast shmem pread path, which attempts to copy_from_user directly
328 * from the backing pages of the object to the user's address space. On a
329 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
330 */
331static int
332i915_gem_shmem_pread_fast(struct drm_device *dev,
333 struct drm_i915_gem_object *obj,
334 struct drm_i915_gem_pread *args,
335 struct drm_file *file)
336{
337 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
338 ssize_t remain;
339 loff_t offset;
340 char __user *user_data;
341 int page_offset, page_length;
342
343 user_data = (char __user *) (uintptr_t) args->data_ptr;
344 remain = args->size;
345
346 offset = args->offset;
347
348 while (remain > 0) {
349 struct page *page;
350 char *vaddr;
351 int ret;
352
353 /* Operation in this page
354 *
355 * page_offset = offset within page
356 * page_length = bytes to copy for this page
357 */
358 page_offset = offset_in_page(offset);
359 page_length = remain;
360 if ((page_offset + remain) > PAGE_SIZE)
361 page_length = PAGE_SIZE - page_offset;
362
363 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
364 if (IS_ERR(page))
365 return PTR_ERR(page);
366
367 vaddr = kmap_atomic(page);
368 ret = __copy_to_user_inatomic(user_data,
369 vaddr + page_offset,
370 page_length);
371 kunmap_atomic(vaddr);
372
373 mark_page_accessed(page);
374 page_cache_release(page);
375 if (ret)
376 return -EFAULT;
377
378 remain -= page_length;
379 user_data += page_length;
380 offset += page_length;
381 }
382
383 return 0;
384}
385
386/**
387 * This is the fallback shmem pread path, which allocates temporary storage
388 * in kernel space to copy_to_user into outside of the struct_mutex, so we
389 * can copy out of the object's backing pages while holding the struct mutex
390 * and not take page faults.
391 */
392static int
393i915_gem_shmem_pread_slow(struct drm_device *dev,
394 struct drm_i915_gem_object *obj,
395 struct drm_i915_gem_pread *args,
396 struct drm_file *file)
397{
398 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
399 struct mm_struct *mm = current->mm;
400 struct page **user_pages;
401 ssize_t remain;
402 loff_t offset, pinned_pages, i;
403 loff_t first_data_page, last_data_page, num_pages;
404 int shmem_page_offset;
405 int data_page_index, data_page_offset;
406 int page_length;
407 int ret;
408 uint64_t data_ptr = args->data_ptr;
409 int do_bit17_swizzling;
410
411 remain = args->size;
412
413 /* Pin the user pages containing the data. We can't fault while
414 * holding the struct mutex, yet we want to hold it while
415 * dereferencing the user data.
416 */
417 first_data_page = data_ptr / PAGE_SIZE;
418 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
419 num_pages = last_data_page - first_data_page + 1;
420
421 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
422 if (user_pages == NULL)
423 return -ENOMEM;
424
425 mutex_unlock(&dev->struct_mutex);
426 down_read(&mm->mmap_sem);
427 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
428 num_pages, 1, 0, user_pages, NULL);
429 up_read(&mm->mmap_sem);
430 mutex_lock(&dev->struct_mutex);
431 if (pinned_pages < num_pages) {
432 ret = -EFAULT;
433 goto out;
434 }
435
436 ret = i915_gem_object_set_cpu_read_domain_range(obj,
437 args->offset,
438 args->size);
439 if (ret)
440 goto out;
441
442 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
443
444 offset = args->offset;
445
446 while (remain > 0) {
447 struct page *page;
448
449 /* Operation in this page
450 *
451 * shmem_page_offset = offset within page in shmem file
452 * data_page_index = page number in get_user_pages return
453 * data_page_offset = offset with data_page_index page.
454 * page_length = bytes to copy for this page
455 */
456 shmem_page_offset = offset_in_page(offset);
457 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
458 data_page_offset = offset_in_page(data_ptr);
459
460 page_length = remain;
461 if ((shmem_page_offset + page_length) > PAGE_SIZE)
462 page_length = PAGE_SIZE - shmem_page_offset;
463 if ((data_page_offset + page_length) > PAGE_SIZE)
464 page_length = PAGE_SIZE - data_page_offset;
465
466 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
467 if (IS_ERR(page)) {
468 ret = PTR_ERR(page);
469 goto out;
470 }
471
472 if (do_bit17_swizzling) {
473 slow_shmem_bit17_copy(page,
474 shmem_page_offset,
475 user_pages[data_page_index],
476 data_page_offset,
477 page_length,
478 1);
479 } else {
480 slow_shmem_copy(user_pages[data_page_index],
481 data_page_offset,
482 page,
483 shmem_page_offset,
484 page_length);
485 }
486
487 mark_page_accessed(page);
488 page_cache_release(page);
489
490 remain -= page_length;
491 data_ptr += page_length;
492 offset += page_length;
493 }
494
495out:
496 for (i = 0; i < pinned_pages; i++) {
497 SetPageDirty(user_pages[i]);
498 mark_page_accessed(user_pages[i]);
499 page_cache_release(user_pages[i]);
500 }
501 drm_free_large(user_pages);
502
503 return ret;
504}
505
506/**
507 * Reads data from the object referenced by handle.
508 *
509 * On error, the contents of *data are undefined.
510 */
511int
512i915_gem_pread_ioctl(struct drm_device *dev, void *data,
513 struct drm_file *file)
514{
515 struct drm_i915_gem_pread *args = data;
516 struct drm_i915_gem_object *obj;
517 int ret = 0;
518
519 if (args->size == 0)
520 return 0;
521
522 if (!access_ok(VERIFY_WRITE,
523 (char __user *)(uintptr_t)args->data_ptr,
524 args->size))
525 return -EFAULT;
526
527 ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
528 args->size);
529 if (ret)
530 return -EFAULT;
531
532 ret = i915_mutex_lock_interruptible(dev);
533 if (ret)
534 return ret;
535
536 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
537 if (&obj->base == NULL) {
538 ret = -ENOENT;
539 goto unlock;
540 }
541
542 /* Bounds check source. */
543 if (args->offset > obj->base.size ||
544 args->size > obj->base.size - args->offset) {
545 ret = -EINVAL;
546 goto out;
547 }
548
549 trace_i915_gem_object_pread(obj, args->offset, args->size);
550
551 ret = i915_gem_object_set_cpu_read_domain_range(obj,
552 args->offset,
553 args->size);
554 if (ret)
555 goto out;
556
557 ret = -EFAULT;
558 if (!i915_gem_object_needs_bit17_swizzle(obj))
559 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
560 if (ret == -EFAULT)
561 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
562
563out:
564 drm_gem_object_unreference(&obj->base);
565unlock:
566 mutex_unlock(&dev->struct_mutex);
567 return ret;
568}
569
570/* This is the fast write path which cannot handle
571 * page faults in the source data
572 */
573
574static inline int
575fast_user_write(struct io_mapping *mapping,
576 loff_t page_base, int page_offset,
577 char __user *user_data,
578 int length)
579{
580 char *vaddr_atomic;
581 unsigned long unwritten;
582
583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
584 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
585 user_data, length);
586 io_mapping_unmap_atomic(vaddr_atomic);
587 return unwritten;
588}
589
590/* Here's the write path which can sleep for
591 * page faults
592 */
593
594static inline void
595slow_kernel_write(struct io_mapping *mapping,
596 loff_t gtt_base, int gtt_offset,
597 struct page *user_page, int user_offset,
598 int length)
599{
600 char __iomem *dst_vaddr;
601 char *src_vaddr;
602
603 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
604 src_vaddr = kmap(user_page);
605
606 memcpy_toio(dst_vaddr + gtt_offset,
607 src_vaddr + user_offset,
608 length);
609
610 kunmap(user_page);
611 io_mapping_unmap(dst_vaddr);
612}
613
614/**
615 * This is the fast pwrite path, where we copy the data directly from the
616 * user into the GTT, uncached.
617 */
618static int
619i915_gem_gtt_pwrite_fast(struct drm_device *dev,
620 struct drm_i915_gem_object *obj,
621 struct drm_i915_gem_pwrite *args,
622 struct drm_file *file)
623{
624 drm_i915_private_t *dev_priv = dev->dev_private;
625 ssize_t remain;
626 loff_t offset, page_base;
627 char __user *user_data;
628 int page_offset, page_length;
629
630 user_data = (char __user *) (uintptr_t) args->data_ptr;
631 remain = args->size;
632
633 offset = obj->gtt_offset + args->offset;
634
635 while (remain > 0) {
636 /* Operation in this page
637 *
638 * page_base = page offset within aperture
639 * page_offset = offset within page
640 * page_length = bytes to copy for this page
641 */
642 page_base = offset & PAGE_MASK;
643 page_offset = offset_in_page(offset);
644 page_length = remain;
645 if ((page_offset + remain) > PAGE_SIZE)
646 page_length = PAGE_SIZE - page_offset;
647
648 /* If we get a fault while copying data, then (presumably) our
649 * source page isn't available. Return the error and we'll
650 * retry in the slow path.
651 */
652 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
653 page_offset, user_data, page_length))
654 return -EFAULT;
655
656 remain -= page_length;
657 user_data += page_length;
658 offset += page_length;
659 }
660
661 return 0;
662}
663
664/**
665 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
666 * the memory and maps it using kmap_atomic for copying.
667 *
668 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
669 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
670 */
671static int
672i915_gem_gtt_pwrite_slow(struct drm_device *dev,
673 struct drm_i915_gem_object *obj,
674 struct drm_i915_gem_pwrite *args,
675 struct drm_file *file)
676{
677 drm_i915_private_t *dev_priv = dev->dev_private;
678 ssize_t remain;
679 loff_t gtt_page_base, offset;
680 loff_t first_data_page, last_data_page, num_pages;
681 loff_t pinned_pages, i;
682 struct page **user_pages;
683 struct mm_struct *mm = current->mm;
684 int gtt_page_offset, data_page_offset, data_page_index, page_length;
685 int ret;
686 uint64_t data_ptr = args->data_ptr;
687
688 remain = args->size;
689
690 /* Pin the user pages containing the data. We can't fault while
691 * holding the struct mutex, and all of the pwrite implementations
692 * want to hold it while dereferencing the user data.
693 */
694 first_data_page = data_ptr / PAGE_SIZE;
695 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
696 num_pages = last_data_page - first_data_page + 1;
697
698 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
699 if (user_pages == NULL)
700 return -ENOMEM;
701
702 mutex_unlock(&dev->struct_mutex);
703 down_read(&mm->mmap_sem);
704 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
705 num_pages, 0, 0, user_pages, NULL);
706 up_read(&mm->mmap_sem);
707 mutex_lock(&dev->struct_mutex);
708 if (pinned_pages < num_pages) {
709 ret = -EFAULT;
710 goto out_unpin_pages;
711 }
712
713 ret = i915_gem_object_set_to_gtt_domain(obj, true);
714 if (ret)
715 goto out_unpin_pages;
716
717 ret = i915_gem_object_put_fence(obj);
718 if (ret)
719 goto out_unpin_pages;
720
721 offset = obj->gtt_offset + args->offset;
722
723 while (remain > 0) {
724 /* Operation in this page
725 *
726 * gtt_page_base = page offset within aperture
727 * gtt_page_offset = offset within page in aperture
728 * data_page_index = page number in get_user_pages return
729 * data_page_offset = offset with data_page_index page.
730 * page_length = bytes to copy for this page
731 */
732 gtt_page_base = offset & PAGE_MASK;
733 gtt_page_offset = offset_in_page(offset);
734 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
735 data_page_offset = offset_in_page(data_ptr);
736
737 page_length = remain;
738 if ((gtt_page_offset + page_length) > PAGE_SIZE)
739 page_length = PAGE_SIZE - gtt_page_offset;
740 if ((data_page_offset + page_length) > PAGE_SIZE)
741 page_length = PAGE_SIZE - data_page_offset;
742
743 slow_kernel_write(dev_priv->mm.gtt_mapping,
744 gtt_page_base, gtt_page_offset,
745 user_pages[data_page_index],
746 data_page_offset,
747 page_length);
748
749 remain -= page_length;
750 offset += page_length;
751 data_ptr += page_length;
752 }
753
754out_unpin_pages:
755 for (i = 0; i < pinned_pages; i++)
756 page_cache_release(user_pages[i]);
757 drm_free_large(user_pages);
758
759 return ret;
760}
761
762/**
763 * This is the fast shmem pwrite path, which attempts to directly
764 * copy_from_user into the kmapped pages backing the object.
765 */
766static int
767i915_gem_shmem_pwrite_fast(struct drm_device *dev,
768 struct drm_i915_gem_object *obj,
769 struct drm_i915_gem_pwrite *args,
770 struct drm_file *file)
771{
772 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
773 ssize_t remain;
774 loff_t offset;
775 char __user *user_data;
776 int page_offset, page_length;
777
778 user_data = (char __user *) (uintptr_t) args->data_ptr;
779 remain = args->size;
780
781 offset = args->offset;
782 obj->dirty = 1;
783
784 while (remain > 0) {
785 struct page *page;
786 char *vaddr;
787 int ret;
788
789 /* Operation in this page
790 *
791 * page_offset = offset within page
792 * page_length = bytes to copy for this page
793 */
794 page_offset = offset_in_page(offset);
795 page_length = remain;
796 if ((page_offset + remain) > PAGE_SIZE)
797 page_length = PAGE_SIZE - page_offset;
798
799 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
800 if (IS_ERR(page))
801 return PTR_ERR(page);
802
803 vaddr = kmap_atomic(page, KM_USER0);
804 ret = __copy_from_user_inatomic(vaddr + page_offset,
805 user_data,
806 page_length);
807 kunmap_atomic(vaddr, KM_USER0);
808
809 set_page_dirty(page);
810 mark_page_accessed(page);
811 page_cache_release(page);
812
813 /* If we get a fault while copying data, then (presumably) our
814 * source page isn't available. Return the error and we'll
815 * retry in the slow path.
816 */
817 if (ret)
818 return -EFAULT;
819
820 remain -= page_length;
821 user_data += page_length;
822 offset += page_length;
823 }
824
825 return 0;
826}
827
828/**
829 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
830 * the memory and maps it using kmap_atomic for copying.
831 *
832 * This avoids taking mmap_sem for faulting on the user's address while the
833 * struct_mutex is held.
834 */
835static int
836i915_gem_shmem_pwrite_slow(struct drm_device *dev,
837 struct drm_i915_gem_object *obj,
838 struct drm_i915_gem_pwrite *args,
839 struct drm_file *file)
840{
841 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
842 struct mm_struct *mm = current->mm;
843 struct page **user_pages;
844 ssize_t remain;
845 loff_t offset, pinned_pages, i;
846 loff_t first_data_page, last_data_page, num_pages;
847 int shmem_page_offset;
848 int data_page_index, data_page_offset;
849 int page_length;
850 int ret;
851 uint64_t data_ptr = args->data_ptr;
852 int do_bit17_swizzling;
853
854 remain = args->size;
855
856 /* Pin the user pages containing the data. We can't fault while
857 * holding the struct mutex, and all of the pwrite implementations
858 * want to hold it while dereferencing the user data.
859 */
860 first_data_page = data_ptr / PAGE_SIZE;
861 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
862 num_pages = last_data_page - first_data_page + 1;
863
864 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
865 if (user_pages == NULL)
866 return -ENOMEM;
867
868 mutex_unlock(&dev->struct_mutex);
869 down_read(&mm->mmap_sem);
870 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
871 num_pages, 0, 0, user_pages, NULL);
872 up_read(&mm->mmap_sem);
873 mutex_lock(&dev->struct_mutex);
874 if (pinned_pages < num_pages) {
875 ret = -EFAULT;
876 goto out;
877 }
878
879 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
880 if (ret)
881 goto out;
882
883 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
884
885 offset = args->offset;
886 obj->dirty = 1;
887
888 while (remain > 0) {
889 struct page *page;
890
891 /* Operation in this page
892 *
893 * shmem_page_offset = offset within page in shmem file
894 * data_page_index = page number in get_user_pages return
895 * data_page_offset = offset with data_page_index page.
896 * page_length = bytes to copy for this page
897 */
898 shmem_page_offset = offset_in_page(offset);
899 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
900 data_page_offset = offset_in_page(data_ptr);
901
902 page_length = remain;
903 if ((shmem_page_offset + page_length) > PAGE_SIZE)
904 page_length = PAGE_SIZE - shmem_page_offset;
905 if ((data_page_offset + page_length) > PAGE_SIZE)
906 page_length = PAGE_SIZE - data_page_offset;
907
908 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
909 if (IS_ERR(page)) {
910 ret = PTR_ERR(page);
911 goto out;
912 }
913
914 if (do_bit17_swizzling) {
915 slow_shmem_bit17_copy(page,
916 shmem_page_offset,
917 user_pages[data_page_index],
918 data_page_offset,
919 page_length,
920 0);
921 } else {
922 slow_shmem_copy(page,
923 shmem_page_offset,
924 user_pages[data_page_index],
925 data_page_offset,
926 page_length);
927 }
928
929 set_page_dirty(page);
930 mark_page_accessed(page);
931 page_cache_release(page);
932
933 remain -= page_length;
934 data_ptr += page_length;
935 offset += page_length;
936 }
937
938out:
939 for (i = 0; i < pinned_pages; i++)
940 page_cache_release(user_pages[i]);
941 drm_free_large(user_pages);
942
943 return ret;
944}
945
946/**
947 * Writes data to the object referenced by handle.
948 *
949 * On error, the contents of the buffer that were to be modified are undefined.
950 */
951int
952i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
953 struct drm_file *file)
954{
955 struct drm_i915_gem_pwrite *args = data;
956 struct drm_i915_gem_object *obj;
957 int ret;
958
959 if (args->size == 0)
960 return 0;
961
962 if (!access_ok(VERIFY_READ,
963 (char __user *)(uintptr_t)args->data_ptr,
964 args->size))
965 return -EFAULT;
966
967 ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
968 args->size);
969 if (ret)
970 return -EFAULT;
971
972 ret = i915_mutex_lock_interruptible(dev);
973 if (ret)
974 return ret;
975
976 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
977 if (&obj->base == NULL) {
978 ret = -ENOENT;
979 goto unlock;
980 }
981
982 /* Bounds check destination. */
983 if (args->offset > obj->base.size ||
984 args->size > obj->base.size - args->offset) {
985 ret = -EINVAL;
986 goto out;
987 }
988
989 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
990
991 /* We can only do the GTT pwrite on untiled buffers, as otherwise
992 * it would end up going through the fenced access, and we'll get
993 * different detiling behavior between reading and writing.
994 * pread/pwrite currently are reading and writing from the CPU
995 * perspective, requiring manual detiling by the client.
996 */
997 if (obj->phys_obj)
998 ret = i915_gem_phys_pwrite(dev, obj, args, file);
999 else if (obj->gtt_space &&
1000 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1001 ret = i915_gem_object_pin(obj, 0, true);
1002 if (ret)
1003 goto out;
1004
1005 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1006 if (ret)
1007 goto out_unpin;
1008
1009 ret = i915_gem_object_put_fence(obj);
1010 if (ret)
1011 goto out_unpin;
1012
1013 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1014 if (ret == -EFAULT)
1015 ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1016
1017out_unpin:
1018 i915_gem_object_unpin(obj);
1019 } else {
1020 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1021 if (ret)
1022 goto out;
1023
1024 ret = -EFAULT;
1025 if (!i915_gem_object_needs_bit17_swizzle(obj))
1026 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1027 if (ret == -EFAULT)
1028 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1029 }
1030
1031out:
1032 drm_gem_object_unreference(&obj->base);
1033unlock:
1034 mutex_unlock(&dev->struct_mutex);
1035 return ret;
1036}
1037
1038/**
1039 * Called when user space prepares to use an object with the CPU, either
1040 * through the mmap ioctl's mapping or a GTT mapping.
1041 */
1042int
1043i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1044 struct drm_file *file)
1045{
1046 struct drm_i915_gem_set_domain *args = data;
1047 struct drm_i915_gem_object *obj;
1048 uint32_t read_domains = args->read_domains;
1049 uint32_t write_domain = args->write_domain;
1050 int ret;
1051
1052 if (!(dev->driver->driver_features & DRIVER_GEM))
1053 return -ENODEV;
1054
1055 /* Only handle setting domains to types used by the CPU. */
1056 if (write_domain & I915_GEM_GPU_DOMAINS)
1057 return -EINVAL;
1058
1059 if (read_domains & I915_GEM_GPU_DOMAINS)
1060 return -EINVAL;
1061
1062 /* Having something in the write domain implies it's in the read
1063 * domain, and only that read domain. Enforce that in the request.
1064 */
1065 if (write_domain != 0 && read_domains != write_domain)
1066 return -EINVAL;
1067
1068 ret = i915_mutex_lock_interruptible(dev);
1069 if (ret)
1070 return ret;
1071
1072 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1073 if (&obj->base == NULL) {
1074 ret = -ENOENT;
1075 goto unlock;
1076 }
1077
1078 if (read_domains & I915_GEM_DOMAIN_GTT) {
1079 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1080
1081 /* Silently promote "you're not bound, there was nothing to do"
1082 * to success, since the client was just asking us to
1083 * make sure everything was done.
1084 */
1085 if (ret == -EINVAL)
1086 ret = 0;
1087 } else {
1088 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1089 }
1090
1091 drm_gem_object_unreference(&obj->base);
1092unlock:
1093 mutex_unlock(&dev->struct_mutex);
1094 return ret;
1095}
1096
1097/**
1098 * Called when user space has done writes to this buffer
1099 */
1100int
1101i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1102 struct drm_file *file)
1103{
1104 struct drm_i915_gem_sw_finish *args = data;
1105 struct drm_i915_gem_object *obj;
1106 int ret = 0;
1107
1108 if (!(dev->driver->driver_features & DRIVER_GEM))
1109 return -ENODEV;
1110
1111 ret = i915_mutex_lock_interruptible(dev);
1112 if (ret)
1113 return ret;
1114
1115 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1116 if (&obj->base == NULL) {
1117 ret = -ENOENT;
1118 goto unlock;
1119 }
1120
1121 /* Pinned buffers may be scanout, so flush the cache */
1122 if (obj->pin_count)
1123 i915_gem_object_flush_cpu_write_domain(obj);
1124
1125 drm_gem_object_unreference(&obj->base);
1126unlock:
1127 mutex_unlock(&dev->struct_mutex);
1128 return ret;
1129}
1130
1131/**
1132 * Maps the contents of an object, returning the address it is mapped
1133 * into.
1134 *
1135 * While the mapping holds a reference on the contents of the object, it doesn't
1136 * imply a ref on the object itself.
1137 */
1138int
1139i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1140 struct drm_file *file)
1141{
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143 struct drm_i915_gem_mmap *args = data;
1144 struct drm_gem_object *obj;
1145 unsigned long addr;
1146
1147 if (!(dev->driver->driver_features & DRIVER_GEM))
1148 return -ENODEV;
1149
1150 obj = drm_gem_object_lookup(dev, file, args->handle);
1151 if (obj == NULL)
1152 return -ENOENT;
1153
1154 if (obj->size > dev_priv->mm.gtt_mappable_end) {
1155 drm_gem_object_unreference_unlocked(obj);
1156 return -E2BIG;
1157 }
1158
1159 down_write(¤t->mm->mmap_sem);
1160 addr = do_mmap(obj->filp, 0, args->size,
1161 PROT_READ | PROT_WRITE, MAP_SHARED,
1162 args->offset);
1163 up_write(¤t->mm->mmap_sem);
1164 drm_gem_object_unreference_unlocked(obj);
1165 if (IS_ERR((void *)addr))
1166 return addr;
1167
1168 args->addr_ptr = (uint64_t) addr;
1169
1170 return 0;
1171}
1172
1173/**
1174 * i915_gem_fault - fault a page into the GTT
1175 * vma: VMA in question
1176 * vmf: fault info
1177 *
1178 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1179 * from userspace. The fault handler takes care of binding the object to
1180 * the GTT (if needed), allocating and programming a fence register (again,
1181 * only if needed based on whether the old reg is still valid or the object
1182 * is tiled) and inserting a new PTE into the faulting process.
1183 *
1184 * Note that the faulting process may involve evicting existing objects
1185 * from the GTT and/or fence registers to make room. So performance may
1186 * suffer if the GTT working set is large or there are few fence registers
1187 * left.
1188 */
1189int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1190{
1191 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1192 struct drm_device *dev = obj->base.dev;
1193 drm_i915_private_t *dev_priv = dev->dev_private;
1194 pgoff_t page_offset;
1195 unsigned long pfn;
1196 int ret = 0;
1197 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1198
1199 /* We don't use vmf->pgoff since that has the fake offset */
1200 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1201 PAGE_SHIFT;
1202
1203 ret = i915_mutex_lock_interruptible(dev);
1204 if (ret)
1205 goto out;
1206
1207 trace_i915_gem_object_fault(obj, page_offset, true, write);
1208
1209 /* Now bind it into the GTT if needed */
1210 if (!obj->map_and_fenceable) {
1211 ret = i915_gem_object_unbind(obj);
1212 if (ret)
1213 goto unlock;
1214 }
1215 if (!obj->gtt_space) {
1216 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1217 if (ret)
1218 goto unlock;
1219
1220 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1221 if (ret)
1222 goto unlock;
1223 }
1224
1225 if (obj->tiling_mode == I915_TILING_NONE)
1226 ret = i915_gem_object_put_fence(obj);
1227 else
1228 ret = i915_gem_object_get_fence(obj, NULL);
1229 if (ret)
1230 goto unlock;
1231
1232 if (i915_gem_object_is_inactive(obj))
1233 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1234
1235 obj->fault_mappable = true;
1236
1237 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1238 page_offset;
1239
1240 /* Finally, remap it using the new GTT offset */
1241 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1242unlock:
1243 mutex_unlock(&dev->struct_mutex);
1244out:
1245 switch (ret) {
1246 case -EIO:
1247 case -EAGAIN:
1248 /* Give the error handler a chance to run and move the
1249 * objects off the GPU active list. Next time we service the
1250 * fault, we should be able to transition the page into the
1251 * GTT without touching the GPU (and so avoid further
1252 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1253 * with coherency, just lost writes.
1254 */
1255 set_need_resched();
1256 case 0:
1257 case -ERESTARTSYS:
1258 case -EINTR:
1259 return VM_FAULT_NOPAGE;
1260 case -ENOMEM:
1261 return VM_FAULT_OOM;
1262 default:
1263 return VM_FAULT_SIGBUS;
1264 }
1265}
1266
1267/**
1268 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1269 * @obj: obj in question
1270 *
1271 * GEM memory mapping works by handing back to userspace a fake mmap offset
1272 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1273 * up the object based on the offset and sets up the various memory mapping
1274 * structures.
1275 *
1276 * This routine allocates and attaches a fake offset for @obj.
1277 */
1278static int
1279i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
1280{
1281 struct drm_device *dev = obj->base.dev;
1282 struct drm_gem_mm *mm = dev->mm_private;
1283 struct drm_map_list *list;
1284 struct drm_local_map *map;
1285 int ret = 0;
1286
1287 /* Set the object up for mmap'ing */
1288 list = &obj->base.map_list;
1289 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1290 if (!list->map)
1291 return -ENOMEM;
1292
1293 map = list->map;
1294 map->type = _DRM_GEM;
1295 map->size = obj->base.size;
1296 map->handle = obj;
1297
1298 /* Get a DRM GEM mmap offset allocated... */
1299 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1300 obj->base.size / PAGE_SIZE,
1301 0, 0);
1302 if (!list->file_offset_node) {
1303 DRM_ERROR("failed to allocate offset for bo %d\n",
1304 obj->base.name);
1305 ret = -ENOSPC;
1306 goto out_free_list;
1307 }
1308
1309 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1310 obj->base.size / PAGE_SIZE,
1311 0);
1312 if (!list->file_offset_node) {
1313 ret = -ENOMEM;
1314 goto out_free_list;
1315 }
1316
1317 list->hash.key = list->file_offset_node->start;
1318 ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1319 if (ret) {
1320 DRM_ERROR("failed to add to map hash\n");
1321 goto out_free_mm;
1322 }
1323
1324 return 0;
1325
1326out_free_mm:
1327 drm_mm_put_block(list->file_offset_node);
1328out_free_list:
1329 kfree(list->map);
1330 list->map = NULL;
1331
1332 return ret;
1333}
1334
1335/**
1336 * i915_gem_release_mmap - remove physical page mappings
1337 * @obj: obj in question
1338 *
1339 * Preserve the reservation of the mmapping with the DRM core code, but
1340 * relinquish ownership of the pages back to the system.
1341 *
1342 * It is vital that we remove the page mapping if we have mapped a tiled
1343 * object through the GTT and then lose the fence register due to
1344 * resource pressure. Similarly if the object has been moved out of the
1345 * aperture, than pages mapped into userspace must be revoked. Removing the
1346 * mapping will then trigger a page fault on the next user access, allowing
1347 * fixup by i915_gem_fault().
1348 */
1349void
1350i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1351{
1352 if (!obj->fault_mappable)
1353 return;
1354
1355 if (obj->base.dev->dev_mapping)
1356 unmap_mapping_range(obj->base.dev->dev_mapping,
1357 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1358 obj->base.size, 1);
1359
1360 obj->fault_mappable = false;
1361}
1362
1363static void
1364i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
1365{
1366 struct drm_device *dev = obj->base.dev;
1367 struct drm_gem_mm *mm = dev->mm_private;
1368 struct drm_map_list *list = &obj->base.map_list;
1369
1370 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1371 drm_mm_put_block(list->file_offset_node);
1372 kfree(list->map);
1373 list->map = NULL;
1374}
1375
1376static uint32_t
1377i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1378{
1379 uint32_t gtt_size;
1380
1381 if (INTEL_INFO(dev)->gen >= 4 ||
1382 tiling_mode == I915_TILING_NONE)
1383 return size;
1384
1385 /* Previous chips need a power-of-two fence region when tiling */
1386 if (INTEL_INFO(dev)->gen == 3)
1387 gtt_size = 1024*1024;
1388 else
1389 gtt_size = 512*1024;
1390
1391 while (gtt_size < size)
1392 gtt_size <<= 1;
1393
1394 return gtt_size;
1395}
1396
1397/**
1398 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1399 * @obj: object to check
1400 *
1401 * Return the required GTT alignment for an object, taking into account
1402 * potential fence register mapping.
1403 */
1404static uint32_t
1405i915_gem_get_gtt_alignment(struct drm_device *dev,
1406 uint32_t size,
1407 int tiling_mode)
1408{
1409 /*
1410 * Minimum alignment is 4k (GTT page size), but might be greater
1411 * if a fence register is needed for the object.
1412 */
1413 if (INTEL_INFO(dev)->gen >= 4 ||
1414 tiling_mode == I915_TILING_NONE)
1415 return 4096;
1416
1417 /*
1418 * Previous chips need to be aligned to the size of the smallest
1419 * fence register that can contain the object.
1420 */
1421 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1422}
1423
1424/**
1425 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1426 * unfenced object
1427 * @dev: the device
1428 * @size: size of the object
1429 * @tiling_mode: tiling mode of the object
1430 *
1431 * Return the required GTT alignment for an object, only taking into account
1432 * unfenced tiled surface requirements.
1433 */
1434uint32_t
1435i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1436 uint32_t size,
1437 int tiling_mode)
1438{
1439 /*
1440 * Minimum alignment is 4k (GTT page size) for sane hw.
1441 */
1442 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1443 tiling_mode == I915_TILING_NONE)
1444 return 4096;
1445
1446 /* Previous hardware however needs to be aligned to a power-of-two
1447 * tile height. The simplest method for determining this is to reuse
1448 * the power-of-tile object size.
1449 */
1450 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1451}
1452
1453int
1454i915_gem_mmap_gtt(struct drm_file *file,
1455 struct drm_device *dev,
1456 uint32_t handle,
1457 uint64_t *offset)
1458{
1459 struct drm_i915_private *dev_priv = dev->dev_private;
1460 struct drm_i915_gem_object *obj;
1461 int ret;
1462
1463 if (!(dev->driver->driver_features & DRIVER_GEM))
1464 return -ENODEV;
1465
1466 ret = i915_mutex_lock_interruptible(dev);
1467 if (ret)
1468 return ret;
1469
1470 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1471 if (&obj->base == NULL) {
1472 ret = -ENOENT;
1473 goto unlock;
1474 }
1475
1476 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1477 ret = -E2BIG;
1478 goto unlock;
1479 }
1480
1481 if (obj->madv != I915_MADV_WILLNEED) {
1482 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1483 ret = -EINVAL;
1484 goto out;
1485 }
1486
1487 if (!obj->base.map_list.map) {
1488 ret = i915_gem_create_mmap_offset(obj);
1489 if (ret)
1490 goto out;
1491 }
1492
1493 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1494
1495out:
1496 drm_gem_object_unreference(&obj->base);
1497unlock:
1498 mutex_unlock(&dev->struct_mutex);
1499 return ret;
1500}
1501
1502/**
1503 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1504 * @dev: DRM device
1505 * @data: GTT mapping ioctl data
1506 * @file: GEM object info
1507 *
1508 * Simply returns the fake offset to userspace so it can mmap it.
1509 * The mmap call will end up in drm_gem_mmap(), which will set things
1510 * up so we can get faults in the handler above.
1511 *
1512 * The fault handler will take care of binding the object into the GTT
1513 * (since it may have been evicted to make room for something), allocating
1514 * a fence register, and mapping the appropriate aperture address into
1515 * userspace.
1516 */
1517int
1518i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1519 struct drm_file *file)
1520{
1521 struct drm_i915_gem_mmap_gtt *args = data;
1522
1523 if (!(dev->driver->driver_features & DRIVER_GEM))
1524 return -ENODEV;
1525
1526 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1527}
1528
1529
1530static int
1531i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1532 gfp_t gfpmask)
1533{
1534 int page_count, i;
1535 struct address_space *mapping;
1536 struct inode *inode;
1537 struct page *page;
1538
1539 /* Get the list of pages out of our struct file. They'll be pinned
1540 * at this point until we release them.
1541 */
1542 page_count = obj->base.size / PAGE_SIZE;
1543 BUG_ON(obj->pages != NULL);
1544 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1545 if (obj->pages == NULL)
1546 return -ENOMEM;
1547
1548 inode = obj->base.filp->f_path.dentry->d_inode;
1549 mapping = inode->i_mapping;
1550 gfpmask |= mapping_gfp_mask(mapping);
1551
1552 for (i = 0; i < page_count; i++) {
1553 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1554 if (IS_ERR(page))
1555 goto err_pages;
1556
1557 obj->pages[i] = page;
1558 }
1559
1560 if (obj->tiling_mode != I915_TILING_NONE)
1561 i915_gem_object_do_bit_17_swizzle(obj);
1562
1563 return 0;
1564
1565err_pages:
1566 while (i--)
1567 page_cache_release(obj->pages[i]);
1568
1569 drm_free_large(obj->pages);
1570 obj->pages = NULL;
1571 return PTR_ERR(page);
1572}
1573
1574static void
1575i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1576{
1577 int page_count = obj->base.size / PAGE_SIZE;
1578 int i;
1579
1580 BUG_ON(obj->madv == __I915_MADV_PURGED);
1581
1582 if (obj->tiling_mode != I915_TILING_NONE)
1583 i915_gem_object_save_bit_17_swizzle(obj);
1584
1585 if (obj->madv == I915_MADV_DONTNEED)
1586 obj->dirty = 0;
1587
1588 for (i = 0; i < page_count; i++) {
1589 if (obj->dirty)
1590 set_page_dirty(obj->pages[i]);
1591
1592 if (obj->madv == I915_MADV_WILLNEED)
1593 mark_page_accessed(obj->pages[i]);
1594
1595 page_cache_release(obj->pages[i]);
1596 }
1597 obj->dirty = 0;
1598
1599 drm_free_large(obj->pages);
1600 obj->pages = NULL;
1601}
1602
1603void
1604i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1605 struct intel_ring_buffer *ring,
1606 u32 seqno)
1607{
1608 struct drm_device *dev = obj->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610
1611 BUG_ON(ring == NULL);
1612 obj->ring = ring;
1613
1614 /* Add a reference if we're newly entering the active list. */
1615 if (!obj->active) {
1616 drm_gem_object_reference(&obj->base);
1617 obj->active = 1;
1618 }
1619
1620 /* Move from whatever list we were on to the tail of execution. */
1621 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1622 list_move_tail(&obj->ring_list, &ring->active_list);
1623
1624 obj->last_rendering_seqno = seqno;
1625 if (obj->fenced_gpu_access) {
1626 struct drm_i915_fence_reg *reg;
1627
1628 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1629
1630 obj->last_fenced_seqno = seqno;
1631 obj->last_fenced_ring = ring;
1632
1633 reg = &dev_priv->fence_regs[obj->fence_reg];
1634 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
1635 }
1636}
1637
1638static void
1639i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1640{
1641 list_del_init(&obj->ring_list);
1642 obj->last_rendering_seqno = 0;
1643}
1644
1645static void
1646i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1647{
1648 struct drm_device *dev = obj->base.dev;
1649 drm_i915_private_t *dev_priv = dev->dev_private;
1650
1651 BUG_ON(!obj->active);
1652 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1653
1654 i915_gem_object_move_off_active(obj);
1655}
1656
1657static void
1658i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1659{
1660 struct drm_device *dev = obj->base.dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662
1663 if (obj->pin_count != 0)
1664 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1665 else
1666 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1667
1668 BUG_ON(!list_empty(&obj->gpu_write_list));
1669 BUG_ON(!obj->active);
1670 obj->ring = NULL;
1671
1672 i915_gem_object_move_off_active(obj);
1673 obj->fenced_gpu_access = false;
1674
1675 obj->active = 0;
1676 obj->pending_gpu_write = false;
1677 drm_gem_object_unreference(&obj->base);
1678
1679 WARN_ON(i915_verify_lists(dev));
1680}
1681
1682/* Immediately discard the backing storage */
1683static void
1684i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1685{
1686 struct inode *inode;
1687
1688 /* Our goal here is to return as much of the memory as
1689 * is possible back to the system as we are called from OOM.
1690 * To do this we must instruct the shmfs to drop all of its
1691 * backing pages, *now*.
1692 */
1693 inode = obj->base.filp->f_path.dentry->d_inode;
1694 shmem_truncate_range(inode, 0, (loff_t)-1);
1695
1696 obj->madv = __I915_MADV_PURGED;
1697}
1698
1699static inline int
1700i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1701{
1702 return obj->madv == I915_MADV_DONTNEED;
1703}
1704
1705static void
1706i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1707 uint32_t flush_domains)
1708{
1709 struct drm_i915_gem_object *obj, *next;
1710
1711 list_for_each_entry_safe(obj, next,
1712 &ring->gpu_write_list,
1713 gpu_write_list) {
1714 if (obj->base.write_domain & flush_domains) {
1715 uint32_t old_write_domain = obj->base.write_domain;
1716
1717 obj->base.write_domain = 0;
1718 list_del_init(&obj->gpu_write_list);
1719 i915_gem_object_move_to_active(obj, ring,
1720 i915_gem_next_request_seqno(ring));
1721
1722 trace_i915_gem_object_change_domain(obj,
1723 obj->base.read_domains,
1724 old_write_domain);
1725 }
1726 }
1727}
1728
1729int
1730i915_add_request(struct intel_ring_buffer *ring,
1731 struct drm_file *file,
1732 struct drm_i915_gem_request *request)
1733{
1734 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1735 uint32_t seqno;
1736 int was_empty;
1737 int ret;
1738
1739 BUG_ON(request == NULL);
1740
1741 ret = ring->add_request(ring, &seqno);
1742 if (ret)
1743 return ret;
1744
1745 trace_i915_gem_request_add(ring, seqno);
1746
1747 request->seqno = seqno;
1748 request->ring = ring;
1749 request->emitted_jiffies = jiffies;
1750 was_empty = list_empty(&ring->request_list);
1751 list_add_tail(&request->list, &ring->request_list);
1752
1753 if (file) {
1754 struct drm_i915_file_private *file_priv = file->driver_priv;
1755
1756 spin_lock(&file_priv->mm.lock);
1757 request->file_priv = file_priv;
1758 list_add_tail(&request->client_list,
1759 &file_priv->mm.request_list);
1760 spin_unlock(&file_priv->mm.lock);
1761 }
1762
1763 ring->outstanding_lazy_request = false;
1764
1765 if (!dev_priv->mm.suspended) {
1766 if (i915_enable_hangcheck) {
1767 mod_timer(&dev_priv->hangcheck_timer,
1768 jiffies +
1769 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1770 }
1771 if (was_empty)
1772 queue_delayed_work(dev_priv->wq,
1773 &dev_priv->mm.retire_work, HZ);
1774 }
1775 return 0;
1776}
1777
1778static inline void
1779i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1780{
1781 struct drm_i915_file_private *file_priv = request->file_priv;
1782
1783 if (!file_priv)
1784 return;
1785
1786 spin_lock(&file_priv->mm.lock);
1787 if (request->file_priv) {
1788 list_del(&request->client_list);
1789 request->file_priv = NULL;
1790 }
1791 spin_unlock(&file_priv->mm.lock);
1792}
1793
1794static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1795 struct intel_ring_buffer *ring)
1796{
1797 while (!list_empty(&ring->request_list)) {
1798 struct drm_i915_gem_request *request;
1799
1800 request = list_first_entry(&ring->request_list,
1801 struct drm_i915_gem_request,
1802 list);
1803
1804 list_del(&request->list);
1805 i915_gem_request_remove_from_client(request);
1806 kfree(request);
1807 }
1808
1809 while (!list_empty(&ring->active_list)) {
1810 struct drm_i915_gem_object *obj;
1811
1812 obj = list_first_entry(&ring->active_list,
1813 struct drm_i915_gem_object,
1814 ring_list);
1815
1816 obj->base.write_domain = 0;
1817 list_del_init(&obj->gpu_write_list);
1818 i915_gem_object_move_to_inactive(obj);
1819 }
1820}
1821
1822static void i915_gem_reset_fences(struct drm_device *dev)
1823{
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 int i;
1826
1827 for (i = 0; i < 16; i++) {
1828 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1829 struct drm_i915_gem_object *obj = reg->obj;
1830
1831 if (!obj)
1832 continue;
1833
1834 if (obj->tiling_mode)
1835 i915_gem_release_mmap(obj);
1836
1837 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1838 reg->obj->fenced_gpu_access = false;
1839 reg->obj->last_fenced_seqno = 0;
1840 reg->obj->last_fenced_ring = NULL;
1841 i915_gem_clear_fence_reg(dev, reg);
1842 }
1843}
1844
1845void i915_gem_reset(struct drm_device *dev)
1846{
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848 struct drm_i915_gem_object *obj;
1849 int i;
1850
1851 for (i = 0; i < I915_NUM_RINGS; i++)
1852 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
1853
1854 /* Remove anything from the flushing lists. The GPU cache is likely
1855 * to be lost on reset along with the data, so simply move the
1856 * lost bo to the inactive list.
1857 */
1858 while (!list_empty(&dev_priv->mm.flushing_list)) {
1859 obj= list_first_entry(&dev_priv->mm.flushing_list,
1860 struct drm_i915_gem_object,
1861 mm_list);
1862
1863 obj->base.write_domain = 0;
1864 list_del_init(&obj->gpu_write_list);
1865 i915_gem_object_move_to_inactive(obj);
1866 }
1867
1868 /* Move everything out of the GPU domains to ensure we do any
1869 * necessary invalidation upon reuse.
1870 */
1871 list_for_each_entry(obj,
1872 &dev_priv->mm.inactive_list,
1873 mm_list)
1874 {
1875 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1876 }
1877
1878 /* The fence registers are invalidated so clear them out */
1879 i915_gem_reset_fences(dev);
1880}
1881
1882/**
1883 * This function clears the request list as sequence numbers are passed.
1884 */
1885static void
1886i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1887{
1888 uint32_t seqno;
1889 int i;
1890
1891 if (list_empty(&ring->request_list))
1892 return;
1893
1894 WARN_ON(i915_verify_lists(ring->dev));
1895
1896 seqno = ring->get_seqno(ring);
1897
1898 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1899 if (seqno >= ring->sync_seqno[i])
1900 ring->sync_seqno[i] = 0;
1901
1902 while (!list_empty(&ring->request_list)) {
1903 struct drm_i915_gem_request *request;
1904
1905 request = list_first_entry(&ring->request_list,
1906 struct drm_i915_gem_request,
1907 list);
1908
1909 if (!i915_seqno_passed(seqno, request->seqno))
1910 break;
1911
1912 trace_i915_gem_request_retire(ring, request->seqno);
1913
1914 list_del(&request->list);
1915 i915_gem_request_remove_from_client(request);
1916 kfree(request);
1917 }
1918
1919 /* Move any buffers on the active list that are no longer referenced
1920 * by the ringbuffer to the flushing/inactive lists as appropriate.
1921 */
1922 while (!list_empty(&ring->active_list)) {
1923 struct drm_i915_gem_object *obj;
1924
1925 obj= list_first_entry(&ring->active_list,
1926 struct drm_i915_gem_object,
1927 ring_list);
1928
1929 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1930 break;
1931
1932 if (obj->base.write_domain != 0)
1933 i915_gem_object_move_to_flushing(obj);
1934 else
1935 i915_gem_object_move_to_inactive(obj);
1936 }
1937
1938 if (unlikely(ring->trace_irq_seqno &&
1939 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1940 ring->irq_put(ring);
1941 ring->trace_irq_seqno = 0;
1942 }
1943
1944 WARN_ON(i915_verify_lists(ring->dev));
1945}
1946
1947void
1948i915_gem_retire_requests(struct drm_device *dev)
1949{
1950 drm_i915_private_t *dev_priv = dev->dev_private;
1951 int i;
1952
1953 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1954 struct drm_i915_gem_object *obj, *next;
1955
1956 /* We must be careful that during unbind() we do not
1957 * accidentally infinitely recurse into retire requests.
1958 * Currently:
1959 * retire -> free -> unbind -> wait -> retire_ring
1960 */
1961 list_for_each_entry_safe(obj, next,
1962 &dev_priv->mm.deferred_free_list,
1963 mm_list)
1964 i915_gem_free_object_tail(obj);
1965 }
1966
1967 for (i = 0; i < I915_NUM_RINGS; i++)
1968 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
1969}
1970
1971static void
1972i915_gem_retire_work_handler(struct work_struct *work)
1973{
1974 drm_i915_private_t *dev_priv;
1975 struct drm_device *dev;
1976 bool idle;
1977 int i;
1978
1979 dev_priv = container_of(work, drm_i915_private_t,
1980 mm.retire_work.work);
1981 dev = dev_priv->dev;
1982
1983 /* Come back later if the device is busy... */
1984 if (!mutex_trylock(&dev->struct_mutex)) {
1985 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1986 return;
1987 }
1988
1989 i915_gem_retire_requests(dev);
1990
1991 /* Send a periodic flush down the ring so we don't hold onto GEM
1992 * objects indefinitely.
1993 */
1994 idle = true;
1995 for (i = 0; i < I915_NUM_RINGS; i++) {
1996 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1997
1998 if (!list_empty(&ring->gpu_write_list)) {
1999 struct drm_i915_gem_request *request;
2000 int ret;
2001
2002 ret = i915_gem_flush_ring(ring,
2003 0, I915_GEM_GPU_DOMAINS);
2004 request = kzalloc(sizeof(*request), GFP_KERNEL);
2005 if (ret || request == NULL ||
2006 i915_add_request(ring, NULL, request))
2007 kfree(request);
2008 }
2009
2010 idle &= list_empty(&ring->request_list);
2011 }
2012
2013 if (!dev_priv->mm.suspended && !idle)
2014 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
2015
2016 mutex_unlock(&dev->struct_mutex);
2017}
2018
2019/**
2020 * Waits for a sequence number to be signaled, and cleans up the
2021 * request and object lists appropriately for that event.
2022 */
2023int
2024i915_wait_request(struct intel_ring_buffer *ring,
2025 uint32_t seqno)
2026{
2027 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2028 u32 ier;
2029 int ret = 0;
2030
2031 BUG_ON(seqno == 0);
2032
2033 if (atomic_read(&dev_priv->mm.wedged)) {
2034 struct completion *x = &dev_priv->error_completion;
2035 bool recovery_complete;
2036 unsigned long flags;
2037
2038 /* Give the error handler a chance to run. */
2039 spin_lock_irqsave(&x->wait.lock, flags);
2040 recovery_complete = x->done > 0;
2041 spin_unlock_irqrestore(&x->wait.lock, flags);
2042
2043 return recovery_complete ? -EIO : -EAGAIN;
2044 }
2045
2046 if (seqno == ring->outstanding_lazy_request) {
2047 struct drm_i915_gem_request *request;
2048
2049 request = kzalloc(sizeof(*request), GFP_KERNEL);
2050 if (request == NULL)
2051 return -ENOMEM;
2052
2053 ret = i915_add_request(ring, NULL, request);
2054 if (ret) {
2055 kfree(request);
2056 return ret;
2057 }
2058
2059 seqno = request->seqno;
2060 }
2061
2062 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2063 if (HAS_PCH_SPLIT(ring->dev))
2064 ier = I915_READ(DEIER) | I915_READ(GTIER);
2065 else
2066 ier = I915_READ(IER);
2067 if (!ier) {
2068 DRM_ERROR("something (likely vbetool) disabled "
2069 "interrupts, re-enabling\n");
2070 ring->dev->driver->irq_preinstall(ring->dev);
2071 ring->dev->driver->irq_postinstall(ring->dev);
2072 }
2073
2074 trace_i915_gem_request_wait_begin(ring, seqno);
2075
2076 ring->waiting_seqno = seqno;
2077 if (ring->irq_get(ring)) {
2078 if (dev_priv->mm.interruptible)
2079 ret = wait_event_interruptible(ring->irq_queue,
2080 i915_seqno_passed(ring->get_seqno(ring), seqno)
2081 || atomic_read(&dev_priv->mm.wedged));
2082 else
2083 wait_event(ring->irq_queue,
2084 i915_seqno_passed(ring->get_seqno(ring), seqno)
2085 || atomic_read(&dev_priv->mm.wedged));
2086
2087 ring->irq_put(ring);
2088 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2089 seqno) ||
2090 atomic_read(&dev_priv->mm.wedged), 3000))
2091 ret = -EBUSY;
2092 ring->waiting_seqno = 0;
2093
2094 trace_i915_gem_request_wait_end(ring, seqno);
2095 }
2096 if (atomic_read(&dev_priv->mm.wedged))
2097 ret = -EAGAIN;
2098
2099 if (ret && ret != -ERESTARTSYS)
2100 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2101 __func__, ret, seqno, ring->get_seqno(ring),
2102 dev_priv->next_seqno);
2103
2104 /* Directly dispatch request retiring. While we have the work queue
2105 * to handle this, the waiter on a request often wants an associated
2106 * buffer to have made it to the inactive list, and we would need
2107 * a separate wait queue to handle that.
2108 */
2109 if (ret == 0)
2110 i915_gem_retire_requests_ring(ring);
2111
2112 return ret;
2113}
2114
2115/**
2116 * Ensures that all rendering to the object has completed and the object is
2117 * safe to unbind from the GTT or access from the CPU.
2118 */
2119int
2120i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2121{
2122 int ret;
2123
2124 /* This function only exists to support waiting for existing rendering,
2125 * not for emitting required flushes.
2126 */
2127 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
2128
2129 /* If there is rendering queued on the buffer being evicted, wait for
2130 * it.
2131 */
2132 if (obj->active) {
2133 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2134 if (ret)
2135 return ret;
2136 }
2137
2138 return 0;
2139}
2140
2141static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2142{
2143 u32 old_write_domain, old_read_domains;
2144
2145 /* Act a barrier for all accesses through the GTT */
2146 mb();
2147
2148 /* Force a pagefault for domain tracking on next user access */
2149 i915_gem_release_mmap(obj);
2150
2151 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2152 return;
2153
2154 old_read_domains = obj->base.read_domains;
2155 old_write_domain = obj->base.write_domain;
2156
2157 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2158 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2159
2160 trace_i915_gem_object_change_domain(obj,
2161 old_read_domains,
2162 old_write_domain);
2163}
2164
2165/**
2166 * Unbinds an object from the GTT aperture.
2167 */
2168int
2169i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2170{
2171 int ret = 0;
2172
2173 if (obj->gtt_space == NULL)
2174 return 0;
2175
2176 if (obj->pin_count != 0) {
2177 DRM_ERROR("Attempting to unbind pinned buffer\n");
2178 return -EINVAL;
2179 }
2180
2181 ret = i915_gem_object_finish_gpu(obj);
2182 if (ret == -ERESTARTSYS)
2183 return ret;
2184 /* Continue on if we fail due to EIO, the GPU is hung so we
2185 * should be safe and we need to cleanup or else we might
2186 * cause memory corruption through use-after-free.
2187 */
2188
2189 i915_gem_object_finish_gtt(obj);
2190
2191 /* Move the object to the CPU domain to ensure that
2192 * any possible CPU writes while it's not in the GTT
2193 * are flushed when we go to remap it.
2194 */
2195 if (ret == 0)
2196 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2197 if (ret == -ERESTARTSYS)
2198 return ret;
2199 if (ret) {
2200 /* In the event of a disaster, abandon all caches and
2201 * hope for the best.
2202 */
2203 i915_gem_clflush_object(obj);
2204 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2205 }
2206
2207 /* release the fence reg _after_ flushing */
2208 ret = i915_gem_object_put_fence(obj);
2209 if (ret == -ERESTARTSYS)
2210 return ret;
2211
2212 trace_i915_gem_object_unbind(obj);
2213
2214 i915_gem_gtt_unbind_object(obj);
2215 i915_gem_object_put_pages_gtt(obj);
2216
2217 list_del_init(&obj->gtt_list);
2218 list_del_init(&obj->mm_list);
2219 /* Avoid an unnecessary call to unbind on rebind. */
2220 obj->map_and_fenceable = true;
2221
2222 drm_mm_put_block(obj->gtt_space);
2223 obj->gtt_space = NULL;
2224 obj->gtt_offset = 0;
2225
2226 if (i915_gem_object_is_purgeable(obj))
2227 i915_gem_object_truncate(obj);
2228
2229 return ret;
2230}
2231
2232int
2233i915_gem_flush_ring(struct intel_ring_buffer *ring,
2234 uint32_t invalidate_domains,
2235 uint32_t flush_domains)
2236{
2237 int ret;
2238
2239 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2240 return 0;
2241
2242 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2243
2244 ret = ring->flush(ring, invalidate_domains, flush_domains);
2245 if (ret)
2246 return ret;
2247
2248 if (flush_domains & I915_GEM_GPU_DOMAINS)
2249 i915_gem_process_flushing_list(ring, flush_domains);
2250
2251 return 0;
2252}
2253
2254static int i915_ring_idle(struct intel_ring_buffer *ring)
2255{
2256 int ret;
2257
2258 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2259 return 0;
2260
2261 if (!list_empty(&ring->gpu_write_list)) {
2262 ret = i915_gem_flush_ring(ring,
2263 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2264 if (ret)
2265 return ret;
2266 }
2267
2268 return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2269}
2270
2271int
2272i915_gpu_idle(struct drm_device *dev)
2273{
2274 drm_i915_private_t *dev_priv = dev->dev_private;
2275 bool lists_empty;
2276 int ret, i;
2277
2278 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2279 list_empty(&dev_priv->mm.active_list));
2280 if (lists_empty)
2281 return 0;
2282
2283 /* Flush everything onto the inactive list. */
2284 for (i = 0; i < I915_NUM_RINGS; i++) {
2285 ret = i915_ring_idle(&dev_priv->ring[i]);
2286 if (ret)
2287 return ret;
2288 }
2289
2290 return 0;
2291}
2292
2293static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2294 struct intel_ring_buffer *pipelined)
2295{
2296 struct drm_device *dev = obj->base.dev;
2297 drm_i915_private_t *dev_priv = dev->dev_private;
2298 u32 size = obj->gtt_space->size;
2299 int regnum = obj->fence_reg;
2300 uint64_t val;
2301
2302 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2303 0xfffff000) << 32;
2304 val |= obj->gtt_offset & 0xfffff000;
2305 val |= (uint64_t)((obj->stride / 128) - 1) <<
2306 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2307
2308 if (obj->tiling_mode == I915_TILING_Y)
2309 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2310 val |= I965_FENCE_REG_VALID;
2311
2312 if (pipelined) {
2313 int ret = intel_ring_begin(pipelined, 6);
2314 if (ret)
2315 return ret;
2316
2317 intel_ring_emit(pipelined, MI_NOOP);
2318 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2319 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2320 intel_ring_emit(pipelined, (u32)val);
2321 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2322 intel_ring_emit(pipelined, (u32)(val >> 32));
2323 intel_ring_advance(pipelined);
2324 } else
2325 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2326
2327 return 0;
2328}
2329
2330static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2331 struct intel_ring_buffer *pipelined)
2332{
2333 struct drm_device *dev = obj->base.dev;
2334 drm_i915_private_t *dev_priv = dev->dev_private;
2335 u32 size = obj->gtt_space->size;
2336 int regnum = obj->fence_reg;
2337 uint64_t val;
2338
2339 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2340 0xfffff000) << 32;
2341 val |= obj->gtt_offset & 0xfffff000;
2342 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2343 if (obj->tiling_mode == I915_TILING_Y)
2344 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2345 val |= I965_FENCE_REG_VALID;
2346
2347 if (pipelined) {
2348 int ret = intel_ring_begin(pipelined, 6);
2349 if (ret)
2350 return ret;
2351
2352 intel_ring_emit(pipelined, MI_NOOP);
2353 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2354 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2355 intel_ring_emit(pipelined, (u32)val);
2356 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2357 intel_ring_emit(pipelined, (u32)(val >> 32));
2358 intel_ring_advance(pipelined);
2359 } else
2360 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2361
2362 return 0;
2363}
2364
2365static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2366 struct intel_ring_buffer *pipelined)
2367{
2368 struct drm_device *dev = obj->base.dev;
2369 drm_i915_private_t *dev_priv = dev->dev_private;
2370 u32 size = obj->gtt_space->size;
2371 u32 fence_reg, val, pitch_val;
2372 int tile_width;
2373
2374 if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2375 (size & -size) != size ||
2376 (obj->gtt_offset & (size - 1)),
2377 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2378 obj->gtt_offset, obj->map_and_fenceable, size))
2379 return -EINVAL;
2380
2381 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2382 tile_width = 128;
2383 else
2384 tile_width = 512;
2385
2386 /* Note: pitch better be a power of two tile widths */
2387 pitch_val = obj->stride / tile_width;
2388 pitch_val = ffs(pitch_val) - 1;
2389
2390 val = obj->gtt_offset;
2391 if (obj->tiling_mode == I915_TILING_Y)
2392 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2393 val |= I915_FENCE_SIZE_BITS(size);
2394 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2395 val |= I830_FENCE_REG_VALID;
2396
2397 fence_reg = obj->fence_reg;
2398 if (fence_reg < 8)
2399 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2400 else
2401 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2402
2403 if (pipelined) {
2404 int ret = intel_ring_begin(pipelined, 4);
2405 if (ret)
2406 return ret;
2407
2408 intel_ring_emit(pipelined, MI_NOOP);
2409 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2410 intel_ring_emit(pipelined, fence_reg);
2411 intel_ring_emit(pipelined, val);
2412 intel_ring_advance(pipelined);
2413 } else
2414 I915_WRITE(fence_reg, val);
2415
2416 return 0;
2417}
2418
2419static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2420 struct intel_ring_buffer *pipelined)
2421{
2422 struct drm_device *dev = obj->base.dev;
2423 drm_i915_private_t *dev_priv = dev->dev_private;
2424 u32 size = obj->gtt_space->size;
2425 int regnum = obj->fence_reg;
2426 uint32_t val;
2427 uint32_t pitch_val;
2428
2429 if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2430 (size & -size) != size ||
2431 (obj->gtt_offset & (size - 1)),
2432 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2433 obj->gtt_offset, size))
2434 return -EINVAL;
2435
2436 pitch_val = obj->stride / 128;
2437 pitch_val = ffs(pitch_val) - 1;
2438
2439 val = obj->gtt_offset;
2440 if (obj->tiling_mode == I915_TILING_Y)
2441 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2442 val |= I830_FENCE_SIZE_BITS(size);
2443 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2444 val |= I830_FENCE_REG_VALID;
2445
2446 if (pipelined) {
2447 int ret = intel_ring_begin(pipelined, 4);
2448 if (ret)
2449 return ret;
2450
2451 intel_ring_emit(pipelined, MI_NOOP);
2452 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2453 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2454 intel_ring_emit(pipelined, val);
2455 intel_ring_advance(pipelined);
2456 } else
2457 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2458
2459 return 0;
2460}
2461
2462static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2463{
2464 return i915_seqno_passed(ring->get_seqno(ring), seqno);
2465}
2466
2467static int
2468i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
2469 struct intel_ring_buffer *pipelined)
2470{
2471 int ret;
2472
2473 if (obj->fenced_gpu_access) {
2474 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2475 ret = i915_gem_flush_ring(obj->last_fenced_ring,
2476 0, obj->base.write_domain);
2477 if (ret)
2478 return ret;
2479 }
2480
2481 obj->fenced_gpu_access = false;
2482 }
2483
2484 if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2485 if (!ring_passed_seqno(obj->last_fenced_ring,
2486 obj->last_fenced_seqno)) {
2487 ret = i915_wait_request(obj->last_fenced_ring,
2488 obj->last_fenced_seqno);
2489 if (ret)
2490 return ret;
2491 }
2492
2493 obj->last_fenced_seqno = 0;
2494 obj->last_fenced_ring = NULL;
2495 }
2496
2497 /* Ensure that all CPU reads are completed before installing a fence
2498 * and all writes before removing the fence.
2499 */
2500 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2501 mb();
2502
2503 return 0;
2504}
2505
2506int
2507i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2508{
2509 int ret;
2510
2511 if (obj->tiling_mode)
2512 i915_gem_release_mmap(obj);
2513
2514 ret = i915_gem_object_flush_fence(obj, NULL);
2515 if (ret)
2516 return ret;
2517
2518 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2519 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2520 i915_gem_clear_fence_reg(obj->base.dev,
2521 &dev_priv->fence_regs[obj->fence_reg]);
2522
2523 obj->fence_reg = I915_FENCE_REG_NONE;
2524 }
2525
2526 return 0;
2527}
2528
2529static struct drm_i915_fence_reg *
2530i915_find_fence_reg(struct drm_device *dev,
2531 struct intel_ring_buffer *pipelined)
2532{
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534 struct drm_i915_fence_reg *reg, *first, *avail;
2535 int i;
2536
2537 /* First try to find a free reg */
2538 avail = NULL;
2539 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2540 reg = &dev_priv->fence_regs[i];
2541 if (!reg->obj)
2542 return reg;
2543
2544 if (!reg->obj->pin_count)
2545 avail = reg;
2546 }
2547
2548 if (avail == NULL)
2549 return NULL;
2550
2551 /* None available, try to steal one or wait for a user to finish */
2552 avail = first = NULL;
2553 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2554 if (reg->obj->pin_count)
2555 continue;
2556
2557 if (first == NULL)
2558 first = reg;
2559
2560 if (!pipelined ||
2561 !reg->obj->last_fenced_ring ||
2562 reg->obj->last_fenced_ring == pipelined) {
2563 avail = reg;
2564 break;
2565 }
2566 }
2567
2568 if (avail == NULL)
2569 avail = first;
2570
2571 return avail;
2572}
2573
2574/**
2575 * i915_gem_object_get_fence - set up a fence reg for an object
2576 * @obj: object to map through a fence reg
2577 * @pipelined: ring on which to queue the change, or NULL for CPU access
2578 * @interruptible: must we wait uninterruptibly for the register to retire?
2579 *
2580 * When mapping objects through the GTT, userspace wants to be able to write
2581 * to them without having to worry about swizzling if the object is tiled.
2582 *
2583 * This function walks the fence regs looking for a free one for @obj,
2584 * stealing one if it can't find any.
2585 *
2586 * It then sets up the reg based on the object's properties: address, pitch
2587 * and tiling format.
2588 */
2589int
2590i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2591 struct intel_ring_buffer *pipelined)
2592{
2593 struct drm_device *dev = obj->base.dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct drm_i915_fence_reg *reg;
2596 int ret;
2597
2598 /* XXX disable pipelining. There are bugs. Shocking. */
2599 pipelined = NULL;
2600
2601 /* Just update our place in the LRU if our fence is getting reused. */
2602 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2603 reg = &dev_priv->fence_regs[obj->fence_reg];
2604 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2605
2606 if (obj->tiling_changed) {
2607 ret = i915_gem_object_flush_fence(obj, pipelined);
2608 if (ret)
2609 return ret;
2610
2611 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2612 pipelined = NULL;
2613
2614 if (pipelined) {
2615 reg->setup_seqno =
2616 i915_gem_next_request_seqno(pipelined);
2617 obj->last_fenced_seqno = reg->setup_seqno;
2618 obj->last_fenced_ring = pipelined;
2619 }
2620
2621 goto update;
2622 }
2623
2624 if (!pipelined) {
2625 if (reg->setup_seqno) {
2626 if (!ring_passed_seqno(obj->last_fenced_ring,
2627 reg->setup_seqno)) {
2628 ret = i915_wait_request(obj->last_fenced_ring,
2629 reg->setup_seqno);
2630 if (ret)
2631 return ret;
2632 }
2633
2634 reg->setup_seqno = 0;
2635 }
2636 } else if (obj->last_fenced_ring &&
2637 obj->last_fenced_ring != pipelined) {
2638 ret = i915_gem_object_flush_fence(obj, pipelined);
2639 if (ret)
2640 return ret;
2641 }
2642
2643 return 0;
2644 }
2645
2646 reg = i915_find_fence_reg(dev, pipelined);
2647 if (reg == NULL)
2648 return -ENOSPC;
2649
2650 ret = i915_gem_object_flush_fence(obj, pipelined);
2651 if (ret)
2652 return ret;
2653
2654 if (reg->obj) {
2655 struct drm_i915_gem_object *old = reg->obj;
2656
2657 drm_gem_object_reference(&old->base);
2658
2659 if (old->tiling_mode)
2660 i915_gem_release_mmap(old);
2661
2662 ret = i915_gem_object_flush_fence(old, pipelined);
2663 if (ret) {
2664 drm_gem_object_unreference(&old->base);
2665 return ret;
2666 }
2667
2668 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2669 pipelined = NULL;
2670
2671 old->fence_reg = I915_FENCE_REG_NONE;
2672 old->last_fenced_ring = pipelined;
2673 old->last_fenced_seqno =
2674 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2675
2676 drm_gem_object_unreference(&old->base);
2677 } else if (obj->last_fenced_seqno == 0)
2678 pipelined = NULL;
2679
2680 reg->obj = obj;
2681 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2682 obj->fence_reg = reg - dev_priv->fence_regs;
2683 obj->last_fenced_ring = pipelined;
2684
2685 reg->setup_seqno =
2686 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
2687 obj->last_fenced_seqno = reg->setup_seqno;
2688
2689update:
2690 obj->tiling_changed = false;
2691 switch (INTEL_INFO(dev)->gen) {
2692 case 7:
2693 case 6:
2694 ret = sandybridge_write_fence_reg(obj, pipelined);
2695 break;
2696 case 5:
2697 case 4:
2698 ret = i965_write_fence_reg(obj, pipelined);
2699 break;
2700 case 3:
2701 ret = i915_write_fence_reg(obj, pipelined);
2702 break;
2703 case 2:
2704 ret = i830_write_fence_reg(obj, pipelined);
2705 break;
2706 }
2707
2708 return ret;
2709}
2710
2711/**
2712 * i915_gem_clear_fence_reg - clear out fence register info
2713 * @obj: object to clear
2714 *
2715 * Zeroes out the fence register itself and clears out the associated
2716 * data structures in dev_priv and obj.
2717 */
2718static void
2719i915_gem_clear_fence_reg(struct drm_device *dev,
2720 struct drm_i915_fence_reg *reg)
2721{
2722 drm_i915_private_t *dev_priv = dev->dev_private;
2723 uint32_t fence_reg = reg - dev_priv->fence_regs;
2724
2725 switch (INTEL_INFO(dev)->gen) {
2726 case 7:
2727 case 6:
2728 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2729 break;
2730 case 5:
2731 case 4:
2732 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
2733 break;
2734 case 3:
2735 if (fence_reg >= 8)
2736 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2737 else
2738 case 2:
2739 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2740
2741 I915_WRITE(fence_reg, 0);
2742 break;
2743 }
2744
2745 list_del_init(®->lru_list);
2746 reg->obj = NULL;
2747 reg->setup_seqno = 0;
2748}
2749
2750/**
2751 * Finds free space in the GTT aperture and binds the object there.
2752 */
2753static int
2754i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2755 unsigned alignment,
2756 bool map_and_fenceable)
2757{
2758 struct drm_device *dev = obj->base.dev;
2759 drm_i915_private_t *dev_priv = dev->dev_private;
2760 struct drm_mm_node *free_space;
2761 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2762 u32 size, fence_size, fence_alignment, unfenced_alignment;
2763 bool mappable, fenceable;
2764 int ret;
2765
2766 if (obj->madv != I915_MADV_WILLNEED) {
2767 DRM_ERROR("Attempting to bind a purgeable object\n");
2768 return -EINVAL;
2769 }
2770
2771 fence_size = i915_gem_get_gtt_size(dev,
2772 obj->base.size,
2773 obj->tiling_mode);
2774 fence_alignment = i915_gem_get_gtt_alignment(dev,
2775 obj->base.size,
2776 obj->tiling_mode);
2777 unfenced_alignment =
2778 i915_gem_get_unfenced_gtt_alignment(dev,
2779 obj->base.size,
2780 obj->tiling_mode);
2781
2782 if (alignment == 0)
2783 alignment = map_and_fenceable ? fence_alignment :
2784 unfenced_alignment;
2785 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2786 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2787 return -EINVAL;
2788 }
2789
2790 size = map_and_fenceable ? fence_size : obj->base.size;
2791
2792 /* If the object is bigger than the entire aperture, reject it early
2793 * before evicting everything in a vain attempt to find space.
2794 */
2795 if (obj->base.size >
2796 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2797 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2798 return -E2BIG;
2799 }
2800
2801 search_free:
2802 if (map_and_fenceable)
2803 free_space =
2804 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2805 size, alignment, 0,
2806 dev_priv->mm.gtt_mappable_end,
2807 0);
2808 else
2809 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2810 size, alignment, 0);
2811
2812 if (free_space != NULL) {
2813 if (map_and_fenceable)
2814 obj->gtt_space =
2815 drm_mm_get_block_range_generic(free_space,
2816 size, alignment, 0,
2817 dev_priv->mm.gtt_mappable_end,
2818 0);
2819 else
2820 obj->gtt_space =
2821 drm_mm_get_block(free_space, size, alignment);
2822 }
2823 if (obj->gtt_space == NULL) {
2824 /* If the gtt is empty and we're still having trouble
2825 * fitting our object in, we're out of memory.
2826 */
2827 ret = i915_gem_evict_something(dev, size, alignment,
2828 map_and_fenceable);
2829 if (ret)
2830 return ret;
2831
2832 goto search_free;
2833 }
2834
2835 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2836 if (ret) {
2837 drm_mm_put_block(obj->gtt_space);
2838 obj->gtt_space = NULL;
2839
2840 if (ret == -ENOMEM) {
2841 /* first try to reclaim some memory by clearing the GTT */
2842 ret = i915_gem_evict_everything(dev, false);
2843 if (ret) {
2844 /* now try to shrink everyone else */
2845 if (gfpmask) {
2846 gfpmask = 0;
2847 goto search_free;
2848 }
2849
2850 return -ENOMEM;
2851 }
2852
2853 goto search_free;
2854 }
2855
2856 return ret;
2857 }
2858
2859 ret = i915_gem_gtt_bind_object(obj);
2860 if (ret) {
2861 i915_gem_object_put_pages_gtt(obj);
2862 drm_mm_put_block(obj->gtt_space);
2863 obj->gtt_space = NULL;
2864
2865 if (i915_gem_evict_everything(dev, false))
2866 return ret;
2867
2868 goto search_free;
2869 }
2870
2871 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2872 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2873
2874 /* Assert that the object is not currently in any GPU domain. As it
2875 * wasn't in the GTT, there shouldn't be any way it could have been in
2876 * a GPU cache
2877 */
2878 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2879 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2880
2881 obj->gtt_offset = obj->gtt_space->start;
2882
2883 fenceable =
2884 obj->gtt_space->size == fence_size &&
2885 (obj->gtt_space->start & (fence_alignment -1)) == 0;
2886
2887 mappable =
2888 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2889
2890 obj->map_and_fenceable = mappable && fenceable;
2891
2892 trace_i915_gem_object_bind(obj, map_and_fenceable);
2893 return 0;
2894}
2895
2896void
2897i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2898{
2899 /* If we don't have a page list set up, then we're not pinned
2900 * to GPU, and we can ignore the cache flush because it'll happen
2901 * again at bind time.
2902 */
2903 if (obj->pages == NULL)
2904 return;
2905
2906 /* If the GPU is snooping the contents of the CPU cache,
2907 * we do not need to manually clear the CPU cache lines. However,
2908 * the caches are only snooped when the render cache is
2909 * flushed/invalidated. As we always have to emit invalidations
2910 * and flushes when moving into and out of the RENDER domain, correct
2911 * snooping behaviour occurs naturally as the result of our domain
2912 * tracking.
2913 */
2914 if (obj->cache_level != I915_CACHE_NONE)
2915 return;
2916
2917 trace_i915_gem_object_clflush(obj);
2918
2919 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2920}
2921
2922/** Flushes any GPU write domain for the object if it's dirty. */
2923static int
2924i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2925{
2926 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2927 return 0;
2928
2929 /* Queue the GPU write cache flushing we need. */
2930 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2931}
2932
2933/** Flushes the GTT write domain for the object if it's dirty. */
2934static void
2935i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2936{
2937 uint32_t old_write_domain;
2938
2939 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2940 return;
2941
2942 /* No actual flushing is required for the GTT write domain. Writes
2943 * to it immediately go to main memory as far as we know, so there's
2944 * no chipset flush. It also doesn't land in render cache.
2945 *
2946 * However, we do have to enforce the order so that all writes through
2947 * the GTT land before any writes to the device, such as updates to
2948 * the GATT itself.
2949 */
2950 wmb();
2951
2952 old_write_domain = obj->base.write_domain;
2953 obj->base.write_domain = 0;
2954
2955 trace_i915_gem_object_change_domain(obj,
2956 obj->base.read_domains,
2957 old_write_domain);
2958}
2959
2960/** Flushes the CPU write domain for the object if it's dirty. */
2961static void
2962i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2963{
2964 uint32_t old_write_domain;
2965
2966 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2967 return;
2968
2969 i915_gem_clflush_object(obj);
2970 intel_gtt_chipset_flush();
2971 old_write_domain = obj->base.write_domain;
2972 obj->base.write_domain = 0;
2973
2974 trace_i915_gem_object_change_domain(obj,
2975 obj->base.read_domains,
2976 old_write_domain);
2977}
2978
2979/**
2980 * Moves a single object to the GTT read, and possibly write domain.
2981 *
2982 * This function returns when the move is complete, including waiting on
2983 * flushes to occur.
2984 */
2985int
2986i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2987{
2988 uint32_t old_write_domain, old_read_domains;
2989 int ret;
2990
2991 /* Not valid to be called on unbound objects. */
2992 if (obj->gtt_space == NULL)
2993 return -EINVAL;
2994
2995 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2996 return 0;
2997
2998 ret = i915_gem_object_flush_gpu_write_domain(obj);
2999 if (ret)
3000 return ret;
3001
3002 if (obj->pending_gpu_write || write) {
3003 ret = i915_gem_object_wait_rendering(obj);
3004 if (ret)
3005 return ret;
3006 }
3007
3008 i915_gem_object_flush_cpu_write_domain(obj);
3009
3010 old_write_domain = obj->base.write_domain;
3011 old_read_domains = obj->base.read_domains;
3012
3013 /* It should now be out of any other write domains, and we can update
3014 * the domain values for our changes.
3015 */
3016 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3017 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3018 if (write) {
3019 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3020 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3021 obj->dirty = 1;
3022 }
3023
3024 trace_i915_gem_object_change_domain(obj,
3025 old_read_domains,
3026 old_write_domain);
3027
3028 return 0;
3029}
3030
3031int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3032 enum i915_cache_level cache_level)
3033{
3034 int ret;
3035
3036 if (obj->cache_level == cache_level)
3037 return 0;
3038
3039 if (obj->pin_count) {
3040 DRM_DEBUG("can not change the cache level of pinned objects\n");
3041 return -EBUSY;
3042 }
3043
3044 if (obj->gtt_space) {
3045 ret = i915_gem_object_finish_gpu(obj);
3046 if (ret)
3047 return ret;
3048
3049 i915_gem_object_finish_gtt(obj);
3050
3051 /* Before SandyBridge, you could not use tiling or fence
3052 * registers with snooped memory, so relinquish any fences
3053 * currently pointing to our region in the aperture.
3054 */
3055 if (INTEL_INFO(obj->base.dev)->gen < 6) {
3056 ret = i915_gem_object_put_fence(obj);
3057 if (ret)
3058 return ret;
3059 }
3060
3061 i915_gem_gtt_rebind_object(obj, cache_level);
3062 }
3063
3064 if (cache_level == I915_CACHE_NONE) {
3065 u32 old_read_domains, old_write_domain;
3066
3067 /* If we're coming from LLC cached, then we haven't
3068 * actually been tracking whether the data is in the
3069 * CPU cache or not, since we only allow one bit set
3070 * in obj->write_domain and have been skipping the clflushes.
3071 * Just set it to the CPU cache for now.
3072 */
3073 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3074 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3075
3076 old_read_domains = obj->base.read_domains;
3077 old_write_domain = obj->base.write_domain;
3078
3079 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3080 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3081
3082 trace_i915_gem_object_change_domain(obj,
3083 old_read_domains,
3084 old_write_domain);
3085 }
3086
3087 obj->cache_level = cache_level;
3088 return 0;
3089}
3090
3091/*
3092 * Prepare buffer for display plane (scanout, cursors, etc).
3093 * Can be called from an uninterruptible phase (modesetting) and allows
3094 * any flushes to be pipelined (for pageflips).
3095 *
3096 * For the display plane, we want to be in the GTT but out of any write
3097 * domains. So in many ways this looks like set_to_gtt_domain() apart from the
3098 * ability to pipeline the waits, pinning and any additional subtleties
3099 * that may differentiate the display plane from ordinary buffers.
3100 */
3101int
3102i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3103 u32 alignment,
3104 struct intel_ring_buffer *pipelined)
3105{
3106 u32 old_read_domains, old_write_domain;
3107 int ret;
3108
3109 ret = i915_gem_object_flush_gpu_write_domain(obj);
3110 if (ret)
3111 return ret;
3112
3113 if (pipelined != obj->ring) {
3114 ret = i915_gem_object_wait_rendering(obj);
3115 if (ret == -ERESTARTSYS)
3116 return ret;
3117 }
3118
3119 /* The display engine is not coherent with the LLC cache on gen6. As
3120 * a result, we make sure that the pinning that is about to occur is
3121 * done with uncached PTEs. This is lowest common denominator for all
3122 * chipsets.
3123 *
3124 * However for gen6+, we could do better by using the GFDT bit instead
3125 * of uncaching, which would allow us to flush all the LLC-cached data
3126 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3127 */
3128 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3129 if (ret)
3130 return ret;
3131
3132 /* As the user may map the buffer once pinned in the display plane
3133 * (e.g. libkms for the bootup splash), we have to ensure that we
3134 * always use map_and_fenceable for all scanout buffers.
3135 */
3136 ret = i915_gem_object_pin(obj, alignment, true);
3137 if (ret)
3138 return ret;
3139
3140 i915_gem_object_flush_cpu_write_domain(obj);
3141
3142 old_write_domain = obj->base.write_domain;
3143 old_read_domains = obj->base.read_domains;
3144
3145 /* It should now be out of any other write domains, and we can update
3146 * the domain values for our changes.
3147 */
3148 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3149 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3150
3151 trace_i915_gem_object_change_domain(obj,
3152 old_read_domains,
3153 old_write_domain);
3154
3155 return 0;
3156}
3157
3158int
3159i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3160{
3161 int ret;
3162
3163 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3164 return 0;
3165
3166 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3167 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
3168 if (ret)
3169 return ret;
3170 }
3171
3172 /* Ensure that we invalidate the GPU's caches and TLBs. */
3173 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3174
3175 return i915_gem_object_wait_rendering(obj);
3176}
3177
3178/**
3179 * Moves a single object to the CPU read, and possibly write domain.
3180 *
3181 * This function returns when the move is complete, including waiting on
3182 * flushes to occur.
3183 */
3184static int
3185i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3186{
3187 uint32_t old_write_domain, old_read_domains;
3188 int ret;
3189
3190 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3191 return 0;
3192
3193 ret = i915_gem_object_flush_gpu_write_domain(obj);
3194 if (ret)
3195 return ret;
3196
3197 ret = i915_gem_object_wait_rendering(obj);
3198 if (ret)
3199 return ret;
3200
3201 i915_gem_object_flush_gtt_write_domain(obj);
3202
3203 /* If we have a partially-valid cache of the object in the CPU,
3204 * finish invalidating it and free the per-page flags.
3205 */
3206 i915_gem_object_set_to_full_cpu_read_domain(obj);
3207
3208 old_write_domain = obj->base.write_domain;
3209 old_read_domains = obj->base.read_domains;
3210
3211 /* Flush the CPU cache if it's still invalid. */
3212 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3213 i915_gem_clflush_object(obj);
3214
3215 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3216 }
3217
3218 /* It should now be out of any other write domains, and we can update
3219 * the domain values for our changes.
3220 */
3221 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3222
3223 /* If we're writing through the CPU, then the GPU read domains will
3224 * need to be invalidated at next use.
3225 */
3226 if (write) {
3227 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3228 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3229 }
3230
3231 trace_i915_gem_object_change_domain(obj,
3232 old_read_domains,
3233 old_write_domain);
3234
3235 return 0;
3236}
3237
3238/**
3239 * Moves the object from a partially CPU read to a full one.
3240 *
3241 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3242 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3243 */
3244static void
3245i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
3246{
3247 if (!obj->page_cpu_valid)
3248 return;
3249
3250 /* If we're partially in the CPU read domain, finish moving it in.
3251 */
3252 if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
3253 int i;
3254
3255 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3256 if (obj->page_cpu_valid[i])
3257 continue;
3258 drm_clflush_pages(obj->pages + i, 1);
3259 }
3260 }
3261
3262 /* Free the page_cpu_valid mappings which are now stale, whether
3263 * or not we've got I915_GEM_DOMAIN_CPU.
3264 */
3265 kfree(obj->page_cpu_valid);
3266 obj->page_cpu_valid = NULL;
3267}
3268
3269/**
3270 * Set the CPU read domain on a range of the object.
3271 *
3272 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3273 * not entirely valid. The page_cpu_valid member of the object flags which
3274 * pages have been flushed, and will be respected by
3275 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3276 * of the whole object.
3277 *
3278 * This function returns when the move is complete, including waiting on
3279 * flushes to occur.
3280 */
3281static int
3282i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3283 uint64_t offset, uint64_t size)
3284{
3285 uint32_t old_read_domains;
3286 int i, ret;
3287
3288 if (offset == 0 && size == obj->base.size)
3289 return i915_gem_object_set_to_cpu_domain(obj, 0);
3290
3291 ret = i915_gem_object_flush_gpu_write_domain(obj);
3292 if (ret)
3293 return ret;
3294
3295 ret = i915_gem_object_wait_rendering(obj);
3296 if (ret)
3297 return ret;
3298
3299 i915_gem_object_flush_gtt_write_domain(obj);
3300
3301 /* If we're already fully in the CPU read domain, we're done. */
3302 if (obj->page_cpu_valid == NULL &&
3303 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
3304 return 0;
3305
3306 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3307 * newly adding I915_GEM_DOMAIN_CPU
3308 */
3309 if (obj->page_cpu_valid == NULL) {
3310 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3311 GFP_KERNEL);
3312 if (obj->page_cpu_valid == NULL)
3313 return -ENOMEM;
3314 } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3315 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
3316
3317 /* Flush the cache on any pages that are still invalid from the CPU's
3318 * perspective.
3319 */
3320 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3321 i++) {
3322 if (obj->page_cpu_valid[i])
3323 continue;
3324
3325 drm_clflush_pages(obj->pages + i, 1);
3326
3327 obj->page_cpu_valid[i] = 1;
3328 }
3329
3330 /* It should now be out of any other write domains, and we can update
3331 * the domain values for our changes.
3332 */
3333 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3334
3335 old_read_domains = obj->base.read_domains;
3336 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3337
3338 trace_i915_gem_object_change_domain(obj,
3339 old_read_domains,
3340 obj->base.write_domain);
3341
3342 return 0;
3343}
3344
3345/* Throttle our rendering by waiting until the ring has completed our requests
3346 * emitted over 20 msec ago.
3347 *
3348 * Note that if we were to use the current jiffies each time around the loop,
3349 * we wouldn't escape the function with any frames outstanding if the time to
3350 * render a frame was over 20ms.
3351 *
3352 * This should get us reasonable parallelism between CPU and GPU but also
3353 * relatively low latency when blocking on a particular request to finish.
3354 */
3355static int
3356i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3357{
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 struct drm_i915_file_private *file_priv = file->driver_priv;
3360 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3361 struct drm_i915_gem_request *request;
3362 struct intel_ring_buffer *ring = NULL;
3363 u32 seqno = 0;
3364 int ret;
3365
3366 if (atomic_read(&dev_priv->mm.wedged))
3367 return -EIO;
3368
3369 spin_lock(&file_priv->mm.lock);
3370 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3371 if (time_after_eq(request->emitted_jiffies, recent_enough))
3372 break;
3373
3374 ring = request->ring;
3375 seqno = request->seqno;
3376 }
3377 spin_unlock(&file_priv->mm.lock);
3378
3379 if (seqno == 0)
3380 return 0;
3381
3382 ret = 0;
3383 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3384 /* And wait for the seqno passing without holding any locks and
3385 * causing extra latency for others. This is safe as the irq
3386 * generation is designed to be run atomically and so is
3387 * lockless.
3388 */
3389 if (ring->irq_get(ring)) {
3390 ret = wait_event_interruptible(ring->irq_queue,
3391 i915_seqno_passed(ring->get_seqno(ring), seqno)
3392 || atomic_read(&dev_priv->mm.wedged));
3393 ring->irq_put(ring);
3394
3395 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3396 ret = -EIO;
3397 }
3398 }
3399
3400 if (ret == 0)
3401 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3402
3403 return ret;
3404}
3405
3406int
3407i915_gem_object_pin(struct drm_i915_gem_object *obj,
3408 uint32_t alignment,
3409 bool map_and_fenceable)
3410{
3411 struct drm_device *dev = obj->base.dev;
3412 struct drm_i915_private *dev_priv = dev->dev_private;
3413 int ret;
3414
3415 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3416 WARN_ON(i915_verify_lists(dev));
3417
3418 if (obj->gtt_space != NULL) {
3419 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3420 (map_and_fenceable && !obj->map_and_fenceable)) {
3421 WARN(obj->pin_count,
3422 "bo is already pinned with incorrect alignment:"
3423 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3424 " obj->map_and_fenceable=%d\n",
3425 obj->gtt_offset, alignment,
3426 map_and_fenceable,
3427 obj->map_and_fenceable);
3428 ret = i915_gem_object_unbind(obj);
3429 if (ret)
3430 return ret;
3431 }
3432 }
3433
3434 if (obj->gtt_space == NULL) {
3435 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3436 map_and_fenceable);
3437 if (ret)
3438 return ret;
3439 }
3440
3441 if (obj->pin_count++ == 0) {
3442 if (!obj->active)
3443 list_move_tail(&obj->mm_list,
3444 &dev_priv->mm.pinned_list);
3445 }
3446 obj->pin_mappable |= map_and_fenceable;
3447
3448 WARN_ON(i915_verify_lists(dev));
3449 return 0;
3450}
3451
3452void
3453i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3454{
3455 struct drm_device *dev = obj->base.dev;
3456 drm_i915_private_t *dev_priv = dev->dev_private;
3457
3458 WARN_ON(i915_verify_lists(dev));
3459 BUG_ON(obj->pin_count == 0);
3460 BUG_ON(obj->gtt_space == NULL);
3461
3462 if (--obj->pin_count == 0) {
3463 if (!obj->active)
3464 list_move_tail(&obj->mm_list,
3465 &dev_priv->mm.inactive_list);
3466 obj->pin_mappable = false;
3467 }
3468 WARN_ON(i915_verify_lists(dev));
3469}
3470
3471int
3472i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3473 struct drm_file *file)
3474{
3475 struct drm_i915_gem_pin *args = data;
3476 struct drm_i915_gem_object *obj;
3477 int ret;
3478
3479 ret = i915_mutex_lock_interruptible(dev);
3480 if (ret)
3481 return ret;
3482
3483 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3484 if (&obj->base == NULL) {
3485 ret = -ENOENT;
3486 goto unlock;
3487 }
3488
3489 if (obj->madv != I915_MADV_WILLNEED) {
3490 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3491 ret = -EINVAL;
3492 goto out;
3493 }
3494
3495 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3496 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3497 args->handle);
3498 ret = -EINVAL;
3499 goto out;
3500 }
3501
3502 obj->user_pin_count++;
3503 obj->pin_filp = file;
3504 if (obj->user_pin_count == 1) {
3505 ret = i915_gem_object_pin(obj, args->alignment, true);
3506 if (ret)
3507 goto out;
3508 }
3509
3510 /* XXX - flush the CPU caches for pinned objects
3511 * as the X server doesn't manage domains yet
3512 */
3513 i915_gem_object_flush_cpu_write_domain(obj);
3514 args->offset = obj->gtt_offset;
3515out:
3516 drm_gem_object_unreference(&obj->base);
3517unlock:
3518 mutex_unlock(&dev->struct_mutex);
3519 return ret;
3520}
3521
3522int
3523i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3524 struct drm_file *file)
3525{
3526 struct drm_i915_gem_pin *args = data;
3527 struct drm_i915_gem_object *obj;
3528 int ret;
3529
3530 ret = i915_mutex_lock_interruptible(dev);
3531 if (ret)
3532 return ret;
3533
3534 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3535 if (&obj->base == NULL) {
3536 ret = -ENOENT;
3537 goto unlock;
3538 }
3539
3540 if (obj->pin_filp != file) {
3541 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3542 args->handle);
3543 ret = -EINVAL;
3544 goto out;
3545 }
3546 obj->user_pin_count--;
3547 if (obj->user_pin_count == 0) {
3548 obj->pin_filp = NULL;
3549 i915_gem_object_unpin(obj);
3550 }
3551
3552out:
3553 drm_gem_object_unreference(&obj->base);
3554unlock:
3555 mutex_unlock(&dev->struct_mutex);
3556 return ret;
3557}
3558
3559int
3560i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3561 struct drm_file *file)
3562{
3563 struct drm_i915_gem_busy *args = data;
3564 struct drm_i915_gem_object *obj;
3565 int ret;
3566
3567 ret = i915_mutex_lock_interruptible(dev);
3568 if (ret)
3569 return ret;
3570
3571 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3572 if (&obj->base == NULL) {
3573 ret = -ENOENT;
3574 goto unlock;
3575 }
3576
3577 /* Count all active objects as busy, even if they are currently not used
3578 * by the gpu. Users of this interface expect objects to eventually
3579 * become non-busy without any further actions, therefore emit any
3580 * necessary flushes here.
3581 */
3582 args->busy = obj->active;
3583 if (args->busy) {
3584 /* Unconditionally flush objects, even when the gpu still uses this
3585 * object. Userspace calling this function indicates that it wants to
3586 * use this buffer rather sooner than later, so issuing the required
3587 * flush earlier is beneficial.
3588 */
3589 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3590 ret = i915_gem_flush_ring(obj->ring,
3591 0, obj->base.write_domain);
3592 } else if (obj->ring->outstanding_lazy_request ==
3593 obj->last_rendering_seqno) {
3594 struct drm_i915_gem_request *request;
3595
3596 /* This ring is not being cleared by active usage,
3597 * so emit a request to do so.
3598 */
3599 request = kzalloc(sizeof(*request), GFP_KERNEL);
3600 if (request)
3601 ret = i915_add_request(obj->ring, NULL,request);
3602 else
3603 ret = -ENOMEM;
3604 }
3605
3606 /* Update the active list for the hardware's current position.
3607 * Otherwise this only updates on a delayed timer or when irqs
3608 * are actually unmasked, and our working set ends up being
3609 * larger than required.
3610 */
3611 i915_gem_retire_requests_ring(obj->ring);
3612
3613 args->busy = obj->active;
3614 }
3615
3616 drm_gem_object_unreference(&obj->base);
3617unlock:
3618 mutex_unlock(&dev->struct_mutex);
3619 return ret;
3620}
3621
3622int
3623i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3624 struct drm_file *file_priv)
3625{
3626 return i915_gem_ring_throttle(dev, file_priv);
3627}
3628
3629int
3630i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3631 struct drm_file *file_priv)
3632{
3633 struct drm_i915_gem_madvise *args = data;
3634 struct drm_i915_gem_object *obj;
3635 int ret;
3636
3637 switch (args->madv) {
3638 case I915_MADV_DONTNEED:
3639 case I915_MADV_WILLNEED:
3640 break;
3641 default:
3642 return -EINVAL;
3643 }
3644
3645 ret = i915_mutex_lock_interruptible(dev);
3646 if (ret)
3647 return ret;
3648
3649 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3650 if (&obj->base == NULL) {
3651 ret = -ENOENT;
3652 goto unlock;
3653 }
3654
3655 if (obj->pin_count) {
3656 ret = -EINVAL;
3657 goto out;
3658 }
3659
3660 if (obj->madv != __I915_MADV_PURGED)
3661 obj->madv = args->madv;
3662
3663 /* if the object is no longer bound, discard its backing storage */
3664 if (i915_gem_object_is_purgeable(obj) &&
3665 obj->gtt_space == NULL)
3666 i915_gem_object_truncate(obj);
3667
3668 args->retained = obj->madv != __I915_MADV_PURGED;
3669
3670out:
3671 drm_gem_object_unreference(&obj->base);
3672unlock:
3673 mutex_unlock(&dev->struct_mutex);
3674 return ret;
3675}
3676
3677struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3678 size_t size)
3679{
3680 struct drm_i915_private *dev_priv = dev->dev_private;
3681 struct drm_i915_gem_object *obj;
3682 struct address_space *mapping;
3683
3684 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3685 if (obj == NULL)
3686 return NULL;
3687
3688 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3689 kfree(obj);
3690 return NULL;
3691 }
3692
3693 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3694 mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
3695
3696 i915_gem_info_add_obj(dev_priv, size);
3697
3698 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3699 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3700
3701 if (IS_GEN6(dev)) {
3702 /* On Gen6, we can have the GPU use the LLC (the CPU
3703 * cache) for about a 10% performance improvement
3704 * compared to uncached. Graphics requests other than
3705 * display scanout are coherent with the CPU in
3706 * accessing this cache. This means in this mode we
3707 * don't need to clflush on the CPU side, and on the
3708 * GPU side we only need to flush internal caches to
3709 * get data visible to the CPU.
3710 *
3711 * However, we maintain the display planes as UC, and so
3712 * need to rebind when first used as such.
3713 */
3714 obj->cache_level = I915_CACHE_LLC;
3715 } else
3716 obj->cache_level = I915_CACHE_NONE;
3717
3718 obj->base.driver_private = NULL;
3719 obj->fence_reg = I915_FENCE_REG_NONE;
3720 INIT_LIST_HEAD(&obj->mm_list);
3721 INIT_LIST_HEAD(&obj->gtt_list);
3722 INIT_LIST_HEAD(&obj->ring_list);
3723 INIT_LIST_HEAD(&obj->exec_list);
3724 INIT_LIST_HEAD(&obj->gpu_write_list);
3725 obj->madv = I915_MADV_WILLNEED;
3726 /* Avoid an unnecessary call to unbind on the first bind. */
3727 obj->map_and_fenceable = true;
3728
3729 return obj;
3730}
3731
3732int i915_gem_init_object(struct drm_gem_object *obj)
3733{
3734 BUG();
3735
3736 return 0;
3737}
3738
3739static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
3740{
3741 struct drm_device *dev = obj->base.dev;
3742 drm_i915_private_t *dev_priv = dev->dev_private;
3743 int ret;
3744
3745 ret = i915_gem_object_unbind(obj);
3746 if (ret == -ERESTARTSYS) {
3747 list_move(&obj->mm_list,
3748 &dev_priv->mm.deferred_free_list);
3749 return;
3750 }
3751
3752 trace_i915_gem_object_destroy(obj);
3753
3754 if (obj->base.map_list.map)
3755 i915_gem_free_mmap_offset(obj);
3756
3757 drm_gem_object_release(&obj->base);
3758 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3759
3760 kfree(obj->page_cpu_valid);
3761 kfree(obj->bit_17);
3762 kfree(obj);
3763}
3764
3765void i915_gem_free_object(struct drm_gem_object *gem_obj)
3766{
3767 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3768 struct drm_device *dev = obj->base.dev;
3769
3770 while (obj->pin_count > 0)
3771 i915_gem_object_unpin(obj);
3772
3773 if (obj->phys_obj)
3774 i915_gem_detach_phys_object(dev, obj);
3775
3776 i915_gem_free_object_tail(obj);
3777}
3778
3779int
3780i915_gem_idle(struct drm_device *dev)
3781{
3782 drm_i915_private_t *dev_priv = dev->dev_private;
3783 int ret;
3784
3785 mutex_lock(&dev->struct_mutex);
3786
3787 if (dev_priv->mm.suspended) {
3788 mutex_unlock(&dev->struct_mutex);
3789 return 0;
3790 }
3791
3792 ret = i915_gpu_idle(dev);
3793 if (ret) {
3794 mutex_unlock(&dev->struct_mutex);
3795 return ret;
3796 }
3797
3798 /* Under UMS, be paranoid and evict. */
3799 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
3800 ret = i915_gem_evict_inactive(dev, false);
3801 if (ret) {
3802 mutex_unlock(&dev->struct_mutex);
3803 return ret;
3804 }
3805 }
3806
3807 i915_gem_reset_fences(dev);
3808
3809 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3810 * We need to replace this with a semaphore, or something.
3811 * And not confound mm.suspended!
3812 */
3813 dev_priv->mm.suspended = 1;
3814 del_timer_sync(&dev_priv->hangcheck_timer);
3815
3816 i915_kernel_lost_context(dev);
3817 i915_gem_cleanup_ringbuffer(dev);
3818
3819 mutex_unlock(&dev->struct_mutex);
3820
3821 /* Cancel the retire work handler, which should be idle now. */
3822 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3823
3824 return 0;
3825}
3826
3827int
3828i915_gem_init_ringbuffer(struct drm_device *dev)
3829{
3830 drm_i915_private_t *dev_priv = dev->dev_private;
3831 int ret;
3832
3833 ret = intel_init_render_ring_buffer(dev);
3834 if (ret)
3835 return ret;
3836
3837 if (HAS_BSD(dev)) {
3838 ret = intel_init_bsd_ring_buffer(dev);
3839 if (ret)
3840 goto cleanup_render_ring;
3841 }
3842
3843 if (HAS_BLT(dev)) {
3844 ret = intel_init_blt_ring_buffer(dev);
3845 if (ret)
3846 goto cleanup_bsd_ring;
3847 }
3848
3849 dev_priv->next_seqno = 1;
3850
3851 return 0;
3852
3853cleanup_bsd_ring:
3854 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3855cleanup_render_ring:
3856 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3857 return ret;
3858}
3859
3860void
3861i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3862{
3863 drm_i915_private_t *dev_priv = dev->dev_private;
3864 int i;
3865
3866 for (i = 0; i < I915_NUM_RINGS; i++)
3867 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
3868}
3869
3870int
3871i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3872 struct drm_file *file_priv)
3873{
3874 drm_i915_private_t *dev_priv = dev->dev_private;
3875 int ret, i;
3876
3877 if (drm_core_check_feature(dev, DRIVER_MODESET))
3878 return 0;
3879
3880 if (atomic_read(&dev_priv->mm.wedged)) {
3881 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3882 atomic_set(&dev_priv->mm.wedged, 0);
3883 }
3884
3885 mutex_lock(&dev->struct_mutex);
3886 dev_priv->mm.suspended = 0;
3887
3888 ret = i915_gem_init_ringbuffer(dev);
3889 if (ret != 0) {
3890 mutex_unlock(&dev->struct_mutex);
3891 return ret;
3892 }
3893
3894 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3895 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3896 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3897 for (i = 0; i < I915_NUM_RINGS; i++) {
3898 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3899 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3900 }
3901 mutex_unlock(&dev->struct_mutex);
3902
3903 ret = drm_irq_install(dev);
3904 if (ret)
3905 goto cleanup_ringbuffer;
3906
3907 return 0;
3908
3909cleanup_ringbuffer:
3910 mutex_lock(&dev->struct_mutex);
3911 i915_gem_cleanup_ringbuffer(dev);
3912 dev_priv->mm.suspended = 1;
3913 mutex_unlock(&dev->struct_mutex);
3914
3915 return ret;
3916}
3917
3918int
3919i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3920 struct drm_file *file_priv)
3921{
3922 if (drm_core_check_feature(dev, DRIVER_MODESET))
3923 return 0;
3924
3925 drm_irq_uninstall(dev);
3926 return i915_gem_idle(dev);
3927}
3928
3929void
3930i915_gem_lastclose(struct drm_device *dev)
3931{
3932 int ret;
3933
3934 if (drm_core_check_feature(dev, DRIVER_MODESET))
3935 return;
3936
3937 ret = i915_gem_idle(dev);
3938 if (ret)
3939 DRM_ERROR("failed to idle hardware: %d\n", ret);
3940}
3941
3942static void
3943init_ring_lists(struct intel_ring_buffer *ring)
3944{
3945 INIT_LIST_HEAD(&ring->active_list);
3946 INIT_LIST_HEAD(&ring->request_list);
3947 INIT_LIST_HEAD(&ring->gpu_write_list);
3948}
3949
3950void
3951i915_gem_load(struct drm_device *dev)
3952{
3953 int i;
3954 drm_i915_private_t *dev_priv = dev->dev_private;
3955
3956 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3957 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3958 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3959 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
3960 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3961 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
3962 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3963 for (i = 0; i < I915_NUM_RINGS; i++)
3964 init_ring_lists(&dev_priv->ring[i]);
3965 for (i = 0; i < 16; i++)
3966 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3967 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3968 i915_gem_retire_work_handler);
3969 init_completion(&dev_priv->error_completion);
3970
3971 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3972 if (IS_GEN3(dev)) {
3973 u32 tmp = I915_READ(MI_ARB_STATE);
3974 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3975 /* arb state is a masked write, so set bit + bit in mask */
3976 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3977 I915_WRITE(MI_ARB_STATE, tmp);
3978 }
3979 }
3980
3981 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3982
3983 /* Old X drivers will take 0-2 for front, back, depth buffers */
3984 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3985 dev_priv->fence_reg_start = 3;
3986
3987 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3988 dev_priv->num_fence_regs = 16;
3989 else
3990 dev_priv->num_fence_regs = 8;
3991
3992 /* Initialize fence registers to zero */
3993 for (i = 0; i < dev_priv->num_fence_regs; i++) {
3994 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
3995 }
3996
3997 i915_gem_detect_bit_6_swizzle(dev);
3998 init_waitqueue_head(&dev_priv->pending_flip_queue);
3999
4000 dev_priv->mm.interruptible = true;
4001
4002 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4003 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4004 register_shrinker(&dev_priv->mm.inactive_shrinker);
4005}
4006
4007/*
4008 * Create a physically contiguous memory object for this object
4009 * e.g. for cursor + overlay regs
4010 */
4011static int i915_gem_init_phys_object(struct drm_device *dev,
4012 int id, int size, int align)
4013{
4014 drm_i915_private_t *dev_priv = dev->dev_private;
4015 struct drm_i915_gem_phys_object *phys_obj;
4016 int ret;
4017
4018 if (dev_priv->mm.phys_objs[id - 1] || !size)
4019 return 0;
4020
4021 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4022 if (!phys_obj)
4023 return -ENOMEM;
4024
4025 phys_obj->id = id;
4026
4027 phys_obj->handle = drm_pci_alloc(dev, size, align);
4028 if (!phys_obj->handle) {
4029 ret = -ENOMEM;
4030 goto kfree_obj;
4031 }
4032#ifdef CONFIG_X86
4033 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4034#endif
4035
4036 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4037
4038 return 0;
4039kfree_obj:
4040 kfree(phys_obj);
4041 return ret;
4042}
4043
4044static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4045{
4046 drm_i915_private_t *dev_priv = dev->dev_private;
4047 struct drm_i915_gem_phys_object *phys_obj;
4048
4049 if (!dev_priv->mm.phys_objs[id - 1])
4050 return;
4051
4052 phys_obj = dev_priv->mm.phys_objs[id - 1];
4053 if (phys_obj->cur_obj) {
4054 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4055 }
4056
4057#ifdef CONFIG_X86
4058 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4059#endif
4060 drm_pci_free(dev, phys_obj->handle);
4061 kfree(phys_obj);
4062 dev_priv->mm.phys_objs[id - 1] = NULL;
4063}
4064
4065void i915_gem_free_all_phys_object(struct drm_device *dev)
4066{
4067 int i;
4068
4069 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4070 i915_gem_free_phys_object(dev, i);
4071}
4072
4073void i915_gem_detach_phys_object(struct drm_device *dev,
4074 struct drm_i915_gem_object *obj)
4075{
4076 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4077 char *vaddr;
4078 int i;
4079 int page_count;
4080
4081 if (!obj->phys_obj)
4082 return;
4083 vaddr = obj->phys_obj->handle->vaddr;
4084
4085 page_count = obj->base.size / PAGE_SIZE;
4086 for (i = 0; i < page_count; i++) {
4087 struct page *page = shmem_read_mapping_page(mapping, i);
4088 if (!IS_ERR(page)) {
4089 char *dst = kmap_atomic(page);
4090 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4091 kunmap_atomic(dst);
4092
4093 drm_clflush_pages(&page, 1);
4094
4095 set_page_dirty(page);
4096 mark_page_accessed(page);
4097 page_cache_release(page);
4098 }
4099 }
4100 intel_gtt_chipset_flush();
4101
4102 obj->phys_obj->cur_obj = NULL;
4103 obj->phys_obj = NULL;
4104}
4105
4106int
4107i915_gem_attach_phys_object(struct drm_device *dev,
4108 struct drm_i915_gem_object *obj,
4109 int id,
4110 int align)
4111{
4112 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4113 drm_i915_private_t *dev_priv = dev->dev_private;
4114 int ret = 0;
4115 int page_count;
4116 int i;
4117
4118 if (id > I915_MAX_PHYS_OBJECT)
4119 return -EINVAL;
4120
4121 if (obj->phys_obj) {
4122 if (obj->phys_obj->id == id)
4123 return 0;
4124 i915_gem_detach_phys_object(dev, obj);
4125 }
4126
4127 /* create a new object */
4128 if (!dev_priv->mm.phys_objs[id - 1]) {
4129 ret = i915_gem_init_phys_object(dev, id,
4130 obj->base.size, align);
4131 if (ret) {
4132 DRM_ERROR("failed to init phys object %d size: %zu\n",
4133 id, obj->base.size);
4134 return ret;
4135 }
4136 }
4137
4138 /* bind to the object */
4139 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4140 obj->phys_obj->cur_obj = obj;
4141
4142 page_count = obj->base.size / PAGE_SIZE;
4143
4144 for (i = 0; i < page_count; i++) {
4145 struct page *page;
4146 char *dst, *src;
4147
4148 page = shmem_read_mapping_page(mapping, i);
4149 if (IS_ERR(page))
4150 return PTR_ERR(page);
4151
4152 src = kmap_atomic(page);
4153 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4154 memcpy(dst, src, PAGE_SIZE);
4155 kunmap_atomic(src);
4156
4157 mark_page_accessed(page);
4158 page_cache_release(page);
4159 }
4160
4161 return 0;
4162}
4163
4164static int
4165i915_gem_phys_pwrite(struct drm_device *dev,
4166 struct drm_i915_gem_object *obj,
4167 struct drm_i915_gem_pwrite *args,
4168 struct drm_file *file_priv)
4169{
4170 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4171 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4172
4173 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4174 unsigned long unwritten;
4175
4176 /* The physical object once assigned is fixed for the lifetime
4177 * of the obj, so we can safely drop the lock and continue
4178 * to access vaddr.
4179 */
4180 mutex_unlock(&dev->struct_mutex);
4181 unwritten = copy_from_user(vaddr, user_data, args->size);
4182 mutex_lock(&dev->struct_mutex);
4183 if (unwritten)
4184 return -EFAULT;
4185 }
4186
4187 intel_gtt_chipset_flush();
4188 return 0;
4189}
4190
4191void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4192{
4193 struct drm_i915_file_private *file_priv = file->driver_priv;
4194
4195 /* Clean up our request list when the client is going away, so that
4196 * later retire_requests won't dereference our soon-to-be-gone
4197 * file_priv.
4198 */
4199 spin_lock(&file_priv->mm.lock);
4200 while (!list_empty(&file_priv->mm.request_list)) {
4201 struct drm_i915_gem_request *request;
4202
4203 request = list_first_entry(&file_priv->mm.request_list,
4204 struct drm_i915_gem_request,
4205 client_list);
4206 list_del(&request->client_list);
4207 request->file_priv = NULL;
4208 }
4209 spin_unlock(&file_priv->mm.lock);
4210}
4211
4212static int
4213i915_gpu_is_active(struct drm_device *dev)
4214{
4215 drm_i915_private_t *dev_priv = dev->dev_private;
4216 int lists_empty;
4217
4218 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4219 list_empty(&dev_priv->mm.active_list);
4220
4221 return !lists_empty;
4222}
4223
4224static int
4225i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4226{
4227 struct drm_i915_private *dev_priv =
4228 container_of(shrinker,
4229 struct drm_i915_private,
4230 mm.inactive_shrinker);
4231 struct drm_device *dev = dev_priv->dev;
4232 struct drm_i915_gem_object *obj, *next;
4233 int nr_to_scan = sc->nr_to_scan;
4234 int cnt;
4235
4236 if (!mutex_trylock(&dev->struct_mutex))
4237 return 0;
4238
4239 /* "fast-path" to count number of available objects */
4240 if (nr_to_scan == 0) {
4241 cnt = 0;
4242 list_for_each_entry(obj,
4243 &dev_priv->mm.inactive_list,
4244 mm_list)
4245 cnt++;
4246 mutex_unlock(&dev->struct_mutex);
4247 return cnt / 100 * sysctl_vfs_cache_pressure;
4248 }
4249
4250rescan:
4251 /* first scan for clean buffers */
4252 i915_gem_retire_requests(dev);
4253
4254 list_for_each_entry_safe(obj, next,
4255 &dev_priv->mm.inactive_list,
4256 mm_list) {
4257 if (i915_gem_object_is_purgeable(obj)) {
4258 if (i915_gem_object_unbind(obj) == 0 &&
4259 --nr_to_scan == 0)
4260 break;
4261 }
4262 }
4263
4264 /* second pass, evict/count anything still on the inactive list */
4265 cnt = 0;
4266 list_for_each_entry_safe(obj, next,
4267 &dev_priv->mm.inactive_list,
4268 mm_list) {
4269 if (nr_to_scan &&
4270 i915_gem_object_unbind(obj) == 0)
4271 nr_to_scan--;
4272 else
4273 cnt++;
4274 }
4275
4276 if (nr_to_scan && i915_gpu_is_active(dev)) {
4277 /*
4278 * We are desperate for pages, so as a last resort, wait
4279 * for the GPU to finish and discard whatever we can.
4280 * This has a dramatic impact to reduce the number of
4281 * OOM-killer events whilst running the GPU aggressively.
4282 */
4283 if (i915_gpu_idle(dev) == 0)
4284 goto rescan;
4285 }
4286 mutex_unlock(&dev->struct_mutex);
4287 return cnt / 100 * sysctl_vfs_cache_pressure;
4288}
1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32#include "i915_trace.h"
33#include "intel_drv.h"
34#include <linux/shmem_fs.h>
35#include <linux/slab.h>
36#include <linux/swap.h>
37#include <linux/pci.h>
38#include <linux/dma-buf.h>
39
40static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
41static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
43static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
44 unsigned alignment,
45 bool map_and_fenceable);
46static int i915_gem_phys_pwrite(struct drm_device *dev,
47 struct drm_i915_gem_object *obj,
48 struct drm_i915_gem_pwrite *args,
49 struct drm_file *file);
50
51static void i915_gem_write_fence(struct drm_device *dev, int reg,
52 struct drm_i915_gem_object *obj);
53static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
54 struct drm_i915_fence_reg *fence,
55 bool enable);
56
57static int i915_gem_inactive_shrink(struct shrinker *shrinker,
58 struct shrink_control *sc);
59static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
60
61static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
62{
63 if (obj->tiling_mode)
64 i915_gem_release_mmap(obj);
65
66 /* As we do not have an associated fence register, we will force
67 * a tiling change if we ever need to acquire one.
68 */
69 obj->fence_dirty = false;
70 obj->fence_reg = I915_FENCE_REG_NONE;
71}
72
73/* some bookkeeping */
74static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
75 size_t size)
76{
77 dev_priv->mm.object_count++;
78 dev_priv->mm.object_memory += size;
79}
80
81static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
82 size_t size)
83{
84 dev_priv->mm.object_count--;
85 dev_priv->mm.object_memory -= size;
86}
87
88static int
89i915_gem_wait_for_error(struct drm_device *dev)
90{
91 struct drm_i915_private *dev_priv = dev->dev_private;
92 struct completion *x = &dev_priv->error_completion;
93 unsigned long flags;
94 int ret;
95
96 if (!atomic_read(&dev_priv->mm.wedged))
97 return 0;
98
99 ret = wait_for_completion_interruptible(x);
100 if (ret)
101 return ret;
102
103 if (atomic_read(&dev_priv->mm.wedged)) {
104 /* GPU is hung, bump the completion count to account for
105 * the token we just consumed so that we never hit zero and
106 * end up waiting upon a subsequent completion event that
107 * will never happen.
108 */
109 spin_lock_irqsave(&x->wait.lock, flags);
110 x->done++;
111 spin_unlock_irqrestore(&x->wait.lock, flags);
112 }
113 return 0;
114}
115
116int i915_mutex_lock_interruptible(struct drm_device *dev)
117{
118 int ret;
119
120 ret = i915_gem_wait_for_error(dev);
121 if (ret)
122 return ret;
123
124 ret = mutex_lock_interruptible(&dev->struct_mutex);
125 if (ret)
126 return ret;
127
128 WARN_ON(i915_verify_lists(dev));
129 return 0;
130}
131
132static inline bool
133i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
134{
135 return !obj->active;
136}
137
138int
139i915_gem_init_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file)
141{
142 struct drm_i915_gem_init *args = data;
143
144 if (drm_core_check_feature(dev, DRIVER_MODESET))
145 return -ENODEV;
146
147 if (args->gtt_start >= args->gtt_end ||
148 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
149 return -EINVAL;
150
151 /* GEM with user mode setting was never supported on ilk and later. */
152 if (INTEL_INFO(dev)->gen >= 5)
153 return -ENODEV;
154
155 mutex_lock(&dev->struct_mutex);
156 i915_gem_init_global_gtt(dev, args->gtt_start,
157 args->gtt_end, args->gtt_end);
158 mutex_unlock(&dev->struct_mutex);
159
160 return 0;
161}
162
163int
164i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
166{
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_get_aperture *args = data;
169 struct drm_i915_gem_object *obj;
170 size_t pinned;
171
172 pinned = 0;
173 mutex_lock(&dev->struct_mutex);
174 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
175 if (obj->pin_count)
176 pinned += obj->gtt_space->size;
177 mutex_unlock(&dev->struct_mutex);
178
179 args->aper_size = dev_priv->mm.gtt_total;
180 args->aper_available_size = args->aper_size - pinned;
181
182 return 0;
183}
184
185static int
186i915_gem_create(struct drm_file *file,
187 struct drm_device *dev,
188 uint64_t size,
189 uint32_t *handle_p)
190{
191 struct drm_i915_gem_object *obj;
192 int ret;
193 u32 handle;
194
195 size = roundup(size, PAGE_SIZE);
196 if (size == 0)
197 return -EINVAL;
198
199 /* Allocate the new object */
200 obj = i915_gem_alloc_object(dev, size);
201 if (obj == NULL)
202 return -ENOMEM;
203
204 ret = drm_gem_handle_create(file, &obj->base, &handle);
205 if (ret) {
206 drm_gem_object_release(&obj->base);
207 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
208 kfree(obj);
209 return ret;
210 }
211
212 /* drop reference from allocate - handle holds it now */
213 drm_gem_object_unreference(&obj->base);
214 trace_i915_gem_object_create(obj);
215
216 *handle_p = handle;
217 return 0;
218}
219
220int
221i915_gem_dumb_create(struct drm_file *file,
222 struct drm_device *dev,
223 struct drm_mode_create_dumb *args)
224{
225 /* have to work out size/pitch and return them */
226 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
227 args->size = args->pitch * args->height;
228 return i915_gem_create(file, dev,
229 args->size, &args->handle);
230}
231
232int i915_gem_dumb_destroy(struct drm_file *file,
233 struct drm_device *dev,
234 uint32_t handle)
235{
236 return drm_gem_handle_delete(file, handle);
237}
238
239/**
240 * Creates a new mm object and returns a handle to it.
241 */
242int
243i915_gem_create_ioctl(struct drm_device *dev, void *data,
244 struct drm_file *file)
245{
246 struct drm_i915_gem_create *args = data;
247
248 return i915_gem_create(file, dev,
249 args->size, &args->handle);
250}
251
252static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
253{
254 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
255
256 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
257 obj->tiling_mode != I915_TILING_NONE;
258}
259
260static inline int
261__copy_to_user_swizzled(char __user *cpu_vaddr,
262 const char *gpu_vaddr, int gpu_offset,
263 int length)
264{
265 int ret, cpu_offset = 0;
266
267 while (length > 0) {
268 int cacheline_end = ALIGN(gpu_offset + 1, 64);
269 int this_length = min(cacheline_end - gpu_offset, length);
270 int swizzled_gpu_offset = gpu_offset ^ 64;
271
272 ret = __copy_to_user(cpu_vaddr + cpu_offset,
273 gpu_vaddr + swizzled_gpu_offset,
274 this_length);
275 if (ret)
276 return ret + length;
277
278 cpu_offset += this_length;
279 gpu_offset += this_length;
280 length -= this_length;
281 }
282
283 return 0;
284}
285
286static inline int
287__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
288 const char __user *cpu_vaddr,
289 int length)
290{
291 int ret, cpu_offset = 0;
292
293 while (length > 0) {
294 int cacheline_end = ALIGN(gpu_offset + 1, 64);
295 int this_length = min(cacheline_end - gpu_offset, length);
296 int swizzled_gpu_offset = gpu_offset ^ 64;
297
298 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
299 cpu_vaddr + cpu_offset,
300 this_length);
301 if (ret)
302 return ret + length;
303
304 cpu_offset += this_length;
305 gpu_offset += this_length;
306 length -= this_length;
307 }
308
309 return 0;
310}
311
312/* Per-page copy function for the shmem pread fastpath.
313 * Flushes invalid cachelines before reading the target if
314 * needs_clflush is set. */
315static int
316shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
317 char __user *user_data,
318 bool page_do_bit17_swizzling, bool needs_clflush)
319{
320 char *vaddr;
321 int ret;
322
323 if (unlikely(page_do_bit17_swizzling))
324 return -EINVAL;
325
326 vaddr = kmap_atomic(page);
327 if (needs_clflush)
328 drm_clflush_virt_range(vaddr + shmem_page_offset,
329 page_length);
330 ret = __copy_to_user_inatomic(user_data,
331 vaddr + shmem_page_offset,
332 page_length);
333 kunmap_atomic(vaddr);
334
335 return ret;
336}
337
338static void
339shmem_clflush_swizzled_range(char *addr, unsigned long length,
340 bool swizzled)
341{
342 if (unlikely(swizzled)) {
343 unsigned long start = (unsigned long) addr;
344 unsigned long end = (unsigned long) addr + length;
345
346 /* For swizzling simply ensure that we always flush both
347 * channels. Lame, but simple and it works. Swizzled
348 * pwrite/pread is far from a hotpath - current userspace
349 * doesn't use it at all. */
350 start = round_down(start, 128);
351 end = round_up(end, 128);
352
353 drm_clflush_virt_range((void *)start, end - start);
354 } else {
355 drm_clflush_virt_range(addr, length);
356 }
357
358}
359
360/* Only difference to the fast-path function is that this can handle bit17
361 * and uses non-atomic copy and kmap functions. */
362static int
363shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
364 char __user *user_data,
365 bool page_do_bit17_swizzling, bool needs_clflush)
366{
367 char *vaddr;
368 int ret;
369
370 vaddr = kmap(page);
371 if (needs_clflush)
372 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
373 page_length,
374 page_do_bit17_swizzling);
375
376 if (page_do_bit17_swizzling)
377 ret = __copy_to_user_swizzled(user_data,
378 vaddr, shmem_page_offset,
379 page_length);
380 else
381 ret = __copy_to_user(user_data,
382 vaddr + shmem_page_offset,
383 page_length);
384 kunmap(page);
385
386 return ret;
387}
388
389static int
390i915_gem_shmem_pread(struct drm_device *dev,
391 struct drm_i915_gem_object *obj,
392 struct drm_i915_gem_pread *args,
393 struct drm_file *file)
394{
395 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
396 char __user *user_data;
397 ssize_t remain;
398 loff_t offset;
399 int shmem_page_offset, page_length, ret = 0;
400 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
401 int hit_slowpath = 0;
402 int prefaulted = 0;
403 int needs_clflush = 0;
404 int release_page;
405
406 user_data = (char __user *) (uintptr_t) args->data_ptr;
407 remain = args->size;
408
409 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
410
411 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
412 /* If we're not in the cpu read domain, set ourself into the gtt
413 * read domain and manually flush cachelines (if required). This
414 * optimizes for the case when the gpu will dirty the data
415 * anyway again before the next pread happens. */
416 if (obj->cache_level == I915_CACHE_NONE)
417 needs_clflush = 1;
418 ret = i915_gem_object_set_to_gtt_domain(obj, false);
419 if (ret)
420 return ret;
421 }
422
423 offset = args->offset;
424
425 while (remain > 0) {
426 struct page *page;
427
428 /* Operation in this page
429 *
430 * shmem_page_offset = offset within page in shmem file
431 * page_length = bytes to copy for this page
432 */
433 shmem_page_offset = offset_in_page(offset);
434 page_length = remain;
435 if ((shmem_page_offset + page_length) > PAGE_SIZE)
436 page_length = PAGE_SIZE - shmem_page_offset;
437
438 if (obj->pages) {
439 page = obj->pages[offset >> PAGE_SHIFT];
440 release_page = 0;
441 } else {
442 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
443 if (IS_ERR(page)) {
444 ret = PTR_ERR(page);
445 goto out;
446 }
447 release_page = 1;
448 }
449
450 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
451 (page_to_phys(page) & (1 << 17)) != 0;
452
453 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
454 user_data, page_do_bit17_swizzling,
455 needs_clflush);
456 if (ret == 0)
457 goto next_page;
458
459 hit_slowpath = 1;
460 page_cache_get(page);
461 mutex_unlock(&dev->struct_mutex);
462
463 if (!prefaulted) {
464 ret = fault_in_multipages_writeable(user_data, remain);
465 /* Userspace is tricking us, but we've already clobbered
466 * its pages with the prefault and promised to write the
467 * data up to the first fault. Hence ignore any errors
468 * and just continue. */
469 (void)ret;
470 prefaulted = 1;
471 }
472
473 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
474 user_data, page_do_bit17_swizzling,
475 needs_clflush);
476
477 mutex_lock(&dev->struct_mutex);
478 page_cache_release(page);
479next_page:
480 mark_page_accessed(page);
481 if (release_page)
482 page_cache_release(page);
483
484 if (ret) {
485 ret = -EFAULT;
486 goto out;
487 }
488
489 remain -= page_length;
490 user_data += page_length;
491 offset += page_length;
492 }
493
494out:
495 if (hit_slowpath) {
496 /* Fixup: Kill any reinstated backing storage pages */
497 if (obj->madv == __I915_MADV_PURGED)
498 i915_gem_object_truncate(obj);
499 }
500
501 return ret;
502}
503
504/**
505 * Reads data from the object referenced by handle.
506 *
507 * On error, the contents of *data are undefined.
508 */
509int
510i915_gem_pread_ioctl(struct drm_device *dev, void *data,
511 struct drm_file *file)
512{
513 struct drm_i915_gem_pread *args = data;
514 struct drm_i915_gem_object *obj;
515 int ret = 0;
516
517 if (args->size == 0)
518 return 0;
519
520 if (!access_ok(VERIFY_WRITE,
521 (char __user *)(uintptr_t)args->data_ptr,
522 args->size))
523 return -EFAULT;
524
525 ret = i915_mutex_lock_interruptible(dev);
526 if (ret)
527 return ret;
528
529 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
530 if (&obj->base == NULL) {
531 ret = -ENOENT;
532 goto unlock;
533 }
534
535 /* Bounds check source. */
536 if (args->offset > obj->base.size ||
537 args->size > obj->base.size - args->offset) {
538 ret = -EINVAL;
539 goto out;
540 }
541
542 /* prime objects have no backing filp to GEM pread/pwrite
543 * pages from.
544 */
545 if (!obj->base.filp) {
546 ret = -EINVAL;
547 goto out;
548 }
549
550 trace_i915_gem_object_pread(obj, args->offset, args->size);
551
552 ret = i915_gem_shmem_pread(dev, obj, args, file);
553
554out:
555 drm_gem_object_unreference(&obj->base);
556unlock:
557 mutex_unlock(&dev->struct_mutex);
558 return ret;
559}
560
561/* This is the fast write path which cannot handle
562 * page faults in the source data
563 */
564
565static inline int
566fast_user_write(struct io_mapping *mapping,
567 loff_t page_base, int page_offset,
568 char __user *user_data,
569 int length)
570{
571 void __iomem *vaddr_atomic;
572 void *vaddr;
573 unsigned long unwritten;
574
575 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
576 /* We can use the cpu mem copy function because this is X86. */
577 vaddr = (void __force*)vaddr_atomic + page_offset;
578 unwritten = __copy_from_user_inatomic_nocache(vaddr,
579 user_data, length);
580 io_mapping_unmap_atomic(vaddr_atomic);
581 return unwritten;
582}
583
584/**
585 * This is the fast pwrite path, where we copy the data directly from the
586 * user into the GTT, uncached.
587 */
588static int
589i915_gem_gtt_pwrite_fast(struct drm_device *dev,
590 struct drm_i915_gem_object *obj,
591 struct drm_i915_gem_pwrite *args,
592 struct drm_file *file)
593{
594 drm_i915_private_t *dev_priv = dev->dev_private;
595 ssize_t remain;
596 loff_t offset, page_base;
597 char __user *user_data;
598 int page_offset, page_length, ret;
599
600 ret = i915_gem_object_pin(obj, 0, true);
601 if (ret)
602 goto out;
603
604 ret = i915_gem_object_set_to_gtt_domain(obj, true);
605 if (ret)
606 goto out_unpin;
607
608 ret = i915_gem_object_put_fence(obj);
609 if (ret)
610 goto out_unpin;
611
612 user_data = (char __user *) (uintptr_t) args->data_ptr;
613 remain = args->size;
614
615 offset = obj->gtt_offset + args->offset;
616
617 while (remain > 0) {
618 /* Operation in this page
619 *
620 * page_base = page offset within aperture
621 * page_offset = offset within page
622 * page_length = bytes to copy for this page
623 */
624 page_base = offset & PAGE_MASK;
625 page_offset = offset_in_page(offset);
626 page_length = remain;
627 if ((page_offset + remain) > PAGE_SIZE)
628 page_length = PAGE_SIZE - page_offset;
629
630 /* If we get a fault while copying data, then (presumably) our
631 * source page isn't available. Return the error and we'll
632 * retry in the slow path.
633 */
634 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
635 page_offset, user_data, page_length)) {
636 ret = -EFAULT;
637 goto out_unpin;
638 }
639
640 remain -= page_length;
641 user_data += page_length;
642 offset += page_length;
643 }
644
645out_unpin:
646 i915_gem_object_unpin(obj);
647out:
648 return ret;
649}
650
651/* Per-page copy function for the shmem pwrite fastpath.
652 * Flushes invalid cachelines before writing to the target if
653 * needs_clflush_before is set and flushes out any written cachelines after
654 * writing if needs_clflush is set. */
655static int
656shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
657 char __user *user_data,
658 bool page_do_bit17_swizzling,
659 bool needs_clflush_before,
660 bool needs_clflush_after)
661{
662 char *vaddr;
663 int ret;
664
665 if (unlikely(page_do_bit17_swizzling))
666 return -EINVAL;
667
668 vaddr = kmap_atomic(page);
669 if (needs_clflush_before)
670 drm_clflush_virt_range(vaddr + shmem_page_offset,
671 page_length);
672 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
673 user_data,
674 page_length);
675 if (needs_clflush_after)
676 drm_clflush_virt_range(vaddr + shmem_page_offset,
677 page_length);
678 kunmap_atomic(vaddr);
679
680 return ret;
681}
682
683/* Only difference to the fast-path function is that this can handle bit17
684 * and uses non-atomic copy and kmap functions. */
685static int
686shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
687 char __user *user_data,
688 bool page_do_bit17_swizzling,
689 bool needs_clflush_before,
690 bool needs_clflush_after)
691{
692 char *vaddr;
693 int ret;
694
695 vaddr = kmap(page);
696 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
697 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
698 page_length,
699 page_do_bit17_swizzling);
700 if (page_do_bit17_swizzling)
701 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
702 user_data,
703 page_length);
704 else
705 ret = __copy_from_user(vaddr + shmem_page_offset,
706 user_data,
707 page_length);
708 if (needs_clflush_after)
709 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
710 page_length,
711 page_do_bit17_swizzling);
712 kunmap(page);
713
714 return ret;
715}
716
717static int
718i915_gem_shmem_pwrite(struct drm_device *dev,
719 struct drm_i915_gem_object *obj,
720 struct drm_i915_gem_pwrite *args,
721 struct drm_file *file)
722{
723 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
724 ssize_t remain;
725 loff_t offset;
726 char __user *user_data;
727 int shmem_page_offset, page_length, ret = 0;
728 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
729 int hit_slowpath = 0;
730 int needs_clflush_after = 0;
731 int needs_clflush_before = 0;
732 int release_page;
733
734 user_data = (char __user *) (uintptr_t) args->data_ptr;
735 remain = args->size;
736
737 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
738
739 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
740 /* If we're not in the cpu write domain, set ourself into the gtt
741 * write domain and manually flush cachelines (if required). This
742 * optimizes for the case when the gpu will use the data
743 * right away and we therefore have to clflush anyway. */
744 if (obj->cache_level == I915_CACHE_NONE)
745 needs_clflush_after = 1;
746 ret = i915_gem_object_set_to_gtt_domain(obj, true);
747 if (ret)
748 return ret;
749 }
750 /* Same trick applies for invalidate partially written cachelines before
751 * writing. */
752 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
753 && obj->cache_level == I915_CACHE_NONE)
754 needs_clflush_before = 1;
755
756 offset = args->offset;
757 obj->dirty = 1;
758
759 while (remain > 0) {
760 struct page *page;
761 int partial_cacheline_write;
762
763 /* Operation in this page
764 *
765 * shmem_page_offset = offset within page in shmem file
766 * page_length = bytes to copy for this page
767 */
768 shmem_page_offset = offset_in_page(offset);
769
770 page_length = remain;
771 if ((shmem_page_offset + page_length) > PAGE_SIZE)
772 page_length = PAGE_SIZE - shmem_page_offset;
773
774 /* If we don't overwrite a cacheline completely we need to be
775 * careful to have up-to-date data by first clflushing. Don't
776 * overcomplicate things and flush the entire patch. */
777 partial_cacheline_write = needs_clflush_before &&
778 ((shmem_page_offset | page_length)
779 & (boot_cpu_data.x86_clflush_size - 1));
780
781 if (obj->pages) {
782 page = obj->pages[offset >> PAGE_SHIFT];
783 release_page = 0;
784 } else {
785 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
786 if (IS_ERR(page)) {
787 ret = PTR_ERR(page);
788 goto out;
789 }
790 release_page = 1;
791 }
792
793 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
794 (page_to_phys(page) & (1 << 17)) != 0;
795
796 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
797 user_data, page_do_bit17_swizzling,
798 partial_cacheline_write,
799 needs_clflush_after);
800 if (ret == 0)
801 goto next_page;
802
803 hit_slowpath = 1;
804 page_cache_get(page);
805 mutex_unlock(&dev->struct_mutex);
806
807 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
808 user_data, page_do_bit17_swizzling,
809 partial_cacheline_write,
810 needs_clflush_after);
811
812 mutex_lock(&dev->struct_mutex);
813 page_cache_release(page);
814next_page:
815 set_page_dirty(page);
816 mark_page_accessed(page);
817 if (release_page)
818 page_cache_release(page);
819
820 if (ret) {
821 ret = -EFAULT;
822 goto out;
823 }
824
825 remain -= page_length;
826 user_data += page_length;
827 offset += page_length;
828 }
829
830out:
831 if (hit_slowpath) {
832 /* Fixup: Kill any reinstated backing storage pages */
833 if (obj->madv == __I915_MADV_PURGED)
834 i915_gem_object_truncate(obj);
835 /* and flush dirty cachelines in case the object isn't in the cpu write
836 * domain anymore. */
837 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
838 i915_gem_clflush_object(obj);
839 intel_gtt_chipset_flush();
840 }
841 }
842
843 if (needs_clflush_after)
844 intel_gtt_chipset_flush();
845
846 return ret;
847}
848
849/**
850 * Writes data to the object referenced by handle.
851 *
852 * On error, the contents of the buffer that were to be modified are undefined.
853 */
854int
855i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file)
857{
858 struct drm_i915_gem_pwrite *args = data;
859 struct drm_i915_gem_object *obj;
860 int ret;
861
862 if (args->size == 0)
863 return 0;
864
865 if (!access_ok(VERIFY_READ,
866 (char __user *)(uintptr_t)args->data_ptr,
867 args->size))
868 return -EFAULT;
869
870 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
871 args->size);
872 if (ret)
873 return -EFAULT;
874
875 ret = i915_mutex_lock_interruptible(dev);
876 if (ret)
877 return ret;
878
879 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
880 if (&obj->base == NULL) {
881 ret = -ENOENT;
882 goto unlock;
883 }
884
885 /* Bounds check destination. */
886 if (args->offset > obj->base.size ||
887 args->size > obj->base.size - args->offset) {
888 ret = -EINVAL;
889 goto out;
890 }
891
892 /* prime objects have no backing filp to GEM pread/pwrite
893 * pages from.
894 */
895 if (!obj->base.filp) {
896 ret = -EINVAL;
897 goto out;
898 }
899
900 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
901
902 ret = -EFAULT;
903 /* We can only do the GTT pwrite on untiled buffers, as otherwise
904 * it would end up going through the fenced access, and we'll get
905 * different detiling behavior between reading and writing.
906 * pread/pwrite currently are reading and writing from the CPU
907 * perspective, requiring manual detiling by the client.
908 */
909 if (obj->phys_obj) {
910 ret = i915_gem_phys_pwrite(dev, obj, args, file);
911 goto out;
912 }
913
914 if (obj->gtt_space &&
915 obj->cache_level == I915_CACHE_NONE &&
916 obj->tiling_mode == I915_TILING_NONE &&
917 obj->map_and_fenceable &&
918 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
919 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
920 /* Note that the gtt paths might fail with non-page-backed user
921 * pointers (e.g. gtt mappings when moving data between
922 * textures). Fallback to the shmem path in that case. */
923 }
924
925 if (ret == -EFAULT)
926 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
927
928out:
929 drm_gem_object_unreference(&obj->base);
930unlock:
931 mutex_unlock(&dev->struct_mutex);
932 return ret;
933}
934
935/**
936 * Called when user space prepares to use an object with the CPU, either
937 * through the mmap ioctl's mapping or a GTT mapping.
938 */
939int
940i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
941 struct drm_file *file)
942{
943 struct drm_i915_gem_set_domain *args = data;
944 struct drm_i915_gem_object *obj;
945 uint32_t read_domains = args->read_domains;
946 uint32_t write_domain = args->write_domain;
947 int ret;
948
949 /* Only handle setting domains to types used by the CPU. */
950 if (write_domain & I915_GEM_GPU_DOMAINS)
951 return -EINVAL;
952
953 if (read_domains & I915_GEM_GPU_DOMAINS)
954 return -EINVAL;
955
956 /* Having something in the write domain implies it's in the read
957 * domain, and only that read domain. Enforce that in the request.
958 */
959 if (write_domain != 0 && read_domains != write_domain)
960 return -EINVAL;
961
962 ret = i915_mutex_lock_interruptible(dev);
963 if (ret)
964 return ret;
965
966 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
967 if (&obj->base == NULL) {
968 ret = -ENOENT;
969 goto unlock;
970 }
971
972 if (read_domains & I915_GEM_DOMAIN_GTT) {
973 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
974
975 /* Silently promote "you're not bound, there was nothing to do"
976 * to success, since the client was just asking us to
977 * make sure everything was done.
978 */
979 if (ret == -EINVAL)
980 ret = 0;
981 } else {
982 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
983 }
984
985 drm_gem_object_unreference(&obj->base);
986unlock:
987 mutex_unlock(&dev->struct_mutex);
988 return ret;
989}
990
991/**
992 * Called when user space has done writes to this buffer
993 */
994int
995i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file)
997{
998 struct drm_i915_gem_sw_finish *args = data;
999 struct drm_i915_gem_object *obj;
1000 int ret = 0;
1001
1002 ret = i915_mutex_lock_interruptible(dev);
1003 if (ret)
1004 return ret;
1005
1006 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1007 if (&obj->base == NULL) {
1008 ret = -ENOENT;
1009 goto unlock;
1010 }
1011
1012 /* Pinned buffers may be scanout, so flush the cache */
1013 if (obj->pin_count)
1014 i915_gem_object_flush_cpu_write_domain(obj);
1015
1016 drm_gem_object_unreference(&obj->base);
1017unlock:
1018 mutex_unlock(&dev->struct_mutex);
1019 return ret;
1020}
1021
1022/**
1023 * Maps the contents of an object, returning the address it is mapped
1024 * into.
1025 *
1026 * While the mapping holds a reference on the contents of the object, it doesn't
1027 * imply a ref on the object itself.
1028 */
1029int
1030i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1031 struct drm_file *file)
1032{
1033 struct drm_i915_gem_mmap *args = data;
1034 struct drm_gem_object *obj;
1035 unsigned long addr;
1036
1037 obj = drm_gem_object_lookup(dev, file, args->handle);
1038 if (obj == NULL)
1039 return -ENOENT;
1040
1041 /* prime objects have no backing filp to GEM mmap
1042 * pages from.
1043 */
1044 if (!obj->filp) {
1045 drm_gem_object_unreference_unlocked(obj);
1046 return -EINVAL;
1047 }
1048
1049 addr = vm_mmap(obj->filp, 0, args->size,
1050 PROT_READ | PROT_WRITE, MAP_SHARED,
1051 args->offset);
1052 drm_gem_object_unreference_unlocked(obj);
1053 if (IS_ERR((void *)addr))
1054 return addr;
1055
1056 args->addr_ptr = (uint64_t) addr;
1057
1058 return 0;
1059}
1060
1061/**
1062 * i915_gem_fault - fault a page into the GTT
1063 * vma: VMA in question
1064 * vmf: fault info
1065 *
1066 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1067 * from userspace. The fault handler takes care of binding the object to
1068 * the GTT (if needed), allocating and programming a fence register (again,
1069 * only if needed based on whether the old reg is still valid or the object
1070 * is tiled) and inserting a new PTE into the faulting process.
1071 *
1072 * Note that the faulting process may involve evicting existing objects
1073 * from the GTT and/or fence registers to make room. So performance may
1074 * suffer if the GTT working set is large or there are few fence registers
1075 * left.
1076 */
1077int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1078{
1079 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1080 struct drm_device *dev = obj->base.dev;
1081 drm_i915_private_t *dev_priv = dev->dev_private;
1082 pgoff_t page_offset;
1083 unsigned long pfn;
1084 int ret = 0;
1085 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1086
1087 /* We don't use vmf->pgoff since that has the fake offset */
1088 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1089 PAGE_SHIFT;
1090
1091 ret = i915_mutex_lock_interruptible(dev);
1092 if (ret)
1093 goto out;
1094
1095 trace_i915_gem_object_fault(obj, page_offset, true, write);
1096
1097 /* Now bind it into the GTT if needed */
1098 if (!obj->map_and_fenceable) {
1099 ret = i915_gem_object_unbind(obj);
1100 if (ret)
1101 goto unlock;
1102 }
1103 if (!obj->gtt_space) {
1104 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1105 if (ret)
1106 goto unlock;
1107
1108 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1109 if (ret)
1110 goto unlock;
1111 }
1112
1113 if (!obj->has_global_gtt_mapping)
1114 i915_gem_gtt_bind_object(obj, obj->cache_level);
1115
1116 ret = i915_gem_object_get_fence(obj);
1117 if (ret)
1118 goto unlock;
1119
1120 if (i915_gem_object_is_inactive(obj))
1121 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1122
1123 obj->fault_mappable = true;
1124
1125 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1126 page_offset;
1127
1128 /* Finally, remap it using the new GTT offset */
1129 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1130unlock:
1131 mutex_unlock(&dev->struct_mutex);
1132out:
1133 switch (ret) {
1134 case -EIO:
1135 case -EAGAIN:
1136 /* Give the error handler a chance to run and move the
1137 * objects off the GPU active list. Next time we service the
1138 * fault, we should be able to transition the page into the
1139 * GTT without touching the GPU (and so avoid further
1140 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1141 * with coherency, just lost writes.
1142 */
1143 set_need_resched();
1144 case 0:
1145 case -ERESTARTSYS:
1146 case -EINTR:
1147 return VM_FAULT_NOPAGE;
1148 case -ENOMEM:
1149 return VM_FAULT_OOM;
1150 default:
1151 return VM_FAULT_SIGBUS;
1152 }
1153}
1154
1155/**
1156 * i915_gem_release_mmap - remove physical page mappings
1157 * @obj: obj in question
1158 *
1159 * Preserve the reservation of the mmapping with the DRM core code, but
1160 * relinquish ownership of the pages back to the system.
1161 *
1162 * It is vital that we remove the page mapping if we have mapped a tiled
1163 * object through the GTT and then lose the fence register due to
1164 * resource pressure. Similarly if the object has been moved out of the
1165 * aperture, than pages mapped into userspace must be revoked. Removing the
1166 * mapping will then trigger a page fault on the next user access, allowing
1167 * fixup by i915_gem_fault().
1168 */
1169void
1170i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1171{
1172 if (!obj->fault_mappable)
1173 return;
1174
1175 if (obj->base.dev->dev_mapping)
1176 unmap_mapping_range(obj->base.dev->dev_mapping,
1177 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1178 obj->base.size, 1);
1179
1180 obj->fault_mappable = false;
1181}
1182
1183static uint32_t
1184i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1185{
1186 uint32_t gtt_size;
1187
1188 if (INTEL_INFO(dev)->gen >= 4 ||
1189 tiling_mode == I915_TILING_NONE)
1190 return size;
1191
1192 /* Previous chips need a power-of-two fence region when tiling */
1193 if (INTEL_INFO(dev)->gen == 3)
1194 gtt_size = 1024*1024;
1195 else
1196 gtt_size = 512*1024;
1197
1198 while (gtt_size < size)
1199 gtt_size <<= 1;
1200
1201 return gtt_size;
1202}
1203
1204/**
1205 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1206 * @obj: object to check
1207 *
1208 * Return the required GTT alignment for an object, taking into account
1209 * potential fence register mapping.
1210 */
1211static uint32_t
1212i915_gem_get_gtt_alignment(struct drm_device *dev,
1213 uint32_t size,
1214 int tiling_mode)
1215{
1216 /*
1217 * Minimum alignment is 4k (GTT page size), but might be greater
1218 * if a fence register is needed for the object.
1219 */
1220 if (INTEL_INFO(dev)->gen >= 4 ||
1221 tiling_mode == I915_TILING_NONE)
1222 return 4096;
1223
1224 /*
1225 * Previous chips need to be aligned to the size of the smallest
1226 * fence register that can contain the object.
1227 */
1228 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1229}
1230
1231/**
1232 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1233 * unfenced object
1234 * @dev: the device
1235 * @size: size of the object
1236 * @tiling_mode: tiling mode of the object
1237 *
1238 * Return the required GTT alignment for an object, only taking into account
1239 * unfenced tiled surface requirements.
1240 */
1241uint32_t
1242i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1243 uint32_t size,
1244 int tiling_mode)
1245{
1246 /*
1247 * Minimum alignment is 4k (GTT page size) for sane hw.
1248 */
1249 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1250 tiling_mode == I915_TILING_NONE)
1251 return 4096;
1252
1253 /* Previous hardware however needs to be aligned to a power-of-two
1254 * tile height. The simplest method for determining this is to reuse
1255 * the power-of-tile object size.
1256 */
1257 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1258}
1259
1260int
1261i915_gem_mmap_gtt(struct drm_file *file,
1262 struct drm_device *dev,
1263 uint32_t handle,
1264 uint64_t *offset)
1265{
1266 struct drm_i915_private *dev_priv = dev->dev_private;
1267 struct drm_i915_gem_object *obj;
1268 int ret;
1269
1270 ret = i915_mutex_lock_interruptible(dev);
1271 if (ret)
1272 return ret;
1273
1274 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1275 if (&obj->base == NULL) {
1276 ret = -ENOENT;
1277 goto unlock;
1278 }
1279
1280 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1281 ret = -E2BIG;
1282 goto out;
1283 }
1284
1285 if (obj->madv != I915_MADV_WILLNEED) {
1286 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1287 ret = -EINVAL;
1288 goto out;
1289 }
1290
1291 if (!obj->base.map_list.map) {
1292 ret = drm_gem_create_mmap_offset(&obj->base);
1293 if (ret)
1294 goto out;
1295 }
1296
1297 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1298
1299out:
1300 drm_gem_object_unreference(&obj->base);
1301unlock:
1302 mutex_unlock(&dev->struct_mutex);
1303 return ret;
1304}
1305
1306/**
1307 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1308 * @dev: DRM device
1309 * @data: GTT mapping ioctl data
1310 * @file: GEM object info
1311 *
1312 * Simply returns the fake offset to userspace so it can mmap it.
1313 * The mmap call will end up in drm_gem_mmap(), which will set things
1314 * up so we can get faults in the handler above.
1315 *
1316 * The fault handler will take care of binding the object into the GTT
1317 * (since it may have been evicted to make room for something), allocating
1318 * a fence register, and mapping the appropriate aperture address into
1319 * userspace.
1320 */
1321int
1322i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1323 struct drm_file *file)
1324{
1325 struct drm_i915_gem_mmap_gtt *args = data;
1326
1327 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1328}
1329
1330int
1331i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1332 gfp_t gfpmask)
1333{
1334 int page_count, i;
1335 struct address_space *mapping;
1336 struct inode *inode;
1337 struct page *page;
1338
1339 if (obj->pages || obj->sg_table)
1340 return 0;
1341
1342 /* Get the list of pages out of our struct file. They'll be pinned
1343 * at this point until we release them.
1344 */
1345 page_count = obj->base.size / PAGE_SIZE;
1346 BUG_ON(obj->pages != NULL);
1347 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1348 if (obj->pages == NULL)
1349 return -ENOMEM;
1350
1351 inode = obj->base.filp->f_path.dentry->d_inode;
1352 mapping = inode->i_mapping;
1353 gfpmask |= mapping_gfp_mask(mapping);
1354
1355 for (i = 0; i < page_count; i++) {
1356 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1357 if (IS_ERR(page))
1358 goto err_pages;
1359
1360 obj->pages[i] = page;
1361 }
1362
1363 if (i915_gem_object_needs_bit17_swizzle(obj))
1364 i915_gem_object_do_bit_17_swizzle(obj);
1365
1366 return 0;
1367
1368err_pages:
1369 while (i--)
1370 page_cache_release(obj->pages[i]);
1371
1372 drm_free_large(obj->pages);
1373 obj->pages = NULL;
1374 return PTR_ERR(page);
1375}
1376
1377static void
1378i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1379{
1380 int page_count = obj->base.size / PAGE_SIZE;
1381 int i;
1382
1383 if (!obj->pages)
1384 return;
1385
1386 BUG_ON(obj->madv == __I915_MADV_PURGED);
1387
1388 if (i915_gem_object_needs_bit17_swizzle(obj))
1389 i915_gem_object_save_bit_17_swizzle(obj);
1390
1391 if (obj->madv == I915_MADV_DONTNEED)
1392 obj->dirty = 0;
1393
1394 for (i = 0; i < page_count; i++) {
1395 if (obj->dirty)
1396 set_page_dirty(obj->pages[i]);
1397
1398 if (obj->madv == I915_MADV_WILLNEED)
1399 mark_page_accessed(obj->pages[i]);
1400
1401 page_cache_release(obj->pages[i]);
1402 }
1403 obj->dirty = 0;
1404
1405 drm_free_large(obj->pages);
1406 obj->pages = NULL;
1407}
1408
1409void
1410i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1411 struct intel_ring_buffer *ring,
1412 u32 seqno)
1413{
1414 struct drm_device *dev = obj->base.dev;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416
1417 BUG_ON(ring == NULL);
1418 obj->ring = ring;
1419
1420 /* Add a reference if we're newly entering the active list. */
1421 if (!obj->active) {
1422 drm_gem_object_reference(&obj->base);
1423 obj->active = 1;
1424 }
1425
1426 /* Move from whatever list we were on to the tail of execution. */
1427 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1428 list_move_tail(&obj->ring_list, &ring->active_list);
1429
1430 obj->last_rendering_seqno = seqno;
1431
1432 if (obj->fenced_gpu_access) {
1433 obj->last_fenced_seqno = seqno;
1434
1435 /* Bump MRU to take account of the delayed flush */
1436 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1437 struct drm_i915_fence_reg *reg;
1438
1439 reg = &dev_priv->fence_regs[obj->fence_reg];
1440 list_move_tail(®->lru_list,
1441 &dev_priv->mm.fence_list);
1442 }
1443 }
1444}
1445
1446static void
1447i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1448{
1449 list_del_init(&obj->ring_list);
1450 obj->last_rendering_seqno = 0;
1451 obj->last_fenced_seqno = 0;
1452}
1453
1454static void
1455i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1456{
1457 struct drm_device *dev = obj->base.dev;
1458 drm_i915_private_t *dev_priv = dev->dev_private;
1459
1460 BUG_ON(!obj->active);
1461 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1462
1463 i915_gem_object_move_off_active(obj);
1464}
1465
1466static void
1467i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1468{
1469 struct drm_device *dev = obj->base.dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471
1472 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1473
1474 BUG_ON(!list_empty(&obj->gpu_write_list));
1475 BUG_ON(!obj->active);
1476 obj->ring = NULL;
1477
1478 i915_gem_object_move_off_active(obj);
1479 obj->fenced_gpu_access = false;
1480
1481 obj->active = 0;
1482 obj->pending_gpu_write = false;
1483 drm_gem_object_unreference(&obj->base);
1484
1485 WARN_ON(i915_verify_lists(dev));
1486}
1487
1488/* Immediately discard the backing storage */
1489static void
1490i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1491{
1492 struct inode *inode;
1493
1494 /* Our goal here is to return as much of the memory as
1495 * is possible back to the system as we are called from OOM.
1496 * To do this we must instruct the shmfs to drop all of its
1497 * backing pages, *now*.
1498 */
1499 inode = obj->base.filp->f_path.dentry->d_inode;
1500 shmem_truncate_range(inode, 0, (loff_t)-1);
1501
1502 if (obj->base.map_list.map)
1503 drm_gem_free_mmap_offset(&obj->base);
1504
1505 obj->madv = __I915_MADV_PURGED;
1506}
1507
1508static inline int
1509i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1510{
1511 return obj->madv == I915_MADV_DONTNEED;
1512}
1513
1514static void
1515i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1516 uint32_t flush_domains)
1517{
1518 struct drm_i915_gem_object *obj, *next;
1519
1520 list_for_each_entry_safe(obj, next,
1521 &ring->gpu_write_list,
1522 gpu_write_list) {
1523 if (obj->base.write_domain & flush_domains) {
1524 uint32_t old_write_domain = obj->base.write_domain;
1525
1526 obj->base.write_domain = 0;
1527 list_del_init(&obj->gpu_write_list);
1528 i915_gem_object_move_to_active(obj, ring,
1529 i915_gem_next_request_seqno(ring));
1530
1531 trace_i915_gem_object_change_domain(obj,
1532 obj->base.read_domains,
1533 old_write_domain);
1534 }
1535 }
1536}
1537
1538static u32
1539i915_gem_get_seqno(struct drm_device *dev)
1540{
1541 drm_i915_private_t *dev_priv = dev->dev_private;
1542 u32 seqno = dev_priv->next_seqno;
1543
1544 /* reserve 0 for non-seqno */
1545 if (++dev_priv->next_seqno == 0)
1546 dev_priv->next_seqno = 1;
1547
1548 return seqno;
1549}
1550
1551u32
1552i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1553{
1554 if (ring->outstanding_lazy_request == 0)
1555 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1556
1557 return ring->outstanding_lazy_request;
1558}
1559
1560int
1561i915_add_request(struct intel_ring_buffer *ring,
1562 struct drm_file *file,
1563 struct drm_i915_gem_request *request)
1564{
1565 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1566 uint32_t seqno;
1567 u32 request_ring_position;
1568 int was_empty;
1569 int ret;
1570
1571 BUG_ON(request == NULL);
1572 seqno = i915_gem_next_request_seqno(ring);
1573
1574 /* Record the position of the start of the request so that
1575 * should we detect the updated seqno part-way through the
1576 * GPU processing the request, we never over-estimate the
1577 * position of the head.
1578 */
1579 request_ring_position = intel_ring_get_tail(ring);
1580
1581 ret = ring->add_request(ring, &seqno);
1582 if (ret)
1583 return ret;
1584
1585 trace_i915_gem_request_add(ring, seqno);
1586
1587 request->seqno = seqno;
1588 request->ring = ring;
1589 request->tail = request_ring_position;
1590 request->emitted_jiffies = jiffies;
1591 was_empty = list_empty(&ring->request_list);
1592 list_add_tail(&request->list, &ring->request_list);
1593
1594 if (file) {
1595 struct drm_i915_file_private *file_priv = file->driver_priv;
1596
1597 spin_lock(&file_priv->mm.lock);
1598 request->file_priv = file_priv;
1599 list_add_tail(&request->client_list,
1600 &file_priv->mm.request_list);
1601 spin_unlock(&file_priv->mm.lock);
1602 }
1603
1604 ring->outstanding_lazy_request = 0;
1605
1606 if (!dev_priv->mm.suspended) {
1607 if (i915_enable_hangcheck) {
1608 mod_timer(&dev_priv->hangcheck_timer,
1609 jiffies +
1610 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1611 }
1612 if (was_empty)
1613 queue_delayed_work(dev_priv->wq,
1614 &dev_priv->mm.retire_work, HZ);
1615 }
1616 return 0;
1617}
1618
1619static inline void
1620i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1621{
1622 struct drm_i915_file_private *file_priv = request->file_priv;
1623
1624 if (!file_priv)
1625 return;
1626
1627 spin_lock(&file_priv->mm.lock);
1628 if (request->file_priv) {
1629 list_del(&request->client_list);
1630 request->file_priv = NULL;
1631 }
1632 spin_unlock(&file_priv->mm.lock);
1633}
1634
1635static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1636 struct intel_ring_buffer *ring)
1637{
1638 while (!list_empty(&ring->request_list)) {
1639 struct drm_i915_gem_request *request;
1640
1641 request = list_first_entry(&ring->request_list,
1642 struct drm_i915_gem_request,
1643 list);
1644
1645 list_del(&request->list);
1646 i915_gem_request_remove_from_client(request);
1647 kfree(request);
1648 }
1649
1650 while (!list_empty(&ring->active_list)) {
1651 struct drm_i915_gem_object *obj;
1652
1653 obj = list_first_entry(&ring->active_list,
1654 struct drm_i915_gem_object,
1655 ring_list);
1656
1657 obj->base.write_domain = 0;
1658 list_del_init(&obj->gpu_write_list);
1659 i915_gem_object_move_to_inactive(obj);
1660 }
1661}
1662
1663static void i915_gem_reset_fences(struct drm_device *dev)
1664{
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 int i;
1667
1668 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1669 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1670
1671 i915_gem_write_fence(dev, i, NULL);
1672
1673 if (reg->obj)
1674 i915_gem_object_fence_lost(reg->obj);
1675
1676 reg->pin_count = 0;
1677 reg->obj = NULL;
1678 INIT_LIST_HEAD(®->lru_list);
1679 }
1680
1681 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1682}
1683
1684void i915_gem_reset(struct drm_device *dev)
1685{
1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687 struct drm_i915_gem_object *obj;
1688 struct intel_ring_buffer *ring;
1689 int i;
1690
1691 for_each_ring(ring, dev_priv, i)
1692 i915_gem_reset_ring_lists(dev_priv, ring);
1693
1694 /* Remove anything from the flushing lists. The GPU cache is likely
1695 * to be lost on reset along with the data, so simply move the
1696 * lost bo to the inactive list.
1697 */
1698 while (!list_empty(&dev_priv->mm.flushing_list)) {
1699 obj = list_first_entry(&dev_priv->mm.flushing_list,
1700 struct drm_i915_gem_object,
1701 mm_list);
1702
1703 obj->base.write_domain = 0;
1704 list_del_init(&obj->gpu_write_list);
1705 i915_gem_object_move_to_inactive(obj);
1706 }
1707
1708 /* Move everything out of the GPU domains to ensure we do any
1709 * necessary invalidation upon reuse.
1710 */
1711 list_for_each_entry(obj,
1712 &dev_priv->mm.inactive_list,
1713 mm_list)
1714 {
1715 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1716 }
1717
1718 /* The fence registers are invalidated so clear them out */
1719 i915_gem_reset_fences(dev);
1720}
1721
1722/**
1723 * This function clears the request list as sequence numbers are passed.
1724 */
1725void
1726i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1727{
1728 uint32_t seqno;
1729 int i;
1730
1731 if (list_empty(&ring->request_list))
1732 return;
1733
1734 WARN_ON(i915_verify_lists(ring->dev));
1735
1736 seqno = ring->get_seqno(ring);
1737
1738 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1739 if (seqno >= ring->sync_seqno[i])
1740 ring->sync_seqno[i] = 0;
1741
1742 while (!list_empty(&ring->request_list)) {
1743 struct drm_i915_gem_request *request;
1744
1745 request = list_first_entry(&ring->request_list,
1746 struct drm_i915_gem_request,
1747 list);
1748
1749 if (!i915_seqno_passed(seqno, request->seqno))
1750 break;
1751
1752 trace_i915_gem_request_retire(ring, request->seqno);
1753 /* We know the GPU must have read the request to have
1754 * sent us the seqno + interrupt, so use the position
1755 * of tail of the request to update the last known position
1756 * of the GPU head.
1757 */
1758 ring->last_retired_head = request->tail;
1759
1760 list_del(&request->list);
1761 i915_gem_request_remove_from_client(request);
1762 kfree(request);
1763 }
1764
1765 /* Move any buffers on the active list that are no longer referenced
1766 * by the ringbuffer to the flushing/inactive lists as appropriate.
1767 */
1768 while (!list_empty(&ring->active_list)) {
1769 struct drm_i915_gem_object *obj;
1770
1771 obj = list_first_entry(&ring->active_list,
1772 struct drm_i915_gem_object,
1773 ring_list);
1774
1775 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1776 break;
1777
1778 if (obj->base.write_domain != 0)
1779 i915_gem_object_move_to_flushing(obj);
1780 else
1781 i915_gem_object_move_to_inactive(obj);
1782 }
1783
1784 if (unlikely(ring->trace_irq_seqno &&
1785 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1786 ring->irq_put(ring);
1787 ring->trace_irq_seqno = 0;
1788 }
1789
1790 WARN_ON(i915_verify_lists(ring->dev));
1791}
1792
1793void
1794i915_gem_retire_requests(struct drm_device *dev)
1795{
1796 drm_i915_private_t *dev_priv = dev->dev_private;
1797 struct intel_ring_buffer *ring;
1798 int i;
1799
1800 for_each_ring(ring, dev_priv, i)
1801 i915_gem_retire_requests_ring(ring);
1802}
1803
1804static void
1805i915_gem_retire_work_handler(struct work_struct *work)
1806{
1807 drm_i915_private_t *dev_priv;
1808 struct drm_device *dev;
1809 struct intel_ring_buffer *ring;
1810 bool idle;
1811 int i;
1812
1813 dev_priv = container_of(work, drm_i915_private_t,
1814 mm.retire_work.work);
1815 dev = dev_priv->dev;
1816
1817 /* Come back later if the device is busy... */
1818 if (!mutex_trylock(&dev->struct_mutex)) {
1819 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1820 return;
1821 }
1822
1823 i915_gem_retire_requests(dev);
1824
1825 /* Send a periodic flush down the ring so we don't hold onto GEM
1826 * objects indefinitely.
1827 */
1828 idle = true;
1829 for_each_ring(ring, dev_priv, i) {
1830 if (!list_empty(&ring->gpu_write_list)) {
1831 struct drm_i915_gem_request *request;
1832 int ret;
1833
1834 ret = i915_gem_flush_ring(ring,
1835 0, I915_GEM_GPU_DOMAINS);
1836 request = kzalloc(sizeof(*request), GFP_KERNEL);
1837 if (ret || request == NULL ||
1838 i915_add_request(ring, NULL, request))
1839 kfree(request);
1840 }
1841
1842 idle &= list_empty(&ring->request_list);
1843 }
1844
1845 if (!dev_priv->mm.suspended && !idle)
1846 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1847
1848 mutex_unlock(&dev->struct_mutex);
1849}
1850
1851static int
1852i915_gem_check_wedge(struct drm_i915_private *dev_priv)
1853{
1854 BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
1855
1856 if (atomic_read(&dev_priv->mm.wedged)) {
1857 struct completion *x = &dev_priv->error_completion;
1858 bool recovery_complete;
1859 unsigned long flags;
1860
1861 /* Give the error handler a chance to run. */
1862 spin_lock_irqsave(&x->wait.lock, flags);
1863 recovery_complete = x->done > 0;
1864 spin_unlock_irqrestore(&x->wait.lock, flags);
1865
1866 return recovery_complete ? -EIO : -EAGAIN;
1867 }
1868
1869 return 0;
1870}
1871
1872/*
1873 * Compare seqno against outstanding lazy request. Emit a request if they are
1874 * equal.
1875 */
1876static int
1877i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1878{
1879 int ret = 0;
1880
1881 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1882
1883 if (seqno == ring->outstanding_lazy_request) {
1884 struct drm_i915_gem_request *request;
1885
1886 request = kzalloc(sizeof(*request), GFP_KERNEL);
1887 if (request == NULL)
1888 return -ENOMEM;
1889
1890 ret = i915_add_request(ring, NULL, request);
1891 if (ret) {
1892 kfree(request);
1893 return ret;
1894 }
1895
1896 BUG_ON(seqno != request->seqno);
1897 }
1898
1899 return ret;
1900}
1901
1902static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1903 bool interruptible)
1904{
1905 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1906 int ret = 0;
1907
1908 if (i915_seqno_passed(ring->get_seqno(ring), seqno))
1909 return 0;
1910
1911 trace_i915_gem_request_wait_begin(ring, seqno);
1912 if (WARN_ON(!ring->irq_get(ring)))
1913 return -ENODEV;
1914
1915#define EXIT_COND \
1916 (i915_seqno_passed(ring->get_seqno(ring), seqno) || \
1917 atomic_read(&dev_priv->mm.wedged))
1918
1919 if (interruptible)
1920 ret = wait_event_interruptible(ring->irq_queue,
1921 EXIT_COND);
1922 else
1923 wait_event(ring->irq_queue, EXIT_COND);
1924
1925 ring->irq_put(ring);
1926 trace_i915_gem_request_wait_end(ring, seqno);
1927#undef EXIT_COND
1928
1929 return ret;
1930}
1931
1932/**
1933 * Waits for a sequence number to be signaled, and cleans up the
1934 * request and object lists appropriately for that event.
1935 */
1936int
1937i915_wait_request(struct intel_ring_buffer *ring,
1938 uint32_t seqno)
1939{
1940 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1941 int ret = 0;
1942
1943 BUG_ON(seqno == 0);
1944
1945 ret = i915_gem_check_wedge(dev_priv);
1946 if (ret)
1947 return ret;
1948
1949 ret = i915_gem_check_olr(ring, seqno);
1950 if (ret)
1951 return ret;
1952
1953 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible);
1954 if (atomic_read(&dev_priv->mm.wedged))
1955 ret = -EAGAIN;
1956
1957 return ret;
1958}
1959
1960/**
1961 * Ensures that all rendering to the object has completed and the object is
1962 * safe to unbind from the GTT or access from the CPU.
1963 */
1964int
1965i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
1966{
1967 int ret;
1968
1969 /* This function only exists to support waiting for existing rendering,
1970 * not for emitting required flushes.
1971 */
1972 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
1973
1974 /* If there is rendering queued on the buffer being evicted, wait for
1975 * it.
1976 */
1977 if (obj->active) {
1978 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
1979 if (ret)
1980 return ret;
1981 i915_gem_retire_requests_ring(obj->ring);
1982 }
1983
1984 return 0;
1985}
1986
1987/**
1988 * i915_gem_object_sync - sync an object to a ring.
1989 *
1990 * @obj: object which may be in use on another ring.
1991 * @to: ring we wish to use the object on. May be NULL.
1992 *
1993 * This code is meant to abstract object synchronization with the GPU.
1994 * Calling with NULL implies synchronizing the object with the CPU
1995 * rather than a particular GPU ring.
1996 *
1997 * Returns 0 if successful, else propagates up the lower layer error.
1998 */
1999int
2000i915_gem_object_sync(struct drm_i915_gem_object *obj,
2001 struct intel_ring_buffer *to)
2002{
2003 struct intel_ring_buffer *from = obj->ring;
2004 u32 seqno;
2005 int ret, idx;
2006
2007 if (from == NULL || to == from)
2008 return 0;
2009
2010 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2011 return i915_gem_object_wait_rendering(obj);
2012
2013 idx = intel_ring_sync_index(from, to);
2014
2015 seqno = obj->last_rendering_seqno;
2016 if (seqno <= from->sync_seqno[idx])
2017 return 0;
2018
2019 ret = i915_gem_check_olr(obj->ring, seqno);
2020 if (ret)
2021 return ret;
2022
2023 ret = to->sync_to(to, from, seqno);
2024 if (!ret)
2025 from->sync_seqno[idx] = seqno;
2026
2027 return ret;
2028}
2029
2030static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2031{
2032 u32 old_write_domain, old_read_domains;
2033
2034 /* Act a barrier for all accesses through the GTT */
2035 mb();
2036
2037 /* Force a pagefault for domain tracking on next user access */
2038 i915_gem_release_mmap(obj);
2039
2040 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2041 return;
2042
2043 old_read_domains = obj->base.read_domains;
2044 old_write_domain = obj->base.write_domain;
2045
2046 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2047 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2048
2049 trace_i915_gem_object_change_domain(obj,
2050 old_read_domains,
2051 old_write_domain);
2052}
2053
2054/**
2055 * Unbinds an object from the GTT aperture.
2056 */
2057int
2058i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2059{
2060 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2061 int ret = 0;
2062
2063 if (obj->gtt_space == NULL)
2064 return 0;
2065
2066 if (obj->pin_count)
2067 return -EBUSY;
2068
2069 ret = i915_gem_object_finish_gpu(obj);
2070 if (ret)
2071 return ret;
2072 /* Continue on if we fail due to EIO, the GPU is hung so we
2073 * should be safe and we need to cleanup or else we might
2074 * cause memory corruption through use-after-free.
2075 */
2076
2077 i915_gem_object_finish_gtt(obj);
2078
2079 /* Move the object to the CPU domain to ensure that
2080 * any possible CPU writes while it's not in the GTT
2081 * are flushed when we go to remap it.
2082 */
2083 if (ret == 0)
2084 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2085 if (ret == -ERESTARTSYS)
2086 return ret;
2087 if (ret) {
2088 /* In the event of a disaster, abandon all caches and
2089 * hope for the best.
2090 */
2091 i915_gem_clflush_object(obj);
2092 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2093 }
2094
2095 /* release the fence reg _after_ flushing */
2096 ret = i915_gem_object_put_fence(obj);
2097 if (ret)
2098 return ret;
2099
2100 trace_i915_gem_object_unbind(obj);
2101
2102 if (obj->has_global_gtt_mapping)
2103 i915_gem_gtt_unbind_object(obj);
2104 if (obj->has_aliasing_ppgtt_mapping) {
2105 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2106 obj->has_aliasing_ppgtt_mapping = 0;
2107 }
2108 i915_gem_gtt_finish_object(obj);
2109
2110 i915_gem_object_put_pages_gtt(obj);
2111
2112 list_del_init(&obj->gtt_list);
2113 list_del_init(&obj->mm_list);
2114 /* Avoid an unnecessary call to unbind on rebind. */
2115 obj->map_and_fenceable = true;
2116
2117 drm_mm_put_block(obj->gtt_space);
2118 obj->gtt_space = NULL;
2119 obj->gtt_offset = 0;
2120
2121 if (i915_gem_object_is_purgeable(obj))
2122 i915_gem_object_truncate(obj);
2123
2124 return ret;
2125}
2126
2127int
2128i915_gem_flush_ring(struct intel_ring_buffer *ring,
2129 uint32_t invalidate_domains,
2130 uint32_t flush_domains)
2131{
2132 int ret;
2133
2134 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2135 return 0;
2136
2137 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2138
2139 ret = ring->flush(ring, invalidate_domains, flush_domains);
2140 if (ret)
2141 return ret;
2142
2143 if (flush_domains & I915_GEM_GPU_DOMAINS)
2144 i915_gem_process_flushing_list(ring, flush_domains);
2145
2146 return 0;
2147}
2148
2149static int i915_ring_idle(struct intel_ring_buffer *ring)
2150{
2151 int ret;
2152
2153 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2154 return 0;
2155
2156 if (!list_empty(&ring->gpu_write_list)) {
2157 ret = i915_gem_flush_ring(ring,
2158 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2159 if (ret)
2160 return ret;
2161 }
2162
2163 return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2164}
2165
2166int i915_gpu_idle(struct drm_device *dev)
2167{
2168 drm_i915_private_t *dev_priv = dev->dev_private;
2169 struct intel_ring_buffer *ring;
2170 int ret, i;
2171
2172 /* Flush everything onto the inactive list. */
2173 for_each_ring(ring, dev_priv, i) {
2174 ret = i915_ring_idle(ring);
2175 if (ret)
2176 return ret;
2177
2178 /* Is the device fubar? */
2179 if (WARN_ON(!list_empty(&ring->gpu_write_list)))
2180 return -EBUSY;
2181 }
2182
2183 return 0;
2184}
2185
2186static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2187 struct drm_i915_gem_object *obj)
2188{
2189 drm_i915_private_t *dev_priv = dev->dev_private;
2190 uint64_t val;
2191
2192 if (obj) {
2193 u32 size = obj->gtt_space->size;
2194
2195 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2196 0xfffff000) << 32;
2197 val |= obj->gtt_offset & 0xfffff000;
2198 val |= (uint64_t)((obj->stride / 128) - 1) <<
2199 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2200
2201 if (obj->tiling_mode == I915_TILING_Y)
2202 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2203 val |= I965_FENCE_REG_VALID;
2204 } else
2205 val = 0;
2206
2207 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2208 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2209}
2210
2211static void i965_write_fence_reg(struct drm_device *dev, int reg,
2212 struct drm_i915_gem_object *obj)
2213{
2214 drm_i915_private_t *dev_priv = dev->dev_private;
2215 uint64_t val;
2216
2217 if (obj) {
2218 u32 size = obj->gtt_space->size;
2219
2220 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2221 0xfffff000) << 32;
2222 val |= obj->gtt_offset & 0xfffff000;
2223 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2224 if (obj->tiling_mode == I915_TILING_Y)
2225 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2226 val |= I965_FENCE_REG_VALID;
2227 } else
2228 val = 0;
2229
2230 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2231 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2232}
2233
2234static void i915_write_fence_reg(struct drm_device *dev, int reg,
2235 struct drm_i915_gem_object *obj)
2236{
2237 drm_i915_private_t *dev_priv = dev->dev_private;
2238 u32 val;
2239
2240 if (obj) {
2241 u32 size = obj->gtt_space->size;
2242 int pitch_val;
2243 int tile_width;
2244
2245 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2246 (size & -size) != size ||
2247 (obj->gtt_offset & (size - 1)),
2248 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2249 obj->gtt_offset, obj->map_and_fenceable, size);
2250
2251 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2252 tile_width = 128;
2253 else
2254 tile_width = 512;
2255
2256 /* Note: pitch better be a power of two tile widths */
2257 pitch_val = obj->stride / tile_width;
2258 pitch_val = ffs(pitch_val) - 1;
2259
2260 val = obj->gtt_offset;
2261 if (obj->tiling_mode == I915_TILING_Y)
2262 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2263 val |= I915_FENCE_SIZE_BITS(size);
2264 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2265 val |= I830_FENCE_REG_VALID;
2266 } else
2267 val = 0;
2268
2269 if (reg < 8)
2270 reg = FENCE_REG_830_0 + reg * 4;
2271 else
2272 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2273
2274 I915_WRITE(reg, val);
2275 POSTING_READ(reg);
2276}
2277
2278static void i830_write_fence_reg(struct drm_device *dev, int reg,
2279 struct drm_i915_gem_object *obj)
2280{
2281 drm_i915_private_t *dev_priv = dev->dev_private;
2282 uint32_t val;
2283
2284 if (obj) {
2285 u32 size = obj->gtt_space->size;
2286 uint32_t pitch_val;
2287
2288 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2289 (size & -size) != size ||
2290 (obj->gtt_offset & (size - 1)),
2291 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2292 obj->gtt_offset, size);
2293
2294 pitch_val = obj->stride / 128;
2295 pitch_val = ffs(pitch_val) - 1;
2296
2297 val = obj->gtt_offset;
2298 if (obj->tiling_mode == I915_TILING_Y)
2299 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2300 val |= I830_FENCE_SIZE_BITS(size);
2301 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2302 val |= I830_FENCE_REG_VALID;
2303 } else
2304 val = 0;
2305
2306 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2307 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2308}
2309
2310static void i915_gem_write_fence(struct drm_device *dev, int reg,
2311 struct drm_i915_gem_object *obj)
2312{
2313 switch (INTEL_INFO(dev)->gen) {
2314 case 7:
2315 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2316 case 5:
2317 case 4: i965_write_fence_reg(dev, reg, obj); break;
2318 case 3: i915_write_fence_reg(dev, reg, obj); break;
2319 case 2: i830_write_fence_reg(dev, reg, obj); break;
2320 default: break;
2321 }
2322}
2323
2324static inline int fence_number(struct drm_i915_private *dev_priv,
2325 struct drm_i915_fence_reg *fence)
2326{
2327 return fence - dev_priv->fence_regs;
2328}
2329
2330static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2331 struct drm_i915_fence_reg *fence,
2332 bool enable)
2333{
2334 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2335 int reg = fence_number(dev_priv, fence);
2336
2337 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2338
2339 if (enable) {
2340 obj->fence_reg = reg;
2341 fence->obj = obj;
2342 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2343 } else {
2344 obj->fence_reg = I915_FENCE_REG_NONE;
2345 fence->obj = NULL;
2346 list_del_init(&fence->lru_list);
2347 }
2348}
2349
2350static int
2351i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2352{
2353 int ret;
2354
2355 if (obj->fenced_gpu_access) {
2356 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2357 ret = i915_gem_flush_ring(obj->ring,
2358 0, obj->base.write_domain);
2359 if (ret)
2360 return ret;
2361 }
2362
2363 obj->fenced_gpu_access = false;
2364 }
2365
2366 if (obj->last_fenced_seqno) {
2367 ret = i915_wait_request(obj->ring, obj->last_fenced_seqno);
2368 if (ret)
2369 return ret;
2370
2371 obj->last_fenced_seqno = 0;
2372 }
2373
2374 /* Ensure that all CPU reads are completed before installing a fence
2375 * and all writes before removing the fence.
2376 */
2377 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2378 mb();
2379
2380 return 0;
2381}
2382
2383int
2384i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2385{
2386 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2387 int ret;
2388
2389 ret = i915_gem_object_flush_fence(obj);
2390 if (ret)
2391 return ret;
2392
2393 if (obj->fence_reg == I915_FENCE_REG_NONE)
2394 return 0;
2395
2396 i915_gem_object_update_fence(obj,
2397 &dev_priv->fence_regs[obj->fence_reg],
2398 false);
2399 i915_gem_object_fence_lost(obj);
2400
2401 return 0;
2402}
2403
2404static struct drm_i915_fence_reg *
2405i915_find_fence_reg(struct drm_device *dev)
2406{
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct drm_i915_fence_reg *reg, *avail;
2409 int i;
2410
2411 /* First try to find a free reg */
2412 avail = NULL;
2413 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2414 reg = &dev_priv->fence_regs[i];
2415 if (!reg->obj)
2416 return reg;
2417
2418 if (!reg->pin_count)
2419 avail = reg;
2420 }
2421
2422 if (avail == NULL)
2423 return NULL;
2424
2425 /* None available, try to steal one or wait for a user to finish */
2426 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2427 if (reg->pin_count)
2428 continue;
2429
2430 return reg;
2431 }
2432
2433 return NULL;
2434}
2435
2436/**
2437 * i915_gem_object_get_fence - set up fencing for an object
2438 * @obj: object to map through a fence reg
2439 *
2440 * When mapping objects through the GTT, userspace wants to be able to write
2441 * to them without having to worry about swizzling if the object is tiled.
2442 * This function walks the fence regs looking for a free one for @obj,
2443 * stealing one if it can't find any.
2444 *
2445 * It then sets up the reg based on the object's properties: address, pitch
2446 * and tiling format.
2447 *
2448 * For an untiled surface, this removes any existing fence.
2449 */
2450int
2451i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2452{
2453 struct drm_device *dev = obj->base.dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 bool enable = obj->tiling_mode != I915_TILING_NONE;
2456 struct drm_i915_fence_reg *reg;
2457 int ret;
2458
2459 /* Have we updated the tiling parameters upon the object and so
2460 * will need to serialise the write to the associated fence register?
2461 */
2462 if (obj->fence_dirty) {
2463 ret = i915_gem_object_flush_fence(obj);
2464 if (ret)
2465 return ret;
2466 }
2467
2468 /* Just update our place in the LRU if our fence is getting reused. */
2469 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2470 reg = &dev_priv->fence_regs[obj->fence_reg];
2471 if (!obj->fence_dirty) {
2472 list_move_tail(®->lru_list,
2473 &dev_priv->mm.fence_list);
2474 return 0;
2475 }
2476 } else if (enable) {
2477 reg = i915_find_fence_reg(dev);
2478 if (reg == NULL)
2479 return -EDEADLK;
2480
2481 if (reg->obj) {
2482 struct drm_i915_gem_object *old = reg->obj;
2483
2484 ret = i915_gem_object_flush_fence(old);
2485 if (ret)
2486 return ret;
2487
2488 i915_gem_object_fence_lost(old);
2489 }
2490 } else
2491 return 0;
2492
2493 i915_gem_object_update_fence(obj, reg, enable);
2494 obj->fence_dirty = false;
2495
2496 return 0;
2497}
2498
2499/**
2500 * Finds free space in the GTT aperture and binds the object there.
2501 */
2502static int
2503i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2504 unsigned alignment,
2505 bool map_and_fenceable)
2506{
2507 struct drm_device *dev = obj->base.dev;
2508 drm_i915_private_t *dev_priv = dev->dev_private;
2509 struct drm_mm_node *free_space;
2510 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2511 u32 size, fence_size, fence_alignment, unfenced_alignment;
2512 bool mappable, fenceable;
2513 int ret;
2514
2515 if (obj->madv != I915_MADV_WILLNEED) {
2516 DRM_ERROR("Attempting to bind a purgeable object\n");
2517 return -EINVAL;
2518 }
2519
2520 fence_size = i915_gem_get_gtt_size(dev,
2521 obj->base.size,
2522 obj->tiling_mode);
2523 fence_alignment = i915_gem_get_gtt_alignment(dev,
2524 obj->base.size,
2525 obj->tiling_mode);
2526 unfenced_alignment =
2527 i915_gem_get_unfenced_gtt_alignment(dev,
2528 obj->base.size,
2529 obj->tiling_mode);
2530
2531 if (alignment == 0)
2532 alignment = map_and_fenceable ? fence_alignment :
2533 unfenced_alignment;
2534 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2535 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2536 return -EINVAL;
2537 }
2538
2539 size = map_and_fenceable ? fence_size : obj->base.size;
2540
2541 /* If the object is bigger than the entire aperture, reject it early
2542 * before evicting everything in a vain attempt to find space.
2543 */
2544 if (obj->base.size >
2545 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2546 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2547 return -E2BIG;
2548 }
2549
2550 search_free:
2551 if (map_and_fenceable)
2552 free_space =
2553 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2554 size, alignment, 0,
2555 dev_priv->mm.gtt_mappable_end,
2556 0);
2557 else
2558 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2559 size, alignment, 0);
2560
2561 if (free_space != NULL) {
2562 if (map_and_fenceable)
2563 obj->gtt_space =
2564 drm_mm_get_block_range_generic(free_space,
2565 size, alignment, 0,
2566 dev_priv->mm.gtt_mappable_end,
2567 0);
2568 else
2569 obj->gtt_space =
2570 drm_mm_get_block(free_space, size, alignment);
2571 }
2572 if (obj->gtt_space == NULL) {
2573 /* If the gtt is empty and we're still having trouble
2574 * fitting our object in, we're out of memory.
2575 */
2576 ret = i915_gem_evict_something(dev, size, alignment,
2577 map_and_fenceable);
2578 if (ret)
2579 return ret;
2580
2581 goto search_free;
2582 }
2583
2584 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2585 if (ret) {
2586 drm_mm_put_block(obj->gtt_space);
2587 obj->gtt_space = NULL;
2588
2589 if (ret == -ENOMEM) {
2590 /* first try to reclaim some memory by clearing the GTT */
2591 ret = i915_gem_evict_everything(dev, false);
2592 if (ret) {
2593 /* now try to shrink everyone else */
2594 if (gfpmask) {
2595 gfpmask = 0;
2596 goto search_free;
2597 }
2598
2599 return -ENOMEM;
2600 }
2601
2602 goto search_free;
2603 }
2604
2605 return ret;
2606 }
2607
2608 ret = i915_gem_gtt_prepare_object(obj);
2609 if (ret) {
2610 i915_gem_object_put_pages_gtt(obj);
2611 drm_mm_put_block(obj->gtt_space);
2612 obj->gtt_space = NULL;
2613
2614 if (i915_gem_evict_everything(dev, false))
2615 return ret;
2616
2617 goto search_free;
2618 }
2619
2620 if (!dev_priv->mm.aliasing_ppgtt)
2621 i915_gem_gtt_bind_object(obj, obj->cache_level);
2622
2623 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2624 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2625
2626 /* Assert that the object is not currently in any GPU domain. As it
2627 * wasn't in the GTT, there shouldn't be any way it could have been in
2628 * a GPU cache
2629 */
2630 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2631 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2632
2633 obj->gtt_offset = obj->gtt_space->start;
2634
2635 fenceable =
2636 obj->gtt_space->size == fence_size &&
2637 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2638
2639 mappable =
2640 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2641
2642 obj->map_and_fenceable = mappable && fenceable;
2643
2644 trace_i915_gem_object_bind(obj, map_and_fenceable);
2645 return 0;
2646}
2647
2648void
2649i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2650{
2651 /* If we don't have a page list set up, then we're not pinned
2652 * to GPU, and we can ignore the cache flush because it'll happen
2653 * again at bind time.
2654 */
2655 if (obj->pages == NULL)
2656 return;
2657
2658 /* If the GPU is snooping the contents of the CPU cache,
2659 * we do not need to manually clear the CPU cache lines. However,
2660 * the caches are only snooped when the render cache is
2661 * flushed/invalidated. As we always have to emit invalidations
2662 * and flushes when moving into and out of the RENDER domain, correct
2663 * snooping behaviour occurs naturally as the result of our domain
2664 * tracking.
2665 */
2666 if (obj->cache_level != I915_CACHE_NONE)
2667 return;
2668
2669 trace_i915_gem_object_clflush(obj);
2670
2671 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2672}
2673
2674/** Flushes any GPU write domain for the object if it's dirty. */
2675static int
2676i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2677{
2678 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2679 return 0;
2680
2681 /* Queue the GPU write cache flushing we need. */
2682 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2683}
2684
2685/** Flushes the GTT write domain for the object if it's dirty. */
2686static void
2687i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2688{
2689 uint32_t old_write_domain;
2690
2691 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2692 return;
2693
2694 /* No actual flushing is required for the GTT write domain. Writes
2695 * to it immediately go to main memory as far as we know, so there's
2696 * no chipset flush. It also doesn't land in render cache.
2697 *
2698 * However, we do have to enforce the order so that all writes through
2699 * the GTT land before any writes to the device, such as updates to
2700 * the GATT itself.
2701 */
2702 wmb();
2703
2704 old_write_domain = obj->base.write_domain;
2705 obj->base.write_domain = 0;
2706
2707 trace_i915_gem_object_change_domain(obj,
2708 obj->base.read_domains,
2709 old_write_domain);
2710}
2711
2712/** Flushes the CPU write domain for the object if it's dirty. */
2713static void
2714i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2715{
2716 uint32_t old_write_domain;
2717
2718 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2719 return;
2720
2721 i915_gem_clflush_object(obj);
2722 intel_gtt_chipset_flush();
2723 old_write_domain = obj->base.write_domain;
2724 obj->base.write_domain = 0;
2725
2726 trace_i915_gem_object_change_domain(obj,
2727 obj->base.read_domains,
2728 old_write_domain);
2729}
2730
2731/**
2732 * Moves a single object to the GTT read, and possibly write domain.
2733 *
2734 * This function returns when the move is complete, including waiting on
2735 * flushes to occur.
2736 */
2737int
2738i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2739{
2740 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2741 uint32_t old_write_domain, old_read_domains;
2742 int ret;
2743
2744 /* Not valid to be called on unbound objects. */
2745 if (obj->gtt_space == NULL)
2746 return -EINVAL;
2747
2748 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2749 return 0;
2750
2751 ret = i915_gem_object_flush_gpu_write_domain(obj);
2752 if (ret)
2753 return ret;
2754
2755 if (obj->pending_gpu_write || write) {
2756 ret = i915_gem_object_wait_rendering(obj);
2757 if (ret)
2758 return ret;
2759 }
2760
2761 i915_gem_object_flush_cpu_write_domain(obj);
2762
2763 old_write_domain = obj->base.write_domain;
2764 old_read_domains = obj->base.read_domains;
2765
2766 /* It should now be out of any other write domains, and we can update
2767 * the domain values for our changes.
2768 */
2769 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2770 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2771 if (write) {
2772 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2773 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2774 obj->dirty = 1;
2775 }
2776
2777 trace_i915_gem_object_change_domain(obj,
2778 old_read_domains,
2779 old_write_domain);
2780
2781 /* And bump the LRU for this access */
2782 if (i915_gem_object_is_inactive(obj))
2783 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2784
2785 return 0;
2786}
2787
2788int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2789 enum i915_cache_level cache_level)
2790{
2791 struct drm_device *dev = obj->base.dev;
2792 drm_i915_private_t *dev_priv = dev->dev_private;
2793 int ret;
2794
2795 if (obj->cache_level == cache_level)
2796 return 0;
2797
2798 if (obj->pin_count) {
2799 DRM_DEBUG("can not change the cache level of pinned objects\n");
2800 return -EBUSY;
2801 }
2802
2803 if (obj->gtt_space) {
2804 ret = i915_gem_object_finish_gpu(obj);
2805 if (ret)
2806 return ret;
2807
2808 i915_gem_object_finish_gtt(obj);
2809
2810 /* Before SandyBridge, you could not use tiling or fence
2811 * registers with snooped memory, so relinquish any fences
2812 * currently pointing to our region in the aperture.
2813 */
2814 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2815 ret = i915_gem_object_put_fence(obj);
2816 if (ret)
2817 return ret;
2818 }
2819
2820 if (obj->has_global_gtt_mapping)
2821 i915_gem_gtt_bind_object(obj, cache_level);
2822 if (obj->has_aliasing_ppgtt_mapping)
2823 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2824 obj, cache_level);
2825 }
2826
2827 if (cache_level == I915_CACHE_NONE) {
2828 u32 old_read_domains, old_write_domain;
2829
2830 /* If we're coming from LLC cached, then we haven't
2831 * actually been tracking whether the data is in the
2832 * CPU cache or not, since we only allow one bit set
2833 * in obj->write_domain and have been skipping the clflushes.
2834 * Just set it to the CPU cache for now.
2835 */
2836 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
2837 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
2838
2839 old_read_domains = obj->base.read_domains;
2840 old_write_domain = obj->base.write_domain;
2841
2842 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2843 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2844
2845 trace_i915_gem_object_change_domain(obj,
2846 old_read_domains,
2847 old_write_domain);
2848 }
2849
2850 obj->cache_level = cache_level;
2851 return 0;
2852}
2853
2854/*
2855 * Prepare buffer for display plane (scanout, cursors, etc).
2856 * Can be called from an uninterruptible phase (modesetting) and allows
2857 * any flushes to be pipelined (for pageflips).
2858 */
2859int
2860i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2861 u32 alignment,
2862 struct intel_ring_buffer *pipelined)
2863{
2864 u32 old_read_domains, old_write_domain;
2865 int ret;
2866
2867 ret = i915_gem_object_flush_gpu_write_domain(obj);
2868 if (ret)
2869 return ret;
2870
2871 if (pipelined != obj->ring) {
2872 ret = i915_gem_object_sync(obj, pipelined);
2873 if (ret)
2874 return ret;
2875 }
2876
2877 /* The display engine is not coherent with the LLC cache on gen6. As
2878 * a result, we make sure that the pinning that is about to occur is
2879 * done with uncached PTEs. This is lowest common denominator for all
2880 * chipsets.
2881 *
2882 * However for gen6+, we could do better by using the GFDT bit instead
2883 * of uncaching, which would allow us to flush all the LLC-cached data
2884 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2885 */
2886 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2887 if (ret)
2888 return ret;
2889
2890 /* As the user may map the buffer once pinned in the display plane
2891 * (e.g. libkms for the bootup splash), we have to ensure that we
2892 * always use map_and_fenceable for all scanout buffers.
2893 */
2894 ret = i915_gem_object_pin(obj, alignment, true);
2895 if (ret)
2896 return ret;
2897
2898 i915_gem_object_flush_cpu_write_domain(obj);
2899
2900 old_write_domain = obj->base.write_domain;
2901 old_read_domains = obj->base.read_domains;
2902
2903 /* It should now be out of any other write domains, and we can update
2904 * the domain values for our changes.
2905 */
2906 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2907 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2908
2909 trace_i915_gem_object_change_domain(obj,
2910 old_read_domains,
2911 old_write_domain);
2912
2913 return 0;
2914}
2915
2916int
2917i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2918{
2919 int ret;
2920
2921 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2922 return 0;
2923
2924 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2925 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2926 if (ret)
2927 return ret;
2928 }
2929
2930 ret = i915_gem_object_wait_rendering(obj);
2931 if (ret)
2932 return ret;
2933
2934 /* Ensure that we invalidate the GPU's caches and TLBs. */
2935 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2936 return 0;
2937}
2938
2939/**
2940 * Moves a single object to the CPU read, and possibly write domain.
2941 *
2942 * This function returns when the move is complete, including waiting on
2943 * flushes to occur.
2944 */
2945int
2946i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2947{
2948 uint32_t old_write_domain, old_read_domains;
2949 int ret;
2950
2951 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2952 return 0;
2953
2954 ret = i915_gem_object_flush_gpu_write_domain(obj);
2955 if (ret)
2956 return ret;
2957
2958 if (write || obj->pending_gpu_write) {
2959 ret = i915_gem_object_wait_rendering(obj);
2960 if (ret)
2961 return ret;
2962 }
2963
2964 i915_gem_object_flush_gtt_write_domain(obj);
2965
2966 old_write_domain = obj->base.write_domain;
2967 old_read_domains = obj->base.read_domains;
2968
2969 /* Flush the CPU cache if it's still invalid. */
2970 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2971 i915_gem_clflush_object(obj);
2972
2973 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2974 }
2975
2976 /* It should now be out of any other write domains, and we can update
2977 * the domain values for our changes.
2978 */
2979 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2980
2981 /* If we're writing through the CPU, then the GPU read domains will
2982 * need to be invalidated at next use.
2983 */
2984 if (write) {
2985 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2986 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2987 }
2988
2989 trace_i915_gem_object_change_domain(obj,
2990 old_read_domains,
2991 old_write_domain);
2992
2993 return 0;
2994}
2995
2996/* Throttle our rendering by waiting until the ring has completed our requests
2997 * emitted over 20 msec ago.
2998 *
2999 * Note that if we were to use the current jiffies each time around the loop,
3000 * we wouldn't escape the function with any frames outstanding if the time to
3001 * render a frame was over 20ms.
3002 *
3003 * This should get us reasonable parallelism between CPU and GPU but also
3004 * relatively low latency when blocking on a particular request to finish.
3005 */
3006static int
3007i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3008{
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct drm_i915_file_private *file_priv = file->driver_priv;
3011 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3012 struct drm_i915_gem_request *request;
3013 struct intel_ring_buffer *ring = NULL;
3014 u32 seqno = 0;
3015 int ret;
3016
3017 if (atomic_read(&dev_priv->mm.wedged))
3018 return -EIO;
3019
3020 spin_lock(&file_priv->mm.lock);
3021 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3022 if (time_after_eq(request->emitted_jiffies, recent_enough))
3023 break;
3024
3025 ring = request->ring;
3026 seqno = request->seqno;
3027 }
3028 spin_unlock(&file_priv->mm.lock);
3029
3030 if (seqno == 0)
3031 return 0;
3032
3033 ret = __wait_seqno(ring, seqno, true);
3034 if (ret == 0)
3035 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3036
3037 return ret;
3038}
3039
3040int
3041i915_gem_object_pin(struct drm_i915_gem_object *obj,
3042 uint32_t alignment,
3043 bool map_and_fenceable)
3044{
3045 int ret;
3046
3047 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3048 return -EBUSY;
3049
3050 if (obj->gtt_space != NULL) {
3051 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3052 (map_and_fenceable && !obj->map_and_fenceable)) {
3053 WARN(obj->pin_count,
3054 "bo is already pinned with incorrect alignment:"
3055 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3056 " obj->map_and_fenceable=%d\n",
3057 obj->gtt_offset, alignment,
3058 map_and_fenceable,
3059 obj->map_and_fenceable);
3060 ret = i915_gem_object_unbind(obj);
3061 if (ret)
3062 return ret;
3063 }
3064 }
3065
3066 if (obj->gtt_space == NULL) {
3067 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3068 map_and_fenceable);
3069 if (ret)
3070 return ret;
3071 }
3072
3073 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3074 i915_gem_gtt_bind_object(obj, obj->cache_level);
3075
3076 obj->pin_count++;
3077 obj->pin_mappable |= map_and_fenceable;
3078
3079 return 0;
3080}
3081
3082void
3083i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3084{
3085 BUG_ON(obj->pin_count == 0);
3086 BUG_ON(obj->gtt_space == NULL);
3087
3088 if (--obj->pin_count == 0)
3089 obj->pin_mappable = false;
3090}
3091
3092int
3093i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3094 struct drm_file *file)
3095{
3096 struct drm_i915_gem_pin *args = data;
3097 struct drm_i915_gem_object *obj;
3098 int ret;
3099
3100 ret = i915_mutex_lock_interruptible(dev);
3101 if (ret)
3102 return ret;
3103
3104 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3105 if (&obj->base == NULL) {
3106 ret = -ENOENT;
3107 goto unlock;
3108 }
3109
3110 if (obj->madv != I915_MADV_WILLNEED) {
3111 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3112 ret = -EINVAL;
3113 goto out;
3114 }
3115
3116 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3117 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3118 args->handle);
3119 ret = -EINVAL;
3120 goto out;
3121 }
3122
3123 obj->user_pin_count++;
3124 obj->pin_filp = file;
3125 if (obj->user_pin_count == 1) {
3126 ret = i915_gem_object_pin(obj, args->alignment, true);
3127 if (ret)
3128 goto out;
3129 }
3130
3131 /* XXX - flush the CPU caches for pinned objects
3132 * as the X server doesn't manage domains yet
3133 */
3134 i915_gem_object_flush_cpu_write_domain(obj);
3135 args->offset = obj->gtt_offset;
3136out:
3137 drm_gem_object_unreference(&obj->base);
3138unlock:
3139 mutex_unlock(&dev->struct_mutex);
3140 return ret;
3141}
3142
3143int
3144i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3145 struct drm_file *file)
3146{
3147 struct drm_i915_gem_pin *args = data;
3148 struct drm_i915_gem_object *obj;
3149 int ret;
3150
3151 ret = i915_mutex_lock_interruptible(dev);
3152 if (ret)
3153 return ret;
3154
3155 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3156 if (&obj->base == NULL) {
3157 ret = -ENOENT;
3158 goto unlock;
3159 }
3160
3161 if (obj->pin_filp != file) {
3162 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3163 args->handle);
3164 ret = -EINVAL;
3165 goto out;
3166 }
3167 obj->user_pin_count--;
3168 if (obj->user_pin_count == 0) {
3169 obj->pin_filp = NULL;
3170 i915_gem_object_unpin(obj);
3171 }
3172
3173out:
3174 drm_gem_object_unreference(&obj->base);
3175unlock:
3176 mutex_unlock(&dev->struct_mutex);
3177 return ret;
3178}
3179
3180int
3181i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3182 struct drm_file *file)
3183{
3184 struct drm_i915_gem_busy *args = data;
3185 struct drm_i915_gem_object *obj;
3186 int ret;
3187
3188 ret = i915_mutex_lock_interruptible(dev);
3189 if (ret)
3190 return ret;
3191
3192 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3193 if (&obj->base == NULL) {
3194 ret = -ENOENT;
3195 goto unlock;
3196 }
3197
3198 /* Count all active objects as busy, even if they are currently not used
3199 * by the gpu. Users of this interface expect objects to eventually
3200 * become non-busy without any further actions, therefore emit any
3201 * necessary flushes here.
3202 */
3203 args->busy = obj->active;
3204 if (args->busy) {
3205 /* Unconditionally flush objects, even when the gpu still uses this
3206 * object. Userspace calling this function indicates that it wants to
3207 * use this buffer rather sooner than later, so issuing the required
3208 * flush earlier is beneficial.
3209 */
3210 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3211 ret = i915_gem_flush_ring(obj->ring,
3212 0, obj->base.write_domain);
3213 } else {
3214 ret = i915_gem_check_olr(obj->ring,
3215 obj->last_rendering_seqno);
3216 }
3217
3218 /* Update the active list for the hardware's current position.
3219 * Otherwise this only updates on a delayed timer or when irqs
3220 * are actually unmasked, and our working set ends up being
3221 * larger than required.
3222 */
3223 i915_gem_retire_requests_ring(obj->ring);
3224
3225 args->busy = obj->active;
3226 }
3227
3228 drm_gem_object_unreference(&obj->base);
3229unlock:
3230 mutex_unlock(&dev->struct_mutex);
3231 return ret;
3232}
3233
3234int
3235i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3236 struct drm_file *file_priv)
3237{
3238 return i915_gem_ring_throttle(dev, file_priv);
3239}
3240
3241int
3242i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3243 struct drm_file *file_priv)
3244{
3245 struct drm_i915_gem_madvise *args = data;
3246 struct drm_i915_gem_object *obj;
3247 int ret;
3248
3249 switch (args->madv) {
3250 case I915_MADV_DONTNEED:
3251 case I915_MADV_WILLNEED:
3252 break;
3253 default:
3254 return -EINVAL;
3255 }
3256
3257 ret = i915_mutex_lock_interruptible(dev);
3258 if (ret)
3259 return ret;
3260
3261 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3262 if (&obj->base == NULL) {
3263 ret = -ENOENT;
3264 goto unlock;
3265 }
3266
3267 if (obj->pin_count) {
3268 ret = -EINVAL;
3269 goto out;
3270 }
3271
3272 if (obj->madv != __I915_MADV_PURGED)
3273 obj->madv = args->madv;
3274
3275 /* if the object is no longer bound, discard its backing storage */
3276 if (i915_gem_object_is_purgeable(obj) &&
3277 obj->gtt_space == NULL)
3278 i915_gem_object_truncate(obj);
3279
3280 args->retained = obj->madv != __I915_MADV_PURGED;
3281
3282out:
3283 drm_gem_object_unreference(&obj->base);
3284unlock:
3285 mutex_unlock(&dev->struct_mutex);
3286 return ret;
3287}
3288
3289struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3290 size_t size)
3291{
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct drm_i915_gem_object *obj;
3294 struct address_space *mapping;
3295 u32 mask;
3296
3297 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3298 if (obj == NULL)
3299 return NULL;
3300
3301 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3302 kfree(obj);
3303 return NULL;
3304 }
3305
3306 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3307 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3308 /* 965gm cannot relocate objects above 4GiB. */
3309 mask &= ~__GFP_HIGHMEM;
3310 mask |= __GFP_DMA32;
3311 }
3312
3313 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3314 mapping_set_gfp_mask(mapping, mask);
3315
3316 i915_gem_info_add_obj(dev_priv, size);
3317
3318 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3319 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3320
3321 if (HAS_LLC(dev)) {
3322 /* On some devices, we can have the GPU use the LLC (the CPU
3323 * cache) for about a 10% performance improvement
3324 * compared to uncached. Graphics requests other than
3325 * display scanout are coherent with the CPU in
3326 * accessing this cache. This means in this mode we
3327 * don't need to clflush on the CPU side, and on the
3328 * GPU side we only need to flush internal caches to
3329 * get data visible to the CPU.
3330 *
3331 * However, we maintain the display planes as UC, and so
3332 * need to rebind when first used as such.
3333 */
3334 obj->cache_level = I915_CACHE_LLC;
3335 } else
3336 obj->cache_level = I915_CACHE_NONE;
3337
3338 obj->base.driver_private = NULL;
3339 obj->fence_reg = I915_FENCE_REG_NONE;
3340 INIT_LIST_HEAD(&obj->mm_list);
3341 INIT_LIST_HEAD(&obj->gtt_list);
3342 INIT_LIST_HEAD(&obj->ring_list);
3343 INIT_LIST_HEAD(&obj->exec_list);
3344 INIT_LIST_HEAD(&obj->gpu_write_list);
3345 obj->madv = I915_MADV_WILLNEED;
3346 /* Avoid an unnecessary call to unbind on the first bind. */
3347 obj->map_and_fenceable = true;
3348
3349 return obj;
3350}
3351
3352int i915_gem_init_object(struct drm_gem_object *obj)
3353{
3354 BUG();
3355
3356 return 0;
3357}
3358
3359void i915_gem_free_object(struct drm_gem_object *gem_obj)
3360{
3361 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3362 struct drm_device *dev = obj->base.dev;
3363 drm_i915_private_t *dev_priv = dev->dev_private;
3364
3365 trace_i915_gem_object_destroy(obj);
3366
3367 if (gem_obj->import_attach)
3368 drm_prime_gem_destroy(gem_obj, obj->sg_table);
3369
3370 if (obj->phys_obj)
3371 i915_gem_detach_phys_object(dev, obj);
3372
3373 obj->pin_count = 0;
3374 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3375 bool was_interruptible;
3376
3377 was_interruptible = dev_priv->mm.interruptible;
3378 dev_priv->mm.interruptible = false;
3379
3380 WARN_ON(i915_gem_object_unbind(obj));
3381
3382 dev_priv->mm.interruptible = was_interruptible;
3383 }
3384
3385 if (obj->base.map_list.map)
3386 drm_gem_free_mmap_offset(&obj->base);
3387
3388 drm_gem_object_release(&obj->base);
3389 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3390
3391 kfree(obj->bit_17);
3392 kfree(obj);
3393}
3394
3395int
3396i915_gem_idle(struct drm_device *dev)
3397{
3398 drm_i915_private_t *dev_priv = dev->dev_private;
3399 int ret;
3400
3401 mutex_lock(&dev->struct_mutex);
3402
3403 if (dev_priv->mm.suspended) {
3404 mutex_unlock(&dev->struct_mutex);
3405 return 0;
3406 }
3407
3408 ret = i915_gpu_idle(dev);
3409 if (ret) {
3410 mutex_unlock(&dev->struct_mutex);
3411 return ret;
3412 }
3413 i915_gem_retire_requests(dev);
3414
3415 /* Under UMS, be paranoid and evict. */
3416 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3417 i915_gem_evict_everything(dev, false);
3418
3419 i915_gem_reset_fences(dev);
3420
3421 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3422 * We need to replace this with a semaphore, or something.
3423 * And not confound mm.suspended!
3424 */
3425 dev_priv->mm.suspended = 1;
3426 del_timer_sync(&dev_priv->hangcheck_timer);
3427
3428 i915_kernel_lost_context(dev);
3429 i915_gem_cleanup_ringbuffer(dev);
3430
3431 mutex_unlock(&dev->struct_mutex);
3432
3433 /* Cancel the retire work handler, which should be idle now. */
3434 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3435
3436 return 0;
3437}
3438
3439void i915_gem_init_swizzling(struct drm_device *dev)
3440{
3441 drm_i915_private_t *dev_priv = dev->dev_private;
3442
3443 if (INTEL_INFO(dev)->gen < 5 ||
3444 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3445 return;
3446
3447 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3448 DISP_TILE_SURFACE_SWIZZLING);
3449
3450 if (IS_GEN5(dev))
3451 return;
3452
3453 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3454 if (IS_GEN6(dev))
3455 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3456 else
3457 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3458}
3459
3460void i915_gem_init_ppgtt(struct drm_device *dev)
3461{
3462 drm_i915_private_t *dev_priv = dev->dev_private;
3463 uint32_t pd_offset;
3464 struct intel_ring_buffer *ring;
3465 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3466 uint32_t __iomem *pd_addr;
3467 uint32_t pd_entry;
3468 int i;
3469
3470 if (!dev_priv->mm.aliasing_ppgtt)
3471 return;
3472
3473
3474 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3475 for (i = 0; i < ppgtt->num_pd_entries; i++) {
3476 dma_addr_t pt_addr;
3477
3478 if (dev_priv->mm.gtt->needs_dmar)
3479 pt_addr = ppgtt->pt_dma_addr[i];
3480 else
3481 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3482
3483 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3484 pd_entry |= GEN6_PDE_VALID;
3485
3486 writel(pd_entry, pd_addr + i);
3487 }
3488 readl(pd_addr);
3489
3490 pd_offset = ppgtt->pd_offset;
3491 pd_offset /= 64; /* in cachelines, */
3492 pd_offset <<= 16;
3493
3494 if (INTEL_INFO(dev)->gen == 6) {
3495 uint32_t ecochk, gab_ctl, ecobits;
3496
3497 ecobits = I915_READ(GAC_ECO_BITS);
3498 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
3499
3500 gab_ctl = I915_READ(GAB_CTL);
3501 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3502
3503 ecochk = I915_READ(GAM_ECOCHK);
3504 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3505 ECOCHK_PPGTT_CACHE64B);
3506 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3507 } else if (INTEL_INFO(dev)->gen >= 7) {
3508 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3509 /* GFX_MODE is per-ring on gen7+ */
3510 }
3511
3512 for_each_ring(ring, dev_priv, i) {
3513 if (INTEL_INFO(dev)->gen >= 7)
3514 I915_WRITE(RING_MODE_GEN7(ring),
3515 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3516
3517 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3518 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3519 }
3520}
3521
3522int
3523i915_gem_init_hw(struct drm_device *dev)
3524{
3525 drm_i915_private_t *dev_priv = dev->dev_private;
3526 int ret;
3527
3528 i915_gem_init_swizzling(dev);
3529
3530 ret = intel_init_render_ring_buffer(dev);
3531 if (ret)
3532 return ret;
3533
3534 if (HAS_BSD(dev)) {
3535 ret = intel_init_bsd_ring_buffer(dev);
3536 if (ret)
3537 goto cleanup_render_ring;
3538 }
3539
3540 if (HAS_BLT(dev)) {
3541 ret = intel_init_blt_ring_buffer(dev);
3542 if (ret)
3543 goto cleanup_bsd_ring;
3544 }
3545
3546 dev_priv->next_seqno = 1;
3547
3548 i915_gem_init_ppgtt(dev);
3549
3550 return 0;
3551
3552cleanup_bsd_ring:
3553 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3554cleanup_render_ring:
3555 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3556 return ret;
3557}
3558
3559static bool
3560intel_enable_ppgtt(struct drm_device *dev)
3561{
3562 if (i915_enable_ppgtt >= 0)
3563 return i915_enable_ppgtt;
3564
3565#ifdef CONFIG_INTEL_IOMMU
3566 /* Disable ppgtt on SNB if VT-d is on. */
3567 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3568 return false;
3569#endif
3570
3571 return true;
3572}
3573
3574int i915_gem_init(struct drm_device *dev)
3575{
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577 unsigned long gtt_size, mappable_size;
3578 int ret;
3579
3580 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3581 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3582
3583 mutex_lock(&dev->struct_mutex);
3584 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3585 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3586 * aperture accordingly when using aliasing ppgtt. */
3587 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3588
3589 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3590
3591 ret = i915_gem_init_aliasing_ppgtt(dev);
3592 if (ret) {
3593 mutex_unlock(&dev->struct_mutex);
3594 return ret;
3595 }
3596 } else {
3597 /* Let GEM Manage all of the aperture.
3598 *
3599 * However, leave one page at the end still bound to the scratch
3600 * page. There are a number of places where the hardware
3601 * apparently prefetches past the end of the object, and we've
3602 * seen multiple hangs with the GPU head pointer stuck in a
3603 * batchbuffer bound at the last page of the aperture. One page
3604 * should be enough to keep any prefetching inside of the
3605 * aperture.
3606 */
3607 i915_gem_init_global_gtt(dev, 0, mappable_size,
3608 gtt_size);
3609 }
3610
3611 ret = i915_gem_init_hw(dev);
3612 mutex_unlock(&dev->struct_mutex);
3613 if (ret) {
3614 i915_gem_cleanup_aliasing_ppgtt(dev);
3615 return ret;
3616 }
3617
3618 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3619 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3620 dev_priv->dri1.allow_batchbuffer = 1;
3621 return 0;
3622}
3623
3624void
3625i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3626{
3627 drm_i915_private_t *dev_priv = dev->dev_private;
3628 struct intel_ring_buffer *ring;
3629 int i;
3630
3631 for_each_ring(ring, dev_priv, i)
3632 intel_cleanup_ring_buffer(ring);
3633}
3634
3635int
3636i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3637 struct drm_file *file_priv)
3638{
3639 drm_i915_private_t *dev_priv = dev->dev_private;
3640 int ret;
3641
3642 if (drm_core_check_feature(dev, DRIVER_MODESET))
3643 return 0;
3644
3645 if (atomic_read(&dev_priv->mm.wedged)) {
3646 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3647 atomic_set(&dev_priv->mm.wedged, 0);
3648 }
3649
3650 mutex_lock(&dev->struct_mutex);
3651 dev_priv->mm.suspended = 0;
3652
3653 ret = i915_gem_init_hw(dev);
3654 if (ret != 0) {
3655 mutex_unlock(&dev->struct_mutex);
3656 return ret;
3657 }
3658
3659 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3660 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3661 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3662 mutex_unlock(&dev->struct_mutex);
3663
3664 ret = drm_irq_install(dev);
3665 if (ret)
3666 goto cleanup_ringbuffer;
3667
3668 return 0;
3669
3670cleanup_ringbuffer:
3671 mutex_lock(&dev->struct_mutex);
3672 i915_gem_cleanup_ringbuffer(dev);
3673 dev_priv->mm.suspended = 1;
3674 mutex_unlock(&dev->struct_mutex);
3675
3676 return ret;
3677}
3678
3679int
3680i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3681 struct drm_file *file_priv)
3682{
3683 if (drm_core_check_feature(dev, DRIVER_MODESET))
3684 return 0;
3685
3686 drm_irq_uninstall(dev);
3687 return i915_gem_idle(dev);
3688}
3689
3690void
3691i915_gem_lastclose(struct drm_device *dev)
3692{
3693 int ret;
3694
3695 if (drm_core_check_feature(dev, DRIVER_MODESET))
3696 return;
3697
3698 ret = i915_gem_idle(dev);
3699 if (ret)
3700 DRM_ERROR("failed to idle hardware: %d\n", ret);
3701}
3702
3703static void
3704init_ring_lists(struct intel_ring_buffer *ring)
3705{
3706 INIT_LIST_HEAD(&ring->active_list);
3707 INIT_LIST_HEAD(&ring->request_list);
3708 INIT_LIST_HEAD(&ring->gpu_write_list);
3709}
3710
3711void
3712i915_gem_load(struct drm_device *dev)
3713{
3714 int i;
3715 drm_i915_private_t *dev_priv = dev->dev_private;
3716
3717 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3718 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3719 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3720 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3721 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3722 for (i = 0; i < I915_NUM_RINGS; i++)
3723 init_ring_lists(&dev_priv->ring[i]);
3724 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3725 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3726 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3727 i915_gem_retire_work_handler);
3728 init_completion(&dev_priv->error_completion);
3729
3730 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3731 if (IS_GEN3(dev)) {
3732 I915_WRITE(MI_ARB_STATE,
3733 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3734 }
3735
3736 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3737
3738 /* Old X drivers will take 0-2 for front, back, depth buffers */
3739 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3740 dev_priv->fence_reg_start = 3;
3741
3742 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3743 dev_priv->num_fence_regs = 16;
3744 else
3745 dev_priv->num_fence_regs = 8;
3746
3747 /* Initialize fence registers to zero */
3748 i915_gem_reset_fences(dev);
3749
3750 i915_gem_detect_bit_6_swizzle(dev);
3751 init_waitqueue_head(&dev_priv->pending_flip_queue);
3752
3753 dev_priv->mm.interruptible = true;
3754
3755 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3756 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3757 register_shrinker(&dev_priv->mm.inactive_shrinker);
3758}
3759
3760/*
3761 * Create a physically contiguous memory object for this object
3762 * e.g. for cursor + overlay regs
3763 */
3764static int i915_gem_init_phys_object(struct drm_device *dev,
3765 int id, int size, int align)
3766{
3767 drm_i915_private_t *dev_priv = dev->dev_private;
3768 struct drm_i915_gem_phys_object *phys_obj;
3769 int ret;
3770
3771 if (dev_priv->mm.phys_objs[id - 1] || !size)
3772 return 0;
3773
3774 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3775 if (!phys_obj)
3776 return -ENOMEM;
3777
3778 phys_obj->id = id;
3779
3780 phys_obj->handle = drm_pci_alloc(dev, size, align);
3781 if (!phys_obj->handle) {
3782 ret = -ENOMEM;
3783 goto kfree_obj;
3784 }
3785#ifdef CONFIG_X86
3786 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3787#endif
3788
3789 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3790
3791 return 0;
3792kfree_obj:
3793 kfree(phys_obj);
3794 return ret;
3795}
3796
3797static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3798{
3799 drm_i915_private_t *dev_priv = dev->dev_private;
3800 struct drm_i915_gem_phys_object *phys_obj;
3801
3802 if (!dev_priv->mm.phys_objs[id - 1])
3803 return;
3804
3805 phys_obj = dev_priv->mm.phys_objs[id - 1];
3806 if (phys_obj->cur_obj) {
3807 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3808 }
3809
3810#ifdef CONFIG_X86
3811 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3812#endif
3813 drm_pci_free(dev, phys_obj->handle);
3814 kfree(phys_obj);
3815 dev_priv->mm.phys_objs[id - 1] = NULL;
3816}
3817
3818void i915_gem_free_all_phys_object(struct drm_device *dev)
3819{
3820 int i;
3821
3822 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3823 i915_gem_free_phys_object(dev, i);
3824}
3825
3826void i915_gem_detach_phys_object(struct drm_device *dev,
3827 struct drm_i915_gem_object *obj)
3828{
3829 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3830 char *vaddr;
3831 int i;
3832 int page_count;
3833
3834 if (!obj->phys_obj)
3835 return;
3836 vaddr = obj->phys_obj->handle->vaddr;
3837
3838 page_count = obj->base.size / PAGE_SIZE;
3839 for (i = 0; i < page_count; i++) {
3840 struct page *page = shmem_read_mapping_page(mapping, i);
3841 if (!IS_ERR(page)) {
3842 char *dst = kmap_atomic(page);
3843 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3844 kunmap_atomic(dst);
3845
3846 drm_clflush_pages(&page, 1);
3847
3848 set_page_dirty(page);
3849 mark_page_accessed(page);
3850 page_cache_release(page);
3851 }
3852 }
3853 intel_gtt_chipset_flush();
3854
3855 obj->phys_obj->cur_obj = NULL;
3856 obj->phys_obj = NULL;
3857}
3858
3859int
3860i915_gem_attach_phys_object(struct drm_device *dev,
3861 struct drm_i915_gem_object *obj,
3862 int id,
3863 int align)
3864{
3865 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3866 drm_i915_private_t *dev_priv = dev->dev_private;
3867 int ret = 0;
3868 int page_count;
3869 int i;
3870
3871 if (id > I915_MAX_PHYS_OBJECT)
3872 return -EINVAL;
3873
3874 if (obj->phys_obj) {
3875 if (obj->phys_obj->id == id)
3876 return 0;
3877 i915_gem_detach_phys_object(dev, obj);
3878 }
3879
3880 /* create a new object */
3881 if (!dev_priv->mm.phys_objs[id - 1]) {
3882 ret = i915_gem_init_phys_object(dev, id,
3883 obj->base.size, align);
3884 if (ret) {
3885 DRM_ERROR("failed to init phys object %d size: %zu\n",
3886 id, obj->base.size);
3887 return ret;
3888 }
3889 }
3890
3891 /* bind to the object */
3892 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3893 obj->phys_obj->cur_obj = obj;
3894
3895 page_count = obj->base.size / PAGE_SIZE;
3896
3897 for (i = 0; i < page_count; i++) {
3898 struct page *page;
3899 char *dst, *src;
3900
3901 page = shmem_read_mapping_page(mapping, i);
3902 if (IS_ERR(page))
3903 return PTR_ERR(page);
3904
3905 src = kmap_atomic(page);
3906 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3907 memcpy(dst, src, PAGE_SIZE);
3908 kunmap_atomic(src);
3909
3910 mark_page_accessed(page);
3911 page_cache_release(page);
3912 }
3913
3914 return 0;
3915}
3916
3917static int
3918i915_gem_phys_pwrite(struct drm_device *dev,
3919 struct drm_i915_gem_object *obj,
3920 struct drm_i915_gem_pwrite *args,
3921 struct drm_file *file_priv)
3922{
3923 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
3924 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
3925
3926 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
3927 unsigned long unwritten;
3928
3929 /* The physical object once assigned is fixed for the lifetime
3930 * of the obj, so we can safely drop the lock and continue
3931 * to access vaddr.
3932 */
3933 mutex_unlock(&dev->struct_mutex);
3934 unwritten = copy_from_user(vaddr, user_data, args->size);
3935 mutex_lock(&dev->struct_mutex);
3936 if (unwritten)
3937 return -EFAULT;
3938 }
3939
3940 intel_gtt_chipset_flush();
3941 return 0;
3942}
3943
3944void i915_gem_release(struct drm_device *dev, struct drm_file *file)
3945{
3946 struct drm_i915_file_private *file_priv = file->driver_priv;
3947
3948 /* Clean up our request list when the client is going away, so that
3949 * later retire_requests won't dereference our soon-to-be-gone
3950 * file_priv.
3951 */
3952 spin_lock(&file_priv->mm.lock);
3953 while (!list_empty(&file_priv->mm.request_list)) {
3954 struct drm_i915_gem_request *request;
3955
3956 request = list_first_entry(&file_priv->mm.request_list,
3957 struct drm_i915_gem_request,
3958 client_list);
3959 list_del(&request->client_list);
3960 request->file_priv = NULL;
3961 }
3962 spin_unlock(&file_priv->mm.lock);
3963}
3964
3965static int
3966i915_gpu_is_active(struct drm_device *dev)
3967{
3968 drm_i915_private_t *dev_priv = dev->dev_private;
3969 int lists_empty;
3970
3971 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
3972 list_empty(&dev_priv->mm.active_list);
3973
3974 return !lists_empty;
3975}
3976
3977static int
3978i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
3979{
3980 struct drm_i915_private *dev_priv =
3981 container_of(shrinker,
3982 struct drm_i915_private,
3983 mm.inactive_shrinker);
3984 struct drm_device *dev = dev_priv->dev;
3985 struct drm_i915_gem_object *obj, *next;
3986 int nr_to_scan = sc->nr_to_scan;
3987 int cnt;
3988
3989 if (!mutex_trylock(&dev->struct_mutex))
3990 return 0;
3991
3992 /* "fast-path" to count number of available objects */
3993 if (nr_to_scan == 0) {
3994 cnt = 0;
3995 list_for_each_entry(obj,
3996 &dev_priv->mm.inactive_list,
3997 mm_list)
3998 cnt++;
3999 mutex_unlock(&dev->struct_mutex);
4000 return cnt / 100 * sysctl_vfs_cache_pressure;
4001 }
4002
4003rescan:
4004 /* first scan for clean buffers */
4005 i915_gem_retire_requests(dev);
4006
4007 list_for_each_entry_safe(obj, next,
4008 &dev_priv->mm.inactive_list,
4009 mm_list) {
4010 if (i915_gem_object_is_purgeable(obj)) {
4011 if (i915_gem_object_unbind(obj) == 0 &&
4012 --nr_to_scan == 0)
4013 break;
4014 }
4015 }
4016
4017 /* second pass, evict/count anything still on the inactive list */
4018 cnt = 0;
4019 list_for_each_entry_safe(obj, next,
4020 &dev_priv->mm.inactive_list,
4021 mm_list) {
4022 if (nr_to_scan &&
4023 i915_gem_object_unbind(obj) == 0)
4024 nr_to_scan--;
4025 else
4026 cnt++;
4027 }
4028
4029 if (nr_to_scan && i915_gpu_is_active(dev)) {
4030 /*
4031 * We are desperate for pages, so as a last resort, wait
4032 * for the GPU to finish and discard whatever we can.
4033 * This has a dramatic impact to reduce the number of
4034 * OOM-killer events whilst running the GPU aggressively.
4035 */
4036 if (i915_gpu_idle(dev) == 0)
4037 goto rescan;
4038 }
4039 mutex_unlock(&dev->struct_mutex);
4040 return cnt / 100 * sysctl_vfs_cache_pressure;
4041}