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1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33#define SUPPORT_SYSRQ
34#endif
35
36#include <linux/module.h>
37#include <linux/ioport.h>
38#include <linux/init.h>
39#include <linux/console.h>
40#include <linux/sysrq.h>
41#include <linux/device.h>
42#include <linux/tty.h>
43#include <linux/tty_flip.h>
44#include <linux/serial_core.h>
45#include <linux/serial.h>
46#include <linux/amba/bus.h>
47#include <linux/amba/serial.h>
48#include <linux/clk.h>
49#include <linux/slab.h>
50#include <linux/dmaengine.h>
51#include <linux/dma-mapping.h>
52#include <linux/scatterlist.h>
53#include <linux/delay.h>
54
55#include <asm/io.h>
56#include <asm/sizes.h>
57
58#define UART_NR 14
59
60#define SERIAL_AMBA_MAJOR 204
61#define SERIAL_AMBA_MINOR 64
62#define SERIAL_AMBA_NR UART_NR
63
64#define AMBA_ISR_PASS_LIMIT 256
65
66#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
67#define UART_DUMMY_DR_RX (1 << 16)
68
69
70#define UART_WA_SAVE_NR 14
71
72static void pl011_lockup_wa(unsigned long data);
73static const u32 uart_wa_reg[UART_WA_SAVE_NR] = {
74 ST_UART011_DMAWM,
75 ST_UART011_TIMEOUT,
76 ST_UART011_LCRH_RX,
77 UART011_IBRD,
78 UART011_FBRD,
79 ST_UART011_LCRH_TX,
80 UART011_IFLS,
81 ST_UART011_XFCR,
82 ST_UART011_XON1,
83 ST_UART011_XON2,
84 ST_UART011_XOFF1,
85 ST_UART011_XOFF2,
86 UART011_CR,
87 UART011_IMSC
88};
89
90static u32 uart_wa_regdata[UART_WA_SAVE_NR];
91static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0);
92
93/* There is by now at least one vendor with differing details, so handle it */
94struct vendor_data {
95 unsigned int ifls;
96 unsigned int fifosize;
97 unsigned int lcrh_tx;
98 unsigned int lcrh_rx;
99 bool oversampling;
100 bool interrupt_may_hang; /* vendor-specific */
101 bool dma_threshold;
102};
103
104static struct vendor_data vendor_arm = {
105 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
106 .fifosize = 16,
107 .lcrh_tx = UART011_LCRH,
108 .lcrh_rx = UART011_LCRH,
109 .oversampling = false,
110 .dma_threshold = false,
111};
112
113static struct vendor_data vendor_st = {
114 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
115 .fifosize = 64,
116 .lcrh_tx = ST_UART011_LCRH_TX,
117 .lcrh_rx = ST_UART011_LCRH_RX,
118 .oversampling = true,
119 .interrupt_may_hang = true,
120 .dma_threshold = true,
121};
122
123static struct uart_amba_port *amba_ports[UART_NR];
124
125/* Deals with DMA transactions */
126
127struct pl011_sgbuf {
128 struct scatterlist sg;
129 char *buf;
130};
131
132struct pl011_dmarx_data {
133 struct dma_chan *chan;
134 struct completion complete;
135 bool use_buf_b;
136 struct pl011_sgbuf sgbuf_a;
137 struct pl011_sgbuf sgbuf_b;
138 dma_cookie_t cookie;
139 bool running;
140};
141
142struct pl011_dmatx_data {
143 struct dma_chan *chan;
144 struct scatterlist sg;
145 char *buf;
146 bool queued;
147};
148
149/*
150 * We wrap our port structure around the generic uart_port.
151 */
152struct uart_amba_port {
153 struct uart_port port;
154 struct clk *clk;
155 const struct vendor_data *vendor;
156 unsigned int dmacr; /* dma control reg */
157 unsigned int im; /* interrupt mask */
158 unsigned int old_status;
159 unsigned int fifosize; /* vendor-specific */
160 unsigned int lcrh_tx; /* vendor-specific */
161 unsigned int lcrh_rx; /* vendor-specific */
162 bool autorts;
163 char type[12];
164 bool interrupt_may_hang; /* vendor-specific */
165#ifdef CONFIG_DMA_ENGINE
166 /* DMA stuff */
167 bool using_tx_dma;
168 bool using_rx_dma;
169 struct pl011_dmarx_data dmarx;
170 struct pl011_dmatx_data dmatx;
171#endif
172};
173
174/*
175 * Reads up to 256 characters from the FIFO or until it's empty and
176 * inserts them into the TTY layer. Returns the number of characters
177 * read from the FIFO.
178 */
179static int pl011_fifo_to_tty(struct uart_amba_port *uap)
180{
181 u16 status, ch;
182 unsigned int flag, max_count = 256;
183 int fifotaken = 0;
184
185 while (max_count--) {
186 status = readw(uap->port.membase + UART01x_FR);
187 if (status & UART01x_FR_RXFE)
188 break;
189
190 /* Take chars from the FIFO and update status */
191 ch = readw(uap->port.membase + UART01x_DR) |
192 UART_DUMMY_DR_RX;
193 flag = TTY_NORMAL;
194 uap->port.icount.rx++;
195 fifotaken++;
196
197 if (unlikely(ch & UART_DR_ERROR)) {
198 if (ch & UART011_DR_BE) {
199 ch &= ~(UART011_DR_FE | UART011_DR_PE);
200 uap->port.icount.brk++;
201 if (uart_handle_break(&uap->port))
202 continue;
203 } else if (ch & UART011_DR_PE)
204 uap->port.icount.parity++;
205 else if (ch & UART011_DR_FE)
206 uap->port.icount.frame++;
207 if (ch & UART011_DR_OE)
208 uap->port.icount.overrun++;
209
210 ch &= uap->port.read_status_mask;
211
212 if (ch & UART011_DR_BE)
213 flag = TTY_BREAK;
214 else if (ch & UART011_DR_PE)
215 flag = TTY_PARITY;
216 else if (ch & UART011_DR_FE)
217 flag = TTY_FRAME;
218 }
219
220 if (uart_handle_sysrq_char(&uap->port, ch & 255))
221 continue;
222
223 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
224 }
225
226 return fifotaken;
227}
228
229
230/*
231 * All the DMA operation mode stuff goes inside this ifdef.
232 * This assumes that you have a generic DMA device interface,
233 * no custom DMA interfaces are supported.
234 */
235#ifdef CONFIG_DMA_ENGINE
236
237#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
238
239static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
240 enum dma_data_direction dir)
241{
242 sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
243 if (!sg->buf)
244 return -ENOMEM;
245
246 sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
247
248 if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
249 kfree(sg->buf);
250 return -EINVAL;
251 }
252 return 0;
253}
254
255static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
256 enum dma_data_direction dir)
257{
258 if (sg->buf) {
259 dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
260 kfree(sg->buf);
261 }
262}
263
264static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
265{
266 /* DMA is the sole user of the platform data right now */
267 struct amba_pl011_data *plat = uap->port.dev->platform_data;
268 struct dma_slave_config tx_conf = {
269 .dst_addr = uap->port.mapbase + UART01x_DR,
270 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
271 .direction = DMA_TO_DEVICE,
272 .dst_maxburst = uap->fifosize >> 1,
273 };
274 struct dma_chan *chan;
275 dma_cap_mask_t mask;
276
277 /* We need platform data */
278 if (!plat || !plat->dma_filter) {
279 dev_info(uap->port.dev, "no DMA platform data\n");
280 return;
281 }
282
283 /* Try to acquire a generic DMA engine slave TX channel */
284 dma_cap_zero(mask);
285 dma_cap_set(DMA_SLAVE, mask);
286
287 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
288 if (!chan) {
289 dev_err(uap->port.dev, "no TX DMA channel!\n");
290 return;
291 }
292
293 dmaengine_slave_config(chan, &tx_conf);
294 uap->dmatx.chan = chan;
295
296 dev_info(uap->port.dev, "DMA channel TX %s\n",
297 dma_chan_name(uap->dmatx.chan));
298
299 /* Optionally make use of an RX channel as well */
300 if (plat->dma_rx_param) {
301 struct dma_slave_config rx_conf = {
302 .src_addr = uap->port.mapbase + UART01x_DR,
303 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
304 .direction = DMA_FROM_DEVICE,
305 .src_maxburst = uap->fifosize >> 1,
306 };
307
308 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
309 if (!chan) {
310 dev_err(uap->port.dev, "no RX DMA channel!\n");
311 return;
312 }
313
314 dmaengine_slave_config(chan, &rx_conf);
315 uap->dmarx.chan = chan;
316
317 dev_info(uap->port.dev, "DMA channel RX %s\n",
318 dma_chan_name(uap->dmarx.chan));
319 }
320}
321
322#ifndef MODULE
323/*
324 * Stack up the UARTs and let the above initcall be done at device
325 * initcall time, because the serial driver is called as an arch
326 * initcall, and at this time the DMA subsystem is not yet registered.
327 * At this point the driver will switch over to using DMA where desired.
328 */
329struct dma_uap {
330 struct list_head node;
331 struct uart_amba_port *uap;
332};
333
334static LIST_HEAD(pl011_dma_uarts);
335
336static int __init pl011_dma_initcall(void)
337{
338 struct list_head *node, *tmp;
339
340 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
341 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
342 pl011_dma_probe_initcall(dmau->uap);
343 list_del(node);
344 kfree(dmau);
345 }
346 return 0;
347}
348
349device_initcall(pl011_dma_initcall);
350
351static void pl011_dma_probe(struct uart_amba_port *uap)
352{
353 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
354 if (dmau) {
355 dmau->uap = uap;
356 list_add_tail(&dmau->node, &pl011_dma_uarts);
357 }
358}
359#else
360static void pl011_dma_probe(struct uart_amba_port *uap)
361{
362 pl011_dma_probe_initcall(uap);
363}
364#endif
365
366static void pl011_dma_remove(struct uart_amba_port *uap)
367{
368 /* TODO: remove the initcall if it has not yet executed */
369 if (uap->dmatx.chan)
370 dma_release_channel(uap->dmatx.chan);
371 if (uap->dmarx.chan)
372 dma_release_channel(uap->dmarx.chan);
373}
374
375/* Forward declare this for the refill routine */
376static int pl011_dma_tx_refill(struct uart_amba_port *uap);
377
378/*
379 * The current DMA TX buffer has been sent.
380 * Try to queue up another DMA buffer.
381 */
382static void pl011_dma_tx_callback(void *data)
383{
384 struct uart_amba_port *uap = data;
385 struct pl011_dmatx_data *dmatx = &uap->dmatx;
386 unsigned long flags;
387 u16 dmacr;
388
389 spin_lock_irqsave(&uap->port.lock, flags);
390 if (uap->dmatx.queued)
391 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
392 DMA_TO_DEVICE);
393
394 dmacr = uap->dmacr;
395 uap->dmacr = dmacr & ~UART011_TXDMAE;
396 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
397
398 /*
399 * If TX DMA was disabled, it means that we've stopped the DMA for
400 * some reason (eg, XOFF received, or we want to send an X-char.)
401 *
402 * Note: we need to be careful here of a potential race between DMA
403 * and the rest of the driver - if the driver disables TX DMA while
404 * a TX buffer completing, we must update the tx queued status to
405 * get further refills (hence we check dmacr).
406 */
407 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
408 uart_circ_empty(&uap->port.state->xmit)) {
409 uap->dmatx.queued = false;
410 spin_unlock_irqrestore(&uap->port.lock, flags);
411 return;
412 }
413
414 if (pl011_dma_tx_refill(uap) <= 0) {
415 /*
416 * We didn't queue a DMA buffer for some reason, but we
417 * have data pending to be sent. Re-enable the TX IRQ.
418 */
419 uap->im |= UART011_TXIM;
420 writew(uap->im, uap->port.membase + UART011_IMSC);
421 }
422 spin_unlock_irqrestore(&uap->port.lock, flags);
423}
424
425/*
426 * Try to refill the TX DMA buffer.
427 * Locking: called with port lock held and IRQs disabled.
428 * Returns:
429 * 1 if we queued up a TX DMA buffer.
430 * 0 if we didn't want to handle this by DMA
431 * <0 on error
432 */
433static int pl011_dma_tx_refill(struct uart_amba_port *uap)
434{
435 struct pl011_dmatx_data *dmatx = &uap->dmatx;
436 struct dma_chan *chan = dmatx->chan;
437 struct dma_device *dma_dev = chan->device;
438 struct dma_async_tx_descriptor *desc;
439 struct circ_buf *xmit = &uap->port.state->xmit;
440 unsigned int count;
441
442 /*
443 * Try to avoid the overhead involved in using DMA if the
444 * transaction fits in the first half of the FIFO, by using
445 * the standard interrupt handling. This ensures that we
446 * issue a uart_write_wakeup() at the appropriate time.
447 */
448 count = uart_circ_chars_pending(xmit);
449 if (count < (uap->fifosize >> 1)) {
450 uap->dmatx.queued = false;
451 return 0;
452 }
453
454 /*
455 * Bodge: don't send the last character by DMA, as this
456 * will prevent XON from notifying us to restart DMA.
457 */
458 count -= 1;
459
460 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
461 if (count > PL011_DMA_BUFFER_SIZE)
462 count = PL011_DMA_BUFFER_SIZE;
463
464 if (xmit->tail < xmit->head)
465 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
466 else {
467 size_t first = UART_XMIT_SIZE - xmit->tail;
468 size_t second = xmit->head;
469
470 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
471 if (second)
472 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
473 }
474
475 dmatx->sg.length = count;
476
477 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
478 uap->dmatx.queued = false;
479 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
480 return -EBUSY;
481 }
482
483 desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_TO_DEVICE,
484 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
485 if (!desc) {
486 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
487 uap->dmatx.queued = false;
488 /*
489 * If DMA cannot be used right now, we complete this
490 * transaction via IRQ and let the TTY layer retry.
491 */
492 dev_dbg(uap->port.dev, "TX DMA busy\n");
493 return -EBUSY;
494 }
495
496 /* Some data to go along to the callback */
497 desc->callback = pl011_dma_tx_callback;
498 desc->callback_param = uap;
499
500 /* All errors should happen at prepare time */
501 dmaengine_submit(desc);
502
503 /* Fire the DMA transaction */
504 dma_dev->device_issue_pending(chan);
505
506 uap->dmacr |= UART011_TXDMAE;
507 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
508 uap->dmatx.queued = true;
509
510 /*
511 * Now we know that DMA will fire, so advance the ring buffer
512 * with the stuff we just dispatched.
513 */
514 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
515 uap->port.icount.tx += count;
516
517 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
518 uart_write_wakeup(&uap->port);
519
520 return 1;
521}
522
523/*
524 * We received a transmit interrupt without a pending X-char but with
525 * pending characters.
526 * Locking: called with port lock held and IRQs disabled.
527 * Returns:
528 * false if we want to use PIO to transmit
529 * true if we queued a DMA buffer
530 */
531static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
532{
533 if (!uap->using_tx_dma)
534 return false;
535
536 /*
537 * If we already have a TX buffer queued, but received a
538 * TX interrupt, it will be because we've just sent an X-char.
539 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
540 */
541 if (uap->dmatx.queued) {
542 uap->dmacr |= UART011_TXDMAE;
543 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
544 uap->im &= ~UART011_TXIM;
545 writew(uap->im, uap->port.membase + UART011_IMSC);
546 return true;
547 }
548
549 /*
550 * We don't have a TX buffer queued, so try to queue one.
551 * If we successfully queued a buffer, mask the TX IRQ.
552 */
553 if (pl011_dma_tx_refill(uap) > 0) {
554 uap->im &= ~UART011_TXIM;
555 writew(uap->im, uap->port.membase + UART011_IMSC);
556 return true;
557 }
558 return false;
559}
560
561/*
562 * Stop the DMA transmit (eg, due to received XOFF).
563 * Locking: called with port lock held and IRQs disabled.
564 */
565static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
566{
567 if (uap->dmatx.queued) {
568 uap->dmacr &= ~UART011_TXDMAE;
569 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
570 }
571}
572
573/*
574 * Try to start a DMA transmit, or in the case of an XON/OFF
575 * character queued for send, try to get that character out ASAP.
576 * Locking: called with port lock held and IRQs disabled.
577 * Returns:
578 * false if we want the TX IRQ to be enabled
579 * true if we have a buffer queued
580 */
581static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
582{
583 u16 dmacr;
584
585 if (!uap->using_tx_dma)
586 return false;
587
588 if (!uap->port.x_char) {
589 /* no X-char, try to push chars out in DMA mode */
590 bool ret = true;
591
592 if (!uap->dmatx.queued) {
593 if (pl011_dma_tx_refill(uap) > 0) {
594 uap->im &= ~UART011_TXIM;
595 ret = true;
596 } else {
597 uap->im |= UART011_TXIM;
598 ret = false;
599 }
600 writew(uap->im, uap->port.membase + UART011_IMSC);
601 } else if (!(uap->dmacr & UART011_TXDMAE)) {
602 uap->dmacr |= UART011_TXDMAE;
603 writew(uap->dmacr,
604 uap->port.membase + UART011_DMACR);
605 }
606 return ret;
607 }
608
609 /*
610 * We have an X-char to send. Disable DMA to prevent it loading
611 * the TX fifo, and then see if we can stuff it into the FIFO.
612 */
613 dmacr = uap->dmacr;
614 uap->dmacr &= ~UART011_TXDMAE;
615 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
616
617 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
618 /*
619 * No space in the FIFO, so enable the transmit interrupt
620 * so we know when there is space. Note that once we've
621 * loaded the character, we should just re-enable DMA.
622 */
623 return false;
624 }
625
626 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
627 uap->port.icount.tx++;
628 uap->port.x_char = 0;
629
630 /* Success - restore the DMA state */
631 uap->dmacr = dmacr;
632 writew(dmacr, uap->port.membase + UART011_DMACR);
633
634 return true;
635}
636
637/*
638 * Flush the transmit buffer.
639 * Locking: called with port lock held and IRQs disabled.
640 */
641static void pl011_dma_flush_buffer(struct uart_port *port)
642{
643 struct uart_amba_port *uap = (struct uart_amba_port *)port;
644
645 if (!uap->using_tx_dma)
646 return;
647
648 /* Avoid deadlock with the DMA engine callback */
649 spin_unlock(&uap->port.lock);
650 dmaengine_terminate_all(uap->dmatx.chan);
651 spin_lock(&uap->port.lock);
652 if (uap->dmatx.queued) {
653 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
654 DMA_TO_DEVICE);
655 uap->dmatx.queued = false;
656 uap->dmacr &= ~UART011_TXDMAE;
657 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
658 }
659}
660
661static void pl011_dma_rx_callback(void *data);
662
663static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
664{
665 struct dma_chan *rxchan = uap->dmarx.chan;
666 struct dma_device *dma_dev;
667 struct pl011_dmarx_data *dmarx = &uap->dmarx;
668 struct dma_async_tx_descriptor *desc;
669 struct pl011_sgbuf *sgbuf;
670
671 if (!rxchan)
672 return -EIO;
673
674 /* Start the RX DMA job */
675 sgbuf = uap->dmarx.use_buf_b ?
676 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
677 dma_dev = rxchan->device;
678 desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1,
679 DMA_FROM_DEVICE,
680 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
681 /*
682 * If the DMA engine is busy and cannot prepare a
683 * channel, no big deal, the driver will fall back
684 * to interrupt mode as a result of this error code.
685 */
686 if (!desc) {
687 uap->dmarx.running = false;
688 dmaengine_terminate_all(rxchan);
689 return -EBUSY;
690 }
691
692 /* Some data to go along to the callback */
693 desc->callback = pl011_dma_rx_callback;
694 desc->callback_param = uap;
695 dmarx->cookie = dmaengine_submit(desc);
696 dma_async_issue_pending(rxchan);
697
698 uap->dmacr |= UART011_RXDMAE;
699 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
700 uap->dmarx.running = true;
701
702 uap->im &= ~UART011_RXIM;
703 writew(uap->im, uap->port.membase + UART011_IMSC);
704
705 return 0;
706}
707
708/*
709 * This is called when either the DMA job is complete, or
710 * the FIFO timeout interrupt occurred. This must be called
711 * with the port spinlock uap->port.lock held.
712 */
713static void pl011_dma_rx_chars(struct uart_amba_port *uap,
714 u32 pending, bool use_buf_b,
715 bool readfifo)
716{
717 struct tty_struct *tty = uap->port.state->port.tty;
718 struct pl011_sgbuf *sgbuf = use_buf_b ?
719 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
720 struct device *dev = uap->dmarx.chan->device->dev;
721 int dma_count = 0;
722 u32 fifotaken = 0; /* only used for vdbg() */
723
724 /* Pick everything from the DMA first */
725 if (pending) {
726 /* Sync in buffer */
727 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
728
729 /*
730 * First take all chars in the DMA pipe, then look in the FIFO.
731 * Note that tty_insert_flip_buf() tries to take as many chars
732 * as it can.
733 */
734 dma_count = tty_insert_flip_string(uap->port.state->port.tty,
735 sgbuf->buf, pending);
736
737 /* Return buffer to device */
738 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
739
740 uap->port.icount.rx += dma_count;
741 if (dma_count < pending)
742 dev_warn(uap->port.dev,
743 "couldn't insert all characters (TTY is full?)\n");
744 }
745
746 /*
747 * Only continue with trying to read the FIFO if all DMA chars have
748 * been taken first.
749 */
750 if (dma_count == pending && readfifo) {
751 /* Clear any error flags */
752 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
753 uap->port.membase + UART011_ICR);
754
755 /*
756 * If we read all the DMA'd characters, and we had an
757 * incomplete buffer, that could be due to an rx error, or
758 * maybe we just timed out. Read any pending chars and check
759 * the error status.
760 *
761 * Error conditions will only occur in the FIFO, these will
762 * trigger an immediate interrupt and stop the DMA job, so we
763 * will always find the error in the FIFO, never in the DMA
764 * buffer.
765 */
766 fifotaken = pl011_fifo_to_tty(uap);
767 }
768
769 spin_unlock(&uap->port.lock);
770 dev_vdbg(uap->port.dev,
771 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
772 dma_count, fifotaken);
773 tty_flip_buffer_push(tty);
774 spin_lock(&uap->port.lock);
775}
776
777static void pl011_dma_rx_irq(struct uart_amba_port *uap)
778{
779 struct pl011_dmarx_data *dmarx = &uap->dmarx;
780 struct dma_chan *rxchan = dmarx->chan;
781 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
782 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
783 size_t pending;
784 struct dma_tx_state state;
785 enum dma_status dmastat;
786
787 /*
788 * Pause the transfer so we can trust the current counter,
789 * do this before we pause the PL011 block, else we may
790 * overflow the FIFO.
791 */
792 if (dmaengine_pause(rxchan))
793 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
794 dmastat = rxchan->device->device_tx_status(rxchan,
795 dmarx->cookie, &state);
796 if (dmastat != DMA_PAUSED)
797 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
798
799 /* Disable RX DMA - incoming data will wait in the FIFO */
800 uap->dmacr &= ~UART011_RXDMAE;
801 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
802 uap->dmarx.running = false;
803
804 pending = sgbuf->sg.length - state.residue;
805 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
806 /* Then we terminate the transfer - we now know our residue */
807 dmaengine_terminate_all(rxchan);
808
809 /*
810 * This will take the chars we have so far and insert
811 * into the framework.
812 */
813 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
814
815 /* Switch buffer & re-trigger DMA job */
816 dmarx->use_buf_b = !dmarx->use_buf_b;
817 if (pl011_dma_rx_trigger_dma(uap)) {
818 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
819 "fall back to interrupt mode\n");
820 uap->im |= UART011_RXIM;
821 writew(uap->im, uap->port.membase + UART011_IMSC);
822 }
823}
824
825static void pl011_dma_rx_callback(void *data)
826{
827 struct uart_amba_port *uap = data;
828 struct pl011_dmarx_data *dmarx = &uap->dmarx;
829 bool lastbuf = dmarx->use_buf_b;
830 int ret;
831
832 /*
833 * This completion interrupt occurs typically when the
834 * RX buffer is totally stuffed but no timeout has yet
835 * occurred. When that happens, we just want the RX
836 * routine to flush out the secondary DMA buffer while
837 * we immediately trigger the next DMA job.
838 */
839 spin_lock_irq(&uap->port.lock);
840 uap->dmarx.running = false;
841 dmarx->use_buf_b = !lastbuf;
842 ret = pl011_dma_rx_trigger_dma(uap);
843
844 pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false);
845 spin_unlock_irq(&uap->port.lock);
846 /*
847 * Do this check after we picked the DMA chars so we don't
848 * get some IRQ immediately from RX.
849 */
850 if (ret) {
851 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
852 "fall back to interrupt mode\n");
853 uap->im |= UART011_RXIM;
854 writew(uap->im, uap->port.membase + UART011_IMSC);
855 }
856}
857
858/*
859 * Stop accepting received characters, when we're shutting down or
860 * suspending this port.
861 * Locking: called with port lock held and IRQs disabled.
862 */
863static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
864{
865 /* FIXME. Just disable the DMA enable */
866 uap->dmacr &= ~UART011_RXDMAE;
867 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
868}
869
870static void pl011_dma_startup(struct uart_amba_port *uap)
871{
872 int ret;
873
874 if (!uap->dmatx.chan)
875 return;
876
877 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
878 if (!uap->dmatx.buf) {
879 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
880 uap->port.fifosize = uap->fifosize;
881 return;
882 }
883
884 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
885
886 /* The DMA buffer is now the FIFO the TTY subsystem can use */
887 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
888 uap->using_tx_dma = true;
889
890 if (!uap->dmarx.chan)
891 goto skip_rx;
892
893 /* Allocate and map DMA RX buffers */
894 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
895 DMA_FROM_DEVICE);
896 if (ret) {
897 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
898 "RX buffer A", ret);
899 goto skip_rx;
900 }
901
902 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
903 DMA_FROM_DEVICE);
904 if (ret) {
905 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
906 "RX buffer B", ret);
907 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
908 DMA_FROM_DEVICE);
909 goto skip_rx;
910 }
911
912 uap->using_rx_dma = true;
913
914skip_rx:
915 /* Turn on DMA error (RX/TX will be enabled on demand) */
916 uap->dmacr |= UART011_DMAONERR;
917 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
918
919 /*
920 * ST Micro variants has some specific dma burst threshold
921 * compensation. Set this to 16 bytes, so burst will only
922 * be issued above/below 16 bytes.
923 */
924 if (uap->vendor->dma_threshold)
925 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
926 uap->port.membase + ST_UART011_DMAWM);
927
928 if (uap->using_rx_dma) {
929 if (pl011_dma_rx_trigger_dma(uap))
930 dev_dbg(uap->port.dev, "could not trigger initial "
931 "RX DMA job, fall back to interrupt mode\n");
932 }
933}
934
935static void pl011_dma_shutdown(struct uart_amba_port *uap)
936{
937 if (!(uap->using_tx_dma || uap->using_rx_dma))
938 return;
939
940 /* Disable RX and TX DMA */
941 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
942 barrier();
943
944 spin_lock_irq(&uap->port.lock);
945 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
946 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
947 spin_unlock_irq(&uap->port.lock);
948
949 if (uap->using_tx_dma) {
950 /* In theory, this should already be done by pl011_dma_flush_buffer */
951 dmaengine_terminate_all(uap->dmatx.chan);
952 if (uap->dmatx.queued) {
953 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
954 DMA_TO_DEVICE);
955 uap->dmatx.queued = false;
956 }
957
958 kfree(uap->dmatx.buf);
959 uap->using_tx_dma = false;
960 }
961
962 if (uap->using_rx_dma) {
963 dmaengine_terminate_all(uap->dmarx.chan);
964 /* Clean up the RX DMA */
965 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
966 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
967 uap->using_rx_dma = false;
968 }
969}
970
971static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
972{
973 return uap->using_rx_dma;
974}
975
976static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
977{
978 return uap->using_rx_dma && uap->dmarx.running;
979}
980
981
982#else
983/* Blank functions if the DMA engine is not available */
984static inline void pl011_dma_probe(struct uart_amba_port *uap)
985{
986}
987
988static inline void pl011_dma_remove(struct uart_amba_port *uap)
989{
990}
991
992static inline void pl011_dma_startup(struct uart_amba_port *uap)
993{
994}
995
996static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
997{
998}
999
1000static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1001{
1002 return false;
1003}
1004
1005static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1006{
1007}
1008
1009static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1010{
1011 return false;
1012}
1013
1014static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1015{
1016}
1017
1018static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1019{
1020}
1021
1022static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1023{
1024 return -EIO;
1025}
1026
1027static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1028{
1029 return false;
1030}
1031
1032static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1033{
1034 return false;
1035}
1036
1037#define pl011_dma_flush_buffer NULL
1038#endif
1039
1040
1041/*
1042 * pl011_lockup_wa
1043 * This workaround aims to break the deadlock situation
1044 * when after long transfer over uart in hardware flow
1045 * control, uart interrupt registers cannot be cleared.
1046 * Hence uart transfer gets blocked.
1047 *
1048 * It is seen that during such deadlock condition ICR
1049 * don't get cleared even on multiple write. This leads
1050 * pass_counter to decrease and finally reach zero. This
1051 * can be taken as trigger point to run this UART_BT_WA.
1052 *
1053 */
1054static void pl011_lockup_wa(unsigned long data)
1055{
1056 struct uart_amba_port *uap = amba_ports[0];
1057 void __iomem *base = uap->port.membase;
1058 struct circ_buf *xmit = &uap->port.state->xmit;
1059 struct tty_struct *tty = uap->port.state->port.tty;
1060 int buf_empty_retries = 200;
1061 int loop;
1062
1063 /* Stop HCI layer from submitting data for tx */
1064 tty->hw_stopped = 1;
1065 while (!uart_circ_empty(xmit)) {
1066 if (buf_empty_retries-- == 0)
1067 break;
1068 udelay(100);
1069 }
1070
1071 /* Backup registers */
1072 for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
1073 uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]);
1074
1075 /* Disable UART so that FIFO data is flushed out */
1076 writew(0x00, uap->port.membase + UART011_CR);
1077
1078 /* Soft reset UART module */
1079 if (uap->port.dev->platform_data) {
1080 struct amba_pl011_data *plat;
1081
1082 plat = uap->port.dev->platform_data;
1083 if (plat->reset)
1084 plat->reset();
1085 }
1086
1087 /* Restore registers */
1088 for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
1089 writew(uart_wa_regdata[loop] ,
1090 uap->port.membase + uart_wa_reg[loop]);
1091
1092 /* Initialise the old status of the modem signals */
1093 uap->old_status = readw(uap->port.membase + UART01x_FR) &
1094 UART01x_FR_MODEM_ANY;
1095
1096 if (readl(base + UART011_MIS) & 0x2)
1097 printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n");
1098
1099 /* Start Tx/Rx */
1100 tty->hw_stopped = 0;
1101}
1102
1103static void pl011_stop_tx(struct uart_port *port)
1104{
1105 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1106
1107 uap->im &= ~UART011_TXIM;
1108 writew(uap->im, uap->port.membase + UART011_IMSC);
1109 pl011_dma_tx_stop(uap);
1110}
1111
1112static void pl011_start_tx(struct uart_port *port)
1113{
1114 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1115
1116 if (!pl011_dma_tx_start(uap)) {
1117 uap->im |= UART011_TXIM;
1118 writew(uap->im, uap->port.membase + UART011_IMSC);
1119 }
1120}
1121
1122static void pl011_stop_rx(struct uart_port *port)
1123{
1124 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1125
1126 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1127 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1128 writew(uap->im, uap->port.membase + UART011_IMSC);
1129
1130 pl011_dma_rx_stop(uap);
1131}
1132
1133static void pl011_enable_ms(struct uart_port *port)
1134{
1135 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1136
1137 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1138 writew(uap->im, uap->port.membase + UART011_IMSC);
1139}
1140
1141static void pl011_rx_chars(struct uart_amba_port *uap)
1142{
1143 struct tty_struct *tty = uap->port.state->port.tty;
1144
1145 pl011_fifo_to_tty(uap);
1146
1147 spin_unlock(&uap->port.lock);
1148 tty_flip_buffer_push(tty);
1149 /*
1150 * If we were temporarily out of DMA mode for a while,
1151 * attempt to switch back to DMA mode again.
1152 */
1153 if (pl011_dma_rx_available(uap)) {
1154 if (pl011_dma_rx_trigger_dma(uap)) {
1155 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1156 "fall back to interrupt mode again\n");
1157 uap->im |= UART011_RXIM;
1158 } else
1159 uap->im &= ~UART011_RXIM;
1160 writew(uap->im, uap->port.membase + UART011_IMSC);
1161 }
1162 spin_lock(&uap->port.lock);
1163}
1164
1165static void pl011_tx_chars(struct uart_amba_port *uap)
1166{
1167 struct circ_buf *xmit = &uap->port.state->xmit;
1168 int count;
1169
1170 if (uap->port.x_char) {
1171 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1172 uap->port.icount.tx++;
1173 uap->port.x_char = 0;
1174 return;
1175 }
1176 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1177 pl011_stop_tx(&uap->port);
1178 return;
1179 }
1180
1181 /* If we are using DMA mode, try to send some characters. */
1182 if (pl011_dma_tx_irq(uap))
1183 return;
1184
1185 count = uap->fifosize >> 1;
1186 do {
1187 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1188 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1189 uap->port.icount.tx++;
1190 if (uart_circ_empty(xmit))
1191 break;
1192 } while (--count > 0);
1193
1194 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1195 uart_write_wakeup(&uap->port);
1196
1197 if (uart_circ_empty(xmit))
1198 pl011_stop_tx(&uap->port);
1199}
1200
1201static void pl011_modem_status(struct uart_amba_port *uap)
1202{
1203 unsigned int status, delta;
1204
1205 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1206
1207 delta = status ^ uap->old_status;
1208 uap->old_status = status;
1209
1210 if (!delta)
1211 return;
1212
1213 if (delta & UART01x_FR_DCD)
1214 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1215
1216 if (delta & UART01x_FR_DSR)
1217 uap->port.icount.dsr++;
1218
1219 if (delta & UART01x_FR_CTS)
1220 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1221
1222 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1223}
1224
1225static irqreturn_t pl011_int(int irq, void *dev_id)
1226{
1227 struct uart_amba_port *uap = dev_id;
1228 unsigned long flags;
1229 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1230 int handled = 0;
1231
1232 spin_lock_irqsave(&uap->port.lock, flags);
1233
1234 status = readw(uap->port.membase + UART011_MIS);
1235 if (status) {
1236 do {
1237 writew(status & ~(UART011_TXIS|UART011_RTIS|
1238 UART011_RXIS),
1239 uap->port.membase + UART011_ICR);
1240
1241 if (status & (UART011_RTIS|UART011_RXIS)) {
1242 if (pl011_dma_rx_running(uap))
1243 pl011_dma_rx_irq(uap);
1244 else
1245 pl011_rx_chars(uap);
1246 }
1247 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1248 UART011_CTSMIS|UART011_RIMIS))
1249 pl011_modem_status(uap);
1250 if (status & UART011_TXIS)
1251 pl011_tx_chars(uap);
1252
1253 if (pass_counter-- == 0) {
1254 if (uap->interrupt_may_hang)
1255 tasklet_schedule(&pl011_lockup_tlet);
1256 break;
1257 }
1258
1259 status = readw(uap->port.membase + UART011_MIS);
1260 } while (status != 0);
1261 handled = 1;
1262 }
1263
1264 spin_unlock_irqrestore(&uap->port.lock, flags);
1265
1266 return IRQ_RETVAL(handled);
1267}
1268
1269static unsigned int pl01x_tx_empty(struct uart_port *port)
1270{
1271 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1272 unsigned int status = readw(uap->port.membase + UART01x_FR);
1273 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1274}
1275
1276static unsigned int pl01x_get_mctrl(struct uart_port *port)
1277{
1278 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1279 unsigned int result = 0;
1280 unsigned int status = readw(uap->port.membase + UART01x_FR);
1281
1282#define TIOCMBIT(uartbit, tiocmbit) \
1283 if (status & uartbit) \
1284 result |= tiocmbit
1285
1286 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1287 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1288 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1289 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1290#undef TIOCMBIT
1291 return result;
1292}
1293
1294static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1295{
1296 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1297 unsigned int cr;
1298
1299 cr = readw(uap->port.membase + UART011_CR);
1300
1301#define TIOCMBIT(tiocmbit, uartbit) \
1302 if (mctrl & tiocmbit) \
1303 cr |= uartbit; \
1304 else \
1305 cr &= ~uartbit
1306
1307 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1308 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1309 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1310 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1311 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1312
1313 if (uap->autorts) {
1314 /* We need to disable auto-RTS if we want to turn RTS off */
1315 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1316 }
1317#undef TIOCMBIT
1318
1319 writew(cr, uap->port.membase + UART011_CR);
1320}
1321
1322static void pl011_break_ctl(struct uart_port *port, int break_state)
1323{
1324 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1325 unsigned long flags;
1326 unsigned int lcr_h;
1327
1328 spin_lock_irqsave(&uap->port.lock, flags);
1329 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1330 if (break_state == -1)
1331 lcr_h |= UART01x_LCRH_BRK;
1332 else
1333 lcr_h &= ~UART01x_LCRH_BRK;
1334 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1335 spin_unlock_irqrestore(&uap->port.lock, flags);
1336}
1337
1338#ifdef CONFIG_CONSOLE_POLL
1339static int pl010_get_poll_char(struct uart_port *port)
1340{
1341 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1342 unsigned int status;
1343
1344 status = readw(uap->port.membase + UART01x_FR);
1345 if (status & UART01x_FR_RXFE)
1346 return NO_POLL_CHAR;
1347
1348 return readw(uap->port.membase + UART01x_DR);
1349}
1350
1351static void pl010_put_poll_char(struct uart_port *port,
1352 unsigned char ch)
1353{
1354 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1355
1356 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1357 barrier();
1358
1359 writew(ch, uap->port.membase + UART01x_DR);
1360}
1361
1362#endif /* CONFIG_CONSOLE_POLL */
1363
1364static int pl011_startup(struct uart_port *port)
1365{
1366 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1367 unsigned int cr;
1368 int retval;
1369
1370 /*
1371 * Try to enable the clock producer.
1372 */
1373 retval = clk_enable(uap->clk);
1374 if (retval)
1375 goto out;
1376
1377 uap->port.uartclk = clk_get_rate(uap->clk);
1378
1379 /*
1380 * Allocate the IRQ
1381 */
1382 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1383 if (retval)
1384 goto clk_dis;
1385
1386 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1387
1388 /*
1389 * Provoke TX FIFO interrupt into asserting.
1390 */
1391 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1392 writew(cr, uap->port.membase + UART011_CR);
1393 writew(0, uap->port.membase + UART011_FBRD);
1394 writew(1, uap->port.membase + UART011_IBRD);
1395 writew(0, uap->port.membase + uap->lcrh_rx);
1396 if (uap->lcrh_tx != uap->lcrh_rx) {
1397 int i;
1398 /*
1399 * Wait 10 PCLKs before writing LCRH_TX register,
1400 * to get this delay write read only register 10 times
1401 */
1402 for (i = 0; i < 10; ++i)
1403 writew(0xff, uap->port.membase + UART011_MIS);
1404 writew(0, uap->port.membase + uap->lcrh_tx);
1405 }
1406 writew(0, uap->port.membase + UART01x_DR);
1407 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1408 barrier();
1409
1410 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1411 writew(cr, uap->port.membase + UART011_CR);
1412
1413 /* Clear pending error interrupts */
1414 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
1415 uap->port.membase + UART011_ICR);
1416
1417 /*
1418 * initialise the old status of the modem signals
1419 */
1420 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1421
1422 /* Startup DMA */
1423 pl011_dma_startup(uap);
1424
1425 /*
1426 * Finally, enable interrupts, only timeouts when using DMA
1427 * if initial RX DMA job failed, start in interrupt mode
1428 * as well.
1429 */
1430 spin_lock_irq(&uap->port.lock);
1431 uap->im = UART011_RTIM;
1432 if (!pl011_dma_rx_running(uap))
1433 uap->im |= UART011_RXIM;
1434 writew(uap->im, uap->port.membase + UART011_IMSC);
1435 spin_unlock_irq(&uap->port.lock);
1436
1437 if (uap->port.dev->platform_data) {
1438 struct amba_pl011_data *plat;
1439
1440 plat = uap->port.dev->platform_data;
1441 if (plat->init)
1442 plat->init();
1443 }
1444
1445 return 0;
1446
1447 clk_dis:
1448 clk_disable(uap->clk);
1449 out:
1450 return retval;
1451}
1452
1453static void pl011_shutdown_channel(struct uart_amba_port *uap,
1454 unsigned int lcrh)
1455{
1456 unsigned long val;
1457
1458 val = readw(uap->port.membase + lcrh);
1459 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1460 writew(val, uap->port.membase + lcrh);
1461}
1462
1463static void pl011_shutdown(struct uart_port *port)
1464{
1465 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1466
1467 /*
1468 * disable all interrupts
1469 */
1470 spin_lock_irq(&uap->port.lock);
1471 uap->im = 0;
1472 writew(uap->im, uap->port.membase + UART011_IMSC);
1473 writew(0xffff, uap->port.membase + UART011_ICR);
1474 spin_unlock_irq(&uap->port.lock);
1475
1476 pl011_dma_shutdown(uap);
1477
1478 /*
1479 * Free the interrupt
1480 */
1481 free_irq(uap->port.irq, uap);
1482
1483 /*
1484 * disable the port
1485 */
1486 uap->autorts = false;
1487 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
1488
1489 /*
1490 * disable break condition and fifos
1491 */
1492 pl011_shutdown_channel(uap, uap->lcrh_rx);
1493 if (uap->lcrh_rx != uap->lcrh_tx)
1494 pl011_shutdown_channel(uap, uap->lcrh_tx);
1495
1496 /*
1497 * Shut down the clock producer
1498 */
1499 clk_disable(uap->clk);
1500
1501 if (uap->port.dev->platform_data) {
1502 struct amba_pl011_data *plat;
1503
1504 plat = uap->port.dev->platform_data;
1505 if (plat->exit)
1506 plat->exit();
1507 }
1508
1509}
1510
1511static void
1512pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1513 struct ktermios *old)
1514{
1515 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1516 unsigned int lcr_h, old_cr;
1517 unsigned long flags;
1518 unsigned int baud, quot, clkdiv;
1519
1520 if (uap->vendor->oversampling)
1521 clkdiv = 8;
1522 else
1523 clkdiv = 16;
1524
1525 /*
1526 * Ask the core to calculate the divisor for us.
1527 */
1528 baud = uart_get_baud_rate(port, termios, old, 0,
1529 port->uartclk / clkdiv);
1530
1531 if (baud > port->uartclk/16)
1532 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1533 else
1534 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1535
1536 switch (termios->c_cflag & CSIZE) {
1537 case CS5:
1538 lcr_h = UART01x_LCRH_WLEN_5;
1539 break;
1540 case CS6:
1541 lcr_h = UART01x_LCRH_WLEN_6;
1542 break;
1543 case CS7:
1544 lcr_h = UART01x_LCRH_WLEN_7;
1545 break;
1546 default: // CS8
1547 lcr_h = UART01x_LCRH_WLEN_8;
1548 break;
1549 }
1550 if (termios->c_cflag & CSTOPB)
1551 lcr_h |= UART01x_LCRH_STP2;
1552 if (termios->c_cflag & PARENB) {
1553 lcr_h |= UART01x_LCRH_PEN;
1554 if (!(termios->c_cflag & PARODD))
1555 lcr_h |= UART01x_LCRH_EPS;
1556 }
1557 if (uap->fifosize > 1)
1558 lcr_h |= UART01x_LCRH_FEN;
1559
1560 spin_lock_irqsave(&port->lock, flags);
1561
1562 /*
1563 * Update the per-port timeout.
1564 */
1565 uart_update_timeout(port, termios->c_cflag, baud);
1566
1567 port->read_status_mask = UART011_DR_OE | 255;
1568 if (termios->c_iflag & INPCK)
1569 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1570 if (termios->c_iflag & (BRKINT | PARMRK))
1571 port->read_status_mask |= UART011_DR_BE;
1572
1573 /*
1574 * Characters to ignore
1575 */
1576 port->ignore_status_mask = 0;
1577 if (termios->c_iflag & IGNPAR)
1578 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1579 if (termios->c_iflag & IGNBRK) {
1580 port->ignore_status_mask |= UART011_DR_BE;
1581 /*
1582 * If we're ignoring parity and break indicators,
1583 * ignore overruns too (for real raw support).
1584 */
1585 if (termios->c_iflag & IGNPAR)
1586 port->ignore_status_mask |= UART011_DR_OE;
1587 }
1588
1589 /*
1590 * Ignore all characters if CREAD is not set.
1591 */
1592 if ((termios->c_cflag & CREAD) == 0)
1593 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1594
1595 if (UART_ENABLE_MS(port, termios->c_cflag))
1596 pl011_enable_ms(port);
1597
1598 /* first, disable everything */
1599 old_cr = readw(port->membase + UART011_CR);
1600 writew(0, port->membase + UART011_CR);
1601
1602 if (termios->c_cflag & CRTSCTS) {
1603 if (old_cr & UART011_CR_RTS)
1604 old_cr |= UART011_CR_RTSEN;
1605
1606 old_cr |= UART011_CR_CTSEN;
1607 uap->autorts = true;
1608 } else {
1609 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1610 uap->autorts = false;
1611 }
1612
1613 if (uap->vendor->oversampling) {
1614 if (baud > port->uartclk / 16)
1615 old_cr |= ST_UART011_CR_OVSFACT;
1616 else
1617 old_cr &= ~ST_UART011_CR_OVSFACT;
1618 }
1619
1620 /* Set baud rate */
1621 writew(quot & 0x3f, port->membase + UART011_FBRD);
1622 writew(quot >> 6, port->membase + UART011_IBRD);
1623
1624 /*
1625 * ----------v----------v----------v----------v-----
1626 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
1627 * ----------^----------^----------^----------^-----
1628 */
1629 writew(lcr_h, port->membase + uap->lcrh_rx);
1630 if (uap->lcrh_rx != uap->lcrh_tx) {
1631 int i;
1632 /*
1633 * Wait 10 PCLKs before writing LCRH_TX register,
1634 * to get this delay write read only register 10 times
1635 */
1636 for (i = 0; i < 10; ++i)
1637 writew(0xff, uap->port.membase + UART011_MIS);
1638 writew(lcr_h, port->membase + uap->lcrh_tx);
1639 }
1640 writew(old_cr, port->membase + UART011_CR);
1641
1642 spin_unlock_irqrestore(&port->lock, flags);
1643}
1644
1645static const char *pl011_type(struct uart_port *port)
1646{
1647 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1648 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1649}
1650
1651/*
1652 * Release the memory region(s) being used by 'port'
1653 */
1654static void pl010_release_port(struct uart_port *port)
1655{
1656 release_mem_region(port->mapbase, SZ_4K);
1657}
1658
1659/*
1660 * Request the memory region(s) being used by 'port'
1661 */
1662static int pl010_request_port(struct uart_port *port)
1663{
1664 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1665 != NULL ? 0 : -EBUSY;
1666}
1667
1668/*
1669 * Configure/autoconfigure the port.
1670 */
1671static void pl010_config_port(struct uart_port *port, int flags)
1672{
1673 if (flags & UART_CONFIG_TYPE) {
1674 port->type = PORT_AMBA;
1675 pl010_request_port(port);
1676 }
1677}
1678
1679/*
1680 * verify the new serial_struct (for TIOCSSERIAL).
1681 */
1682static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
1683{
1684 int ret = 0;
1685 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1686 ret = -EINVAL;
1687 if (ser->irq < 0 || ser->irq >= nr_irqs)
1688 ret = -EINVAL;
1689 if (ser->baud_base < 9600)
1690 ret = -EINVAL;
1691 return ret;
1692}
1693
1694static struct uart_ops amba_pl011_pops = {
1695 .tx_empty = pl01x_tx_empty,
1696 .set_mctrl = pl011_set_mctrl,
1697 .get_mctrl = pl01x_get_mctrl,
1698 .stop_tx = pl011_stop_tx,
1699 .start_tx = pl011_start_tx,
1700 .stop_rx = pl011_stop_rx,
1701 .enable_ms = pl011_enable_ms,
1702 .break_ctl = pl011_break_ctl,
1703 .startup = pl011_startup,
1704 .shutdown = pl011_shutdown,
1705 .flush_buffer = pl011_dma_flush_buffer,
1706 .set_termios = pl011_set_termios,
1707 .type = pl011_type,
1708 .release_port = pl010_release_port,
1709 .request_port = pl010_request_port,
1710 .config_port = pl010_config_port,
1711 .verify_port = pl010_verify_port,
1712#ifdef CONFIG_CONSOLE_POLL
1713 .poll_get_char = pl010_get_poll_char,
1714 .poll_put_char = pl010_put_poll_char,
1715#endif
1716};
1717
1718static struct uart_amba_port *amba_ports[UART_NR];
1719
1720#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1721
1722static void pl011_console_putchar(struct uart_port *port, int ch)
1723{
1724 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1725
1726 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1727 barrier();
1728 writew(ch, uap->port.membase + UART01x_DR);
1729}
1730
1731static void
1732pl011_console_write(struct console *co, const char *s, unsigned int count)
1733{
1734 struct uart_amba_port *uap = amba_ports[co->index];
1735 unsigned int status, old_cr, new_cr;
1736
1737 clk_enable(uap->clk);
1738
1739 /*
1740 * First save the CR then disable the interrupts
1741 */
1742 old_cr = readw(uap->port.membase + UART011_CR);
1743 new_cr = old_cr & ~UART011_CR_CTSEN;
1744 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1745 writew(new_cr, uap->port.membase + UART011_CR);
1746
1747 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1748
1749 /*
1750 * Finally, wait for transmitter to become empty
1751 * and restore the TCR
1752 */
1753 do {
1754 status = readw(uap->port.membase + UART01x_FR);
1755 } while (status & UART01x_FR_BUSY);
1756 writew(old_cr, uap->port.membase + UART011_CR);
1757
1758 clk_disable(uap->clk);
1759}
1760
1761static void __init
1762pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1763 int *parity, int *bits)
1764{
1765 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1766 unsigned int lcr_h, ibrd, fbrd;
1767
1768 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1769
1770 *parity = 'n';
1771 if (lcr_h & UART01x_LCRH_PEN) {
1772 if (lcr_h & UART01x_LCRH_EPS)
1773 *parity = 'e';
1774 else
1775 *parity = 'o';
1776 }
1777
1778 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1779 *bits = 7;
1780 else
1781 *bits = 8;
1782
1783 ibrd = readw(uap->port.membase + UART011_IBRD);
1784 fbrd = readw(uap->port.membase + UART011_FBRD);
1785
1786 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1787
1788 if (uap->vendor->oversampling) {
1789 if (readw(uap->port.membase + UART011_CR)
1790 & ST_UART011_CR_OVSFACT)
1791 *baud *= 2;
1792 }
1793 }
1794}
1795
1796static int __init pl011_console_setup(struct console *co, char *options)
1797{
1798 struct uart_amba_port *uap;
1799 int baud = 38400;
1800 int bits = 8;
1801 int parity = 'n';
1802 int flow = 'n';
1803
1804 /*
1805 * Check whether an invalid uart number has been specified, and
1806 * if so, search for the first available port that does have
1807 * console support.
1808 */
1809 if (co->index >= UART_NR)
1810 co->index = 0;
1811 uap = amba_ports[co->index];
1812 if (!uap)
1813 return -ENODEV;
1814
1815 if (uap->port.dev->platform_data) {
1816 struct amba_pl011_data *plat;
1817
1818 plat = uap->port.dev->platform_data;
1819 if (plat->init)
1820 plat->init();
1821 }
1822
1823 uap->port.uartclk = clk_get_rate(uap->clk);
1824
1825 if (options)
1826 uart_parse_options(options, &baud, &parity, &bits, &flow);
1827 else
1828 pl011_console_get_options(uap, &baud, &parity, &bits);
1829
1830 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1831}
1832
1833static struct uart_driver amba_reg;
1834static struct console amba_console = {
1835 .name = "ttyAMA",
1836 .write = pl011_console_write,
1837 .device = uart_console_device,
1838 .setup = pl011_console_setup,
1839 .flags = CON_PRINTBUFFER,
1840 .index = -1,
1841 .data = &amba_reg,
1842};
1843
1844#define AMBA_CONSOLE (&amba_console)
1845#else
1846#define AMBA_CONSOLE NULL
1847#endif
1848
1849static struct uart_driver amba_reg = {
1850 .owner = THIS_MODULE,
1851 .driver_name = "ttyAMA",
1852 .dev_name = "ttyAMA",
1853 .major = SERIAL_AMBA_MAJOR,
1854 .minor = SERIAL_AMBA_MINOR,
1855 .nr = UART_NR,
1856 .cons = AMBA_CONSOLE,
1857};
1858
1859static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1860{
1861 struct uart_amba_port *uap;
1862 struct vendor_data *vendor = id->data;
1863 void __iomem *base;
1864 int i, ret;
1865
1866 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1867 if (amba_ports[i] == NULL)
1868 break;
1869
1870 if (i == ARRAY_SIZE(amba_ports)) {
1871 ret = -EBUSY;
1872 goto out;
1873 }
1874
1875 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1876 if (uap == NULL) {
1877 ret = -ENOMEM;
1878 goto out;
1879 }
1880
1881 base = ioremap(dev->res.start, resource_size(&dev->res));
1882 if (!base) {
1883 ret = -ENOMEM;
1884 goto free;
1885 }
1886
1887 uap->clk = clk_get(&dev->dev, NULL);
1888 if (IS_ERR(uap->clk)) {
1889 ret = PTR_ERR(uap->clk);
1890 goto unmap;
1891 }
1892
1893 uap->vendor = vendor;
1894 uap->lcrh_rx = vendor->lcrh_rx;
1895 uap->lcrh_tx = vendor->lcrh_tx;
1896 uap->fifosize = vendor->fifosize;
1897 uap->interrupt_may_hang = vendor->interrupt_may_hang;
1898 uap->port.dev = &dev->dev;
1899 uap->port.mapbase = dev->res.start;
1900 uap->port.membase = base;
1901 uap->port.iotype = UPIO_MEM;
1902 uap->port.irq = dev->irq[0];
1903 uap->port.fifosize = uap->fifosize;
1904 uap->port.ops = &amba_pl011_pops;
1905 uap->port.flags = UPF_BOOT_AUTOCONF;
1906 uap->port.line = i;
1907 pl011_dma_probe(uap);
1908
1909 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
1910
1911 amba_ports[i] = uap;
1912
1913 amba_set_drvdata(dev, uap);
1914 ret = uart_add_one_port(&amba_reg, &uap->port);
1915 if (ret) {
1916 amba_set_drvdata(dev, NULL);
1917 amba_ports[i] = NULL;
1918 pl011_dma_remove(uap);
1919 clk_put(uap->clk);
1920 unmap:
1921 iounmap(base);
1922 free:
1923 kfree(uap);
1924 }
1925 out:
1926 return ret;
1927}
1928
1929static int pl011_remove(struct amba_device *dev)
1930{
1931 struct uart_amba_port *uap = amba_get_drvdata(dev);
1932 int i;
1933
1934 amba_set_drvdata(dev, NULL);
1935
1936 uart_remove_one_port(&amba_reg, &uap->port);
1937
1938 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1939 if (amba_ports[i] == uap)
1940 amba_ports[i] = NULL;
1941
1942 pl011_dma_remove(uap);
1943 iounmap(uap->port.membase);
1944 clk_put(uap->clk);
1945 kfree(uap);
1946 return 0;
1947}
1948
1949#ifdef CONFIG_PM
1950static int pl011_suspend(struct amba_device *dev, pm_message_t state)
1951{
1952 struct uart_amba_port *uap = amba_get_drvdata(dev);
1953
1954 if (!uap)
1955 return -EINVAL;
1956
1957 return uart_suspend_port(&amba_reg, &uap->port);
1958}
1959
1960static int pl011_resume(struct amba_device *dev)
1961{
1962 struct uart_amba_port *uap = amba_get_drvdata(dev);
1963
1964 if (!uap)
1965 return -EINVAL;
1966
1967 return uart_resume_port(&amba_reg, &uap->port);
1968}
1969#endif
1970
1971static struct amba_id pl011_ids[] = {
1972 {
1973 .id = 0x00041011,
1974 .mask = 0x000fffff,
1975 .data = &vendor_arm,
1976 },
1977 {
1978 .id = 0x00380802,
1979 .mask = 0x00ffffff,
1980 .data = &vendor_st,
1981 },
1982 { 0, 0 },
1983};
1984
1985static struct amba_driver pl011_driver = {
1986 .drv = {
1987 .name = "uart-pl011",
1988 },
1989 .id_table = pl011_ids,
1990 .probe = pl011_probe,
1991 .remove = pl011_remove,
1992#ifdef CONFIG_PM
1993 .suspend = pl011_suspend,
1994 .resume = pl011_resume,
1995#endif
1996};
1997
1998static int __init pl011_init(void)
1999{
2000 int ret;
2001 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2002
2003 ret = uart_register_driver(&amba_reg);
2004 if (ret == 0) {
2005 ret = amba_driver_register(&pl011_driver);
2006 if (ret)
2007 uart_unregister_driver(&amba_reg);
2008 }
2009 return ret;
2010}
2011
2012static void __exit pl011_exit(void)
2013{
2014 amba_driver_unregister(&pl011_driver);
2015 uart_unregister_driver(&amba_reg);
2016}
2017
2018/*
2019 * While this can be a module, if builtin it's most likely the console
2020 * So let's leave module_exit but move module_init to an earlier place
2021 */
2022arch_initcall(pl011_init);
2023module_exit(pl011_exit);
2024
2025MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2026MODULE_DESCRIPTION("ARM AMBA serial port driver");
2027MODULE_LICENSE("GPL");
1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33#define SUPPORT_SYSRQ
34#endif
35
36#include <linux/module.h>
37#include <linux/ioport.h>
38#include <linux/init.h>
39#include <linux/console.h>
40#include <linux/sysrq.h>
41#include <linux/device.h>
42#include <linux/tty.h>
43#include <linux/tty_flip.h>
44#include <linux/serial_core.h>
45#include <linux/serial.h>
46#include <linux/amba/bus.h>
47#include <linux/amba/serial.h>
48#include <linux/clk.h>
49#include <linux/slab.h>
50#include <linux/dmaengine.h>
51#include <linux/dma-mapping.h>
52#include <linux/scatterlist.h>
53#include <linux/delay.h>
54#include <linux/types.h>
55#include <linux/pinctrl/consumer.h>
56
57#include <asm/io.h>
58#include <asm/sizes.h>
59
60#define UART_NR 14
61
62#define SERIAL_AMBA_MAJOR 204
63#define SERIAL_AMBA_MINOR 64
64#define SERIAL_AMBA_NR UART_NR
65
66#define AMBA_ISR_PASS_LIMIT 256
67
68#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
69#define UART_DUMMY_DR_RX (1 << 16)
70
71/* There is by now at least one vendor with differing details, so handle it */
72struct vendor_data {
73 unsigned int ifls;
74 unsigned int fifosize;
75 unsigned int lcrh_tx;
76 unsigned int lcrh_rx;
77 bool oversampling;
78 bool interrupt_may_hang; /* vendor-specific */
79 bool dma_threshold;
80 bool cts_event_workaround;
81};
82
83static struct vendor_data vendor_arm = {
84 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
85 .fifosize = 16,
86 .lcrh_tx = UART011_LCRH,
87 .lcrh_rx = UART011_LCRH,
88 .oversampling = false,
89 .dma_threshold = false,
90 .cts_event_workaround = false,
91};
92
93static struct vendor_data vendor_st = {
94 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
95 .fifosize = 64,
96 .lcrh_tx = ST_UART011_LCRH_TX,
97 .lcrh_rx = ST_UART011_LCRH_RX,
98 .oversampling = true,
99 .interrupt_may_hang = true,
100 .dma_threshold = true,
101 .cts_event_workaround = true,
102};
103
104static struct uart_amba_port *amba_ports[UART_NR];
105
106/* Deals with DMA transactions */
107
108struct pl011_sgbuf {
109 struct scatterlist sg;
110 char *buf;
111};
112
113struct pl011_dmarx_data {
114 struct dma_chan *chan;
115 struct completion complete;
116 bool use_buf_b;
117 struct pl011_sgbuf sgbuf_a;
118 struct pl011_sgbuf sgbuf_b;
119 dma_cookie_t cookie;
120 bool running;
121};
122
123struct pl011_dmatx_data {
124 struct dma_chan *chan;
125 struct scatterlist sg;
126 char *buf;
127 bool queued;
128};
129
130/*
131 * We wrap our port structure around the generic uart_port.
132 */
133struct uart_amba_port {
134 struct uart_port port;
135 struct clk *clk;
136 /* Two optional pin states - default & sleep */
137 struct pinctrl *pinctrl;
138 struct pinctrl_state *pins_default;
139 struct pinctrl_state *pins_sleep;
140 const struct vendor_data *vendor;
141 unsigned int dmacr; /* dma control reg */
142 unsigned int im; /* interrupt mask */
143 unsigned int old_status;
144 unsigned int fifosize; /* vendor-specific */
145 unsigned int lcrh_tx; /* vendor-specific */
146 unsigned int lcrh_rx; /* vendor-specific */
147 unsigned int old_cr; /* state during shutdown */
148 bool autorts;
149 char type[12];
150 bool interrupt_may_hang; /* vendor-specific */
151#ifdef CONFIG_DMA_ENGINE
152 /* DMA stuff */
153 bool using_tx_dma;
154 bool using_rx_dma;
155 struct pl011_dmarx_data dmarx;
156 struct pl011_dmatx_data dmatx;
157#endif
158};
159
160/*
161 * Reads up to 256 characters from the FIFO or until it's empty and
162 * inserts them into the TTY layer. Returns the number of characters
163 * read from the FIFO.
164 */
165static int pl011_fifo_to_tty(struct uart_amba_port *uap)
166{
167 u16 status, ch;
168 unsigned int flag, max_count = 256;
169 int fifotaken = 0;
170
171 while (max_count--) {
172 status = readw(uap->port.membase + UART01x_FR);
173 if (status & UART01x_FR_RXFE)
174 break;
175
176 /* Take chars from the FIFO and update status */
177 ch = readw(uap->port.membase + UART01x_DR) |
178 UART_DUMMY_DR_RX;
179 flag = TTY_NORMAL;
180 uap->port.icount.rx++;
181 fifotaken++;
182
183 if (unlikely(ch & UART_DR_ERROR)) {
184 if (ch & UART011_DR_BE) {
185 ch &= ~(UART011_DR_FE | UART011_DR_PE);
186 uap->port.icount.brk++;
187 if (uart_handle_break(&uap->port))
188 continue;
189 } else if (ch & UART011_DR_PE)
190 uap->port.icount.parity++;
191 else if (ch & UART011_DR_FE)
192 uap->port.icount.frame++;
193 if (ch & UART011_DR_OE)
194 uap->port.icount.overrun++;
195
196 ch &= uap->port.read_status_mask;
197
198 if (ch & UART011_DR_BE)
199 flag = TTY_BREAK;
200 else if (ch & UART011_DR_PE)
201 flag = TTY_PARITY;
202 else if (ch & UART011_DR_FE)
203 flag = TTY_FRAME;
204 }
205
206 if (uart_handle_sysrq_char(&uap->port, ch & 255))
207 continue;
208
209 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
210 }
211
212 return fifotaken;
213}
214
215
216/*
217 * All the DMA operation mode stuff goes inside this ifdef.
218 * This assumes that you have a generic DMA device interface,
219 * no custom DMA interfaces are supported.
220 */
221#ifdef CONFIG_DMA_ENGINE
222
223#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
224
225static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
226 enum dma_data_direction dir)
227{
228 sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
229 if (!sg->buf)
230 return -ENOMEM;
231
232 sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
233
234 if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
235 kfree(sg->buf);
236 return -EINVAL;
237 }
238 return 0;
239}
240
241static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
242 enum dma_data_direction dir)
243{
244 if (sg->buf) {
245 dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
246 kfree(sg->buf);
247 }
248}
249
250static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
251{
252 /* DMA is the sole user of the platform data right now */
253 struct amba_pl011_data *plat = uap->port.dev->platform_data;
254 struct dma_slave_config tx_conf = {
255 .dst_addr = uap->port.mapbase + UART01x_DR,
256 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
257 .direction = DMA_MEM_TO_DEV,
258 .dst_maxburst = uap->fifosize >> 1,
259 .device_fc = false,
260 };
261 struct dma_chan *chan;
262 dma_cap_mask_t mask;
263
264 /* We need platform data */
265 if (!plat || !plat->dma_filter) {
266 dev_info(uap->port.dev, "no DMA platform data\n");
267 return;
268 }
269
270 /* Try to acquire a generic DMA engine slave TX channel */
271 dma_cap_zero(mask);
272 dma_cap_set(DMA_SLAVE, mask);
273
274 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
275 if (!chan) {
276 dev_err(uap->port.dev, "no TX DMA channel!\n");
277 return;
278 }
279
280 dmaengine_slave_config(chan, &tx_conf);
281 uap->dmatx.chan = chan;
282
283 dev_info(uap->port.dev, "DMA channel TX %s\n",
284 dma_chan_name(uap->dmatx.chan));
285
286 /* Optionally make use of an RX channel as well */
287 if (plat->dma_rx_param) {
288 struct dma_slave_config rx_conf = {
289 .src_addr = uap->port.mapbase + UART01x_DR,
290 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
291 .direction = DMA_DEV_TO_MEM,
292 .src_maxburst = uap->fifosize >> 1,
293 .device_fc = false,
294 };
295
296 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
297 if (!chan) {
298 dev_err(uap->port.dev, "no RX DMA channel!\n");
299 return;
300 }
301
302 dmaengine_slave_config(chan, &rx_conf);
303 uap->dmarx.chan = chan;
304
305 dev_info(uap->port.dev, "DMA channel RX %s\n",
306 dma_chan_name(uap->dmarx.chan));
307 }
308}
309
310#ifndef MODULE
311/*
312 * Stack up the UARTs and let the above initcall be done at device
313 * initcall time, because the serial driver is called as an arch
314 * initcall, and at this time the DMA subsystem is not yet registered.
315 * At this point the driver will switch over to using DMA where desired.
316 */
317struct dma_uap {
318 struct list_head node;
319 struct uart_amba_port *uap;
320};
321
322static LIST_HEAD(pl011_dma_uarts);
323
324static int __init pl011_dma_initcall(void)
325{
326 struct list_head *node, *tmp;
327
328 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
329 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
330 pl011_dma_probe_initcall(dmau->uap);
331 list_del(node);
332 kfree(dmau);
333 }
334 return 0;
335}
336
337device_initcall(pl011_dma_initcall);
338
339static void pl011_dma_probe(struct uart_amba_port *uap)
340{
341 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
342 if (dmau) {
343 dmau->uap = uap;
344 list_add_tail(&dmau->node, &pl011_dma_uarts);
345 }
346}
347#else
348static void pl011_dma_probe(struct uart_amba_port *uap)
349{
350 pl011_dma_probe_initcall(uap);
351}
352#endif
353
354static void pl011_dma_remove(struct uart_amba_port *uap)
355{
356 /* TODO: remove the initcall if it has not yet executed */
357 if (uap->dmatx.chan)
358 dma_release_channel(uap->dmatx.chan);
359 if (uap->dmarx.chan)
360 dma_release_channel(uap->dmarx.chan);
361}
362
363/* Forward declare this for the refill routine */
364static int pl011_dma_tx_refill(struct uart_amba_port *uap);
365
366/*
367 * The current DMA TX buffer has been sent.
368 * Try to queue up another DMA buffer.
369 */
370static void pl011_dma_tx_callback(void *data)
371{
372 struct uart_amba_port *uap = data;
373 struct pl011_dmatx_data *dmatx = &uap->dmatx;
374 unsigned long flags;
375 u16 dmacr;
376
377 spin_lock_irqsave(&uap->port.lock, flags);
378 if (uap->dmatx.queued)
379 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
380 DMA_TO_DEVICE);
381
382 dmacr = uap->dmacr;
383 uap->dmacr = dmacr & ~UART011_TXDMAE;
384 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
385
386 /*
387 * If TX DMA was disabled, it means that we've stopped the DMA for
388 * some reason (eg, XOFF received, or we want to send an X-char.)
389 *
390 * Note: we need to be careful here of a potential race between DMA
391 * and the rest of the driver - if the driver disables TX DMA while
392 * a TX buffer completing, we must update the tx queued status to
393 * get further refills (hence we check dmacr).
394 */
395 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
396 uart_circ_empty(&uap->port.state->xmit)) {
397 uap->dmatx.queued = false;
398 spin_unlock_irqrestore(&uap->port.lock, flags);
399 return;
400 }
401
402 if (pl011_dma_tx_refill(uap) <= 0) {
403 /*
404 * We didn't queue a DMA buffer for some reason, but we
405 * have data pending to be sent. Re-enable the TX IRQ.
406 */
407 uap->im |= UART011_TXIM;
408 writew(uap->im, uap->port.membase + UART011_IMSC);
409 }
410 spin_unlock_irqrestore(&uap->port.lock, flags);
411}
412
413/*
414 * Try to refill the TX DMA buffer.
415 * Locking: called with port lock held and IRQs disabled.
416 * Returns:
417 * 1 if we queued up a TX DMA buffer.
418 * 0 if we didn't want to handle this by DMA
419 * <0 on error
420 */
421static int pl011_dma_tx_refill(struct uart_amba_port *uap)
422{
423 struct pl011_dmatx_data *dmatx = &uap->dmatx;
424 struct dma_chan *chan = dmatx->chan;
425 struct dma_device *dma_dev = chan->device;
426 struct dma_async_tx_descriptor *desc;
427 struct circ_buf *xmit = &uap->port.state->xmit;
428 unsigned int count;
429
430 /*
431 * Try to avoid the overhead involved in using DMA if the
432 * transaction fits in the first half of the FIFO, by using
433 * the standard interrupt handling. This ensures that we
434 * issue a uart_write_wakeup() at the appropriate time.
435 */
436 count = uart_circ_chars_pending(xmit);
437 if (count < (uap->fifosize >> 1)) {
438 uap->dmatx.queued = false;
439 return 0;
440 }
441
442 /*
443 * Bodge: don't send the last character by DMA, as this
444 * will prevent XON from notifying us to restart DMA.
445 */
446 count -= 1;
447
448 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
449 if (count > PL011_DMA_BUFFER_SIZE)
450 count = PL011_DMA_BUFFER_SIZE;
451
452 if (xmit->tail < xmit->head)
453 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
454 else {
455 size_t first = UART_XMIT_SIZE - xmit->tail;
456 size_t second = xmit->head;
457
458 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
459 if (second)
460 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
461 }
462
463 dmatx->sg.length = count;
464
465 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
466 uap->dmatx.queued = false;
467 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
468 return -EBUSY;
469 }
470
471 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
472 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
473 if (!desc) {
474 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
475 uap->dmatx.queued = false;
476 /*
477 * If DMA cannot be used right now, we complete this
478 * transaction via IRQ and let the TTY layer retry.
479 */
480 dev_dbg(uap->port.dev, "TX DMA busy\n");
481 return -EBUSY;
482 }
483
484 /* Some data to go along to the callback */
485 desc->callback = pl011_dma_tx_callback;
486 desc->callback_param = uap;
487
488 /* All errors should happen at prepare time */
489 dmaengine_submit(desc);
490
491 /* Fire the DMA transaction */
492 dma_dev->device_issue_pending(chan);
493
494 uap->dmacr |= UART011_TXDMAE;
495 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
496 uap->dmatx.queued = true;
497
498 /*
499 * Now we know that DMA will fire, so advance the ring buffer
500 * with the stuff we just dispatched.
501 */
502 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
503 uap->port.icount.tx += count;
504
505 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
506 uart_write_wakeup(&uap->port);
507
508 return 1;
509}
510
511/*
512 * We received a transmit interrupt without a pending X-char but with
513 * pending characters.
514 * Locking: called with port lock held and IRQs disabled.
515 * Returns:
516 * false if we want to use PIO to transmit
517 * true if we queued a DMA buffer
518 */
519static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
520{
521 if (!uap->using_tx_dma)
522 return false;
523
524 /*
525 * If we already have a TX buffer queued, but received a
526 * TX interrupt, it will be because we've just sent an X-char.
527 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
528 */
529 if (uap->dmatx.queued) {
530 uap->dmacr |= UART011_TXDMAE;
531 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
532 uap->im &= ~UART011_TXIM;
533 writew(uap->im, uap->port.membase + UART011_IMSC);
534 return true;
535 }
536
537 /*
538 * We don't have a TX buffer queued, so try to queue one.
539 * If we successfully queued a buffer, mask the TX IRQ.
540 */
541 if (pl011_dma_tx_refill(uap) > 0) {
542 uap->im &= ~UART011_TXIM;
543 writew(uap->im, uap->port.membase + UART011_IMSC);
544 return true;
545 }
546 return false;
547}
548
549/*
550 * Stop the DMA transmit (eg, due to received XOFF).
551 * Locking: called with port lock held and IRQs disabled.
552 */
553static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
554{
555 if (uap->dmatx.queued) {
556 uap->dmacr &= ~UART011_TXDMAE;
557 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
558 }
559}
560
561/*
562 * Try to start a DMA transmit, or in the case of an XON/OFF
563 * character queued for send, try to get that character out ASAP.
564 * Locking: called with port lock held and IRQs disabled.
565 * Returns:
566 * false if we want the TX IRQ to be enabled
567 * true if we have a buffer queued
568 */
569static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
570{
571 u16 dmacr;
572
573 if (!uap->using_tx_dma)
574 return false;
575
576 if (!uap->port.x_char) {
577 /* no X-char, try to push chars out in DMA mode */
578 bool ret = true;
579
580 if (!uap->dmatx.queued) {
581 if (pl011_dma_tx_refill(uap) > 0) {
582 uap->im &= ~UART011_TXIM;
583 ret = true;
584 } else {
585 uap->im |= UART011_TXIM;
586 ret = false;
587 }
588 writew(uap->im, uap->port.membase + UART011_IMSC);
589 } else if (!(uap->dmacr & UART011_TXDMAE)) {
590 uap->dmacr |= UART011_TXDMAE;
591 writew(uap->dmacr,
592 uap->port.membase + UART011_DMACR);
593 }
594 return ret;
595 }
596
597 /*
598 * We have an X-char to send. Disable DMA to prevent it loading
599 * the TX fifo, and then see if we can stuff it into the FIFO.
600 */
601 dmacr = uap->dmacr;
602 uap->dmacr &= ~UART011_TXDMAE;
603 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
604
605 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
606 /*
607 * No space in the FIFO, so enable the transmit interrupt
608 * so we know when there is space. Note that once we've
609 * loaded the character, we should just re-enable DMA.
610 */
611 return false;
612 }
613
614 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
615 uap->port.icount.tx++;
616 uap->port.x_char = 0;
617
618 /* Success - restore the DMA state */
619 uap->dmacr = dmacr;
620 writew(dmacr, uap->port.membase + UART011_DMACR);
621
622 return true;
623}
624
625/*
626 * Flush the transmit buffer.
627 * Locking: called with port lock held and IRQs disabled.
628 */
629static void pl011_dma_flush_buffer(struct uart_port *port)
630{
631 struct uart_amba_port *uap = (struct uart_amba_port *)port;
632
633 if (!uap->using_tx_dma)
634 return;
635
636 /* Avoid deadlock with the DMA engine callback */
637 spin_unlock(&uap->port.lock);
638 dmaengine_terminate_all(uap->dmatx.chan);
639 spin_lock(&uap->port.lock);
640 if (uap->dmatx.queued) {
641 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
642 DMA_TO_DEVICE);
643 uap->dmatx.queued = false;
644 uap->dmacr &= ~UART011_TXDMAE;
645 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
646 }
647}
648
649static void pl011_dma_rx_callback(void *data);
650
651static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
652{
653 struct dma_chan *rxchan = uap->dmarx.chan;
654 struct pl011_dmarx_data *dmarx = &uap->dmarx;
655 struct dma_async_tx_descriptor *desc;
656 struct pl011_sgbuf *sgbuf;
657
658 if (!rxchan)
659 return -EIO;
660
661 /* Start the RX DMA job */
662 sgbuf = uap->dmarx.use_buf_b ?
663 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
664 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
665 DMA_DEV_TO_MEM,
666 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
667 /*
668 * If the DMA engine is busy and cannot prepare a
669 * channel, no big deal, the driver will fall back
670 * to interrupt mode as a result of this error code.
671 */
672 if (!desc) {
673 uap->dmarx.running = false;
674 dmaengine_terminate_all(rxchan);
675 return -EBUSY;
676 }
677
678 /* Some data to go along to the callback */
679 desc->callback = pl011_dma_rx_callback;
680 desc->callback_param = uap;
681 dmarx->cookie = dmaengine_submit(desc);
682 dma_async_issue_pending(rxchan);
683
684 uap->dmacr |= UART011_RXDMAE;
685 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
686 uap->dmarx.running = true;
687
688 uap->im &= ~UART011_RXIM;
689 writew(uap->im, uap->port.membase + UART011_IMSC);
690
691 return 0;
692}
693
694/*
695 * This is called when either the DMA job is complete, or
696 * the FIFO timeout interrupt occurred. This must be called
697 * with the port spinlock uap->port.lock held.
698 */
699static void pl011_dma_rx_chars(struct uart_amba_port *uap,
700 u32 pending, bool use_buf_b,
701 bool readfifo)
702{
703 struct tty_struct *tty = uap->port.state->port.tty;
704 struct pl011_sgbuf *sgbuf = use_buf_b ?
705 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
706 struct device *dev = uap->dmarx.chan->device->dev;
707 int dma_count = 0;
708 u32 fifotaken = 0; /* only used for vdbg() */
709
710 /* Pick everything from the DMA first */
711 if (pending) {
712 /* Sync in buffer */
713 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
714
715 /*
716 * First take all chars in the DMA pipe, then look in the FIFO.
717 * Note that tty_insert_flip_buf() tries to take as many chars
718 * as it can.
719 */
720 dma_count = tty_insert_flip_string(uap->port.state->port.tty,
721 sgbuf->buf, pending);
722
723 /* Return buffer to device */
724 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
725
726 uap->port.icount.rx += dma_count;
727 if (dma_count < pending)
728 dev_warn(uap->port.dev,
729 "couldn't insert all characters (TTY is full?)\n");
730 }
731
732 /*
733 * Only continue with trying to read the FIFO if all DMA chars have
734 * been taken first.
735 */
736 if (dma_count == pending && readfifo) {
737 /* Clear any error flags */
738 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
739 uap->port.membase + UART011_ICR);
740
741 /*
742 * If we read all the DMA'd characters, and we had an
743 * incomplete buffer, that could be due to an rx error, or
744 * maybe we just timed out. Read any pending chars and check
745 * the error status.
746 *
747 * Error conditions will only occur in the FIFO, these will
748 * trigger an immediate interrupt and stop the DMA job, so we
749 * will always find the error in the FIFO, never in the DMA
750 * buffer.
751 */
752 fifotaken = pl011_fifo_to_tty(uap);
753 }
754
755 spin_unlock(&uap->port.lock);
756 dev_vdbg(uap->port.dev,
757 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
758 dma_count, fifotaken);
759 tty_flip_buffer_push(tty);
760 spin_lock(&uap->port.lock);
761}
762
763static void pl011_dma_rx_irq(struct uart_amba_port *uap)
764{
765 struct pl011_dmarx_data *dmarx = &uap->dmarx;
766 struct dma_chan *rxchan = dmarx->chan;
767 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
768 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
769 size_t pending;
770 struct dma_tx_state state;
771 enum dma_status dmastat;
772
773 /*
774 * Pause the transfer so we can trust the current counter,
775 * do this before we pause the PL011 block, else we may
776 * overflow the FIFO.
777 */
778 if (dmaengine_pause(rxchan))
779 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
780 dmastat = rxchan->device->device_tx_status(rxchan,
781 dmarx->cookie, &state);
782 if (dmastat != DMA_PAUSED)
783 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
784
785 /* Disable RX DMA - incoming data will wait in the FIFO */
786 uap->dmacr &= ~UART011_RXDMAE;
787 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
788 uap->dmarx.running = false;
789
790 pending = sgbuf->sg.length - state.residue;
791 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
792 /* Then we terminate the transfer - we now know our residue */
793 dmaengine_terminate_all(rxchan);
794
795 /*
796 * This will take the chars we have so far and insert
797 * into the framework.
798 */
799 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
800
801 /* Switch buffer & re-trigger DMA job */
802 dmarx->use_buf_b = !dmarx->use_buf_b;
803 if (pl011_dma_rx_trigger_dma(uap)) {
804 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
805 "fall back to interrupt mode\n");
806 uap->im |= UART011_RXIM;
807 writew(uap->im, uap->port.membase + UART011_IMSC);
808 }
809}
810
811static void pl011_dma_rx_callback(void *data)
812{
813 struct uart_amba_port *uap = data;
814 struct pl011_dmarx_data *dmarx = &uap->dmarx;
815 struct dma_chan *rxchan = dmarx->chan;
816 bool lastbuf = dmarx->use_buf_b;
817 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
818 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
819 size_t pending;
820 struct dma_tx_state state;
821 int ret;
822
823 /*
824 * This completion interrupt occurs typically when the
825 * RX buffer is totally stuffed but no timeout has yet
826 * occurred. When that happens, we just want the RX
827 * routine to flush out the secondary DMA buffer while
828 * we immediately trigger the next DMA job.
829 */
830 spin_lock_irq(&uap->port.lock);
831 /*
832 * Rx data can be taken by the UART interrupts during
833 * the DMA irq handler. So we check the residue here.
834 */
835 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
836 pending = sgbuf->sg.length - state.residue;
837 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
838 /* Then we terminate the transfer - we now know our residue */
839 dmaengine_terminate_all(rxchan);
840
841 uap->dmarx.running = false;
842 dmarx->use_buf_b = !lastbuf;
843 ret = pl011_dma_rx_trigger_dma(uap);
844
845 pl011_dma_rx_chars(uap, pending, lastbuf, false);
846 spin_unlock_irq(&uap->port.lock);
847 /*
848 * Do this check after we picked the DMA chars so we don't
849 * get some IRQ immediately from RX.
850 */
851 if (ret) {
852 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
853 "fall back to interrupt mode\n");
854 uap->im |= UART011_RXIM;
855 writew(uap->im, uap->port.membase + UART011_IMSC);
856 }
857}
858
859/*
860 * Stop accepting received characters, when we're shutting down or
861 * suspending this port.
862 * Locking: called with port lock held and IRQs disabled.
863 */
864static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
865{
866 /* FIXME. Just disable the DMA enable */
867 uap->dmacr &= ~UART011_RXDMAE;
868 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
869}
870
871static void pl011_dma_startup(struct uart_amba_port *uap)
872{
873 int ret;
874
875 if (!uap->dmatx.chan)
876 return;
877
878 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
879 if (!uap->dmatx.buf) {
880 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
881 uap->port.fifosize = uap->fifosize;
882 return;
883 }
884
885 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
886
887 /* The DMA buffer is now the FIFO the TTY subsystem can use */
888 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
889 uap->using_tx_dma = true;
890
891 if (!uap->dmarx.chan)
892 goto skip_rx;
893
894 /* Allocate and map DMA RX buffers */
895 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
896 DMA_FROM_DEVICE);
897 if (ret) {
898 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
899 "RX buffer A", ret);
900 goto skip_rx;
901 }
902
903 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
904 DMA_FROM_DEVICE);
905 if (ret) {
906 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
907 "RX buffer B", ret);
908 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
909 DMA_FROM_DEVICE);
910 goto skip_rx;
911 }
912
913 uap->using_rx_dma = true;
914
915skip_rx:
916 /* Turn on DMA error (RX/TX will be enabled on demand) */
917 uap->dmacr |= UART011_DMAONERR;
918 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
919
920 /*
921 * ST Micro variants has some specific dma burst threshold
922 * compensation. Set this to 16 bytes, so burst will only
923 * be issued above/below 16 bytes.
924 */
925 if (uap->vendor->dma_threshold)
926 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
927 uap->port.membase + ST_UART011_DMAWM);
928
929 if (uap->using_rx_dma) {
930 if (pl011_dma_rx_trigger_dma(uap))
931 dev_dbg(uap->port.dev, "could not trigger initial "
932 "RX DMA job, fall back to interrupt mode\n");
933 }
934}
935
936static void pl011_dma_shutdown(struct uart_amba_port *uap)
937{
938 if (!(uap->using_tx_dma || uap->using_rx_dma))
939 return;
940
941 /* Disable RX and TX DMA */
942 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
943 barrier();
944
945 spin_lock_irq(&uap->port.lock);
946 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
947 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
948 spin_unlock_irq(&uap->port.lock);
949
950 if (uap->using_tx_dma) {
951 /* In theory, this should already be done by pl011_dma_flush_buffer */
952 dmaengine_terminate_all(uap->dmatx.chan);
953 if (uap->dmatx.queued) {
954 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
955 DMA_TO_DEVICE);
956 uap->dmatx.queued = false;
957 }
958
959 kfree(uap->dmatx.buf);
960 uap->using_tx_dma = false;
961 }
962
963 if (uap->using_rx_dma) {
964 dmaengine_terminate_all(uap->dmarx.chan);
965 /* Clean up the RX DMA */
966 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
967 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
968 uap->using_rx_dma = false;
969 }
970}
971
972static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
973{
974 return uap->using_rx_dma;
975}
976
977static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
978{
979 return uap->using_rx_dma && uap->dmarx.running;
980}
981
982
983#else
984/* Blank functions if the DMA engine is not available */
985static inline void pl011_dma_probe(struct uart_amba_port *uap)
986{
987}
988
989static inline void pl011_dma_remove(struct uart_amba_port *uap)
990{
991}
992
993static inline void pl011_dma_startup(struct uart_amba_port *uap)
994{
995}
996
997static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
998{
999}
1000
1001static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1002{
1003 return false;
1004}
1005
1006static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1007{
1008}
1009
1010static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1011{
1012 return false;
1013}
1014
1015static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1016{
1017}
1018
1019static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1020{
1021}
1022
1023static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1024{
1025 return -EIO;
1026}
1027
1028static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1029{
1030 return false;
1031}
1032
1033static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1034{
1035 return false;
1036}
1037
1038#define pl011_dma_flush_buffer NULL
1039#endif
1040
1041static void pl011_stop_tx(struct uart_port *port)
1042{
1043 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1044
1045 uap->im &= ~UART011_TXIM;
1046 writew(uap->im, uap->port.membase + UART011_IMSC);
1047 pl011_dma_tx_stop(uap);
1048}
1049
1050static void pl011_start_tx(struct uart_port *port)
1051{
1052 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1053
1054 if (!pl011_dma_tx_start(uap)) {
1055 uap->im |= UART011_TXIM;
1056 writew(uap->im, uap->port.membase + UART011_IMSC);
1057 }
1058}
1059
1060static void pl011_stop_rx(struct uart_port *port)
1061{
1062 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1063
1064 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1065 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1066 writew(uap->im, uap->port.membase + UART011_IMSC);
1067
1068 pl011_dma_rx_stop(uap);
1069}
1070
1071static void pl011_enable_ms(struct uart_port *port)
1072{
1073 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1074
1075 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1076 writew(uap->im, uap->port.membase + UART011_IMSC);
1077}
1078
1079static void pl011_rx_chars(struct uart_amba_port *uap)
1080{
1081 struct tty_struct *tty = uap->port.state->port.tty;
1082
1083 pl011_fifo_to_tty(uap);
1084
1085 spin_unlock(&uap->port.lock);
1086 tty_flip_buffer_push(tty);
1087 /*
1088 * If we were temporarily out of DMA mode for a while,
1089 * attempt to switch back to DMA mode again.
1090 */
1091 if (pl011_dma_rx_available(uap)) {
1092 if (pl011_dma_rx_trigger_dma(uap)) {
1093 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1094 "fall back to interrupt mode again\n");
1095 uap->im |= UART011_RXIM;
1096 } else
1097 uap->im &= ~UART011_RXIM;
1098 writew(uap->im, uap->port.membase + UART011_IMSC);
1099 }
1100 spin_lock(&uap->port.lock);
1101}
1102
1103static void pl011_tx_chars(struct uart_amba_port *uap)
1104{
1105 struct circ_buf *xmit = &uap->port.state->xmit;
1106 int count;
1107
1108 if (uap->port.x_char) {
1109 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1110 uap->port.icount.tx++;
1111 uap->port.x_char = 0;
1112 return;
1113 }
1114 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1115 pl011_stop_tx(&uap->port);
1116 return;
1117 }
1118
1119 /* If we are using DMA mode, try to send some characters. */
1120 if (pl011_dma_tx_irq(uap))
1121 return;
1122
1123 count = uap->fifosize >> 1;
1124 do {
1125 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1126 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1127 uap->port.icount.tx++;
1128 if (uart_circ_empty(xmit))
1129 break;
1130 } while (--count > 0);
1131
1132 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1133 uart_write_wakeup(&uap->port);
1134
1135 if (uart_circ_empty(xmit))
1136 pl011_stop_tx(&uap->port);
1137}
1138
1139static void pl011_modem_status(struct uart_amba_port *uap)
1140{
1141 unsigned int status, delta;
1142
1143 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1144
1145 delta = status ^ uap->old_status;
1146 uap->old_status = status;
1147
1148 if (!delta)
1149 return;
1150
1151 if (delta & UART01x_FR_DCD)
1152 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1153
1154 if (delta & UART01x_FR_DSR)
1155 uap->port.icount.dsr++;
1156
1157 if (delta & UART01x_FR_CTS)
1158 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1159
1160 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1161}
1162
1163static irqreturn_t pl011_int(int irq, void *dev_id)
1164{
1165 struct uart_amba_port *uap = dev_id;
1166 unsigned long flags;
1167 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1168 int handled = 0;
1169 unsigned int dummy_read;
1170
1171 spin_lock_irqsave(&uap->port.lock, flags);
1172
1173 status = readw(uap->port.membase + UART011_MIS);
1174 if (status) {
1175 do {
1176 if (uap->vendor->cts_event_workaround) {
1177 /* workaround to make sure that all bits are unlocked.. */
1178 writew(0x00, uap->port.membase + UART011_ICR);
1179
1180 /*
1181 * WA: introduce 26ns(1 uart clk) delay before W1C;
1182 * single apb access will incur 2 pclk(133.12Mhz) delay,
1183 * so add 2 dummy reads
1184 */
1185 dummy_read = readw(uap->port.membase + UART011_ICR);
1186 dummy_read = readw(uap->port.membase + UART011_ICR);
1187 }
1188
1189 writew(status & ~(UART011_TXIS|UART011_RTIS|
1190 UART011_RXIS),
1191 uap->port.membase + UART011_ICR);
1192
1193 if (status & (UART011_RTIS|UART011_RXIS)) {
1194 if (pl011_dma_rx_running(uap))
1195 pl011_dma_rx_irq(uap);
1196 else
1197 pl011_rx_chars(uap);
1198 }
1199 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1200 UART011_CTSMIS|UART011_RIMIS))
1201 pl011_modem_status(uap);
1202 if (status & UART011_TXIS)
1203 pl011_tx_chars(uap);
1204
1205 if (pass_counter-- == 0)
1206 break;
1207
1208 status = readw(uap->port.membase + UART011_MIS);
1209 } while (status != 0);
1210 handled = 1;
1211 }
1212
1213 spin_unlock_irqrestore(&uap->port.lock, flags);
1214
1215 return IRQ_RETVAL(handled);
1216}
1217
1218static unsigned int pl01x_tx_empty(struct uart_port *port)
1219{
1220 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1221 unsigned int status = readw(uap->port.membase + UART01x_FR);
1222 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1223}
1224
1225static unsigned int pl01x_get_mctrl(struct uart_port *port)
1226{
1227 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1228 unsigned int result = 0;
1229 unsigned int status = readw(uap->port.membase + UART01x_FR);
1230
1231#define TIOCMBIT(uartbit, tiocmbit) \
1232 if (status & uartbit) \
1233 result |= tiocmbit
1234
1235 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1236 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1237 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1238 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1239#undef TIOCMBIT
1240 return result;
1241}
1242
1243static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1244{
1245 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1246 unsigned int cr;
1247
1248 cr = readw(uap->port.membase + UART011_CR);
1249
1250#define TIOCMBIT(tiocmbit, uartbit) \
1251 if (mctrl & tiocmbit) \
1252 cr |= uartbit; \
1253 else \
1254 cr &= ~uartbit
1255
1256 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1257 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1258 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1259 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1260 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1261
1262 if (uap->autorts) {
1263 /* We need to disable auto-RTS if we want to turn RTS off */
1264 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1265 }
1266#undef TIOCMBIT
1267
1268 writew(cr, uap->port.membase + UART011_CR);
1269}
1270
1271static void pl011_break_ctl(struct uart_port *port, int break_state)
1272{
1273 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1274 unsigned long flags;
1275 unsigned int lcr_h;
1276
1277 spin_lock_irqsave(&uap->port.lock, flags);
1278 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1279 if (break_state == -1)
1280 lcr_h |= UART01x_LCRH_BRK;
1281 else
1282 lcr_h &= ~UART01x_LCRH_BRK;
1283 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1284 spin_unlock_irqrestore(&uap->port.lock, flags);
1285}
1286
1287#ifdef CONFIG_CONSOLE_POLL
1288static int pl010_get_poll_char(struct uart_port *port)
1289{
1290 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1291 unsigned int status;
1292
1293 status = readw(uap->port.membase + UART01x_FR);
1294 if (status & UART01x_FR_RXFE)
1295 return NO_POLL_CHAR;
1296
1297 return readw(uap->port.membase + UART01x_DR);
1298}
1299
1300static void pl010_put_poll_char(struct uart_port *port,
1301 unsigned char ch)
1302{
1303 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1304
1305 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1306 barrier();
1307
1308 writew(ch, uap->port.membase + UART01x_DR);
1309}
1310
1311#endif /* CONFIG_CONSOLE_POLL */
1312
1313static int pl011_startup(struct uart_port *port)
1314{
1315 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1316 unsigned int cr;
1317 int retval;
1318
1319 /* Optionaly enable pins to be muxed in and configured */
1320 if (!IS_ERR(uap->pins_default)) {
1321 retval = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1322 if (retval)
1323 dev_err(port->dev,
1324 "could not set default pins\n");
1325 }
1326
1327 retval = clk_prepare(uap->clk);
1328 if (retval)
1329 goto out;
1330
1331 /*
1332 * Try to enable the clock producer.
1333 */
1334 retval = clk_enable(uap->clk);
1335 if (retval)
1336 goto clk_unprep;
1337
1338 uap->port.uartclk = clk_get_rate(uap->clk);
1339
1340 /* Clear pending error and receive interrupts */
1341 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
1342 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
1343
1344 /*
1345 * Allocate the IRQ
1346 */
1347 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1348 if (retval)
1349 goto clk_dis;
1350
1351 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1352
1353 /*
1354 * Provoke TX FIFO interrupt into asserting.
1355 */
1356 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1357 writew(cr, uap->port.membase + UART011_CR);
1358 writew(0, uap->port.membase + UART011_FBRD);
1359 writew(1, uap->port.membase + UART011_IBRD);
1360 writew(0, uap->port.membase + uap->lcrh_rx);
1361 if (uap->lcrh_tx != uap->lcrh_rx) {
1362 int i;
1363 /*
1364 * Wait 10 PCLKs before writing LCRH_TX register,
1365 * to get this delay write read only register 10 times
1366 */
1367 for (i = 0; i < 10; ++i)
1368 writew(0xff, uap->port.membase + UART011_MIS);
1369 writew(0, uap->port.membase + uap->lcrh_tx);
1370 }
1371 writew(0, uap->port.membase + UART01x_DR);
1372 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1373 barrier();
1374
1375 /* restore RTS and DTR */
1376 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1377 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1378 writew(cr, uap->port.membase + UART011_CR);
1379
1380 /*
1381 * initialise the old status of the modem signals
1382 */
1383 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1384
1385 /* Startup DMA */
1386 pl011_dma_startup(uap);
1387
1388 /*
1389 * Finally, enable interrupts, only timeouts when using DMA
1390 * if initial RX DMA job failed, start in interrupt mode
1391 * as well.
1392 */
1393 spin_lock_irq(&uap->port.lock);
1394 /* Clear out any spuriously appearing RX interrupts */
1395 writew(UART011_RTIS | UART011_RXIS,
1396 uap->port.membase + UART011_ICR);
1397 uap->im = UART011_RTIM;
1398 if (!pl011_dma_rx_running(uap))
1399 uap->im |= UART011_RXIM;
1400 writew(uap->im, uap->port.membase + UART011_IMSC);
1401 spin_unlock_irq(&uap->port.lock);
1402
1403 if (uap->port.dev->platform_data) {
1404 struct amba_pl011_data *plat;
1405
1406 plat = uap->port.dev->platform_data;
1407 if (plat->init)
1408 plat->init();
1409 }
1410
1411 return 0;
1412
1413 clk_dis:
1414 clk_disable(uap->clk);
1415 clk_unprep:
1416 clk_unprepare(uap->clk);
1417 out:
1418 return retval;
1419}
1420
1421static void pl011_shutdown_channel(struct uart_amba_port *uap,
1422 unsigned int lcrh)
1423{
1424 unsigned long val;
1425
1426 val = readw(uap->port.membase + lcrh);
1427 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1428 writew(val, uap->port.membase + lcrh);
1429}
1430
1431static void pl011_shutdown(struct uart_port *port)
1432{
1433 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1434 unsigned int cr;
1435 int retval;
1436
1437 /*
1438 * disable all interrupts
1439 */
1440 spin_lock_irq(&uap->port.lock);
1441 uap->im = 0;
1442 writew(uap->im, uap->port.membase + UART011_IMSC);
1443 writew(0xffff, uap->port.membase + UART011_ICR);
1444 spin_unlock_irq(&uap->port.lock);
1445
1446 pl011_dma_shutdown(uap);
1447
1448 /*
1449 * Free the interrupt
1450 */
1451 free_irq(uap->port.irq, uap);
1452
1453 /*
1454 * disable the port
1455 * disable the port. It should not disable RTS and DTR.
1456 * Also RTS and DTR state should be preserved to restore
1457 * it during startup().
1458 */
1459 uap->autorts = false;
1460 cr = readw(uap->port.membase + UART011_CR);
1461 uap->old_cr = cr;
1462 cr &= UART011_CR_RTS | UART011_CR_DTR;
1463 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1464 writew(cr, uap->port.membase + UART011_CR);
1465
1466 /*
1467 * disable break condition and fifos
1468 */
1469 pl011_shutdown_channel(uap, uap->lcrh_rx);
1470 if (uap->lcrh_rx != uap->lcrh_tx)
1471 pl011_shutdown_channel(uap, uap->lcrh_tx);
1472
1473 /*
1474 * Shut down the clock producer
1475 */
1476 clk_disable(uap->clk);
1477 clk_unprepare(uap->clk);
1478 /* Optionally let pins go into sleep states */
1479 if (!IS_ERR(uap->pins_sleep)) {
1480 retval = pinctrl_select_state(uap->pinctrl, uap->pins_sleep);
1481 if (retval)
1482 dev_err(port->dev,
1483 "could not set pins to sleep state\n");
1484 }
1485
1486
1487 if (uap->port.dev->platform_data) {
1488 struct amba_pl011_data *plat;
1489
1490 plat = uap->port.dev->platform_data;
1491 if (plat->exit)
1492 plat->exit();
1493 }
1494
1495}
1496
1497static void
1498pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1499 struct ktermios *old)
1500{
1501 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1502 unsigned int lcr_h, old_cr;
1503 unsigned long flags;
1504 unsigned int baud, quot, clkdiv;
1505
1506 if (uap->vendor->oversampling)
1507 clkdiv = 8;
1508 else
1509 clkdiv = 16;
1510
1511 /*
1512 * Ask the core to calculate the divisor for us.
1513 */
1514 baud = uart_get_baud_rate(port, termios, old, 0,
1515 port->uartclk / clkdiv);
1516
1517 if (baud > port->uartclk/16)
1518 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1519 else
1520 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1521
1522 switch (termios->c_cflag & CSIZE) {
1523 case CS5:
1524 lcr_h = UART01x_LCRH_WLEN_5;
1525 break;
1526 case CS6:
1527 lcr_h = UART01x_LCRH_WLEN_6;
1528 break;
1529 case CS7:
1530 lcr_h = UART01x_LCRH_WLEN_7;
1531 break;
1532 default: // CS8
1533 lcr_h = UART01x_LCRH_WLEN_8;
1534 break;
1535 }
1536 if (termios->c_cflag & CSTOPB)
1537 lcr_h |= UART01x_LCRH_STP2;
1538 if (termios->c_cflag & PARENB) {
1539 lcr_h |= UART01x_LCRH_PEN;
1540 if (!(termios->c_cflag & PARODD))
1541 lcr_h |= UART01x_LCRH_EPS;
1542 }
1543 if (uap->fifosize > 1)
1544 lcr_h |= UART01x_LCRH_FEN;
1545
1546 spin_lock_irqsave(&port->lock, flags);
1547
1548 /*
1549 * Update the per-port timeout.
1550 */
1551 uart_update_timeout(port, termios->c_cflag, baud);
1552
1553 port->read_status_mask = UART011_DR_OE | 255;
1554 if (termios->c_iflag & INPCK)
1555 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1556 if (termios->c_iflag & (BRKINT | PARMRK))
1557 port->read_status_mask |= UART011_DR_BE;
1558
1559 /*
1560 * Characters to ignore
1561 */
1562 port->ignore_status_mask = 0;
1563 if (termios->c_iflag & IGNPAR)
1564 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1565 if (termios->c_iflag & IGNBRK) {
1566 port->ignore_status_mask |= UART011_DR_BE;
1567 /*
1568 * If we're ignoring parity and break indicators,
1569 * ignore overruns too (for real raw support).
1570 */
1571 if (termios->c_iflag & IGNPAR)
1572 port->ignore_status_mask |= UART011_DR_OE;
1573 }
1574
1575 /*
1576 * Ignore all characters if CREAD is not set.
1577 */
1578 if ((termios->c_cflag & CREAD) == 0)
1579 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1580
1581 if (UART_ENABLE_MS(port, termios->c_cflag))
1582 pl011_enable_ms(port);
1583
1584 /* first, disable everything */
1585 old_cr = readw(port->membase + UART011_CR);
1586 writew(0, port->membase + UART011_CR);
1587
1588 if (termios->c_cflag & CRTSCTS) {
1589 if (old_cr & UART011_CR_RTS)
1590 old_cr |= UART011_CR_RTSEN;
1591
1592 old_cr |= UART011_CR_CTSEN;
1593 uap->autorts = true;
1594 } else {
1595 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1596 uap->autorts = false;
1597 }
1598
1599 if (uap->vendor->oversampling) {
1600 if (baud > port->uartclk / 16)
1601 old_cr |= ST_UART011_CR_OVSFACT;
1602 else
1603 old_cr &= ~ST_UART011_CR_OVSFACT;
1604 }
1605
1606 /*
1607 * Workaround for the ST Micro oversampling variants to
1608 * increase the bitrate slightly, by lowering the divisor,
1609 * to avoid delayed sampling of start bit at high speeds,
1610 * else we see data corruption.
1611 */
1612 if (uap->vendor->oversampling) {
1613 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1614 quot -= 1;
1615 else if ((baud > 3250000) && (quot > 2))
1616 quot -= 2;
1617 }
1618 /* Set baud rate */
1619 writew(quot & 0x3f, port->membase + UART011_FBRD);
1620 writew(quot >> 6, port->membase + UART011_IBRD);
1621
1622 /*
1623 * ----------v----------v----------v----------v-----
1624 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1625 * UART011_FBRD & UART011_IBRD.
1626 * ----------^----------^----------^----------^-----
1627 */
1628 writew(lcr_h, port->membase + uap->lcrh_rx);
1629 if (uap->lcrh_rx != uap->lcrh_tx) {
1630 int i;
1631 /*
1632 * Wait 10 PCLKs before writing LCRH_TX register,
1633 * to get this delay write read only register 10 times
1634 */
1635 for (i = 0; i < 10; ++i)
1636 writew(0xff, uap->port.membase + UART011_MIS);
1637 writew(lcr_h, port->membase + uap->lcrh_tx);
1638 }
1639 writew(old_cr, port->membase + UART011_CR);
1640
1641 spin_unlock_irqrestore(&port->lock, flags);
1642}
1643
1644static const char *pl011_type(struct uart_port *port)
1645{
1646 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1647 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1648}
1649
1650/*
1651 * Release the memory region(s) being used by 'port'
1652 */
1653static void pl010_release_port(struct uart_port *port)
1654{
1655 release_mem_region(port->mapbase, SZ_4K);
1656}
1657
1658/*
1659 * Request the memory region(s) being used by 'port'
1660 */
1661static int pl010_request_port(struct uart_port *port)
1662{
1663 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1664 != NULL ? 0 : -EBUSY;
1665}
1666
1667/*
1668 * Configure/autoconfigure the port.
1669 */
1670static void pl010_config_port(struct uart_port *port, int flags)
1671{
1672 if (flags & UART_CONFIG_TYPE) {
1673 port->type = PORT_AMBA;
1674 pl010_request_port(port);
1675 }
1676}
1677
1678/*
1679 * verify the new serial_struct (for TIOCSSERIAL).
1680 */
1681static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
1682{
1683 int ret = 0;
1684 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1685 ret = -EINVAL;
1686 if (ser->irq < 0 || ser->irq >= nr_irqs)
1687 ret = -EINVAL;
1688 if (ser->baud_base < 9600)
1689 ret = -EINVAL;
1690 return ret;
1691}
1692
1693static struct uart_ops amba_pl011_pops = {
1694 .tx_empty = pl01x_tx_empty,
1695 .set_mctrl = pl011_set_mctrl,
1696 .get_mctrl = pl01x_get_mctrl,
1697 .stop_tx = pl011_stop_tx,
1698 .start_tx = pl011_start_tx,
1699 .stop_rx = pl011_stop_rx,
1700 .enable_ms = pl011_enable_ms,
1701 .break_ctl = pl011_break_ctl,
1702 .startup = pl011_startup,
1703 .shutdown = pl011_shutdown,
1704 .flush_buffer = pl011_dma_flush_buffer,
1705 .set_termios = pl011_set_termios,
1706 .type = pl011_type,
1707 .release_port = pl010_release_port,
1708 .request_port = pl010_request_port,
1709 .config_port = pl010_config_port,
1710 .verify_port = pl010_verify_port,
1711#ifdef CONFIG_CONSOLE_POLL
1712 .poll_get_char = pl010_get_poll_char,
1713 .poll_put_char = pl010_put_poll_char,
1714#endif
1715};
1716
1717static struct uart_amba_port *amba_ports[UART_NR];
1718
1719#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1720
1721static void pl011_console_putchar(struct uart_port *port, int ch)
1722{
1723 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1724
1725 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1726 barrier();
1727 writew(ch, uap->port.membase + UART01x_DR);
1728}
1729
1730static void
1731pl011_console_write(struct console *co, const char *s, unsigned int count)
1732{
1733 struct uart_amba_port *uap = amba_ports[co->index];
1734 unsigned int status, old_cr, new_cr;
1735 unsigned long flags;
1736 int locked = 1;
1737
1738 clk_enable(uap->clk);
1739
1740 local_irq_save(flags);
1741 if (uap->port.sysrq)
1742 locked = 0;
1743 else if (oops_in_progress)
1744 locked = spin_trylock(&uap->port.lock);
1745 else
1746 spin_lock(&uap->port.lock);
1747
1748 /*
1749 * First save the CR then disable the interrupts
1750 */
1751 old_cr = readw(uap->port.membase + UART011_CR);
1752 new_cr = old_cr & ~UART011_CR_CTSEN;
1753 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1754 writew(new_cr, uap->port.membase + UART011_CR);
1755
1756 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1757
1758 /*
1759 * Finally, wait for transmitter to become empty
1760 * and restore the TCR
1761 */
1762 do {
1763 status = readw(uap->port.membase + UART01x_FR);
1764 } while (status & UART01x_FR_BUSY);
1765 writew(old_cr, uap->port.membase + UART011_CR);
1766
1767 if (locked)
1768 spin_unlock(&uap->port.lock);
1769 local_irq_restore(flags);
1770
1771 clk_disable(uap->clk);
1772}
1773
1774static void __init
1775pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1776 int *parity, int *bits)
1777{
1778 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1779 unsigned int lcr_h, ibrd, fbrd;
1780
1781 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1782
1783 *parity = 'n';
1784 if (lcr_h & UART01x_LCRH_PEN) {
1785 if (lcr_h & UART01x_LCRH_EPS)
1786 *parity = 'e';
1787 else
1788 *parity = 'o';
1789 }
1790
1791 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1792 *bits = 7;
1793 else
1794 *bits = 8;
1795
1796 ibrd = readw(uap->port.membase + UART011_IBRD);
1797 fbrd = readw(uap->port.membase + UART011_FBRD);
1798
1799 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1800
1801 if (uap->vendor->oversampling) {
1802 if (readw(uap->port.membase + UART011_CR)
1803 & ST_UART011_CR_OVSFACT)
1804 *baud *= 2;
1805 }
1806 }
1807}
1808
1809static int __init pl011_console_setup(struct console *co, char *options)
1810{
1811 struct uart_amba_port *uap;
1812 int baud = 38400;
1813 int bits = 8;
1814 int parity = 'n';
1815 int flow = 'n';
1816 int ret;
1817
1818 /*
1819 * Check whether an invalid uart number has been specified, and
1820 * if so, search for the first available port that does have
1821 * console support.
1822 */
1823 if (co->index >= UART_NR)
1824 co->index = 0;
1825 uap = amba_ports[co->index];
1826 if (!uap)
1827 return -ENODEV;
1828
1829 /* Allow pins to be muxed in and configured */
1830 if (!IS_ERR(uap->pins_default)) {
1831 ret = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1832 if (ret)
1833 dev_err(uap->port.dev,
1834 "could not set default pins\n");
1835 }
1836
1837 ret = clk_prepare(uap->clk);
1838 if (ret)
1839 return ret;
1840
1841 if (uap->port.dev->platform_data) {
1842 struct amba_pl011_data *plat;
1843
1844 plat = uap->port.dev->platform_data;
1845 if (plat->init)
1846 plat->init();
1847 }
1848
1849 uap->port.uartclk = clk_get_rate(uap->clk);
1850
1851 if (options)
1852 uart_parse_options(options, &baud, &parity, &bits, &flow);
1853 else
1854 pl011_console_get_options(uap, &baud, &parity, &bits);
1855
1856 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1857}
1858
1859static struct uart_driver amba_reg;
1860static struct console amba_console = {
1861 .name = "ttyAMA",
1862 .write = pl011_console_write,
1863 .device = uart_console_device,
1864 .setup = pl011_console_setup,
1865 .flags = CON_PRINTBUFFER,
1866 .index = -1,
1867 .data = &amba_reg,
1868};
1869
1870#define AMBA_CONSOLE (&amba_console)
1871#else
1872#define AMBA_CONSOLE NULL
1873#endif
1874
1875static struct uart_driver amba_reg = {
1876 .owner = THIS_MODULE,
1877 .driver_name = "ttyAMA",
1878 .dev_name = "ttyAMA",
1879 .major = SERIAL_AMBA_MAJOR,
1880 .minor = SERIAL_AMBA_MINOR,
1881 .nr = UART_NR,
1882 .cons = AMBA_CONSOLE,
1883};
1884
1885static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1886{
1887 struct uart_amba_port *uap;
1888 struct vendor_data *vendor = id->data;
1889 void __iomem *base;
1890 int i, ret;
1891
1892 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1893 if (amba_ports[i] == NULL)
1894 break;
1895
1896 if (i == ARRAY_SIZE(amba_ports)) {
1897 ret = -EBUSY;
1898 goto out;
1899 }
1900
1901 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1902 if (uap == NULL) {
1903 ret = -ENOMEM;
1904 goto out;
1905 }
1906
1907 base = ioremap(dev->res.start, resource_size(&dev->res));
1908 if (!base) {
1909 ret = -ENOMEM;
1910 goto free;
1911 }
1912
1913 uap->pinctrl = devm_pinctrl_get(&dev->dev);
1914 if (IS_ERR(uap->pinctrl)) {
1915 ret = PTR_ERR(uap->pinctrl);
1916 goto unmap;
1917 }
1918 uap->pins_default = pinctrl_lookup_state(uap->pinctrl,
1919 PINCTRL_STATE_DEFAULT);
1920 if (IS_ERR(uap->pins_default))
1921 dev_err(&dev->dev, "could not get default pinstate\n");
1922
1923 uap->pins_sleep = pinctrl_lookup_state(uap->pinctrl,
1924 PINCTRL_STATE_SLEEP);
1925 if (IS_ERR(uap->pins_sleep))
1926 dev_dbg(&dev->dev, "could not get sleep pinstate\n");
1927
1928 uap->clk = clk_get(&dev->dev, NULL);
1929 if (IS_ERR(uap->clk)) {
1930 ret = PTR_ERR(uap->clk);
1931 goto unmap;
1932 }
1933
1934 uap->vendor = vendor;
1935 uap->lcrh_rx = vendor->lcrh_rx;
1936 uap->lcrh_tx = vendor->lcrh_tx;
1937 uap->old_cr = 0;
1938 uap->fifosize = vendor->fifosize;
1939 uap->interrupt_may_hang = vendor->interrupt_may_hang;
1940 uap->port.dev = &dev->dev;
1941 uap->port.mapbase = dev->res.start;
1942 uap->port.membase = base;
1943 uap->port.iotype = UPIO_MEM;
1944 uap->port.irq = dev->irq[0];
1945 uap->port.fifosize = uap->fifosize;
1946 uap->port.ops = &amba_pl011_pops;
1947 uap->port.flags = UPF_BOOT_AUTOCONF;
1948 uap->port.line = i;
1949 pl011_dma_probe(uap);
1950
1951 /* Ensure interrupts from this UART are masked and cleared */
1952 writew(0, uap->port.membase + UART011_IMSC);
1953 writew(0xffff, uap->port.membase + UART011_ICR);
1954
1955 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
1956
1957 amba_ports[i] = uap;
1958
1959 amba_set_drvdata(dev, uap);
1960 ret = uart_add_one_port(&amba_reg, &uap->port);
1961 if (ret) {
1962 amba_set_drvdata(dev, NULL);
1963 amba_ports[i] = NULL;
1964 pl011_dma_remove(uap);
1965 clk_put(uap->clk);
1966 unmap:
1967 iounmap(base);
1968 free:
1969 kfree(uap);
1970 }
1971 out:
1972 return ret;
1973}
1974
1975static int pl011_remove(struct amba_device *dev)
1976{
1977 struct uart_amba_port *uap = amba_get_drvdata(dev);
1978 int i;
1979
1980 amba_set_drvdata(dev, NULL);
1981
1982 uart_remove_one_port(&amba_reg, &uap->port);
1983
1984 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1985 if (amba_ports[i] == uap)
1986 amba_ports[i] = NULL;
1987
1988 pl011_dma_remove(uap);
1989 iounmap(uap->port.membase);
1990 clk_put(uap->clk);
1991 kfree(uap);
1992 return 0;
1993}
1994
1995#ifdef CONFIG_PM
1996static int pl011_suspend(struct amba_device *dev, pm_message_t state)
1997{
1998 struct uart_amba_port *uap = amba_get_drvdata(dev);
1999
2000 if (!uap)
2001 return -EINVAL;
2002
2003 return uart_suspend_port(&amba_reg, &uap->port);
2004}
2005
2006static int pl011_resume(struct amba_device *dev)
2007{
2008 struct uart_amba_port *uap = amba_get_drvdata(dev);
2009
2010 if (!uap)
2011 return -EINVAL;
2012
2013 return uart_resume_port(&amba_reg, &uap->port);
2014}
2015#endif
2016
2017static struct amba_id pl011_ids[] = {
2018 {
2019 .id = 0x00041011,
2020 .mask = 0x000fffff,
2021 .data = &vendor_arm,
2022 },
2023 {
2024 .id = 0x00380802,
2025 .mask = 0x00ffffff,
2026 .data = &vendor_st,
2027 },
2028 { 0, 0 },
2029};
2030
2031MODULE_DEVICE_TABLE(amba, pl011_ids);
2032
2033static struct amba_driver pl011_driver = {
2034 .drv = {
2035 .name = "uart-pl011",
2036 },
2037 .id_table = pl011_ids,
2038 .probe = pl011_probe,
2039 .remove = pl011_remove,
2040#ifdef CONFIG_PM
2041 .suspend = pl011_suspend,
2042 .resume = pl011_resume,
2043#endif
2044};
2045
2046static int __init pl011_init(void)
2047{
2048 int ret;
2049 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2050
2051 ret = uart_register_driver(&amba_reg);
2052 if (ret == 0) {
2053 ret = amba_driver_register(&pl011_driver);
2054 if (ret)
2055 uart_unregister_driver(&amba_reg);
2056 }
2057 return ret;
2058}
2059
2060static void __exit pl011_exit(void)
2061{
2062 amba_driver_unregister(&pl011_driver);
2063 uart_unregister_driver(&amba_reg);
2064}
2065
2066/*
2067 * While this can be a module, if builtin it's most likely the console
2068 * So let's leave module_exit but move module_init to an earlier place
2069 */
2070arch_initcall(pl011_init);
2071module_exit(pl011_exit);
2072
2073MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2074MODULE_DESCRIPTION("ARM AMBA serial port driver");
2075MODULE_LICENSE("GPL");