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1/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
12#include <linux/pci-aspm.h>
13#include "pci.h"
14
15#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16#define CARDBUS_RESERVE_BUSNR 3
17
18/* Ugh. Need to stop exporting this to modules. */
19LIST_HEAD(pci_root_buses);
20EXPORT_SYMBOL(pci_root_buses);
21
22
23static int find_anything(struct device *dev, void *data)
24{
25 return 1;
26}
27
28/*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33int no_pci_devices(void)
34{
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42}
43EXPORT_SYMBOL(no_pci_devices);
44
45/*
46 * PCI Bus Class
47 */
48static void release_pcibus_dev(struct device *dev)
49{
50 struct pci_bus *pci_bus = to_pci_bus(dev);
51
52 if (pci_bus->bridge)
53 put_device(pci_bus->bridge);
54 pci_bus_remove_resources(pci_bus);
55 pci_release_bus_of_node(pci_bus);
56 kfree(pci_bus);
57}
58
59static struct class pcibus_class = {
60 .name = "pci_bus",
61 .dev_release = &release_pcibus_dev,
62 .dev_attrs = pcibus_dev_attrs,
63};
64
65static int __init pcibus_class_init(void)
66{
67 return class_register(&pcibus_class);
68}
69postcore_initcall(pcibus_class_init);
70
71static u64 pci_size(u64 base, u64 maxbase, u64 mask)
72{
73 u64 size = mask & maxbase; /* Find the significant bits */
74 if (!size)
75 return 0;
76
77 /* Get the lowest of them to find the decode size, and
78 from that the extent. */
79 size = (size & ~(size-1)) - 1;
80
81 /* base == maxbase can be valid only if the BAR has
82 already been programmed with all 1s. */
83 if (base == maxbase && ((base | size) & mask) != mask)
84 return 0;
85
86 return size;
87}
88
89static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
90{
91 u32 mem_type;
92 unsigned long flags;
93
94 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
95 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
96 flags |= IORESOURCE_IO;
97 return flags;
98 }
99
100 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
101 flags |= IORESOURCE_MEM;
102 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
103 flags |= IORESOURCE_PREFETCH;
104
105 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
106 switch (mem_type) {
107 case PCI_BASE_ADDRESS_MEM_TYPE_32:
108 break;
109 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
110 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
111 break;
112 case PCI_BASE_ADDRESS_MEM_TYPE_64:
113 flags |= IORESOURCE_MEM_64;
114 break;
115 default:
116 dev_warn(&dev->dev,
117 "mem unknown type %x treated as 32-bit BAR\n",
118 mem_type);
119 break;
120 }
121 return flags;
122}
123
124/**
125 * pci_read_base - read a PCI BAR
126 * @dev: the PCI device
127 * @type: type of the BAR
128 * @res: resource buffer to be filled in
129 * @pos: BAR position in the config space
130 *
131 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
132 */
133int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
134 struct resource *res, unsigned int pos)
135{
136 u32 l, sz, mask;
137 u16 orig_cmd;
138
139 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
140
141 if (!dev->mmio_always_on) {
142 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
143 pci_write_config_word(dev, PCI_COMMAND,
144 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
145 }
146
147 res->name = pci_name(dev);
148
149 pci_read_config_dword(dev, pos, &l);
150 pci_write_config_dword(dev, pos, l | mask);
151 pci_read_config_dword(dev, pos, &sz);
152 pci_write_config_dword(dev, pos, l);
153
154 if (!dev->mmio_always_on)
155 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
156
157 /*
158 * All bits set in sz means the device isn't working properly.
159 * If the BAR isn't implemented, all bits must be 0. If it's a
160 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
161 * 1 must be clear.
162 */
163 if (!sz || sz == 0xffffffff)
164 goto fail;
165
166 /*
167 * I don't know how l can have all bits set. Copied from old code.
168 * Maybe it fixes a bug on some ancient platform.
169 */
170 if (l == 0xffffffff)
171 l = 0;
172
173 if (type == pci_bar_unknown) {
174 res->flags = decode_bar(dev, l);
175 res->flags |= IORESOURCE_SIZEALIGN;
176 if (res->flags & IORESOURCE_IO) {
177 l &= PCI_BASE_ADDRESS_IO_MASK;
178 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
179 } else {
180 l &= PCI_BASE_ADDRESS_MEM_MASK;
181 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
182 }
183 } else {
184 res->flags |= (l & IORESOURCE_ROM_ENABLE);
185 l &= PCI_ROM_ADDRESS_MASK;
186 mask = (u32)PCI_ROM_ADDRESS_MASK;
187 }
188
189 if (res->flags & IORESOURCE_MEM_64) {
190 u64 l64 = l;
191 u64 sz64 = sz;
192 u64 mask64 = mask | (u64)~0 << 32;
193
194 pci_read_config_dword(dev, pos + 4, &l);
195 pci_write_config_dword(dev, pos + 4, ~0);
196 pci_read_config_dword(dev, pos + 4, &sz);
197 pci_write_config_dword(dev, pos + 4, l);
198
199 l64 |= ((u64)l << 32);
200 sz64 |= ((u64)sz << 32);
201
202 sz64 = pci_size(l64, sz64, mask64);
203
204 if (!sz64)
205 goto fail;
206
207 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
208 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
209 pos);
210 goto fail;
211 }
212
213 if ((sizeof(resource_size_t) < 8) && l) {
214 /* Address above 32-bit boundary; disable the BAR */
215 pci_write_config_dword(dev, pos, 0);
216 pci_write_config_dword(dev, pos + 4, 0);
217 res->start = 0;
218 res->end = sz64;
219 } else {
220 res->start = l64;
221 res->end = l64 + sz64;
222 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
223 pos, res);
224 }
225 } else {
226 sz = pci_size(l, sz, mask);
227
228 if (!sz)
229 goto fail;
230
231 res->start = l;
232 res->end = l + sz;
233
234 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
235 }
236
237 out:
238 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
239 fail:
240 res->flags = 0;
241 goto out;
242}
243
244static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
245{
246 unsigned int pos, reg;
247
248 for (pos = 0; pos < howmany; pos++) {
249 struct resource *res = &dev->resource[pos];
250 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
251 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
252 }
253
254 if (rom) {
255 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
256 dev->rom_base_reg = rom;
257 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
258 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
259 IORESOURCE_SIZEALIGN;
260 __pci_read_base(dev, pci_bar_mem32, res, rom);
261 }
262}
263
264static void __devinit pci_read_bridge_io(struct pci_bus *child)
265{
266 struct pci_dev *dev = child->self;
267 u8 io_base_lo, io_limit_lo;
268 unsigned long base, limit;
269 struct resource *res;
270
271 res = child->resource[0];
272 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
273 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
274 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
275 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
276
277 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
278 u16 io_base_hi, io_limit_hi;
279 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
280 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
281 base |= (io_base_hi << 16);
282 limit |= (io_limit_hi << 16);
283 }
284
285 if (base && base <= limit) {
286 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
287 if (!res->start)
288 res->start = base;
289 if (!res->end)
290 res->end = limit + 0xfff;
291 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
292 }
293}
294
295static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
296{
297 struct pci_dev *dev = child->self;
298 u16 mem_base_lo, mem_limit_lo;
299 unsigned long base, limit;
300 struct resource *res;
301
302 res = child->resource[1];
303 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
304 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
305 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
306 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
307 if (base && base <= limit) {
308 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
309 res->start = base;
310 res->end = limit + 0xfffff;
311 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
312 }
313}
314
315static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
316{
317 struct pci_dev *dev = child->self;
318 u16 mem_base_lo, mem_limit_lo;
319 unsigned long base, limit;
320 struct resource *res;
321
322 res = child->resource[2];
323 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
324 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
325 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
326 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
327
328 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
329 u32 mem_base_hi, mem_limit_hi;
330 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
331 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
332
333 /*
334 * Some bridges set the base > limit by default, and some
335 * (broken) BIOSes do not initialize them. If we find
336 * this, just assume they are not being used.
337 */
338 if (mem_base_hi <= mem_limit_hi) {
339#if BITS_PER_LONG == 64
340 base |= ((long) mem_base_hi) << 32;
341 limit |= ((long) mem_limit_hi) << 32;
342#else
343 if (mem_base_hi || mem_limit_hi) {
344 dev_err(&dev->dev, "can't handle 64-bit "
345 "address space for bridge\n");
346 return;
347 }
348#endif
349 }
350 }
351 if (base && base <= limit) {
352 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
353 IORESOURCE_MEM | IORESOURCE_PREFETCH;
354 if (res->flags & PCI_PREF_RANGE_TYPE_64)
355 res->flags |= IORESOURCE_MEM_64;
356 res->start = base;
357 res->end = limit + 0xfffff;
358 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
359 }
360}
361
362void __devinit pci_read_bridge_bases(struct pci_bus *child)
363{
364 struct pci_dev *dev = child->self;
365 struct resource *res;
366 int i;
367
368 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
369 return;
370
371 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
372 child->secondary, child->subordinate,
373 dev->transparent ? " (subtractive decode)" : "");
374
375 pci_bus_remove_resources(child);
376 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
377 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
378
379 pci_read_bridge_io(child);
380 pci_read_bridge_mmio(child);
381 pci_read_bridge_mmio_pref(child);
382
383 if (dev->transparent) {
384 pci_bus_for_each_resource(child->parent, res, i) {
385 if (res) {
386 pci_bus_add_resource(child, res,
387 PCI_SUBTRACTIVE_DECODE);
388 dev_printk(KERN_DEBUG, &dev->dev,
389 " bridge window %pR (subtractive decode)\n",
390 res);
391 }
392 }
393 }
394}
395
396static struct pci_bus * pci_alloc_bus(void)
397{
398 struct pci_bus *b;
399
400 b = kzalloc(sizeof(*b), GFP_KERNEL);
401 if (b) {
402 INIT_LIST_HEAD(&b->node);
403 INIT_LIST_HEAD(&b->children);
404 INIT_LIST_HEAD(&b->devices);
405 INIT_LIST_HEAD(&b->slots);
406 INIT_LIST_HEAD(&b->resources);
407 b->max_bus_speed = PCI_SPEED_UNKNOWN;
408 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
409 }
410 return b;
411}
412
413static unsigned char pcix_bus_speed[] = {
414 PCI_SPEED_UNKNOWN, /* 0 */
415 PCI_SPEED_66MHz_PCIX, /* 1 */
416 PCI_SPEED_100MHz_PCIX, /* 2 */
417 PCI_SPEED_133MHz_PCIX, /* 3 */
418 PCI_SPEED_UNKNOWN, /* 4 */
419 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
420 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
421 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
422 PCI_SPEED_UNKNOWN, /* 8 */
423 PCI_SPEED_66MHz_PCIX_266, /* 9 */
424 PCI_SPEED_100MHz_PCIX_266, /* A */
425 PCI_SPEED_133MHz_PCIX_266, /* B */
426 PCI_SPEED_UNKNOWN, /* C */
427 PCI_SPEED_66MHz_PCIX_533, /* D */
428 PCI_SPEED_100MHz_PCIX_533, /* E */
429 PCI_SPEED_133MHz_PCIX_533 /* F */
430};
431
432static unsigned char pcie_link_speed[] = {
433 PCI_SPEED_UNKNOWN, /* 0 */
434 PCIE_SPEED_2_5GT, /* 1 */
435 PCIE_SPEED_5_0GT, /* 2 */
436 PCIE_SPEED_8_0GT, /* 3 */
437 PCI_SPEED_UNKNOWN, /* 4 */
438 PCI_SPEED_UNKNOWN, /* 5 */
439 PCI_SPEED_UNKNOWN, /* 6 */
440 PCI_SPEED_UNKNOWN, /* 7 */
441 PCI_SPEED_UNKNOWN, /* 8 */
442 PCI_SPEED_UNKNOWN, /* 9 */
443 PCI_SPEED_UNKNOWN, /* A */
444 PCI_SPEED_UNKNOWN, /* B */
445 PCI_SPEED_UNKNOWN, /* C */
446 PCI_SPEED_UNKNOWN, /* D */
447 PCI_SPEED_UNKNOWN, /* E */
448 PCI_SPEED_UNKNOWN /* F */
449};
450
451void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
452{
453 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
454}
455EXPORT_SYMBOL_GPL(pcie_update_link_speed);
456
457static unsigned char agp_speeds[] = {
458 AGP_UNKNOWN,
459 AGP_1X,
460 AGP_2X,
461 AGP_4X,
462 AGP_8X
463};
464
465static enum pci_bus_speed agp_speed(int agp3, int agpstat)
466{
467 int index = 0;
468
469 if (agpstat & 4)
470 index = 3;
471 else if (agpstat & 2)
472 index = 2;
473 else if (agpstat & 1)
474 index = 1;
475 else
476 goto out;
477
478 if (agp3) {
479 index += 2;
480 if (index == 5)
481 index = 0;
482 }
483
484 out:
485 return agp_speeds[index];
486}
487
488
489static void pci_set_bus_speed(struct pci_bus *bus)
490{
491 struct pci_dev *bridge = bus->self;
492 int pos;
493
494 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
495 if (!pos)
496 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
497 if (pos) {
498 u32 agpstat, agpcmd;
499
500 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
501 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
502
503 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
504 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
505 }
506
507 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
508 if (pos) {
509 u16 status;
510 enum pci_bus_speed max;
511 pci_read_config_word(bridge, pos + 2, &status);
512
513 if (status & 0x8000) {
514 max = PCI_SPEED_133MHz_PCIX_533;
515 } else if (status & 0x4000) {
516 max = PCI_SPEED_133MHz_PCIX_266;
517 } else if (status & 0x0002) {
518 if (((status >> 12) & 0x3) == 2) {
519 max = PCI_SPEED_133MHz_PCIX_ECC;
520 } else {
521 max = PCI_SPEED_133MHz_PCIX;
522 }
523 } else {
524 max = PCI_SPEED_66MHz_PCIX;
525 }
526
527 bus->max_bus_speed = max;
528 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
529
530 return;
531 }
532
533 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
534 if (pos) {
535 u32 linkcap;
536 u16 linksta;
537
538 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
539 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
540
541 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
542 pcie_update_link_speed(bus, linksta);
543 }
544}
545
546
547static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
548 struct pci_dev *bridge, int busnr)
549{
550 struct pci_bus *child;
551 int i;
552
553 /*
554 * Allocate a new bus, and inherit stuff from the parent..
555 */
556 child = pci_alloc_bus();
557 if (!child)
558 return NULL;
559
560 child->parent = parent;
561 child->ops = parent->ops;
562 child->sysdata = parent->sysdata;
563 child->bus_flags = parent->bus_flags;
564
565 /* initialize some portions of the bus device, but don't register it
566 * now as the parent is not properly set up yet. This device will get
567 * registered later in pci_bus_add_devices()
568 */
569 child->dev.class = &pcibus_class;
570 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
571
572 /*
573 * Set up the primary, secondary and subordinate
574 * bus numbers.
575 */
576 child->number = child->secondary = busnr;
577 child->primary = parent->secondary;
578 child->subordinate = 0xff;
579
580 if (!bridge)
581 return child;
582
583 child->self = bridge;
584 child->bridge = get_device(&bridge->dev);
585 pci_set_bus_of_node(child);
586 pci_set_bus_speed(child);
587
588 /* Set up default resource pointers and names.. */
589 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
590 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
591 child->resource[i]->name = child->name;
592 }
593 bridge->subordinate = child;
594
595 return child;
596}
597
598struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
599{
600 struct pci_bus *child;
601
602 child = pci_alloc_child_bus(parent, dev, busnr);
603 if (child) {
604 down_write(&pci_bus_sem);
605 list_add_tail(&child->node, &parent->children);
606 up_write(&pci_bus_sem);
607 }
608 return child;
609}
610
611static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
612{
613 struct pci_bus *parent = child->parent;
614
615 /* Attempts to fix that up are really dangerous unless
616 we're going to re-assign all bus numbers. */
617 if (!pcibios_assign_all_busses())
618 return;
619
620 while (parent->parent && parent->subordinate < max) {
621 parent->subordinate = max;
622 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
623 parent = parent->parent;
624 }
625}
626
627/*
628 * If it's a bridge, configure it and scan the bus behind it.
629 * For CardBus bridges, we don't scan behind as the devices will
630 * be handled by the bridge driver itself.
631 *
632 * We need to process bridges in two passes -- first we scan those
633 * already configured by the BIOS and after we are done with all of
634 * them, we proceed to assigning numbers to the remaining buses in
635 * order to avoid overlaps between old and new bus numbers.
636 */
637int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
638{
639 struct pci_bus *child;
640 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
641 u32 buses, i, j = 0;
642 u16 bctl;
643 u8 primary, secondary, subordinate;
644 int broken = 0;
645
646 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
647 primary = buses & 0xFF;
648 secondary = (buses >> 8) & 0xFF;
649 subordinate = (buses >> 16) & 0xFF;
650
651 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
652 secondary, subordinate, pass);
653
654 /* Check if setup is sensible at all */
655 if (!pass &&
656 (primary != bus->number || secondary <= bus->number)) {
657 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
658 broken = 1;
659 }
660
661 /* Disable MasterAbortMode during probing to avoid reporting
662 of bus errors (in some architectures) */
663 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
664 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
665 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
666
667 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
668 !is_cardbus && !broken) {
669 unsigned int cmax;
670 /*
671 * Bus already configured by firmware, process it in the first
672 * pass and just note the configuration.
673 */
674 if (pass)
675 goto out;
676
677 /*
678 * If we already got to this bus through a different bridge,
679 * don't re-add it. This can happen with the i450NX chipset.
680 *
681 * However, we continue to descend down the hierarchy and
682 * scan remaining child buses.
683 */
684 child = pci_find_bus(pci_domain_nr(bus), secondary);
685 if (!child) {
686 child = pci_add_new_bus(bus, dev, secondary);
687 if (!child)
688 goto out;
689 child->primary = primary;
690 child->subordinate = subordinate;
691 child->bridge_ctl = bctl;
692 }
693
694 cmax = pci_scan_child_bus(child);
695 if (cmax > max)
696 max = cmax;
697 if (child->subordinate > max)
698 max = child->subordinate;
699 } else {
700 /*
701 * We need to assign a number to this bus which we always
702 * do in the second pass.
703 */
704 if (!pass) {
705 if (pcibios_assign_all_busses() || broken)
706 /* Temporarily disable forwarding of the
707 configuration cycles on all bridges in
708 this bus segment to avoid possible
709 conflicts in the second pass between two
710 bridges programmed with overlapping
711 bus ranges. */
712 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
713 buses & ~0xffffff);
714 goto out;
715 }
716
717 /* Clear errors */
718 pci_write_config_word(dev, PCI_STATUS, 0xffff);
719
720 /* Prevent assigning a bus number that already exists.
721 * This can happen when a bridge is hot-plugged, so in
722 * this case we only re-scan this bus. */
723 child = pci_find_bus(pci_domain_nr(bus), max+1);
724 if (!child) {
725 child = pci_add_new_bus(bus, dev, ++max);
726 if (!child)
727 goto out;
728 }
729 buses = (buses & 0xff000000)
730 | ((unsigned int)(child->primary) << 0)
731 | ((unsigned int)(child->secondary) << 8)
732 | ((unsigned int)(child->subordinate) << 16);
733
734 /*
735 * yenta.c forces a secondary latency timer of 176.
736 * Copy that behaviour here.
737 */
738 if (is_cardbus) {
739 buses &= ~0xff000000;
740 buses |= CARDBUS_LATENCY_TIMER << 24;
741 }
742
743 /*
744 * We need to blast all three values with a single write.
745 */
746 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
747
748 if (!is_cardbus) {
749 child->bridge_ctl = bctl;
750 /*
751 * Adjust subordinate busnr in parent buses.
752 * We do this before scanning for children because
753 * some devices may not be detected if the bios
754 * was lazy.
755 */
756 pci_fixup_parent_subordinate_busnr(child, max);
757 /* Now we can scan all subordinate buses... */
758 max = pci_scan_child_bus(child);
759 /*
760 * now fix it up again since we have found
761 * the real value of max.
762 */
763 pci_fixup_parent_subordinate_busnr(child, max);
764 } else {
765 /*
766 * For CardBus bridges, we leave 4 bus numbers
767 * as cards with a PCI-to-PCI bridge can be
768 * inserted later.
769 */
770 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
771 struct pci_bus *parent = bus;
772 if (pci_find_bus(pci_domain_nr(bus),
773 max+i+1))
774 break;
775 while (parent->parent) {
776 if ((!pcibios_assign_all_busses()) &&
777 (parent->subordinate > max) &&
778 (parent->subordinate <= max+i)) {
779 j = 1;
780 }
781 parent = parent->parent;
782 }
783 if (j) {
784 /*
785 * Often, there are two cardbus bridges
786 * -- try to leave one valid bus number
787 * for each one.
788 */
789 i /= 2;
790 break;
791 }
792 }
793 max += i;
794 pci_fixup_parent_subordinate_busnr(child, max);
795 }
796 /*
797 * Set the subordinate bus number to its real value.
798 */
799 child->subordinate = max;
800 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
801 }
802
803 sprintf(child->name,
804 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
805 pci_domain_nr(bus), child->number);
806
807 /* Has only triggered on CardBus, fixup is in yenta_socket */
808 while (bus->parent) {
809 if ((child->subordinate > bus->subordinate) ||
810 (child->number > bus->subordinate) ||
811 (child->number < bus->number) ||
812 (child->subordinate < bus->number)) {
813 dev_info(&child->dev, "[bus %02x-%02x] %s "
814 "hidden behind%s bridge %s [bus %02x-%02x]\n",
815 child->number, child->subordinate,
816 (bus->number > child->subordinate &&
817 bus->subordinate < child->number) ?
818 "wholly" : "partially",
819 bus->self->transparent ? " transparent" : "",
820 dev_name(&bus->dev),
821 bus->number, bus->subordinate);
822 }
823 bus = bus->parent;
824 }
825
826out:
827 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
828
829 return max;
830}
831
832/*
833 * Read interrupt line and base address registers.
834 * The architecture-dependent code can tweak these, of course.
835 */
836static void pci_read_irq(struct pci_dev *dev)
837{
838 unsigned char irq;
839
840 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
841 dev->pin = irq;
842 if (irq)
843 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
844 dev->irq = irq;
845}
846
847void set_pcie_port_type(struct pci_dev *pdev)
848{
849 int pos;
850 u16 reg16;
851
852 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
853 if (!pos)
854 return;
855 pdev->is_pcie = 1;
856 pdev->pcie_cap = pos;
857 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
858 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
859 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
860 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
861}
862
863void set_pcie_hotplug_bridge(struct pci_dev *pdev)
864{
865 int pos;
866 u16 reg16;
867 u32 reg32;
868
869 pos = pci_pcie_cap(pdev);
870 if (!pos)
871 return;
872 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
873 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
874 return;
875 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);
876 if (reg32 & PCI_EXP_SLTCAP_HPC)
877 pdev->is_hotplug_bridge = 1;
878}
879
880#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
881
882/**
883 * pci_setup_device - fill in class and map information of a device
884 * @dev: the device structure to fill
885 *
886 * Initialize the device structure with information about the device's
887 * vendor,class,memory and IO-space addresses,IRQ lines etc.
888 * Called at initialisation of the PCI subsystem and by CardBus services.
889 * Returns 0 on success and negative if unknown type of device (not normal,
890 * bridge or CardBus).
891 */
892int pci_setup_device(struct pci_dev *dev)
893{
894 u32 class;
895 u8 hdr_type;
896 struct pci_slot *slot;
897 int pos = 0;
898
899 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
900 return -EIO;
901
902 dev->sysdata = dev->bus->sysdata;
903 dev->dev.parent = dev->bus->bridge;
904 dev->dev.bus = &pci_bus_type;
905 dev->hdr_type = hdr_type & 0x7f;
906 dev->multifunction = !!(hdr_type & 0x80);
907 dev->error_state = pci_channel_io_normal;
908 set_pcie_port_type(dev);
909
910 list_for_each_entry(slot, &dev->bus->slots, list)
911 if (PCI_SLOT(dev->devfn) == slot->number)
912 dev->slot = slot;
913
914 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
915 set this higher, assuming the system even supports it. */
916 dev->dma_mask = 0xffffffff;
917
918 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
919 dev->bus->number, PCI_SLOT(dev->devfn),
920 PCI_FUNC(dev->devfn));
921
922 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
923 dev->revision = class & 0xff;
924 class >>= 8; /* upper 3 bytes */
925 dev->class = class;
926 class >>= 8;
927
928 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
929 dev->vendor, dev->device, dev->hdr_type, class);
930
931 /* need to have dev->class ready */
932 dev->cfg_size = pci_cfg_space_size(dev);
933
934 /* "Unknown power state" */
935 dev->current_state = PCI_UNKNOWN;
936
937 /* Early fixups, before probing the BARs */
938 pci_fixup_device(pci_fixup_early, dev);
939 /* device class may be changed after fixup */
940 class = dev->class >> 8;
941
942 switch (dev->hdr_type) { /* header type */
943 case PCI_HEADER_TYPE_NORMAL: /* standard header */
944 if (class == PCI_CLASS_BRIDGE_PCI)
945 goto bad;
946 pci_read_irq(dev);
947 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
948 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
949 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
950
951 /*
952 * Do the ugly legacy mode stuff here rather than broken chip
953 * quirk code. Legacy mode ATA controllers have fixed
954 * addresses. These are not always echoed in BAR0-3, and
955 * BAR0-3 in a few cases contain junk!
956 */
957 if (class == PCI_CLASS_STORAGE_IDE) {
958 u8 progif;
959 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
960 if ((progif & 1) == 0) {
961 dev->resource[0].start = 0x1F0;
962 dev->resource[0].end = 0x1F7;
963 dev->resource[0].flags = LEGACY_IO_RESOURCE;
964 dev->resource[1].start = 0x3F6;
965 dev->resource[1].end = 0x3F6;
966 dev->resource[1].flags = LEGACY_IO_RESOURCE;
967 }
968 if ((progif & 4) == 0) {
969 dev->resource[2].start = 0x170;
970 dev->resource[2].end = 0x177;
971 dev->resource[2].flags = LEGACY_IO_RESOURCE;
972 dev->resource[3].start = 0x376;
973 dev->resource[3].end = 0x376;
974 dev->resource[3].flags = LEGACY_IO_RESOURCE;
975 }
976 }
977 break;
978
979 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
980 if (class != PCI_CLASS_BRIDGE_PCI)
981 goto bad;
982 /* The PCI-to-PCI bridge spec requires that subtractive
983 decoding (i.e. transparent) bridge must have programming
984 interface code of 0x01. */
985 pci_read_irq(dev);
986 dev->transparent = ((dev->class & 0xff) == 1);
987 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
988 set_pcie_hotplug_bridge(dev);
989 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
990 if (pos) {
991 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
992 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
993 }
994 break;
995
996 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
997 if (class != PCI_CLASS_BRIDGE_CARDBUS)
998 goto bad;
999 pci_read_irq(dev);
1000 pci_read_bases(dev, 1, 0);
1001 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1002 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1003 break;
1004
1005 default: /* unknown header */
1006 dev_err(&dev->dev, "unknown header type %02x, "
1007 "ignoring device\n", dev->hdr_type);
1008 return -EIO;
1009
1010 bad:
1011 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1012 "type %02x)\n", class, dev->hdr_type);
1013 dev->class = PCI_CLASS_NOT_DEFINED;
1014 }
1015
1016 /* We found a fine healthy device, go go go... */
1017 return 0;
1018}
1019
1020static void pci_release_capabilities(struct pci_dev *dev)
1021{
1022 pci_vpd_release(dev);
1023 pci_iov_release(dev);
1024}
1025
1026/**
1027 * pci_release_dev - free a pci device structure when all users of it are finished.
1028 * @dev: device that's been disconnected
1029 *
1030 * Will be called only by the device core when all users of this pci device are
1031 * done.
1032 */
1033static void pci_release_dev(struct device *dev)
1034{
1035 struct pci_dev *pci_dev;
1036
1037 pci_dev = to_pci_dev(dev);
1038 pci_release_capabilities(pci_dev);
1039 pci_release_of_node(pci_dev);
1040 kfree(pci_dev);
1041}
1042
1043/**
1044 * pci_cfg_space_size - get the configuration space size of the PCI device.
1045 * @dev: PCI device
1046 *
1047 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1048 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1049 * access it. Maybe we don't have a way to generate extended config space
1050 * accesses, or the device is behind a reverse Express bridge. So we try
1051 * reading the dword at 0x100 which must either be 0 or a valid extended
1052 * capability header.
1053 */
1054int pci_cfg_space_size_ext(struct pci_dev *dev)
1055{
1056 u32 status;
1057 int pos = PCI_CFG_SPACE_SIZE;
1058
1059 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1060 goto fail;
1061 if (status == 0xffffffff)
1062 goto fail;
1063
1064 return PCI_CFG_SPACE_EXP_SIZE;
1065
1066 fail:
1067 return PCI_CFG_SPACE_SIZE;
1068}
1069
1070int pci_cfg_space_size(struct pci_dev *dev)
1071{
1072 int pos;
1073 u32 status;
1074 u16 class;
1075
1076 class = dev->class >> 8;
1077 if (class == PCI_CLASS_BRIDGE_HOST)
1078 return pci_cfg_space_size_ext(dev);
1079
1080 pos = pci_pcie_cap(dev);
1081 if (!pos) {
1082 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1083 if (!pos)
1084 goto fail;
1085
1086 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1087 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1088 goto fail;
1089 }
1090
1091 return pci_cfg_space_size_ext(dev);
1092
1093 fail:
1094 return PCI_CFG_SPACE_SIZE;
1095}
1096
1097static void pci_release_bus_bridge_dev(struct device *dev)
1098{
1099 kfree(dev);
1100}
1101
1102struct pci_dev *alloc_pci_dev(void)
1103{
1104 struct pci_dev *dev;
1105
1106 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1107 if (!dev)
1108 return NULL;
1109
1110 INIT_LIST_HEAD(&dev->bus_list);
1111
1112 return dev;
1113}
1114EXPORT_SYMBOL(alloc_pci_dev);
1115
1116/*
1117 * Read the config data for a PCI device, sanity-check it
1118 * and fill in the dev structure...
1119 */
1120static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1121{
1122 struct pci_dev *dev;
1123 u32 l;
1124 int delay = 1;
1125
1126 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1127 return NULL;
1128
1129 /* some broken boards return 0 or ~0 if a slot is empty: */
1130 if (l == 0xffffffff || l == 0x00000000 ||
1131 l == 0x0000ffff || l == 0xffff0000)
1132 return NULL;
1133
1134 /* Configuration request Retry Status */
1135 while (l == 0xffff0001) {
1136 msleep(delay);
1137 delay *= 2;
1138 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1139 return NULL;
1140 /* Card hasn't responded in 60 seconds? Must be stuck. */
1141 if (delay > 60 * 1000) {
1142 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1143 "responding\n", pci_domain_nr(bus),
1144 bus->number, PCI_SLOT(devfn),
1145 PCI_FUNC(devfn));
1146 return NULL;
1147 }
1148 }
1149
1150 dev = alloc_pci_dev();
1151 if (!dev)
1152 return NULL;
1153
1154 dev->bus = bus;
1155 dev->devfn = devfn;
1156 dev->vendor = l & 0xffff;
1157 dev->device = (l >> 16) & 0xffff;
1158
1159 pci_set_of_node(dev);
1160
1161 if (pci_setup_device(dev)) {
1162 kfree(dev);
1163 return NULL;
1164 }
1165
1166 return dev;
1167}
1168
1169static void pci_init_capabilities(struct pci_dev *dev)
1170{
1171 /* MSI/MSI-X list */
1172 pci_msi_init_pci_dev(dev);
1173
1174 /* Buffers for saving PCIe and PCI-X capabilities */
1175 pci_allocate_cap_save_buffers(dev);
1176
1177 /* Power Management */
1178 pci_pm_init(dev);
1179 platform_pci_wakeup_init(dev);
1180
1181 /* Vital Product Data */
1182 pci_vpd_pci22_init(dev);
1183
1184 /* Alternative Routing-ID Forwarding */
1185 pci_enable_ari(dev);
1186
1187 /* Single Root I/O Virtualization */
1188 pci_iov_init(dev);
1189
1190 /* Enable ACS P2P upstream forwarding */
1191 pci_enable_acs(dev);
1192}
1193
1194void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1195{
1196 device_initialize(&dev->dev);
1197 dev->dev.release = pci_release_dev;
1198 pci_dev_get(dev);
1199
1200 dev->dev.dma_mask = &dev->dma_mask;
1201 dev->dev.dma_parms = &dev->dma_parms;
1202 dev->dev.coherent_dma_mask = 0xffffffffull;
1203
1204 pci_set_dma_max_seg_size(dev, 65536);
1205 pci_set_dma_seg_boundary(dev, 0xffffffff);
1206
1207 /* Fix up broken headers */
1208 pci_fixup_device(pci_fixup_header, dev);
1209
1210 /* Clear the state_saved flag. */
1211 dev->state_saved = false;
1212
1213 /* Initialize various capabilities */
1214 pci_init_capabilities(dev);
1215
1216 /*
1217 * Add the device to our list of discovered devices
1218 * and the bus list for fixup functions, etc.
1219 */
1220 down_write(&pci_bus_sem);
1221 list_add_tail(&dev->bus_list, &bus->devices);
1222 up_write(&pci_bus_sem);
1223}
1224
1225struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1226{
1227 struct pci_dev *dev;
1228
1229 dev = pci_get_slot(bus, devfn);
1230 if (dev) {
1231 pci_dev_put(dev);
1232 return dev;
1233 }
1234
1235 dev = pci_scan_device(bus, devfn);
1236 if (!dev)
1237 return NULL;
1238
1239 pci_device_add(dev, bus);
1240
1241 return dev;
1242}
1243EXPORT_SYMBOL(pci_scan_single_device);
1244
1245static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1246{
1247 u16 cap;
1248 unsigned pos, next_fn;
1249
1250 if (!dev)
1251 return 0;
1252
1253 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1254 if (!pos)
1255 return 0;
1256 pci_read_config_word(dev, pos + 4, &cap);
1257 next_fn = cap >> 8;
1258 if (next_fn <= fn)
1259 return 0;
1260 return next_fn;
1261}
1262
1263static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1264{
1265 return (fn + 1) % 8;
1266}
1267
1268static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1269{
1270 return 0;
1271}
1272
1273static int only_one_child(struct pci_bus *bus)
1274{
1275 struct pci_dev *parent = bus->self;
1276 if (!parent || !pci_is_pcie(parent))
1277 return 0;
1278 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1279 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1280 return 1;
1281 return 0;
1282}
1283
1284/**
1285 * pci_scan_slot - scan a PCI slot on a bus for devices.
1286 * @bus: PCI bus to scan
1287 * @devfn: slot number to scan (must have zero function.)
1288 *
1289 * Scan a PCI slot on the specified PCI bus for devices, adding
1290 * discovered devices to the @bus->devices list. New devices
1291 * will not have is_added set.
1292 *
1293 * Returns the number of new devices found.
1294 */
1295int pci_scan_slot(struct pci_bus *bus, int devfn)
1296{
1297 unsigned fn, nr = 0;
1298 struct pci_dev *dev;
1299 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1300
1301 if (only_one_child(bus) && (devfn > 0))
1302 return 0; /* Already scanned the entire slot */
1303
1304 dev = pci_scan_single_device(bus, devfn);
1305 if (!dev)
1306 return 0;
1307 if (!dev->is_added)
1308 nr++;
1309
1310 if (pci_ari_enabled(bus))
1311 next_fn = next_ari_fn;
1312 else if (dev->multifunction)
1313 next_fn = next_trad_fn;
1314
1315 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1316 dev = pci_scan_single_device(bus, devfn + fn);
1317 if (dev) {
1318 if (!dev->is_added)
1319 nr++;
1320 dev->multifunction = 1;
1321 }
1322 }
1323
1324 /* only one slot has pcie device */
1325 if (bus->self && nr)
1326 pcie_aspm_init_link_state(bus->self);
1327
1328 return nr;
1329}
1330
1331static int pcie_find_smpss(struct pci_dev *dev, void *data)
1332{
1333 u8 *smpss = data;
1334
1335 if (!pci_is_pcie(dev))
1336 return 0;
1337
1338 /* For PCIE hotplug enabled slots not connected directly to a
1339 * PCI-E root port, there can be problems when hotplugging
1340 * devices. This is due to the possibility of hotplugging a
1341 * device into the fabric with a smaller MPS that the devices
1342 * currently running have configured. Modifying the MPS on the
1343 * running devices could cause a fatal bus error due to an
1344 * incoming frame being larger than the newly configured MPS.
1345 * To work around this, the MPS for the entire fabric must be
1346 * set to the minimum size. Any devices hotplugged into this
1347 * fabric will have the minimum MPS set. If the PCI hotplug
1348 * slot is directly connected to the root port and there are not
1349 * other devices on the fabric (which seems to be the most
1350 * common case), then this is not an issue and MPS discovery
1351 * will occur as normal.
1352 */
1353 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1354 (dev->bus->self &&
1355 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
1356 *smpss = 0;
1357
1358 if (*smpss > dev->pcie_mpss)
1359 *smpss = dev->pcie_mpss;
1360
1361 return 0;
1362}
1363
1364static void pcie_write_mps(struct pci_dev *dev, int mps)
1365{
1366 int rc, dev_mpss;
1367
1368 dev_mpss = 128 << dev->pcie_mpss;
1369
1370 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1371 if (dev->bus->self) {
1372 dev_dbg(&dev->bus->dev, "Bus MPSS %d\n",
1373 128 << dev->bus->self->pcie_mpss);
1374
1375 /* For "MPS Force Max", the assumption is made that
1376 * downstream communication will never be larger than
1377 * the MRRS. So, the MPS only needs to be configured
1378 * for the upstream communication. This being the case,
1379 * walk from the top down and set the MPS of the child
1380 * to that of the parent bus.
1381 */
1382 mps = 128 << dev->bus->self->pcie_mpss;
1383 if (mps > dev_mpss)
1384 dev_warn(&dev->dev, "MPS configured higher than"
1385 " maximum supported by the device. If"
1386 " a bus issue occurs, try running with"
1387 " pci=pcie_bus_safe.\n");
1388 }
1389
1390 dev->pcie_mpss = ffs(mps) - 8;
1391 }
1392
1393 rc = pcie_set_mps(dev, mps);
1394 if (rc)
1395 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1396}
1397
1398static void pcie_write_mrrs(struct pci_dev *dev, int mps)
1399{
1400 int rc, mrrs, dev_mpss;
1401
1402 /* In the "safe" case, do not configure the MRRS. There appear to be
1403 * issues with setting MRRS to 0 on a number of devices.
1404 */
1405
1406 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1407 return;
1408
1409 dev_mpss = 128 << dev->pcie_mpss;
1410
1411 /* For Max performance, the MRRS must be set to the largest supported
1412 * value. However, it cannot be configured larger than the MPS the
1413 * device or the bus can support. This assumes that the largest MRRS
1414 * available on the device cannot be smaller than the device MPSS.
1415 */
1416 mrrs = min(mps, dev_mpss);
1417
1418 /* MRRS is a R/W register. Invalid values can be written, but a
1419 * subsequent read will verify if the value is acceptable or not.
1420 * If the MRRS value provided is not acceptable (e.g., too large),
1421 * shrink the value until it is acceptable to the HW.
1422 */
1423 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1424 dev_warn(&dev->dev, "Attempting to modify the PCI-E MRRS value"
1425 " to %d. If any issues are encountered, please try "
1426 "running with pci=pcie_bus_safe\n", mrrs);
1427 rc = pcie_set_readrq(dev, mrrs);
1428 if (rc)
1429 dev_err(&dev->dev,
1430 "Failed attempting to set the MRRS\n");
1431
1432 mrrs /= 2;
1433 }
1434}
1435
1436static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1437{
1438 int mps = 128 << *(u8 *)data;
1439
1440 if (!pci_is_pcie(dev))
1441 return 0;
1442
1443 dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
1444 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
1445
1446 pcie_write_mps(dev, mps);
1447 pcie_write_mrrs(dev, mps);
1448
1449 dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
1450 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
1451
1452 return 0;
1453}
1454
1455/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down,
1456 * parents then children fashion. If this changes, then this code will not
1457 * work as designed.
1458 */
1459void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1460{
1461 u8 smpss;
1462
1463 if (!pci_is_pcie(bus->self))
1464 return;
1465
1466 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1467 return;
1468
1469 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1470 * to be aware to the MPS of the destination. To work around this,
1471 * simply force the MPS of the entire system to the smallest possible.
1472 */
1473 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1474 smpss = 0;
1475
1476 if (pcie_bus_config == PCIE_BUS_SAFE) {
1477 smpss = mpss;
1478
1479 pcie_find_smpss(bus->self, &smpss);
1480 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1481 }
1482
1483 pcie_bus_configure_set(bus->self, &smpss);
1484 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1485}
1486EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1487
1488unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1489{
1490 unsigned int devfn, pass, max = bus->secondary;
1491 struct pci_dev *dev;
1492
1493 dev_dbg(&bus->dev, "scanning bus\n");
1494
1495 /* Go find them, Rover! */
1496 for (devfn = 0; devfn < 0x100; devfn += 8)
1497 pci_scan_slot(bus, devfn);
1498
1499 /* Reserve buses for SR-IOV capability. */
1500 max += pci_iov_bus_range(bus);
1501
1502 /*
1503 * After performing arch-dependent fixup of the bus, look behind
1504 * all PCI-to-PCI bridges on this bus.
1505 */
1506 if (!bus->is_added) {
1507 dev_dbg(&bus->dev, "fixups for bus\n");
1508 pcibios_fixup_bus(bus);
1509 if (pci_is_root_bus(bus))
1510 bus->is_added = 1;
1511 }
1512
1513 for (pass=0; pass < 2; pass++)
1514 list_for_each_entry(dev, &bus->devices, bus_list) {
1515 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1516 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1517 max = pci_scan_bridge(bus, dev, max, pass);
1518 }
1519
1520 /*
1521 * We've scanned the bus and so we know all about what's on
1522 * the other side of any bridges that may be on this bus plus
1523 * any devices.
1524 *
1525 * Return how far we've got finding sub-buses.
1526 */
1527 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1528 return max;
1529}
1530
1531struct pci_bus * pci_create_bus(struct device *parent,
1532 int bus, struct pci_ops *ops, void *sysdata)
1533{
1534 int error;
1535 struct pci_bus *b, *b2;
1536 struct device *dev;
1537
1538 b = pci_alloc_bus();
1539 if (!b)
1540 return NULL;
1541
1542 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1543 if (!dev){
1544 kfree(b);
1545 return NULL;
1546 }
1547
1548 b->sysdata = sysdata;
1549 b->ops = ops;
1550
1551 b2 = pci_find_bus(pci_domain_nr(b), bus);
1552 if (b2) {
1553 /* If we already got to this bus through a different bridge, ignore it */
1554 dev_dbg(&b2->dev, "bus already known\n");
1555 goto err_out;
1556 }
1557
1558 down_write(&pci_bus_sem);
1559 list_add_tail(&b->node, &pci_root_buses);
1560 up_write(&pci_bus_sem);
1561
1562 dev->parent = parent;
1563 dev->release = pci_release_bus_bridge_dev;
1564 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1565 error = device_register(dev);
1566 if (error)
1567 goto dev_reg_err;
1568 b->bridge = get_device(dev);
1569 device_enable_async_suspend(b->bridge);
1570 pci_set_bus_of_node(b);
1571
1572 if (!parent)
1573 set_dev_node(b->bridge, pcibus_to_node(b));
1574
1575 b->dev.class = &pcibus_class;
1576 b->dev.parent = b->bridge;
1577 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1578 error = device_register(&b->dev);
1579 if (error)
1580 goto class_dev_reg_err;
1581
1582 /* Create legacy_io and legacy_mem files for this bus */
1583 pci_create_legacy_files(b);
1584
1585 b->number = b->secondary = bus;
1586 b->resource[0] = &ioport_resource;
1587 b->resource[1] = &iomem_resource;
1588
1589 return b;
1590
1591class_dev_reg_err:
1592 device_unregister(dev);
1593dev_reg_err:
1594 down_write(&pci_bus_sem);
1595 list_del(&b->node);
1596 up_write(&pci_bus_sem);
1597err_out:
1598 kfree(dev);
1599 kfree(b);
1600 return NULL;
1601}
1602
1603struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1604 int bus, struct pci_ops *ops, void *sysdata)
1605{
1606 struct pci_bus *b;
1607
1608 b = pci_create_bus(parent, bus, ops, sysdata);
1609 if (b)
1610 b->subordinate = pci_scan_child_bus(b);
1611 return b;
1612}
1613EXPORT_SYMBOL(pci_scan_bus_parented);
1614
1615#ifdef CONFIG_HOTPLUG
1616/**
1617 * pci_rescan_bus - scan a PCI bus for devices.
1618 * @bus: PCI bus to scan
1619 *
1620 * Scan a PCI bus and child buses for new devices, adds them,
1621 * and enables them.
1622 *
1623 * Returns the max number of subordinate bus discovered.
1624 */
1625unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1626{
1627 unsigned int max;
1628 struct pci_dev *dev;
1629
1630 max = pci_scan_child_bus(bus);
1631
1632 down_read(&pci_bus_sem);
1633 list_for_each_entry(dev, &bus->devices, bus_list)
1634 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1635 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1636 if (dev->subordinate)
1637 pci_bus_size_bridges(dev->subordinate);
1638 up_read(&pci_bus_sem);
1639
1640 pci_bus_assign_resources(bus);
1641 pci_enable_bridges(bus);
1642 pci_bus_add_devices(bus);
1643
1644 return max;
1645}
1646EXPORT_SYMBOL_GPL(pci_rescan_bus);
1647
1648EXPORT_SYMBOL(pci_add_new_bus);
1649EXPORT_SYMBOL(pci_scan_slot);
1650EXPORT_SYMBOL(pci_scan_bridge);
1651EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1652#endif
1653
1654static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1655{
1656 const struct pci_dev *a = to_pci_dev(d_a);
1657 const struct pci_dev *b = to_pci_dev(d_b);
1658
1659 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1660 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1661
1662 if (a->bus->number < b->bus->number) return -1;
1663 else if (a->bus->number > b->bus->number) return 1;
1664
1665 if (a->devfn < b->devfn) return -1;
1666 else if (a->devfn > b->devfn) return 1;
1667
1668 return 0;
1669}
1670
1671void __init pci_sort_breadthfirst(void)
1672{
1673 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1674}
1/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
12#include <linux/pci-aspm.h>
13#include <asm-generic/pci-bridge.h>
14#include "pci.h"
15
16#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17#define CARDBUS_RESERVE_BUSNR 3
18
19/* Ugh. Need to stop exporting this to modules. */
20LIST_HEAD(pci_root_buses);
21EXPORT_SYMBOL(pci_root_buses);
22
23static int find_anything(struct device *dev, void *data)
24{
25 return 1;
26}
27
28/*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33int no_pci_devices(void)
34{
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42}
43EXPORT_SYMBOL(no_pci_devices);
44
45/*
46 * PCI Bus Class
47 */
48static void release_pcibus_dev(struct device *dev)
49{
50 struct pci_bus *pci_bus = to_pci_bus(dev);
51
52 if (pci_bus->bridge)
53 put_device(pci_bus->bridge);
54 pci_bus_remove_resources(pci_bus);
55 pci_release_bus_of_node(pci_bus);
56 kfree(pci_bus);
57}
58
59static struct class pcibus_class = {
60 .name = "pci_bus",
61 .dev_release = &release_pcibus_dev,
62 .dev_attrs = pcibus_dev_attrs,
63};
64
65static int __init pcibus_class_init(void)
66{
67 return class_register(&pcibus_class);
68}
69postcore_initcall(pcibus_class_init);
70
71static u64 pci_size(u64 base, u64 maxbase, u64 mask)
72{
73 u64 size = mask & maxbase; /* Find the significant bits */
74 if (!size)
75 return 0;
76
77 /* Get the lowest of them to find the decode size, and
78 from that the extent. */
79 size = (size & ~(size-1)) - 1;
80
81 /* base == maxbase can be valid only if the BAR has
82 already been programmed with all 1s. */
83 if (base == maxbase && ((base | size) & mask) != mask)
84 return 0;
85
86 return size;
87}
88
89static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
90{
91 u32 mem_type;
92 unsigned long flags;
93
94 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
95 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
96 flags |= IORESOURCE_IO;
97 return flags;
98 }
99
100 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
101 flags |= IORESOURCE_MEM;
102 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
103 flags |= IORESOURCE_PREFETCH;
104
105 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
106 switch (mem_type) {
107 case PCI_BASE_ADDRESS_MEM_TYPE_32:
108 break;
109 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
110 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
111 break;
112 case PCI_BASE_ADDRESS_MEM_TYPE_64:
113 flags |= IORESOURCE_MEM_64;
114 break;
115 default:
116 dev_warn(&dev->dev,
117 "mem unknown type %x treated as 32-bit BAR\n",
118 mem_type);
119 break;
120 }
121 return flags;
122}
123
124/**
125 * pci_read_base - read a PCI BAR
126 * @dev: the PCI device
127 * @type: type of the BAR
128 * @res: resource buffer to be filled in
129 * @pos: BAR position in the config space
130 *
131 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
132 */
133int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
134 struct resource *res, unsigned int pos)
135{
136 u32 l, sz, mask;
137 u16 orig_cmd;
138 struct pci_bus_region region;
139
140 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
141
142 if (!dev->mmio_always_on) {
143 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
144 pci_write_config_word(dev, PCI_COMMAND,
145 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
146 }
147
148 res->name = pci_name(dev);
149
150 pci_read_config_dword(dev, pos, &l);
151 pci_write_config_dword(dev, pos, l | mask);
152 pci_read_config_dword(dev, pos, &sz);
153 pci_write_config_dword(dev, pos, l);
154
155 if (!dev->mmio_always_on)
156 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
157
158 /*
159 * All bits set in sz means the device isn't working properly.
160 * If the BAR isn't implemented, all bits must be 0. If it's a
161 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
162 * 1 must be clear.
163 */
164 if (!sz || sz == 0xffffffff)
165 goto fail;
166
167 /*
168 * I don't know how l can have all bits set. Copied from old code.
169 * Maybe it fixes a bug on some ancient platform.
170 */
171 if (l == 0xffffffff)
172 l = 0;
173
174 if (type == pci_bar_unknown) {
175 res->flags = decode_bar(dev, l);
176 res->flags |= IORESOURCE_SIZEALIGN;
177 if (res->flags & IORESOURCE_IO) {
178 l &= PCI_BASE_ADDRESS_IO_MASK;
179 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
180 } else {
181 l &= PCI_BASE_ADDRESS_MEM_MASK;
182 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
183 }
184 } else {
185 res->flags |= (l & IORESOURCE_ROM_ENABLE);
186 l &= PCI_ROM_ADDRESS_MASK;
187 mask = (u32)PCI_ROM_ADDRESS_MASK;
188 }
189
190 if (res->flags & IORESOURCE_MEM_64) {
191 u64 l64 = l;
192 u64 sz64 = sz;
193 u64 mask64 = mask | (u64)~0 << 32;
194
195 pci_read_config_dword(dev, pos + 4, &l);
196 pci_write_config_dword(dev, pos + 4, ~0);
197 pci_read_config_dword(dev, pos + 4, &sz);
198 pci_write_config_dword(dev, pos + 4, l);
199
200 l64 |= ((u64)l << 32);
201 sz64 |= ((u64)sz << 32);
202
203 sz64 = pci_size(l64, sz64, mask64);
204
205 if (!sz64)
206 goto fail;
207
208 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
209 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
210 pos);
211 goto fail;
212 }
213
214 if ((sizeof(resource_size_t) < 8) && l) {
215 /* Address above 32-bit boundary; disable the BAR */
216 pci_write_config_dword(dev, pos, 0);
217 pci_write_config_dword(dev, pos + 4, 0);
218 region.start = 0;
219 region.end = sz64;
220 pcibios_bus_to_resource(dev, res, ®ion);
221 } else {
222 region.start = l64;
223 region.end = l64 + sz64;
224 pcibios_bus_to_resource(dev, res, ®ion);
225 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
226 pos, res);
227 }
228 } else {
229 sz = pci_size(l, sz, mask);
230
231 if (!sz)
232 goto fail;
233
234 region.start = l;
235 region.end = l + sz;
236 pcibios_bus_to_resource(dev, res, ®ion);
237
238 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
239 }
240
241 out:
242 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
243 fail:
244 res->flags = 0;
245 goto out;
246}
247
248static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
249{
250 unsigned int pos, reg;
251
252 for (pos = 0; pos < howmany; pos++) {
253 struct resource *res = &dev->resource[pos];
254 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
255 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
256 }
257
258 if (rom) {
259 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
260 dev->rom_base_reg = rom;
261 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
262 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
263 IORESOURCE_SIZEALIGN;
264 __pci_read_base(dev, pci_bar_mem32, res, rom);
265 }
266}
267
268static void __devinit pci_read_bridge_io(struct pci_bus *child)
269{
270 struct pci_dev *dev = child->self;
271 u8 io_base_lo, io_limit_lo;
272 unsigned long base, limit;
273 struct pci_bus_region region;
274 struct resource *res, res2;
275
276 res = child->resource[0];
277 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
278 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
279 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
280 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
281
282 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
283 u16 io_base_hi, io_limit_hi;
284 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
285 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
286 base |= (io_base_hi << 16);
287 limit |= (io_limit_hi << 16);
288 }
289
290 if (base && base <= limit) {
291 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
292 res2.flags = res->flags;
293 region.start = base;
294 region.end = limit + 0xfff;
295 pcibios_bus_to_resource(dev, &res2, ®ion);
296 if (!res->start)
297 res->start = res2.start;
298 if (!res->end)
299 res->end = res2.end;
300 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
301 }
302}
303
304static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
305{
306 struct pci_dev *dev = child->self;
307 u16 mem_base_lo, mem_limit_lo;
308 unsigned long base, limit;
309 struct pci_bus_region region;
310 struct resource *res;
311
312 res = child->resource[1];
313 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
314 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
315 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
316 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
317 if (base && base <= limit) {
318 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
319 region.start = base;
320 region.end = limit + 0xfffff;
321 pcibios_bus_to_resource(dev, res, ®ion);
322 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
323 }
324}
325
326static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
327{
328 struct pci_dev *dev = child->self;
329 u16 mem_base_lo, mem_limit_lo;
330 unsigned long base, limit;
331 struct pci_bus_region region;
332 struct resource *res;
333
334 res = child->resource[2];
335 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
336 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
337 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
338 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
339
340 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
341 u32 mem_base_hi, mem_limit_hi;
342 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
343 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
344
345 /*
346 * Some bridges set the base > limit by default, and some
347 * (broken) BIOSes do not initialize them. If we find
348 * this, just assume they are not being used.
349 */
350 if (mem_base_hi <= mem_limit_hi) {
351#if BITS_PER_LONG == 64
352 base |= ((long) mem_base_hi) << 32;
353 limit |= ((long) mem_limit_hi) << 32;
354#else
355 if (mem_base_hi || mem_limit_hi) {
356 dev_err(&dev->dev, "can't handle 64-bit "
357 "address space for bridge\n");
358 return;
359 }
360#endif
361 }
362 }
363 if (base && base <= limit) {
364 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
365 IORESOURCE_MEM | IORESOURCE_PREFETCH;
366 if (res->flags & PCI_PREF_RANGE_TYPE_64)
367 res->flags |= IORESOURCE_MEM_64;
368 region.start = base;
369 region.end = limit + 0xfffff;
370 pcibios_bus_to_resource(dev, res, ®ion);
371 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
372 }
373}
374
375void __devinit pci_read_bridge_bases(struct pci_bus *child)
376{
377 struct pci_dev *dev = child->self;
378 struct resource *res;
379 int i;
380
381 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
382 return;
383
384 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
385 child->secondary, child->subordinate,
386 dev->transparent ? " (subtractive decode)" : "");
387
388 pci_bus_remove_resources(child);
389 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
390 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
391
392 pci_read_bridge_io(child);
393 pci_read_bridge_mmio(child);
394 pci_read_bridge_mmio_pref(child);
395
396 if (dev->transparent) {
397 pci_bus_for_each_resource(child->parent, res, i) {
398 if (res) {
399 pci_bus_add_resource(child, res,
400 PCI_SUBTRACTIVE_DECODE);
401 dev_printk(KERN_DEBUG, &dev->dev,
402 " bridge window %pR (subtractive decode)\n",
403 res);
404 }
405 }
406 }
407}
408
409static struct pci_bus * pci_alloc_bus(void)
410{
411 struct pci_bus *b;
412
413 b = kzalloc(sizeof(*b), GFP_KERNEL);
414 if (b) {
415 INIT_LIST_HEAD(&b->node);
416 INIT_LIST_HEAD(&b->children);
417 INIT_LIST_HEAD(&b->devices);
418 INIT_LIST_HEAD(&b->slots);
419 INIT_LIST_HEAD(&b->resources);
420 b->max_bus_speed = PCI_SPEED_UNKNOWN;
421 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
422 }
423 return b;
424}
425
426static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
427{
428 struct pci_host_bridge *bridge;
429
430 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
431 if (bridge) {
432 INIT_LIST_HEAD(&bridge->windows);
433 bridge->bus = b;
434 }
435
436 return bridge;
437}
438
439static unsigned char pcix_bus_speed[] = {
440 PCI_SPEED_UNKNOWN, /* 0 */
441 PCI_SPEED_66MHz_PCIX, /* 1 */
442 PCI_SPEED_100MHz_PCIX, /* 2 */
443 PCI_SPEED_133MHz_PCIX, /* 3 */
444 PCI_SPEED_UNKNOWN, /* 4 */
445 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
446 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
447 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
448 PCI_SPEED_UNKNOWN, /* 8 */
449 PCI_SPEED_66MHz_PCIX_266, /* 9 */
450 PCI_SPEED_100MHz_PCIX_266, /* A */
451 PCI_SPEED_133MHz_PCIX_266, /* B */
452 PCI_SPEED_UNKNOWN, /* C */
453 PCI_SPEED_66MHz_PCIX_533, /* D */
454 PCI_SPEED_100MHz_PCIX_533, /* E */
455 PCI_SPEED_133MHz_PCIX_533 /* F */
456};
457
458static unsigned char pcie_link_speed[] = {
459 PCI_SPEED_UNKNOWN, /* 0 */
460 PCIE_SPEED_2_5GT, /* 1 */
461 PCIE_SPEED_5_0GT, /* 2 */
462 PCIE_SPEED_8_0GT, /* 3 */
463 PCI_SPEED_UNKNOWN, /* 4 */
464 PCI_SPEED_UNKNOWN, /* 5 */
465 PCI_SPEED_UNKNOWN, /* 6 */
466 PCI_SPEED_UNKNOWN, /* 7 */
467 PCI_SPEED_UNKNOWN, /* 8 */
468 PCI_SPEED_UNKNOWN, /* 9 */
469 PCI_SPEED_UNKNOWN, /* A */
470 PCI_SPEED_UNKNOWN, /* B */
471 PCI_SPEED_UNKNOWN, /* C */
472 PCI_SPEED_UNKNOWN, /* D */
473 PCI_SPEED_UNKNOWN, /* E */
474 PCI_SPEED_UNKNOWN /* F */
475};
476
477void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
478{
479 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
480}
481EXPORT_SYMBOL_GPL(pcie_update_link_speed);
482
483static unsigned char agp_speeds[] = {
484 AGP_UNKNOWN,
485 AGP_1X,
486 AGP_2X,
487 AGP_4X,
488 AGP_8X
489};
490
491static enum pci_bus_speed agp_speed(int agp3, int agpstat)
492{
493 int index = 0;
494
495 if (agpstat & 4)
496 index = 3;
497 else if (agpstat & 2)
498 index = 2;
499 else if (agpstat & 1)
500 index = 1;
501 else
502 goto out;
503
504 if (agp3) {
505 index += 2;
506 if (index == 5)
507 index = 0;
508 }
509
510 out:
511 return agp_speeds[index];
512}
513
514
515static void pci_set_bus_speed(struct pci_bus *bus)
516{
517 struct pci_dev *bridge = bus->self;
518 int pos;
519
520 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
521 if (!pos)
522 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
523 if (pos) {
524 u32 agpstat, agpcmd;
525
526 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
527 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
528
529 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
530 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
531 }
532
533 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
534 if (pos) {
535 u16 status;
536 enum pci_bus_speed max;
537 pci_read_config_word(bridge, pos + 2, &status);
538
539 if (status & 0x8000) {
540 max = PCI_SPEED_133MHz_PCIX_533;
541 } else if (status & 0x4000) {
542 max = PCI_SPEED_133MHz_PCIX_266;
543 } else if (status & 0x0002) {
544 if (((status >> 12) & 0x3) == 2) {
545 max = PCI_SPEED_133MHz_PCIX_ECC;
546 } else {
547 max = PCI_SPEED_133MHz_PCIX;
548 }
549 } else {
550 max = PCI_SPEED_66MHz_PCIX;
551 }
552
553 bus->max_bus_speed = max;
554 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
555
556 return;
557 }
558
559 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
560 if (pos) {
561 u32 linkcap;
562 u16 linksta;
563
564 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
565 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
566
567 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
568 pcie_update_link_speed(bus, linksta);
569 }
570}
571
572
573static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
574 struct pci_dev *bridge, int busnr)
575{
576 struct pci_bus *child;
577 int i;
578
579 /*
580 * Allocate a new bus, and inherit stuff from the parent..
581 */
582 child = pci_alloc_bus();
583 if (!child)
584 return NULL;
585
586 child->parent = parent;
587 child->ops = parent->ops;
588 child->sysdata = parent->sysdata;
589 child->bus_flags = parent->bus_flags;
590
591 /* initialize some portions of the bus device, but don't register it
592 * now as the parent is not properly set up yet. This device will get
593 * registered later in pci_bus_add_devices()
594 */
595 child->dev.class = &pcibus_class;
596 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
597
598 /*
599 * Set up the primary, secondary and subordinate
600 * bus numbers.
601 */
602 child->number = child->secondary = busnr;
603 child->primary = parent->secondary;
604 child->subordinate = 0xff;
605
606 if (!bridge)
607 return child;
608
609 child->self = bridge;
610 child->bridge = get_device(&bridge->dev);
611 pci_set_bus_of_node(child);
612 pci_set_bus_speed(child);
613
614 /* Set up default resource pointers and names.. */
615 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
616 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
617 child->resource[i]->name = child->name;
618 }
619 bridge->subordinate = child;
620
621 return child;
622}
623
624struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
625{
626 struct pci_bus *child;
627
628 child = pci_alloc_child_bus(parent, dev, busnr);
629 if (child) {
630 down_write(&pci_bus_sem);
631 list_add_tail(&child->node, &parent->children);
632 up_write(&pci_bus_sem);
633 }
634 return child;
635}
636
637static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
638{
639 struct pci_bus *parent = child->parent;
640
641 /* Attempts to fix that up are really dangerous unless
642 we're going to re-assign all bus numbers. */
643 if (!pcibios_assign_all_busses())
644 return;
645
646 while (parent->parent && parent->subordinate < max) {
647 parent->subordinate = max;
648 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
649 parent = parent->parent;
650 }
651}
652
653/*
654 * If it's a bridge, configure it and scan the bus behind it.
655 * For CardBus bridges, we don't scan behind as the devices will
656 * be handled by the bridge driver itself.
657 *
658 * We need to process bridges in two passes -- first we scan those
659 * already configured by the BIOS and after we are done with all of
660 * them, we proceed to assigning numbers to the remaining buses in
661 * order to avoid overlaps between old and new bus numbers.
662 */
663int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
664{
665 struct pci_bus *child;
666 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
667 u32 buses, i, j = 0;
668 u16 bctl;
669 u8 primary, secondary, subordinate;
670 int broken = 0;
671
672 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
673 primary = buses & 0xFF;
674 secondary = (buses >> 8) & 0xFF;
675 subordinate = (buses >> 16) & 0xFF;
676
677 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
678 secondary, subordinate, pass);
679
680 if (!primary && (primary != bus->number) && secondary && subordinate) {
681 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
682 primary = bus->number;
683 }
684
685 /* Check if setup is sensible at all */
686 if (!pass &&
687 (primary != bus->number || secondary <= bus->number)) {
688 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
689 broken = 1;
690 }
691
692 /* Disable MasterAbortMode during probing to avoid reporting
693 of bus errors (in some architectures) */
694 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
695 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
696 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
697
698 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
699 !is_cardbus && !broken) {
700 unsigned int cmax;
701 /*
702 * Bus already configured by firmware, process it in the first
703 * pass and just note the configuration.
704 */
705 if (pass)
706 goto out;
707
708 /*
709 * If we already got to this bus through a different bridge,
710 * don't re-add it. This can happen with the i450NX chipset.
711 *
712 * However, we continue to descend down the hierarchy and
713 * scan remaining child buses.
714 */
715 child = pci_find_bus(pci_domain_nr(bus), secondary);
716 if (!child) {
717 child = pci_add_new_bus(bus, dev, secondary);
718 if (!child)
719 goto out;
720 child->primary = primary;
721 child->subordinate = subordinate;
722 child->bridge_ctl = bctl;
723 }
724
725 cmax = pci_scan_child_bus(child);
726 if (cmax > max)
727 max = cmax;
728 if (child->subordinate > max)
729 max = child->subordinate;
730 } else {
731 /*
732 * We need to assign a number to this bus which we always
733 * do in the second pass.
734 */
735 if (!pass) {
736 if (pcibios_assign_all_busses() || broken)
737 /* Temporarily disable forwarding of the
738 configuration cycles on all bridges in
739 this bus segment to avoid possible
740 conflicts in the second pass between two
741 bridges programmed with overlapping
742 bus ranges. */
743 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
744 buses & ~0xffffff);
745 goto out;
746 }
747
748 /* Clear errors */
749 pci_write_config_word(dev, PCI_STATUS, 0xffff);
750
751 /* Prevent assigning a bus number that already exists.
752 * This can happen when a bridge is hot-plugged, so in
753 * this case we only re-scan this bus. */
754 child = pci_find_bus(pci_domain_nr(bus), max+1);
755 if (!child) {
756 child = pci_add_new_bus(bus, dev, ++max);
757 if (!child)
758 goto out;
759 }
760 buses = (buses & 0xff000000)
761 | ((unsigned int)(child->primary) << 0)
762 | ((unsigned int)(child->secondary) << 8)
763 | ((unsigned int)(child->subordinate) << 16);
764
765 /*
766 * yenta.c forces a secondary latency timer of 176.
767 * Copy that behaviour here.
768 */
769 if (is_cardbus) {
770 buses &= ~0xff000000;
771 buses |= CARDBUS_LATENCY_TIMER << 24;
772 }
773
774 /*
775 * We need to blast all three values with a single write.
776 */
777 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
778
779 if (!is_cardbus) {
780 child->bridge_ctl = bctl;
781 /*
782 * Adjust subordinate busnr in parent buses.
783 * We do this before scanning for children because
784 * some devices may not be detected if the bios
785 * was lazy.
786 */
787 pci_fixup_parent_subordinate_busnr(child, max);
788 /* Now we can scan all subordinate buses... */
789 max = pci_scan_child_bus(child);
790 /*
791 * now fix it up again since we have found
792 * the real value of max.
793 */
794 pci_fixup_parent_subordinate_busnr(child, max);
795 } else {
796 /*
797 * For CardBus bridges, we leave 4 bus numbers
798 * as cards with a PCI-to-PCI bridge can be
799 * inserted later.
800 */
801 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
802 struct pci_bus *parent = bus;
803 if (pci_find_bus(pci_domain_nr(bus),
804 max+i+1))
805 break;
806 while (parent->parent) {
807 if ((!pcibios_assign_all_busses()) &&
808 (parent->subordinate > max) &&
809 (parent->subordinate <= max+i)) {
810 j = 1;
811 }
812 parent = parent->parent;
813 }
814 if (j) {
815 /*
816 * Often, there are two cardbus bridges
817 * -- try to leave one valid bus number
818 * for each one.
819 */
820 i /= 2;
821 break;
822 }
823 }
824 max += i;
825 pci_fixup_parent_subordinate_busnr(child, max);
826 }
827 /*
828 * Set the subordinate bus number to its real value.
829 */
830 child->subordinate = max;
831 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
832 }
833
834 sprintf(child->name,
835 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
836 pci_domain_nr(bus), child->number);
837
838 /* Has only triggered on CardBus, fixup is in yenta_socket */
839 while (bus->parent) {
840 if ((child->subordinate > bus->subordinate) ||
841 (child->number > bus->subordinate) ||
842 (child->number < bus->number) ||
843 (child->subordinate < bus->number)) {
844 dev_info(&child->dev, "[bus %02x-%02x] %s "
845 "hidden behind%s bridge %s [bus %02x-%02x]\n",
846 child->number, child->subordinate,
847 (bus->number > child->subordinate &&
848 bus->subordinate < child->number) ?
849 "wholly" : "partially",
850 bus->self->transparent ? " transparent" : "",
851 dev_name(&bus->dev),
852 bus->number, bus->subordinate);
853 }
854 bus = bus->parent;
855 }
856
857out:
858 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
859
860 return max;
861}
862
863/*
864 * Read interrupt line and base address registers.
865 * The architecture-dependent code can tweak these, of course.
866 */
867static void pci_read_irq(struct pci_dev *dev)
868{
869 unsigned char irq;
870
871 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
872 dev->pin = irq;
873 if (irq)
874 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
875 dev->irq = irq;
876}
877
878void set_pcie_port_type(struct pci_dev *pdev)
879{
880 int pos;
881 u16 reg16;
882
883 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
884 if (!pos)
885 return;
886 pdev->is_pcie = 1;
887 pdev->pcie_cap = pos;
888 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
889 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
890 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
891 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
892}
893
894void set_pcie_hotplug_bridge(struct pci_dev *pdev)
895{
896 int pos;
897 u16 reg16;
898 u32 reg32;
899
900 pos = pci_pcie_cap(pdev);
901 if (!pos)
902 return;
903 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
904 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
905 return;
906 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);
907 if (reg32 & PCI_EXP_SLTCAP_HPC)
908 pdev->is_hotplug_bridge = 1;
909}
910
911#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
912
913/**
914 * pci_setup_device - fill in class and map information of a device
915 * @dev: the device structure to fill
916 *
917 * Initialize the device structure with information about the device's
918 * vendor,class,memory and IO-space addresses,IRQ lines etc.
919 * Called at initialisation of the PCI subsystem and by CardBus services.
920 * Returns 0 on success and negative if unknown type of device (not normal,
921 * bridge or CardBus).
922 */
923int pci_setup_device(struct pci_dev *dev)
924{
925 u32 class;
926 u8 hdr_type;
927 struct pci_slot *slot;
928 int pos = 0;
929 struct pci_bus_region region;
930 struct resource *res;
931
932 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
933 return -EIO;
934
935 dev->sysdata = dev->bus->sysdata;
936 dev->dev.parent = dev->bus->bridge;
937 dev->dev.bus = &pci_bus_type;
938 dev->hdr_type = hdr_type & 0x7f;
939 dev->multifunction = !!(hdr_type & 0x80);
940 dev->error_state = pci_channel_io_normal;
941 set_pcie_port_type(dev);
942
943 list_for_each_entry(slot, &dev->bus->slots, list)
944 if (PCI_SLOT(dev->devfn) == slot->number)
945 dev->slot = slot;
946
947 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
948 set this higher, assuming the system even supports it. */
949 dev->dma_mask = 0xffffffff;
950
951 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
952 dev->bus->number, PCI_SLOT(dev->devfn),
953 PCI_FUNC(dev->devfn));
954
955 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
956 dev->revision = class & 0xff;
957 dev->class = class >> 8; /* upper 3 bytes */
958
959 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
960 dev->vendor, dev->device, dev->hdr_type, dev->class);
961
962 /* need to have dev->class ready */
963 dev->cfg_size = pci_cfg_space_size(dev);
964
965 /* "Unknown power state" */
966 dev->current_state = PCI_UNKNOWN;
967
968 /* Early fixups, before probing the BARs */
969 pci_fixup_device(pci_fixup_early, dev);
970 /* device class may be changed after fixup */
971 class = dev->class >> 8;
972
973 switch (dev->hdr_type) { /* header type */
974 case PCI_HEADER_TYPE_NORMAL: /* standard header */
975 if (class == PCI_CLASS_BRIDGE_PCI)
976 goto bad;
977 pci_read_irq(dev);
978 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
979 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
980 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
981
982 /*
983 * Do the ugly legacy mode stuff here rather than broken chip
984 * quirk code. Legacy mode ATA controllers have fixed
985 * addresses. These are not always echoed in BAR0-3, and
986 * BAR0-3 in a few cases contain junk!
987 */
988 if (class == PCI_CLASS_STORAGE_IDE) {
989 u8 progif;
990 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
991 if ((progif & 1) == 0) {
992 region.start = 0x1F0;
993 region.end = 0x1F7;
994 res = &dev->resource[0];
995 res->flags = LEGACY_IO_RESOURCE;
996 pcibios_bus_to_resource(dev, res, ®ion);
997 region.start = 0x3F6;
998 region.end = 0x3F6;
999 res = &dev->resource[1];
1000 res->flags = LEGACY_IO_RESOURCE;
1001 pcibios_bus_to_resource(dev, res, ®ion);
1002 }
1003 if ((progif & 4) == 0) {
1004 region.start = 0x170;
1005 region.end = 0x177;
1006 res = &dev->resource[2];
1007 res->flags = LEGACY_IO_RESOURCE;
1008 pcibios_bus_to_resource(dev, res, ®ion);
1009 region.start = 0x376;
1010 region.end = 0x376;
1011 res = &dev->resource[3];
1012 res->flags = LEGACY_IO_RESOURCE;
1013 pcibios_bus_to_resource(dev, res, ®ion);
1014 }
1015 }
1016 break;
1017
1018 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1019 if (class != PCI_CLASS_BRIDGE_PCI)
1020 goto bad;
1021 /* The PCI-to-PCI bridge spec requires that subtractive
1022 decoding (i.e. transparent) bridge must have programming
1023 interface code of 0x01. */
1024 pci_read_irq(dev);
1025 dev->transparent = ((dev->class & 0xff) == 1);
1026 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1027 set_pcie_hotplug_bridge(dev);
1028 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1029 if (pos) {
1030 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1031 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1032 }
1033 break;
1034
1035 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1036 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1037 goto bad;
1038 pci_read_irq(dev);
1039 pci_read_bases(dev, 1, 0);
1040 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1041 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1042 break;
1043
1044 default: /* unknown header */
1045 dev_err(&dev->dev, "unknown header type %02x, "
1046 "ignoring device\n", dev->hdr_type);
1047 return -EIO;
1048
1049 bad:
1050 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header "
1051 "type %02x)\n", dev->class, dev->hdr_type);
1052 dev->class = PCI_CLASS_NOT_DEFINED;
1053 }
1054
1055 /* We found a fine healthy device, go go go... */
1056 return 0;
1057}
1058
1059static void pci_release_capabilities(struct pci_dev *dev)
1060{
1061 pci_vpd_release(dev);
1062 pci_iov_release(dev);
1063 pci_free_cap_save_buffers(dev);
1064}
1065
1066/**
1067 * pci_release_dev - free a pci device structure when all users of it are finished.
1068 * @dev: device that's been disconnected
1069 *
1070 * Will be called only by the device core when all users of this pci device are
1071 * done.
1072 */
1073static void pci_release_dev(struct device *dev)
1074{
1075 struct pci_dev *pci_dev;
1076
1077 pci_dev = to_pci_dev(dev);
1078 pci_release_capabilities(pci_dev);
1079 pci_release_of_node(pci_dev);
1080 kfree(pci_dev);
1081}
1082
1083/**
1084 * pci_cfg_space_size - get the configuration space size of the PCI device.
1085 * @dev: PCI device
1086 *
1087 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1088 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1089 * access it. Maybe we don't have a way to generate extended config space
1090 * accesses, or the device is behind a reverse Express bridge. So we try
1091 * reading the dword at 0x100 which must either be 0 or a valid extended
1092 * capability header.
1093 */
1094int pci_cfg_space_size_ext(struct pci_dev *dev)
1095{
1096 u32 status;
1097 int pos = PCI_CFG_SPACE_SIZE;
1098
1099 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1100 goto fail;
1101 if (status == 0xffffffff)
1102 goto fail;
1103
1104 return PCI_CFG_SPACE_EXP_SIZE;
1105
1106 fail:
1107 return PCI_CFG_SPACE_SIZE;
1108}
1109
1110int pci_cfg_space_size(struct pci_dev *dev)
1111{
1112 int pos;
1113 u32 status;
1114 u16 class;
1115
1116 class = dev->class >> 8;
1117 if (class == PCI_CLASS_BRIDGE_HOST)
1118 return pci_cfg_space_size_ext(dev);
1119
1120 pos = pci_pcie_cap(dev);
1121 if (!pos) {
1122 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1123 if (!pos)
1124 goto fail;
1125
1126 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1127 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1128 goto fail;
1129 }
1130
1131 return pci_cfg_space_size_ext(dev);
1132
1133 fail:
1134 return PCI_CFG_SPACE_SIZE;
1135}
1136
1137static void pci_release_bus_bridge_dev(struct device *dev)
1138{
1139 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
1140
1141 if (bridge->release_fn)
1142 bridge->release_fn(bridge);
1143
1144 pci_free_resource_list(&bridge->windows);
1145
1146 kfree(bridge);
1147}
1148
1149struct pci_dev *alloc_pci_dev(void)
1150{
1151 struct pci_dev *dev;
1152
1153 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1154 if (!dev)
1155 return NULL;
1156
1157 INIT_LIST_HEAD(&dev->bus_list);
1158
1159 return dev;
1160}
1161EXPORT_SYMBOL(alloc_pci_dev);
1162
1163bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1164 int crs_timeout)
1165{
1166 int delay = 1;
1167
1168 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1169 return false;
1170
1171 /* some broken boards return 0 or ~0 if a slot is empty: */
1172 if (*l == 0xffffffff || *l == 0x00000000 ||
1173 *l == 0x0000ffff || *l == 0xffff0000)
1174 return false;
1175
1176 /* Configuration request Retry Status */
1177 while (*l == 0xffff0001) {
1178 if (!crs_timeout)
1179 return false;
1180
1181 msleep(delay);
1182 delay *= 2;
1183 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1184 return false;
1185 /* Card hasn't responded in 60 seconds? Must be stuck. */
1186 if (delay > crs_timeout) {
1187 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1188 "responding\n", pci_domain_nr(bus),
1189 bus->number, PCI_SLOT(devfn),
1190 PCI_FUNC(devfn));
1191 return false;
1192 }
1193 }
1194
1195 return true;
1196}
1197EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1198
1199/*
1200 * Read the config data for a PCI device, sanity-check it
1201 * and fill in the dev structure...
1202 */
1203static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1204{
1205 struct pci_dev *dev;
1206 u32 l;
1207
1208 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1209 return NULL;
1210
1211 dev = alloc_pci_dev();
1212 if (!dev)
1213 return NULL;
1214
1215 dev->bus = bus;
1216 dev->devfn = devfn;
1217 dev->vendor = l & 0xffff;
1218 dev->device = (l >> 16) & 0xffff;
1219
1220 pci_set_of_node(dev);
1221
1222 if (pci_setup_device(dev)) {
1223 kfree(dev);
1224 return NULL;
1225 }
1226
1227 return dev;
1228}
1229
1230static void pci_init_capabilities(struct pci_dev *dev)
1231{
1232 /* MSI/MSI-X list */
1233 pci_msi_init_pci_dev(dev);
1234
1235 /* Buffers for saving PCIe and PCI-X capabilities */
1236 pci_allocate_cap_save_buffers(dev);
1237
1238 /* Power Management */
1239 pci_pm_init(dev);
1240 platform_pci_wakeup_init(dev);
1241
1242 /* Vital Product Data */
1243 pci_vpd_pci22_init(dev);
1244
1245 /* Alternative Routing-ID Forwarding */
1246 pci_enable_ari(dev);
1247
1248 /* Single Root I/O Virtualization */
1249 pci_iov_init(dev);
1250
1251 /* Enable ACS P2P upstream forwarding */
1252 pci_enable_acs(dev);
1253}
1254
1255void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1256{
1257 device_initialize(&dev->dev);
1258 dev->dev.release = pci_release_dev;
1259 pci_dev_get(dev);
1260
1261 dev->dev.dma_mask = &dev->dma_mask;
1262 dev->dev.dma_parms = &dev->dma_parms;
1263 dev->dev.coherent_dma_mask = 0xffffffffull;
1264
1265 pci_set_dma_max_seg_size(dev, 65536);
1266 pci_set_dma_seg_boundary(dev, 0xffffffff);
1267
1268 /* Fix up broken headers */
1269 pci_fixup_device(pci_fixup_header, dev);
1270
1271 /* moved out from quirk header fixup code */
1272 pci_reassigndev_resource_alignment(dev);
1273
1274 /* Clear the state_saved flag. */
1275 dev->state_saved = false;
1276
1277 /* Initialize various capabilities */
1278 pci_init_capabilities(dev);
1279
1280 /*
1281 * Add the device to our list of discovered devices
1282 * and the bus list for fixup functions, etc.
1283 */
1284 down_write(&pci_bus_sem);
1285 list_add_tail(&dev->bus_list, &bus->devices);
1286 up_write(&pci_bus_sem);
1287}
1288
1289struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1290{
1291 struct pci_dev *dev;
1292
1293 dev = pci_get_slot(bus, devfn);
1294 if (dev) {
1295 pci_dev_put(dev);
1296 return dev;
1297 }
1298
1299 dev = pci_scan_device(bus, devfn);
1300 if (!dev)
1301 return NULL;
1302
1303 pci_device_add(dev, bus);
1304
1305 return dev;
1306}
1307EXPORT_SYMBOL(pci_scan_single_device);
1308
1309static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1310{
1311 u16 cap;
1312 unsigned pos, next_fn;
1313
1314 if (!dev)
1315 return 0;
1316
1317 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1318 if (!pos)
1319 return 0;
1320 pci_read_config_word(dev, pos + 4, &cap);
1321 next_fn = cap >> 8;
1322 if (next_fn <= fn)
1323 return 0;
1324 return next_fn;
1325}
1326
1327static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1328{
1329 return (fn + 1) % 8;
1330}
1331
1332static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1333{
1334 return 0;
1335}
1336
1337static int only_one_child(struct pci_bus *bus)
1338{
1339 struct pci_dev *parent = bus->self;
1340
1341 if (!parent || !pci_is_pcie(parent))
1342 return 0;
1343 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
1344 return 1;
1345 if (parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM &&
1346 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1347 return 1;
1348 return 0;
1349}
1350
1351/**
1352 * pci_scan_slot - scan a PCI slot on a bus for devices.
1353 * @bus: PCI bus to scan
1354 * @devfn: slot number to scan (must have zero function.)
1355 *
1356 * Scan a PCI slot on the specified PCI bus for devices, adding
1357 * discovered devices to the @bus->devices list. New devices
1358 * will not have is_added set.
1359 *
1360 * Returns the number of new devices found.
1361 */
1362int pci_scan_slot(struct pci_bus *bus, int devfn)
1363{
1364 unsigned fn, nr = 0;
1365 struct pci_dev *dev;
1366 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1367
1368 if (only_one_child(bus) && (devfn > 0))
1369 return 0; /* Already scanned the entire slot */
1370
1371 dev = pci_scan_single_device(bus, devfn);
1372 if (!dev)
1373 return 0;
1374 if (!dev->is_added)
1375 nr++;
1376
1377 if (pci_ari_enabled(bus))
1378 next_fn = next_ari_fn;
1379 else if (dev->multifunction)
1380 next_fn = next_trad_fn;
1381
1382 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1383 dev = pci_scan_single_device(bus, devfn + fn);
1384 if (dev) {
1385 if (!dev->is_added)
1386 nr++;
1387 dev->multifunction = 1;
1388 }
1389 }
1390
1391 /* only one slot has pcie device */
1392 if (bus->self && nr)
1393 pcie_aspm_init_link_state(bus->self);
1394
1395 return nr;
1396}
1397
1398static int pcie_find_smpss(struct pci_dev *dev, void *data)
1399{
1400 u8 *smpss = data;
1401
1402 if (!pci_is_pcie(dev))
1403 return 0;
1404
1405 /* For PCIE hotplug enabled slots not connected directly to a
1406 * PCI-E root port, there can be problems when hotplugging
1407 * devices. This is due to the possibility of hotplugging a
1408 * device into the fabric with a smaller MPS that the devices
1409 * currently running have configured. Modifying the MPS on the
1410 * running devices could cause a fatal bus error due to an
1411 * incoming frame being larger than the newly configured MPS.
1412 * To work around this, the MPS for the entire fabric must be
1413 * set to the minimum size. Any devices hotplugged into this
1414 * fabric will have the minimum MPS set. If the PCI hotplug
1415 * slot is directly connected to the root port and there are not
1416 * other devices on the fabric (which seems to be the most
1417 * common case), then this is not an issue and MPS discovery
1418 * will occur as normal.
1419 */
1420 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1421 (dev->bus->self &&
1422 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
1423 *smpss = 0;
1424
1425 if (*smpss > dev->pcie_mpss)
1426 *smpss = dev->pcie_mpss;
1427
1428 return 0;
1429}
1430
1431static void pcie_write_mps(struct pci_dev *dev, int mps)
1432{
1433 int rc;
1434
1435 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1436 mps = 128 << dev->pcie_mpss;
1437
1438 if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self)
1439 /* For "Performance", the assumption is made that
1440 * downstream communication will never be larger than
1441 * the MRRS. So, the MPS only needs to be configured
1442 * for the upstream communication. This being the case,
1443 * walk from the top down and set the MPS of the child
1444 * to that of the parent bus.
1445 *
1446 * Configure the device MPS with the smaller of the
1447 * device MPSS or the bridge MPS (which is assumed to be
1448 * properly configured at this point to the largest
1449 * allowable MPS based on its parent bus).
1450 */
1451 mps = min(mps, pcie_get_mps(dev->bus->self));
1452 }
1453
1454 rc = pcie_set_mps(dev, mps);
1455 if (rc)
1456 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1457}
1458
1459static void pcie_write_mrrs(struct pci_dev *dev)
1460{
1461 int rc, mrrs;
1462
1463 /* In the "safe" case, do not configure the MRRS. There appear to be
1464 * issues with setting MRRS to 0 on a number of devices.
1465 */
1466 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1467 return;
1468
1469 /* For Max performance, the MRRS must be set to the largest supported
1470 * value. However, it cannot be configured larger than the MPS the
1471 * device or the bus can support. This should already be properly
1472 * configured by a prior call to pcie_write_mps.
1473 */
1474 mrrs = pcie_get_mps(dev);
1475
1476 /* MRRS is a R/W register. Invalid values can be written, but a
1477 * subsequent read will verify if the value is acceptable or not.
1478 * If the MRRS value provided is not acceptable (e.g., too large),
1479 * shrink the value until it is acceptable to the HW.
1480 */
1481 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1482 rc = pcie_set_readrq(dev, mrrs);
1483 if (!rc)
1484 break;
1485
1486 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1487 mrrs /= 2;
1488 }
1489
1490 if (mrrs < 128)
1491 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1492 "safe value. If problems are experienced, try running "
1493 "with pci=pcie_bus_safe.\n");
1494}
1495
1496static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1497{
1498 int mps, orig_mps;
1499
1500 if (!pci_is_pcie(dev))
1501 return 0;
1502
1503 mps = 128 << *(u8 *)data;
1504 orig_mps = pcie_get_mps(dev);
1505
1506 pcie_write_mps(dev, mps);
1507 pcie_write_mrrs(dev);
1508
1509 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1510 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1511 orig_mps, pcie_get_readrq(dev));
1512
1513 return 0;
1514}
1515
1516/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1517 * parents then children fashion. If this changes, then this code will not
1518 * work as designed.
1519 */
1520void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1521{
1522 u8 smpss;
1523
1524 if (!pci_is_pcie(bus->self))
1525 return;
1526
1527 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1528 return;
1529
1530 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1531 * to be aware to the MPS of the destination. To work around this,
1532 * simply force the MPS of the entire system to the smallest possible.
1533 */
1534 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1535 smpss = 0;
1536
1537 if (pcie_bus_config == PCIE_BUS_SAFE) {
1538 smpss = mpss;
1539
1540 pcie_find_smpss(bus->self, &smpss);
1541 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1542 }
1543
1544 pcie_bus_configure_set(bus->self, &smpss);
1545 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1546}
1547EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1548
1549unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1550{
1551 unsigned int devfn, pass, max = bus->secondary;
1552 struct pci_dev *dev;
1553
1554 dev_dbg(&bus->dev, "scanning bus\n");
1555
1556 /* Go find them, Rover! */
1557 for (devfn = 0; devfn < 0x100; devfn += 8)
1558 pci_scan_slot(bus, devfn);
1559
1560 /* Reserve buses for SR-IOV capability. */
1561 max += pci_iov_bus_range(bus);
1562
1563 /*
1564 * After performing arch-dependent fixup of the bus, look behind
1565 * all PCI-to-PCI bridges on this bus.
1566 */
1567 if (!bus->is_added) {
1568 dev_dbg(&bus->dev, "fixups for bus\n");
1569 pcibios_fixup_bus(bus);
1570 if (pci_is_root_bus(bus))
1571 bus->is_added = 1;
1572 }
1573
1574 for (pass=0; pass < 2; pass++)
1575 list_for_each_entry(dev, &bus->devices, bus_list) {
1576 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1577 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1578 max = pci_scan_bridge(bus, dev, max, pass);
1579 }
1580
1581 /*
1582 * We've scanned the bus and so we know all about what's on
1583 * the other side of any bridges that may be on this bus plus
1584 * any devices.
1585 *
1586 * Return how far we've got finding sub-buses.
1587 */
1588 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1589 return max;
1590}
1591
1592struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1593 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1594{
1595 int error;
1596 struct pci_host_bridge *bridge;
1597 struct pci_bus *b, *b2;
1598 struct pci_host_bridge_window *window, *n;
1599 struct resource *res;
1600 resource_size_t offset;
1601 char bus_addr[64];
1602 char *fmt;
1603
1604
1605 b = pci_alloc_bus();
1606 if (!b)
1607 return NULL;
1608
1609 b->sysdata = sysdata;
1610 b->ops = ops;
1611 b2 = pci_find_bus(pci_domain_nr(b), bus);
1612 if (b2) {
1613 /* If we already got to this bus through a different bridge, ignore it */
1614 dev_dbg(&b2->dev, "bus already known\n");
1615 goto err_out;
1616 }
1617
1618 bridge = pci_alloc_host_bridge(b);
1619 if (!bridge)
1620 goto err_out;
1621
1622 bridge->dev.parent = parent;
1623 bridge->dev.release = pci_release_bus_bridge_dev;
1624 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1625 error = device_register(&bridge->dev);
1626 if (error)
1627 goto bridge_dev_reg_err;
1628 b->bridge = get_device(&bridge->dev);
1629 device_enable_async_suspend(b->bridge);
1630 pci_set_bus_of_node(b);
1631
1632 if (!parent)
1633 set_dev_node(b->bridge, pcibus_to_node(b));
1634
1635 b->dev.class = &pcibus_class;
1636 b->dev.parent = b->bridge;
1637 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1638 error = device_register(&b->dev);
1639 if (error)
1640 goto class_dev_reg_err;
1641
1642 /* Create legacy_io and legacy_mem files for this bus */
1643 pci_create_legacy_files(b);
1644
1645 b->number = b->secondary = bus;
1646
1647 if (parent)
1648 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1649 else
1650 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1651
1652 /* Add initial resources to the bus */
1653 list_for_each_entry_safe(window, n, resources, list) {
1654 list_move_tail(&window->list, &bridge->windows);
1655 res = window->res;
1656 offset = window->offset;
1657 pci_bus_add_resource(b, res, 0);
1658 if (offset) {
1659 if (resource_type(res) == IORESOURCE_IO)
1660 fmt = " (bus address [%#06llx-%#06llx])";
1661 else
1662 fmt = " (bus address [%#010llx-%#010llx])";
1663 snprintf(bus_addr, sizeof(bus_addr), fmt,
1664 (unsigned long long) (res->start - offset),
1665 (unsigned long long) (res->end - offset));
1666 } else
1667 bus_addr[0] = '\0';
1668 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
1669 }
1670
1671 down_write(&pci_bus_sem);
1672 list_add_tail(&b->node, &pci_root_buses);
1673 up_write(&pci_bus_sem);
1674
1675 return b;
1676
1677class_dev_reg_err:
1678 put_device(&bridge->dev);
1679 device_unregister(&bridge->dev);
1680bridge_dev_reg_err:
1681 kfree(bridge);
1682err_out:
1683 kfree(b);
1684 return NULL;
1685}
1686
1687struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
1688 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1689{
1690 struct pci_bus *b;
1691
1692 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1693 if (!b)
1694 return NULL;
1695
1696 b->subordinate = pci_scan_child_bus(b);
1697 pci_bus_add_devices(b);
1698 return b;
1699}
1700EXPORT_SYMBOL(pci_scan_root_bus);
1701
1702/* Deprecated; use pci_scan_root_bus() instead */
1703struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1704 int bus, struct pci_ops *ops, void *sysdata)
1705{
1706 LIST_HEAD(resources);
1707 struct pci_bus *b;
1708
1709 pci_add_resource(&resources, &ioport_resource);
1710 pci_add_resource(&resources, &iomem_resource);
1711 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
1712 if (b)
1713 b->subordinate = pci_scan_child_bus(b);
1714 else
1715 pci_free_resource_list(&resources);
1716 return b;
1717}
1718EXPORT_SYMBOL(pci_scan_bus_parented);
1719
1720struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
1721 void *sysdata)
1722{
1723 LIST_HEAD(resources);
1724 struct pci_bus *b;
1725
1726 pci_add_resource(&resources, &ioport_resource);
1727 pci_add_resource(&resources, &iomem_resource);
1728 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1729 if (b) {
1730 b->subordinate = pci_scan_child_bus(b);
1731 pci_bus_add_devices(b);
1732 } else {
1733 pci_free_resource_list(&resources);
1734 }
1735 return b;
1736}
1737EXPORT_SYMBOL(pci_scan_bus);
1738
1739#ifdef CONFIG_HOTPLUG
1740/**
1741 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
1742 * @bridge: PCI bridge for the bus to scan
1743 *
1744 * Scan a PCI bus and child buses for new devices, add them,
1745 * and enable them, resizing bridge mmio/io resource if necessary
1746 * and possible. The caller must ensure the child devices are already
1747 * removed for resizing to occur.
1748 *
1749 * Returns the max number of subordinate bus discovered.
1750 */
1751unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
1752{
1753 unsigned int max;
1754 struct pci_bus *bus = bridge->subordinate;
1755
1756 max = pci_scan_child_bus(bus);
1757
1758 pci_assign_unassigned_bridge_resources(bridge);
1759
1760 pci_bus_add_devices(bus);
1761
1762 return max;
1763}
1764
1765EXPORT_SYMBOL(pci_add_new_bus);
1766EXPORT_SYMBOL(pci_scan_slot);
1767EXPORT_SYMBOL(pci_scan_bridge);
1768EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1769#endif
1770
1771static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1772{
1773 const struct pci_dev *a = to_pci_dev(d_a);
1774 const struct pci_dev *b = to_pci_dev(d_b);
1775
1776 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1777 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1778
1779 if (a->bus->number < b->bus->number) return -1;
1780 else if (a->bus->number > b->bus->number) return 1;
1781
1782 if (a->devfn < b->devfn) return -1;
1783 else if (a->devfn > b->devfn) return 1;
1784
1785 return 0;
1786}
1787
1788void __init pci_sort_breadthfirst(void)
1789{
1790 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1791}