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1/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
12#include <linux/pci-aspm.h>
13#include "pci.h"
14
15#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16#define CARDBUS_RESERVE_BUSNR 3
17
18/* Ugh. Need to stop exporting this to modules. */
19LIST_HEAD(pci_root_buses);
20EXPORT_SYMBOL(pci_root_buses);
21
22
23static int find_anything(struct device *dev, void *data)
24{
25 return 1;
26}
27
28/*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33int no_pci_devices(void)
34{
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42}
43EXPORT_SYMBOL(no_pci_devices);
44
45/*
46 * PCI Bus Class
47 */
48static void release_pcibus_dev(struct device *dev)
49{
50 struct pci_bus *pci_bus = to_pci_bus(dev);
51
52 if (pci_bus->bridge)
53 put_device(pci_bus->bridge);
54 pci_bus_remove_resources(pci_bus);
55 pci_release_bus_of_node(pci_bus);
56 kfree(pci_bus);
57}
58
59static struct class pcibus_class = {
60 .name = "pci_bus",
61 .dev_release = &release_pcibus_dev,
62 .dev_attrs = pcibus_dev_attrs,
63};
64
65static int __init pcibus_class_init(void)
66{
67 return class_register(&pcibus_class);
68}
69postcore_initcall(pcibus_class_init);
70
71static u64 pci_size(u64 base, u64 maxbase, u64 mask)
72{
73 u64 size = mask & maxbase; /* Find the significant bits */
74 if (!size)
75 return 0;
76
77 /* Get the lowest of them to find the decode size, and
78 from that the extent. */
79 size = (size & ~(size-1)) - 1;
80
81 /* base == maxbase can be valid only if the BAR has
82 already been programmed with all 1s. */
83 if (base == maxbase && ((base | size) & mask) != mask)
84 return 0;
85
86 return size;
87}
88
89static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
90{
91 u32 mem_type;
92 unsigned long flags;
93
94 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
95 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
96 flags |= IORESOURCE_IO;
97 return flags;
98 }
99
100 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
101 flags |= IORESOURCE_MEM;
102 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
103 flags |= IORESOURCE_PREFETCH;
104
105 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
106 switch (mem_type) {
107 case PCI_BASE_ADDRESS_MEM_TYPE_32:
108 break;
109 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
110 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
111 break;
112 case PCI_BASE_ADDRESS_MEM_TYPE_64:
113 flags |= IORESOURCE_MEM_64;
114 break;
115 default:
116 dev_warn(&dev->dev,
117 "mem unknown type %x treated as 32-bit BAR\n",
118 mem_type);
119 break;
120 }
121 return flags;
122}
123
124/**
125 * pci_read_base - read a PCI BAR
126 * @dev: the PCI device
127 * @type: type of the BAR
128 * @res: resource buffer to be filled in
129 * @pos: BAR position in the config space
130 *
131 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
132 */
133int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
134 struct resource *res, unsigned int pos)
135{
136 u32 l, sz, mask;
137 u16 orig_cmd;
138
139 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
140
141 if (!dev->mmio_always_on) {
142 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
143 pci_write_config_word(dev, PCI_COMMAND,
144 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
145 }
146
147 res->name = pci_name(dev);
148
149 pci_read_config_dword(dev, pos, &l);
150 pci_write_config_dword(dev, pos, l | mask);
151 pci_read_config_dword(dev, pos, &sz);
152 pci_write_config_dword(dev, pos, l);
153
154 if (!dev->mmio_always_on)
155 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
156
157 /*
158 * All bits set in sz means the device isn't working properly.
159 * If the BAR isn't implemented, all bits must be 0. If it's a
160 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
161 * 1 must be clear.
162 */
163 if (!sz || sz == 0xffffffff)
164 goto fail;
165
166 /*
167 * I don't know how l can have all bits set. Copied from old code.
168 * Maybe it fixes a bug on some ancient platform.
169 */
170 if (l == 0xffffffff)
171 l = 0;
172
173 if (type == pci_bar_unknown) {
174 res->flags = decode_bar(dev, l);
175 res->flags |= IORESOURCE_SIZEALIGN;
176 if (res->flags & IORESOURCE_IO) {
177 l &= PCI_BASE_ADDRESS_IO_MASK;
178 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
179 } else {
180 l &= PCI_BASE_ADDRESS_MEM_MASK;
181 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
182 }
183 } else {
184 res->flags |= (l & IORESOURCE_ROM_ENABLE);
185 l &= PCI_ROM_ADDRESS_MASK;
186 mask = (u32)PCI_ROM_ADDRESS_MASK;
187 }
188
189 if (res->flags & IORESOURCE_MEM_64) {
190 u64 l64 = l;
191 u64 sz64 = sz;
192 u64 mask64 = mask | (u64)~0 << 32;
193
194 pci_read_config_dword(dev, pos + 4, &l);
195 pci_write_config_dword(dev, pos + 4, ~0);
196 pci_read_config_dword(dev, pos + 4, &sz);
197 pci_write_config_dword(dev, pos + 4, l);
198
199 l64 |= ((u64)l << 32);
200 sz64 |= ((u64)sz << 32);
201
202 sz64 = pci_size(l64, sz64, mask64);
203
204 if (!sz64)
205 goto fail;
206
207 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
208 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
209 pos);
210 goto fail;
211 }
212
213 if ((sizeof(resource_size_t) < 8) && l) {
214 /* Address above 32-bit boundary; disable the BAR */
215 pci_write_config_dword(dev, pos, 0);
216 pci_write_config_dword(dev, pos + 4, 0);
217 res->start = 0;
218 res->end = sz64;
219 } else {
220 res->start = l64;
221 res->end = l64 + sz64;
222 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
223 pos, res);
224 }
225 } else {
226 sz = pci_size(l, sz, mask);
227
228 if (!sz)
229 goto fail;
230
231 res->start = l;
232 res->end = l + sz;
233
234 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
235 }
236
237 out:
238 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
239 fail:
240 res->flags = 0;
241 goto out;
242}
243
244static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
245{
246 unsigned int pos, reg;
247
248 for (pos = 0; pos < howmany; pos++) {
249 struct resource *res = &dev->resource[pos];
250 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
251 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
252 }
253
254 if (rom) {
255 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
256 dev->rom_base_reg = rom;
257 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
258 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
259 IORESOURCE_SIZEALIGN;
260 __pci_read_base(dev, pci_bar_mem32, res, rom);
261 }
262}
263
264static void __devinit pci_read_bridge_io(struct pci_bus *child)
265{
266 struct pci_dev *dev = child->self;
267 u8 io_base_lo, io_limit_lo;
268 unsigned long base, limit;
269 struct resource *res;
270
271 res = child->resource[0];
272 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
273 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
274 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
275 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
276
277 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
278 u16 io_base_hi, io_limit_hi;
279 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
280 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
281 base |= (io_base_hi << 16);
282 limit |= (io_limit_hi << 16);
283 }
284
285 if (base && base <= limit) {
286 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
287 if (!res->start)
288 res->start = base;
289 if (!res->end)
290 res->end = limit + 0xfff;
291 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
292 }
293}
294
295static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
296{
297 struct pci_dev *dev = child->self;
298 u16 mem_base_lo, mem_limit_lo;
299 unsigned long base, limit;
300 struct resource *res;
301
302 res = child->resource[1];
303 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
304 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
305 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
306 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
307 if (base && base <= limit) {
308 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
309 res->start = base;
310 res->end = limit + 0xfffff;
311 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
312 }
313}
314
315static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
316{
317 struct pci_dev *dev = child->self;
318 u16 mem_base_lo, mem_limit_lo;
319 unsigned long base, limit;
320 struct resource *res;
321
322 res = child->resource[2];
323 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
324 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
325 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
326 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
327
328 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
329 u32 mem_base_hi, mem_limit_hi;
330 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
331 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
332
333 /*
334 * Some bridges set the base > limit by default, and some
335 * (broken) BIOSes do not initialize them. If we find
336 * this, just assume they are not being used.
337 */
338 if (mem_base_hi <= mem_limit_hi) {
339#if BITS_PER_LONG == 64
340 base |= ((long) mem_base_hi) << 32;
341 limit |= ((long) mem_limit_hi) << 32;
342#else
343 if (mem_base_hi || mem_limit_hi) {
344 dev_err(&dev->dev, "can't handle 64-bit "
345 "address space for bridge\n");
346 return;
347 }
348#endif
349 }
350 }
351 if (base && base <= limit) {
352 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
353 IORESOURCE_MEM | IORESOURCE_PREFETCH;
354 if (res->flags & PCI_PREF_RANGE_TYPE_64)
355 res->flags |= IORESOURCE_MEM_64;
356 res->start = base;
357 res->end = limit + 0xfffff;
358 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
359 }
360}
361
362void __devinit pci_read_bridge_bases(struct pci_bus *child)
363{
364 struct pci_dev *dev = child->self;
365 struct resource *res;
366 int i;
367
368 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
369 return;
370
371 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
372 child->secondary, child->subordinate,
373 dev->transparent ? " (subtractive decode)" : "");
374
375 pci_bus_remove_resources(child);
376 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
377 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
378
379 pci_read_bridge_io(child);
380 pci_read_bridge_mmio(child);
381 pci_read_bridge_mmio_pref(child);
382
383 if (dev->transparent) {
384 pci_bus_for_each_resource(child->parent, res, i) {
385 if (res) {
386 pci_bus_add_resource(child, res,
387 PCI_SUBTRACTIVE_DECODE);
388 dev_printk(KERN_DEBUG, &dev->dev,
389 " bridge window %pR (subtractive decode)\n",
390 res);
391 }
392 }
393 }
394}
395
396static struct pci_bus * pci_alloc_bus(void)
397{
398 struct pci_bus *b;
399
400 b = kzalloc(sizeof(*b), GFP_KERNEL);
401 if (b) {
402 INIT_LIST_HEAD(&b->node);
403 INIT_LIST_HEAD(&b->children);
404 INIT_LIST_HEAD(&b->devices);
405 INIT_LIST_HEAD(&b->slots);
406 INIT_LIST_HEAD(&b->resources);
407 b->max_bus_speed = PCI_SPEED_UNKNOWN;
408 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
409 }
410 return b;
411}
412
413static unsigned char pcix_bus_speed[] = {
414 PCI_SPEED_UNKNOWN, /* 0 */
415 PCI_SPEED_66MHz_PCIX, /* 1 */
416 PCI_SPEED_100MHz_PCIX, /* 2 */
417 PCI_SPEED_133MHz_PCIX, /* 3 */
418 PCI_SPEED_UNKNOWN, /* 4 */
419 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
420 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
421 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
422 PCI_SPEED_UNKNOWN, /* 8 */
423 PCI_SPEED_66MHz_PCIX_266, /* 9 */
424 PCI_SPEED_100MHz_PCIX_266, /* A */
425 PCI_SPEED_133MHz_PCIX_266, /* B */
426 PCI_SPEED_UNKNOWN, /* C */
427 PCI_SPEED_66MHz_PCIX_533, /* D */
428 PCI_SPEED_100MHz_PCIX_533, /* E */
429 PCI_SPEED_133MHz_PCIX_533 /* F */
430};
431
432static unsigned char pcie_link_speed[] = {
433 PCI_SPEED_UNKNOWN, /* 0 */
434 PCIE_SPEED_2_5GT, /* 1 */
435 PCIE_SPEED_5_0GT, /* 2 */
436 PCIE_SPEED_8_0GT, /* 3 */
437 PCI_SPEED_UNKNOWN, /* 4 */
438 PCI_SPEED_UNKNOWN, /* 5 */
439 PCI_SPEED_UNKNOWN, /* 6 */
440 PCI_SPEED_UNKNOWN, /* 7 */
441 PCI_SPEED_UNKNOWN, /* 8 */
442 PCI_SPEED_UNKNOWN, /* 9 */
443 PCI_SPEED_UNKNOWN, /* A */
444 PCI_SPEED_UNKNOWN, /* B */
445 PCI_SPEED_UNKNOWN, /* C */
446 PCI_SPEED_UNKNOWN, /* D */
447 PCI_SPEED_UNKNOWN, /* E */
448 PCI_SPEED_UNKNOWN /* F */
449};
450
451void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
452{
453 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
454}
455EXPORT_SYMBOL_GPL(pcie_update_link_speed);
456
457static unsigned char agp_speeds[] = {
458 AGP_UNKNOWN,
459 AGP_1X,
460 AGP_2X,
461 AGP_4X,
462 AGP_8X
463};
464
465static enum pci_bus_speed agp_speed(int agp3, int agpstat)
466{
467 int index = 0;
468
469 if (agpstat & 4)
470 index = 3;
471 else if (agpstat & 2)
472 index = 2;
473 else if (agpstat & 1)
474 index = 1;
475 else
476 goto out;
477
478 if (agp3) {
479 index += 2;
480 if (index == 5)
481 index = 0;
482 }
483
484 out:
485 return agp_speeds[index];
486}
487
488
489static void pci_set_bus_speed(struct pci_bus *bus)
490{
491 struct pci_dev *bridge = bus->self;
492 int pos;
493
494 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
495 if (!pos)
496 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
497 if (pos) {
498 u32 agpstat, agpcmd;
499
500 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
501 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
502
503 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
504 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
505 }
506
507 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
508 if (pos) {
509 u16 status;
510 enum pci_bus_speed max;
511 pci_read_config_word(bridge, pos + 2, &status);
512
513 if (status & 0x8000) {
514 max = PCI_SPEED_133MHz_PCIX_533;
515 } else if (status & 0x4000) {
516 max = PCI_SPEED_133MHz_PCIX_266;
517 } else if (status & 0x0002) {
518 if (((status >> 12) & 0x3) == 2) {
519 max = PCI_SPEED_133MHz_PCIX_ECC;
520 } else {
521 max = PCI_SPEED_133MHz_PCIX;
522 }
523 } else {
524 max = PCI_SPEED_66MHz_PCIX;
525 }
526
527 bus->max_bus_speed = max;
528 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
529
530 return;
531 }
532
533 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
534 if (pos) {
535 u32 linkcap;
536 u16 linksta;
537
538 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
539 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
540
541 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
542 pcie_update_link_speed(bus, linksta);
543 }
544}
545
546
547static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
548 struct pci_dev *bridge, int busnr)
549{
550 struct pci_bus *child;
551 int i;
552
553 /*
554 * Allocate a new bus, and inherit stuff from the parent..
555 */
556 child = pci_alloc_bus();
557 if (!child)
558 return NULL;
559
560 child->parent = parent;
561 child->ops = parent->ops;
562 child->sysdata = parent->sysdata;
563 child->bus_flags = parent->bus_flags;
564
565 /* initialize some portions of the bus device, but don't register it
566 * now as the parent is not properly set up yet. This device will get
567 * registered later in pci_bus_add_devices()
568 */
569 child->dev.class = &pcibus_class;
570 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
571
572 /*
573 * Set up the primary, secondary and subordinate
574 * bus numbers.
575 */
576 child->number = child->secondary = busnr;
577 child->primary = parent->secondary;
578 child->subordinate = 0xff;
579
580 if (!bridge)
581 return child;
582
583 child->self = bridge;
584 child->bridge = get_device(&bridge->dev);
585 pci_set_bus_of_node(child);
586 pci_set_bus_speed(child);
587
588 /* Set up default resource pointers and names.. */
589 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
590 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
591 child->resource[i]->name = child->name;
592 }
593 bridge->subordinate = child;
594
595 return child;
596}
597
598struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
599{
600 struct pci_bus *child;
601
602 child = pci_alloc_child_bus(parent, dev, busnr);
603 if (child) {
604 down_write(&pci_bus_sem);
605 list_add_tail(&child->node, &parent->children);
606 up_write(&pci_bus_sem);
607 }
608 return child;
609}
610
611static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
612{
613 struct pci_bus *parent = child->parent;
614
615 /* Attempts to fix that up are really dangerous unless
616 we're going to re-assign all bus numbers. */
617 if (!pcibios_assign_all_busses())
618 return;
619
620 while (parent->parent && parent->subordinate < max) {
621 parent->subordinate = max;
622 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
623 parent = parent->parent;
624 }
625}
626
627/*
628 * If it's a bridge, configure it and scan the bus behind it.
629 * For CardBus bridges, we don't scan behind as the devices will
630 * be handled by the bridge driver itself.
631 *
632 * We need to process bridges in two passes -- first we scan those
633 * already configured by the BIOS and after we are done with all of
634 * them, we proceed to assigning numbers to the remaining buses in
635 * order to avoid overlaps between old and new bus numbers.
636 */
637int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
638{
639 struct pci_bus *child;
640 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
641 u32 buses, i, j = 0;
642 u16 bctl;
643 u8 primary, secondary, subordinate;
644 int broken = 0;
645
646 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
647 primary = buses & 0xFF;
648 secondary = (buses >> 8) & 0xFF;
649 subordinate = (buses >> 16) & 0xFF;
650
651 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
652 secondary, subordinate, pass);
653
654 /* Check if setup is sensible at all */
655 if (!pass &&
656 (primary != bus->number || secondary <= bus->number)) {
657 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
658 broken = 1;
659 }
660
661 /* Disable MasterAbortMode during probing to avoid reporting
662 of bus errors (in some architectures) */
663 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
664 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
665 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
666
667 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
668 !is_cardbus && !broken) {
669 unsigned int cmax;
670 /*
671 * Bus already configured by firmware, process it in the first
672 * pass and just note the configuration.
673 */
674 if (pass)
675 goto out;
676
677 /*
678 * If we already got to this bus through a different bridge,
679 * don't re-add it. This can happen with the i450NX chipset.
680 *
681 * However, we continue to descend down the hierarchy and
682 * scan remaining child buses.
683 */
684 child = pci_find_bus(pci_domain_nr(bus), secondary);
685 if (!child) {
686 child = pci_add_new_bus(bus, dev, secondary);
687 if (!child)
688 goto out;
689 child->primary = primary;
690 child->subordinate = subordinate;
691 child->bridge_ctl = bctl;
692 }
693
694 cmax = pci_scan_child_bus(child);
695 if (cmax > max)
696 max = cmax;
697 if (child->subordinate > max)
698 max = child->subordinate;
699 } else {
700 /*
701 * We need to assign a number to this bus which we always
702 * do in the second pass.
703 */
704 if (!pass) {
705 if (pcibios_assign_all_busses() || broken)
706 /* Temporarily disable forwarding of the
707 configuration cycles on all bridges in
708 this bus segment to avoid possible
709 conflicts in the second pass between two
710 bridges programmed with overlapping
711 bus ranges. */
712 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
713 buses & ~0xffffff);
714 goto out;
715 }
716
717 /* Clear errors */
718 pci_write_config_word(dev, PCI_STATUS, 0xffff);
719
720 /* Prevent assigning a bus number that already exists.
721 * This can happen when a bridge is hot-plugged, so in
722 * this case we only re-scan this bus. */
723 child = pci_find_bus(pci_domain_nr(bus), max+1);
724 if (!child) {
725 child = pci_add_new_bus(bus, dev, ++max);
726 if (!child)
727 goto out;
728 }
729 buses = (buses & 0xff000000)
730 | ((unsigned int)(child->primary) << 0)
731 | ((unsigned int)(child->secondary) << 8)
732 | ((unsigned int)(child->subordinate) << 16);
733
734 /*
735 * yenta.c forces a secondary latency timer of 176.
736 * Copy that behaviour here.
737 */
738 if (is_cardbus) {
739 buses &= ~0xff000000;
740 buses |= CARDBUS_LATENCY_TIMER << 24;
741 }
742
743 /*
744 * We need to blast all three values with a single write.
745 */
746 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
747
748 if (!is_cardbus) {
749 child->bridge_ctl = bctl;
750 /*
751 * Adjust subordinate busnr in parent buses.
752 * We do this before scanning for children because
753 * some devices may not be detected if the bios
754 * was lazy.
755 */
756 pci_fixup_parent_subordinate_busnr(child, max);
757 /* Now we can scan all subordinate buses... */
758 max = pci_scan_child_bus(child);
759 /*
760 * now fix it up again since we have found
761 * the real value of max.
762 */
763 pci_fixup_parent_subordinate_busnr(child, max);
764 } else {
765 /*
766 * For CardBus bridges, we leave 4 bus numbers
767 * as cards with a PCI-to-PCI bridge can be
768 * inserted later.
769 */
770 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
771 struct pci_bus *parent = bus;
772 if (pci_find_bus(pci_domain_nr(bus),
773 max+i+1))
774 break;
775 while (parent->parent) {
776 if ((!pcibios_assign_all_busses()) &&
777 (parent->subordinate > max) &&
778 (parent->subordinate <= max+i)) {
779 j = 1;
780 }
781 parent = parent->parent;
782 }
783 if (j) {
784 /*
785 * Often, there are two cardbus bridges
786 * -- try to leave one valid bus number
787 * for each one.
788 */
789 i /= 2;
790 break;
791 }
792 }
793 max += i;
794 pci_fixup_parent_subordinate_busnr(child, max);
795 }
796 /*
797 * Set the subordinate bus number to its real value.
798 */
799 child->subordinate = max;
800 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
801 }
802
803 sprintf(child->name,
804 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
805 pci_domain_nr(bus), child->number);
806
807 /* Has only triggered on CardBus, fixup is in yenta_socket */
808 while (bus->parent) {
809 if ((child->subordinate > bus->subordinate) ||
810 (child->number > bus->subordinate) ||
811 (child->number < bus->number) ||
812 (child->subordinate < bus->number)) {
813 dev_info(&child->dev, "[bus %02x-%02x] %s "
814 "hidden behind%s bridge %s [bus %02x-%02x]\n",
815 child->number, child->subordinate,
816 (bus->number > child->subordinate &&
817 bus->subordinate < child->number) ?
818 "wholly" : "partially",
819 bus->self->transparent ? " transparent" : "",
820 dev_name(&bus->dev),
821 bus->number, bus->subordinate);
822 }
823 bus = bus->parent;
824 }
825
826out:
827 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
828
829 return max;
830}
831
832/*
833 * Read interrupt line and base address registers.
834 * The architecture-dependent code can tweak these, of course.
835 */
836static void pci_read_irq(struct pci_dev *dev)
837{
838 unsigned char irq;
839
840 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
841 dev->pin = irq;
842 if (irq)
843 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
844 dev->irq = irq;
845}
846
847void set_pcie_port_type(struct pci_dev *pdev)
848{
849 int pos;
850 u16 reg16;
851
852 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
853 if (!pos)
854 return;
855 pdev->is_pcie = 1;
856 pdev->pcie_cap = pos;
857 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
858 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
859 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
860 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
861}
862
863void set_pcie_hotplug_bridge(struct pci_dev *pdev)
864{
865 int pos;
866 u16 reg16;
867 u32 reg32;
868
869 pos = pci_pcie_cap(pdev);
870 if (!pos)
871 return;
872 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
873 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
874 return;
875 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);
876 if (reg32 & PCI_EXP_SLTCAP_HPC)
877 pdev->is_hotplug_bridge = 1;
878}
879
880#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
881
882/**
883 * pci_setup_device - fill in class and map information of a device
884 * @dev: the device structure to fill
885 *
886 * Initialize the device structure with information about the device's
887 * vendor,class,memory and IO-space addresses,IRQ lines etc.
888 * Called at initialisation of the PCI subsystem and by CardBus services.
889 * Returns 0 on success and negative if unknown type of device (not normal,
890 * bridge or CardBus).
891 */
892int pci_setup_device(struct pci_dev *dev)
893{
894 u32 class;
895 u8 hdr_type;
896 struct pci_slot *slot;
897 int pos = 0;
898
899 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
900 return -EIO;
901
902 dev->sysdata = dev->bus->sysdata;
903 dev->dev.parent = dev->bus->bridge;
904 dev->dev.bus = &pci_bus_type;
905 dev->hdr_type = hdr_type & 0x7f;
906 dev->multifunction = !!(hdr_type & 0x80);
907 dev->error_state = pci_channel_io_normal;
908 set_pcie_port_type(dev);
909
910 list_for_each_entry(slot, &dev->bus->slots, list)
911 if (PCI_SLOT(dev->devfn) == slot->number)
912 dev->slot = slot;
913
914 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
915 set this higher, assuming the system even supports it. */
916 dev->dma_mask = 0xffffffff;
917
918 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
919 dev->bus->number, PCI_SLOT(dev->devfn),
920 PCI_FUNC(dev->devfn));
921
922 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
923 dev->revision = class & 0xff;
924 class >>= 8; /* upper 3 bytes */
925 dev->class = class;
926 class >>= 8;
927
928 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
929 dev->vendor, dev->device, dev->hdr_type, class);
930
931 /* need to have dev->class ready */
932 dev->cfg_size = pci_cfg_space_size(dev);
933
934 /* "Unknown power state" */
935 dev->current_state = PCI_UNKNOWN;
936
937 /* Early fixups, before probing the BARs */
938 pci_fixup_device(pci_fixup_early, dev);
939 /* device class may be changed after fixup */
940 class = dev->class >> 8;
941
942 switch (dev->hdr_type) { /* header type */
943 case PCI_HEADER_TYPE_NORMAL: /* standard header */
944 if (class == PCI_CLASS_BRIDGE_PCI)
945 goto bad;
946 pci_read_irq(dev);
947 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
948 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
949 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
950
951 /*
952 * Do the ugly legacy mode stuff here rather than broken chip
953 * quirk code. Legacy mode ATA controllers have fixed
954 * addresses. These are not always echoed in BAR0-3, and
955 * BAR0-3 in a few cases contain junk!
956 */
957 if (class == PCI_CLASS_STORAGE_IDE) {
958 u8 progif;
959 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
960 if ((progif & 1) == 0) {
961 dev->resource[0].start = 0x1F0;
962 dev->resource[0].end = 0x1F7;
963 dev->resource[0].flags = LEGACY_IO_RESOURCE;
964 dev->resource[1].start = 0x3F6;
965 dev->resource[1].end = 0x3F6;
966 dev->resource[1].flags = LEGACY_IO_RESOURCE;
967 }
968 if ((progif & 4) == 0) {
969 dev->resource[2].start = 0x170;
970 dev->resource[2].end = 0x177;
971 dev->resource[2].flags = LEGACY_IO_RESOURCE;
972 dev->resource[3].start = 0x376;
973 dev->resource[3].end = 0x376;
974 dev->resource[3].flags = LEGACY_IO_RESOURCE;
975 }
976 }
977 break;
978
979 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
980 if (class != PCI_CLASS_BRIDGE_PCI)
981 goto bad;
982 /* The PCI-to-PCI bridge spec requires that subtractive
983 decoding (i.e. transparent) bridge must have programming
984 interface code of 0x01. */
985 pci_read_irq(dev);
986 dev->transparent = ((dev->class & 0xff) == 1);
987 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
988 set_pcie_hotplug_bridge(dev);
989 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
990 if (pos) {
991 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
992 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
993 }
994 break;
995
996 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
997 if (class != PCI_CLASS_BRIDGE_CARDBUS)
998 goto bad;
999 pci_read_irq(dev);
1000 pci_read_bases(dev, 1, 0);
1001 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1002 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1003 break;
1004
1005 default: /* unknown header */
1006 dev_err(&dev->dev, "unknown header type %02x, "
1007 "ignoring device\n", dev->hdr_type);
1008 return -EIO;
1009
1010 bad:
1011 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1012 "type %02x)\n", class, dev->hdr_type);
1013 dev->class = PCI_CLASS_NOT_DEFINED;
1014 }
1015
1016 /* We found a fine healthy device, go go go... */
1017 return 0;
1018}
1019
1020static void pci_release_capabilities(struct pci_dev *dev)
1021{
1022 pci_vpd_release(dev);
1023 pci_iov_release(dev);
1024}
1025
1026/**
1027 * pci_release_dev - free a pci device structure when all users of it are finished.
1028 * @dev: device that's been disconnected
1029 *
1030 * Will be called only by the device core when all users of this pci device are
1031 * done.
1032 */
1033static void pci_release_dev(struct device *dev)
1034{
1035 struct pci_dev *pci_dev;
1036
1037 pci_dev = to_pci_dev(dev);
1038 pci_release_capabilities(pci_dev);
1039 pci_release_of_node(pci_dev);
1040 kfree(pci_dev);
1041}
1042
1043/**
1044 * pci_cfg_space_size - get the configuration space size of the PCI device.
1045 * @dev: PCI device
1046 *
1047 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1048 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1049 * access it. Maybe we don't have a way to generate extended config space
1050 * accesses, or the device is behind a reverse Express bridge. So we try
1051 * reading the dword at 0x100 which must either be 0 or a valid extended
1052 * capability header.
1053 */
1054int pci_cfg_space_size_ext(struct pci_dev *dev)
1055{
1056 u32 status;
1057 int pos = PCI_CFG_SPACE_SIZE;
1058
1059 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1060 goto fail;
1061 if (status == 0xffffffff)
1062 goto fail;
1063
1064 return PCI_CFG_SPACE_EXP_SIZE;
1065
1066 fail:
1067 return PCI_CFG_SPACE_SIZE;
1068}
1069
1070int pci_cfg_space_size(struct pci_dev *dev)
1071{
1072 int pos;
1073 u32 status;
1074 u16 class;
1075
1076 class = dev->class >> 8;
1077 if (class == PCI_CLASS_BRIDGE_HOST)
1078 return pci_cfg_space_size_ext(dev);
1079
1080 pos = pci_pcie_cap(dev);
1081 if (!pos) {
1082 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1083 if (!pos)
1084 goto fail;
1085
1086 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1087 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1088 goto fail;
1089 }
1090
1091 return pci_cfg_space_size_ext(dev);
1092
1093 fail:
1094 return PCI_CFG_SPACE_SIZE;
1095}
1096
1097static void pci_release_bus_bridge_dev(struct device *dev)
1098{
1099 kfree(dev);
1100}
1101
1102struct pci_dev *alloc_pci_dev(void)
1103{
1104 struct pci_dev *dev;
1105
1106 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1107 if (!dev)
1108 return NULL;
1109
1110 INIT_LIST_HEAD(&dev->bus_list);
1111
1112 return dev;
1113}
1114EXPORT_SYMBOL(alloc_pci_dev);
1115
1116/*
1117 * Read the config data for a PCI device, sanity-check it
1118 * and fill in the dev structure...
1119 */
1120static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1121{
1122 struct pci_dev *dev;
1123 u32 l;
1124 int delay = 1;
1125
1126 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1127 return NULL;
1128
1129 /* some broken boards return 0 or ~0 if a slot is empty: */
1130 if (l == 0xffffffff || l == 0x00000000 ||
1131 l == 0x0000ffff || l == 0xffff0000)
1132 return NULL;
1133
1134 /* Configuration request Retry Status */
1135 while (l == 0xffff0001) {
1136 msleep(delay);
1137 delay *= 2;
1138 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1139 return NULL;
1140 /* Card hasn't responded in 60 seconds? Must be stuck. */
1141 if (delay > 60 * 1000) {
1142 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1143 "responding\n", pci_domain_nr(bus),
1144 bus->number, PCI_SLOT(devfn),
1145 PCI_FUNC(devfn));
1146 return NULL;
1147 }
1148 }
1149
1150 dev = alloc_pci_dev();
1151 if (!dev)
1152 return NULL;
1153
1154 dev->bus = bus;
1155 dev->devfn = devfn;
1156 dev->vendor = l & 0xffff;
1157 dev->device = (l >> 16) & 0xffff;
1158
1159 pci_set_of_node(dev);
1160
1161 if (pci_setup_device(dev)) {
1162 kfree(dev);
1163 return NULL;
1164 }
1165
1166 return dev;
1167}
1168
1169static void pci_init_capabilities(struct pci_dev *dev)
1170{
1171 /* MSI/MSI-X list */
1172 pci_msi_init_pci_dev(dev);
1173
1174 /* Buffers for saving PCIe and PCI-X capabilities */
1175 pci_allocate_cap_save_buffers(dev);
1176
1177 /* Power Management */
1178 pci_pm_init(dev);
1179 platform_pci_wakeup_init(dev);
1180
1181 /* Vital Product Data */
1182 pci_vpd_pci22_init(dev);
1183
1184 /* Alternative Routing-ID Forwarding */
1185 pci_enable_ari(dev);
1186
1187 /* Single Root I/O Virtualization */
1188 pci_iov_init(dev);
1189
1190 /* Enable ACS P2P upstream forwarding */
1191 pci_enable_acs(dev);
1192}
1193
1194void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1195{
1196 device_initialize(&dev->dev);
1197 dev->dev.release = pci_release_dev;
1198 pci_dev_get(dev);
1199
1200 dev->dev.dma_mask = &dev->dma_mask;
1201 dev->dev.dma_parms = &dev->dma_parms;
1202 dev->dev.coherent_dma_mask = 0xffffffffull;
1203
1204 pci_set_dma_max_seg_size(dev, 65536);
1205 pci_set_dma_seg_boundary(dev, 0xffffffff);
1206
1207 /* Fix up broken headers */
1208 pci_fixup_device(pci_fixup_header, dev);
1209
1210 /* Clear the state_saved flag. */
1211 dev->state_saved = false;
1212
1213 /* Initialize various capabilities */
1214 pci_init_capabilities(dev);
1215
1216 /*
1217 * Add the device to our list of discovered devices
1218 * and the bus list for fixup functions, etc.
1219 */
1220 down_write(&pci_bus_sem);
1221 list_add_tail(&dev->bus_list, &bus->devices);
1222 up_write(&pci_bus_sem);
1223}
1224
1225struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1226{
1227 struct pci_dev *dev;
1228
1229 dev = pci_get_slot(bus, devfn);
1230 if (dev) {
1231 pci_dev_put(dev);
1232 return dev;
1233 }
1234
1235 dev = pci_scan_device(bus, devfn);
1236 if (!dev)
1237 return NULL;
1238
1239 pci_device_add(dev, bus);
1240
1241 return dev;
1242}
1243EXPORT_SYMBOL(pci_scan_single_device);
1244
1245static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1246{
1247 u16 cap;
1248 unsigned pos, next_fn;
1249
1250 if (!dev)
1251 return 0;
1252
1253 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1254 if (!pos)
1255 return 0;
1256 pci_read_config_word(dev, pos + 4, &cap);
1257 next_fn = cap >> 8;
1258 if (next_fn <= fn)
1259 return 0;
1260 return next_fn;
1261}
1262
1263static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1264{
1265 return (fn + 1) % 8;
1266}
1267
1268static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1269{
1270 return 0;
1271}
1272
1273static int only_one_child(struct pci_bus *bus)
1274{
1275 struct pci_dev *parent = bus->self;
1276 if (!parent || !pci_is_pcie(parent))
1277 return 0;
1278 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1279 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1280 return 1;
1281 return 0;
1282}
1283
1284/**
1285 * pci_scan_slot - scan a PCI slot on a bus for devices.
1286 * @bus: PCI bus to scan
1287 * @devfn: slot number to scan (must have zero function.)
1288 *
1289 * Scan a PCI slot on the specified PCI bus for devices, adding
1290 * discovered devices to the @bus->devices list. New devices
1291 * will not have is_added set.
1292 *
1293 * Returns the number of new devices found.
1294 */
1295int pci_scan_slot(struct pci_bus *bus, int devfn)
1296{
1297 unsigned fn, nr = 0;
1298 struct pci_dev *dev;
1299 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1300
1301 if (only_one_child(bus) && (devfn > 0))
1302 return 0; /* Already scanned the entire slot */
1303
1304 dev = pci_scan_single_device(bus, devfn);
1305 if (!dev)
1306 return 0;
1307 if (!dev->is_added)
1308 nr++;
1309
1310 if (pci_ari_enabled(bus))
1311 next_fn = next_ari_fn;
1312 else if (dev->multifunction)
1313 next_fn = next_trad_fn;
1314
1315 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1316 dev = pci_scan_single_device(bus, devfn + fn);
1317 if (dev) {
1318 if (!dev->is_added)
1319 nr++;
1320 dev->multifunction = 1;
1321 }
1322 }
1323
1324 /* only one slot has pcie device */
1325 if (bus->self && nr)
1326 pcie_aspm_init_link_state(bus->self);
1327
1328 return nr;
1329}
1330
1331static int pcie_find_smpss(struct pci_dev *dev, void *data)
1332{
1333 u8 *smpss = data;
1334
1335 if (!pci_is_pcie(dev))
1336 return 0;
1337
1338 /* For PCIE hotplug enabled slots not connected directly to a
1339 * PCI-E root port, there can be problems when hotplugging
1340 * devices. This is due to the possibility of hotplugging a
1341 * device into the fabric with a smaller MPS that the devices
1342 * currently running have configured. Modifying the MPS on the
1343 * running devices could cause a fatal bus error due to an
1344 * incoming frame being larger than the newly configured MPS.
1345 * To work around this, the MPS for the entire fabric must be
1346 * set to the minimum size. Any devices hotplugged into this
1347 * fabric will have the minimum MPS set. If the PCI hotplug
1348 * slot is directly connected to the root port and there are not
1349 * other devices on the fabric (which seems to be the most
1350 * common case), then this is not an issue and MPS discovery
1351 * will occur as normal.
1352 */
1353 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1354 (dev->bus->self &&
1355 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
1356 *smpss = 0;
1357
1358 if (*smpss > dev->pcie_mpss)
1359 *smpss = dev->pcie_mpss;
1360
1361 return 0;
1362}
1363
1364static void pcie_write_mps(struct pci_dev *dev, int mps)
1365{
1366 int rc, dev_mpss;
1367
1368 dev_mpss = 128 << dev->pcie_mpss;
1369
1370 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1371 if (dev->bus->self) {
1372 dev_dbg(&dev->bus->dev, "Bus MPSS %d\n",
1373 128 << dev->bus->self->pcie_mpss);
1374
1375 /* For "MPS Force Max", the assumption is made that
1376 * downstream communication will never be larger than
1377 * the MRRS. So, the MPS only needs to be configured
1378 * for the upstream communication. This being the case,
1379 * walk from the top down and set the MPS of the child
1380 * to that of the parent bus.
1381 */
1382 mps = 128 << dev->bus->self->pcie_mpss;
1383 if (mps > dev_mpss)
1384 dev_warn(&dev->dev, "MPS configured higher than"
1385 " maximum supported by the device. If"
1386 " a bus issue occurs, try running with"
1387 " pci=pcie_bus_safe.\n");
1388 }
1389
1390 dev->pcie_mpss = ffs(mps) - 8;
1391 }
1392
1393 rc = pcie_set_mps(dev, mps);
1394 if (rc)
1395 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1396}
1397
1398static void pcie_write_mrrs(struct pci_dev *dev, int mps)
1399{
1400 int rc, mrrs, dev_mpss;
1401
1402 /* In the "safe" case, do not configure the MRRS. There appear to be
1403 * issues with setting MRRS to 0 on a number of devices.
1404 */
1405
1406 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1407 return;
1408
1409 dev_mpss = 128 << dev->pcie_mpss;
1410
1411 /* For Max performance, the MRRS must be set to the largest supported
1412 * value. However, it cannot be configured larger than the MPS the
1413 * device or the bus can support. This assumes that the largest MRRS
1414 * available on the device cannot be smaller than the device MPSS.
1415 */
1416 mrrs = min(mps, dev_mpss);
1417
1418 /* MRRS is a R/W register. Invalid values can be written, but a
1419 * subsequent read will verify if the value is acceptable or not.
1420 * If the MRRS value provided is not acceptable (e.g., too large),
1421 * shrink the value until it is acceptable to the HW.
1422 */
1423 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1424 dev_warn(&dev->dev, "Attempting to modify the PCI-E MRRS value"
1425 " to %d. If any issues are encountered, please try "
1426 "running with pci=pcie_bus_safe\n", mrrs);
1427 rc = pcie_set_readrq(dev, mrrs);
1428 if (rc)
1429 dev_err(&dev->dev,
1430 "Failed attempting to set the MRRS\n");
1431
1432 mrrs /= 2;
1433 }
1434}
1435
1436static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1437{
1438 int mps = 128 << *(u8 *)data;
1439
1440 if (!pci_is_pcie(dev))
1441 return 0;
1442
1443 dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
1444 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
1445
1446 pcie_write_mps(dev, mps);
1447 pcie_write_mrrs(dev, mps);
1448
1449 dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
1450 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
1451
1452 return 0;
1453}
1454
1455/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down,
1456 * parents then children fashion. If this changes, then this code will not
1457 * work as designed.
1458 */
1459void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1460{
1461 u8 smpss;
1462
1463 if (!pci_is_pcie(bus->self))
1464 return;
1465
1466 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1467 return;
1468
1469 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1470 * to be aware to the MPS of the destination. To work around this,
1471 * simply force the MPS of the entire system to the smallest possible.
1472 */
1473 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1474 smpss = 0;
1475
1476 if (pcie_bus_config == PCIE_BUS_SAFE) {
1477 smpss = mpss;
1478
1479 pcie_find_smpss(bus->self, &smpss);
1480 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1481 }
1482
1483 pcie_bus_configure_set(bus->self, &smpss);
1484 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1485}
1486EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1487
1488unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1489{
1490 unsigned int devfn, pass, max = bus->secondary;
1491 struct pci_dev *dev;
1492
1493 dev_dbg(&bus->dev, "scanning bus\n");
1494
1495 /* Go find them, Rover! */
1496 for (devfn = 0; devfn < 0x100; devfn += 8)
1497 pci_scan_slot(bus, devfn);
1498
1499 /* Reserve buses for SR-IOV capability. */
1500 max += pci_iov_bus_range(bus);
1501
1502 /*
1503 * After performing arch-dependent fixup of the bus, look behind
1504 * all PCI-to-PCI bridges on this bus.
1505 */
1506 if (!bus->is_added) {
1507 dev_dbg(&bus->dev, "fixups for bus\n");
1508 pcibios_fixup_bus(bus);
1509 if (pci_is_root_bus(bus))
1510 bus->is_added = 1;
1511 }
1512
1513 for (pass=0; pass < 2; pass++)
1514 list_for_each_entry(dev, &bus->devices, bus_list) {
1515 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1516 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1517 max = pci_scan_bridge(bus, dev, max, pass);
1518 }
1519
1520 /*
1521 * We've scanned the bus and so we know all about what's on
1522 * the other side of any bridges that may be on this bus plus
1523 * any devices.
1524 *
1525 * Return how far we've got finding sub-buses.
1526 */
1527 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1528 return max;
1529}
1530
1531struct pci_bus * pci_create_bus(struct device *parent,
1532 int bus, struct pci_ops *ops, void *sysdata)
1533{
1534 int error;
1535 struct pci_bus *b, *b2;
1536 struct device *dev;
1537
1538 b = pci_alloc_bus();
1539 if (!b)
1540 return NULL;
1541
1542 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1543 if (!dev){
1544 kfree(b);
1545 return NULL;
1546 }
1547
1548 b->sysdata = sysdata;
1549 b->ops = ops;
1550
1551 b2 = pci_find_bus(pci_domain_nr(b), bus);
1552 if (b2) {
1553 /* If we already got to this bus through a different bridge, ignore it */
1554 dev_dbg(&b2->dev, "bus already known\n");
1555 goto err_out;
1556 }
1557
1558 down_write(&pci_bus_sem);
1559 list_add_tail(&b->node, &pci_root_buses);
1560 up_write(&pci_bus_sem);
1561
1562 dev->parent = parent;
1563 dev->release = pci_release_bus_bridge_dev;
1564 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1565 error = device_register(dev);
1566 if (error)
1567 goto dev_reg_err;
1568 b->bridge = get_device(dev);
1569 device_enable_async_suspend(b->bridge);
1570 pci_set_bus_of_node(b);
1571
1572 if (!parent)
1573 set_dev_node(b->bridge, pcibus_to_node(b));
1574
1575 b->dev.class = &pcibus_class;
1576 b->dev.parent = b->bridge;
1577 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1578 error = device_register(&b->dev);
1579 if (error)
1580 goto class_dev_reg_err;
1581
1582 /* Create legacy_io and legacy_mem files for this bus */
1583 pci_create_legacy_files(b);
1584
1585 b->number = b->secondary = bus;
1586 b->resource[0] = &ioport_resource;
1587 b->resource[1] = &iomem_resource;
1588
1589 return b;
1590
1591class_dev_reg_err:
1592 device_unregister(dev);
1593dev_reg_err:
1594 down_write(&pci_bus_sem);
1595 list_del(&b->node);
1596 up_write(&pci_bus_sem);
1597err_out:
1598 kfree(dev);
1599 kfree(b);
1600 return NULL;
1601}
1602
1603struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1604 int bus, struct pci_ops *ops, void *sysdata)
1605{
1606 struct pci_bus *b;
1607
1608 b = pci_create_bus(parent, bus, ops, sysdata);
1609 if (b)
1610 b->subordinate = pci_scan_child_bus(b);
1611 return b;
1612}
1613EXPORT_SYMBOL(pci_scan_bus_parented);
1614
1615#ifdef CONFIG_HOTPLUG
1616/**
1617 * pci_rescan_bus - scan a PCI bus for devices.
1618 * @bus: PCI bus to scan
1619 *
1620 * Scan a PCI bus and child buses for new devices, adds them,
1621 * and enables them.
1622 *
1623 * Returns the max number of subordinate bus discovered.
1624 */
1625unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1626{
1627 unsigned int max;
1628 struct pci_dev *dev;
1629
1630 max = pci_scan_child_bus(bus);
1631
1632 down_read(&pci_bus_sem);
1633 list_for_each_entry(dev, &bus->devices, bus_list)
1634 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1635 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1636 if (dev->subordinate)
1637 pci_bus_size_bridges(dev->subordinate);
1638 up_read(&pci_bus_sem);
1639
1640 pci_bus_assign_resources(bus);
1641 pci_enable_bridges(bus);
1642 pci_bus_add_devices(bus);
1643
1644 return max;
1645}
1646EXPORT_SYMBOL_GPL(pci_rescan_bus);
1647
1648EXPORT_SYMBOL(pci_add_new_bus);
1649EXPORT_SYMBOL(pci_scan_slot);
1650EXPORT_SYMBOL(pci_scan_bridge);
1651EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1652#endif
1653
1654static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1655{
1656 const struct pci_dev *a = to_pci_dev(d_a);
1657 const struct pci_dev *b = to_pci_dev(d_b);
1658
1659 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1660 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1661
1662 if (a->bus->number < b->bus->number) return -1;
1663 else if (a->bus->number > b->bus->number) return 1;
1664
1665 if (a->devfn < b->devfn) return -1;
1666 else if (a->devfn > b->devfn) return 1;
1667
1668 return 0;
1669}
1670
1671void __init pci_sort_breadthfirst(void)
1672{
1673 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1674}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI detection and setup code
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/of_device.h>
11#include <linux/of_pci.h>
12#include <linux/pci_hotplug.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/cpumask.h>
16#include <linux/pci-aspm.h>
17#include <linux/aer.h>
18#include <linux/acpi.h>
19#include <linux/hypervisor.h>
20#include <linux/irqdomain.h>
21#include <linux/pm_runtime.h>
22#include "pci.h"
23
24#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25#define CARDBUS_RESERVE_BUSNR 3
26
27static struct resource busn_resource = {
28 .name = "PCI busn",
29 .start = 0,
30 .end = 255,
31 .flags = IORESOURCE_BUS,
32};
33
34/* Ugh. Need to stop exporting this to modules. */
35LIST_HEAD(pci_root_buses);
36EXPORT_SYMBOL(pci_root_buses);
37
38static LIST_HEAD(pci_domain_busn_res_list);
39
40struct pci_domain_busn_res {
41 struct list_head list;
42 struct resource res;
43 int domain_nr;
44};
45
46static struct resource *get_pci_domain_busn_res(int domain_nr)
47{
48 struct pci_domain_busn_res *r;
49
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
52 return &r->res;
53
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 if (!r)
56 return NULL;
57
58 r->domain_nr = domain_nr;
59 r->res.start = 0;
60 r->res.end = 0xff;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
62
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
64
65 return &r->res;
66}
67
68static int find_anything(struct device *dev, void *data)
69{
70 return 1;
71}
72
73/*
74 * Some device drivers need know if PCI is initiated.
75 * Basically, we think PCI is not initiated when there
76 * is no device to be found on the pci_bus_type.
77 */
78int no_pci_devices(void)
79{
80 struct device *dev;
81 int no_devices;
82
83 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
84 no_devices = (dev == NULL);
85 put_device(dev);
86 return no_devices;
87}
88EXPORT_SYMBOL(no_pci_devices);
89
90/*
91 * PCI Bus Class
92 */
93static void release_pcibus_dev(struct device *dev)
94{
95 struct pci_bus *pci_bus = to_pci_bus(dev);
96
97 put_device(pci_bus->bridge);
98 pci_bus_remove_resources(pci_bus);
99 pci_release_bus_of_node(pci_bus);
100 kfree(pci_bus);
101}
102
103static struct class pcibus_class = {
104 .name = "pci_bus",
105 .dev_release = &release_pcibus_dev,
106 .dev_groups = pcibus_groups,
107};
108
109static int __init pcibus_class_init(void)
110{
111 return class_register(&pcibus_class);
112}
113postcore_initcall(pcibus_class_init);
114
115static u64 pci_size(u64 base, u64 maxbase, u64 mask)
116{
117 u64 size = mask & maxbase; /* Find the significant bits */
118 if (!size)
119 return 0;
120
121 /*
122 * Get the lowest of them to find the decode size, and from that
123 * the extent.
124 */
125 size = (size & ~(size-1)) - 1;
126
127 /*
128 * base == maxbase can be valid only if the BAR has already been
129 * programmed with all 1s.
130 */
131 if (base == maxbase && ((base | size) & mask) != mask)
132 return 0;
133
134 return size;
135}
136
137static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
138{
139 u32 mem_type;
140 unsigned long flags;
141
142 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
143 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
144 flags |= IORESOURCE_IO;
145 return flags;
146 }
147
148 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
149 flags |= IORESOURCE_MEM;
150 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
151 flags |= IORESOURCE_PREFETCH;
152
153 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
154 switch (mem_type) {
155 case PCI_BASE_ADDRESS_MEM_TYPE_32:
156 break;
157 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
158 /* 1M mem BAR treated as 32-bit BAR */
159 break;
160 case PCI_BASE_ADDRESS_MEM_TYPE_64:
161 flags |= IORESOURCE_MEM_64;
162 break;
163 default:
164 /* mem unknown type treated as 32-bit BAR */
165 break;
166 }
167 return flags;
168}
169
170#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
171
172/**
173 * pci_read_base - Read a PCI BAR
174 * @dev: the PCI device
175 * @type: type of the BAR
176 * @res: resource buffer to be filled in
177 * @pos: BAR position in the config space
178 *
179 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
180 */
181int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
182 struct resource *res, unsigned int pos)
183{
184 u32 l = 0, sz = 0, mask;
185 u64 l64, sz64, mask64;
186 u16 orig_cmd;
187 struct pci_bus_region region, inverted_region;
188
189 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
190
191 /* No printks while decoding is disabled! */
192 if (!dev->mmio_always_on) {
193 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
194 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
195 pci_write_config_word(dev, PCI_COMMAND,
196 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
197 }
198 }
199
200 res->name = pci_name(dev);
201
202 pci_read_config_dword(dev, pos, &l);
203 pci_write_config_dword(dev, pos, l | mask);
204 pci_read_config_dword(dev, pos, &sz);
205 pci_write_config_dword(dev, pos, l);
206
207 /*
208 * All bits set in sz means the device isn't working properly.
209 * If the BAR isn't implemented, all bits must be 0. If it's a
210 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
211 * 1 must be clear.
212 */
213 if (sz == 0xffffffff)
214 sz = 0;
215
216 /*
217 * I don't know how l can have all bits set. Copied from old code.
218 * Maybe it fixes a bug on some ancient platform.
219 */
220 if (l == 0xffffffff)
221 l = 0;
222
223 if (type == pci_bar_unknown) {
224 res->flags = decode_bar(dev, l);
225 res->flags |= IORESOURCE_SIZEALIGN;
226 if (res->flags & IORESOURCE_IO) {
227 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
229 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
230 } else {
231 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
232 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
233 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
234 }
235 } else {
236 if (l & PCI_ROM_ADDRESS_ENABLE)
237 res->flags |= IORESOURCE_ROM_ENABLE;
238 l64 = l & PCI_ROM_ADDRESS_MASK;
239 sz64 = sz & PCI_ROM_ADDRESS_MASK;
240 mask64 = PCI_ROM_ADDRESS_MASK;
241 }
242
243 if (res->flags & IORESOURCE_MEM_64) {
244 pci_read_config_dword(dev, pos + 4, &l);
245 pci_write_config_dword(dev, pos + 4, ~0);
246 pci_read_config_dword(dev, pos + 4, &sz);
247 pci_write_config_dword(dev, pos + 4, l);
248
249 l64 |= ((u64)l << 32);
250 sz64 |= ((u64)sz << 32);
251 mask64 |= ((u64)~0 << 32);
252 }
253
254 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
255 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
256
257 if (!sz64)
258 goto fail;
259
260 sz64 = pci_size(l64, sz64, mask64);
261 if (!sz64) {
262 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
263 pos);
264 goto fail;
265 }
266
267 if (res->flags & IORESOURCE_MEM_64) {
268 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
269 && sz64 > 0x100000000ULL) {
270 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
271 res->start = 0;
272 res->end = 0;
273 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
274 pos, (unsigned long long)sz64);
275 goto out;
276 }
277
278 if ((sizeof(pci_bus_addr_t) < 8) && l) {
279 /* Above 32-bit boundary; try to reallocate */
280 res->flags |= IORESOURCE_UNSET;
281 res->start = 0;
282 res->end = sz64;
283 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
284 pos, (unsigned long long)l64);
285 goto out;
286 }
287 }
288
289 region.start = l64;
290 region.end = l64 + sz64;
291
292 pcibios_bus_to_resource(dev->bus, res, ®ion);
293 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
294
295 /*
296 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
297 * the corresponding resource address (the physical address used by
298 * the CPU. Converting that resource address back to a bus address
299 * should yield the original BAR value:
300 *
301 * resource_to_bus(bus_to_resource(A)) == A
302 *
303 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
304 * be claimed by the device.
305 */
306 if (inverted_region.start != region.start) {
307 res->flags |= IORESOURCE_UNSET;
308 res->start = 0;
309 res->end = region.end - region.start;
310 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
311 pos, (unsigned long long)region.start);
312 }
313
314 goto out;
315
316
317fail:
318 res->flags = 0;
319out:
320 if (res->flags)
321 pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res);
322
323 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
324}
325
326static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
327{
328 unsigned int pos, reg;
329
330 if (dev->non_compliant_bars)
331 return;
332
333 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
334 if (dev->is_virtfn)
335 return;
336
337 for (pos = 0; pos < howmany; pos++) {
338 struct resource *res = &dev->resource[pos];
339 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
340 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
341 }
342
343 if (rom) {
344 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
345 dev->rom_base_reg = rom;
346 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
347 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
348 __pci_read_base(dev, pci_bar_mem32, res, rom);
349 }
350}
351
352static void pci_read_bridge_io(struct pci_bus *child)
353{
354 struct pci_dev *dev = child->self;
355 u8 io_base_lo, io_limit_lo;
356 unsigned long io_mask, io_granularity, base, limit;
357 struct pci_bus_region region;
358 struct resource *res;
359
360 io_mask = PCI_IO_RANGE_MASK;
361 io_granularity = 0x1000;
362 if (dev->io_window_1k) {
363 /* Support 1K I/O space granularity */
364 io_mask = PCI_IO_1K_RANGE_MASK;
365 io_granularity = 0x400;
366 }
367
368 res = child->resource[0];
369 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
370 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
371 base = (io_base_lo & io_mask) << 8;
372 limit = (io_limit_lo & io_mask) << 8;
373
374 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
375 u16 io_base_hi, io_limit_hi;
376
377 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
378 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
379 base |= ((unsigned long) io_base_hi << 16);
380 limit |= ((unsigned long) io_limit_hi << 16);
381 }
382
383 if (base <= limit) {
384 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
385 region.start = base;
386 region.end = limit + io_granularity - 1;
387 pcibios_bus_to_resource(dev->bus, res, ®ion);
388 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
389 }
390}
391
392static void pci_read_bridge_mmio(struct pci_bus *child)
393{
394 struct pci_dev *dev = child->self;
395 u16 mem_base_lo, mem_limit_lo;
396 unsigned long base, limit;
397 struct pci_bus_region region;
398 struct resource *res;
399
400 res = child->resource[1];
401 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
402 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
403 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
404 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
405 if (base <= limit) {
406 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
407 region.start = base;
408 region.end = limit + 0xfffff;
409 pcibios_bus_to_resource(dev->bus, res, ®ion);
410 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
411 }
412}
413
414static void pci_read_bridge_mmio_pref(struct pci_bus *child)
415{
416 struct pci_dev *dev = child->self;
417 u16 mem_base_lo, mem_limit_lo;
418 u64 base64, limit64;
419 pci_bus_addr_t base, limit;
420 struct pci_bus_region region;
421 struct resource *res;
422
423 res = child->resource[2];
424 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
425 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
426 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
427 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
428
429 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
430 u32 mem_base_hi, mem_limit_hi;
431
432 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
433 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
434
435 /*
436 * Some bridges set the base > limit by default, and some
437 * (broken) BIOSes do not initialize them. If we find
438 * this, just assume they are not being used.
439 */
440 if (mem_base_hi <= mem_limit_hi) {
441 base64 |= (u64) mem_base_hi << 32;
442 limit64 |= (u64) mem_limit_hi << 32;
443 }
444 }
445
446 base = (pci_bus_addr_t) base64;
447 limit = (pci_bus_addr_t) limit64;
448
449 if (base != base64) {
450 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
451 (unsigned long long) base64);
452 return;
453 }
454
455 if (base <= limit) {
456 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
457 IORESOURCE_MEM | IORESOURCE_PREFETCH;
458 if (res->flags & PCI_PREF_RANGE_TYPE_64)
459 res->flags |= IORESOURCE_MEM_64;
460 region.start = base;
461 region.end = limit + 0xfffff;
462 pcibios_bus_to_resource(dev->bus, res, ®ion);
463 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
464 }
465}
466
467void pci_read_bridge_bases(struct pci_bus *child)
468{
469 struct pci_dev *dev = child->self;
470 struct resource *res;
471 int i;
472
473 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
474 return;
475
476 pci_info(dev, "PCI bridge to %pR%s\n",
477 &child->busn_res,
478 dev->transparent ? " (subtractive decode)" : "");
479
480 pci_bus_remove_resources(child);
481 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
482 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
483
484 pci_read_bridge_io(child);
485 pci_read_bridge_mmio(child);
486 pci_read_bridge_mmio_pref(child);
487
488 if (dev->transparent) {
489 pci_bus_for_each_resource(child->parent, res, i) {
490 if (res && res->flags) {
491 pci_bus_add_resource(child, res,
492 PCI_SUBTRACTIVE_DECODE);
493 pci_printk(KERN_DEBUG, dev,
494 " bridge window %pR (subtractive decode)\n",
495 res);
496 }
497 }
498 }
499}
500
501static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
502{
503 struct pci_bus *b;
504
505 b = kzalloc(sizeof(*b), GFP_KERNEL);
506 if (!b)
507 return NULL;
508
509 INIT_LIST_HEAD(&b->node);
510 INIT_LIST_HEAD(&b->children);
511 INIT_LIST_HEAD(&b->devices);
512 INIT_LIST_HEAD(&b->slots);
513 INIT_LIST_HEAD(&b->resources);
514 b->max_bus_speed = PCI_SPEED_UNKNOWN;
515 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
516#ifdef CONFIG_PCI_DOMAINS_GENERIC
517 if (parent)
518 b->domain_nr = parent->domain_nr;
519#endif
520 return b;
521}
522
523static void devm_pci_release_host_bridge_dev(struct device *dev)
524{
525 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
526
527 if (bridge->release_fn)
528 bridge->release_fn(bridge);
529}
530
531static void pci_release_host_bridge_dev(struct device *dev)
532{
533 devm_pci_release_host_bridge_dev(dev);
534 pci_free_host_bridge(to_pci_host_bridge(dev));
535}
536
537struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
538{
539 struct pci_host_bridge *bridge;
540
541 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
542 if (!bridge)
543 return NULL;
544
545 INIT_LIST_HEAD(&bridge->windows);
546 bridge->dev.release = pci_release_host_bridge_dev;
547
548 /*
549 * We assume we can manage these PCIe features. Some systems may
550 * reserve these for use by the platform itself, e.g., an ACPI BIOS
551 * may implement its own AER handling and use _OSC to prevent the
552 * OS from interfering.
553 */
554 bridge->native_aer = 1;
555 bridge->native_hotplug = 1;
556 bridge->native_pme = 1;
557
558 return bridge;
559}
560EXPORT_SYMBOL(pci_alloc_host_bridge);
561
562struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
563 size_t priv)
564{
565 struct pci_host_bridge *bridge;
566
567 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
568 if (!bridge)
569 return NULL;
570
571 INIT_LIST_HEAD(&bridge->windows);
572 bridge->dev.release = devm_pci_release_host_bridge_dev;
573
574 return bridge;
575}
576EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
577
578void pci_free_host_bridge(struct pci_host_bridge *bridge)
579{
580 pci_free_resource_list(&bridge->windows);
581
582 kfree(bridge);
583}
584EXPORT_SYMBOL(pci_free_host_bridge);
585
586static const unsigned char pcix_bus_speed[] = {
587 PCI_SPEED_UNKNOWN, /* 0 */
588 PCI_SPEED_66MHz_PCIX, /* 1 */
589 PCI_SPEED_100MHz_PCIX, /* 2 */
590 PCI_SPEED_133MHz_PCIX, /* 3 */
591 PCI_SPEED_UNKNOWN, /* 4 */
592 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
593 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
594 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
595 PCI_SPEED_UNKNOWN, /* 8 */
596 PCI_SPEED_66MHz_PCIX_266, /* 9 */
597 PCI_SPEED_100MHz_PCIX_266, /* A */
598 PCI_SPEED_133MHz_PCIX_266, /* B */
599 PCI_SPEED_UNKNOWN, /* C */
600 PCI_SPEED_66MHz_PCIX_533, /* D */
601 PCI_SPEED_100MHz_PCIX_533, /* E */
602 PCI_SPEED_133MHz_PCIX_533 /* F */
603};
604
605const unsigned char pcie_link_speed[] = {
606 PCI_SPEED_UNKNOWN, /* 0 */
607 PCIE_SPEED_2_5GT, /* 1 */
608 PCIE_SPEED_5_0GT, /* 2 */
609 PCIE_SPEED_8_0GT, /* 3 */
610 PCIE_SPEED_16_0GT, /* 4 */
611 PCI_SPEED_UNKNOWN, /* 5 */
612 PCI_SPEED_UNKNOWN, /* 6 */
613 PCI_SPEED_UNKNOWN, /* 7 */
614 PCI_SPEED_UNKNOWN, /* 8 */
615 PCI_SPEED_UNKNOWN, /* 9 */
616 PCI_SPEED_UNKNOWN, /* A */
617 PCI_SPEED_UNKNOWN, /* B */
618 PCI_SPEED_UNKNOWN, /* C */
619 PCI_SPEED_UNKNOWN, /* D */
620 PCI_SPEED_UNKNOWN, /* E */
621 PCI_SPEED_UNKNOWN /* F */
622};
623
624void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
625{
626 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
627}
628EXPORT_SYMBOL_GPL(pcie_update_link_speed);
629
630static unsigned char agp_speeds[] = {
631 AGP_UNKNOWN,
632 AGP_1X,
633 AGP_2X,
634 AGP_4X,
635 AGP_8X
636};
637
638static enum pci_bus_speed agp_speed(int agp3, int agpstat)
639{
640 int index = 0;
641
642 if (agpstat & 4)
643 index = 3;
644 else if (agpstat & 2)
645 index = 2;
646 else if (agpstat & 1)
647 index = 1;
648 else
649 goto out;
650
651 if (agp3) {
652 index += 2;
653 if (index == 5)
654 index = 0;
655 }
656
657 out:
658 return agp_speeds[index];
659}
660
661static void pci_set_bus_speed(struct pci_bus *bus)
662{
663 struct pci_dev *bridge = bus->self;
664 int pos;
665
666 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
667 if (!pos)
668 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
669 if (pos) {
670 u32 agpstat, agpcmd;
671
672 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
673 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
674
675 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
676 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
677 }
678
679 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
680 if (pos) {
681 u16 status;
682 enum pci_bus_speed max;
683
684 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
685 &status);
686
687 if (status & PCI_X_SSTATUS_533MHZ) {
688 max = PCI_SPEED_133MHz_PCIX_533;
689 } else if (status & PCI_X_SSTATUS_266MHZ) {
690 max = PCI_SPEED_133MHz_PCIX_266;
691 } else if (status & PCI_X_SSTATUS_133MHZ) {
692 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
693 max = PCI_SPEED_133MHz_PCIX_ECC;
694 else
695 max = PCI_SPEED_133MHz_PCIX;
696 } else {
697 max = PCI_SPEED_66MHz_PCIX;
698 }
699
700 bus->max_bus_speed = max;
701 bus->cur_bus_speed = pcix_bus_speed[
702 (status & PCI_X_SSTATUS_FREQ) >> 6];
703
704 return;
705 }
706
707 if (pci_is_pcie(bridge)) {
708 u32 linkcap;
709 u16 linksta;
710
711 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
712 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
713
714 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
715 pcie_update_link_speed(bus, linksta);
716 }
717}
718
719static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
720{
721 struct irq_domain *d;
722
723 /*
724 * Any firmware interface that can resolve the msi_domain
725 * should be called from here.
726 */
727 d = pci_host_bridge_of_msi_domain(bus);
728 if (!d)
729 d = pci_host_bridge_acpi_msi_domain(bus);
730
731#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
732 /*
733 * If no IRQ domain was found via the OF tree, try looking it up
734 * directly through the fwnode_handle.
735 */
736 if (!d) {
737 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
738
739 if (fwnode)
740 d = irq_find_matching_fwnode(fwnode,
741 DOMAIN_BUS_PCI_MSI);
742 }
743#endif
744
745 return d;
746}
747
748static void pci_set_bus_msi_domain(struct pci_bus *bus)
749{
750 struct irq_domain *d;
751 struct pci_bus *b;
752
753 /*
754 * The bus can be a root bus, a subordinate bus, or a virtual bus
755 * created by an SR-IOV device. Walk up to the first bridge device
756 * found or derive the domain from the host bridge.
757 */
758 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
759 if (b->self)
760 d = dev_get_msi_domain(&b->self->dev);
761 }
762
763 if (!d)
764 d = pci_host_bridge_msi_domain(b);
765
766 dev_set_msi_domain(&bus->dev, d);
767}
768
769static int pci_register_host_bridge(struct pci_host_bridge *bridge)
770{
771 struct device *parent = bridge->dev.parent;
772 struct resource_entry *window, *n;
773 struct pci_bus *bus, *b;
774 resource_size_t offset;
775 LIST_HEAD(resources);
776 struct resource *res;
777 char addr[64], *fmt;
778 const char *name;
779 int err;
780
781 bus = pci_alloc_bus(NULL);
782 if (!bus)
783 return -ENOMEM;
784
785 bridge->bus = bus;
786
787 /* Temporarily move resources off the list */
788 list_splice_init(&bridge->windows, &resources);
789 bus->sysdata = bridge->sysdata;
790 bus->msi = bridge->msi;
791 bus->ops = bridge->ops;
792 bus->number = bus->busn_res.start = bridge->busnr;
793#ifdef CONFIG_PCI_DOMAINS_GENERIC
794 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
795#endif
796
797 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
798 if (b) {
799 /* Ignore it if we already got here via a different bridge */
800 dev_dbg(&b->dev, "bus already known\n");
801 err = -EEXIST;
802 goto free;
803 }
804
805 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
806 bridge->busnr);
807
808 err = pcibios_root_bridge_prepare(bridge);
809 if (err)
810 goto free;
811
812 err = device_register(&bridge->dev);
813 if (err)
814 put_device(&bridge->dev);
815
816 bus->bridge = get_device(&bridge->dev);
817 device_enable_async_suspend(bus->bridge);
818 pci_set_bus_of_node(bus);
819 pci_set_bus_msi_domain(bus);
820
821 if (!parent)
822 set_dev_node(bus->bridge, pcibus_to_node(bus));
823
824 bus->dev.class = &pcibus_class;
825 bus->dev.parent = bus->bridge;
826
827 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
828 name = dev_name(&bus->dev);
829
830 err = device_register(&bus->dev);
831 if (err)
832 goto unregister;
833
834 pcibios_add_bus(bus);
835
836 /* Create legacy_io and legacy_mem files for this bus */
837 pci_create_legacy_files(bus);
838
839 if (parent)
840 dev_info(parent, "PCI host bridge to bus %s\n", name);
841 else
842 pr_info("PCI host bridge to bus %s\n", name);
843
844 /* Add initial resources to the bus */
845 resource_list_for_each_entry_safe(window, n, &resources) {
846 list_move_tail(&window->node, &bridge->windows);
847 offset = window->offset;
848 res = window->res;
849
850 if (res->flags & IORESOURCE_BUS)
851 pci_bus_insert_busn_res(bus, bus->number, res->end);
852 else
853 pci_bus_add_resource(bus, res, 0);
854
855 if (offset) {
856 if (resource_type(res) == IORESOURCE_IO)
857 fmt = " (bus address [%#06llx-%#06llx])";
858 else
859 fmt = " (bus address [%#010llx-%#010llx])";
860
861 snprintf(addr, sizeof(addr), fmt,
862 (unsigned long long)(res->start - offset),
863 (unsigned long long)(res->end - offset));
864 } else
865 addr[0] = '\0';
866
867 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
868 }
869
870 down_write(&pci_bus_sem);
871 list_add_tail(&bus->node, &pci_root_buses);
872 up_write(&pci_bus_sem);
873
874 return 0;
875
876unregister:
877 put_device(&bridge->dev);
878 device_unregister(&bridge->dev);
879
880free:
881 kfree(bus);
882 return err;
883}
884
885static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
886 struct pci_dev *bridge, int busnr)
887{
888 struct pci_bus *child;
889 int i;
890 int ret;
891
892 /* Allocate a new bus and inherit stuff from the parent */
893 child = pci_alloc_bus(parent);
894 if (!child)
895 return NULL;
896
897 child->parent = parent;
898 child->ops = parent->ops;
899 child->msi = parent->msi;
900 child->sysdata = parent->sysdata;
901 child->bus_flags = parent->bus_flags;
902
903 /*
904 * Initialize some portions of the bus device, but don't register
905 * it now as the parent is not properly set up yet.
906 */
907 child->dev.class = &pcibus_class;
908 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
909
910 /* Set up the primary, secondary and subordinate bus numbers */
911 child->number = child->busn_res.start = busnr;
912 child->primary = parent->busn_res.start;
913 child->busn_res.end = 0xff;
914
915 if (!bridge) {
916 child->dev.parent = parent->bridge;
917 goto add_dev;
918 }
919
920 child->self = bridge;
921 child->bridge = get_device(&bridge->dev);
922 child->dev.parent = child->bridge;
923 pci_set_bus_of_node(child);
924 pci_set_bus_speed(child);
925
926 /* Set up default resource pointers and names */
927 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
928 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
929 child->resource[i]->name = child->name;
930 }
931 bridge->subordinate = child;
932
933add_dev:
934 pci_set_bus_msi_domain(child);
935 ret = device_register(&child->dev);
936 WARN_ON(ret < 0);
937
938 pcibios_add_bus(child);
939
940 if (child->ops->add_bus) {
941 ret = child->ops->add_bus(child);
942 if (WARN_ON(ret < 0))
943 dev_err(&child->dev, "failed to add bus: %d\n", ret);
944 }
945
946 /* Create legacy_io and legacy_mem files for this bus */
947 pci_create_legacy_files(child);
948
949 return child;
950}
951
952struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
953 int busnr)
954{
955 struct pci_bus *child;
956
957 child = pci_alloc_child_bus(parent, dev, busnr);
958 if (child) {
959 down_write(&pci_bus_sem);
960 list_add_tail(&child->node, &parent->children);
961 up_write(&pci_bus_sem);
962 }
963 return child;
964}
965EXPORT_SYMBOL(pci_add_new_bus);
966
967static void pci_enable_crs(struct pci_dev *pdev)
968{
969 u16 root_cap = 0;
970
971 /* Enable CRS Software Visibility if supported */
972 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
973 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
974 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
975 PCI_EXP_RTCTL_CRSSVE);
976}
977
978static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
979 unsigned int available_buses);
980
981/*
982 * pci_scan_bridge_extend() - Scan buses behind a bridge
983 * @bus: Parent bus the bridge is on
984 * @dev: Bridge itself
985 * @max: Starting subordinate number of buses behind this bridge
986 * @available_buses: Total number of buses available for this bridge and
987 * the devices below. After the minimal bus space has
988 * been allocated the remaining buses will be
989 * distributed equally between hotplug-capable bridges.
990 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
991 * that need to be reconfigured.
992 *
993 * If it's a bridge, configure it and scan the bus behind it.
994 * For CardBus bridges, we don't scan behind as the devices will
995 * be handled by the bridge driver itself.
996 *
997 * We need to process bridges in two passes -- first we scan those
998 * already configured by the BIOS and after we are done with all of
999 * them, we proceed to assigning numbers to the remaining buses in
1000 * order to avoid overlaps between old and new bus numbers.
1001 */
1002static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1003 int max, unsigned int available_buses,
1004 int pass)
1005{
1006 struct pci_bus *child;
1007 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1008 u32 buses, i, j = 0;
1009 u16 bctl;
1010 u8 primary, secondary, subordinate;
1011 int broken = 0;
1012
1013 /*
1014 * Make sure the bridge is powered on to be able to access config
1015 * space of devices below it.
1016 */
1017 pm_runtime_get_sync(&dev->dev);
1018
1019 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1020 primary = buses & 0xFF;
1021 secondary = (buses >> 8) & 0xFF;
1022 subordinate = (buses >> 16) & 0xFF;
1023
1024 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1025 secondary, subordinate, pass);
1026
1027 if (!primary && (primary != bus->number) && secondary && subordinate) {
1028 pci_warn(dev, "Primary bus is hard wired to 0\n");
1029 primary = bus->number;
1030 }
1031
1032 /* Check if setup is sensible at all */
1033 if (!pass &&
1034 (primary != bus->number || secondary <= bus->number ||
1035 secondary > subordinate)) {
1036 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1037 secondary, subordinate);
1038 broken = 1;
1039 }
1040
1041 /*
1042 * Disable Master-Abort Mode during probing to avoid reporting of
1043 * bus errors in some architectures.
1044 */
1045 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1046 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1047 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1048
1049 pci_enable_crs(dev);
1050
1051 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1052 !is_cardbus && !broken) {
1053 unsigned int cmax;
1054
1055 /*
1056 * Bus already configured by firmware, process it in the
1057 * first pass and just note the configuration.
1058 */
1059 if (pass)
1060 goto out;
1061
1062 /*
1063 * The bus might already exist for two reasons: Either we
1064 * are rescanning the bus or the bus is reachable through
1065 * more than one bridge. The second case can happen with
1066 * the i450NX chipset.
1067 */
1068 child = pci_find_bus(pci_domain_nr(bus), secondary);
1069 if (!child) {
1070 child = pci_add_new_bus(bus, dev, secondary);
1071 if (!child)
1072 goto out;
1073 child->primary = primary;
1074 pci_bus_insert_busn_res(child, secondary, subordinate);
1075 child->bridge_ctl = bctl;
1076 }
1077
1078 cmax = pci_scan_child_bus(child);
1079 if (cmax > subordinate)
1080 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1081 subordinate, cmax);
1082
1083 /* Subordinate should equal child->busn_res.end */
1084 if (subordinate > max)
1085 max = subordinate;
1086 } else {
1087
1088 /*
1089 * We need to assign a number to this bus which we always
1090 * do in the second pass.
1091 */
1092 if (!pass) {
1093 if (pcibios_assign_all_busses() || broken || is_cardbus)
1094
1095 /*
1096 * Temporarily disable forwarding of the
1097 * configuration cycles on all bridges in
1098 * this bus segment to avoid possible
1099 * conflicts in the second pass between two
1100 * bridges programmed with overlapping bus
1101 * ranges.
1102 */
1103 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1104 buses & ~0xffffff);
1105 goto out;
1106 }
1107
1108 /* Clear errors */
1109 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1110
1111 /*
1112 * Prevent assigning a bus number that already exists.
1113 * This can happen when a bridge is hot-plugged, so in this
1114 * case we only re-scan this bus.
1115 */
1116 child = pci_find_bus(pci_domain_nr(bus), max+1);
1117 if (!child) {
1118 child = pci_add_new_bus(bus, dev, max+1);
1119 if (!child)
1120 goto out;
1121 pci_bus_insert_busn_res(child, max+1,
1122 bus->busn_res.end);
1123 }
1124 max++;
1125 if (available_buses)
1126 available_buses--;
1127
1128 buses = (buses & 0xff000000)
1129 | ((unsigned int)(child->primary) << 0)
1130 | ((unsigned int)(child->busn_res.start) << 8)
1131 | ((unsigned int)(child->busn_res.end) << 16);
1132
1133 /*
1134 * yenta.c forces a secondary latency timer of 176.
1135 * Copy that behaviour here.
1136 */
1137 if (is_cardbus) {
1138 buses &= ~0xff000000;
1139 buses |= CARDBUS_LATENCY_TIMER << 24;
1140 }
1141
1142 /* We need to blast all three values with a single write */
1143 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1144
1145 if (!is_cardbus) {
1146 child->bridge_ctl = bctl;
1147 max = pci_scan_child_bus_extend(child, available_buses);
1148 } else {
1149
1150 /*
1151 * For CardBus bridges, we leave 4 bus numbers as
1152 * cards with a PCI-to-PCI bridge can be inserted
1153 * later.
1154 */
1155 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1156 struct pci_bus *parent = bus;
1157 if (pci_find_bus(pci_domain_nr(bus),
1158 max+i+1))
1159 break;
1160 while (parent->parent) {
1161 if ((!pcibios_assign_all_busses()) &&
1162 (parent->busn_res.end > max) &&
1163 (parent->busn_res.end <= max+i)) {
1164 j = 1;
1165 }
1166 parent = parent->parent;
1167 }
1168 if (j) {
1169
1170 /*
1171 * Often, there are two CardBus
1172 * bridges -- try to leave one
1173 * valid bus number for each one.
1174 */
1175 i /= 2;
1176 break;
1177 }
1178 }
1179 max += i;
1180 }
1181
1182 /* Set subordinate bus number to its real value */
1183 pci_bus_update_busn_res_end(child, max);
1184 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1185 }
1186
1187 sprintf(child->name,
1188 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1189 pci_domain_nr(bus), child->number);
1190
1191 /* Has only triggered on CardBus, fixup is in yenta_socket */
1192 while (bus->parent) {
1193 if ((child->busn_res.end > bus->busn_res.end) ||
1194 (child->number > bus->busn_res.end) ||
1195 (child->number < bus->number) ||
1196 (child->busn_res.end < bus->number)) {
1197 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1198 &child->busn_res,
1199 (bus->number > child->busn_res.end &&
1200 bus->busn_res.end < child->number) ?
1201 "wholly" : "partially",
1202 bus->self->transparent ? " transparent" : "",
1203 dev_name(&bus->dev),
1204 &bus->busn_res);
1205 }
1206 bus = bus->parent;
1207 }
1208
1209out:
1210 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1211
1212 pm_runtime_put(&dev->dev);
1213
1214 return max;
1215}
1216
1217/*
1218 * pci_scan_bridge() - Scan buses behind a bridge
1219 * @bus: Parent bus the bridge is on
1220 * @dev: Bridge itself
1221 * @max: Starting subordinate number of buses behind this bridge
1222 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1223 * that need to be reconfigured.
1224 *
1225 * If it's a bridge, configure it and scan the bus behind it.
1226 * For CardBus bridges, we don't scan behind as the devices will
1227 * be handled by the bridge driver itself.
1228 *
1229 * We need to process bridges in two passes -- first we scan those
1230 * already configured by the BIOS and after we are done with all of
1231 * them, we proceed to assigning numbers to the remaining buses in
1232 * order to avoid overlaps between old and new bus numbers.
1233 */
1234int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1235{
1236 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1237}
1238EXPORT_SYMBOL(pci_scan_bridge);
1239
1240/*
1241 * Read interrupt line and base address registers.
1242 * The architecture-dependent code can tweak these, of course.
1243 */
1244static void pci_read_irq(struct pci_dev *dev)
1245{
1246 unsigned char irq;
1247
1248 /* VFs are not allowed to use INTx, so skip the config reads */
1249 if (dev->is_virtfn) {
1250 dev->pin = 0;
1251 dev->irq = 0;
1252 return;
1253 }
1254
1255 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1256 dev->pin = irq;
1257 if (irq)
1258 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1259 dev->irq = irq;
1260}
1261
1262void set_pcie_port_type(struct pci_dev *pdev)
1263{
1264 int pos;
1265 u16 reg16;
1266 int type;
1267 struct pci_dev *parent;
1268
1269 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1270 if (!pos)
1271 return;
1272
1273 pdev->pcie_cap = pos;
1274 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1275 pdev->pcie_flags_reg = reg16;
1276 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1277 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1278
1279 /*
1280 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1281 * of a Link. No PCIe component has two Links. Two Links are
1282 * connected by a Switch that has a Port on each Link and internal
1283 * logic to connect the two Ports.
1284 */
1285 type = pci_pcie_type(pdev);
1286 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1287 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1288 pdev->has_secondary_link = 1;
1289 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1290 type == PCI_EXP_TYPE_DOWNSTREAM) {
1291 parent = pci_upstream_bridge(pdev);
1292
1293 /*
1294 * Usually there's an upstream device (Root Port or Switch
1295 * Downstream Port), but we can't assume one exists.
1296 */
1297 if (parent && !parent->has_secondary_link)
1298 pdev->has_secondary_link = 1;
1299 }
1300}
1301
1302void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1303{
1304 u32 reg32;
1305
1306 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1307 if (reg32 & PCI_EXP_SLTCAP_HPC)
1308 pdev->is_hotplug_bridge = 1;
1309}
1310
1311static void set_pcie_thunderbolt(struct pci_dev *dev)
1312{
1313 int vsec = 0;
1314 u32 header;
1315
1316 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1317 PCI_EXT_CAP_ID_VNDR))) {
1318 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1319
1320 /* Is the device part of a Thunderbolt controller? */
1321 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1322 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1323 dev->is_thunderbolt = 1;
1324 return;
1325 }
1326 }
1327}
1328
1329/**
1330 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1331 * @dev: PCI device
1332 *
1333 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1334 * when forwarding a type1 configuration request the bridge must check that
1335 * the extended register address field is zero. The bridge is not permitted
1336 * to forward the transactions and must handle it as an Unsupported Request.
1337 * Some bridges do not follow this rule and simply drop the extended register
1338 * bits, resulting in the standard config space being aliased, every 256
1339 * bytes across the entire configuration space. Test for this condition by
1340 * comparing the first dword of each potential alias to the vendor/device ID.
1341 * Known offenders:
1342 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1343 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1344 */
1345static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1346{
1347#ifdef CONFIG_PCI_QUIRKS
1348 int pos;
1349 u32 header, tmp;
1350
1351 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1352
1353 for (pos = PCI_CFG_SPACE_SIZE;
1354 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1355 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1356 || header != tmp)
1357 return false;
1358 }
1359
1360 return true;
1361#else
1362 return false;
1363#endif
1364}
1365
1366/**
1367 * pci_cfg_space_size - Get the configuration space size of the PCI device
1368 * @dev: PCI device
1369 *
1370 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1371 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1372 * access it. Maybe we don't have a way to generate extended config space
1373 * accesses, or the device is behind a reverse Express bridge. So we try
1374 * reading the dword at 0x100 which must either be 0 or a valid extended
1375 * capability header.
1376 */
1377static int pci_cfg_space_size_ext(struct pci_dev *dev)
1378{
1379 u32 status;
1380 int pos = PCI_CFG_SPACE_SIZE;
1381
1382 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1383 return PCI_CFG_SPACE_SIZE;
1384 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1385 return PCI_CFG_SPACE_SIZE;
1386
1387 return PCI_CFG_SPACE_EXP_SIZE;
1388}
1389
1390int pci_cfg_space_size(struct pci_dev *dev)
1391{
1392 int pos;
1393 u32 status;
1394 u16 class;
1395
1396 class = dev->class >> 8;
1397 if (class == PCI_CLASS_BRIDGE_HOST)
1398 return pci_cfg_space_size_ext(dev);
1399
1400 if (pci_is_pcie(dev))
1401 return pci_cfg_space_size_ext(dev);
1402
1403 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1404 if (!pos)
1405 return PCI_CFG_SPACE_SIZE;
1406
1407 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1408 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1409 return pci_cfg_space_size_ext(dev);
1410
1411 return PCI_CFG_SPACE_SIZE;
1412}
1413
1414static u32 pci_class(struct pci_dev *dev)
1415{
1416 u32 class;
1417
1418#ifdef CONFIG_PCI_IOV
1419 if (dev->is_virtfn)
1420 return dev->physfn->sriov->class;
1421#endif
1422 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1423 return class;
1424}
1425
1426static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1427{
1428#ifdef CONFIG_PCI_IOV
1429 if (dev->is_virtfn) {
1430 *vendor = dev->physfn->sriov->subsystem_vendor;
1431 *device = dev->physfn->sriov->subsystem_device;
1432 return;
1433 }
1434#endif
1435 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1436 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1437}
1438
1439static u8 pci_hdr_type(struct pci_dev *dev)
1440{
1441 u8 hdr_type;
1442
1443#ifdef CONFIG_PCI_IOV
1444 if (dev->is_virtfn)
1445 return dev->physfn->sriov->hdr_type;
1446#endif
1447 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1448 return hdr_type;
1449}
1450
1451#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1452
1453static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1454{
1455 /*
1456 * Disable the MSI hardware to avoid screaming interrupts
1457 * during boot. This is the power on reset default so
1458 * usually this should be a noop.
1459 */
1460 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1461 if (dev->msi_cap)
1462 pci_msi_set_enable(dev, 0);
1463
1464 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1465 if (dev->msix_cap)
1466 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1467}
1468
1469/**
1470 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1471 * @dev: PCI device
1472 *
1473 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1474 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1475 */
1476static int pci_intx_mask_broken(struct pci_dev *dev)
1477{
1478 u16 orig, toggle, new;
1479
1480 pci_read_config_word(dev, PCI_COMMAND, &orig);
1481 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1482 pci_write_config_word(dev, PCI_COMMAND, toggle);
1483 pci_read_config_word(dev, PCI_COMMAND, &new);
1484
1485 pci_write_config_word(dev, PCI_COMMAND, orig);
1486
1487 /*
1488 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1489 * r2.3, so strictly speaking, a device is not *broken* if it's not
1490 * writable. But we'll live with the misnomer for now.
1491 */
1492 if (new != toggle)
1493 return 1;
1494 return 0;
1495}
1496
1497/**
1498 * pci_setup_device - Fill in class and map information of a device
1499 * @dev: the device structure to fill
1500 *
1501 * Initialize the device structure with information about the device's
1502 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1503 * Called at initialisation of the PCI subsystem and by CardBus services.
1504 * Returns 0 on success and negative if unknown type of device (not normal,
1505 * bridge or CardBus).
1506 */
1507int pci_setup_device(struct pci_dev *dev)
1508{
1509 u32 class;
1510 u16 cmd;
1511 u8 hdr_type;
1512 int pos = 0;
1513 struct pci_bus_region region;
1514 struct resource *res;
1515
1516 hdr_type = pci_hdr_type(dev);
1517
1518 dev->sysdata = dev->bus->sysdata;
1519 dev->dev.parent = dev->bus->bridge;
1520 dev->dev.bus = &pci_bus_type;
1521 dev->hdr_type = hdr_type & 0x7f;
1522 dev->multifunction = !!(hdr_type & 0x80);
1523 dev->error_state = pci_channel_io_normal;
1524 set_pcie_port_type(dev);
1525
1526 pci_dev_assign_slot(dev);
1527
1528 /*
1529 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1530 * set this higher, assuming the system even supports it.
1531 */
1532 dev->dma_mask = 0xffffffff;
1533
1534 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1535 dev->bus->number, PCI_SLOT(dev->devfn),
1536 PCI_FUNC(dev->devfn));
1537
1538 class = pci_class(dev);
1539
1540 dev->revision = class & 0xff;
1541 dev->class = class >> 8; /* upper 3 bytes */
1542
1543 pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
1544 dev->vendor, dev->device, dev->hdr_type, dev->class);
1545
1546 /* Need to have dev->class ready */
1547 dev->cfg_size = pci_cfg_space_size(dev);
1548
1549 /* Need to have dev->cfg_size ready */
1550 set_pcie_thunderbolt(dev);
1551
1552 /* "Unknown power state" */
1553 dev->current_state = PCI_UNKNOWN;
1554
1555 /* Early fixups, before probing the BARs */
1556 pci_fixup_device(pci_fixup_early, dev);
1557
1558 /* Device class may be changed after fixup */
1559 class = dev->class >> 8;
1560
1561 if (dev->non_compliant_bars) {
1562 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1563 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1564 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1565 cmd &= ~PCI_COMMAND_IO;
1566 cmd &= ~PCI_COMMAND_MEMORY;
1567 pci_write_config_word(dev, PCI_COMMAND, cmd);
1568 }
1569 }
1570
1571 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1572
1573 switch (dev->hdr_type) { /* header type */
1574 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1575 if (class == PCI_CLASS_BRIDGE_PCI)
1576 goto bad;
1577 pci_read_irq(dev);
1578 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1579
1580 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1581
1582 /*
1583 * Do the ugly legacy mode stuff here rather than broken chip
1584 * quirk code. Legacy mode ATA controllers have fixed
1585 * addresses. These are not always echoed in BAR0-3, and
1586 * BAR0-3 in a few cases contain junk!
1587 */
1588 if (class == PCI_CLASS_STORAGE_IDE) {
1589 u8 progif;
1590 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1591 if ((progif & 1) == 0) {
1592 region.start = 0x1F0;
1593 region.end = 0x1F7;
1594 res = &dev->resource[0];
1595 res->flags = LEGACY_IO_RESOURCE;
1596 pcibios_bus_to_resource(dev->bus, res, ®ion);
1597 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1598 res);
1599 region.start = 0x3F6;
1600 region.end = 0x3F6;
1601 res = &dev->resource[1];
1602 res->flags = LEGACY_IO_RESOURCE;
1603 pcibios_bus_to_resource(dev->bus, res, ®ion);
1604 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1605 res);
1606 }
1607 if ((progif & 4) == 0) {
1608 region.start = 0x170;
1609 region.end = 0x177;
1610 res = &dev->resource[2];
1611 res->flags = LEGACY_IO_RESOURCE;
1612 pcibios_bus_to_resource(dev->bus, res, ®ion);
1613 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1614 res);
1615 region.start = 0x376;
1616 region.end = 0x376;
1617 res = &dev->resource[3];
1618 res->flags = LEGACY_IO_RESOURCE;
1619 pcibios_bus_to_resource(dev->bus, res, ®ion);
1620 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1621 res);
1622 }
1623 }
1624 break;
1625
1626 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1627 if (class != PCI_CLASS_BRIDGE_PCI)
1628 goto bad;
1629
1630 /*
1631 * The PCI-to-PCI bridge spec requires that subtractive
1632 * decoding (i.e. transparent) bridge must have programming
1633 * interface code of 0x01.
1634 */
1635 pci_read_irq(dev);
1636 dev->transparent = ((dev->class & 0xff) == 1);
1637 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1638 set_pcie_hotplug_bridge(dev);
1639 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1640 if (pos) {
1641 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1642 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1643 }
1644 break;
1645
1646 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1647 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1648 goto bad;
1649 pci_read_irq(dev);
1650 pci_read_bases(dev, 1, 0);
1651 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1652 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1653 break;
1654
1655 default: /* unknown header */
1656 pci_err(dev, "unknown header type %02x, ignoring device\n",
1657 dev->hdr_type);
1658 return -EIO;
1659
1660 bad:
1661 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1662 dev->class, dev->hdr_type);
1663 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1664 }
1665
1666 /* We found a fine healthy device, go go go... */
1667 return 0;
1668}
1669
1670static void pci_configure_mps(struct pci_dev *dev)
1671{
1672 struct pci_dev *bridge = pci_upstream_bridge(dev);
1673 int mps, p_mps, rc;
1674
1675 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1676 return;
1677
1678 mps = pcie_get_mps(dev);
1679 p_mps = pcie_get_mps(bridge);
1680
1681 if (mps == p_mps)
1682 return;
1683
1684 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1685 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1686 mps, pci_name(bridge), p_mps);
1687 return;
1688 }
1689
1690 /*
1691 * Fancier MPS configuration is done later by
1692 * pcie_bus_configure_settings()
1693 */
1694 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1695 return;
1696
1697 rc = pcie_set_mps(dev, p_mps);
1698 if (rc) {
1699 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1700 p_mps);
1701 return;
1702 }
1703
1704 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
1705 p_mps, mps, 128 << dev->pcie_mpss);
1706}
1707
1708static struct hpp_type0 pci_default_type0 = {
1709 .revision = 1,
1710 .cache_line_size = 8,
1711 .latency_timer = 0x40,
1712 .enable_serr = 0,
1713 .enable_perr = 0,
1714};
1715
1716static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1717{
1718 u16 pci_cmd, pci_bctl;
1719
1720 if (!hpp)
1721 hpp = &pci_default_type0;
1722
1723 if (hpp->revision > 1) {
1724 pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
1725 hpp->revision);
1726 hpp = &pci_default_type0;
1727 }
1728
1729 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1730 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1731 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1732 if (hpp->enable_serr)
1733 pci_cmd |= PCI_COMMAND_SERR;
1734 if (hpp->enable_perr)
1735 pci_cmd |= PCI_COMMAND_PARITY;
1736 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1737
1738 /* Program bridge control value */
1739 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1740 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1741 hpp->latency_timer);
1742 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1743 if (hpp->enable_serr)
1744 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1745 if (hpp->enable_perr)
1746 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1747 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1748 }
1749}
1750
1751static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1752{
1753 int pos;
1754
1755 if (!hpp)
1756 return;
1757
1758 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1759 if (!pos)
1760 return;
1761
1762 pci_warn(dev, "PCI-X settings not supported\n");
1763}
1764
1765static bool pcie_root_rcb_set(struct pci_dev *dev)
1766{
1767 struct pci_dev *rp = pcie_find_root_port(dev);
1768 u16 lnkctl;
1769
1770 if (!rp)
1771 return false;
1772
1773 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1774 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1775 return true;
1776
1777 return false;
1778}
1779
1780static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1781{
1782 int pos;
1783 u32 reg32;
1784
1785 if (!hpp)
1786 return;
1787
1788 if (!pci_is_pcie(dev))
1789 return;
1790
1791 if (hpp->revision > 1) {
1792 pci_warn(dev, "PCIe settings rev %d not supported\n",
1793 hpp->revision);
1794 return;
1795 }
1796
1797 /*
1798 * Don't allow _HPX to change MPS or MRRS settings. We manage
1799 * those to make sure they're consistent with the rest of the
1800 * platform.
1801 */
1802 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1803 PCI_EXP_DEVCTL_READRQ;
1804 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1805 PCI_EXP_DEVCTL_READRQ);
1806
1807 /* Initialize Device Control Register */
1808 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1809 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1810
1811 /* Initialize Link Control Register */
1812 if (pcie_cap_has_lnkctl(dev)) {
1813
1814 /*
1815 * If the Root Port supports Read Completion Boundary of
1816 * 128, set RCB to 128. Otherwise, clear it.
1817 */
1818 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1819 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1820 if (pcie_root_rcb_set(dev))
1821 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1822
1823 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1824 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1825 }
1826
1827 /* Find Advanced Error Reporting Enhanced Capability */
1828 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1829 if (!pos)
1830 return;
1831
1832 /* Initialize Uncorrectable Error Mask Register */
1833 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1834 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1835 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1836
1837 /* Initialize Uncorrectable Error Severity Register */
1838 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1839 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1840 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1841
1842 /* Initialize Correctable Error Mask Register */
1843 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1844 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1845 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1846
1847 /* Initialize Advanced Error Capabilities and Control Register */
1848 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1849 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1850
1851 /* Don't enable ECRC generation or checking if unsupported */
1852 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
1853 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
1854 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
1855 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
1856 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1857
1858 /*
1859 * FIXME: The following two registers are not supported yet.
1860 *
1861 * o Secondary Uncorrectable Error Severity Register
1862 * o Secondary Uncorrectable Error Mask Register
1863 */
1864}
1865
1866int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
1867{
1868 struct pci_host_bridge *host;
1869 u32 cap;
1870 u16 ctl;
1871 int ret;
1872
1873 if (!pci_is_pcie(dev))
1874 return 0;
1875
1876 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
1877 if (ret)
1878 return 0;
1879
1880 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
1881 return 0;
1882
1883 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
1884 if (ret)
1885 return 0;
1886
1887 host = pci_find_host_bridge(dev->bus);
1888 if (!host)
1889 return 0;
1890
1891 /*
1892 * If some device in the hierarchy doesn't handle Extended Tags
1893 * correctly, make sure they're disabled.
1894 */
1895 if (host->no_ext_tags) {
1896 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
1897 pci_info(dev, "disabling Extended Tags\n");
1898 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1899 PCI_EXP_DEVCTL_EXT_TAG);
1900 }
1901 return 0;
1902 }
1903
1904 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
1905 pci_info(dev, "enabling Extended Tags\n");
1906 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
1907 PCI_EXP_DEVCTL_EXT_TAG);
1908 }
1909 return 0;
1910}
1911
1912/**
1913 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
1914 * @dev: PCI device to query
1915 *
1916 * Returns true if the device has enabled relaxed ordering attribute.
1917 */
1918bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
1919{
1920 u16 v;
1921
1922 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
1923
1924 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
1925}
1926EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
1927
1928static void pci_configure_relaxed_ordering(struct pci_dev *dev)
1929{
1930 struct pci_dev *root;
1931
1932 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
1933 if (dev->is_virtfn)
1934 return;
1935
1936 if (!pcie_relaxed_ordering_enabled(dev))
1937 return;
1938
1939 /*
1940 * For now, we only deal with Relaxed Ordering issues with Root
1941 * Ports. Peer-to-Peer DMA is another can of worms.
1942 */
1943 root = pci_find_pcie_root_port(dev);
1944 if (!root)
1945 return;
1946
1947 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
1948 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1949 PCI_EXP_DEVCTL_RELAX_EN);
1950 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
1951 }
1952}
1953
1954static void pci_configure_ltr(struct pci_dev *dev)
1955{
1956#ifdef CONFIG_PCIEASPM
1957 u32 cap;
1958 struct pci_dev *bridge;
1959
1960 if (!pci_is_pcie(dev))
1961 return;
1962
1963 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
1964 if (!(cap & PCI_EXP_DEVCAP2_LTR))
1965 return;
1966
1967 /*
1968 * Software must not enable LTR in an Endpoint unless the Root
1969 * Complex and all intermediate Switches indicate support for LTR.
1970 * PCIe r3.1, sec 6.18.
1971 */
1972 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1973 dev->ltr_path = 1;
1974 else {
1975 bridge = pci_upstream_bridge(dev);
1976 if (bridge && bridge->ltr_path)
1977 dev->ltr_path = 1;
1978 }
1979
1980 if (dev->ltr_path)
1981 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
1982 PCI_EXP_DEVCTL2_LTR_EN);
1983#endif
1984}
1985
1986static void pci_configure_device(struct pci_dev *dev)
1987{
1988 struct hotplug_params hpp;
1989 int ret;
1990
1991 pci_configure_mps(dev);
1992 pci_configure_extended_tags(dev, NULL);
1993 pci_configure_relaxed_ordering(dev);
1994 pci_configure_ltr(dev);
1995
1996 memset(&hpp, 0, sizeof(hpp));
1997 ret = pci_get_hp_params(dev, &hpp);
1998 if (ret)
1999 return;
2000
2001 program_hpp_type2(dev, hpp.t2);
2002 program_hpp_type1(dev, hpp.t1);
2003 program_hpp_type0(dev, hpp.t0);
2004}
2005
2006static void pci_release_capabilities(struct pci_dev *dev)
2007{
2008 pci_vpd_release(dev);
2009 pci_iov_release(dev);
2010 pci_free_cap_save_buffers(dev);
2011}
2012
2013/**
2014 * pci_release_dev - Free a PCI device structure when all users of it are
2015 * finished
2016 * @dev: device that's been disconnected
2017 *
2018 * Will be called only by the device core when all users of this PCI device are
2019 * done.
2020 */
2021static void pci_release_dev(struct device *dev)
2022{
2023 struct pci_dev *pci_dev;
2024
2025 pci_dev = to_pci_dev(dev);
2026 pci_release_capabilities(pci_dev);
2027 pci_release_of_node(pci_dev);
2028 pcibios_release_device(pci_dev);
2029 pci_bus_put(pci_dev->bus);
2030 kfree(pci_dev->driver_override);
2031 kfree(pci_dev->dma_alias_mask);
2032 kfree(pci_dev);
2033}
2034
2035struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2036{
2037 struct pci_dev *dev;
2038
2039 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2040 if (!dev)
2041 return NULL;
2042
2043 INIT_LIST_HEAD(&dev->bus_list);
2044 dev->dev.type = &pci_dev_type;
2045 dev->bus = pci_bus_get(bus);
2046
2047 return dev;
2048}
2049EXPORT_SYMBOL(pci_alloc_dev);
2050
2051static bool pci_bus_crs_vendor_id(u32 l)
2052{
2053 return (l & 0xffff) == 0x0001;
2054}
2055
2056static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2057 int timeout)
2058{
2059 int delay = 1;
2060
2061 if (!pci_bus_crs_vendor_id(*l))
2062 return true; /* not a CRS completion */
2063
2064 if (!timeout)
2065 return false; /* CRS, but caller doesn't want to wait */
2066
2067 /*
2068 * We got the reserved Vendor ID that indicates a completion with
2069 * Configuration Request Retry Status (CRS). Retry until we get a
2070 * valid Vendor ID or we time out.
2071 */
2072 while (pci_bus_crs_vendor_id(*l)) {
2073 if (delay > timeout) {
2074 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2075 pci_domain_nr(bus), bus->number,
2076 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2077
2078 return false;
2079 }
2080 if (delay >= 1000)
2081 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2082 pci_domain_nr(bus), bus->number,
2083 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2084
2085 msleep(delay);
2086 delay *= 2;
2087
2088 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2089 return false;
2090 }
2091
2092 if (delay >= 1000)
2093 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2094 pci_domain_nr(bus), bus->number,
2095 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2096
2097 return true;
2098}
2099
2100bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2101 int timeout)
2102{
2103 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2104 return false;
2105
2106 /* Some broken boards return 0 or ~0 if a slot is empty: */
2107 if (*l == 0xffffffff || *l == 0x00000000 ||
2108 *l == 0x0000ffff || *l == 0xffff0000)
2109 return false;
2110
2111 if (pci_bus_crs_vendor_id(*l))
2112 return pci_bus_wait_crs(bus, devfn, l, timeout);
2113
2114 return true;
2115}
2116EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2117
2118/*
2119 * Read the config data for a PCI device, sanity-check it,
2120 * and fill in the dev structure.
2121 */
2122static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2123{
2124 struct pci_dev *dev;
2125 u32 l;
2126
2127 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2128 return NULL;
2129
2130 dev = pci_alloc_dev(bus);
2131 if (!dev)
2132 return NULL;
2133
2134 dev->devfn = devfn;
2135 dev->vendor = l & 0xffff;
2136 dev->device = (l >> 16) & 0xffff;
2137
2138 pci_set_of_node(dev);
2139
2140 if (pci_setup_device(dev)) {
2141 pci_bus_put(dev->bus);
2142 kfree(dev);
2143 return NULL;
2144 }
2145
2146 return dev;
2147}
2148
2149static void pci_init_capabilities(struct pci_dev *dev)
2150{
2151 /* Enhanced Allocation */
2152 pci_ea_init(dev);
2153
2154 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2155 pci_msi_setup_pci_dev(dev);
2156
2157 /* Buffers for saving PCIe and PCI-X capabilities */
2158 pci_allocate_cap_save_buffers(dev);
2159
2160 /* Power Management */
2161 pci_pm_init(dev);
2162
2163 /* Vital Product Data */
2164 pci_vpd_init(dev);
2165
2166 /* Alternative Routing-ID Forwarding */
2167 pci_configure_ari(dev);
2168
2169 /* Single Root I/O Virtualization */
2170 pci_iov_init(dev);
2171
2172 /* Address Translation Services */
2173 pci_ats_init(dev);
2174
2175 /* Enable ACS P2P upstream forwarding */
2176 pci_enable_acs(dev);
2177
2178 /* Precision Time Measurement */
2179 pci_ptm_init(dev);
2180
2181 /* Advanced Error Reporting */
2182 pci_aer_init(dev);
2183
2184 if (pci_probe_reset_function(dev) == 0)
2185 dev->reset_fn = 1;
2186}
2187
2188/*
2189 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2190 * devices. Firmware interfaces that can select the MSI domain on a
2191 * per-device basis should be called from here.
2192 */
2193static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2194{
2195 struct irq_domain *d;
2196
2197 /*
2198 * If a domain has been set through the pcibios_add_device()
2199 * callback, then this is the one (platform code knows best).
2200 */
2201 d = dev_get_msi_domain(&dev->dev);
2202 if (d)
2203 return d;
2204
2205 /*
2206 * Let's see if we have a firmware interface able to provide
2207 * the domain.
2208 */
2209 d = pci_msi_get_device_domain(dev);
2210 if (d)
2211 return d;
2212
2213 return NULL;
2214}
2215
2216static void pci_set_msi_domain(struct pci_dev *dev)
2217{
2218 struct irq_domain *d;
2219
2220 /*
2221 * If the platform or firmware interfaces cannot supply a
2222 * device-specific MSI domain, then inherit the default domain
2223 * from the host bridge itself.
2224 */
2225 d = pci_dev_msi_domain(dev);
2226 if (!d)
2227 d = dev_get_msi_domain(&dev->bus->dev);
2228
2229 dev_set_msi_domain(&dev->dev, d);
2230}
2231
2232void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2233{
2234 int ret;
2235
2236 pci_configure_device(dev);
2237
2238 device_initialize(&dev->dev);
2239 dev->dev.release = pci_release_dev;
2240
2241 set_dev_node(&dev->dev, pcibus_to_node(bus));
2242 dev->dev.dma_mask = &dev->dma_mask;
2243 dev->dev.dma_parms = &dev->dma_parms;
2244 dev->dev.coherent_dma_mask = 0xffffffffull;
2245
2246 pci_set_dma_max_seg_size(dev, 65536);
2247 pci_set_dma_seg_boundary(dev, 0xffffffff);
2248
2249 /* Fix up broken headers */
2250 pci_fixup_device(pci_fixup_header, dev);
2251
2252 /* Moved out from quirk header fixup code */
2253 pci_reassigndev_resource_alignment(dev);
2254
2255 /* Clear the state_saved flag */
2256 dev->state_saved = false;
2257
2258 /* Initialize various capabilities */
2259 pci_init_capabilities(dev);
2260
2261 /*
2262 * Add the device to our list of discovered devices
2263 * and the bus list for fixup functions, etc.
2264 */
2265 down_write(&pci_bus_sem);
2266 list_add_tail(&dev->bus_list, &bus->devices);
2267 up_write(&pci_bus_sem);
2268
2269 ret = pcibios_add_device(dev);
2270 WARN_ON(ret < 0);
2271
2272 /* Set up MSI IRQ domain */
2273 pci_set_msi_domain(dev);
2274
2275 /* Notifier could use PCI capabilities */
2276 dev->match_driver = false;
2277 ret = device_add(&dev->dev);
2278 WARN_ON(ret < 0);
2279}
2280
2281struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2282{
2283 struct pci_dev *dev;
2284
2285 dev = pci_get_slot(bus, devfn);
2286 if (dev) {
2287 pci_dev_put(dev);
2288 return dev;
2289 }
2290
2291 dev = pci_scan_device(bus, devfn);
2292 if (!dev)
2293 return NULL;
2294
2295 pci_device_add(dev, bus);
2296
2297 return dev;
2298}
2299EXPORT_SYMBOL(pci_scan_single_device);
2300
2301static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2302{
2303 int pos;
2304 u16 cap = 0;
2305 unsigned next_fn;
2306
2307 if (pci_ari_enabled(bus)) {
2308 if (!dev)
2309 return 0;
2310 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2311 if (!pos)
2312 return 0;
2313
2314 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2315 next_fn = PCI_ARI_CAP_NFN(cap);
2316 if (next_fn <= fn)
2317 return 0; /* protect against malformed list */
2318
2319 return next_fn;
2320 }
2321
2322 /* dev may be NULL for non-contiguous multifunction devices */
2323 if (!dev || dev->multifunction)
2324 return (fn + 1) % 8;
2325
2326 return 0;
2327}
2328
2329static int only_one_child(struct pci_bus *bus)
2330{
2331 struct pci_dev *bridge = bus->self;
2332
2333 /*
2334 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2335 * we scan for all possible devices, not just Device 0.
2336 */
2337 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2338 return 0;
2339
2340 /*
2341 * A PCIe Downstream Port normally leads to a Link with only Device
2342 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2343 * only for Device 0 in that situation.
2344 *
2345 * Checking has_secondary_link is a hack to identify Downstream
2346 * Ports because sometimes Switches are configured such that the
2347 * PCIe Port Type labels are backwards.
2348 */
2349 if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
2350 return 1;
2351
2352 return 0;
2353}
2354
2355/**
2356 * pci_scan_slot - Scan a PCI slot on a bus for devices
2357 * @bus: PCI bus to scan
2358 * @devfn: slot number to scan (must have zero function)
2359 *
2360 * Scan a PCI slot on the specified PCI bus for devices, adding
2361 * discovered devices to the @bus->devices list. New devices
2362 * will not have is_added set.
2363 *
2364 * Returns the number of new devices found.
2365 */
2366int pci_scan_slot(struct pci_bus *bus, int devfn)
2367{
2368 unsigned fn, nr = 0;
2369 struct pci_dev *dev;
2370
2371 if (only_one_child(bus) && (devfn > 0))
2372 return 0; /* Already scanned the entire slot */
2373
2374 dev = pci_scan_single_device(bus, devfn);
2375 if (!dev)
2376 return 0;
2377 if (!dev->is_added)
2378 nr++;
2379
2380 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2381 dev = pci_scan_single_device(bus, devfn + fn);
2382 if (dev) {
2383 if (!dev->is_added)
2384 nr++;
2385 dev->multifunction = 1;
2386 }
2387 }
2388
2389 /* Only one slot has PCIe device */
2390 if (bus->self && nr)
2391 pcie_aspm_init_link_state(bus->self);
2392
2393 return nr;
2394}
2395EXPORT_SYMBOL(pci_scan_slot);
2396
2397static int pcie_find_smpss(struct pci_dev *dev, void *data)
2398{
2399 u8 *smpss = data;
2400
2401 if (!pci_is_pcie(dev))
2402 return 0;
2403
2404 /*
2405 * We don't have a way to change MPS settings on devices that have
2406 * drivers attached. A hot-added device might support only the minimum
2407 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2408 * where devices may be hot-added, we limit the fabric MPS to 128 so
2409 * hot-added devices will work correctly.
2410 *
2411 * However, if we hot-add a device to a slot directly below a Root
2412 * Port, it's impossible for there to be other existing devices below
2413 * the port. We don't limit the MPS in this case because we can
2414 * reconfigure MPS on both the Root Port and the hot-added device,
2415 * and there are no other devices involved.
2416 *
2417 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2418 */
2419 if (dev->is_hotplug_bridge &&
2420 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2421 *smpss = 0;
2422
2423 if (*smpss > dev->pcie_mpss)
2424 *smpss = dev->pcie_mpss;
2425
2426 return 0;
2427}
2428
2429static void pcie_write_mps(struct pci_dev *dev, int mps)
2430{
2431 int rc;
2432
2433 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2434 mps = 128 << dev->pcie_mpss;
2435
2436 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2437 dev->bus->self)
2438
2439 /*
2440 * For "Performance", the assumption is made that
2441 * downstream communication will never be larger than
2442 * the MRRS. So, the MPS only needs to be configured
2443 * for the upstream communication. This being the case,
2444 * walk from the top down and set the MPS of the child
2445 * to that of the parent bus.
2446 *
2447 * Configure the device MPS with the smaller of the
2448 * device MPSS or the bridge MPS (which is assumed to be
2449 * properly configured at this point to the largest
2450 * allowable MPS based on its parent bus).
2451 */
2452 mps = min(mps, pcie_get_mps(dev->bus->self));
2453 }
2454
2455 rc = pcie_set_mps(dev, mps);
2456 if (rc)
2457 pci_err(dev, "Failed attempting to set the MPS\n");
2458}
2459
2460static void pcie_write_mrrs(struct pci_dev *dev)
2461{
2462 int rc, mrrs;
2463
2464 /*
2465 * In the "safe" case, do not configure the MRRS. There appear to be
2466 * issues with setting MRRS to 0 on a number of devices.
2467 */
2468 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2469 return;
2470
2471 /*
2472 * For max performance, the MRRS must be set to the largest supported
2473 * value. However, it cannot be configured larger than the MPS the
2474 * device or the bus can support. This should already be properly
2475 * configured by a prior call to pcie_write_mps().
2476 */
2477 mrrs = pcie_get_mps(dev);
2478
2479 /*
2480 * MRRS is a R/W register. Invalid values can be written, but a
2481 * subsequent read will verify if the value is acceptable or not.
2482 * If the MRRS value provided is not acceptable (e.g., too large),
2483 * shrink the value until it is acceptable to the HW.
2484 */
2485 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2486 rc = pcie_set_readrq(dev, mrrs);
2487 if (!rc)
2488 break;
2489
2490 pci_warn(dev, "Failed attempting to set the MRRS\n");
2491 mrrs /= 2;
2492 }
2493
2494 if (mrrs < 128)
2495 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2496}
2497
2498static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2499{
2500 int mps, orig_mps;
2501
2502 if (!pci_is_pcie(dev))
2503 return 0;
2504
2505 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2506 pcie_bus_config == PCIE_BUS_DEFAULT)
2507 return 0;
2508
2509 mps = 128 << *(u8 *)data;
2510 orig_mps = pcie_get_mps(dev);
2511
2512 pcie_write_mps(dev, mps);
2513 pcie_write_mrrs(dev);
2514
2515 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2516 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2517 orig_mps, pcie_get_readrq(dev));
2518
2519 return 0;
2520}
2521
2522/*
2523 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2524 * parents then children fashion. If this changes, then this code will not
2525 * work as designed.
2526 */
2527void pcie_bus_configure_settings(struct pci_bus *bus)
2528{
2529 u8 smpss = 0;
2530
2531 if (!bus->self)
2532 return;
2533
2534 if (!pci_is_pcie(bus->self))
2535 return;
2536
2537 /*
2538 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2539 * to be aware of the MPS of the destination. To work around this,
2540 * simply force the MPS of the entire system to the smallest possible.
2541 */
2542 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2543 smpss = 0;
2544
2545 if (pcie_bus_config == PCIE_BUS_SAFE) {
2546 smpss = bus->self->pcie_mpss;
2547
2548 pcie_find_smpss(bus->self, &smpss);
2549 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2550 }
2551
2552 pcie_bus_configure_set(bus->self, &smpss);
2553 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2554}
2555EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2556
2557/*
2558 * Called after each bus is probed, but before its children are examined. This
2559 * is marked as __weak because multiple architectures define it.
2560 */
2561void __weak pcibios_fixup_bus(struct pci_bus *bus)
2562{
2563 /* nothing to do, expected to be removed in the future */
2564}
2565
2566/**
2567 * pci_scan_child_bus_extend() - Scan devices below a bus
2568 * @bus: Bus to scan for devices
2569 * @available_buses: Total number of buses available (%0 does not try to
2570 * extend beyond the minimal)
2571 *
2572 * Scans devices below @bus including subordinate buses. Returns new
2573 * subordinate number including all the found devices. Passing
2574 * @available_buses causes the remaining bus space to be distributed
2575 * equally between hotplug-capable bridges to allow future extension of the
2576 * hierarchy.
2577 */
2578static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2579 unsigned int available_buses)
2580{
2581 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2582 unsigned int start = bus->busn_res.start;
2583 unsigned int devfn, fn, cmax, max = start;
2584 struct pci_dev *dev;
2585 int nr_devs;
2586
2587 dev_dbg(&bus->dev, "scanning bus\n");
2588
2589 /* Go find them, Rover! */
2590 for (devfn = 0; devfn < 256; devfn += 8) {
2591 nr_devs = pci_scan_slot(bus, devfn);
2592
2593 /*
2594 * The Jailhouse hypervisor may pass individual functions of a
2595 * multi-function device to a guest without passing function 0.
2596 * Look for them as well.
2597 */
2598 if (jailhouse_paravirt() && nr_devs == 0) {
2599 for (fn = 1; fn < 8; fn++) {
2600 dev = pci_scan_single_device(bus, devfn + fn);
2601 if (dev)
2602 dev->multifunction = 1;
2603 }
2604 }
2605 }
2606
2607 /* Reserve buses for SR-IOV capability */
2608 used_buses = pci_iov_bus_range(bus);
2609 max += used_buses;
2610
2611 /*
2612 * After performing arch-dependent fixup of the bus, look behind
2613 * all PCI-to-PCI bridges on this bus.
2614 */
2615 if (!bus->is_added) {
2616 dev_dbg(&bus->dev, "fixups for bus\n");
2617 pcibios_fixup_bus(bus);
2618 bus->is_added = 1;
2619 }
2620
2621 /*
2622 * Calculate how many hotplug bridges and normal bridges there
2623 * are on this bus. We will distribute the additional available
2624 * buses between hotplug bridges.
2625 */
2626 for_each_pci_bridge(dev, bus) {
2627 if (dev->is_hotplug_bridge)
2628 hotplug_bridges++;
2629 else
2630 normal_bridges++;
2631 }
2632
2633 /*
2634 * Scan bridges that are already configured. We don't touch them
2635 * unless they are misconfigured (which will be done in the second
2636 * scan below).
2637 */
2638 for_each_pci_bridge(dev, bus) {
2639 cmax = max;
2640 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2641 used_buses += cmax - max;
2642 }
2643
2644 /* Scan bridges that need to be reconfigured */
2645 for_each_pci_bridge(dev, bus) {
2646 unsigned int buses = 0;
2647
2648 if (!hotplug_bridges && normal_bridges == 1) {
2649
2650 /*
2651 * There is only one bridge on the bus (upstream
2652 * port) so it gets all available buses which it
2653 * can then distribute to the possible hotplug
2654 * bridges below.
2655 */
2656 buses = available_buses;
2657 } else if (dev->is_hotplug_bridge) {
2658
2659 /*
2660 * Distribute the extra buses between hotplug
2661 * bridges if any.
2662 */
2663 buses = available_buses / hotplug_bridges;
2664 buses = min(buses, available_buses - used_buses);
2665 }
2666
2667 cmax = max;
2668 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2669 used_buses += max - cmax;
2670 }
2671
2672 /*
2673 * Make sure a hotplug bridge has at least the minimum requested
2674 * number of buses but allow it to grow up to the maximum available
2675 * bus number of there is room.
2676 */
2677 if (bus->self && bus->self->is_hotplug_bridge) {
2678 used_buses = max_t(unsigned int, available_buses,
2679 pci_hotplug_bus_size - 1);
2680 if (max - start < used_buses) {
2681 max = start + used_buses;
2682
2683 /* Do not allocate more buses than we have room left */
2684 if (max > bus->busn_res.end)
2685 max = bus->busn_res.end;
2686
2687 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2688 &bus->busn_res, max - start);
2689 }
2690 }
2691
2692 /*
2693 * We've scanned the bus and so we know all about what's on
2694 * the other side of any bridges that may be on this bus plus
2695 * any devices.
2696 *
2697 * Return how far we've got finding sub-buses.
2698 */
2699 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2700 return max;
2701}
2702
2703/**
2704 * pci_scan_child_bus() - Scan devices below a bus
2705 * @bus: Bus to scan for devices
2706 *
2707 * Scans devices below @bus including subordinate buses. Returns new
2708 * subordinate number including all the found devices.
2709 */
2710unsigned int pci_scan_child_bus(struct pci_bus *bus)
2711{
2712 return pci_scan_child_bus_extend(bus, 0);
2713}
2714EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2715
2716/**
2717 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2718 * @bridge: Host bridge to set up
2719 *
2720 * Default empty implementation. Replace with an architecture-specific setup
2721 * routine, if necessary.
2722 */
2723int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2724{
2725 return 0;
2726}
2727
2728void __weak pcibios_add_bus(struct pci_bus *bus)
2729{
2730}
2731
2732void __weak pcibios_remove_bus(struct pci_bus *bus)
2733{
2734}
2735
2736struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2737 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2738{
2739 int error;
2740 struct pci_host_bridge *bridge;
2741
2742 bridge = pci_alloc_host_bridge(0);
2743 if (!bridge)
2744 return NULL;
2745
2746 bridge->dev.parent = parent;
2747
2748 list_splice_init(resources, &bridge->windows);
2749 bridge->sysdata = sysdata;
2750 bridge->busnr = bus;
2751 bridge->ops = ops;
2752
2753 error = pci_register_host_bridge(bridge);
2754 if (error < 0)
2755 goto err_out;
2756
2757 return bridge->bus;
2758
2759err_out:
2760 kfree(bridge);
2761 return NULL;
2762}
2763EXPORT_SYMBOL_GPL(pci_create_root_bus);
2764
2765int pci_host_probe(struct pci_host_bridge *bridge)
2766{
2767 struct pci_bus *bus, *child;
2768 int ret;
2769
2770 ret = pci_scan_root_bus_bridge(bridge);
2771 if (ret < 0) {
2772 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2773 return ret;
2774 }
2775
2776 bus = bridge->bus;
2777
2778 /*
2779 * We insert PCI resources into the iomem_resource and
2780 * ioport_resource trees in either pci_bus_claim_resources()
2781 * or pci_bus_assign_resources().
2782 */
2783 if (pci_has_flag(PCI_PROBE_ONLY)) {
2784 pci_bus_claim_resources(bus);
2785 } else {
2786 pci_bus_size_bridges(bus);
2787 pci_bus_assign_resources(bus);
2788
2789 list_for_each_entry(child, &bus->children, node)
2790 pcie_bus_configure_settings(child);
2791 }
2792
2793 pci_bus_add_devices(bus);
2794 return 0;
2795}
2796EXPORT_SYMBOL_GPL(pci_host_probe);
2797
2798int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2799{
2800 struct resource *res = &b->busn_res;
2801 struct resource *parent_res, *conflict;
2802
2803 res->start = bus;
2804 res->end = bus_max;
2805 res->flags = IORESOURCE_BUS;
2806
2807 if (!pci_is_root_bus(b))
2808 parent_res = &b->parent->busn_res;
2809 else {
2810 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2811 res->flags |= IORESOURCE_PCI_FIXED;
2812 }
2813
2814 conflict = request_resource_conflict(parent_res, res);
2815
2816 if (conflict)
2817 dev_printk(KERN_DEBUG, &b->dev,
2818 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2819 res, pci_is_root_bus(b) ? "domain " : "",
2820 parent_res, conflict->name, conflict);
2821
2822 return conflict == NULL;
2823}
2824
2825int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2826{
2827 struct resource *res = &b->busn_res;
2828 struct resource old_res = *res;
2829 resource_size_t size;
2830 int ret;
2831
2832 if (res->start > bus_max)
2833 return -EINVAL;
2834
2835 size = bus_max - res->start + 1;
2836 ret = adjust_resource(res, res->start, size);
2837 dev_printk(KERN_DEBUG, &b->dev,
2838 "busn_res: %pR end %s updated to %02x\n",
2839 &old_res, ret ? "can not be" : "is", bus_max);
2840
2841 if (!ret && !res->parent)
2842 pci_bus_insert_busn_res(b, res->start, res->end);
2843
2844 return ret;
2845}
2846
2847void pci_bus_release_busn_res(struct pci_bus *b)
2848{
2849 struct resource *res = &b->busn_res;
2850 int ret;
2851
2852 if (!res->flags || !res->parent)
2853 return;
2854
2855 ret = release_resource(res);
2856 dev_printk(KERN_DEBUG, &b->dev,
2857 "busn_res: %pR %s released\n",
2858 res, ret ? "can not be" : "is");
2859}
2860
2861int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
2862{
2863 struct resource_entry *window;
2864 bool found = false;
2865 struct pci_bus *b;
2866 int max, bus, ret;
2867
2868 if (!bridge)
2869 return -EINVAL;
2870
2871 resource_list_for_each_entry(window, &bridge->windows)
2872 if (window->res->flags & IORESOURCE_BUS) {
2873 found = true;
2874 break;
2875 }
2876
2877 ret = pci_register_host_bridge(bridge);
2878 if (ret < 0)
2879 return ret;
2880
2881 b = bridge->bus;
2882 bus = bridge->busnr;
2883
2884 if (!found) {
2885 dev_info(&b->dev,
2886 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2887 bus);
2888 pci_bus_insert_busn_res(b, bus, 255);
2889 }
2890
2891 max = pci_scan_child_bus(b);
2892
2893 if (!found)
2894 pci_bus_update_busn_res_end(b, max);
2895
2896 return 0;
2897}
2898EXPORT_SYMBOL(pci_scan_root_bus_bridge);
2899
2900struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2901 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2902{
2903 struct resource_entry *window;
2904 bool found = false;
2905 struct pci_bus *b;
2906 int max;
2907
2908 resource_list_for_each_entry(window, resources)
2909 if (window->res->flags & IORESOURCE_BUS) {
2910 found = true;
2911 break;
2912 }
2913
2914 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2915 if (!b)
2916 return NULL;
2917
2918 if (!found) {
2919 dev_info(&b->dev,
2920 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2921 bus);
2922 pci_bus_insert_busn_res(b, bus, 255);
2923 }
2924
2925 max = pci_scan_child_bus(b);
2926
2927 if (!found)
2928 pci_bus_update_busn_res_end(b, max);
2929
2930 return b;
2931}
2932EXPORT_SYMBOL(pci_scan_root_bus);
2933
2934struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2935 void *sysdata)
2936{
2937 LIST_HEAD(resources);
2938 struct pci_bus *b;
2939
2940 pci_add_resource(&resources, &ioport_resource);
2941 pci_add_resource(&resources, &iomem_resource);
2942 pci_add_resource(&resources, &busn_resource);
2943 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2944 if (b) {
2945 pci_scan_child_bus(b);
2946 } else {
2947 pci_free_resource_list(&resources);
2948 }
2949 return b;
2950}
2951EXPORT_SYMBOL(pci_scan_bus);
2952
2953/**
2954 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
2955 * @bridge: PCI bridge for the bus to scan
2956 *
2957 * Scan a PCI bus and child buses for new devices, add them,
2958 * and enable them, resizing bridge mmio/io resource if necessary
2959 * and possible. The caller must ensure the child devices are already
2960 * removed for resizing to occur.
2961 *
2962 * Returns the max number of subordinate bus discovered.
2963 */
2964unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2965{
2966 unsigned int max;
2967 struct pci_bus *bus = bridge->subordinate;
2968
2969 max = pci_scan_child_bus(bus);
2970
2971 pci_assign_unassigned_bridge_resources(bridge);
2972
2973 pci_bus_add_devices(bus);
2974
2975 return max;
2976}
2977
2978/**
2979 * pci_rescan_bus - Scan a PCI bus for devices
2980 * @bus: PCI bus to scan
2981 *
2982 * Scan a PCI bus and child buses for new devices, add them,
2983 * and enable them.
2984 *
2985 * Returns the max number of subordinate bus discovered.
2986 */
2987unsigned int pci_rescan_bus(struct pci_bus *bus)
2988{
2989 unsigned int max;
2990
2991 max = pci_scan_child_bus(bus);
2992 pci_assign_unassigned_bus_resources(bus);
2993 pci_bus_add_devices(bus);
2994
2995 return max;
2996}
2997EXPORT_SYMBOL_GPL(pci_rescan_bus);
2998
2999/*
3000 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3001 * routines should always be executed under this mutex.
3002 */
3003static DEFINE_MUTEX(pci_rescan_remove_lock);
3004
3005void pci_lock_rescan_remove(void)
3006{
3007 mutex_lock(&pci_rescan_remove_lock);
3008}
3009EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3010
3011void pci_unlock_rescan_remove(void)
3012{
3013 mutex_unlock(&pci_rescan_remove_lock);
3014}
3015EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3016
3017static int __init pci_sort_bf_cmp(const struct device *d_a,
3018 const struct device *d_b)
3019{
3020 const struct pci_dev *a = to_pci_dev(d_a);
3021 const struct pci_dev *b = to_pci_dev(d_b);
3022
3023 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3024 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3025
3026 if (a->bus->number < b->bus->number) return -1;
3027 else if (a->bus->number > b->bus->number) return 1;
3028
3029 if (a->devfn < b->devfn) return -1;
3030 else if (a->devfn > b->devfn) return 1;
3031
3032 return 0;
3033}
3034
3035void __init pci_sort_breadthfirst(void)
3036{
3037 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3038}
3039
3040int pci_hp_add_bridge(struct pci_dev *dev)
3041{
3042 struct pci_bus *parent = dev->bus;
3043 int busnr, start = parent->busn_res.start;
3044 unsigned int available_buses = 0;
3045 int end = parent->busn_res.end;
3046
3047 for (busnr = start; busnr <= end; busnr++) {
3048 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3049 break;
3050 }
3051 if (busnr-- > end) {
3052 pci_err(dev, "No bus number available for hot-added bridge\n");
3053 return -1;
3054 }
3055
3056 /* Scan bridges that are already configured */
3057 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3058
3059 /*
3060 * Distribute the available bus numbers between hotplug-capable
3061 * bridges to make extending the chain later possible.
3062 */
3063 available_buses = end - busnr;
3064
3065 /* Scan bridges that need to be reconfigured */
3066 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3067
3068 if (!dev->subordinate)
3069 return -1;
3070
3071 return 0;
3072}
3073EXPORT_SYMBOL_GPL(pci_hp_add_bridge);