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1/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
12#include <linux/pci-aspm.h>
13#include "pci.h"
14
15#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16#define CARDBUS_RESERVE_BUSNR 3
17
18/* Ugh. Need to stop exporting this to modules. */
19LIST_HEAD(pci_root_buses);
20EXPORT_SYMBOL(pci_root_buses);
21
22
23static int find_anything(struct device *dev, void *data)
24{
25 return 1;
26}
27
28/*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33int no_pci_devices(void)
34{
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42}
43EXPORT_SYMBOL(no_pci_devices);
44
45/*
46 * PCI Bus Class
47 */
48static void release_pcibus_dev(struct device *dev)
49{
50 struct pci_bus *pci_bus = to_pci_bus(dev);
51
52 if (pci_bus->bridge)
53 put_device(pci_bus->bridge);
54 pci_bus_remove_resources(pci_bus);
55 pci_release_bus_of_node(pci_bus);
56 kfree(pci_bus);
57}
58
59static struct class pcibus_class = {
60 .name = "pci_bus",
61 .dev_release = &release_pcibus_dev,
62 .dev_attrs = pcibus_dev_attrs,
63};
64
65static int __init pcibus_class_init(void)
66{
67 return class_register(&pcibus_class);
68}
69postcore_initcall(pcibus_class_init);
70
71static u64 pci_size(u64 base, u64 maxbase, u64 mask)
72{
73 u64 size = mask & maxbase; /* Find the significant bits */
74 if (!size)
75 return 0;
76
77 /* Get the lowest of them to find the decode size, and
78 from that the extent. */
79 size = (size & ~(size-1)) - 1;
80
81 /* base == maxbase can be valid only if the BAR has
82 already been programmed with all 1s. */
83 if (base == maxbase && ((base | size) & mask) != mask)
84 return 0;
85
86 return size;
87}
88
89static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
90{
91 u32 mem_type;
92 unsigned long flags;
93
94 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
95 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
96 flags |= IORESOURCE_IO;
97 return flags;
98 }
99
100 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
101 flags |= IORESOURCE_MEM;
102 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
103 flags |= IORESOURCE_PREFETCH;
104
105 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
106 switch (mem_type) {
107 case PCI_BASE_ADDRESS_MEM_TYPE_32:
108 break;
109 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
110 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
111 break;
112 case PCI_BASE_ADDRESS_MEM_TYPE_64:
113 flags |= IORESOURCE_MEM_64;
114 break;
115 default:
116 dev_warn(&dev->dev,
117 "mem unknown type %x treated as 32-bit BAR\n",
118 mem_type);
119 break;
120 }
121 return flags;
122}
123
124/**
125 * pci_read_base - read a PCI BAR
126 * @dev: the PCI device
127 * @type: type of the BAR
128 * @res: resource buffer to be filled in
129 * @pos: BAR position in the config space
130 *
131 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
132 */
133int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
134 struct resource *res, unsigned int pos)
135{
136 u32 l, sz, mask;
137 u16 orig_cmd;
138
139 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
140
141 if (!dev->mmio_always_on) {
142 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
143 pci_write_config_word(dev, PCI_COMMAND,
144 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
145 }
146
147 res->name = pci_name(dev);
148
149 pci_read_config_dword(dev, pos, &l);
150 pci_write_config_dword(dev, pos, l | mask);
151 pci_read_config_dword(dev, pos, &sz);
152 pci_write_config_dword(dev, pos, l);
153
154 if (!dev->mmio_always_on)
155 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
156
157 /*
158 * All bits set in sz means the device isn't working properly.
159 * If the BAR isn't implemented, all bits must be 0. If it's a
160 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
161 * 1 must be clear.
162 */
163 if (!sz || sz == 0xffffffff)
164 goto fail;
165
166 /*
167 * I don't know how l can have all bits set. Copied from old code.
168 * Maybe it fixes a bug on some ancient platform.
169 */
170 if (l == 0xffffffff)
171 l = 0;
172
173 if (type == pci_bar_unknown) {
174 res->flags = decode_bar(dev, l);
175 res->flags |= IORESOURCE_SIZEALIGN;
176 if (res->flags & IORESOURCE_IO) {
177 l &= PCI_BASE_ADDRESS_IO_MASK;
178 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
179 } else {
180 l &= PCI_BASE_ADDRESS_MEM_MASK;
181 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
182 }
183 } else {
184 res->flags |= (l & IORESOURCE_ROM_ENABLE);
185 l &= PCI_ROM_ADDRESS_MASK;
186 mask = (u32)PCI_ROM_ADDRESS_MASK;
187 }
188
189 if (res->flags & IORESOURCE_MEM_64) {
190 u64 l64 = l;
191 u64 sz64 = sz;
192 u64 mask64 = mask | (u64)~0 << 32;
193
194 pci_read_config_dword(dev, pos + 4, &l);
195 pci_write_config_dword(dev, pos + 4, ~0);
196 pci_read_config_dword(dev, pos + 4, &sz);
197 pci_write_config_dword(dev, pos + 4, l);
198
199 l64 |= ((u64)l << 32);
200 sz64 |= ((u64)sz << 32);
201
202 sz64 = pci_size(l64, sz64, mask64);
203
204 if (!sz64)
205 goto fail;
206
207 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
208 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
209 pos);
210 goto fail;
211 }
212
213 if ((sizeof(resource_size_t) < 8) && l) {
214 /* Address above 32-bit boundary; disable the BAR */
215 pci_write_config_dword(dev, pos, 0);
216 pci_write_config_dword(dev, pos + 4, 0);
217 res->start = 0;
218 res->end = sz64;
219 } else {
220 res->start = l64;
221 res->end = l64 + sz64;
222 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
223 pos, res);
224 }
225 } else {
226 sz = pci_size(l, sz, mask);
227
228 if (!sz)
229 goto fail;
230
231 res->start = l;
232 res->end = l + sz;
233
234 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
235 }
236
237 out:
238 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
239 fail:
240 res->flags = 0;
241 goto out;
242}
243
244static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
245{
246 unsigned int pos, reg;
247
248 for (pos = 0; pos < howmany; pos++) {
249 struct resource *res = &dev->resource[pos];
250 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
251 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
252 }
253
254 if (rom) {
255 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
256 dev->rom_base_reg = rom;
257 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
258 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
259 IORESOURCE_SIZEALIGN;
260 __pci_read_base(dev, pci_bar_mem32, res, rom);
261 }
262}
263
264static void __devinit pci_read_bridge_io(struct pci_bus *child)
265{
266 struct pci_dev *dev = child->self;
267 u8 io_base_lo, io_limit_lo;
268 unsigned long base, limit;
269 struct resource *res;
270
271 res = child->resource[0];
272 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
273 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
274 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
275 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
276
277 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
278 u16 io_base_hi, io_limit_hi;
279 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
280 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
281 base |= (io_base_hi << 16);
282 limit |= (io_limit_hi << 16);
283 }
284
285 if (base && base <= limit) {
286 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
287 if (!res->start)
288 res->start = base;
289 if (!res->end)
290 res->end = limit + 0xfff;
291 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
292 }
293}
294
295static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
296{
297 struct pci_dev *dev = child->self;
298 u16 mem_base_lo, mem_limit_lo;
299 unsigned long base, limit;
300 struct resource *res;
301
302 res = child->resource[1];
303 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
304 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
305 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
306 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
307 if (base && base <= limit) {
308 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
309 res->start = base;
310 res->end = limit + 0xfffff;
311 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
312 }
313}
314
315static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
316{
317 struct pci_dev *dev = child->self;
318 u16 mem_base_lo, mem_limit_lo;
319 unsigned long base, limit;
320 struct resource *res;
321
322 res = child->resource[2];
323 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
324 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
325 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
326 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
327
328 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
329 u32 mem_base_hi, mem_limit_hi;
330 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
331 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
332
333 /*
334 * Some bridges set the base > limit by default, and some
335 * (broken) BIOSes do not initialize them. If we find
336 * this, just assume they are not being used.
337 */
338 if (mem_base_hi <= mem_limit_hi) {
339#if BITS_PER_LONG == 64
340 base |= ((long) mem_base_hi) << 32;
341 limit |= ((long) mem_limit_hi) << 32;
342#else
343 if (mem_base_hi || mem_limit_hi) {
344 dev_err(&dev->dev, "can't handle 64-bit "
345 "address space for bridge\n");
346 return;
347 }
348#endif
349 }
350 }
351 if (base && base <= limit) {
352 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
353 IORESOURCE_MEM | IORESOURCE_PREFETCH;
354 if (res->flags & PCI_PREF_RANGE_TYPE_64)
355 res->flags |= IORESOURCE_MEM_64;
356 res->start = base;
357 res->end = limit + 0xfffff;
358 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
359 }
360}
361
362void __devinit pci_read_bridge_bases(struct pci_bus *child)
363{
364 struct pci_dev *dev = child->self;
365 struct resource *res;
366 int i;
367
368 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
369 return;
370
371 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
372 child->secondary, child->subordinate,
373 dev->transparent ? " (subtractive decode)" : "");
374
375 pci_bus_remove_resources(child);
376 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
377 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
378
379 pci_read_bridge_io(child);
380 pci_read_bridge_mmio(child);
381 pci_read_bridge_mmio_pref(child);
382
383 if (dev->transparent) {
384 pci_bus_for_each_resource(child->parent, res, i) {
385 if (res) {
386 pci_bus_add_resource(child, res,
387 PCI_SUBTRACTIVE_DECODE);
388 dev_printk(KERN_DEBUG, &dev->dev,
389 " bridge window %pR (subtractive decode)\n",
390 res);
391 }
392 }
393 }
394}
395
396static struct pci_bus * pci_alloc_bus(void)
397{
398 struct pci_bus *b;
399
400 b = kzalloc(sizeof(*b), GFP_KERNEL);
401 if (b) {
402 INIT_LIST_HEAD(&b->node);
403 INIT_LIST_HEAD(&b->children);
404 INIT_LIST_HEAD(&b->devices);
405 INIT_LIST_HEAD(&b->slots);
406 INIT_LIST_HEAD(&b->resources);
407 b->max_bus_speed = PCI_SPEED_UNKNOWN;
408 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
409 }
410 return b;
411}
412
413static unsigned char pcix_bus_speed[] = {
414 PCI_SPEED_UNKNOWN, /* 0 */
415 PCI_SPEED_66MHz_PCIX, /* 1 */
416 PCI_SPEED_100MHz_PCIX, /* 2 */
417 PCI_SPEED_133MHz_PCIX, /* 3 */
418 PCI_SPEED_UNKNOWN, /* 4 */
419 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
420 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
421 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
422 PCI_SPEED_UNKNOWN, /* 8 */
423 PCI_SPEED_66MHz_PCIX_266, /* 9 */
424 PCI_SPEED_100MHz_PCIX_266, /* A */
425 PCI_SPEED_133MHz_PCIX_266, /* B */
426 PCI_SPEED_UNKNOWN, /* C */
427 PCI_SPEED_66MHz_PCIX_533, /* D */
428 PCI_SPEED_100MHz_PCIX_533, /* E */
429 PCI_SPEED_133MHz_PCIX_533 /* F */
430};
431
432static unsigned char pcie_link_speed[] = {
433 PCI_SPEED_UNKNOWN, /* 0 */
434 PCIE_SPEED_2_5GT, /* 1 */
435 PCIE_SPEED_5_0GT, /* 2 */
436 PCIE_SPEED_8_0GT, /* 3 */
437 PCI_SPEED_UNKNOWN, /* 4 */
438 PCI_SPEED_UNKNOWN, /* 5 */
439 PCI_SPEED_UNKNOWN, /* 6 */
440 PCI_SPEED_UNKNOWN, /* 7 */
441 PCI_SPEED_UNKNOWN, /* 8 */
442 PCI_SPEED_UNKNOWN, /* 9 */
443 PCI_SPEED_UNKNOWN, /* A */
444 PCI_SPEED_UNKNOWN, /* B */
445 PCI_SPEED_UNKNOWN, /* C */
446 PCI_SPEED_UNKNOWN, /* D */
447 PCI_SPEED_UNKNOWN, /* E */
448 PCI_SPEED_UNKNOWN /* F */
449};
450
451void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
452{
453 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
454}
455EXPORT_SYMBOL_GPL(pcie_update_link_speed);
456
457static unsigned char agp_speeds[] = {
458 AGP_UNKNOWN,
459 AGP_1X,
460 AGP_2X,
461 AGP_4X,
462 AGP_8X
463};
464
465static enum pci_bus_speed agp_speed(int agp3, int agpstat)
466{
467 int index = 0;
468
469 if (agpstat & 4)
470 index = 3;
471 else if (agpstat & 2)
472 index = 2;
473 else if (agpstat & 1)
474 index = 1;
475 else
476 goto out;
477
478 if (agp3) {
479 index += 2;
480 if (index == 5)
481 index = 0;
482 }
483
484 out:
485 return agp_speeds[index];
486}
487
488
489static void pci_set_bus_speed(struct pci_bus *bus)
490{
491 struct pci_dev *bridge = bus->self;
492 int pos;
493
494 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
495 if (!pos)
496 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
497 if (pos) {
498 u32 agpstat, agpcmd;
499
500 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
501 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
502
503 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
504 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
505 }
506
507 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
508 if (pos) {
509 u16 status;
510 enum pci_bus_speed max;
511 pci_read_config_word(bridge, pos + 2, &status);
512
513 if (status & 0x8000) {
514 max = PCI_SPEED_133MHz_PCIX_533;
515 } else if (status & 0x4000) {
516 max = PCI_SPEED_133MHz_PCIX_266;
517 } else if (status & 0x0002) {
518 if (((status >> 12) & 0x3) == 2) {
519 max = PCI_SPEED_133MHz_PCIX_ECC;
520 } else {
521 max = PCI_SPEED_133MHz_PCIX;
522 }
523 } else {
524 max = PCI_SPEED_66MHz_PCIX;
525 }
526
527 bus->max_bus_speed = max;
528 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
529
530 return;
531 }
532
533 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
534 if (pos) {
535 u32 linkcap;
536 u16 linksta;
537
538 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
539 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
540
541 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
542 pcie_update_link_speed(bus, linksta);
543 }
544}
545
546
547static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
548 struct pci_dev *bridge, int busnr)
549{
550 struct pci_bus *child;
551 int i;
552
553 /*
554 * Allocate a new bus, and inherit stuff from the parent..
555 */
556 child = pci_alloc_bus();
557 if (!child)
558 return NULL;
559
560 child->parent = parent;
561 child->ops = parent->ops;
562 child->sysdata = parent->sysdata;
563 child->bus_flags = parent->bus_flags;
564
565 /* initialize some portions of the bus device, but don't register it
566 * now as the parent is not properly set up yet. This device will get
567 * registered later in pci_bus_add_devices()
568 */
569 child->dev.class = &pcibus_class;
570 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
571
572 /*
573 * Set up the primary, secondary and subordinate
574 * bus numbers.
575 */
576 child->number = child->secondary = busnr;
577 child->primary = parent->secondary;
578 child->subordinate = 0xff;
579
580 if (!bridge)
581 return child;
582
583 child->self = bridge;
584 child->bridge = get_device(&bridge->dev);
585 pci_set_bus_of_node(child);
586 pci_set_bus_speed(child);
587
588 /* Set up default resource pointers and names.. */
589 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
590 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
591 child->resource[i]->name = child->name;
592 }
593 bridge->subordinate = child;
594
595 return child;
596}
597
598struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
599{
600 struct pci_bus *child;
601
602 child = pci_alloc_child_bus(parent, dev, busnr);
603 if (child) {
604 down_write(&pci_bus_sem);
605 list_add_tail(&child->node, &parent->children);
606 up_write(&pci_bus_sem);
607 }
608 return child;
609}
610
611static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
612{
613 struct pci_bus *parent = child->parent;
614
615 /* Attempts to fix that up are really dangerous unless
616 we're going to re-assign all bus numbers. */
617 if (!pcibios_assign_all_busses())
618 return;
619
620 while (parent->parent && parent->subordinate < max) {
621 parent->subordinate = max;
622 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
623 parent = parent->parent;
624 }
625}
626
627/*
628 * If it's a bridge, configure it and scan the bus behind it.
629 * For CardBus bridges, we don't scan behind as the devices will
630 * be handled by the bridge driver itself.
631 *
632 * We need to process bridges in two passes -- first we scan those
633 * already configured by the BIOS and after we are done with all of
634 * them, we proceed to assigning numbers to the remaining buses in
635 * order to avoid overlaps between old and new bus numbers.
636 */
637int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
638{
639 struct pci_bus *child;
640 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
641 u32 buses, i, j = 0;
642 u16 bctl;
643 u8 primary, secondary, subordinate;
644 int broken = 0;
645
646 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
647 primary = buses & 0xFF;
648 secondary = (buses >> 8) & 0xFF;
649 subordinate = (buses >> 16) & 0xFF;
650
651 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
652 secondary, subordinate, pass);
653
654 /* Check if setup is sensible at all */
655 if (!pass &&
656 (primary != bus->number || secondary <= bus->number)) {
657 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
658 broken = 1;
659 }
660
661 /* Disable MasterAbortMode during probing to avoid reporting
662 of bus errors (in some architectures) */
663 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
664 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
665 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
666
667 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
668 !is_cardbus && !broken) {
669 unsigned int cmax;
670 /*
671 * Bus already configured by firmware, process it in the first
672 * pass and just note the configuration.
673 */
674 if (pass)
675 goto out;
676
677 /*
678 * If we already got to this bus through a different bridge,
679 * don't re-add it. This can happen with the i450NX chipset.
680 *
681 * However, we continue to descend down the hierarchy and
682 * scan remaining child buses.
683 */
684 child = pci_find_bus(pci_domain_nr(bus), secondary);
685 if (!child) {
686 child = pci_add_new_bus(bus, dev, secondary);
687 if (!child)
688 goto out;
689 child->primary = primary;
690 child->subordinate = subordinate;
691 child->bridge_ctl = bctl;
692 }
693
694 cmax = pci_scan_child_bus(child);
695 if (cmax > max)
696 max = cmax;
697 if (child->subordinate > max)
698 max = child->subordinate;
699 } else {
700 /*
701 * We need to assign a number to this bus which we always
702 * do in the second pass.
703 */
704 if (!pass) {
705 if (pcibios_assign_all_busses() || broken)
706 /* Temporarily disable forwarding of the
707 configuration cycles on all bridges in
708 this bus segment to avoid possible
709 conflicts in the second pass between two
710 bridges programmed with overlapping
711 bus ranges. */
712 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
713 buses & ~0xffffff);
714 goto out;
715 }
716
717 /* Clear errors */
718 pci_write_config_word(dev, PCI_STATUS, 0xffff);
719
720 /* Prevent assigning a bus number that already exists.
721 * This can happen when a bridge is hot-plugged, so in
722 * this case we only re-scan this bus. */
723 child = pci_find_bus(pci_domain_nr(bus), max+1);
724 if (!child) {
725 child = pci_add_new_bus(bus, dev, ++max);
726 if (!child)
727 goto out;
728 }
729 buses = (buses & 0xff000000)
730 | ((unsigned int)(child->primary) << 0)
731 | ((unsigned int)(child->secondary) << 8)
732 | ((unsigned int)(child->subordinate) << 16);
733
734 /*
735 * yenta.c forces a secondary latency timer of 176.
736 * Copy that behaviour here.
737 */
738 if (is_cardbus) {
739 buses &= ~0xff000000;
740 buses |= CARDBUS_LATENCY_TIMER << 24;
741 }
742
743 /*
744 * We need to blast all three values with a single write.
745 */
746 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
747
748 if (!is_cardbus) {
749 child->bridge_ctl = bctl;
750 /*
751 * Adjust subordinate busnr in parent buses.
752 * We do this before scanning for children because
753 * some devices may not be detected if the bios
754 * was lazy.
755 */
756 pci_fixup_parent_subordinate_busnr(child, max);
757 /* Now we can scan all subordinate buses... */
758 max = pci_scan_child_bus(child);
759 /*
760 * now fix it up again since we have found
761 * the real value of max.
762 */
763 pci_fixup_parent_subordinate_busnr(child, max);
764 } else {
765 /*
766 * For CardBus bridges, we leave 4 bus numbers
767 * as cards with a PCI-to-PCI bridge can be
768 * inserted later.
769 */
770 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
771 struct pci_bus *parent = bus;
772 if (pci_find_bus(pci_domain_nr(bus),
773 max+i+1))
774 break;
775 while (parent->parent) {
776 if ((!pcibios_assign_all_busses()) &&
777 (parent->subordinate > max) &&
778 (parent->subordinate <= max+i)) {
779 j = 1;
780 }
781 parent = parent->parent;
782 }
783 if (j) {
784 /*
785 * Often, there are two cardbus bridges
786 * -- try to leave one valid bus number
787 * for each one.
788 */
789 i /= 2;
790 break;
791 }
792 }
793 max += i;
794 pci_fixup_parent_subordinate_busnr(child, max);
795 }
796 /*
797 * Set the subordinate bus number to its real value.
798 */
799 child->subordinate = max;
800 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
801 }
802
803 sprintf(child->name,
804 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
805 pci_domain_nr(bus), child->number);
806
807 /* Has only triggered on CardBus, fixup is in yenta_socket */
808 while (bus->parent) {
809 if ((child->subordinate > bus->subordinate) ||
810 (child->number > bus->subordinate) ||
811 (child->number < bus->number) ||
812 (child->subordinate < bus->number)) {
813 dev_info(&child->dev, "[bus %02x-%02x] %s "
814 "hidden behind%s bridge %s [bus %02x-%02x]\n",
815 child->number, child->subordinate,
816 (bus->number > child->subordinate &&
817 bus->subordinate < child->number) ?
818 "wholly" : "partially",
819 bus->self->transparent ? " transparent" : "",
820 dev_name(&bus->dev),
821 bus->number, bus->subordinate);
822 }
823 bus = bus->parent;
824 }
825
826out:
827 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
828
829 return max;
830}
831
832/*
833 * Read interrupt line and base address registers.
834 * The architecture-dependent code can tweak these, of course.
835 */
836static void pci_read_irq(struct pci_dev *dev)
837{
838 unsigned char irq;
839
840 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
841 dev->pin = irq;
842 if (irq)
843 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
844 dev->irq = irq;
845}
846
847void set_pcie_port_type(struct pci_dev *pdev)
848{
849 int pos;
850 u16 reg16;
851
852 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
853 if (!pos)
854 return;
855 pdev->is_pcie = 1;
856 pdev->pcie_cap = pos;
857 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
858 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
859 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
860 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
861}
862
863void set_pcie_hotplug_bridge(struct pci_dev *pdev)
864{
865 int pos;
866 u16 reg16;
867 u32 reg32;
868
869 pos = pci_pcie_cap(pdev);
870 if (!pos)
871 return;
872 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
873 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
874 return;
875 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);
876 if (reg32 & PCI_EXP_SLTCAP_HPC)
877 pdev->is_hotplug_bridge = 1;
878}
879
880#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
881
882/**
883 * pci_setup_device - fill in class and map information of a device
884 * @dev: the device structure to fill
885 *
886 * Initialize the device structure with information about the device's
887 * vendor,class,memory and IO-space addresses,IRQ lines etc.
888 * Called at initialisation of the PCI subsystem and by CardBus services.
889 * Returns 0 on success and negative if unknown type of device (not normal,
890 * bridge or CardBus).
891 */
892int pci_setup_device(struct pci_dev *dev)
893{
894 u32 class;
895 u8 hdr_type;
896 struct pci_slot *slot;
897 int pos = 0;
898
899 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
900 return -EIO;
901
902 dev->sysdata = dev->bus->sysdata;
903 dev->dev.parent = dev->bus->bridge;
904 dev->dev.bus = &pci_bus_type;
905 dev->hdr_type = hdr_type & 0x7f;
906 dev->multifunction = !!(hdr_type & 0x80);
907 dev->error_state = pci_channel_io_normal;
908 set_pcie_port_type(dev);
909
910 list_for_each_entry(slot, &dev->bus->slots, list)
911 if (PCI_SLOT(dev->devfn) == slot->number)
912 dev->slot = slot;
913
914 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
915 set this higher, assuming the system even supports it. */
916 dev->dma_mask = 0xffffffff;
917
918 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
919 dev->bus->number, PCI_SLOT(dev->devfn),
920 PCI_FUNC(dev->devfn));
921
922 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
923 dev->revision = class & 0xff;
924 class >>= 8; /* upper 3 bytes */
925 dev->class = class;
926 class >>= 8;
927
928 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
929 dev->vendor, dev->device, dev->hdr_type, class);
930
931 /* need to have dev->class ready */
932 dev->cfg_size = pci_cfg_space_size(dev);
933
934 /* "Unknown power state" */
935 dev->current_state = PCI_UNKNOWN;
936
937 /* Early fixups, before probing the BARs */
938 pci_fixup_device(pci_fixup_early, dev);
939 /* device class may be changed after fixup */
940 class = dev->class >> 8;
941
942 switch (dev->hdr_type) { /* header type */
943 case PCI_HEADER_TYPE_NORMAL: /* standard header */
944 if (class == PCI_CLASS_BRIDGE_PCI)
945 goto bad;
946 pci_read_irq(dev);
947 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
948 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
949 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
950
951 /*
952 * Do the ugly legacy mode stuff here rather than broken chip
953 * quirk code. Legacy mode ATA controllers have fixed
954 * addresses. These are not always echoed in BAR0-3, and
955 * BAR0-3 in a few cases contain junk!
956 */
957 if (class == PCI_CLASS_STORAGE_IDE) {
958 u8 progif;
959 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
960 if ((progif & 1) == 0) {
961 dev->resource[0].start = 0x1F0;
962 dev->resource[0].end = 0x1F7;
963 dev->resource[0].flags = LEGACY_IO_RESOURCE;
964 dev->resource[1].start = 0x3F6;
965 dev->resource[1].end = 0x3F6;
966 dev->resource[1].flags = LEGACY_IO_RESOURCE;
967 }
968 if ((progif & 4) == 0) {
969 dev->resource[2].start = 0x170;
970 dev->resource[2].end = 0x177;
971 dev->resource[2].flags = LEGACY_IO_RESOURCE;
972 dev->resource[3].start = 0x376;
973 dev->resource[3].end = 0x376;
974 dev->resource[3].flags = LEGACY_IO_RESOURCE;
975 }
976 }
977 break;
978
979 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
980 if (class != PCI_CLASS_BRIDGE_PCI)
981 goto bad;
982 /* The PCI-to-PCI bridge spec requires that subtractive
983 decoding (i.e. transparent) bridge must have programming
984 interface code of 0x01. */
985 pci_read_irq(dev);
986 dev->transparent = ((dev->class & 0xff) == 1);
987 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
988 set_pcie_hotplug_bridge(dev);
989 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
990 if (pos) {
991 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
992 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
993 }
994 break;
995
996 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
997 if (class != PCI_CLASS_BRIDGE_CARDBUS)
998 goto bad;
999 pci_read_irq(dev);
1000 pci_read_bases(dev, 1, 0);
1001 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1002 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1003 break;
1004
1005 default: /* unknown header */
1006 dev_err(&dev->dev, "unknown header type %02x, "
1007 "ignoring device\n", dev->hdr_type);
1008 return -EIO;
1009
1010 bad:
1011 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1012 "type %02x)\n", class, dev->hdr_type);
1013 dev->class = PCI_CLASS_NOT_DEFINED;
1014 }
1015
1016 /* We found a fine healthy device, go go go... */
1017 return 0;
1018}
1019
1020static void pci_release_capabilities(struct pci_dev *dev)
1021{
1022 pci_vpd_release(dev);
1023 pci_iov_release(dev);
1024}
1025
1026/**
1027 * pci_release_dev - free a pci device structure when all users of it are finished.
1028 * @dev: device that's been disconnected
1029 *
1030 * Will be called only by the device core when all users of this pci device are
1031 * done.
1032 */
1033static void pci_release_dev(struct device *dev)
1034{
1035 struct pci_dev *pci_dev;
1036
1037 pci_dev = to_pci_dev(dev);
1038 pci_release_capabilities(pci_dev);
1039 pci_release_of_node(pci_dev);
1040 kfree(pci_dev);
1041}
1042
1043/**
1044 * pci_cfg_space_size - get the configuration space size of the PCI device.
1045 * @dev: PCI device
1046 *
1047 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1048 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1049 * access it. Maybe we don't have a way to generate extended config space
1050 * accesses, or the device is behind a reverse Express bridge. So we try
1051 * reading the dword at 0x100 which must either be 0 or a valid extended
1052 * capability header.
1053 */
1054int pci_cfg_space_size_ext(struct pci_dev *dev)
1055{
1056 u32 status;
1057 int pos = PCI_CFG_SPACE_SIZE;
1058
1059 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1060 goto fail;
1061 if (status == 0xffffffff)
1062 goto fail;
1063
1064 return PCI_CFG_SPACE_EXP_SIZE;
1065
1066 fail:
1067 return PCI_CFG_SPACE_SIZE;
1068}
1069
1070int pci_cfg_space_size(struct pci_dev *dev)
1071{
1072 int pos;
1073 u32 status;
1074 u16 class;
1075
1076 class = dev->class >> 8;
1077 if (class == PCI_CLASS_BRIDGE_HOST)
1078 return pci_cfg_space_size_ext(dev);
1079
1080 pos = pci_pcie_cap(dev);
1081 if (!pos) {
1082 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1083 if (!pos)
1084 goto fail;
1085
1086 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1087 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1088 goto fail;
1089 }
1090
1091 return pci_cfg_space_size_ext(dev);
1092
1093 fail:
1094 return PCI_CFG_SPACE_SIZE;
1095}
1096
1097static void pci_release_bus_bridge_dev(struct device *dev)
1098{
1099 kfree(dev);
1100}
1101
1102struct pci_dev *alloc_pci_dev(void)
1103{
1104 struct pci_dev *dev;
1105
1106 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1107 if (!dev)
1108 return NULL;
1109
1110 INIT_LIST_HEAD(&dev->bus_list);
1111
1112 return dev;
1113}
1114EXPORT_SYMBOL(alloc_pci_dev);
1115
1116/*
1117 * Read the config data for a PCI device, sanity-check it
1118 * and fill in the dev structure...
1119 */
1120static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1121{
1122 struct pci_dev *dev;
1123 u32 l;
1124 int delay = 1;
1125
1126 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1127 return NULL;
1128
1129 /* some broken boards return 0 or ~0 if a slot is empty: */
1130 if (l == 0xffffffff || l == 0x00000000 ||
1131 l == 0x0000ffff || l == 0xffff0000)
1132 return NULL;
1133
1134 /* Configuration request Retry Status */
1135 while (l == 0xffff0001) {
1136 msleep(delay);
1137 delay *= 2;
1138 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1139 return NULL;
1140 /* Card hasn't responded in 60 seconds? Must be stuck. */
1141 if (delay > 60 * 1000) {
1142 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1143 "responding\n", pci_domain_nr(bus),
1144 bus->number, PCI_SLOT(devfn),
1145 PCI_FUNC(devfn));
1146 return NULL;
1147 }
1148 }
1149
1150 dev = alloc_pci_dev();
1151 if (!dev)
1152 return NULL;
1153
1154 dev->bus = bus;
1155 dev->devfn = devfn;
1156 dev->vendor = l & 0xffff;
1157 dev->device = (l >> 16) & 0xffff;
1158
1159 pci_set_of_node(dev);
1160
1161 if (pci_setup_device(dev)) {
1162 kfree(dev);
1163 return NULL;
1164 }
1165
1166 return dev;
1167}
1168
1169static void pci_init_capabilities(struct pci_dev *dev)
1170{
1171 /* MSI/MSI-X list */
1172 pci_msi_init_pci_dev(dev);
1173
1174 /* Buffers for saving PCIe and PCI-X capabilities */
1175 pci_allocate_cap_save_buffers(dev);
1176
1177 /* Power Management */
1178 pci_pm_init(dev);
1179 platform_pci_wakeup_init(dev);
1180
1181 /* Vital Product Data */
1182 pci_vpd_pci22_init(dev);
1183
1184 /* Alternative Routing-ID Forwarding */
1185 pci_enable_ari(dev);
1186
1187 /* Single Root I/O Virtualization */
1188 pci_iov_init(dev);
1189
1190 /* Enable ACS P2P upstream forwarding */
1191 pci_enable_acs(dev);
1192}
1193
1194void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1195{
1196 device_initialize(&dev->dev);
1197 dev->dev.release = pci_release_dev;
1198 pci_dev_get(dev);
1199
1200 dev->dev.dma_mask = &dev->dma_mask;
1201 dev->dev.dma_parms = &dev->dma_parms;
1202 dev->dev.coherent_dma_mask = 0xffffffffull;
1203
1204 pci_set_dma_max_seg_size(dev, 65536);
1205 pci_set_dma_seg_boundary(dev, 0xffffffff);
1206
1207 /* Fix up broken headers */
1208 pci_fixup_device(pci_fixup_header, dev);
1209
1210 /* Clear the state_saved flag. */
1211 dev->state_saved = false;
1212
1213 /* Initialize various capabilities */
1214 pci_init_capabilities(dev);
1215
1216 /*
1217 * Add the device to our list of discovered devices
1218 * and the bus list for fixup functions, etc.
1219 */
1220 down_write(&pci_bus_sem);
1221 list_add_tail(&dev->bus_list, &bus->devices);
1222 up_write(&pci_bus_sem);
1223}
1224
1225struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1226{
1227 struct pci_dev *dev;
1228
1229 dev = pci_get_slot(bus, devfn);
1230 if (dev) {
1231 pci_dev_put(dev);
1232 return dev;
1233 }
1234
1235 dev = pci_scan_device(bus, devfn);
1236 if (!dev)
1237 return NULL;
1238
1239 pci_device_add(dev, bus);
1240
1241 return dev;
1242}
1243EXPORT_SYMBOL(pci_scan_single_device);
1244
1245static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1246{
1247 u16 cap;
1248 unsigned pos, next_fn;
1249
1250 if (!dev)
1251 return 0;
1252
1253 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1254 if (!pos)
1255 return 0;
1256 pci_read_config_word(dev, pos + 4, &cap);
1257 next_fn = cap >> 8;
1258 if (next_fn <= fn)
1259 return 0;
1260 return next_fn;
1261}
1262
1263static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1264{
1265 return (fn + 1) % 8;
1266}
1267
1268static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1269{
1270 return 0;
1271}
1272
1273static int only_one_child(struct pci_bus *bus)
1274{
1275 struct pci_dev *parent = bus->self;
1276 if (!parent || !pci_is_pcie(parent))
1277 return 0;
1278 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1279 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1280 return 1;
1281 return 0;
1282}
1283
1284/**
1285 * pci_scan_slot - scan a PCI slot on a bus for devices.
1286 * @bus: PCI bus to scan
1287 * @devfn: slot number to scan (must have zero function.)
1288 *
1289 * Scan a PCI slot on the specified PCI bus for devices, adding
1290 * discovered devices to the @bus->devices list. New devices
1291 * will not have is_added set.
1292 *
1293 * Returns the number of new devices found.
1294 */
1295int pci_scan_slot(struct pci_bus *bus, int devfn)
1296{
1297 unsigned fn, nr = 0;
1298 struct pci_dev *dev;
1299 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1300
1301 if (only_one_child(bus) && (devfn > 0))
1302 return 0; /* Already scanned the entire slot */
1303
1304 dev = pci_scan_single_device(bus, devfn);
1305 if (!dev)
1306 return 0;
1307 if (!dev->is_added)
1308 nr++;
1309
1310 if (pci_ari_enabled(bus))
1311 next_fn = next_ari_fn;
1312 else if (dev->multifunction)
1313 next_fn = next_trad_fn;
1314
1315 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1316 dev = pci_scan_single_device(bus, devfn + fn);
1317 if (dev) {
1318 if (!dev->is_added)
1319 nr++;
1320 dev->multifunction = 1;
1321 }
1322 }
1323
1324 /* only one slot has pcie device */
1325 if (bus->self && nr)
1326 pcie_aspm_init_link_state(bus->self);
1327
1328 return nr;
1329}
1330
1331static int pcie_find_smpss(struct pci_dev *dev, void *data)
1332{
1333 u8 *smpss = data;
1334
1335 if (!pci_is_pcie(dev))
1336 return 0;
1337
1338 /* For PCIE hotplug enabled slots not connected directly to a
1339 * PCI-E root port, there can be problems when hotplugging
1340 * devices. This is due to the possibility of hotplugging a
1341 * device into the fabric with a smaller MPS that the devices
1342 * currently running have configured. Modifying the MPS on the
1343 * running devices could cause a fatal bus error due to an
1344 * incoming frame being larger than the newly configured MPS.
1345 * To work around this, the MPS for the entire fabric must be
1346 * set to the minimum size. Any devices hotplugged into this
1347 * fabric will have the minimum MPS set. If the PCI hotplug
1348 * slot is directly connected to the root port and there are not
1349 * other devices on the fabric (which seems to be the most
1350 * common case), then this is not an issue and MPS discovery
1351 * will occur as normal.
1352 */
1353 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1354 (dev->bus->self &&
1355 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
1356 *smpss = 0;
1357
1358 if (*smpss > dev->pcie_mpss)
1359 *smpss = dev->pcie_mpss;
1360
1361 return 0;
1362}
1363
1364static void pcie_write_mps(struct pci_dev *dev, int mps)
1365{
1366 int rc, dev_mpss;
1367
1368 dev_mpss = 128 << dev->pcie_mpss;
1369
1370 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1371 if (dev->bus->self) {
1372 dev_dbg(&dev->bus->dev, "Bus MPSS %d\n",
1373 128 << dev->bus->self->pcie_mpss);
1374
1375 /* For "MPS Force Max", the assumption is made that
1376 * downstream communication will never be larger than
1377 * the MRRS. So, the MPS only needs to be configured
1378 * for the upstream communication. This being the case,
1379 * walk from the top down and set the MPS of the child
1380 * to that of the parent bus.
1381 */
1382 mps = 128 << dev->bus->self->pcie_mpss;
1383 if (mps > dev_mpss)
1384 dev_warn(&dev->dev, "MPS configured higher than"
1385 " maximum supported by the device. If"
1386 " a bus issue occurs, try running with"
1387 " pci=pcie_bus_safe.\n");
1388 }
1389
1390 dev->pcie_mpss = ffs(mps) - 8;
1391 }
1392
1393 rc = pcie_set_mps(dev, mps);
1394 if (rc)
1395 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1396}
1397
1398static void pcie_write_mrrs(struct pci_dev *dev, int mps)
1399{
1400 int rc, mrrs, dev_mpss;
1401
1402 /* In the "safe" case, do not configure the MRRS. There appear to be
1403 * issues with setting MRRS to 0 on a number of devices.
1404 */
1405
1406 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1407 return;
1408
1409 dev_mpss = 128 << dev->pcie_mpss;
1410
1411 /* For Max performance, the MRRS must be set to the largest supported
1412 * value. However, it cannot be configured larger than the MPS the
1413 * device or the bus can support. This assumes that the largest MRRS
1414 * available on the device cannot be smaller than the device MPSS.
1415 */
1416 mrrs = min(mps, dev_mpss);
1417
1418 /* MRRS is a R/W register. Invalid values can be written, but a
1419 * subsequent read will verify if the value is acceptable or not.
1420 * If the MRRS value provided is not acceptable (e.g., too large),
1421 * shrink the value until it is acceptable to the HW.
1422 */
1423 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1424 dev_warn(&dev->dev, "Attempting to modify the PCI-E MRRS value"
1425 " to %d. If any issues are encountered, please try "
1426 "running with pci=pcie_bus_safe\n", mrrs);
1427 rc = pcie_set_readrq(dev, mrrs);
1428 if (rc)
1429 dev_err(&dev->dev,
1430 "Failed attempting to set the MRRS\n");
1431
1432 mrrs /= 2;
1433 }
1434}
1435
1436static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1437{
1438 int mps = 128 << *(u8 *)data;
1439
1440 if (!pci_is_pcie(dev))
1441 return 0;
1442
1443 dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
1444 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
1445
1446 pcie_write_mps(dev, mps);
1447 pcie_write_mrrs(dev, mps);
1448
1449 dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
1450 pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
1451
1452 return 0;
1453}
1454
1455/* pcie_bus_configure_mps requires that pci_walk_bus work in a top-down,
1456 * parents then children fashion. If this changes, then this code will not
1457 * work as designed.
1458 */
1459void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1460{
1461 u8 smpss;
1462
1463 if (!pci_is_pcie(bus->self))
1464 return;
1465
1466 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1467 return;
1468
1469 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1470 * to be aware to the MPS of the destination. To work around this,
1471 * simply force the MPS of the entire system to the smallest possible.
1472 */
1473 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1474 smpss = 0;
1475
1476 if (pcie_bus_config == PCIE_BUS_SAFE) {
1477 smpss = mpss;
1478
1479 pcie_find_smpss(bus->self, &smpss);
1480 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1481 }
1482
1483 pcie_bus_configure_set(bus->self, &smpss);
1484 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1485}
1486EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1487
1488unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1489{
1490 unsigned int devfn, pass, max = bus->secondary;
1491 struct pci_dev *dev;
1492
1493 dev_dbg(&bus->dev, "scanning bus\n");
1494
1495 /* Go find them, Rover! */
1496 for (devfn = 0; devfn < 0x100; devfn += 8)
1497 pci_scan_slot(bus, devfn);
1498
1499 /* Reserve buses for SR-IOV capability. */
1500 max += pci_iov_bus_range(bus);
1501
1502 /*
1503 * After performing arch-dependent fixup of the bus, look behind
1504 * all PCI-to-PCI bridges on this bus.
1505 */
1506 if (!bus->is_added) {
1507 dev_dbg(&bus->dev, "fixups for bus\n");
1508 pcibios_fixup_bus(bus);
1509 if (pci_is_root_bus(bus))
1510 bus->is_added = 1;
1511 }
1512
1513 for (pass=0; pass < 2; pass++)
1514 list_for_each_entry(dev, &bus->devices, bus_list) {
1515 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1516 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1517 max = pci_scan_bridge(bus, dev, max, pass);
1518 }
1519
1520 /*
1521 * We've scanned the bus and so we know all about what's on
1522 * the other side of any bridges that may be on this bus plus
1523 * any devices.
1524 *
1525 * Return how far we've got finding sub-buses.
1526 */
1527 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1528 return max;
1529}
1530
1531struct pci_bus * pci_create_bus(struct device *parent,
1532 int bus, struct pci_ops *ops, void *sysdata)
1533{
1534 int error;
1535 struct pci_bus *b, *b2;
1536 struct device *dev;
1537
1538 b = pci_alloc_bus();
1539 if (!b)
1540 return NULL;
1541
1542 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1543 if (!dev){
1544 kfree(b);
1545 return NULL;
1546 }
1547
1548 b->sysdata = sysdata;
1549 b->ops = ops;
1550
1551 b2 = pci_find_bus(pci_domain_nr(b), bus);
1552 if (b2) {
1553 /* If we already got to this bus through a different bridge, ignore it */
1554 dev_dbg(&b2->dev, "bus already known\n");
1555 goto err_out;
1556 }
1557
1558 down_write(&pci_bus_sem);
1559 list_add_tail(&b->node, &pci_root_buses);
1560 up_write(&pci_bus_sem);
1561
1562 dev->parent = parent;
1563 dev->release = pci_release_bus_bridge_dev;
1564 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1565 error = device_register(dev);
1566 if (error)
1567 goto dev_reg_err;
1568 b->bridge = get_device(dev);
1569 device_enable_async_suspend(b->bridge);
1570 pci_set_bus_of_node(b);
1571
1572 if (!parent)
1573 set_dev_node(b->bridge, pcibus_to_node(b));
1574
1575 b->dev.class = &pcibus_class;
1576 b->dev.parent = b->bridge;
1577 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1578 error = device_register(&b->dev);
1579 if (error)
1580 goto class_dev_reg_err;
1581
1582 /* Create legacy_io and legacy_mem files for this bus */
1583 pci_create_legacy_files(b);
1584
1585 b->number = b->secondary = bus;
1586 b->resource[0] = &ioport_resource;
1587 b->resource[1] = &iomem_resource;
1588
1589 return b;
1590
1591class_dev_reg_err:
1592 device_unregister(dev);
1593dev_reg_err:
1594 down_write(&pci_bus_sem);
1595 list_del(&b->node);
1596 up_write(&pci_bus_sem);
1597err_out:
1598 kfree(dev);
1599 kfree(b);
1600 return NULL;
1601}
1602
1603struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1604 int bus, struct pci_ops *ops, void *sysdata)
1605{
1606 struct pci_bus *b;
1607
1608 b = pci_create_bus(parent, bus, ops, sysdata);
1609 if (b)
1610 b->subordinate = pci_scan_child_bus(b);
1611 return b;
1612}
1613EXPORT_SYMBOL(pci_scan_bus_parented);
1614
1615#ifdef CONFIG_HOTPLUG
1616/**
1617 * pci_rescan_bus - scan a PCI bus for devices.
1618 * @bus: PCI bus to scan
1619 *
1620 * Scan a PCI bus and child buses for new devices, adds them,
1621 * and enables them.
1622 *
1623 * Returns the max number of subordinate bus discovered.
1624 */
1625unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1626{
1627 unsigned int max;
1628 struct pci_dev *dev;
1629
1630 max = pci_scan_child_bus(bus);
1631
1632 down_read(&pci_bus_sem);
1633 list_for_each_entry(dev, &bus->devices, bus_list)
1634 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1635 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1636 if (dev->subordinate)
1637 pci_bus_size_bridges(dev->subordinate);
1638 up_read(&pci_bus_sem);
1639
1640 pci_bus_assign_resources(bus);
1641 pci_enable_bridges(bus);
1642 pci_bus_add_devices(bus);
1643
1644 return max;
1645}
1646EXPORT_SYMBOL_GPL(pci_rescan_bus);
1647
1648EXPORT_SYMBOL(pci_add_new_bus);
1649EXPORT_SYMBOL(pci_scan_slot);
1650EXPORT_SYMBOL(pci_scan_bridge);
1651EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1652#endif
1653
1654static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1655{
1656 const struct pci_dev *a = to_pci_dev(d_a);
1657 const struct pci_dev *b = to_pci_dev(d_b);
1658
1659 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1660 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1661
1662 if (a->bus->number < b->bus->number) return -1;
1663 else if (a->bus->number > b->bus->number) return 1;
1664
1665 if (a->devfn < b->devfn) return -1;
1666 else if (a->devfn > b->devfn) return 1;
1667
1668 return 0;
1669}
1670
1671void __init pci_sort_breadthfirst(void)
1672{
1673 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1674}
1/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/of_device.h>
10#include <linux/of_pci.h>
11#include <linux/pci_hotplug.h>
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/cpumask.h>
15#include <linux/pci-aspm.h>
16#include <linux/aer.h>
17#include <linux/acpi.h>
18#include <linux/irqdomain.h>
19#include "pci.h"
20
21#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22#define CARDBUS_RESERVE_BUSNR 3
23
24static struct resource busn_resource = {
25 .name = "PCI busn",
26 .start = 0,
27 .end = 255,
28 .flags = IORESOURCE_BUS,
29};
30
31/* Ugh. Need to stop exporting this to modules. */
32LIST_HEAD(pci_root_buses);
33EXPORT_SYMBOL(pci_root_buses);
34
35static LIST_HEAD(pci_domain_busn_res_list);
36
37struct pci_domain_busn_res {
38 struct list_head list;
39 struct resource res;
40 int domain_nr;
41};
42
43static struct resource *get_pci_domain_busn_res(int domain_nr)
44{
45 struct pci_domain_busn_res *r;
46
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
49 return &r->res;
50
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
52 if (!r)
53 return NULL;
54
55 r->domain_nr = domain_nr;
56 r->res.start = 0;
57 r->res.end = 0xff;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
61
62 return &r->res;
63}
64
65static int find_anything(struct device *dev, void *data)
66{
67 return 1;
68}
69
70/*
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
74 */
75int no_pci_devices(void)
76{
77 struct device *dev;
78 int no_devices;
79
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
82 put_device(dev);
83 return no_devices;
84}
85EXPORT_SYMBOL(no_pci_devices);
86
87/*
88 * PCI Bus Class
89 */
90static void release_pcibus_dev(struct device *dev)
91{
92 struct pci_bus *pci_bus = to_pci_bus(dev);
93
94 put_device(pci_bus->bridge);
95 pci_bus_remove_resources(pci_bus);
96 pci_release_bus_of_node(pci_bus);
97 kfree(pci_bus);
98}
99
100static struct class pcibus_class = {
101 .name = "pci_bus",
102 .dev_release = &release_pcibus_dev,
103 .dev_groups = pcibus_groups,
104};
105
106static int __init pcibus_class_init(void)
107{
108 return class_register(&pcibus_class);
109}
110postcore_initcall(pcibus_class_init);
111
112static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113{
114 u64 size = mask & maxbase; /* Find the significant bits */
115 if (!size)
116 return 0;
117
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
121
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
125 return 0;
126
127 return size;
128}
129
130static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
131{
132 u32 mem_type;
133 unsigned long flags;
134
135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
138 return flags;
139 }
140
141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
145
146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 switch (mem_type) {
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
151 /* 1M mem BAR treated as 32-bit BAR */
152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
154 flags |= IORESOURCE_MEM_64;
155 break;
156 default:
157 /* mem unknown type treated as 32-bit BAR */
158 break;
159 }
160 return flags;
161}
162
163#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
164
165/**
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
171 *
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
173 */
174int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
175 struct resource *res, unsigned int pos)
176{
177 u32 l, sz, mask;
178 u64 l64, sz64, mask64;
179 u16 orig_cmd;
180 struct pci_bus_region region, inverted_region;
181
182 if (dev->non_compliant_bars)
183 return 0;
184
185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186
187 /* No printks while decoding is disabled! */
188 if (!dev->mmio_always_on) {
189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
191 pci_write_config_word(dev, PCI_COMMAND,
192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 }
194 }
195
196 res->name = pci_name(dev);
197
198 pci_read_config_dword(dev, pos, &l);
199 pci_write_config_dword(dev, pos, l | mask);
200 pci_read_config_dword(dev, pos, &sz);
201 pci_write_config_dword(dev, pos, l);
202
203 /*
204 * All bits set in sz means the device isn't working properly.
205 * If the BAR isn't implemented, all bits must be 0. If it's a
206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 * 1 must be clear.
208 */
209 if (sz == 0xffffffff)
210 sz = 0;
211
212 /*
213 * I don't know how l can have all bits set. Copied from old code.
214 * Maybe it fixes a bug on some ancient platform.
215 */
216 if (l == 0xffffffff)
217 l = 0;
218
219 if (type == pci_bar_unknown) {
220 res->flags = decode_bar(dev, l);
221 res->flags |= IORESOURCE_SIZEALIGN;
222 if (res->flags & IORESOURCE_IO) {
223 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
226 } else {
227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 }
231 } else {
232 res->flags |= (l & IORESOURCE_ROM_ENABLE);
233 l64 = l & PCI_ROM_ADDRESS_MASK;
234 sz64 = sz & PCI_ROM_ADDRESS_MASK;
235 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
236 }
237
238 if (res->flags & IORESOURCE_MEM_64) {
239 pci_read_config_dword(dev, pos + 4, &l);
240 pci_write_config_dword(dev, pos + 4, ~0);
241 pci_read_config_dword(dev, pos + 4, &sz);
242 pci_write_config_dword(dev, pos + 4, l);
243
244 l64 |= ((u64)l << 32);
245 sz64 |= ((u64)sz << 32);
246 mask64 |= ((u64)~0 << 32);
247 }
248
249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
251
252 if (!sz64)
253 goto fail;
254
255 sz64 = pci_size(l64, sz64, mask64);
256 if (!sz64) {
257 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
258 pos);
259 goto fail;
260 }
261
262 if (res->flags & IORESOURCE_MEM_64) {
263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
264 && sz64 > 0x100000000ULL) {
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 res->start = 0;
267 res->end = 0;
268 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
269 pos, (unsigned long long)sz64);
270 goto out;
271 }
272
273 if ((sizeof(pci_bus_addr_t) < 8) && l) {
274 /* Above 32-bit boundary; try to reallocate */
275 res->flags |= IORESOURCE_UNSET;
276 res->start = 0;
277 res->end = sz64;
278 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
279 pos, (unsigned long long)l64);
280 goto out;
281 }
282 }
283
284 region.start = l64;
285 region.end = l64 + sz64;
286
287 pcibios_bus_to_resource(dev->bus, res, ®ion);
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
289
290 /*
291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
292 * the corresponding resource address (the physical address used by
293 * the CPU. Converting that resource address back to a bus address
294 * should yield the original BAR value:
295 *
296 * resource_to_bus(bus_to_resource(A)) == A
297 *
298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
299 * be claimed by the device.
300 */
301 if (inverted_region.start != region.start) {
302 res->flags |= IORESOURCE_UNSET;
303 res->start = 0;
304 res->end = region.end - region.start;
305 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
306 pos, (unsigned long long)region.start);
307 }
308
309 goto out;
310
311
312fail:
313 res->flags = 0;
314out:
315 if (res->flags)
316 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
317
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
319}
320
321static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322{
323 unsigned int pos, reg;
324
325 for (pos = 0; pos < howmany; pos++) {
326 struct resource *res = &dev->resource[pos];
327 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
328 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
329 }
330
331 if (rom) {
332 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
333 dev->rom_base_reg = rom;
334 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
335 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
336 __pci_read_base(dev, pci_bar_mem32, res, rom);
337 }
338}
339
340static void pci_read_bridge_io(struct pci_bus *child)
341{
342 struct pci_dev *dev = child->self;
343 u8 io_base_lo, io_limit_lo;
344 unsigned long io_mask, io_granularity, base, limit;
345 struct pci_bus_region region;
346 struct resource *res;
347
348 io_mask = PCI_IO_RANGE_MASK;
349 io_granularity = 0x1000;
350 if (dev->io_window_1k) {
351 /* Support 1K I/O space granularity */
352 io_mask = PCI_IO_1K_RANGE_MASK;
353 io_granularity = 0x400;
354 }
355
356 res = child->resource[0];
357 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
358 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
359 base = (io_base_lo & io_mask) << 8;
360 limit = (io_limit_lo & io_mask) << 8;
361
362 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
363 u16 io_base_hi, io_limit_hi;
364
365 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
366 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
367 base |= ((unsigned long) io_base_hi << 16);
368 limit |= ((unsigned long) io_limit_hi << 16);
369 }
370
371 if (base <= limit) {
372 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
373 region.start = base;
374 region.end = limit + io_granularity - 1;
375 pcibios_bus_to_resource(dev->bus, res, ®ion);
376 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
377 }
378}
379
380static void pci_read_bridge_mmio(struct pci_bus *child)
381{
382 struct pci_dev *dev = child->self;
383 u16 mem_base_lo, mem_limit_lo;
384 unsigned long base, limit;
385 struct pci_bus_region region;
386 struct resource *res;
387
388 res = child->resource[1];
389 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
390 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
391 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
392 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
393 if (base <= limit) {
394 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
395 region.start = base;
396 region.end = limit + 0xfffff;
397 pcibios_bus_to_resource(dev->bus, res, ®ion);
398 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
399 }
400}
401
402static void pci_read_bridge_mmio_pref(struct pci_bus *child)
403{
404 struct pci_dev *dev = child->self;
405 u16 mem_base_lo, mem_limit_lo;
406 u64 base64, limit64;
407 pci_bus_addr_t base, limit;
408 struct pci_bus_region region;
409 struct resource *res;
410
411 res = child->resource[2];
412 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
413 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
414 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
415 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
416
417 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
418 u32 mem_base_hi, mem_limit_hi;
419
420 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
421 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
422
423 /*
424 * Some bridges set the base > limit by default, and some
425 * (broken) BIOSes do not initialize them. If we find
426 * this, just assume they are not being used.
427 */
428 if (mem_base_hi <= mem_limit_hi) {
429 base64 |= (u64) mem_base_hi << 32;
430 limit64 |= (u64) mem_limit_hi << 32;
431 }
432 }
433
434 base = (pci_bus_addr_t) base64;
435 limit = (pci_bus_addr_t) limit64;
436
437 if (base != base64) {
438 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
439 (unsigned long long) base64);
440 return;
441 }
442
443 if (base <= limit) {
444 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
445 IORESOURCE_MEM | IORESOURCE_PREFETCH;
446 if (res->flags & PCI_PREF_RANGE_TYPE_64)
447 res->flags |= IORESOURCE_MEM_64;
448 region.start = base;
449 region.end = limit + 0xfffff;
450 pcibios_bus_to_resource(dev->bus, res, ®ion);
451 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
452 }
453}
454
455void pci_read_bridge_bases(struct pci_bus *child)
456{
457 struct pci_dev *dev = child->self;
458 struct resource *res;
459 int i;
460
461 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
462 return;
463
464 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
465 &child->busn_res,
466 dev->transparent ? " (subtractive decode)" : "");
467
468 pci_bus_remove_resources(child);
469 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
470 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
471
472 pci_read_bridge_io(child);
473 pci_read_bridge_mmio(child);
474 pci_read_bridge_mmio_pref(child);
475
476 if (dev->transparent) {
477 pci_bus_for_each_resource(child->parent, res, i) {
478 if (res && res->flags) {
479 pci_bus_add_resource(child, res,
480 PCI_SUBTRACTIVE_DECODE);
481 dev_printk(KERN_DEBUG, &dev->dev,
482 " bridge window %pR (subtractive decode)\n",
483 res);
484 }
485 }
486 }
487}
488
489static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
490{
491 struct pci_bus *b;
492
493 b = kzalloc(sizeof(*b), GFP_KERNEL);
494 if (!b)
495 return NULL;
496
497 INIT_LIST_HEAD(&b->node);
498 INIT_LIST_HEAD(&b->children);
499 INIT_LIST_HEAD(&b->devices);
500 INIT_LIST_HEAD(&b->slots);
501 INIT_LIST_HEAD(&b->resources);
502 b->max_bus_speed = PCI_SPEED_UNKNOWN;
503 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
504#ifdef CONFIG_PCI_DOMAINS_GENERIC
505 if (parent)
506 b->domain_nr = parent->domain_nr;
507#endif
508 return b;
509}
510
511static void pci_release_host_bridge_dev(struct device *dev)
512{
513 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
514
515 if (bridge->release_fn)
516 bridge->release_fn(bridge);
517
518 pci_free_resource_list(&bridge->windows);
519
520 kfree(bridge);
521}
522
523static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
524{
525 struct pci_host_bridge *bridge;
526
527 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
528 if (!bridge)
529 return NULL;
530
531 INIT_LIST_HEAD(&bridge->windows);
532 bridge->bus = b;
533 return bridge;
534}
535
536static const unsigned char pcix_bus_speed[] = {
537 PCI_SPEED_UNKNOWN, /* 0 */
538 PCI_SPEED_66MHz_PCIX, /* 1 */
539 PCI_SPEED_100MHz_PCIX, /* 2 */
540 PCI_SPEED_133MHz_PCIX, /* 3 */
541 PCI_SPEED_UNKNOWN, /* 4 */
542 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
543 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
544 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
545 PCI_SPEED_UNKNOWN, /* 8 */
546 PCI_SPEED_66MHz_PCIX_266, /* 9 */
547 PCI_SPEED_100MHz_PCIX_266, /* A */
548 PCI_SPEED_133MHz_PCIX_266, /* B */
549 PCI_SPEED_UNKNOWN, /* C */
550 PCI_SPEED_66MHz_PCIX_533, /* D */
551 PCI_SPEED_100MHz_PCIX_533, /* E */
552 PCI_SPEED_133MHz_PCIX_533 /* F */
553};
554
555const unsigned char pcie_link_speed[] = {
556 PCI_SPEED_UNKNOWN, /* 0 */
557 PCIE_SPEED_2_5GT, /* 1 */
558 PCIE_SPEED_5_0GT, /* 2 */
559 PCIE_SPEED_8_0GT, /* 3 */
560 PCI_SPEED_UNKNOWN, /* 4 */
561 PCI_SPEED_UNKNOWN, /* 5 */
562 PCI_SPEED_UNKNOWN, /* 6 */
563 PCI_SPEED_UNKNOWN, /* 7 */
564 PCI_SPEED_UNKNOWN, /* 8 */
565 PCI_SPEED_UNKNOWN, /* 9 */
566 PCI_SPEED_UNKNOWN, /* A */
567 PCI_SPEED_UNKNOWN, /* B */
568 PCI_SPEED_UNKNOWN, /* C */
569 PCI_SPEED_UNKNOWN, /* D */
570 PCI_SPEED_UNKNOWN, /* E */
571 PCI_SPEED_UNKNOWN /* F */
572};
573
574void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
575{
576 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
577}
578EXPORT_SYMBOL_GPL(pcie_update_link_speed);
579
580static unsigned char agp_speeds[] = {
581 AGP_UNKNOWN,
582 AGP_1X,
583 AGP_2X,
584 AGP_4X,
585 AGP_8X
586};
587
588static enum pci_bus_speed agp_speed(int agp3, int agpstat)
589{
590 int index = 0;
591
592 if (agpstat & 4)
593 index = 3;
594 else if (agpstat & 2)
595 index = 2;
596 else if (agpstat & 1)
597 index = 1;
598 else
599 goto out;
600
601 if (agp3) {
602 index += 2;
603 if (index == 5)
604 index = 0;
605 }
606
607 out:
608 return agp_speeds[index];
609}
610
611static void pci_set_bus_speed(struct pci_bus *bus)
612{
613 struct pci_dev *bridge = bus->self;
614 int pos;
615
616 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
617 if (!pos)
618 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
619 if (pos) {
620 u32 agpstat, agpcmd;
621
622 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
623 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
624
625 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
626 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
627 }
628
629 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
630 if (pos) {
631 u16 status;
632 enum pci_bus_speed max;
633
634 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
635 &status);
636
637 if (status & PCI_X_SSTATUS_533MHZ) {
638 max = PCI_SPEED_133MHz_PCIX_533;
639 } else if (status & PCI_X_SSTATUS_266MHZ) {
640 max = PCI_SPEED_133MHz_PCIX_266;
641 } else if (status & PCI_X_SSTATUS_133MHZ) {
642 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
643 max = PCI_SPEED_133MHz_PCIX_ECC;
644 else
645 max = PCI_SPEED_133MHz_PCIX;
646 } else {
647 max = PCI_SPEED_66MHz_PCIX;
648 }
649
650 bus->max_bus_speed = max;
651 bus->cur_bus_speed = pcix_bus_speed[
652 (status & PCI_X_SSTATUS_FREQ) >> 6];
653
654 return;
655 }
656
657 if (pci_is_pcie(bridge)) {
658 u32 linkcap;
659 u16 linksta;
660
661 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
662 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
663
664 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
665 pcie_update_link_speed(bus, linksta);
666 }
667}
668
669static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
670{
671 struct irq_domain *d;
672
673 /*
674 * Any firmware interface that can resolve the msi_domain
675 * should be called from here.
676 */
677 d = pci_host_bridge_of_msi_domain(bus);
678 if (!d)
679 d = pci_host_bridge_acpi_msi_domain(bus);
680
681#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
682 /*
683 * If no IRQ domain was found via the OF tree, try looking it up
684 * directly through the fwnode_handle.
685 */
686 if (!d) {
687 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
688
689 if (fwnode)
690 d = irq_find_matching_fwnode(fwnode,
691 DOMAIN_BUS_PCI_MSI);
692 }
693#endif
694
695 return d;
696}
697
698static void pci_set_bus_msi_domain(struct pci_bus *bus)
699{
700 struct irq_domain *d;
701 struct pci_bus *b;
702
703 /*
704 * The bus can be a root bus, a subordinate bus, or a virtual bus
705 * created by an SR-IOV device. Walk up to the first bridge device
706 * found or derive the domain from the host bridge.
707 */
708 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
709 if (b->self)
710 d = dev_get_msi_domain(&b->self->dev);
711 }
712
713 if (!d)
714 d = pci_host_bridge_msi_domain(b);
715
716 dev_set_msi_domain(&bus->dev, d);
717}
718
719static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
720 struct pci_dev *bridge, int busnr)
721{
722 struct pci_bus *child;
723 int i;
724 int ret;
725
726 /*
727 * Allocate a new bus, and inherit stuff from the parent..
728 */
729 child = pci_alloc_bus(parent);
730 if (!child)
731 return NULL;
732
733 child->parent = parent;
734 child->ops = parent->ops;
735 child->msi = parent->msi;
736 child->sysdata = parent->sysdata;
737 child->bus_flags = parent->bus_flags;
738
739 /* initialize some portions of the bus device, but don't register it
740 * now as the parent is not properly set up yet.
741 */
742 child->dev.class = &pcibus_class;
743 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
744
745 /*
746 * Set up the primary, secondary and subordinate
747 * bus numbers.
748 */
749 child->number = child->busn_res.start = busnr;
750 child->primary = parent->busn_res.start;
751 child->busn_res.end = 0xff;
752
753 if (!bridge) {
754 child->dev.parent = parent->bridge;
755 goto add_dev;
756 }
757
758 child->self = bridge;
759 child->bridge = get_device(&bridge->dev);
760 child->dev.parent = child->bridge;
761 pci_set_bus_of_node(child);
762 pci_set_bus_speed(child);
763
764 /* Set up default resource pointers and names.. */
765 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
766 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
767 child->resource[i]->name = child->name;
768 }
769 bridge->subordinate = child;
770
771add_dev:
772 pci_set_bus_msi_domain(child);
773 ret = device_register(&child->dev);
774 WARN_ON(ret < 0);
775
776 pcibios_add_bus(child);
777
778 if (child->ops->add_bus) {
779 ret = child->ops->add_bus(child);
780 if (WARN_ON(ret < 0))
781 dev_err(&child->dev, "failed to add bus: %d\n", ret);
782 }
783
784 /* Create legacy_io and legacy_mem files for this bus */
785 pci_create_legacy_files(child);
786
787 return child;
788}
789
790struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
791 int busnr)
792{
793 struct pci_bus *child;
794
795 child = pci_alloc_child_bus(parent, dev, busnr);
796 if (child) {
797 down_write(&pci_bus_sem);
798 list_add_tail(&child->node, &parent->children);
799 up_write(&pci_bus_sem);
800 }
801 return child;
802}
803EXPORT_SYMBOL(pci_add_new_bus);
804
805static void pci_enable_crs(struct pci_dev *pdev)
806{
807 u16 root_cap = 0;
808
809 /* Enable CRS Software Visibility if supported */
810 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
811 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
812 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
813 PCI_EXP_RTCTL_CRSSVE);
814}
815
816/*
817 * If it's a bridge, configure it and scan the bus behind it.
818 * For CardBus bridges, we don't scan behind as the devices will
819 * be handled by the bridge driver itself.
820 *
821 * We need to process bridges in two passes -- first we scan those
822 * already configured by the BIOS and after we are done with all of
823 * them, we proceed to assigning numbers to the remaining buses in
824 * order to avoid overlaps between old and new bus numbers.
825 */
826int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
827{
828 struct pci_bus *child;
829 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
830 u32 buses, i, j = 0;
831 u16 bctl;
832 u8 primary, secondary, subordinate;
833 int broken = 0;
834
835 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
836 primary = buses & 0xFF;
837 secondary = (buses >> 8) & 0xFF;
838 subordinate = (buses >> 16) & 0xFF;
839
840 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
841 secondary, subordinate, pass);
842
843 if (!primary && (primary != bus->number) && secondary && subordinate) {
844 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
845 primary = bus->number;
846 }
847
848 /* Check if setup is sensible at all */
849 if (!pass &&
850 (primary != bus->number || secondary <= bus->number ||
851 secondary > subordinate)) {
852 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
853 secondary, subordinate);
854 broken = 1;
855 }
856
857 /* Disable MasterAbortMode during probing to avoid reporting
858 of bus errors (in some architectures) */
859 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
860 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
861 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
862
863 pci_enable_crs(dev);
864
865 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
866 !is_cardbus && !broken) {
867 unsigned int cmax;
868 /*
869 * Bus already configured by firmware, process it in the first
870 * pass and just note the configuration.
871 */
872 if (pass)
873 goto out;
874
875 /*
876 * The bus might already exist for two reasons: Either we are
877 * rescanning the bus or the bus is reachable through more than
878 * one bridge. The second case can happen with the i450NX
879 * chipset.
880 */
881 child = pci_find_bus(pci_domain_nr(bus), secondary);
882 if (!child) {
883 child = pci_add_new_bus(bus, dev, secondary);
884 if (!child)
885 goto out;
886 child->primary = primary;
887 pci_bus_insert_busn_res(child, secondary, subordinate);
888 child->bridge_ctl = bctl;
889 }
890
891 cmax = pci_scan_child_bus(child);
892 if (cmax > subordinate)
893 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
894 subordinate, cmax);
895 /* subordinate should equal child->busn_res.end */
896 if (subordinate > max)
897 max = subordinate;
898 } else {
899 /*
900 * We need to assign a number to this bus which we always
901 * do in the second pass.
902 */
903 if (!pass) {
904 if (pcibios_assign_all_busses() || broken || is_cardbus)
905 /* Temporarily disable forwarding of the
906 configuration cycles on all bridges in
907 this bus segment to avoid possible
908 conflicts in the second pass between two
909 bridges programmed with overlapping
910 bus ranges. */
911 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
912 buses & ~0xffffff);
913 goto out;
914 }
915
916 /* Clear errors */
917 pci_write_config_word(dev, PCI_STATUS, 0xffff);
918
919 /* Prevent assigning a bus number that already exists.
920 * This can happen when a bridge is hot-plugged, so in
921 * this case we only re-scan this bus. */
922 child = pci_find_bus(pci_domain_nr(bus), max+1);
923 if (!child) {
924 child = pci_add_new_bus(bus, dev, max+1);
925 if (!child)
926 goto out;
927 pci_bus_insert_busn_res(child, max+1, 0xff);
928 }
929 max++;
930 buses = (buses & 0xff000000)
931 | ((unsigned int)(child->primary) << 0)
932 | ((unsigned int)(child->busn_res.start) << 8)
933 | ((unsigned int)(child->busn_res.end) << 16);
934
935 /*
936 * yenta.c forces a secondary latency timer of 176.
937 * Copy that behaviour here.
938 */
939 if (is_cardbus) {
940 buses &= ~0xff000000;
941 buses |= CARDBUS_LATENCY_TIMER << 24;
942 }
943
944 /*
945 * We need to blast all three values with a single write.
946 */
947 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
948
949 if (!is_cardbus) {
950 child->bridge_ctl = bctl;
951 max = pci_scan_child_bus(child);
952 } else {
953 /*
954 * For CardBus bridges, we leave 4 bus numbers
955 * as cards with a PCI-to-PCI bridge can be
956 * inserted later.
957 */
958 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
959 struct pci_bus *parent = bus;
960 if (pci_find_bus(pci_domain_nr(bus),
961 max+i+1))
962 break;
963 while (parent->parent) {
964 if ((!pcibios_assign_all_busses()) &&
965 (parent->busn_res.end > max) &&
966 (parent->busn_res.end <= max+i)) {
967 j = 1;
968 }
969 parent = parent->parent;
970 }
971 if (j) {
972 /*
973 * Often, there are two cardbus bridges
974 * -- try to leave one valid bus number
975 * for each one.
976 */
977 i /= 2;
978 break;
979 }
980 }
981 max += i;
982 }
983 /*
984 * Set the subordinate bus number to its real value.
985 */
986 pci_bus_update_busn_res_end(child, max);
987 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
988 }
989
990 sprintf(child->name,
991 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
992 pci_domain_nr(bus), child->number);
993
994 /* Has only triggered on CardBus, fixup is in yenta_socket */
995 while (bus->parent) {
996 if ((child->busn_res.end > bus->busn_res.end) ||
997 (child->number > bus->busn_res.end) ||
998 (child->number < bus->number) ||
999 (child->busn_res.end < bus->number)) {
1000 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1001 &child->busn_res,
1002 (bus->number > child->busn_res.end &&
1003 bus->busn_res.end < child->number) ?
1004 "wholly" : "partially",
1005 bus->self->transparent ? " transparent" : "",
1006 dev_name(&bus->dev),
1007 &bus->busn_res);
1008 }
1009 bus = bus->parent;
1010 }
1011
1012out:
1013 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1014
1015 return max;
1016}
1017EXPORT_SYMBOL(pci_scan_bridge);
1018
1019/*
1020 * Read interrupt line and base address registers.
1021 * The architecture-dependent code can tweak these, of course.
1022 */
1023static void pci_read_irq(struct pci_dev *dev)
1024{
1025 unsigned char irq;
1026
1027 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1028 dev->pin = irq;
1029 if (irq)
1030 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1031 dev->irq = irq;
1032}
1033
1034void set_pcie_port_type(struct pci_dev *pdev)
1035{
1036 int pos;
1037 u16 reg16;
1038 int type;
1039 struct pci_dev *parent;
1040
1041 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1042 if (!pos)
1043 return;
1044 pdev->pcie_cap = pos;
1045 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1046 pdev->pcie_flags_reg = reg16;
1047 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1048 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1049
1050 /*
1051 * A Root Port is always the upstream end of a Link. No PCIe
1052 * component has two Links. Two Links are connected by a Switch
1053 * that has a Port on each Link and internal logic to connect the
1054 * two Ports.
1055 */
1056 type = pci_pcie_type(pdev);
1057 if (type == PCI_EXP_TYPE_ROOT_PORT)
1058 pdev->has_secondary_link = 1;
1059 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1060 type == PCI_EXP_TYPE_DOWNSTREAM) {
1061 parent = pci_upstream_bridge(pdev);
1062
1063 /*
1064 * Usually there's an upstream device (Root Port or Switch
1065 * Downstream Port), but we can't assume one exists.
1066 */
1067 if (parent && !parent->has_secondary_link)
1068 pdev->has_secondary_link = 1;
1069 }
1070}
1071
1072void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1073{
1074 u32 reg32;
1075
1076 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1077 if (reg32 & PCI_EXP_SLTCAP_HPC)
1078 pdev->is_hotplug_bridge = 1;
1079}
1080
1081/**
1082 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1083 * @dev: PCI device
1084 *
1085 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1086 * when forwarding a type1 configuration request the bridge must check that
1087 * the extended register address field is zero. The bridge is not permitted
1088 * to forward the transactions and must handle it as an Unsupported Request.
1089 * Some bridges do not follow this rule and simply drop the extended register
1090 * bits, resulting in the standard config space being aliased, every 256
1091 * bytes across the entire configuration space. Test for this condition by
1092 * comparing the first dword of each potential alias to the vendor/device ID.
1093 * Known offenders:
1094 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1095 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1096 */
1097static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1098{
1099#ifdef CONFIG_PCI_QUIRKS
1100 int pos;
1101 u32 header, tmp;
1102
1103 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1104
1105 for (pos = PCI_CFG_SPACE_SIZE;
1106 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1107 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1108 || header != tmp)
1109 return false;
1110 }
1111
1112 return true;
1113#else
1114 return false;
1115#endif
1116}
1117
1118/**
1119 * pci_cfg_space_size - get the configuration space size of the PCI device.
1120 * @dev: PCI device
1121 *
1122 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1123 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1124 * access it. Maybe we don't have a way to generate extended config space
1125 * accesses, or the device is behind a reverse Express bridge. So we try
1126 * reading the dword at 0x100 which must either be 0 or a valid extended
1127 * capability header.
1128 */
1129static int pci_cfg_space_size_ext(struct pci_dev *dev)
1130{
1131 u32 status;
1132 int pos = PCI_CFG_SPACE_SIZE;
1133
1134 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1135 return PCI_CFG_SPACE_SIZE;
1136 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1137 return PCI_CFG_SPACE_SIZE;
1138
1139 return PCI_CFG_SPACE_EXP_SIZE;
1140}
1141
1142int pci_cfg_space_size(struct pci_dev *dev)
1143{
1144 int pos;
1145 u32 status;
1146 u16 class;
1147
1148 class = dev->class >> 8;
1149 if (class == PCI_CLASS_BRIDGE_HOST)
1150 return pci_cfg_space_size_ext(dev);
1151
1152 if (pci_is_pcie(dev))
1153 return pci_cfg_space_size_ext(dev);
1154
1155 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1156 if (!pos)
1157 return PCI_CFG_SPACE_SIZE;
1158
1159 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1160 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1161 return pci_cfg_space_size_ext(dev);
1162
1163 return PCI_CFG_SPACE_SIZE;
1164}
1165
1166#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1167
1168static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1169{
1170 /*
1171 * Disable the MSI hardware to avoid screaming interrupts
1172 * during boot. This is the power on reset default so
1173 * usually this should be a noop.
1174 */
1175 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1176 if (dev->msi_cap)
1177 pci_msi_set_enable(dev, 0);
1178
1179 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1180 if (dev->msix_cap)
1181 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1182}
1183
1184/**
1185 * pci_setup_device - fill in class and map information of a device
1186 * @dev: the device structure to fill
1187 *
1188 * Initialize the device structure with information about the device's
1189 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1190 * Called at initialisation of the PCI subsystem and by CardBus services.
1191 * Returns 0 on success and negative if unknown type of device (not normal,
1192 * bridge or CardBus).
1193 */
1194int pci_setup_device(struct pci_dev *dev)
1195{
1196 u32 class;
1197 u16 cmd;
1198 u8 hdr_type;
1199 int pos = 0;
1200 struct pci_bus_region region;
1201 struct resource *res;
1202
1203 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1204 return -EIO;
1205
1206 dev->sysdata = dev->bus->sysdata;
1207 dev->dev.parent = dev->bus->bridge;
1208 dev->dev.bus = &pci_bus_type;
1209 dev->hdr_type = hdr_type & 0x7f;
1210 dev->multifunction = !!(hdr_type & 0x80);
1211 dev->error_state = pci_channel_io_normal;
1212 set_pcie_port_type(dev);
1213
1214 pci_dev_assign_slot(dev);
1215 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1216 set this higher, assuming the system even supports it. */
1217 dev->dma_mask = 0xffffffff;
1218
1219 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1220 dev->bus->number, PCI_SLOT(dev->devfn),
1221 PCI_FUNC(dev->devfn));
1222
1223 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1224 dev->revision = class & 0xff;
1225 dev->class = class >> 8; /* upper 3 bytes */
1226
1227 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1228 dev->vendor, dev->device, dev->hdr_type, dev->class);
1229
1230 /* need to have dev->class ready */
1231 dev->cfg_size = pci_cfg_space_size(dev);
1232
1233 /* "Unknown power state" */
1234 dev->current_state = PCI_UNKNOWN;
1235
1236 /* Early fixups, before probing the BARs */
1237 pci_fixup_device(pci_fixup_early, dev);
1238 /* device class may be changed after fixup */
1239 class = dev->class >> 8;
1240
1241 if (dev->non_compliant_bars) {
1242 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1243 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1244 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1245 cmd &= ~PCI_COMMAND_IO;
1246 cmd &= ~PCI_COMMAND_MEMORY;
1247 pci_write_config_word(dev, PCI_COMMAND, cmd);
1248 }
1249 }
1250
1251 switch (dev->hdr_type) { /* header type */
1252 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1253 if (class == PCI_CLASS_BRIDGE_PCI)
1254 goto bad;
1255 pci_read_irq(dev);
1256 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1257 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1258 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1259
1260 /*
1261 * Do the ugly legacy mode stuff here rather than broken chip
1262 * quirk code. Legacy mode ATA controllers have fixed
1263 * addresses. These are not always echoed in BAR0-3, and
1264 * BAR0-3 in a few cases contain junk!
1265 */
1266 if (class == PCI_CLASS_STORAGE_IDE) {
1267 u8 progif;
1268 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1269 if ((progif & 1) == 0) {
1270 region.start = 0x1F0;
1271 region.end = 0x1F7;
1272 res = &dev->resource[0];
1273 res->flags = LEGACY_IO_RESOURCE;
1274 pcibios_bus_to_resource(dev->bus, res, ®ion);
1275 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1276 res);
1277 region.start = 0x3F6;
1278 region.end = 0x3F6;
1279 res = &dev->resource[1];
1280 res->flags = LEGACY_IO_RESOURCE;
1281 pcibios_bus_to_resource(dev->bus, res, ®ion);
1282 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1283 res);
1284 }
1285 if ((progif & 4) == 0) {
1286 region.start = 0x170;
1287 region.end = 0x177;
1288 res = &dev->resource[2];
1289 res->flags = LEGACY_IO_RESOURCE;
1290 pcibios_bus_to_resource(dev->bus, res, ®ion);
1291 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1292 res);
1293 region.start = 0x376;
1294 region.end = 0x376;
1295 res = &dev->resource[3];
1296 res->flags = LEGACY_IO_RESOURCE;
1297 pcibios_bus_to_resource(dev->bus, res, ®ion);
1298 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1299 res);
1300 }
1301 }
1302 break;
1303
1304 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1305 if (class != PCI_CLASS_BRIDGE_PCI)
1306 goto bad;
1307 /* The PCI-to-PCI bridge spec requires that subtractive
1308 decoding (i.e. transparent) bridge must have programming
1309 interface code of 0x01. */
1310 pci_read_irq(dev);
1311 dev->transparent = ((dev->class & 0xff) == 1);
1312 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1313 set_pcie_hotplug_bridge(dev);
1314 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1315 if (pos) {
1316 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1317 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1318 }
1319 break;
1320
1321 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1322 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1323 goto bad;
1324 pci_read_irq(dev);
1325 pci_read_bases(dev, 1, 0);
1326 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1327 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1328 break;
1329
1330 default: /* unknown header */
1331 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1332 dev->hdr_type);
1333 return -EIO;
1334
1335 bad:
1336 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1337 dev->class, dev->hdr_type);
1338 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1339 }
1340
1341 /* We found a fine healthy device, go go go... */
1342 return 0;
1343}
1344
1345static void pci_configure_mps(struct pci_dev *dev)
1346{
1347 struct pci_dev *bridge = pci_upstream_bridge(dev);
1348 int mps, p_mps, rc;
1349
1350 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1351 return;
1352
1353 mps = pcie_get_mps(dev);
1354 p_mps = pcie_get_mps(bridge);
1355
1356 if (mps == p_mps)
1357 return;
1358
1359 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1360 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1361 mps, pci_name(bridge), p_mps);
1362 return;
1363 }
1364
1365 /*
1366 * Fancier MPS configuration is done later by
1367 * pcie_bus_configure_settings()
1368 */
1369 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1370 return;
1371
1372 rc = pcie_set_mps(dev, p_mps);
1373 if (rc) {
1374 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1375 p_mps);
1376 return;
1377 }
1378
1379 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1380 p_mps, mps, 128 << dev->pcie_mpss);
1381}
1382
1383static struct hpp_type0 pci_default_type0 = {
1384 .revision = 1,
1385 .cache_line_size = 8,
1386 .latency_timer = 0x40,
1387 .enable_serr = 0,
1388 .enable_perr = 0,
1389};
1390
1391static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1392{
1393 u16 pci_cmd, pci_bctl;
1394
1395 if (!hpp)
1396 hpp = &pci_default_type0;
1397
1398 if (hpp->revision > 1) {
1399 dev_warn(&dev->dev,
1400 "PCI settings rev %d not supported; using defaults\n",
1401 hpp->revision);
1402 hpp = &pci_default_type0;
1403 }
1404
1405 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1406 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1407 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1408 if (hpp->enable_serr)
1409 pci_cmd |= PCI_COMMAND_SERR;
1410 if (hpp->enable_perr)
1411 pci_cmd |= PCI_COMMAND_PARITY;
1412 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1413
1414 /* Program bridge control value */
1415 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1416 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1417 hpp->latency_timer);
1418 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1419 if (hpp->enable_serr)
1420 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1421 if (hpp->enable_perr)
1422 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1423 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1424 }
1425}
1426
1427static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1428{
1429 if (hpp)
1430 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1431}
1432
1433static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1434{
1435 int pos;
1436 u32 reg32;
1437
1438 if (!hpp)
1439 return;
1440
1441 if (hpp->revision > 1) {
1442 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1443 hpp->revision);
1444 return;
1445 }
1446
1447 /*
1448 * Don't allow _HPX to change MPS or MRRS settings. We manage
1449 * those to make sure they're consistent with the rest of the
1450 * platform.
1451 */
1452 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1453 PCI_EXP_DEVCTL_READRQ;
1454 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1455 PCI_EXP_DEVCTL_READRQ);
1456
1457 /* Initialize Device Control Register */
1458 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1459 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1460
1461 /* Initialize Link Control Register */
1462 if (pcie_cap_has_lnkctl(dev))
1463 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1464 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1465
1466 /* Find Advanced Error Reporting Enhanced Capability */
1467 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1468 if (!pos)
1469 return;
1470
1471 /* Initialize Uncorrectable Error Mask Register */
1472 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1473 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1474 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1475
1476 /* Initialize Uncorrectable Error Severity Register */
1477 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1478 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1479 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1480
1481 /* Initialize Correctable Error Mask Register */
1482 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1483 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1484 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1485
1486 /* Initialize Advanced Error Capabilities and Control Register */
1487 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1488 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1489 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1490
1491 /*
1492 * FIXME: The following two registers are not supported yet.
1493 *
1494 * o Secondary Uncorrectable Error Severity Register
1495 * o Secondary Uncorrectable Error Mask Register
1496 */
1497}
1498
1499static void pci_configure_device(struct pci_dev *dev)
1500{
1501 struct hotplug_params hpp;
1502 int ret;
1503
1504 pci_configure_mps(dev);
1505
1506 memset(&hpp, 0, sizeof(hpp));
1507 ret = pci_get_hp_params(dev, &hpp);
1508 if (ret)
1509 return;
1510
1511 program_hpp_type2(dev, hpp.t2);
1512 program_hpp_type1(dev, hpp.t1);
1513 program_hpp_type0(dev, hpp.t0);
1514}
1515
1516static void pci_release_capabilities(struct pci_dev *dev)
1517{
1518 pci_vpd_release(dev);
1519 pci_iov_release(dev);
1520 pci_free_cap_save_buffers(dev);
1521}
1522
1523/**
1524 * pci_release_dev - free a pci device structure when all users of it are finished.
1525 * @dev: device that's been disconnected
1526 *
1527 * Will be called only by the device core when all users of this pci device are
1528 * done.
1529 */
1530static void pci_release_dev(struct device *dev)
1531{
1532 struct pci_dev *pci_dev;
1533
1534 pci_dev = to_pci_dev(dev);
1535 pci_release_capabilities(pci_dev);
1536 pci_release_of_node(pci_dev);
1537 pcibios_release_device(pci_dev);
1538 pci_bus_put(pci_dev->bus);
1539 kfree(pci_dev->driver_override);
1540 kfree(pci_dev);
1541}
1542
1543struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1544{
1545 struct pci_dev *dev;
1546
1547 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1548 if (!dev)
1549 return NULL;
1550
1551 INIT_LIST_HEAD(&dev->bus_list);
1552 dev->dev.type = &pci_dev_type;
1553 dev->bus = pci_bus_get(bus);
1554
1555 return dev;
1556}
1557EXPORT_SYMBOL(pci_alloc_dev);
1558
1559bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1560 int crs_timeout)
1561{
1562 int delay = 1;
1563
1564 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1565 return false;
1566
1567 /* some broken boards return 0 or ~0 if a slot is empty: */
1568 if (*l == 0xffffffff || *l == 0x00000000 ||
1569 *l == 0x0000ffff || *l == 0xffff0000)
1570 return false;
1571
1572 /*
1573 * Configuration Request Retry Status. Some root ports return the
1574 * actual device ID instead of the synthetic ID (0xFFFF) required
1575 * by the PCIe spec. Ignore the device ID and only check for
1576 * (vendor id == 1).
1577 */
1578 while ((*l & 0xffff) == 0x0001) {
1579 if (!crs_timeout)
1580 return false;
1581
1582 msleep(delay);
1583 delay *= 2;
1584 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1585 return false;
1586 /* Card hasn't responded in 60 seconds? Must be stuck. */
1587 if (delay > crs_timeout) {
1588 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1589 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1590 PCI_FUNC(devfn));
1591 return false;
1592 }
1593 }
1594
1595 return true;
1596}
1597EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1598
1599/*
1600 * Read the config data for a PCI device, sanity-check it
1601 * and fill in the dev structure...
1602 */
1603static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1604{
1605 struct pci_dev *dev;
1606 u32 l;
1607
1608 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1609 return NULL;
1610
1611 dev = pci_alloc_dev(bus);
1612 if (!dev)
1613 return NULL;
1614
1615 dev->devfn = devfn;
1616 dev->vendor = l & 0xffff;
1617 dev->device = (l >> 16) & 0xffff;
1618
1619 pci_set_of_node(dev);
1620
1621 if (pci_setup_device(dev)) {
1622 pci_bus_put(dev->bus);
1623 kfree(dev);
1624 return NULL;
1625 }
1626
1627 return dev;
1628}
1629
1630static void pci_init_capabilities(struct pci_dev *dev)
1631{
1632 /* Enhanced Allocation */
1633 pci_ea_init(dev);
1634
1635 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1636 pci_msi_setup_pci_dev(dev);
1637
1638 /* Buffers for saving PCIe and PCI-X capabilities */
1639 pci_allocate_cap_save_buffers(dev);
1640
1641 /* Power Management */
1642 pci_pm_init(dev);
1643
1644 /* Vital Product Data */
1645 pci_vpd_init(dev);
1646
1647 /* Alternative Routing-ID Forwarding */
1648 pci_configure_ari(dev);
1649
1650 /* Single Root I/O Virtualization */
1651 pci_iov_init(dev);
1652
1653 /* Address Translation Services */
1654 pci_ats_init(dev);
1655
1656 /* Enable ACS P2P upstream forwarding */
1657 pci_enable_acs(dev);
1658
1659 pci_cleanup_aer_error_status_regs(dev);
1660}
1661
1662/*
1663 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1664 * devices. Firmware interfaces that can select the MSI domain on a
1665 * per-device basis should be called from here.
1666 */
1667static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1668{
1669 struct irq_domain *d;
1670
1671 /*
1672 * If a domain has been set through the pcibios_add_device
1673 * callback, then this is the one (platform code knows best).
1674 */
1675 d = dev_get_msi_domain(&dev->dev);
1676 if (d)
1677 return d;
1678
1679 /*
1680 * Let's see if we have a firmware interface able to provide
1681 * the domain.
1682 */
1683 d = pci_msi_get_device_domain(dev);
1684 if (d)
1685 return d;
1686
1687 return NULL;
1688}
1689
1690static void pci_set_msi_domain(struct pci_dev *dev)
1691{
1692 struct irq_domain *d;
1693
1694 /*
1695 * If the platform or firmware interfaces cannot supply a
1696 * device-specific MSI domain, then inherit the default domain
1697 * from the host bridge itself.
1698 */
1699 d = pci_dev_msi_domain(dev);
1700 if (!d)
1701 d = dev_get_msi_domain(&dev->bus->dev);
1702
1703 dev_set_msi_domain(&dev->dev, d);
1704}
1705
1706/**
1707 * pci_dma_configure - Setup DMA configuration
1708 * @dev: ptr to pci_dev struct of the PCI device
1709 *
1710 * Function to update PCI devices's DMA configuration using the same
1711 * info from the OF node or ACPI node of host bridge's parent (if any).
1712 */
1713static void pci_dma_configure(struct pci_dev *dev)
1714{
1715 struct device *bridge = pci_get_host_bridge_device(dev);
1716
1717 if (IS_ENABLED(CONFIG_OF) &&
1718 bridge->parent && bridge->parent->of_node) {
1719 of_dma_configure(&dev->dev, bridge->parent->of_node);
1720 } else if (has_acpi_companion(bridge)) {
1721 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1722 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1723
1724 if (attr == DEV_DMA_NOT_SUPPORTED)
1725 dev_warn(&dev->dev, "DMA not supported.\n");
1726 else
1727 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1728 attr == DEV_DMA_COHERENT);
1729 }
1730
1731 pci_put_host_bridge_device(bridge);
1732}
1733
1734void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1735{
1736 int ret;
1737
1738 pci_configure_device(dev);
1739
1740 device_initialize(&dev->dev);
1741 dev->dev.release = pci_release_dev;
1742
1743 set_dev_node(&dev->dev, pcibus_to_node(bus));
1744 dev->dev.dma_mask = &dev->dma_mask;
1745 dev->dev.dma_parms = &dev->dma_parms;
1746 dev->dev.coherent_dma_mask = 0xffffffffull;
1747 pci_dma_configure(dev);
1748
1749 pci_set_dma_max_seg_size(dev, 65536);
1750 pci_set_dma_seg_boundary(dev, 0xffffffff);
1751
1752 /* Fix up broken headers */
1753 pci_fixup_device(pci_fixup_header, dev);
1754
1755 /* moved out from quirk header fixup code */
1756 pci_reassigndev_resource_alignment(dev);
1757
1758 /* Clear the state_saved flag. */
1759 dev->state_saved = false;
1760
1761 /* Initialize various capabilities */
1762 pci_init_capabilities(dev);
1763
1764 /*
1765 * Add the device to our list of discovered devices
1766 * and the bus list for fixup functions, etc.
1767 */
1768 down_write(&pci_bus_sem);
1769 list_add_tail(&dev->bus_list, &bus->devices);
1770 up_write(&pci_bus_sem);
1771
1772 ret = pcibios_add_device(dev);
1773 WARN_ON(ret < 0);
1774
1775 /* Setup MSI irq domain */
1776 pci_set_msi_domain(dev);
1777
1778 /* Notifier could use PCI capabilities */
1779 dev->match_driver = false;
1780 ret = device_add(&dev->dev);
1781 WARN_ON(ret < 0);
1782}
1783
1784struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1785{
1786 struct pci_dev *dev;
1787
1788 dev = pci_get_slot(bus, devfn);
1789 if (dev) {
1790 pci_dev_put(dev);
1791 return dev;
1792 }
1793
1794 dev = pci_scan_device(bus, devfn);
1795 if (!dev)
1796 return NULL;
1797
1798 pci_device_add(dev, bus);
1799
1800 return dev;
1801}
1802EXPORT_SYMBOL(pci_scan_single_device);
1803
1804static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1805{
1806 int pos;
1807 u16 cap = 0;
1808 unsigned next_fn;
1809
1810 if (pci_ari_enabled(bus)) {
1811 if (!dev)
1812 return 0;
1813 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1814 if (!pos)
1815 return 0;
1816
1817 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1818 next_fn = PCI_ARI_CAP_NFN(cap);
1819 if (next_fn <= fn)
1820 return 0; /* protect against malformed list */
1821
1822 return next_fn;
1823 }
1824
1825 /* dev may be NULL for non-contiguous multifunction devices */
1826 if (!dev || dev->multifunction)
1827 return (fn + 1) % 8;
1828
1829 return 0;
1830}
1831
1832static int only_one_child(struct pci_bus *bus)
1833{
1834 struct pci_dev *parent = bus->self;
1835
1836 if (!parent || !pci_is_pcie(parent))
1837 return 0;
1838 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1839 return 1;
1840
1841 /*
1842 * PCIe downstream ports are bridges that normally lead to only a
1843 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
1844 * possible devices, not just device 0. See PCIe spec r3.0,
1845 * sec 7.3.1.
1846 */
1847 if (parent->has_secondary_link &&
1848 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1849 return 1;
1850 return 0;
1851}
1852
1853/**
1854 * pci_scan_slot - scan a PCI slot on a bus for devices.
1855 * @bus: PCI bus to scan
1856 * @devfn: slot number to scan (must have zero function.)
1857 *
1858 * Scan a PCI slot on the specified PCI bus for devices, adding
1859 * discovered devices to the @bus->devices list. New devices
1860 * will not have is_added set.
1861 *
1862 * Returns the number of new devices found.
1863 */
1864int pci_scan_slot(struct pci_bus *bus, int devfn)
1865{
1866 unsigned fn, nr = 0;
1867 struct pci_dev *dev;
1868
1869 if (only_one_child(bus) && (devfn > 0))
1870 return 0; /* Already scanned the entire slot */
1871
1872 dev = pci_scan_single_device(bus, devfn);
1873 if (!dev)
1874 return 0;
1875 if (!dev->is_added)
1876 nr++;
1877
1878 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1879 dev = pci_scan_single_device(bus, devfn + fn);
1880 if (dev) {
1881 if (!dev->is_added)
1882 nr++;
1883 dev->multifunction = 1;
1884 }
1885 }
1886
1887 /* only one slot has pcie device */
1888 if (bus->self && nr)
1889 pcie_aspm_init_link_state(bus->self);
1890
1891 return nr;
1892}
1893EXPORT_SYMBOL(pci_scan_slot);
1894
1895static int pcie_find_smpss(struct pci_dev *dev, void *data)
1896{
1897 u8 *smpss = data;
1898
1899 if (!pci_is_pcie(dev))
1900 return 0;
1901
1902 /*
1903 * We don't have a way to change MPS settings on devices that have
1904 * drivers attached. A hot-added device might support only the minimum
1905 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1906 * where devices may be hot-added, we limit the fabric MPS to 128 so
1907 * hot-added devices will work correctly.
1908 *
1909 * However, if we hot-add a device to a slot directly below a Root
1910 * Port, it's impossible for there to be other existing devices below
1911 * the port. We don't limit the MPS in this case because we can
1912 * reconfigure MPS on both the Root Port and the hot-added device,
1913 * and there are no other devices involved.
1914 *
1915 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1916 */
1917 if (dev->is_hotplug_bridge &&
1918 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1919 *smpss = 0;
1920
1921 if (*smpss > dev->pcie_mpss)
1922 *smpss = dev->pcie_mpss;
1923
1924 return 0;
1925}
1926
1927static void pcie_write_mps(struct pci_dev *dev, int mps)
1928{
1929 int rc;
1930
1931 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1932 mps = 128 << dev->pcie_mpss;
1933
1934 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1935 dev->bus->self)
1936 /* For "Performance", the assumption is made that
1937 * downstream communication will never be larger than
1938 * the MRRS. So, the MPS only needs to be configured
1939 * for the upstream communication. This being the case,
1940 * walk from the top down and set the MPS of the child
1941 * to that of the parent bus.
1942 *
1943 * Configure the device MPS with the smaller of the
1944 * device MPSS or the bridge MPS (which is assumed to be
1945 * properly configured at this point to the largest
1946 * allowable MPS based on its parent bus).
1947 */
1948 mps = min(mps, pcie_get_mps(dev->bus->self));
1949 }
1950
1951 rc = pcie_set_mps(dev, mps);
1952 if (rc)
1953 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1954}
1955
1956static void pcie_write_mrrs(struct pci_dev *dev)
1957{
1958 int rc, mrrs;
1959
1960 /* In the "safe" case, do not configure the MRRS. There appear to be
1961 * issues with setting MRRS to 0 on a number of devices.
1962 */
1963 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1964 return;
1965
1966 /* For Max performance, the MRRS must be set to the largest supported
1967 * value. However, it cannot be configured larger than the MPS the
1968 * device or the bus can support. This should already be properly
1969 * configured by a prior call to pcie_write_mps.
1970 */
1971 mrrs = pcie_get_mps(dev);
1972
1973 /* MRRS is a R/W register. Invalid values can be written, but a
1974 * subsequent read will verify if the value is acceptable or not.
1975 * If the MRRS value provided is not acceptable (e.g., too large),
1976 * shrink the value until it is acceptable to the HW.
1977 */
1978 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1979 rc = pcie_set_readrq(dev, mrrs);
1980 if (!rc)
1981 break;
1982
1983 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1984 mrrs /= 2;
1985 }
1986
1987 if (mrrs < 128)
1988 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1989}
1990
1991static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1992{
1993 int mps, orig_mps;
1994
1995 if (!pci_is_pcie(dev))
1996 return 0;
1997
1998 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
1999 pcie_bus_config == PCIE_BUS_DEFAULT)
2000 return 0;
2001
2002 mps = 128 << *(u8 *)data;
2003 orig_mps = pcie_get_mps(dev);
2004
2005 pcie_write_mps(dev, mps);
2006 pcie_write_mrrs(dev);
2007
2008 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2009 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2010 orig_mps, pcie_get_readrq(dev));
2011
2012 return 0;
2013}
2014
2015/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2016 * parents then children fashion. If this changes, then this code will not
2017 * work as designed.
2018 */
2019void pcie_bus_configure_settings(struct pci_bus *bus)
2020{
2021 u8 smpss = 0;
2022
2023 if (!bus->self)
2024 return;
2025
2026 if (!pci_is_pcie(bus->self))
2027 return;
2028
2029 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2030 * to be aware of the MPS of the destination. To work around this,
2031 * simply force the MPS of the entire system to the smallest possible.
2032 */
2033 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2034 smpss = 0;
2035
2036 if (pcie_bus_config == PCIE_BUS_SAFE) {
2037 smpss = bus->self->pcie_mpss;
2038
2039 pcie_find_smpss(bus->self, &smpss);
2040 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2041 }
2042
2043 pcie_bus_configure_set(bus->self, &smpss);
2044 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2045}
2046EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2047
2048unsigned int pci_scan_child_bus(struct pci_bus *bus)
2049{
2050 unsigned int devfn, pass, max = bus->busn_res.start;
2051 struct pci_dev *dev;
2052
2053 dev_dbg(&bus->dev, "scanning bus\n");
2054
2055 /* Go find them, Rover! */
2056 for (devfn = 0; devfn < 0x100; devfn += 8)
2057 pci_scan_slot(bus, devfn);
2058
2059 /* Reserve buses for SR-IOV capability. */
2060 max += pci_iov_bus_range(bus);
2061
2062 /*
2063 * After performing arch-dependent fixup of the bus, look behind
2064 * all PCI-to-PCI bridges on this bus.
2065 */
2066 if (!bus->is_added) {
2067 dev_dbg(&bus->dev, "fixups for bus\n");
2068 pcibios_fixup_bus(bus);
2069 bus->is_added = 1;
2070 }
2071
2072 for (pass = 0; pass < 2; pass++)
2073 list_for_each_entry(dev, &bus->devices, bus_list) {
2074 if (pci_is_bridge(dev))
2075 max = pci_scan_bridge(bus, dev, max, pass);
2076 }
2077
2078 /*
2079 * We've scanned the bus and so we know all about what's on
2080 * the other side of any bridges that may be on this bus plus
2081 * any devices.
2082 *
2083 * Return how far we've got finding sub-buses.
2084 */
2085 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2086 return max;
2087}
2088EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2089
2090/**
2091 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2092 * @bridge: Host bridge to set up.
2093 *
2094 * Default empty implementation. Replace with an architecture-specific setup
2095 * routine, if necessary.
2096 */
2097int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2098{
2099 return 0;
2100}
2101
2102void __weak pcibios_add_bus(struct pci_bus *bus)
2103{
2104}
2105
2106void __weak pcibios_remove_bus(struct pci_bus *bus)
2107{
2108}
2109
2110struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2111 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2112{
2113 int error;
2114 struct pci_host_bridge *bridge;
2115 struct pci_bus *b, *b2;
2116 struct resource_entry *window, *n;
2117 struct resource *res;
2118 resource_size_t offset;
2119 char bus_addr[64];
2120 char *fmt;
2121
2122 b = pci_alloc_bus(NULL);
2123 if (!b)
2124 return NULL;
2125
2126 b->sysdata = sysdata;
2127 b->ops = ops;
2128 b->number = b->busn_res.start = bus;
2129 pci_bus_assign_domain_nr(b, parent);
2130 b2 = pci_find_bus(pci_domain_nr(b), bus);
2131 if (b2) {
2132 /* If we already got to this bus through a different bridge, ignore it */
2133 dev_dbg(&b2->dev, "bus already known\n");
2134 goto err_out;
2135 }
2136
2137 bridge = pci_alloc_host_bridge(b);
2138 if (!bridge)
2139 goto err_out;
2140
2141 bridge->dev.parent = parent;
2142 bridge->dev.release = pci_release_host_bridge_dev;
2143 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2144 error = pcibios_root_bridge_prepare(bridge);
2145 if (error) {
2146 kfree(bridge);
2147 goto err_out;
2148 }
2149
2150 error = device_register(&bridge->dev);
2151 if (error) {
2152 put_device(&bridge->dev);
2153 goto err_out;
2154 }
2155 b->bridge = get_device(&bridge->dev);
2156 device_enable_async_suspend(b->bridge);
2157 pci_set_bus_of_node(b);
2158 pci_set_bus_msi_domain(b);
2159
2160 if (!parent)
2161 set_dev_node(b->bridge, pcibus_to_node(b));
2162
2163 b->dev.class = &pcibus_class;
2164 b->dev.parent = b->bridge;
2165 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2166 error = device_register(&b->dev);
2167 if (error)
2168 goto class_dev_reg_err;
2169
2170 pcibios_add_bus(b);
2171
2172 /* Create legacy_io and legacy_mem files for this bus */
2173 pci_create_legacy_files(b);
2174
2175 if (parent)
2176 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2177 else
2178 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2179
2180 /* Add initial resources to the bus */
2181 resource_list_for_each_entry_safe(window, n, resources) {
2182 list_move_tail(&window->node, &bridge->windows);
2183 res = window->res;
2184 offset = window->offset;
2185 if (res->flags & IORESOURCE_BUS)
2186 pci_bus_insert_busn_res(b, bus, res->end);
2187 else
2188 pci_bus_add_resource(b, res, 0);
2189 if (offset) {
2190 if (resource_type(res) == IORESOURCE_IO)
2191 fmt = " (bus address [%#06llx-%#06llx])";
2192 else
2193 fmt = " (bus address [%#010llx-%#010llx])";
2194 snprintf(bus_addr, sizeof(bus_addr), fmt,
2195 (unsigned long long) (res->start - offset),
2196 (unsigned long long) (res->end - offset));
2197 } else
2198 bus_addr[0] = '\0';
2199 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2200 }
2201
2202 down_write(&pci_bus_sem);
2203 list_add_tail(&b->node, &pci_root_buses);
2204 up_write(&pci_bus_sem);
2205
2206 return b;
2207
2208class_dev_reg_err:
2209 put_device(&bridge->dev);
2210 device_unregister(&bridge->dev);
2211err_out:
2212 kfree(b);
2213 return NULL;
2214}
2215EXPORT_SYMBOL_GPL(pci_create_root_bus);
2216
2217int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2218{
2219 struct resource *res = &b->busn_res;
2220 struct resource *parent_res, *conflict;
2221
2222 res->start = bus;
2223 res->end = bus_max;
2224 res->flags = IORESOURCE_BUS;
2225
2226 if (!pci_is_root_bus(b))
2227 parent_res = &b->parent->busn_res;
2228 else {
2229 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2230 res->flags |= IORESOURCE_PCI_FIXED;
2231 }
2232
2233 conflict = request_resource_conflict(parent_res, res);
2234
2235 if (conflict)
2236 dev_printk(KERN_DEBUG, &b->dev,
2237 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2238 res, pci_is_root_bus(b) ? "domain " : "",
2239 parent_res, conflict->name, conflict);
2240
2241 return conflict == NULL;
2242}
2243
2244int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2245{
2246 struct resource *res = &b->busn_res;
2247 struct resource old_res = *res;
2248 resource_size_t size;
2249 int ret;
2250
2251 if (res->start > bus_max)
2252 return -EINVAL;
2253
2254 size = bus_max - res->start + 1;
2255 ret = adjust_resource(res, res->start, size);
2256 dev_printk(KERN_DEBUG, &b->dev,
2257 "busn_res: %pR end %s updated to %02x\n",
2258 &old_res, ret ? "can not be" : "is", bus_max);
2259
2260 if (!ret && !res->parent)
2261 pci_bus_insert_busn_res(b, res->start, res->end);
2262
2263 return ret;
2264}
2265
2266void pci_bus_release_busn_res(struct pci_bus *b)
2267{
2268 struct resource *res = &b->busn_res;
2269 int ret;
2270
2271 if (!res->flags || !res->parent)
2272 return;
2273
2274 ret = release_resource(res);
2275 dev_printk(KERN_DEBUG, &b->dev,
2276 "busn_res: %pR %s released\n",
2277 res, ret ? "can not be" : "is");
2278}
2279
2280struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2281 struct pci_ops *ops, void *sysdata,
2282 struct list_head *resources, struct msi_controller *msi)
2283{
2284 struct resource_entry *window;
2285 bool found = false;
2286 struct pci_bus *b;
2287 int max;
2288
2289 resource_list_for_each_entry(window, resources)
2290 if (window->res->flags & IORESOURCE_BUS) {
2291 found = true;
2292 break;
2293 }
2294
2295 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2296 if (!b)
2297 return NULL;
2298
2299 b->msi = msi;
2300
2301 if (!found) {
2302 dev_info(&b->dev,
2303 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2304 bus);
2305 pci_bus_insert_busn_res(b, bus, 255);
2306 }
2307
2308 max = pci_scan_child_bus(b);
2309
2310 if (!found)
2311 pci_bus_update_busn_res_end(b, max);
2312
2313 return b;
2314}
2315
2316struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2317 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2318{
2319 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2320 NULL);
2321}
2322EXPORT_SYMBOL(pci_scan_root_bus);
2323
2324struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2325 void *sysdata)
2326{
2327 LIST_HEAD(resources);
2328 struct pci_bus *b;
2329
2330 pci_add_resource(&resources, &ioport_resource);
2331 pci_add_resource(&resources, &iomem_resource);
2332 pci_add_resource(&resources, &busn_resource);
2333 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2334 if (b) {
2335 pci_scan_child_bus(b);
2336 } else {
2337 pci_free_resource_list(&resources);
2338 }
2339 return b;
2340}
2341EXPORT_SYMBOL(pci_scan_bus);
2342
2343/**
2344 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2345 * @bridge: PCI bridge for the bus to scan
2346 *
2347 * Scan a PCI bus and child buses for new devices, add them,
2348 * and enable them, resizing bridge mmio/io resource if necessary
2349 * and possible. The caller must ensure the child devices are already
2350 * removed for resizing to occur.
2351 *
2352 * Returns the max number of subordinate bus discovered.
2353 */
2354unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2355{
2356 unsigned int max;
2357 struct pci_bus *bus = bridge->subordinate;
2358
2359 max = pci_scan_child_bus(bus);
2360
2361 pci_assign_unassigned_bridge_resources(bridge);
2362
2363 pci_bus_add_devices(bus);
2364
2365 return max;
2366}
2367
2368/**
2369 * pci_rescan_bus - scan a PCI bus for devices.
2370 * @bus: PCI bus to scan
2371 *
2372 * Scan a PCI bus and child buses for new devices, adds them,
2373 * and enables them.
2374 *
2375 * Returns the max number of subordinate bus discovered.
2376 */
2377unsigned int pci_rescan_bus(struct pci_bus *bus)
2378{
2379 unsigned int max;
2380
2381 max = pci_scan_child_bus(bus);
2382 pci_assign_unassigned_bus_resources(bus);
2383 pci_bus_add_devices(bus);
2384
2385 return max;
2386}
2387EXPORT_SYMBOL_GPL(pci_rescan_bus);
2388
2389/*
2390 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2391 * routines should always be executed under this mutex.
2392 */
2393static DEFINE_MUTEX(pci_rescan_remove_lock);
2394
2395void pci_lock_rescan_remove(void)
2396{
2397 mutex_lock(&pci_rescan_remove_lock);
2398}
2399EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2400
2401void pci_unlock_rescan_remove(void)
2402{
2403 mutex_unlock(&pci_rescan_remove_lock);
2404}
2405EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2406
2407static int __init pci_sort_bf_cmp(const struct device *d_a,
2408 const struct device *d_b)
2409{
2410 const struct pci_dev *a = to_pci_dev(d_a);
2411 const struct pci_dev *b = to_pci_dev(d_b);
2412
2413 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2414 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2415
2416 if (a->bus->number < b->bus->number) return -1;
2417 else if (a->bus->number > b->bus->number) return 1;
2418
2419 if (a->devfn < b->devfn) return -1;
2420 else if (a->devfn > b->devfn) return 1;
2421
2422 return 0;
2423}
2424
2425void __init pci_sort_breadthfirst(void)
2426{
2427 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2428}