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1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include "drmP.h"
28#include "radeon.h"
29#include "radeon_asic.h"
30#include "radeon_drm.h"
31#include "nid.h"
32#include "atom.h"
33#include "ni_reg.h"
34#include "cayman_blit_shaders.h"
35
36extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
37extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
38extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
39extern void evergreen_mc_program(struct radeon_device *rdev);
40extern void evergreen_irq_suspend(struct radeon_device *rdev);
41extern int evergreen_mc_init(struct radeon_device *rdev);
42extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
43
44#define EVERGREEN_PFP_UCODE_SIZE 1120
45#define EVERGREEN_PM4_UCODE_SIZE 1376
46#define EVERGREEN_RLC_UCODE_SIZE 768
47#define BTC_MC_UCODE_SIZE 6024
48
49#define CAYMAN_PFP_UCODE_SIZE 2176
50#define CAYMAN_PM4_UCODE_SIZE 2176
51#define CAYMAN_RLC_UCODE_SIZE 1024
52#define CAYMAN_MC_UCODE_SIZE 6037
53
54/* Firmware Names */
55MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
56MODULE_FIRMWARE("radeon/BARTS_me.bin");
57MODULE_FIRMWARE("radeon/BARTS_mc.bin");
58MODULE_FIRMWARE("radeon/BTC_rlc.bin");
59MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
60MODULE_FIRMWARE("radeon/TURKS_me.bin");
61MODULE_FIRMWARE("radeon/TURKS_mc.bin");
62MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
63MODULE_FIRMWARE("radeon/CAICOS_me.bin");
64MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
65MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
66MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
67MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
68MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
69
70#define BTC_IO_MC_REGS_SIZE 29
71
72static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
73 {0x00000077, 0xff010100},
74 {0x00000078, 0x00000000},
75 {0x00000079, 0x00001434},
76 {0x0000007a, 0xcc08ec08},
77 {0x0000007b, 0x00040000},
78 {0x0000007c, 0x000080c0},
79 {0x0000007d, 0x09000000},
80 {0x0000007e, 0x00210404},
81 {0x00000081, 0x08a8e800},
82 {0x00000082, 0x00030444},
83 {0x00000083, 0x00000000},
84 {0x00000085, 0x00000001},
85 {0x00000086, 0x00000002},
86 {0x00000087, 0x48490000},
87 {0x00000088, 0x20244647},
88 {0x00000089, 0x00000005},
89 {0x0000008b, 0x66030000},
90 {0x0000008c, 0x00006603},
91 {0x0000008d, 0x00000100},
92 {0x0000008f, 0x00001c0a},
93 {0x00000090, 0xff000001},
94 {0x00000094, 0x00101101},
95 {0x00000095, 0x00000fff},
96 {0x00000096, 0x00116fff},
97 {0x00000097, 0x60010000},
98 {0x00000098, 0x10010000},
99 {0x00000099, 0x00006000},
100 {0x0000009a, 0x00001000},
101 {0x0000009f, 0x00946a00}
102};
103
104static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
105 {0x00000077, 0xff010100},
106 {0x00000078, 0x00000000},
107 {0x00000079, 0x00001434},
108 {0x0000007a, 0xcc08ec08},
109 {0x0000007b, 0x00040000},
110 {0x0000007c, 0x000080c0},
111 {0x0000007d, 0x09000000},
112 {0x0000007e, 0x00210404},
113 {0x00000081, 0x08a8e800},
114 {0x00000082, 0x00030444},
115 {0x00000083, 0x00000000},
116 {0x00000085, 0x00000001},
117 {0x00000086, 0x00000002},
118 {0x00000087, 0x48490000},
119 {0x00000088, 0x20244647},
120 {0x00000089, 0x00000005},
121 {0x0000008b, 0x66030000},
122 {0x0000008c, 0x00006603},
123 {0x0000008d, 0x00000100},
124 {0x0000008f, 0x00001c0a},
125 {0x00000090, 0xff000001},
126 {0x00000094, 0x00101101},
127 {0x00000095, 0x00000fff},
128 {0x00000096, 0x00116fff},
129 {0x00000097, 0x60010000},
130 {0x00000098, 0x10010000},
131 {0x00000099, 0x00006000},
132 {0x0000009a, 0x00001000},
133 {0x0000009f, 0x00936a00}
134};
135
136static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
137 {0x00000077, 0xff010100},
138 {0x00000078, 0x00000000},
139 {0x00000079, 0x00001434},
140 {0x0000007a, 0xcc08ec08},
141 {0x0000007b, 0x00040000},
142 {0x0000007c, 0x000080c0},
143 {0x0000007d, 0x09000000},
144 {0x0000007e, 0x00210404},
145 {0x00000081, 0x08a8e800},
146 {0x00000082, 0x00030444},
147 {0x00000083, 0x00000000},
148 {0x00000085, 0x00000001},
149 {0x00000086, 0x00000002},
150 {0x00000087, 0x48490000},
151 {0x00000088, 0x20244647},
152 {0x00000089, 0x00000005},
153 {0x0000008b, 0x66030000},
154 {0x0000008c, 0x00006603},
155 {0x0000008d, 0x00000100},
156 {0x0000008f, 0x00001c0a},
157 {0x00000090, 0xff000001},
158 {0x00000094, 0x00101101},
159 {0x00000095, 0x00000fff},
160 {0x00000096, 0x00116fff},
161 {0x00000097, 0x60010000},
162 {0x00000098, 0x10010000},
163 {0x00000099, 0x00006000},
164 {0x0000009a, 0x00001000},
165 {0x0000009f, 0x00916a00}
166};
167
168static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
169 {0x00000077, 0xff010100},
170 {0x00000078, 0x00000000},
171 {0x00000079, 0x00001434},
172 {0x0000007a, 0xcc08ec08},
173 {0x0000007b, 0x00040000},
174 {0x0000007c, 0x000080c0},
175 {0x0000007d, 0x09000000},
176 {0x0000007e, 0x00210404},
177 {0x00000081, 0x08a8e800},
178 {0x00000082, 0x00030444},
179 {0x00000083, 0x00000000},
180 {0x00000085, 0x00000001},
181 {0x00000086, 0x00000002},
182 {0x00000087, 0x48490000},
183 {0x00000088, 0x20244647},
184 {0x00000089, 0x00000005},
185 {0x0000008b, 0x66030000},
186 {0x0000008c, 0x00006603},
187 {0x0000008d, 0x00000100},
188 {0x0000008f, 0x00001c0a},
189 {0x00000090, 0xff000001},
190 {0x00000094, 0x00101101},
191 {0x00000095, 0x00000fff},
192 {0x00000096, 0x00116fff},
193 {0x00000097, 0x60010000},
194 {0x00000098, 0x10010000},
195 {0x00000099, 0x00006000},
196 {0x0000009a, 0x00001000},
197 {0x0000009f, 0x00976b00}
198};
199
200int ni_mc_load_microcode(struct radeon_device *rdev)
201{
202 const __be32 *fw_data;
203 u32 mem_type, running, blackout = 0;
204 u32 *io_mc_regs;
205 int i, ucode_size, regs_size;
206
207 if (!rdev->mc_fw)
208 return -EINVAL;
209
210 switch (rdev->family) {
211 case CHIP_BARTS:
212 io_mc_regs = (u32 *)&barts_io_mc_regs;
213 ucode_size = BTC_MC_UCODE_SIZE;
214 regs_size = BTC_IO_MC_REGS_SIZE;
215 break;
216 case CHIP_TURKS:
217 io_mc_regs = (u32 *)&turks_io_mc_regs;
218 ucode_size = BTC_MC_UCODE_SIZE;
219 regs_size = BTC_IO_MC_REGS_SIZE;
220 break;
221 case CHIP_CAICOS:
222 default:
223 io_mc_regs = (u32 *)&caicos_io_mc_regs;
224 ucode_size = BTC_MC_UCODE_SIZE;
225 regs_size = BTC_IO_MC_REGS_SIZE;
226 break;
227 case CHIP_CAYMAN:
228 io_mc_regs = (u32 *)&cayman_io_mc_regs;
229 ucode_size = CAYMAN_MC_UCODE_SIZE;
230 regs_size = BTC_IO_MC_REGS_SIZE;
231 break;
232 }
233
234 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
235 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
236
237 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
238 if (running) {
239 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
240 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
241 }
242
243 /* reset the engine and set to writable */
244 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
245 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
246
247 /* load mc io regs */
248 for (i = 0; i < regs_size; i++) {
249 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
250 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
251 }
252 /* load the MC ucode */
253 fw_data = (const __be32 *)rdev->mc_fw->data;
254 for (i = 0; i < ucode_size; i++)
255 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
256
257 /* put the engine back into the active state */
258 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
259 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
260 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
261
262 /* wait for training to complete */
263 while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD))
264 udelay(10);
265
266 if (running)
267 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
268 }
269
270 return 0;
271}
272
273int ni_init_microcode(struct radeon_device *rdev)
274{
275 struct platform_device *pdev;
276 const char *chip_name;
277 const char *rlc_chip_name;
278 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
279 char fw_name[30];
280 int err;
281
282 DRM_DEBUG("\n");
283
284 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
285 err = IS_ERR(pdev);
286 if (err) {
287 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
288 return -EINVAL;
289 }
290
291 switch (rdev->family) {
292 case CHIP_BARTS:
293 chip_name = "BARTS";
294 rlc_chip_name = "BTC";
295 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
296 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
297 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
298 mc_req_size = BTC_MC_UCODE_SIZE * 4;
299 break;
300 case CHIP_TURKS:
301 chip_name = "TURKS";
302 rlc_chip_name = "BTC";
303 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
304 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
305 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
306 mc_req_size = BTC_MC_UCODE_SIZE * 4;
307 break;
308 case CHIP_CAICOS:
309 chip_name = "CAICOS";
310 rlc_chip_name = "BTC";
311 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
312 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
313 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
314 mc_req_size = BTC_MC_UCODE_SIZE * 4;
315 break;
316 case CHIP_CAYMAN:
317 chip_name = "CAYMAN";
318 rlc_chip_name = "CAYMAN";
319 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
320 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
321 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
322 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
323 break;
324 default: BUG();
325 }
326
327 DRM_INFO("Loading %s Microcode\n", chip_name);
328
329 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
330 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
331 if (err)
332 goto out;
333 if (rdev->pfp_fw->size != pfp_req_size) {
334 printk(KERN_ERR
335 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
336 rdev->pfp_fw->size, fw_name);
337 err = -EINVAL;
338 goto out;
339 }
340
341 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
342 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
343 if (err)
344 goto out;
345 if (rdev->me_fw->size != me_req_size) {
346 printk(KERN_ERR
347 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
348 rdev->me_fw->size, fw_name);
349 err = -EINVAL;
350 }
351
352 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
353 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
354 if (err)
355 goto out;
356 if (rdev->rlc_fw->size != rlc_req_size) {
357 printk(KERN_ERR
358 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
359 rdev->rlc_fw->size, fw_name);
360 err = -EINVAL;
361 }
362
363 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
364 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
365 if (err)
366 goto out;
367 if (rdev->mc_fw->size != mc_req_size) {
368 printk(KERN_ERR
369 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
370 rdev->mc_fw->size, fw_name);
371 err = -EINVAL;
372 }
373out:
374 platform_device_unregister(pdev);
375
376 if (err) {
377 if (err != -EINVAL)
378 printk(KERN_ERR
379 "ni_cp: Failed to load firmware \"%s\"\n",
380 fw_name);
381 release_firmware(rdev->pfp_fw);
382 rdev->pfp_fw = NULL;
383 release_firmware(rdev->me_fw);
384 rdev->me_fw = NULL;
385 release_firmware(rdev->rlc_fw);
386 rdev->rlc_fw = NULL;
387 release_firmware(rdev->mc_fw);
388 rdev->mc_fw = NULL;
389 }
390 return err;
391}
392
393/*
394 * Core functions
395 */
396static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
397 u32 num_tile_pipes,
398 u32 num_backends_per_asic,
399 u32 *backend_disable_mask_per_asic,
400 u32 num_shader_engines)
401{
402 u32 backend_map = 0;
403 u32 enabled_backends_mask = 0;
404 u32 enabled_backends_count = 0;
405 u32 num_backends_per_se;
406 u32 cur_pipe;
407 u32 swizzle_pipe[CAYMAN_MAX_PIPES];
408 u32 cur_backend = 0;
409 u32 i;
410 bool force_no_swizzle;
411
412 /* force legal values */
413 if (num_tile_pipes < 1)
414 num_tile_pipes = 1;
415 if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
416 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
417 if (num_shader_engines < 1)
418 num_shader_engines = 1;
419 if (num_shader_engines > rdev->config.cayman.max_shader_engines)
420 num_shader_engines = rdev->config.cayman.max_shader_engines;
421 if (num_backends_per_asic < num_shader_engines)
422 num_backends_per_asic = num_shader_engines;
423 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
424 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
425
426 /* make sure we have the same number of backends per se */
427 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
428 /* set up the number of backends per se */
429 num_backends_per_se = num_backends_per_asic / num_shader_engines;
430 if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
431 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
432 num_backends_per_asic = num_backends_per_se * num_shader_engines;
433 }
434
435 /* create enable mask and count for enabled backends */
436 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
437 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
438 enabled_backends_mask |= (1 << i);
439 ++enabled_backends_count;
440 }
441 if (enabled_backends_count == num_backends_per_asic)
442 break;
443 }
444
445 /* force the backends mask to match the current number of backends */
446 if (enabled_backends_count != num_backends_per_asic) {
447 u32 this_backend_enabled;
448 u32 shader_engine;
449 u32 backend_per_se;
450
451 enabled_backends_mask = 0;
452 enabled_backends_count = 0;
453 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
454 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
455 /* calc the current se */
456 shader_engine = i / rdev->config.cayman.max_backends_per_se;
457 /* calc the backend per se */
458 backend_per_se = i % rdev->config.cayman.max_backends_per_se;
459 /* default to not enabled */
460 this_backend_enabled = 0;
461 if ((shader_engine < num_shader_engines) &&
462 (backend_per_se < num_backends_per_se))
463 this_backend_enabled = 1;
464 if (this_backend_enabled) {
465 enabled_backends_mask |= (1 << i);
466 *backend_disable_mask_per_asic &= ~(1 << i);
467 ++enabled_backends_count;
468 }
469 }
470 }
471
472
473 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
474 switch (rdev->family) {
475 case CHIP_CAYMAN:
476 force_no_swizzle = true;
477 break;
478 default:
479 force_no_swizzle = false;
480 break;
481 }
482 if (force_no_swizzle) {
483 bool last_backend_enabled = false;
484
485 force_no_swizzle = false;
486 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
487 if (((enabled_backends_mask >> i) & 1) == 1) {
488 if (last_backend_enabled)
489 force_no_swizzle = true;
490 last_backend_enabled = true;
491 } else
492 last_backend_enabled = false;
493 }
494 }
495
496 switch (num_tile_pipes) {
497 case 1:
498 case 3:
499 case 5:
500 case 7:
501 DRM_ERROR("odd number of pipes!\n");
502 break;
503 case 2:
504 swizzle_pipe[0] = 0;
505 swizzle_pipe[1] = 1;
506 break;
507 case 4:
508 if (force_no_swizzle) {
509 swizzle_pipe[0] = 0;
510 swizzle_pipe[1] = 1;
511 swizzle_pipe[2] = 2;
512 swizzle_pipe[3] = 3;
513 } else {
514 swizzle_pipe[0] = 0;
515 swizzle_pipe[1] = 2;
516 swizzle_pipe[2] = 1;
517 swizzle_pipe[3] = 3;
518 }
519 break;
520 case 6:
521 if (force_no_swizzle) {
522 swizzle_pipe[0] = 0;
523 swizzle_pipe[1] = 1;
524 swizzle_pipe[2] = 2;
525 swizzle_pipe[3] = 3;
526 swizzle_pipe[4] = 4;
527 swizzle_pipe[5] = 5;
528 } else {
529 swizzle_pipe[0] = 0;
530 swizzle_pipe[1] = 2;
531 swizzle_pipe[2] = 4;
532 swizzle_pipe[3] = 1;
533 swizzle_pipe[4] = 3;
534 swizzle_pipe[5] = 5;
535 }
536 break;
537 case 8:
538 if (force_no_swizzle) {
539 swizzle_pipe[0] = 0;
540 swizzle_pipe[1] = 1;
541 swizzle_pipe[2] = 2;
542 swizzle_pipe[3] = 3;
543 swizzle_pipe[4] = 4;
544 swizzle_pipe[5] = 5;
545 swizzle_pipe[6] = 6;
546 swizzle_pipe[7] = 7;
547 } else {
548 swizzle_pipe[0] = 0;
549 swizzle_pipe[1] = 2;
550 swizzle_pipe[2] = 4;
551 swizzle_pipe[3] = 6;
552 swizzle_pipe[4] = 1;
553 swizzle_pipe[5] = 3;
554 swizzle_pipe[6] = 5;
555 swizzle_pipe[7] = 7;
556 }
557 break;
558 }
559
560 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
561 while (((1 << cur_backend) & enabled_backends_mask) == 0)
562 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
563
564 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
565
566 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
567 }
568
569 return backend_map;
570}
571
572static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
573 u32 disable_mask_per_se,
574 u32 max_disable_mask_per_se,
575 u32 num_shader_engines)
576{
577 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
578 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
579
580 if (num_shader_engines == 1)
581 return disable_mask_per_asic;
582 else if (num_shader_engines == 2)
583 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
584 else
585 return 0xffffffff;
586}
587
588static void cayman_gpu_init(struct radeon_device *rdev)
589{
590 u32 cc_rb_backend_disable = 0;
591 u32 cc_gc_shader_pipe_config;
592 u32 gb_addr_config = 0;
593 u32 mc_shared_chmap, mc_arb_ramcfg;
594 u32 gb_backend_map;
595 u32 cgts_tcc_disable;
596 u32 sx_debug_1;
597 u32 smx_dc_ctl0;
598 u32 gc_user_shader_pipe_config;
599 u32 gc_user_rb_backend_disable;
600 u32 cgts_user_tcc_disable;
601 u32 cgts_sm_ctrl_reg;
602 u32 hdp_host_path_cntl;
603 u32 tmp;
604 int i, j;
605
606 switch (rdev->family) {
607 case CHIP_CAYMAN:
608 default:
609 rdev->config.cayman.max_shader_engines = 2;
610 rdev->config.cayman.max_pipes_per_simd = 4;
611 rdev->config.cayman.max_tile_pipes = 8;
612 rdev->config.cayman.max_simds_per_se = 12;
613 rdev->config.cayman.max_backends_per_se = 4;
614 rdev->config.cayman.max_texture_channel_caches = 8;
615 rdev->config.cayman.max_gprs = 256;
616 rdev->config.cayman.max_threads = 256;
617 rdev->config.cayman.max_gs_threads = 32;
618 rdev->config.cayman.max_stack_entries = 512;
619 rdev->config.cayman.sx_num_of_sets = 8;
620 rdev->config.cayman.sx_max_export_size = 256;
621 rdev->config.cayman.sx_max_export_pos_size = 64;
622 rdev->config.cayman.sx_max_export_smx_size = 192;
623 rdev->config.cayman.max_hw_contexts = 8;
624 rdev->config.cayman.sq_num_cf_insts = 2;
625
626 rdev->config.cayman.sc_prim_fifo_size = 0x100;
627 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
628 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
629 break;
630 }
631
632 /* Initialize HDP */
633 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
634 WREG32((0x2c14 + j), 0x00000000);
635 WREG32((0x2c18 + j), 0x00000000);
636 WREG32((0x2c1c + j), 0x00000000);
637 WREG32((0x2c20 + j), 0x00000000);
638 WREG32((0x2c24 + j), 0x00000000);
639 }
640
641 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
642
643 evergreen_fix_pci_max_read_req_size(rdev);
644
645 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
646 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
647
648 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
649 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
650 cgts_tcc_disable = 0xff000000;
651 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
652 gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
653 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
654
655 rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
656 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
657 rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
658 rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
659 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
660 rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
661 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
662 rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
663 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
664 rdev->config.cayman.backend_disable_mask_per_asic =
665 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
666 rdev->config.cayman.num_shader_engines);
667 rdev->config.cayman.backend_map =
668 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
669 rdev->config.cayman.num_backends_per_se *
670 rdev->config.cayman.num_shader_engines,
671 &rdev->config.cayman.backend_disable_mask_per_asic,
672 rdev->config.cayman.num_shader_engines);
673 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
674 rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
675 tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
676 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
677 if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
678 rdev->config.cayman.mem_max_burst_length_bytes = 512;
679 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
680 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
681 if (rdev->config.cayman.mem_row_size_in_kb > 4)
682 rdev->config.cayman.mem_row_size_in_kb = 4;
683 /* XXX use MC settings? */
684 rdev->config.cayman.shader_engine_tile_size = 32;
685 rdev->config.cayman.num_gpus = 1;
686 rdev->config.cayman.multi_gpu_tile_size = 64;
687
688 //gb_addr_config = 0x02011003
689#if 0
690 gb_addr_config = RREG32(GB_ADDR_CONFIG);
691#else
692 gb_addr_config = 0;
693 switch (rdev->config.cayman.num_tile_pipes) {
694 case 1:
695 default:
696 gb_addr_config |= NUM_PIPES(0);
697 break;
698 case 2:
699 gb_addr_config |= NUM_PIPES(1);
700 break;
701 case 4:
702 gb_addr_config |= NUM_PIPES(2);
703 break;
704 case 8:
705 gb_addr_config |= NUM_PIPES(3);
706 break;
707 }
708
709 tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
710 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
711 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
712 tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
713 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
714 switch (rdev->config.cayman.num_gpus) {
715 case 1:
716 default:
717 gb_addr_config |= NUM_GPUS(0);
718 break;
719 case 2:
720 gb_addr_config |= NUM_GPUS(1);
721 break;
722 case 4:
723 gb_addr_config |= NUM_GPUS(2);
724 break;
725 }
726 switch (rdev->config.cayman.multi_gpu_tile_size) {
727 case 16:
728 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
729 break;
730 case 32:
731 default:
732 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
733 break;
734 case 64:
735 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
736 break;
737 case 128:
738 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
739 break;
740 }
741 switch (rdev->config.cayman.mem_row_size_in_kb) {
742 case 1:
743 default:
744 gb_addr_config |= ROW_SIZE(0);
745 break;
746 case 2:
747 gb_addr_config |= ROW_SIZE(1);
748 break;
749 case 4:
750 gb_addr_config |= ROW_SIZE(2);
751 break;
752 }
753#endif
754
755 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
756 rdev->config.cayman.num_tile_pipes = (1 << tmp);
757 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
758 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
759 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
760 rdev->config.cayman.num_shader_engines = tmp + 1;
761 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
762 rdev->config.cayman.num_gpus = tmp + 1;
763 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
764 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
765 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
766 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
767
768 //gb_backend_map = 0x76541032;
769#if 0
770 gb_backend_map = RREG32(GB_BACKEND_MAP);
771#else
772 gb_backend_map =
773 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
774 rdev->config.cayman.num_backends_per_se *
775 rdev->config.cayman.num_shader_engines,
776 &rdev->config.cayman.backend_disable_mask_per_asic,
777 rdev->config.cayman.num_shader_engines);
778#endif
779 /* setup tiling info dword. gb_addr_config is not adequate since it does
780 * not have bank info, so create a custom tiling dword.
781 * bits 3:0 num_pipes
782 * bits 7:4 num_banks
783 * bits 11:8 group_size
784 * bits 15:12 row_size
785 */
786 rdev->config.cayman.tile_config = 0;
787 switch (rdev->config.cayman.num_tile_pipes) {
788 case 1:
789 default:
790 rdev->config.cayman.tile_config |= (0 << 0);
791 break;
792 case 2:
793 rdev->config.cayman.tile_config |= (1 << 0);
794 break;
795 case 4:
796 rdev->config.cayman.tile_config |= (2 << 0);
797 break;
798 case 8:
799 rdev->config.cayman.tile_config |= (3 << 0);
800 break;
801 }
802 rdev->config.cayman.tile_config |=
803 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
804 rdev->config.cayman.tile_config |=
805 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
806 rdev->config.cayman.tile_config |=
807 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
808
809 rdev->config.cayman.backend_map = gb_backend_map;
810 WREG32(GB_BACKEND_MAP, gb_backend_map);
811 WREG32(GB_ADDR_CONFIG, gb_addr_config);
812 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
813 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
814
815 /* primary versions */
816 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
817 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
818 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
819
820 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
821 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
822
823 /* user versions */
824 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
825 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
826 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
827
828 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
829 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
830
831 /* reprogram the shader complex */
832 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
833 for (i = 0; i < 16; i++)
834 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
835 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
836
837 /* set HW defaults for 3D engine */
838 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
839
840 sx_debug_1 = RREG32(SX_DEBUG_1);
841 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
842 WREG32(SX_DEBUG_1, sx_debug_1);
843
844 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
845 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
846 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
847 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
848
849 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
850
851 /* need to be explicitly zero-ed */
852 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
853 WREG32(SQ_LSTMP_RING_BASE, 0);
854 WREG32(SQ_HSTMP_RING_BASE, 0);
855 WREG32(SQ_ESTMP_RING_BASE, 0);
856 WREG32(SQ_GSTMP_RING_BASE, 0);
857 WREG32(SQ_VSTMP_RING_BASE, 0);
858 WREG32(SQ_PSTMP_RING_BASE, 0);
859
860 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
861
862 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
863 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
864 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
865
866 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
867 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
868 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
869
870
871 WREG32(VGT_NUM_INSTANCES, 1);
872
873 WREG32(CP_PERFMON_CNTL, 0);
874
875 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
876 FETCH_FIFO_HIWATER(0x4) |
877 DONE_FIFO_HIWATER(0xe0) |
878 ALU_UPDATE_FIFO_HIWATER(0x8)));
879
880 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
881 WREG32(SQ_CONFIG, (VC_ENABLE |
882 EXPORT_SRC_C |
883 GFX_PRIO(0) |
884 CS1_PRIO(0) |
885 CS2_PRIO(1)));
886 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
887
888 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
889 FORCE_EOV_MAX_REZ_CNT(255)));
890
891 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
892 AUTO_INVLD_EN(ES_AND_GS_AUTO));
893
894 WREG32(VGT_GS_VERTEX_REUSE, 16);
895 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
896
897 WREG32(CB_PERF_CTR0_SEL_0, 0);
898 WREG32(CB_PERF_CTR0_SEL_1, 0);
899 WREG32(CB_PERF_CTR1_SEL_0, 0);
900 WREG32(CB_PERF_CTR1_SEL_1, 0);
901 WREG32(CB_PERF_CTR2_SEL_0, 0);
902 WREG32(CB_PERF_CTR2_SEL_1, 0);
903 WREG32(CB_PERF_CTR3_SEL_0, 0);
904 WREG32(CB_PERF_CTR3_SEL_1, 0);
905
906 tmp = RREG32(HDP_MISC_CNTL);
907 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
908 WREG32(HDP_MISC_CNTL, tmp);
909
910 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
911 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
912
913 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
914
915 udelay(50);
916}
917
918/*
919 * GART
920 */
921void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
922{
923 /* flush hdp cache */
924 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
925
926 /* bits 0-7 are the VM contexts0-7 */
927 WREG32(VM_INVALIDATE_REQUEST, 1);
928}
929
930int cayman_pcie_gart_enable(struct radeon_device *rdev)
931{
932 int r;
933
934 if (rdev->gart.table.vram.robj == NULL) {
935 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
936 return -EINVAL;
937 }
938 r = radeon_gart_table_vram_pin(rdev);
939 if (r)
940 return r;
941 radeon_gart_restore(rdev);
942 /* Setup TLB control */
943 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB |
944 ENABLE_L1_FRAGMENT_PROCESSING |
945 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
946 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
947 /* Setup L2 cache */
948 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
949 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
950 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
951 EFFECTIVE_L2_QUEUE_SIZE(7) |
952 CONTEXT1_IDENTITY_ACCESS_MODE(1));
953 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
954 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
955 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
956 /* setup context0 */
957 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
958 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
959 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
960 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
961 (u32)(rdev->dummy_page.addr >> 12));
962 WREG32(VM_CONTEXT0_CNTL2, 0);
963 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
964 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
965 /* disable context1-7 */
966 WREG32(VM_CONTEXT1_CNTL2, 0);
967 WREG32(VM_CONTEXT1_CNTL, 0);
968
969 cayman_pcie_gart_tlb_flush(rdev);
970 rdev->gart.ready = true;
971 return 0;
972}
973
974void cayman_pcie_gart_disable(struct radeon_device *rdev)
975{
976 int r;
977
978 /* Disable all tables */
979 WREG32(VM_CONTEXT0_CNTL, 0);
980 WREG32(VM_CONTEXT1_CNTL, 0);
981 /* Setup TLB control */
982 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
983 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
984 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
985 /* Setup L2 cache */
986 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
987 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
988 EFFECTIVE_L2_QUEUE_SIZE(7) |
989 CONTEXT1_IDENTITY_ACCESS_MODE(1));
990 WREG32(VM_L2_CNTL2, 0);
991 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
992 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
993 if (rdev->gart.table.vram.robj) {
994 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
995 if (likely(r == 0)) {
996 radeon_bo_kunmap(rdev->gart.table.vram.robj);
997 radeon_bo_unpin(rdev->gart.table.vram.robj);
998 radeon_bo_unreserve(rdev->gart.table.vram.robj);
999 }
1000 }
1001}
1002
1003void cayman_pcie_gart_fini(struct radeon_device *rdev)
1004{
1005 cayman_pcie_gart_disable(rdev);
1006 radeon_gart_table_vram_free(rdev);
1007 radeon_gart_fini(rdev);
1008}
1009
1010/*
1011 * CP.
1012 */
1013static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1014{
1015 if (enable)
1016 WREG32(CP_ME_CNTL, 0);
1017 else {
1018 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1019 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1020 WREG32(SCRATCH_UMSK, 0);
1021 }
1022}
1023
1024static int cayman_cp_load_microcode(struct radeon_device *rdev)
1025{
1026 const __be32 *fw_data;
1027 int i;
1028
1029 if (!rdev->me_fw || !rdev->pfp_fw)
1030 return -EINVAL;
1031
1032 cayman_cp_enable(rdev, false);
1033
1034 fw_data = (const __be32 *)rdev->pfp_fw->data;
1035 WREG32(CP_PFP_UCODE_ADDR, 0);
1036 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1037 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1038 WREG32(CP_PFP_UCODE_ADDR, 0);
1039
1040 fw_data = (const __be32 *)rdev->me_fw->data;
1041 WREG32(CP_ME_RAM_WADDR, 0);
1042 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1043 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1044
1045 WREG32(CP_PFP_UCODE_ADDR, 0);
1046 WREG32(CP_ME_RAM_WADDR, 0);
1047 WREG32(CP_ME_RAM_RADDR, 0);
1048 return 0;
1049}
1050
1051static int cayman_cp_start(struct radeon_device *rdev)
1052{
1053 int r, i;
1054
1055 r = radeon_ring_lock(rdev, 7);
1056 if (r) {
1057 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1058 return r;
1059 }
1060 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1061 radeon_ring_write(rdev, 0x1);
1062 radeon_ring_write(rdev, 0x0);
1063 radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1);
1064 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1065 radeon_ring_write(rdev, 0);
1066 radeon_ring_write(rdev, 0);
1067 radeon_ring_unlock_commit(rdev);
1068
1069 cayman_cp_enable(rdev, true);
1070
1071 r = radeon_ring_lock(rdev, cayman_default_size + 19);
1072 if (r) {
1073 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1074 return r;
1075 }
1076
1077 /* setup clear context state */
1078 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1079 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1080
1081 for (i = 0; i < cayman_default_size; i++)
1082 radeon_ring_write(rdev, cayman_default_state[i]);
1083
1084 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1085 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1086
1087 /* set clear context state */
1088 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1089 radeon_ring_write(rdev, 0);
1090
1091 /* SQ_VTX_BASE_VTX_LOC */
1092 radeon_ring_write(rdev, 0xc0026f00);
1093 radeon_ring_write(rdev, 0x00000000);
1094 radeon_ring_write(rdev, 0x00000000);
1095 radeon_ring_write(rdev, 0x00000000);
1096
1097 /* Clear consts */
1098 radeon_ring_write(rdev, 0xc0036f00);
1099 radeon_ring_write(rdev, 0x00000bc4);
1100 radeon_ring_write(rdev, 0xffffffff);
1101 radeon_ring_write(rdev, 0xffffffff);
1102 radeon_ring_write(rdev, 0xffffffff);
1103
1104 radeon_ring_write(rdev, 0xc0026900);
1105 radeon_ring_write(rdev, 0x00000316);
1106 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1107 radeon_ring_write(rdev, 0x00000010); /* */
1108
1109 radeon_ring_unlock_commit(rdev);
1110
1111 /* XXX init other rings */
1112
1113 return 0;
1114}
1115
1116static void cayman_cp_fini(struct radeon_device *rdev)
1117{
1118 cayman_cp_enable(rdev, false);
1119 radeon_ring_fini(rdev);
1120}
1121
1122int cayman_cp_resume(struct radeon_device *rdev)
1123{
1124 u32 tmp;
1125 u32 rb_bufsz;
1126 int r;
1127
1128 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1129 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1130 SOFT_RESET_PA |
1131 SOFT_RESET_SH |
1132 SOFT_RESET_VGT |
1133 SOFT_RESET_SPI |
1134 SOFT_RESET_SX));
1135 RREG32(GRBM_SOFT_RESET);
1136 mdelay(15);
1137 WREG32(GRBM_SOFT_RESET, 0);
1138 RREG32(GRBM_SOFT_RESET);
1139
1140 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1141
1142 /* Set the write pointer delay */
1143 WREG32(CP_RB_WPTR_DELAY, 0);
1144
1145 WREG32(CP_DEBUG, (1 << 27));
1146
1147 /* ring 0 - compute and gfx */
1148 /* Set ring buffer size */
1149 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1150 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1151#ifdef __BIG_ENDIAN
1152 tmp |= BUF_SWAP_32BIT;
1153#endif
1154 WREG32(CP_RB0_CNTL, tmp);
1155
1156 /* Initialize the ring buffer's read and write pointers */
1157 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1158 rdev->cp.wptr = 0;
1159 WREG32(CP_RB0_WPTR, rdev->cp.wptr);
1160
1161 /* set the wb address wether it's enabled or not */
1162 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1163 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1164 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1165
1166 if (rdev->wb.enabled)
1167 WREG32(SCRATCH_UMSK, 0xff);
1168 else {
1169 tmp |= RB_NO_UPDATE;
1170 WREG32(SCRATCH_UMSK, 0);
1171 }
1172
1173 mdelay(1);
1174 WREG32(CP_RB0_CNTL, tmp);
1175
1176 WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);
1177
1178 rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1179
1180 /* ring1 - compute only */
1181 /* Set ring buffer size */
1182 rb_bufsz = drm_order(rdev->cp1.ring_size / 8);
1183 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1184#ifdef __BIG_ENDIAN
1185 tmp |= BUF_SWAP_32BIT;
1186#endif
1187 WREG32(CP_RB1_CNTL, tmp);
1188
1189 /* Initialize the ring buffer's read and write pointers */
1190 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1191 rdev->cp1.wptr = 0;
1192 WREG32(CP_RB1_WPTR, rdev->cp1.wptr);
1193
1194 /* set the wb address wether it's enabled or not */
1195 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1196 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1197
1198 mdelay(1);
1199 WREG32(CP_RB1_CNTL, tmp);
1200
1201 WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);
1202
1203 rdev->cp1.rptr = RREG32(CP_RB1_RPTR);
1204
1205 /* ring2 - compute only */
1206 /* Set ring buffer size */
1207 rb_bufsz = drm_order(rdev->cp2.ring_size / 8);
1208 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1209#ifdef __BIG_ENDIAN
1210 tmp |= BUF_SWAP_32BIT;
1211#endif
1212 WREG32(CP_RB2_CNTL, tmp);
1213
1214 /* Initialize the ring buffer's read and write pointers */
1215 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1216 rdev->cp2.wptr = 0;
1217 WREG32(CP_RB2_WPTR, rdev->cp2.wptr);
1218
1219 /* set the wb address wether it's enabled or not */
1220 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1221 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1222
1223 mdelay(1);
1224 WREG32(CP_RB2_CNTL, tmp);
1225
1226 WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);
1227
1228 rdev->cp2.rptr = RREG32(CP_RB2_RPTR);
1229
1230 /* start the rings */
1231 cayman_cp_start(rdev);
1232 rdev->cp.ready = true;
1233 rdev->cp1.ready = true;
1234 rdev->cp2.ready = true;
1235 /* this only test cp0 */
1236 r = radeon_ring_test(rdev);
1237 if (r) {
1238 rdev->cp.ready = false;
1239 rdev->cp1.ready = false;
1240 rdev->cp2.ready = false;
1241 return r;
1242 }
1243
1244 return 0;
1245}
1246
1247bool cayman_gpu_is_lockup(struct radeon_device *rdev)
1248{
1249 u32 srbm_status;
1250 u32 grbm_status;
1251 u32 grbm_status_se0, grbm_status_se1;
1252 struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup;
1253 int r;
1254
1255 srbm_status = RREG32(SRBM_STATUS);
1256 grbm_status = RREG32(GRBM_STATUS);
1257 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1258 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1259 if (!(grbm_status & GUI_ACTIVE)) {
1260 r100_gpu_lockup_update(lockup, &rdev->cp);
1261 return false;
1262 }
1263 /* force CP activities */
1264 r = radeon_ring_lock(rdev, 2);
1265 if (!r) {
1266 /* PACKET2 NOP */
1267 radeon_ring_write(rdev, 0x80000000);
1268 radeon_ring_write(rdev, 0x80000000);
1269 radeon_ring_unlock_commit(rdev);
1270 }
1271 /* XXX deal with CP0,1,2 */
1272 rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1273 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1274}
1275
1276static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1277{
1278 struct evergreen_mc_save save;
1279 u32 grbm_reset = 0;
1280
1281 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1282 return 0;
1283
1284 dev_info(rdev->dev, "GPU softreset \n");
1285 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1286 RREG32(GRBM_STATUS));
1287 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1288 RREG32(GRBM_STATUS_SE0));
1289 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1290 RREG32(GRBM_STATUS_SE1));
1291 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1292 RREG32(SRBM_STATUS));
1293 evergreen_mc_stop(rdev, &save);
1294 if (evergreen_mc_wait_for_idle(rdev)) {
1295 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1296 }
1297 /* Disable CP parsing/prefetching */
1298 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1299
1300 /* reset all the gfx blocks */
1301 grbm_reset = (SOFT_RESET_CP |
1302 SOFT_RESET_CB |
1303 SOFT_RESET_DB |
1304 SOFT_RESET_GDS |
1305 SOFT_RESET_PA |
1306 SOFT_RESET_SC |
1307 SOFT_RESET_SPI |
1308 SOFT_RESET_SH |
1309 SOFT_RESET_SX |
1310 SOFT_RESET_TC |
1311 SOFT_RESET_TA |
1312 SOFT_RESET_VGT |
1313 SOFT_RESET_IA);
1314
1315 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1316 WREG32(GRBM_SOFT_RESET, grbm_reset);
1317 (void)RREG32(GRBM_SOFT_RESET);
1318 udelay(50);
1319 WREG32(GRBM_SOFT_RESET, 0);
1320 (void)RREG32(GRBM_SOFT_RESET);
1321 /* Wait a little for things to settle down */
1322 udelay(50);
1323 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1324 RREG32(GRBM_STATUS));
1325 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1326 RREG32(GRBM_STATUS_SE0));
1327 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1328 RREG32(GRBM_STATUS_SE1));
1329 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1330 RREG32(SRBM_STATUS));
1331 evergreen_mc_resume(rdev, &save);
1332 return 0;
1333}
1334
1335int cayman_asic_reset(struct radeon_device *rdev)
1336{
1337 return cayman_gpu_soft_reset(rdev);
1338}
1339
1340static int cayman_startup(struct radeon_device *rdev)
1341{
1342 int r;
1343
1344 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1345 r = ni_init_microcode(rdev);
1346 if (r) {
1347 DRM_ERROR("Failed to load firmware!\n");
1348 return r;
1349 }
1350 }
1351 r = ni_mc_load_microcode(rdev);
1352 if (r) {
1353 DRM_ERROR("Failed to load MC firmware!\n");
1354 return r;
1355 }
1356
1357 evergreen_mc_program(rdev);
1358 r = cayman_pcie_gart_enable(rdev);
1359 if (r)
1360 return r;
1361 cayman_gpu_init(rdev);
1362
1363 r = evergreen_blit_init(rdev);
1364 if (r) {
1365 evergreen_blit_fini(rdev);
1366 rdev->asic->copy = NULL;
1367 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1368 }
1369
1370 /* allocate wb buffer */
1371 r = radeon_wb_init(rdev);
1372 if (r)
1373 return r;
1374
1375 /* Enable IRQ */
1376 r = r600_irq_init(rdev);
1377 if (r) {
1378 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1379 radeon_irq_kms_fini(rdev);
1380 return r;
1381 }
1382 evergreen_irq_set(rdev);
1383
1384 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1385 if (r)
1386 return r;
1387 r = cayman_cp_load_microcode(rdev);
1388 if (r)
1389 return r;
1390 r = cayman_cp_resume(rdev);
1391 if (r)
1392 return r;
1393
1394 return 0;
1395}
1396
1397int cayman_resume(struct radeon_device *rdev)
1398{
1399 int r;
1400
1401 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1402 * posting will perform necessary task to bring back GPU into good
1403 * shape.
1404 */
1405 /* post card */
1406 atom_asic_init(rdev->mode_info.atom_context);
1407
1408 r = cayman_startup(rdev);
1409 if (r) {
1410 DRM_ERROR("cayman startup failed on resume\n");
1411 return r;
1412 }
1413
1414 r = r600_ib_test(rdev);
1415 if (r) {
1416 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1417 return r;
1418 }
1419
1420 return r;
1421
1422}
1423
1424int cayman_suspend(struct radeon_device *rdev)
1425{
1426 int r;
1427
1428 /* FIXME: we should wait for ring to be empty */
1429 cayman_cp_enable(rdev, false);
1430 rdev->cp.ready = false;
1431 evergreen_irq_suspend(rdev);
1432 radeon_wb_disable(rdev);
1433 cayman_pcie_gart_disable(rdev);
1434
1435 /* unpin shaders bo */
1436 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1437 if (likely(r == 0)) {
1438 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1439 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1440 }
1441
1442 return 0;
1443}
1444
1445/* Plan is to move initialization in that function and use
1446 * helper function so that radeon_device_init pretty much
1447 * do nothing more than calling asic specific function. This
1448 * should also allow to remove a bunch of callback function
1449 * like vram_info.
1450 */
1451int cayman_init(struct radeon_device *rdev)
1452{
1453 int r;
1454
1455 /* This don't do much */
1456 r = radeon_gem_init(rdev);
1457 if (r)
1458 return r;
1459 /* Read BIOS */
1460 if (!radeon_get_bios(rdev)) {
1461 if (ASIC_IS_AVIVO(rdev))
1462 return -EINVAL;
1463 }
1464 /* Must be an ATOMBIOS */
1465 if (!rdev->is_atom_bios) {
1466 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1467 return -EINVAL;
1468 }
1469 r = radeon_atombios_init(rdev);
1470 if (r)
1471 return r;
1472
1473 /* Post card if necessary */
1474 if (!radeon_card_posted(rdev)) {
1475 if (!rdev->bios) {
1476 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1477 return -EINVAL;
1478 }
1479 DRM_INFO("GPU not posted. posting now...\n");
1480 atom_asic_init(rdev->mode_info.atom_context);
1481 }
1482 /* Initialize scratch registers */
1483 r600_scratch_init(rdev);
1484 /* Initialize surface registers */
1485 radeon_surface_init(rdev);
1486 /* Initialize clocks */
1487 radeon_get_clock_info(rdev->ddev);
1488 /* Fence driver */
1489 r = radeon_fence_driver_init(rdev);
1490 if (r)
1491 return r;
1492 /* initialize memory controller */
1493 r = evergreen_mc_init(rdev);
1494 if (r)
1495 return r;
1496 /* Memory manager */
1497 r = radeon_bo_init(rdev);
1498 if (r)
1499 return r;
1500
1501 r = radeon_irq_kms_init(rdev);
1502 if (r)
1503 return r;
1504
1505 rdev->cp.ring_obj = NULL;
1506 r600_ring_init(rdev, 1024 * 1024);
1507
1508 rdev->ih.ring_obj = NULL;
1509 r600_ih_ring_init(rdev, 64 * 1024);
1510
1511 r = r600_pcie_gart_init(rdev);
1512 if (r)
1513 return r;
1514
1515 rdev->accel_working = true;
1516 r = cayman_startup(rdev);
1517 if (r) {
1518 dev_err(rdev->dev, "disabling GPU acceleration\n");
1519 cayman_cp_fini(rdev);
1520 r600_irq_fini(rdev);
1521 radeon_wb_fini(rdev);
1522 radeon_irq_kms_fini(rdev);
1523 cayman_pcie_gart_fini(rdev);
1524 rdev->accel_working = false;
1525 }
1526 if (rdev->accel_working) {
1527 r = radeon_ib_pool_init(rdev);
1528 if (r) {
1529 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
1530 rdev->accel_working = false;
1531 }
1532 r = r600_ib_test(rdev);
1533 if (r) {
1534 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1535 rdev->accel_working = false;
1536 }
1537 }
1538
1539 /* Don't start up if the MC ucode is missing.
1540 * The default clocks and voltages before the MC ucode
1541 * is loaded are not suffient for advanced operations.
1542 */
1543 if (!rdev->mc_fw) {
1544 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1545 return -EINVAL;
1546 }
1547
1548 return 0;
1549}
1550
1551void cayman_fini(struct radeon_device *rdev)
1552{
1553 evergreen_blit_fini(rdev);
1554 cayman_cp_fini(rdev);
1555 r600_irq_fini(rdev);
1556 radeon_wb_fini(rdev);
1557 radeon_ib_pool_fini(rdev);
1558 radeon_irq_kms_fini(rdev);
1559 cayman_pcie_gart_fini(rdev);
1560 radeon_gem_fini(rdev);
1561 radeon_fence_driver_fini(rdev);
1562 radeon_bo_fini(rdev);
1563 radeon_atombios_fini(rdev);
1564 kfree(rdev->bios);
1565 rdev->bios = NULL;
1566}
1567
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include "drmP.h"
29#include "radeon.h"
30#include "radeon_asic.h"
31#include "radeon_drm.h"
32#include "nid.h"
33#include "atom.h"
34#include "ni_reg.h"
35#include "cayman_blit_shaders.h"
36
37extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
38extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
39extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
40extern void evergreen_mc_program(struct radeon_device *rdev);
41extern void evergreen_irq_suspend(struct radeon_device *rdev);
42extern int evergreen_mc_init(struct radeon_device *rdev);
43extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
44extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
45extern void si_rlc_fini(struct radeon_device *rdev);
46extern int si_rlc_init(struct radeon_device *rdev);
47
48#define EVERGREEN_PFP_UCODE_SIZE 1120
49#define EVERGREEN_PM4_UCODE_SIZE 1376
50#define EVERGREEN_RLC_UCODE_SIZE 768
51#define BTC_MC_UCODE_SIZE 6024
52
53#define CAYMAN_PFP_UCODE_SIZE 2176
54#define CAYMAN_PM4_UCODE_SIZE 2176
55#define CAYMAN_RLC_UCODE_SIZE 1024
56#define CAYMAN_MC_UCODE_SIZE 6037
57
58#define ARUBA_RLC_UCODE_SIZE 1536
59
60/* Firmware Names */
61MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
62MODULE_FIRMWARE("radeon/BARTS_me.bin");
63MODULE_FIRMWARE("radeon/BARTS_mc.bin");
64MODULE_FIRMWARE("radeon/BTC_rlc.bin");
65MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
66MODULE_FIRMWARE("radeon/TURKS_me.bin");
67MODULE_FIRMWARE("radeon/TURKS_mc.bin");
68MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
69MODULE_FIRMWARE("radeon/CAICOS_me.bin");
70MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
71MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
72MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
73MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
74MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
75MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
76MODULE_FIRMWARE("radeon/ARUBA_me.bin");
77MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
78
79#define BTC_IO_MC_REGS_SIZE 29
80
81static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
82 {0x00000077, 0xff010100},
83 {0x00000078, 0x00000000},
84 {0x00000079, 0x00001434},
85 {0x0000007a, 0xcc08ec08},
86 {0x0000007b, 0x00040000},
87 {0x0000007c, 0x000080c0},
88 {0x0000007d, 0x09000000},
89 {0x0000007e, 0x00210404},
90 {0x00000081, 0x08a8e800},
91 {0x00000082, 0x00030444},
92 {0x00000083, 0x00000000},
93 {0x00000085, 0x00000001},
94 {0x00000086, 0x00000002},
95 {0x00000087, 0x48490000},
96 {0x00000088, 0x20244647},
97 {0x00000089, 0x00000005},
98 {0x0000008b, 0x66030000},
99 {0x0000008c, 0x00006603},
100 {0x0000008d, 0x00000100},
101 {0x0000008f, 0x00001c0a},
102 {0x00000090, 0xff000001},
103 {0x00000094, 0x00101101},
104 {0x00000095, 0x00000fff},
105 {0x00000096, 0x00116fff},
106 {0x00000097, 0x60010000},
107 {0x00000098, 0x10010000},
108 {0x00000099, 0x00006000},
109 {0x0000009a, 0x00001000},
110 {0x0000009f, 0x00946a00}
111};
112
113static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
114 {0x00000077, 0xff010100},
115 {0x00000078, 0x00000000},
116 {0x00000079, 0x00001434},
117 {0x0000007a, 0xcc08ec08},
118 {0x0000007b, 0x00040000},
119 {0x0000007c, 0x000080c0},
120 {0x0000007d, 0x09000000},
121 {0x0000007e, 0x00210404},
122 {0x00000081, 0x08a8e800},
123 {0x00000082, 0x00030444},
124 {0x00000083, 0x00000000},
125 {0x00000085, 0x00000001},
126 {0x00000086, 0x00000002},
127 {0x00000087, 0x48490000},
128 {0x00000088, 0x20244647},
129 {0x00000089, 0x00000005},
130 {0x0000008b, 0x66030000},
131 {0x0000008c, 0x00006603},
132 {0x0000008d, 0x00000100},
133 {0x0000008f, 0x00001c0a},
134 {0x00000090, 0xff000001},
135 {0x00000094, 0x00101101},
136 {0x00000095, 0x00000fff},
137 {0x00000096, 0x00116fff},
138 {0x00000097, 0x60010000},
139 {0x00000098, 0x10010000},
140 {0x00000099, 0x00006000},
141 {0x0000009a, 0x00001000},
142 {0x0000009f, 0x00936a00}
143};
144
145static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
146 {0x00000077, 0xff010100},
147 {0x00000078, 0x00000000},
148 {0x00000079, 0x00001434},
149 {0x0000007a, 0xcc08ec08},
150 {0x0000007b, 0x00040000},
151 {0x0000007c, 0x000080c0},
152 {0x0000007d, 0x09000000},
153 {0x0000007e, 0x00210404},
154 {0x00000081, 0x08a8e800},
155 {0x00000082, 0x00030444},
156 {0x00000083, 0x00000000},
157 {0x00000085, 0x00000001},
158 {0x00000086, 0x00000002},
159 {0x00000087, 0x48490000},
160 {0x00000088, 0x20244647},
161 {0x00000089, 0x00000005},
162 {0x0000008b, 0x66030000},
163 {0x0000008c, 0x00006603},
164 {0x0000008d, 0x00000100},
165 {0x0000008f, 0x00001c0a},
166 {0x00000090, 0xff000001},
167 {0x00000094, 0x00101101},
168 {0x00000095, 0x00000fff},
169 {0x00000096, 0x00116fff},
170 {0x00000097, 0x60010000},
171 {0x00000098, 0x10010000},
172 {0x00000099, 0x00006000},
173 {0x0000009a, 0x00001000},
174 {0x0000009f, 0x00916a00}
175};
176
177static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
178 {0x00000077, 0xff010100},
179 {0x00000078, 0x00000000},
180 {0x00000079, 0x00001434},
181 {0x0000007a, 0xcc08ec08},
182 {0x0000007b, 0x00040000},
183 {0x0000007c, 0x000080c0},
184 {0x0000007d, 0x09000000},
185 {0x0000007e, 0x00210404},
186 {0x00000081, 0x08a8e800},
187 {0x00000082, 0x00030444},
188 {0x00000083, 0x00000000},
189 {0x00000085, 0x00000001},
190 {0x00000086, 0x00000002},
191 {0x00000087, 0x48490000},
192 {0x00000088, 0x20244647},
193 {0x00000089, 0x00000005},
194 {0x0000008b, 0x66030000},
195 {0x0000008c, 0x00006603},
196 {0x0000008d, 0x00000100},
197 {0x0000008f, 0x00001c0a},
198 {0x00000090, 0xff000001},
199 {0x00000094, 0x00101101},
200 {0x00000095, 0x00000fff},
201 {0x00000096, 0x00116fff},
202 {0x00000097, 0x60010000},
203 {0x00000098, 0x10010000},
204 {0x00000099, 0x00006000},
205 {0x0000009a, 0x00001000},
206 {0x0000009f, 0x00976b00}
207};
208
209int ni_mc_load_microcode(struct radeon_device *rdev)
210{
211 const __be32 *fw_data;
212 u32 mem_type, running, blackout = 0;
213 u32 *io_mc_regs;
214 int i, ucode_size, regs_size;
215
216 if (!rdev->mc_fw)
217 return -EINVAL;
218
219 switch (rdev->family) {
220 case CHIP_BARTS:
221 io_mc_regs = (u32 *)&barts_io_mc_regs;
222 ucode_size = BTC_MC_UCODE_SIZE;
223 regs_size = BTC_IO_MC_REGS_SIZE;
224 break;
225 case CHIP_TURKS:
226 io_mc_regs = (u32 *)&turks_io_mc_regs;
227 ucode_size = BTC_MC_UCODE_SIZE;
228 regs_size = BTC_IO_MC_REGS_SIZE;
229 break;
230 case CHIP_CAICOS:
231 default:
232 io_mc_regs = (u32 *)&caicos_io_mc_regs;
233 ucode_size = BTC_MC_UCODE_SIZE;
234 regs_size = BTC_IO_MC_REGS_SIZE;
235 break;
236 case CHIP_CAYMAN:
237 io_mc_regs = (u32 *)&cayman_io_mc_regs;
238 ucode_size = CAYMAN_MC_UCODE_SIZE;
239 regs_size = BTC_IO_MC_REGS_SIZE;
240 break;
241 }
242
243 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
244 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
245
246 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
247 if (running) {
248 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
249 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
250 }
251
252 /* reset the engine and set to writable */
253 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
254 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
255
256 /* load mc io regs */
257 for (i = 0; i < regs_size; i++) {
258 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
259 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
260 }
261 /* load the MC ucode */
262 fw_data = (const __be32 *)rdev->mc_fw->data;
263 for (i = 0; i < ucode_size; i++)
264 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
265
266 /* put the engine back into the active state */
267 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
268 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
269 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
270
271 /* wait for training to complete */
272 for (i = 0; i < rdev->usec_timeout; i++) {
273 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
274 break;
275 udelay(1);
276 }
277
278 if (running)
279 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
280 }
281
282 return 0;
283}
284
285int ni_init_microcode(struct radeon_device *rdev)
286{
287 struct platform_device *pdev;
288 const char *chip_name;
289 const char *rlc_chip_name;
290 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
291 char fw_name[30];
292 int err;
293
294 DRM_DEBUG("\n");
295
296 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
297 err = IS_ERR(pdev);
298 if (err) {
299 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
300 return -EINVAL;
301 }
302
303 switch (rdev->family) {
304 case CHIP_BARTS:
305 chip_name = "BARTS";
306 rlc_chip_name = "BTC";
307 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
308 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
309 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
310 mc_req_size = BTC_MC_UCODE_SIZE * 4;
311 break;
312 case CHIP_TURKS:
313 chip_name = "TURKS";
314 rlc_chip_name = "BTC";
315 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
316 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
317 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
318 mc_req_size = BTC_MC_UCODE_SIZE * 4;
319 break;
320 case CHIP_CAICOS:
321 chip_name = "CAICOS";
322 rlc_chip_name = "BTC";
323 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
324 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
325 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
326 mc_req_size = BTC_MC_UCODE_SIZE * 4;
327 break;
328 case CHIP_CAYMAN:
329 chip_name = "CAYMAN";
330 rlc_chip_name = "CAYMAN";
331 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
332 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
333 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
334 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
335 break;
336 case CHIP_ARUBA:
337 chip_name = "ARUBA";
338 rlc_chip_name = "ARUBA";
339 /* pfp/me same size as CAYMAN */
340 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
341 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
342 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
343 mc_req_size = 0;
344 break;
345 default: BUG();
346 }
347
348 DRM_INFO("Loading %s Microcode\n", chip_name);
349
350 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
351 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
352 if (err)
353 goto out;
354 if (rdev->pfp_fw->size != pfp_req_size) {
355 printk(KERN_ERR
356 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
357 rdev->pfp_fw->size, fw_name);
358 err = -EINVAL;
359 goto out;
360 }
361
362 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
363 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
364 if (err)
365 goto out;
366 if (rdev->me_fw->size != me_req_size) {
367 printk(KERN_ERR
368 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
369 rdev->me_fw->size, fw_name);
370 err = -EINVAL;
371 }
372
373 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
374 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
375 if (err)
376 goto out;
377 if (rdev->rlc_fw->size != rlc_req_size) {
378 printk(KERN_ERR
379 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
380 rdev->rlc_fw->size, fw_name);
381 err = -EINVAL;
382 }
383
384 /* no MC ucode on TN */
385 if (!(rdev->flags & RADEON_IS_IGP)) {
386 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
387 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
388 if (err)
389 goto out;
390 if (rdev->mc_fw->size != mc_req_size) {
391 printk(KERN_ERR
392 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
393 rdev->mc_fw->size, fw_name);
394 err = -EINVAL;
395 }
396 }
397out:
398 platform_device_unregister(pdev);
399
400 if (err) {
401 if (err != -EINVAL)
402 printk(KERN_ERR
403 "ni_cp: Failed to load firmware \"%s\"\n",
404 fw_name);
405 release_firmware(rdev->pfp_fw);
406 rdev->pfp_fw = NULL;
407 release_firmware(rdev->me_fw);
408 rdev->me_fw = NULL;
409 release_firmware(rdev->rlc_fw);
410 rdev->rlc_fw = NULL;
411 release_firmware(rdev->mc_fw);
412 rdev->mc_fw = NULL;
413 }
414 return err;
415}
416
417/*
418 * Core functions
419 */
420static void cayman_gpu_init(struct radeon_device *rdev)
421{
422 u32 gb_addr_config = 0;
423 u32 mc_shared_chmap, mc_arb_ramcfg;
424 u32 cgts_tcc_disable;
425 u32 sx_debug_1;
426 u32 smx_dc_ctl0;
427 u32 cgts_sm_ctrl_reg;
428 u32 hdp_host_path_cntl;
429 u32 tmp;
430 u32 disabled_rb_mask;
431 int i, j;
432
433 switch (rdev->family) {
434 case CHIP_CAYMAN:
435 rdev->config.cayman.max_shader_engines = 2;
436 rdev->config.cayman.max_pipes_per_simd = 4;
437 rdev->config.cayman.max_tile_pipes = 8;
438 rdev->config.cayman.max_simds_per_se = 12;
439 rdev->config.cayman.max_backends_per_se = 4;
440 rdev->config.cayman.max_texture_channel_caches = 8;
441 rdev->config.cayman.max_gprs = 256;
442 rdev->config.cayman.max_threads = 256;
443 rdev->config.cayman.max_gs_threads = 32;
444 rdev->config.cayman.max_stack_entries = 512;
445 rdev->config.cayman.sx_num_of_sets = 8;
446 rdev->config.cayman.sx_max_export_size = 256;
447 rdev->config.cayman.sx_max_export_pos_size = 64;
448 rdev->config.cayman.sx_max_export_smx_size = 192;
449 rdev->config.cayman.max_hw_contexts = 8;
450 rdev->config.cayman.sq_num_cf_insts = 2;
451
452 rdev->config.cayman.sc_prim_fifo_size = 0x100;
453 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
454 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
455 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
456 break;
457 case CHIP_ARUBA:
458 default:
459 rdev->config.cayman.max_shader_engines = 1;
460 rdev->config.cayman.max_pipes_per_simd = 4;
461 rdev->config.cayman.max_tile_pipes = 2;
462 if ((rdev->pdev->device == 0x9900) ||
463 (rdev->pdev->device == 0x9901) ||
464 (rdev->pdev->device == 0x9905) ||
465 (rdev->pdev->device == 0x9906) ||
466 (rdev->pdev->device == 0x9907) ||
467 (rdev->pdev->device == 0x9908) ||
468 (rdev->pdev->device == 0x9909) ||
469 (rdev->pdev->device == 0x9910) ||
470 (rdev->pdev->device == 0x9917)) {
471 rdev->config.cayman.max_simds_per_se = 6;
472 rdev->config.cayman.max_backends_per_se = 2;
473 } else if ((rdev->pdev->device == 0x9903) ||
474 (rdev->pdev->device == 0x9904) ||
475 (rdev->pdev->device == 0x990A) ||
476 (rdev->pdev->device == 0x9913) ||
477 (rdev->pdev->device == 0x9918)) {
478 rdev->config.cayman.max_simds_per_se = 4;
479 rdev->config.cayman.max_backends_per_se = 2;
480 } else if ((rdev->pdev->device == 0x9919) ||
481 (rdev->pdev->device == 0x9990) ||
482 (rdev->pdev->device == 0x9991) ||
483 (rdev->pdev->device == 0x9994) ||
484 (rdev->pdev->device == 0x99A0)) {
485 rdev->config.cayman.max_simds_per_se = 3;
486 rdev->config.cayman.max_backends_per_se = 1;
487 } else {
488 rdev->config.cayman.max_simds_per_se = 2;
489 rdev->config.cayman.max_backends_per_se = 1;
490 }
491 rdev->config.cayman.max_texture_channel_caches = 2;
492 rdev->config.cayman.max_gprs = 256;
493 rdev->config.cayman.max_threads = 256;
494 rdev->config.cayman.max_gs_threads = 32;
495 rdev->config.cayman.max_stack_entries = 512;
496 rdev->config.cayman.sx_num_of_sets = 8;
497 rdev->config.cayman.sx_max_export_size = 256;
498 rdev->config.cayman.sx_max_export_pos_size = 64;
499 rdev->config.cayman.sx_max_export_smx_size = 192;
500 rdev->config.cayman.max_hw_contexts = 8;
501 rdev->config.cayman.sq_num_cf_insts = 2;
502
503 rdev->config.cayman.sc_prim_fifo_size = 0x40;
504 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
505 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
506 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
507 break;
508 }
509
510 /* Initialize HDP */
511 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
512 WREG32((0x2c14 + j), 0x00000000);
513 WREG32((0x2c18 + j), 0x00000000);
514 WREG32((0x2c1c + j), 0x00000000);
515 WREG32((0x2c20 + j), 0x00000000);
516 WREG32((0x2c24 + j), 0x00000000);
517 }
518
519 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
520
521 evergreen_fix_pci_max_read_req_size(rdev);
522
523 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
524 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
525
526 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
527 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
528 if (rdev->config.cayman.mem_row_size_in_kb > 4)
529 rdev->config.cayman.mem_row_size_in_kb = 4;
530 /* XXX use MC settings? */
531 rdev->config.cayman.shader_engine_tile_size = 32;
532 rdev->config.cayman.num_gpus = 1;
533 rdev->config.cayman.multi_gpu_tile_size = 64;
534
535 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
536 rdev->config.cayman.num_tile_pipes = (1 << tmp);
537 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
538 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
539 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
540 rdev->config.cayman.num_shader_engines = tmp + 1;
541 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
542 rdev->config.cayman.num_gpus = tmp + 1;
543 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
544 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
545 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
546 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
547
548
549 /* setup tiling info dword. gb_addr_config is not adequate since it does
550 * not have bank info, so create a custom tiling dword.
551 * bits 3:0 num_pipes
552 * bits 7:4 num_banks
553 * bits 11:8 group_size
554 * bits 15:12 row_size
555 */
556 rdev->config.cayman.tile_config = 0;
557 switch (rdev->config.cayman.num_tile_pipes) {
558 case 1:
559 default:
560 rdev->config.cayman.tile_config |= (0 << 0);
561 break;
562 case 2:
563 rdev->config.cayman.tile_config |= (1 << 0);
564 break;
565 case 4:
566 rdev->config.cayman.tile_config |= (2 << 0);
567 break;
568 case 8:
569 rdev->config.cayman.tile_config |= (3 << 0);
570 break;
571 }
572
573 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
574 if (rdev->flags & RADEON_IS_IGP)
575 rdev->config.cayman.tile_config |= 1 << 4;
576 else {
577 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
578 case 0: /* four banks */
579 rdev->config.cayman.tile_config |= 0 << 4;
580 break;
581 case 1: /* eight banks */
582 rdev->config.cayman.tile_config |= 1 << 4;
583 break;
584 case 2: /* sixteen banks */
585 default:
586 rdev->config.cayman.tile_config |= 2 << 4;
587 break;
588 }
589 }
590 rdev->config.cayman.tile_config |=
591 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
592 rdev->config.cayman.tile_config |=
593 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
594
595 tmp = 0;
596 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
597 u32 rb_disable_bitmap;
598
599 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
600 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
601 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
602 tmp <<= 4;
603 tmp |= rb_disable_bitmap;
604 }
605 /* enabled rb are just the one not disabled :) */
606 disabled_rb_mask = tmp;
607
608 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
609 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
610
611 WREG32(GB_ADDR_CONFIG, gb_addr_config);
612 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
613 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
614
615 tmp = gb_addr_config & NUM_PIPES_MASK;
616 tmp = r6xx_remap_render_backend(rdev, tmp,
617 rdev->config.cayman.max_backends_per_se *
618 rdev->config.cayman.max_shader_engines,
619 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
620 WREG32(GB_BACKEND_MAP, tmp);
621
622 cgts_tcc_disable = 0xffff0000;
623 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
624 cgts_tcc_disable &= ~(1 << (16 + i));
625 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
626 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
627 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
628 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
629
630 /* reprogram the shader complex */
631 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
632 for (i = 0; i < 16; i++)
633 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
634 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
635
636 /* set HW defaults for 3D engine */
637 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
638
639 sx_debug_1 = RREG32(SX_DEBUG_1);
640 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
641 WREG32(SX_DEBUG_1, sx_debug_1);
642
643 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
644 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
645 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
646 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
647
648 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
649
650 /* need to be explicitly zero-ed */
651 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
652 WREG32(SQ_LSTMP_RING_BASE, 0);
653 WREG32(SQ_HSTMP_RING_BASE, 0);
654 WREG32(SQ_ESTMP_RING_BASE, 0);
655 WREG32(SQ_GSTMP_RING_BASE, 0);
656 WREG32(SQ_VSTMP_RING_BASE, 0);
657 WREG32(SQ_PSTMP_RING_BASE, 0);
658
659 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
660
661 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
662 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
663 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
664
665 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
666 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
667 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
668
669
670 WREG32(VGT_NUM_INSTANCES, 1);
671
672 WREG32(CP_PERFMON_CNTL, 0);
673
674 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
675 FETCH_FIFO_HIWATER(0x4) |
676 DONE_FIFO_HIWATER(0xe0) |
677 ALU_UPDATE_FIFO_HIWATER(0x8)));
678
679 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
680 WREG32(SQ_CONFIG, (VC_ENABLE |
681 EXPORT_SRC_C |
682 GFX_PRIO(0) |
683 CS1_PRIO(0) |
684 CS2_PRIO(1)));
685 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
686
687 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
688 FORCE_EOV_MAX_REZ_CNT(255)));
689
690 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
691 AUTO_INVLD_EN(ES_AND_GS_AUTO));
692
693 WREG32(VGT_GS_VERTEX_REUSE, 16);
694 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
695
696 WREG32(CB_PERF_CTR0_SEL_0, 0);
697 WREG32(CB_PERF_CTR0_SEL_1, 0);
698 WREG32(CB_PERF_CTR1_SEL_0, 0);
699 WREG32(CB_PERF_CTR1_SEL_1, 0);
700 WREG32(CB_PERF_CTR2_SEL_0, 0);
701 WREG32(CB_PERF_CTR2_SEL_1, 0);
702 WREG32(CB_PERF_CTR3_SEL_0, 0);
703 WREG32(CB_PERF_CTR3_SEL_1, 0);
704
705 tmp = RREG32(HDP_MISC_CNTL);
706 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
707 WREG32(HDP_MISC_CNTL, tmp);
708
709 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
710 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
711
712 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
713
714 udelay(50);
715}
716
717/*
718 * GART
719 */
720void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
721{
722 /* flush hdp cache */
723 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
724
725 /* bits 0-7 are the VM contexts0-7 */
726 WREG32(VM_INVALIDATE_REQUEST, 1);
727}
728
729int cayman_pcie_gart_enable(struct radeon_device *rdev)
730{
731 int i, r;
732
733 if (rdev->gart.robj == NULL) {
734 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
735 return -EINVAL;
736 }
737 r = radeon_gart_table_vram_pin(rdev);
738 if (r)
739 return r;
740 radeon_gart_restore(rdev);
741 /* Setup TLB control */
742 WREG32(MC_VM_MX_L1_TLB_CNTL,
743 (0xA << 7) |
744 ENABLE_L1_TLB |
745 ENABLE_L1_FRAGMENT_PROCESSING |
746 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
747 ENABLE_ADVANCED_DRIVER_MODEL |
748 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
749 /* Setup L2 cache */
750 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
751 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
752 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
753 EFFECTIVE_L2_QUEUE_SIZE(7) |
754 CONTEXT1_IDENTITY_ACCESS_MODE(1));
755 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
756 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
757 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
758 /* setup context0 */
759 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
760 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
761 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
762 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
763 (u32)(rdev->dummy_page.addr >> 12));
764 WREG32(VM_CONTEXT0_CNTL2, 0);
765 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
766 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
767
768 WREG32(0x15D4, 0);
769 WREG32(0x15D8, 0);
770 WREG32(0x15DC, 0);
771
772 /* empty context1-7 */
773 for (i = 1; i < 8; i++) {
774 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
775 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
776 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
777 rdev->gart.table_addr >> 12);
778 }
779
780 /* enable context1-7 */
781 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
782 (u32)(rdev->dummy_page.addr >> 12));
783 WREG32(VM_CONTEXT1_CNTL2, 0);
784 WREG32(VM_CONTEXT1_CNTL, 0);
785 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
786 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
787
788 cayman_pcie_gart_tlb_flush(rdev);
789 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
790 (unsigned)(rdev->mc.gtt_size >> 20),
791 (unsigned long long)rdev->gart.table_addr);
792 rdev->gart.ready = true;
793 return 0;
794}
795
796void cayman_pcie_gart_disable(struct radeon_device *rdev)
797{
798 /* Disable all tables */
799 WREG32(VM_CONTEXT0_CNTL, 0);
800 WREG32(VM_CONTEXT1_CNTL, 0);
801 /* Setup TLB control */
802 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
803 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
804 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
805 /* Setup L2 cache */
806 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
807 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
808 EFFECTIVE_L2_QUEUE_SIZE(7) |
809 CONTEXT1_IDENTITY_ACCESS_MODE(1));
810 WREG32(VM_L2_CNTL2, 0);
811 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
812 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
813 radeon_gart_table_vram_unpin(rdev);
814}
815
816void cayman_pcie_gart_fini(struct radeon_device *rdev)
817{
818 cayman_pcie_gart_disable(rdev);
819 radeon_gart_table_vram_free(rdev);
820 radeon_gart_fini(rdev);
821}
822
823void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
824 int ring, u32 cp_int_cntl)
825{
826 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
827
828 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
829 WREG32(CP_INT_CNTL, cp_int_cntl);
830}
831
832/*
833 * CP.
834 */
835void cayman_fence_ring_emit(struct radeon_device *rdev,
836 struct radeon_fence *fence)
837{
838 struct radeon_ring *ring = &rdev->ring[fence->ring];
839 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
840
841 /* flush read cache over gart for this vmid */
842 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
843 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
844 radeon_ring_write(ring, 0);
845 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
846 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
847 radeon_ring_write(ring, 0xFFFFFFFF);
848 radeon_ring_write(ring, 0);
849 radeon_ring_write(ring, 10); /* poll interval */
850 /* EVENT_WRITE_EOP - flush caches, send int */
851 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
852 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
853 radeon_ring_write(ring, addr & 0xffffffff);
854 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
855 radeon_ring_write(ring, fence->seq);
856 radeon_ring_write(ring, 0);
857}
858
859void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
860{
861 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
862
863 /* set to DX10/11 mode */
864 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
865 radeon_ring_write(ring, 1);
866 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
867 radeon_ring_write(ring,
868#ifdef __BIG_ENDIAN
869 (2 << 0) |
870#endif
871 (ib->gpu_addr & 0xFFFFFFFC));
872 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
873 radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
874
875 /* flush read cache over gart for this vmid */
876 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
877 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
878 radeon_ring_write(ring, ib->vm_id);
879 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
880 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
881 radeon_ring_write(ring, 0xFFFFFFFF);
882 radeon_ring_write(ring, 0);
883 radeon_ring_write(ring, 10); /* poll interval */
884}
885
886static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
887{
888 if (enable)
889 WREG32(CP_ME_CNTL, 0);
890 else {
891 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
892 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
893 WREG32(SCRATCH_UMSK, 0);
894 }
895}
896
897static int cayman_cp_load_microcode(struct radeon_device *rdev)
898{
899 const __be32 *fw_data;
900 int i;
901
902 if (!rdev->me_fw || !rdev->pfp_fw)
903 return -EINVAL;
904
905 cayman_cp_enable(rdev, false);
906
907 fw_data = (const __be32 *)rdev->pfp_fw->data;
908 WREG32(CP_PFP_UCODE_ADDR, 0);
909 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
910 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
911 WREG32(CP_PFP_UCODE_ADDR, 0);
912
913 fw_data = (const __be32 *)rdev->me_fw->data;
914 WREG32(CP_ME_RAM_WADDR, 0);
915 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
916 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
917
918 WREG32(CP_PFP_UCODE_ADDR, 0);
919 WREG32(CP_ME_RAM_WADDR, 0);
920 WREG32(CP_ME_RAM_RADDR, 0);
921 return 0;
922}
923
924static int cayman_cp_start(struct radeon_device *rdev)
925{
926 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
927 int r, i;
928
929 r = radeon_ring_lock(rdev, ring, 7);
930 if (r) {
931 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
932 return r;
933 }
934 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
935 radeon_ring_write(ring, 0x1);
936 radeon_ring_write(ring, 0x0);
937 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
938 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
939 radeon_ring_write(ring, 0);
940 radeon_ring_write(ring, 0);
941 radeon_ring_unlock_commit(rdev, ring);
942
943 cayman_cp_enable(rdev, true);
944
945 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
946 if (r) {
947 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
948 return r;
949 }
950
951 /* setup clear context state */
952 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
953 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
954
955 for (i = 0; i < cayman_default_size; i++)
956 radeon_ring_write(ring, cayman_default_state[i]);
957
958 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
959 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
960
961 /* set clear context state */
962 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
963 radeon_ring_write(ring, 0);
964
965 /* SQ_VTX_BASE_VTX_LOC */
966 radeon_ring_write(ring, 0xc0026f00);
967 radeon_ring_write(ring, 0x00000000);
968 radeon_ring_write(ring, 0x00000000);
969 radeon_ring_write(ring, 0x00000000);
970
971 /* Clear consts */
972 radeon_ring_write(ring, 0xc0036f00);
973 radeon_ring_write(ring, 0x00000bc4);
974 radeon_ring_write(ring, 0xffffffff);
975 radeon_ring_write(ring, 0xffffffff);
976 radeon_ring_write(ring, 0xffffffff);
977
978 radeon_ring_write(ring, 0xc0026900);
979 radeon_ring_write(ring, 0x00000316);
980 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
981 radeon_ring_write(ring, 0x00000010); /* */
982
983 radeon_ring_unlock_commit(rdev, ring);
984
985 /* XXX init other rings */
986
987 return 0;
988}
989
990static void cayman_cp_fini(struct radeon_device *rdev)
991{
992 cayman_cp_enable(rdev, false);
993 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
994}
995
996int cayman_cp_resume(struct radeon_device *rdev)
997{
998 struct radeon_ring *ring;
999 u32 tmp;
1000 u32 rb_bufsz;
1001 int r;
1002
1003 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1004 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1005 SOFT_RESET_PA |
1006 SOFT_RESET_SH |
1007 SOFT_RESET_VGT |
1008 SOFT_RESET_SPI |
1009 SOFT_RESET_SX));
1010 RREG32(GRBM_SOFT_RESET);
1011 mdelay(15);
1012 WREG32(GRBM_SOFT_RESET, 0);
1013 RREG32(GRBM_SOFT_RESET);
1014
1015 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1016 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1017
1018 /* Set the write pointer delay */
1019 WREG32(CP_RB_WPTR_DELAY, 0);
1020
1021 WREG32(CP_DEBUG, (1 << 27));
1022
1023 /* ring 0 - compute and gfx */
1024 /* Set ring buffer size */
1025 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1026 rb_bufsz = drm_order(ring->ring_size / 8);
1027 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1028#ifdef __BIG_ENDIAN
1029 tmp |= BUF_SWAP_32BIT;
1030#endif
1031 WREG32(CP_RB0_CNTL, tmp);
1032
1033 /* Initialize the ring buffer's read and write pointers */
1034 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1035 ring->wptr = 0;
1036 WREG32(CP_RB0_WPTR, ring->wptr);
1037
1038 /* set the wb address wether it's enabled or not */
1039 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1040 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1041 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1042
1043 if (rdev->wb.enabled)
1044 WREG32(SCRATCH_UMSK, 0xff);
1045 else {
1046 tmp |= RB_NO_UPDATE;
1047 WREG32(SCRATCH_UMSK, 0);
1048 }
1049
1050 mdelay(1);
1051 WREG32(CP_RB0_CNTL, tmp);
1052
1053 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1054
1055 ring->rptr = RREG32(CP_RB0_RPTR);
1056
1057 /* ring1 - compute only */
1058 /* Set ring buffer size */
1059 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1060 rb_bufsz = drm_order(ring->ring_size / 8);
1061 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1062#ifdef __BIG_ENDIAN
1063 tmp |= BUF_SWAP_32BIT;
1064#endif
1065 WREG32(CP_RB1_CNTL, tmp);
1066
1067 /* Initialize the ring buffer's read and write pointers */
1068 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1069 ring->wptr = 0;
1070 WREG32(CP_RB1_WPTR, ring->wptr);
1071
1072 /* set the wb address wether it's enabled or not */
1073 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1074 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1075
1076 mdelay(1);
1077 WREG32(CP_RB1_CNTL, tmp);
1078
1079 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1080
1081 ring->rptr = RREG32(CP_RB1_RPTR);
1082
1083 /* ring2 - compute only */
1084 /* Set ring buffer size */
1085 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1086 rb_bufsz = drm_order(ring->ring_size / 8);
1087 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1088#ifdef __BIG_ENDIAN
1089 tmp |= BUF_SWAP_32BIT;
1090#endif
1091 WREG32(CP_RB2_CNTL, tmp);
1092
1093 /* Initialize the ring buffer's read and write pointers */
1094 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1095 ring->wptr = 0;
1096 WREG32(CP_RB2_WPTR, ring->wptr);
1097
1098 /* set the wb address wether it's enabled or not */
1099 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1100 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1101
1102 mdelay(1);
1103 WREG32(CP_RB2_CNTL, tmp);
1104
1105 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1106
1107 ring->rptr = RREG32(CP_RB2_RPTR);
1108
1109 /* start the rings */
1110 cayman_cp_start(rdev);
1111 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1112 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1113 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1114 /* this only test cp0 */
1115 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1116 if (r) {
1117 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1118 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1119 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1120 return r;
1121 }
1122
1123 return 0;
1124}
1125
1126static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1127{
1128 struct evergreen_mc_save save;
1129 u32 grbm_reset = 0;
1130
1131 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1132 return 0;
1133
1134 dev_info(rdev->dev, "GPU softreset \n");
1135 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1136 RREG32(GRBM_STATUS));
1137 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1138 RREG32(GRBM_STATUS_SE0));
1139 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1140 RREG32(GRBM_STATUS_SE1));
1141 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1142 RREG32(SRBM_STATUS));
1143 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1144 RREG32(0x14F8));
1145 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1146 RREG32(0x14D8));
1147 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1148 RREG32(0x14FC));
1149 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1150 RREG32(0x14DC));
1151
1152 evergreen_mc_stop(rdev, &save);
1153 if (evergreen_mc_wait_for_idle(rdev)) {
1154 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1155 }
1156 /* Disable CP parsing/prefetching */
1157 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1158
1159 /* reset all the gfx blocks */
1160 grbm_reset = (SOFT_RESET_CP |
1161 SOFT_RESET_CB |
1162 SOFT_RESET_DB |
1163 SOFT_RESET_GDS |
1164 SOFT_RESET_PA |
1165 SOFT_RESET_SC |
1166 SOFT_RESET_SPI |
1167 SOFT_RESET_SH |
1168 SOFT_RESET_SX |
1169 SOFT_RESET_TC |
1170 SOFT_RESET_TA |
1171 SOFT_RESET_VGT |
1172 SOFT_RESET_IA);
1173
1174 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1175 WREG32(GRBM_SOFT_RESET, grbm_reset);
1176 (void)RREG32(GRBM_SOFT_RESET);
1177 udelay(50);
1178 WREG32(GRBM_SOFT_RESET, 0);
1179 (void)RREG32(GRBM_SOFT_RESET);
1180 /* Wait a little for things to settle down */
1181 udelay(50);
1182
1183 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1184 RREG32(GRBM_STATUS));
1185 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1186 RREG32(GRBM_STATUS_SE0));
1187 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1188 RREG32(GRBM_STATUS_SE1));
1189 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1190 RREG32(SRBM_STATUS));
1191 evergreen_mc_resume(rdev, &save);
1192 return 0;
1193}
1194
1195int cayman_asic_reset(struct radeon_device *rdev)
1196{
1197 return cayman_gpu_soft_reset(rdev);
1198}
1199
1200static int cayman_startup(struct radeon_device *rdev)
1201{
1202 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1203 int r;
1204
1205 /* enable pcie gen2 link */
1206 evergreen_pcie_gen2_enable(rdev);
1207
1208 if (rdev->flags & RADEON_IS_IGP) {
1209 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1210 r = ni_init_microcode(rdev);
1211 if (r) {
1212 DRM_ERROR("Failed to load firmware!\n");
1213 return r;
1214 }
1215 }
1216 } else {
1217 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1218 r = ni_init_microcode(rdev);
1219 if (r) {
1220 DRM_ERROR("Failed to load firmware!\n");
1221 return r;
1222 }
1223 }
1224
1225 r = ni_mc_load_microcode(rdev);
1226 if (r) {
1227 DRM_ERROR("Failed to load MC firmware!\n");
1228 return r;
1229 }
1230 }
1231
1232 r = r600_vram_scratch_init(rdev);
1233 if (r)
1234 return r;
1235
1236 evergreen_mc_program(rdev);
1237 r = cayman_pcie_gart_enable(rdev);
1238 if (r)
1239 return r;
1240 cayman_gpu_init(rdev);
1241
1242 r = evergreen_blit_init(rdev);
1243 if (r) {
1244 r600_blit_fini(rdev);
1245 rdev->asic->copy.copy = NULL;
1246 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1247 }
1248
1249 /* allocate rlc buffers */
1250 if (rdev->flags & RADEON_IS_IGP) {
1251 r = si_rlc_init(rdev);
1252 if (r) {
1253 DRM_ERROR("Failed to init rlc BOs!\n");
1254 return r;
1255 }
1256 }
1257
1258 /* allocate wb buffer */
1259 r = radeon_wb_init(rdev);
1260 if (r)
1261 return r;
1262
1263 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1264 if (r) {
1265 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1266 return r;
1267 }
1268
1269 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1270 if (r) {
1271 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1272 return r;
1273 }
1274
1275 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1276 if (r) {
1277 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1278 return r;
1279 }
1280
1281 /* Enable IRQ */
1282 r = r600_irq_init(rdev);
1283 if (r) {
1284 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1285 radeon_irq_kms_fini(rdev);
1286 return r;
1287 }
1288 evergreen_irq_set(rdev);
1289
1290 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1291 CP_RB0_RPTR, CP_RB0_WPTR,
1292 0, 0xfffff, RADEON_CP_PACKET2);
1293 if (r)
1294 return r;
1295 r = cayman_cp_load_microcode(rdev);
1296 if (r)
1297 return r;
1298 r = cayman_cp_resume(rdev);
1299 if (r)
1300 return r;
1301
1302 r = radeon_ib_pool_start(rdev);
1303 if (r)
1304 return r;
1305
1306 r = radeon_ib_ring_tests(rdev);
1307 if (r)
1308 return r;
1309
1310 r = radeon_vm_manager_start(rdev);
1311 if (r)
1312 return r;
1313
1314 r = r600_audio_init(rdev);
1315 if (r)
1316 return r;
1317
1318 return 0;
1319}
1320
1321int cayman_resume(struct radeon_device *rdev)
1322{
1323 int r;
1324
1325 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1326 * posting will perform necessary task to bring back GPU into good
1327 * shape.
1328 */
1329 /* post card */
1330 atom_asic_init(rdev->mode_info.atom_context);
1331
1332 rdev->accel_working = true;
1333 r = cayman_startup(rdev);
1334 if (r) {
1335 DRM_ERROR("cayman startup failed on resume\n");
1336 rdev->accel_working = false;
1337 return r;
1338 }
1339 return r;
1340}
1341
1342int cayman_suspend(struct radeon_device *rdev)
1343{
1344 r600_audio_fini(rdev);
1345 /* FIXME: we should wait for ring to be empty */
1346 radeon_ib_pool_suspend(rdev);
1347 radeon_vm_manager_suspend(rdev);
1348 r600_blit_suspend(rdev);
1349 cayman_cp_enable(rdev, false);
1350 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1351 evergreen_irq_suspend(rdev);
1352 radeon_wb_disable(rdev);
1353 cayman_pcie_gart_disable(rdev);
1354 return 0;
1355}
1356
1357/* Plan is to move initialization in that function and use
1358 * helper function so that radeon_device_init pretty much
1359 * do nothing more than calling asic specific function. This
1360 * should also allow to remove a bunch of callback function
1361 * like vram_info.
1362 */
1363int cayman_init(struct radeon_device *rdev)
1364{
1365 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1366 int r;
1367
1368 /* Read BIOS */
1369 if (!radeon_get_bios(rdev)) {
1370 if (ASIC_IS_AVIVO(rdev))
1371 return -EINVAL;
1372 }
1373 /* Must be an ATOMBIOS */
1374 if (!rdev->is_atom_bios) {
1375 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1376 return -EINVAL;
1377 }
1378 r = radeon_atombios_init(rdev);
1379 if (r)
1380 return r;
1381
1382 /* Post card if necessary */
1383 if (!radeon_card_posted(rdev)) {
1384 if (!rdev->bios) {
1385 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1386 return -EINVAL;
1387 }
1388 DRM_INFO("GPU not posted. posting now...\n");
1389 atom_asic_init(rdev->mode_info.atom_context);
1390 }
1391 /* Initialize scratch registers */
1392 r600_scratch_init(rdev);
1393 /* Initialize surface registers */
1394 radeon_surface_init(rdev);
1395 /* Initialize clocks */
1396 radeon_get_clock_info(rdev->ddev);
1397 /* Fence driver */
1398 r = radeon_fence_driver_init(rdev);
1399 if (r)
1400 return r;
1401 /* initialize memory controller */
1402 r = evergreen_mc_init(rdev);
1403 if (r)
1404 return r;
1405 /* Memory manager */
1406 r = radeon_bo_init(rdev);
1407 if (r)
1408 return r;
1409
1410 r = radeon_irq_kms_init(rdev);
1411 if (r)
1412 return r;
1413
1414 ring->ring_obj = NULL;
1415 r600_ring_init(rdev, ring, 1024 * 1024);
1416
1417 rdev->ih.ring_obj = NULL;
1418 r600_ih_ring_init(rdev, 64 * 1024);
1419
1420 r = r600_pcie_gart_init(rdev);
1421 if (r)
1422 return r;
1423
1424 r = radeon_ib_pool_init(rdev);
1425 rdev->accel_working = true;
1426 if (r) {
1427 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1428 rdev->accel_working = false;
1429 }
1430 r = radeon_vm_manager_init(rdev);
1431 if (r) {
1432 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1433 }
1434
1435 r = cayman_startup(rdev);
1436 if (r) {
1437 dev_err(rdev->dev, "disabling GPU acceleration\n");
1438 cayman_cp_fini(rdev);
1439 r600_irq_fini(rdev);
1440 if (rdev->flags & RADEON_IS_IGP)
1441 si_rlc_fini(rdev);
1442 radeon_wb_fini(rdev);
1443 r100_ib_fini(rdev);
1444 radeon_vm_manager_fini(rdev);
1445 radeon_irq_kms_fini(rdev);
1446 cayman_pcie_gart_fini(rdev);
1447 rdev->accel_working = false;
1448 }
1449
1450 /* Don't start up if the MC ucode is missing.
1451 * The default clocks and voltages before the MC ucode
1452 * is loaded are not suffient for advanced operations.
1453 *
1454 * We can skip this check for TN, because there is no MC
1455 * ucode.
1456 */
1457 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
1458 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1459 return -EINVAL;
1460 }
1461
1462 return 0;
1463}
1464
1465void cayman_fini(struct radeon_device *rdev)
1466{
1467 r600_blit_fini(rdev);
1468 cayman_cp_fini(rdev);
1469 r600_irq_fini(rdev);
1470 if (rdev->flags & RADEON_IS_IGP)
1471 si_rlc_fini(rdev);
1472 radeon_wb_fini(rdev);
1473 radeon_vm_manager_fini(rdev);
1474 r100_ib_fini(rdev);
1475 radeon_irq_kms_fini(rdev);
1476 cayman_pcie_gart_fini(rdev);
1477 r600_vram_scratch_fini(rdev);
1478 radeon_gem_fini(rdev);
1479 radeon_fence_driver_fini(rdev);
1480 radeon_bo_fini(rdev);
1481 radeon_atombios_fini(rdev);
1482 kfree(rdev->bios);
1483 rdev->bios = NULL;
1484}
1485
1486/*
1487 * vm
1488 */
1489int cayman_vm_init(struct radeon_device *rdev)
1490{
1491 /* number of VMs */
1492 rdev->vm_manager.nvm = 8;
1493 /* base offset of vram pages */
1494 if (rdev->flags & RADEON_IS_IGP) {
1495 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1496 tmp <<= 22;
1497 rdev->vm_manager.vram_base_offset = tmp;
1498 } else
1499 rdev->vm_manager.vram_base_offset = 0;
1500 return 0;
1501}
1502
1503void cayman_vm_fini(struct radeon_device *rdev)
1504{
1505}
1506
1507int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
1508{
1509 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (id << 2), 0);
1510 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (id << 2), vm->last_pfn);
1511 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
1512 /* flush hdp cache */
1513 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1514 /* bits 0-7 are the VM contexts0-7 */
1515 WREG32(VM_INVALIDATE_REQUEST, 1 << id);
1516 return 0;
1517}
1518
1519void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
1520{
1521 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0);
1522 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0);
1523 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
1524 /* flush hdp cache */
1525 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1526 /* bits 0-7 are the VM contexts0-7 */
1527 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1528}
1529
1530void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
1531{
1532 if (vm->id == -1)
1533 return;
1534
1535 /* flush hdp cache */
1536 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1537 /* bits 0-7 are the VM contexts0-7 */
1538 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1539}
1540
1541#define R600_PTE_VALID (1 << 0)
1542#define R600_PTE_SYSTEM (1 << 1)
1543#define R600_PTE_SNOOPED (1 << 2)
1544#define R600_PTE_READABLE (1 << 5)
1545#define R600_PTE_WRITEABLE (1 << 6)
1546
1547uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
1548 struct radeon_vm *vm,
1549 uint32_t flags)
1550{
1551 uint32_t r600_flags = 0;
1552
1553 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
1554 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1555 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1556 if (flags & RADEON_VM_PAGE_SYSTEM) {
1557 r600_flags |= R600_PTE_SYSTEM;
1558 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1559 }
1560 return r600_flags;
1561}
1562
1563void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
1564 unsigned pfn, uint64_t addr, uint32_t flags)
1565{
1566 void __iomem *ptr = (void *)vm->pt;
1567
1568 addr = addr & 0xFFFFFFFFFFFFF000ULL;
1569 addr |= flags;
1570 writeq(addr, ptr + (pfn * 8));
1571}