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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72#include <ttm/ttm_execbuf_util.h>
73
74#include "radeon_family.h"
75#include "radeon_mode.h"
76#include "radeon_reg.h"
77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
89extern int radeon_testing;
90extern int radeon_connector_table;
91extern int radeon_tv;
92extern int radeon_audio;
93extern int radeon_disp_priority;
94extern int radeon_hw_i2c;
95extern int radeon_pcie_gen2;
96extern int radeon_msi;
97extern int radeon_lockup_timeout;
98
99/*
100 * Copy from radeon_drv.h so we don't have to include both and have conflicting
101 * symbol;
102 */
103#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
104#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
105/* RADEON_IB_POOL_SIZE must be a power of 2 */
106#define RADEON_IB_POOL_SIZE 16
107#define RADEON_DEBUGFS_MAX_COMPONENTS 32
108#define RADEONFB_CONN_LIMIT 4
109#define RADEON_BIOS_NUM_SCRATCH 8
110
111/* max number of rings */
112#define RADEON_NUM_RINGS 3
113
114/* fence seq are set to this number when signaled */
115#define RADEON_FENCE_SIGNALED_SEQ 0LL
116#define RADEON_FENCE_NOTEMITED_SEQ (~0LL)
117
118/* internal ring indices */
119/* r1xx+ has gfx CP ring */
120#define RADEON_RING_TYPE_GFX_INDEX 0
121
122/* cayman has 2 compute CP rings */
123#define CAYMAN_RING_TYPE_CP1_INDEX 1
124#define CAYMAN_RING_TYPE_CP2_INDEX 2
125
126/* hardcode those limit for now */
127#define RADEON_VA_RESERVED_SIZE (8 << 20)
128#define RADEON_IB_VM_MAX_SIZE (64 << 10)
129
130/*
131 * Errata workarounds.
132 */
133enum radeon_pll_errata {
134 CHIP_ERRATA_R300_CG = 0x00000001,
135 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
136 CHIP_ERRATA_PLL_DELAY = 0x00000004
137};
138
139
140struct radeon_device;
141
142
143/*
144 * BIOS.
145 */
146bool radeon_get_bios(struct radeon_device *rdev);
147
148
149/*
150 * Mutex which allows recursive locking from the same process.
151 */
152struct radeon_mutex {
153 struct mutex mutex;
154 struct task_struct *owner;
155 int level;
156};
157
158static inline void radeon_mutex_init(struct radeon_mutex *mutex)
159{
160 mutex_init(&mutex->mutex);
161 mutex->owner = NULL;
162 mutex->level = 0;
163}
164
165static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
166{
167 if (mutex_trylock(&mutex->mutex)) {
168 /* The mutex was unlocked before, so it's ours now */
169 mutex->owner = current;
170 } else if (mutex->owner != current) {
171 /* Another process locked the mutex, take it */
172 mutex_lock(&mutex->mutex);
173 mutex->owner = current;
174 }
175 /* Otherwise the mutex was already locked by this process */
176
177 mutex->level++;
178}
179
180static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
181{
182 if (--mutex->level > 0)
183 return;
184
185 mutex->owner = NULL;
186 mutex_unlock(&mutex->mutex);
187}
188
189
190/*
191 * Dummy page
192 */
193struct radeon_dummy_page {
194 struct page *page;
195 dma_addr_t addr;
196};
197int radeon_dummy_page_init(struct radeon_device *rdev);
198void radeon_dummy_page_fini(struct radeon_device *rdev);
199
200
201/*
202 * Clocks
203 */
204struct radeon_clock {
205 struct radeon_pll p1pll;
206 struct radeon_pll p2pll;
207 struct radeon_pll dcpll;
208 struct radeon_pll spll;
209 struct radeon_pll mpll;
210 /* 10 Khz units */
211 uint32_t default_mclk;
212 uint32_t default_sclk;
213 uint32_t default_dispclk;
214 uint32_t dp_extclk;
215 uint32_t max_pixel_clock;
216};
217
218/*
219 * Power management
220 */
221int radeon_pm_init(struct radeon_device *rdev);
222void radeon_pm_fini(struct radeon_device *rdev);
223void radeon_pm_compute_clocks(struct radeon_device *rdev);
224void radeon_pm_suspend(struct radeon_device *rdev);
225void radeon_pm_resume(struct radeon_device *rdev);
226void radeon_combios_get_power_modes(struct radeon_device *rdev);
227void radeon_atombios_get_power_modes(struct radeon_device *rdev);
228void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
229void rs690_pm_info(struct radeon_device *rdev);
230extern int rv6xx_get_temp(struct radeon_device *rdev);
231extern int rv770_get_temp(struct radeon_device *rdev);
232extern int evergreen_get_temp(struct radeon_device *rdev);
233extern int sumo_get_temp(struct radeon_device *rdev);
234extern int si_get_temp(struct radeon_device *rdev);
235extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
236 unsigned *bankh, unsigned *mtaspect,
237 unsigned *tile_split);
238
239/*
240 * Fences.
241 */
242struct radeon_fence_driver {
243 uint32_t scratch_reg;
244 uint64_t gpu_addr;
245 volatile uint32_t *cpu_addr;
246 /* seq is protected by ring emission lock */
247 uint64_t seq;
248 atomic64_t last_seq;
249 unsigned long last_activity;
250 bool initialized;
251};
252
253struct radeon_fence {
254 struct radeon_device *rdev;
255 struct kref kref;
256 /* protected by radeon_fence.lock */
257 uint64_t seq;
258 /* RB, DMA, etc. */
259 unsigned ring;
260};
261
262int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
263int radeon_fence_driver_init(struct radeon_device *rdev);
264void radeon_fence_driver_fini(struct radeon_device *rdev);
265int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
266int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
267void radeon_fence_process(struct radeon_device *rdev, int ring);
268bool radeon_fence_signaled(struct radeon_fence *fence);
269int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
270int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
271int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
272int radeon_fence_wait_any(struct radeon_device *rdev,
273 struct radeon_fence **fences,
274 bool intr);
275struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
276void radeon_fence_unref(struct radeon_fence **fence);
277unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
278
279/*
280 * Tiling registers
281 */
282struct radeon_surface_reg {
283 struct radeon_bo *bo;
284};
285
286#define RADEON_GEM_MAX_SURFACES 8
287
288/*
289 * TTM.
290 */
291struct radeon_mman {
292 struct ttm_bo_global_ref bo_global_ref;
293 struct drm_global_reference mem_global_ref;
294 struct ttm_bo_device bdev;
295 bool mem_global_referenced;
296 bool initialized;
297};
298
299/* bo virtual address in a specific vm */
300struct radeon_bo_va {
301 /* bo list is protected by bo being reserved */
302 struct list_head bo_list;
303 /* vm list is protected by vm mutex */
304 struct list_head vm_list;
305 /* constant after initialization */
306 struct radeon_vm *vm;
307 struct radeon_bo *bo;
308 uint64_t soffset;
309 uint64_t eoffset;
310 uint32_t flags;
311 struct radeon_fence *fence;
312 bool valid;
313};
314
315struct radeon_bo {
316 /* Protected by gem.mutex */
317 struct list_head list;
318 /* Protected by tbo.reserved */
319 u32 placements[3];
320 struct ttm_placement placement;
321 struct ttm_buffer_object tbo;
322 struct ttm_bo_kmap_obj kmap;
323 unsigned pin_count;
324 void *kptr;
325 u32 tiling_flags;
326 u32 pitch;
327 int surface_reg;
328 /* list of all virtual address to which this bo
329 * is associated to
330 */
331 struct list_head va;
332 /* Constant after initialization */
333 struct radeon_device *rdev;
334 struct drm_gem_object gem_base;
335
336 struct ttm_bo_kmap_obj dma_buf_vmap;
337 int vmapping_count;
338};
339#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
340
341struct radeon_bo_list {
342 struct ttm_validate_buffer tv;
343 struct radeon_bo *bo;
344 uint64_t gpu_offset;
345 unsigned rdomain;
346 unsigned wdomain;
347 u32 tiling_flags;
348};
349
350/* sub-allocation manager, it has to be protected by another lock.
351 * By conception this is an helper for other part of the driver
352 * like the indirect buffer or semaphore, which both have their
353 * locking.
354 *
355 * Principe is simple, we keep a list of sub allocation in offset
356 * order (first entry has offset == 0, last entry has the highest
357 * offset).
358 *
359 * When allocating new object we first check if there is room at
360 * the end total_size - (last_object_offset + last_object_size) >=
361 * alloc_size. If so we allocate new object there.
362 *
363 * When there is not enough room at the end, we start waiting for
364 * each sub object until we reach object_offset+object_size >=
365 * alloc_size, this object then become the sub object we return.
366 *
367 * Alignment can't be bigger than page size.
368 *
369 * Hole are not considered for allocation to keep things simple.
370 * Assumption is that there won't be hole (all object on same
371 * alignment).
372 */
373struct radeon_sa_manager {
374 spinlock_t lock;
375 struct radeon_bo *bo;
376 struct list_head *hole;
377 struct list_head flist[RADEON_NUM_RINGS];
378 struct list_head olist;
379 unsigned size;
380 uint64_t gpu_addr;
381 void *cpu_ptr;
382 uint32_t domain;
383};
384
385struct radeon_sa_bo;
386
387/* sub-allocation buffer */
388struct radeon_sa_bo {
389 struct list_head olist;
390 struct list_head flist;
391 struct radeon_sa_manager *manager;
392 unsigned soffset;
393 unsigned eoffset;
394 struct radeon_fence *fence;
395};
396
397/*
398 * GEM objects.
399 */
400struct radeon_gem {
401 struct mutex mutex;
402 struct list_head objects;
403};
404
405int radeon_gem_init(struct radeon_device *rdev);
406void radeon_gem_fini(struct radeon_device *rdev);
407int radeon_gem_object_create(struct radeon_device *rdev, int size,
408 int alignment, int initial_domain,
409 bool discardable, bool kernel,
410 struct drm_gem_object **obj);
411
412int radeon_mode_dumb_create(struct drm_file *file_priv,
413 struct drm_device *dev,
414 struct drm_mode_create_dumb *args);
415int radeon_mode_dumb_mmap(struct drm_file *filp,
416 struct drm_device *dev,
417 uint32_t handle, uint64_t *offset_p);
418int radeon_mode_dumb_destroy(struct drm_file *file_priv,
419 struct drm_device *dev,
420 uint32_t handle);
421
422/*
423 * Semaphores.
424 */
425/* everything here is constant */
426struct radeon_semaphore {
427 struct radeon_sa_bo *sa_bo;
428 signed waiters;
429 uint64_t gpu_addr;
430};
431
432int radeon_semaphore_create(struct radeon_device *rdev,
433 struct radeon_semaphore **semaphore);
434void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
435 struct radeon_semaphore *semaphore);
436void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
437 struct radeon_semaphore *semaphore);
438int radeon_semaphore_sync_rings(struct radeon_device *rdev,
439 struct radeon_semaphore *semaphore,
440 bool sync_to[RADEON_NUM_RINGS],
441 int dst_ring);
442void radeon_semaphore_free(struct radeon_device *rdev,
443 struct radeon_semaphore *semaphore,
444 struct radeon_fence *fence);
445
446/*
447 * GART structures, functions & helpers
448 */
449struct radeon_mc;
450
451#define RADEON_GPU_PAGE_SIZE 4096
452#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
453#define RADEON_GPU_PAGE_SHIFT 12
454#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
455
456struct radeon_gart {
457 dma_addr_t table_addr;
458 struct radeon_bo *robj;
459 void *ptr;
460 unsigned num_gpu_pages;
461 unsigned num_cpu_pages;
462 unsigned table_size;
463 struct page **pages;
464 dma_addr_t *pages_addr;
465 bool ready;
466};
467
468int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
469void radeon_gart_table_ram_free(struct radeon_device *rdev);
470int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
471void radeon_gart_table_vram_free(struct radeon_device *rdev);
472int radeon_gart_table_vram_pin(struct radeon_device *rdev);
473void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
474int radeon_gart_init(struct radeon_device *rdev);
475void radeon_gart_fini(struct radeon_device *rdev);
476void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
477 int pages);
478int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
479 int pages, struct page **pagelist,
480 dma_addr_t *dma_addr);
481void radeon_gart_restore(struct radeon_device *rdev);
482
483
484/*
485 * GPU MC structures, functions & helpers
486 */
487struct radeon_mc {
488 resource_size_t aper_size;
489 resource_size_t aper_base;
490 resource_size_t agp_base;
491 /* for some chips with <= 32MB we need to lie
492 * about vram size near mc fb location */
493 u64 mc_vram_size;
494 u64 visible_vram_size;
495 u64 gtt_size;
496 u64 gtt_start;
497 u64 gtt_end;
498 u64 vram_start;
499 u64 vram_end;
500 unsigned vram_width;
501 u64 real_vram_size;
502 int vram_mtrr;
503 bool vram_is_ddr;
504 bool igp_sideport_enabled;
505 u64 gtt_base_align;
506};
507
508bool radeon_combios_sideport_present(struct radeon_device *rdev);
509bool radeon_atombios_sideport_present(struct radeon_device *rdev);
510
511/*
512 * GPU scratch registers structures, functions & helpers
513 */
514struct radeon_scratch {
515 unsigned num_reg;
516 uint32_t reg_base;
517 bool free[32];
518 uint32_t reg[32];
519};
520
521int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
522void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
523
524
525/*
526 * IRQS.
527 */
528
529struct radeon_unpin_work {
530 struct work_struct work;
531 struct radeon_device *rdev;
532 int crtc_id;
533 struct radeon_fence *fence;
534 struct drm_pending_vblank_event *event;
535 struct radeon_bo *old_rbo;
536 u64 new_crtc_base;
537};
538
539struct r500_irq_stat_regs {
540 u32 disp_int;
541 u32 hdmi0_status;
542};
543
544struct r600_irq_stat_regs {
545 u32 disp_int;
546 u32 disp_int_cont;
547 u32 disp_int_cont2;
548 u32 d1grph_int;
549 u32 d2grph_int;
550 u32 hdmi0_status;
551 u32 hdmi1_status;
552};
553
554struct evergreen_irq_stat_regs {
555 u32 disp_int;
556 u32 disp_int_cont;
557 u32 disp_int_cont2;
558 u32 disp_int_cont3;
559 u32 disp_int_cont4;
560 u32 disp_int_cont5;
561 u32 d1grph_int;
562 u32 d2grph_int;
563 u32 d3grph_int;
564 u32 d4grph_int;
565 u32 d5grph_int;
566 u32 d6grph_int;
567 u32 afmt_status1;
568 u32 afmt_status2;
569 u32 afmt_status3;
570 u32 afmt_status4;
571 u32 afmt_status5;
572 u32 afmt_status6;
573};
574
575union radeon_irq_stat_regs {
576 struct r500_irq_stat_regs r500;
577 struct r600_irq_stat_regs r600;
578 struct evergreen_irq_stat_regs evergreen;
579};
580
581#define RADEON_MAX_HPD_PINS 6
582#define RADEON_MAX_CRTCS 6
583#define RADEON_MAX_AFMT_BLOCKS 6
584
585struct radeon_irq {
586 bool installed;
587 bool sw_int[RADEON_NUM_RINGS];
588 bool crtc_vblank_int[RADEON_MAX_CRTCS];
589 bool pflip[RADEON_MAX_CRTCS];
590 wait_queue_head_t vblank_queue;
591 bool hpd[RADEON_MAX_HPD_PINS];
592 bool gui_idle;
593 bool gui_idle_acked;
594 wait_queue_head_t idle_queue;
595 bool afmt[RADEON_MAX_AFMT_BLOCKS];
596 spinlock_t sw_lock;
597 int sw_refcount[RADEON_NUM_RINGS];
598 union radeon_irq_stat_regs stat_regs;
599 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
600 int pflip_refcount[RADEON_MAX_CRTCS];
601};
602
603int radeon_irq_kms_init(struct radeon_device *rdev);
604void radeon_irq_kms_fini(struct radeon_device *rdev);
605void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
606void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
607void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
608void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
609
610/*
611 * CP & rings.
612 */
613
614struct radeon_ib {
615 struct radeon_sa_bo *sa_bo;
616 uint32_t length_dw;
617 uint64_t gpu_addr;
618 uint32_t *ptr;
619 struct radeon_fence *fence;
620 unsigned vm_id;
621 bool is_const_ib;
622 struct radeon_semaphore *semaphore;
623};
624
625struct radeon_ring {
626 struct radeon_bo *ring_obj;
627 volatile uint32_t *ring;
628 unsigned rptr;
629 unsigned rptr_offs;
630 unsigned rptr_reg;
631 unsigned wptr;
632 unsigned wptr_old;
633 unsigned wptr_reg;
634 unsigned ring_size;
635 unsigned ring_free_dw;
636 int count_dw;
637 unsigned long last_activity;
638 unsigned last_rptr;
639 uint64_t gpu_addr;
640 uint32_t align_mask;
641 uint32_t ptr_mask;
642 bool ready;
643 u32 ptr_reg_shift;
644 u32 ptr_reg_mask;
645 u32 nop;
646};
647
648/*
649 * VM
650 */
651struct radeon_vm {
652 struct list_head list;
653 struct list_head va;
654 int id;
655 unsigned last_pfn;
656 u64 pt_gpu_addr;
657 u64 *pt;
658 struct radeon_sa_bo *sa_bo;
659 struct mutex mutex;
660 /* last fence for cs using this vm */
661 struct radeon_fence *fence;
662};
663
664struct radeon_vm_funcs {
665 int (*init)(struct radeon_device *rdev);
666 void (*fini)(struct radeon_device *rdev);
667 /* cs mutex must be lock for schedule_ib */
668 int (*bind)(struct radeon_device *rdev, struct radeon_vm *vm, int id);
669 void (*unbind)(struct radeon_device *rdev, struct radeon_vm *vm);
670 void (*tlb_flush)(struct radeon_device *rdev, struct radeon_vm *vm);
671 uint32_t (*page_flags)(struct radeon_device *rdev,
672 struct radeon_vm *vm,
673 uint32_t flags);
674 void (*set_page)(struct radeon_device *rdev, struct radeon_vm *vm,
675 unsigned pfn, uint64_t addr, uint32_t flags);
676};
677
678struct radeon_vm_manager {
679 struct list_head lru_vm;
680 uint32_t use_bitmap;
681 struct radeon_sa_manager sa_manager;
682 uint32_t max_pfn;
683 /* fields constant after init */
684 const struct radeon_vm_funcs *funcs;
685 /* number of VMIDs */
686 unsigned nvm;
687 /* vram base address for page table entry */
688 u64 vram_base_offset;
689 /* is vm enabled? */
690 bool enabled;
691};
692
693/*
694 * file private structure
695 */
696struct radeon_fpriv {
697 struct radeon_vm vm;
698};
699
700/*
701 * R6xx+ IH ring
702 */
703struct r600_ih {
704 struct radeon_bo *ring_obj;
705 volatile uint32_t *ring;
706 unsigned rptr;
707 unsigned rptr_offs;
708 unsigned wptr;
709 unsigned wptr_old;
710 unsigned ring_size;
711 uint64_t gpu_addr;
712 uint32_t ptr_mask;
713 spinlock_t lock;
714 bool enabled;
715};
716
717struct r600_blit_cp_primitives {
718 void (*set_render_target)(struct radeon_device *rdev, int format,
719 int w, int h, u64 gpu_addr);
720 void (*cp_set_surface_sync)(struct radeon_device *rdev,
721 u32 sync_type, u32 size,
722 u64 mc_addr);
723 void (*set_shaders)(struct radeon_device *rdev);
724 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
725 void (*set_tex_resource)(struct radeon_device *rdev,
726 int format, int w, int h, int pitch,
727 u64 gpu_addr, u32 size);
728 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
729 int x2, int y2);
730 void (*draw_auto)(struct radeon_device *rdev);
731 void (*set_default_state)(struct radeon_device *rdev);
732};
733
734struct r600_blit {
735 struct radeon_bo *shader_obj;
736 struct r600_blit_cp_primitives primitives;
737 int max_dim;
738 int ring_size_common;
739 int ring_size_per_loop;
740 u64 shader_gpu_addr;
741 u32 vs_offset, ps_offset;
742 u32 state_offset;
743 u32 state_len;
744};
745
746void r600_blit_suspend(struct radeon_device *rdev);
747
748/*
749 * SI RLC stuff
750 */
751struct si_rlc {
752 /* for power gating */
753 struct radeon_bo *save_restore_obj;
754 uint64_t save_restore_gpu_addr;
755 /* for clear state */
756 struct radeon_bo *clear_state_obj;
757 uint64_t clear_state_gpu_addr;
758};
759
760int radeon_ib_get(struct radeon_device *rdev, int ring,
761 struct radeon_ib *ib, unsigned size);
762void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
763int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
764int radeon_ib_pool_init(struct radeon_device *rdev);
765void radeon_ib_pool_fini(struct radeon_device *rdev);
766int radeon_ib_pool_start(struct radeon_device *rdev);
767int radeon_ib_pool_suspend(struct radeon_device *rdev);
768int radeon_ib_ring_tests(struct radeon_device *rdev);
769/* Ring access between begin & end cannot sleep */
770int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
771void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
772int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
773int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
774void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
775void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
776void radeon_ring_undo(struct radeon_ring *ring);
777void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
778int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
779void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
780void radeon_ring_lockup_update(struct radeon_ring *ring);
781bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
782int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
783 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
784 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
785void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
786
787
788/*
789 * CS.
790 */
791struct radeon_cs_reloc {
792 struct drm_gem_object *gobj;
793 struct radeon_bo *robj;
794 struct radeon_bo_list lobj;
795 uint32_t handle;
796 uint32_t flags;
797};
798
799struct radeon_cs_chunk {
800 uint32_t chunk_id;
801 uint32_t length_dw;
802 int kpage_idx[2];
803 uint32_t *kpage[2];
804 uint32_t *kdata;
805 void __user *user_ptr;
806 int last_copied_page;
807 int last_page_index;
808};
809
810struct radeon_cs_parser {
811 struct device *dev;
812 struct radeon_device *rdev;
813 struct drm_file *filp;
814 /* chunks */
815 unsigned nchunks;
816 struct radeon_cs_chunk *chunks;
817 uint64_t *chunks_array;
818 /* IB */
819 unsigned idx;
820 /* relocations */
821 unsigned nrelocs;
822 struct radeon_cs_reloc *relocs;
823 struct radeon_cs_reloc **relocs_ptr;
824 struct list_head validated;
825 /* indices of various chunks */
826 int chunk_ib_idx;
827 int chunk_relocs_idx;
828 int chunk_flags_idx;
829 int chunk_const_ib_idx;
830 struct radeon_ib ib;
831 struct radeon_ib const_ib;
832 void *track;
833 unsigned family;
834 int parser_error;
835 u32 cs_flags;
836 u32 ring;
837 s32 priority;
838};
839
840extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
841extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
842
843struct radeon_cs_packet {
844 unsigned idx;
845 unsigned type;
846 unsigned reg;
847 unsigned opcode;
848 int count;
849 unsigned one_reg_wr;
850};
851
852typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
853 struct radeon_cs_packet *pkt,
854 unsigned idx, unsigned reg);
855typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
856 struct radeon_cs_packet *pkt);
857
858
859/*
860 * AGP
861 */
862int radeon_agp_init(struct radeon_device *rdev);
863void radeon_agp_resume(struct radeon_device *rdev);
864void radeon_agp_suspend(struct radeon_device *rdev);
865void radeon_agp_fini(struct radeon_device *rdev);
866
867
868/*
869 * Writeback
870 */
871struct radeon_wb {
872 struct radeon_bo *wb_obj;
873 volatile uint32_t *wb;
874 uint64_t gpu_addr;
875 bool enabled;
876 bool use_event;
877};
878
879#define RADEON_WB_SCRATCH_OFFSET 0
880#define RADEON_WB_CP_RPTR_OFFSET 1024
881#define RADEON_WB_CP1_RPTR_OFFSET 1280
882#define RADEON_WB_CP2_RPTR_OFFSET 1536
883#define R600_WB_IH_WPTR_OFFSET 2048
884#define R600_WB_EVENT_OFFSET 3072
885
886/**
887 * struct radeon_pm - power management datas
888 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
889 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
890 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
891 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
892 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
893 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
894 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
895 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
896 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
897 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
898 * @needed_bandwidth: current bandwidth needs
899 *
900 * It keeps track of various data needed to take powermanagement decision.
901 * Bandwidth need is used to determine minimun clock of the GPU and memory.
902 * Equation between gpu/memory clock and available bandwidth is hw dependent
903 * (type of memory, bus size, efficiency, ...)
904 */
905
906enum radeon_pm_method {
907 PM_METHOD_PROFILE,
908 PM_METHOD_DYNPM,
909};
910
911enum radeon_dynpm_state {
912 DYNPM_STATE_DISABLED,
913 DYNPM_STATE_MINIMUM,
914 DYNPM_STATE_PAUSED,
915 DYNPM_STATE_ACTIVE,
916 DYNPM_STATE_SUSPENDED,
917};
918enum radeon_dynpm_action {
919 DYNPM_ACTION_NONE,
920 DYNPM_ACTION_MINIMUM,
921 DYNPM_ACTION_DOWNCLOCK,
922 DYNPM_ACTION_UPCLOCK,
923 DYNPM_ACTION_DEFAULT
924};
925
926enum radeon_voltage_type {
927 VOLTAGE_NONE = 0,
928 VOLTAGE_GPIO,
929 VOLTAGE_VDDC,
930 VOLTAGE_SW
931};
932
933enum radeon_pm_state_type {
934 POWER_STATE_TYPE_DEFAULT,
935 POWER_STATE_TYPE_POWERSAVE,
936 POWER_STATE_TYPE_BATTERY,
937 POWER_STATE_TYPE_BALANCED,
938 POWER_STATE_TYPE_PERFORMANCE,
939};
940
941enum radeon_pm_profile_type {
942 PM_PROFILE_DEFAULT,
943 PM_PROFILE_AUTO,
944 PM_PROFILE_LOW,
945 PM_PROFILE_MID,
946 PM_PROFILE_HIGH,
947};
948
949#define PM_PROFILE_DEFAULT_IDX 0
950#define PM_PROFILE_LOW_SH_IDX 1
951#define PM_PROFILE_MID_SH_IDX 2
952#define PM_PROFILE_HIGH_SH_IDX 3
953#define PM_PROFILE_LOW_MH_IDX 4
954#define PM_PROFILE_MID_MH_IDX 5
955#define PM_PROFILE_HIGH_MH_IDX 6
956#define PM_PROFILE_MAX 7
957
958struct radeon_pm_profile {
959 int dpms_off_ps_idx;
960 int dpms_on_ps_idx;
961 int dpms_off_cm_idx;
962 int dpms_on_cm_idx;
963};
964
965enum radeon_int_thermal_type {
966 THERMAL_TYPE_NONE,
967 THERMAL_TYPE_RV6XX,
968 THERMAL_TYPE_RV770,
969 THERMAL_TYPE_EVERGREEN,
970 THERMAL_TYPE_SUMO,
971 THERMAL_TYPE_NI,
972 THERMAL_TYPE_SI,
973};
974
975struct radeon_voltage {
976 enum radeon_voltage_type type;
977 /* gpio voltage */
978 struct radeon_gpio_rec gpio;
979 u32 delay; /* delay in usec from voltage drop to sclk change */
980 bool active_high; /* voltage drop is active when bit is high */
981 /* VDDC voltage */
982 u8 vddc_id; /* index into vddc voltage table */
983 u8 vddci_id; /* index into vddci voltage table */
984 bool vddci_enabled;
985 /* r6xx+ sw */
986 u16 voltage;
987 /* evergreen+ vddci */
988 u16 vddci;
989};
990
991/* clock mode flags */
992#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
993
994struct radeon_pm_clock_info {
995 /* memory clock */
996 u32 mclk;
997 /* engine clock */
998 u32 sclk;
999 /* voltage info */
1000 struct radeon_voltage voltage;
1001 /* standardized clock flags */
1002 u32 flags;
1003};
1004
1005/* state flags */
1006#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1007
1008struct radeon_power_state {
1009 enum radeon_pm_state_type type;
1010 struct radeon_pm_clock_info *clock_info;
1011 /* number of valid clock modes in this power state */
1012 int num_clock_modes;
1013 struct radeon_pm_clock_info *default_clock_mode;
1014 /* standardized state flags */
1015 u32 flags;
1016 u32 misc; /* vbios specific flags */
1017 u32 misc2; /* vbios specific flags */
1018 int pcie_lanes; /* pcie lanes */
1019};
1020
1021/*
1022 * Some modes are overclocked by very low value, accept them
1023 */
1024#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1025
1026struct radeon_pm {
1027 struct mutex mutex;
1028 u32 active_crtcs;
1029 int active_crtc_count;
1030 int req_vblank;
1031 bool vblank_sync;
1032 bool gui_idle;
1033 fixed20_12 max_bandwidth;
1034 fixed20_12 igp_sideport_mclk;
1035 fixed20_12 igp_system_mclk;
1036 fixed20_12 igp_ht_link_clk;
1037 fixed20_12 igp_ht_link_width;
1038 fixed20_12 k8_bandwidth;
1039 fixed20_12 sideport_bandwidth;
1040 fixed20_12 ht_bandwidth;
1041 fixed20_12 core_bandwidth;
1042 fixed20_12 sclk;
1043 fixed20_12 mclk;
1044 fixed20_12 needed_bandwidth;
1045 struct radeon_power_state *power_state;
1046 /* number of valid power states */
1047 int num_power_states;
1048 int current_power_state_index;
1049 int current_clock_mode_index;
1050 int requested_power_state_index;
1051 int requested_clock_mode_index;
1052 int default_power_state_index;
1053 u32 current_sclk;
1054 u32 current_mclk;
1055 u16 current_vddc;
1056 u16 current_vddci;
1057 u32 default_sclk;
1058 u32 default_mclk;
1059 u16 default_vddc;
1060 u16 default_vddci;
1061 struct radeon_i2c_chan *i2c_bus;
1062 /* selected pm method */
1063 enum radeon_pm_method pm_method;
1064 /* dynpm power management */
1065 struct delayed_work dynpm_idle_work;
1066 enum radeon_dynpm_state dynpm_state;
1067 enum radeon_dynpm_action dynpm_planned_action;
1068 unsigned long dynpm_action_timeout;
1069 bool dynpm_can_upclock;
1070 bool dynpm_can_downclock;
1071 /* profile-based power management */
1072 enum radeon_pm_profile_type profile;
1073 int profile_index;
1074 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1075 /* internal thermal controller on rv6xx+ */
1076 enum radeon_int_thermal_type int_thermal_type;
1077 struct device *int_hwmon_dev;
1078};
1079
1080int radeon_pm_get_type_index(struct radeon_device *rdev,
1081 enum radeon_pm_state_type ps_type,
1082 int instance);
1083
1084struct r600_audio {
1085 int channels;
1086 int rate;
1087 int bits_per_sample;
1088 u8 status_bits;
1089 u8 category_code;
1090};
1091
1092/*
1093 * Benchmarking
1094 */
1095void radeon_benchmark(struct radeon_device *rdev, int test_number);
1096
1097
1098/*
1099 * Testing
1100 */
1101void radeon_test_moves(struct radeon_device *rdev);
1102void radeon_test_ring_sync(struct radeon_device *rdev,
1103 struct radeon_ring *cpA,
1104 struct radeon_ring *cpB);
1105void radeon_test_syncing(struct radeon_device *rdev);
1106
1107
1108/*
1109 * Debugfs
1110 */
1111struct radeon_debugfs {
1112 struct drm_info_list *files;
1113 unsigned num_files;
1114};
1115
1116int radeon_debugfs_add_files(struct radeon_device *rdev,
1117 struct drm_info_list *files,
1118 unsigned nfiles);
1119int radeon_debugfs_fence_init(struct radeon_device *rdev);
1120
1121
1122/*
1123 * ASIC specific functions.
1124 */
1125struct radeon_asic {
1126 int (*init)(struct radeon_device *rdev);
1127 void (*fini)(struct radeon_device *rdev);
1128 int (*resume)(struct radeon_device *rdev);
1129 int (*suspend)(struct radeon_device *rdev);
1130 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1131 int (*asic_reset)(struct radeon_device *rdev);
1132 /* ioctl hw specific callback. Some hw might want to perform special
1133 * operation on specific ioctl. For instance on wait idle some hw
1134 * might want to perform and HDP flush through MMIO as it seems that
1135 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1136 * through ring.
1137 */
1138 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1139 /* check if 3D engine is idle */
1140 bool (*gui_idle)(struct radeon_device *rdev);
1141 /* wait for mc_idle */
1142 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1143 /* gart */
1144 struct {
1145 void (*tlb_flush)(struct radeon_device *rdev);
1146 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1147 } gart;
1148 /* ring specific callbacks */
1149 struct {
1150 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1151 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1152 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1153 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1154 struct radeon_semaphore *semaphore, bool emit_wait);
1155 int (*cs_parse)(struct radeon_cs_parser *p);
1156 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1157 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1158 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1159 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1160 } ring[RADEON_NUM_RINGS];
1161 /* irqs */
1162 struct {
1163 int (*set)(struct radeon_device *rdev);
1164 int (*process)(struct radeon_device *rdev);
1165 } irq;
1166 /* displays */
1167 struct {
1168 /* display watermarks */
1169 void (*bandwidth_update)(struct radeon_device *rdev);
1170 /* get frame count */
1171 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1172 /* wait for vblank */
1173 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1174 } display;
1175 /* copy functions for bo handling */
1176 struct {
1177 int (*blit)(struct radeon_device *rdev,
1178 uint64_t src_offset,
1179 uint64_t dst_offset,
1180 unsigned num_gpu_pages,
1181 struct radeon_fence *fence);
1182 u32 blit_ring_index;
1183 int (*dma)(struct radeon_device *rdev,
1184 uint64_t src_offset,
1185 uint64_t dst_offset,
1186 unsigned num_gpu_pages,
1187 struct radeon_fence *fence);
1188 u32 dma_ring_index;
1189 /* method used for bo copy */
1190 int (*copy)(struct radeon_device *rdev,
1191 uint64_t src_offset,
1192 uint64_t dst_offset,
1193 unsigned num_gpu_pages,
1194 struct radeon_fence *fence);
1195 /* ring used for bo copies */
1196 u32 copy_ring_index;
1197 } copy;
1198 /* surfaces */
1199 struct {
1200 int (*set_reg)(struct radeon_device *rdev, int reg,
1201 uint32_t tiling_flags, uint32_t pitch,
1202 uint32_t offset, uint32_t obj_size);
1203 void (*clear_reg)(struct radeon_device *rdev, int reg);
1204 } surface;
1205 /* hotplug detect */
1206 struct {
1207 void (*init)(struct radeon_device *rdev);
1208 void (*fini)(struct radeon_device *rdev);
1209 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1210 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1211 } hpd;
1212 /* power management */
1213 struct {
1214 void (*misc)(struct radeon_device *rdev);
1215 void (*prepare)(struct radeon_device *rdev);
1216 void (*finish)(struct radeon_device *rdev);
1217 void (*init_profile)(struct radeon_device *rdev);
1218 void (*get_dynpm_state)(struct radeon_device *rdev);
1219 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1220 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1221 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1222 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1223 int (*get_pcie_lanes)(struct radeon_device *rdev);
1224 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1225 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1226 } pm;
1227 /* pageflipping */
1228 struct {
1229 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1230 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1231 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1232 } pflip;
1233};
1234
1235/*
1236 * Asic structures
1237 */
1238struct r100_asic {
1239 const unsigned *reg_safe_bm;
1240 unsigned reg_safe_bm_size;
1241 u32 hdp_cntl;
1242};
1243
1244struct r300_asic {
1245 const unsigned *reg_safe_bm;
1246 unsigned reg_safe_bm_size;
1247 u32 resync_scratch;
1248 u32 hdp_cntl;
1249};
1250
1251struct r600_asic {
1252 unsigned max_pipes;
1253 unsigned max_tile_pipes;
1254 unsigned max_simds;
1255 unsigned max_backends;
1256 unsigned max_gprs;
1257 unsigned max_threads;
1258 unsigned max_stack_entries;
1259 unsigned max_hw_contexts;
1260 unsigned max_gs_threads;
1261 unsigned sx_max_export_size;
1262 unsigned sx_max_export_pos_size;
1263 unsigned sx_max_export_smx_size;
1264 unsigned sq_num_cf_insts;
1265 unsigned tiling_nbanks;
1266 unsigned tiling_npipes;
1267 unsigned tiling_group_size;
1268 unsigned tile_config;
1269 unsigned backend_map;
1270};
1271
1272struct rv770_asic {
1273 unsigned max_pipes;
1274 unsigned max_tile_pipes;
1275 unsigned max_simds;
1276 unsigned max_backends;
1277 unsigned max_gprs;
1278 unsigned max_threads;
1279 unsigned max_stack_entries;
1280 unsigned max_hw_contexts;
1281 unsigned max_gs_threads;
1282 unsigned sx_max_export_size;
1283 unsigned sx_max_export_pos_size;
1284 unsigned sx_max_export_smx_size;
1285 unsigned sq_num_cf_insts;
1286 unsigned sx_num_of_sets;
1287 unsigned sc_prim_fifo_size;
1288 unsigned sc_hiz_tile_fifo_size;
1289 unsigned sc_earlyz_tile_fifo_fize;
1290 unsigned tiling_nbanks;
1291 unsigned tiling_npipes;
1292 unsigned tiling_group_size;
1293 unsigned tile_config;
1294 unsigned backend_map;
1295};
1296
1297struct evergreen_asic {
1298 unsigned num_ses;
1299 unsigned max_pipes;
1300 unsigned max_tile_pipes;
1301 unsigned max_simds;
1302 unsigned max_backends;
1303 unsigned max_gprs;
1304 unsigned max_threads;
1305 unsigned max_stack_entries;
1306 unsigned max_hw_contexts;
1307 unsigned max_gs_threads;
1308 unsigned sx_max_export_size;
1309 unsigned sx_max_export_pos_size;
1310 unsigned sx_max_export_smx_size;
1311 unsigned sq_num_cf_insts;
1312 unsigned sx_num_of_sets;
1313 unsigned sc_prim_fifo_size;
1314 unsigned sc_hiz_tile_fifo_size;
1315 unsigned sc_earlyz_tile_fifo_size;
1316 unsigned tiling_nbanks;
1317 unsigned tiling_npipes;
1318 unsigned tiling_group_size;
1319 unsigned tile_config;
1320 unsigned backend_map;
1321};
1322
1323struct cayman_asic {
1324 unsigned max_shader_engines;
1325 unsigned max_pipes_per_simd;
1326 unsigned max_tile_pipes;
1327 unsigned max_simds_per_se;
1328 unsigned max_backends_per_se;
1329 unsigned max_texture_channel_caches;
1330 unsigned max_gprs;
1331 unsigned max_threads;
1332 unsigned max_gs_threads;
1333 unsigned max_stack_entries;
1334 unsigned sx_num_of_sets;
1335 unsigned sx_max_export_size;
1336 unsigned sx_max_export_pos_size;
1337 unsigned sx_max_export_smx_size;
1338 unsigned max_hw_contexts;
1339 unsigned sq_num_cf_insts;
1340 unsigned sc_prim_fifo_size;
1341 unsigned sc_hiz_tile_fifo_size;
1342 unsigned sc_earlyz_tile_fifo_size;
1343
1344 unsigned num_shader_engines;
1345 unsigned num_shader_pipes_per_simd;
1346 unsigned num_tile_pipes;
1347 unsigned num_simds_per_se;
1348 unsigned num_backends_per_se;
1349 unsigned backend_disable_mask_per_asic;
1350 unsigned backend_map;
1351 unsigned num_texture_channel_caches;
1352 unsigned mem_max_burst_length_bytes;
1353 unsigned mem_row_size_in_kb;
1354 unsigned shader_engine_tile_size;
1355 unsigned num_gpus;
1356 unsigned multi_gpu_tile_size;
1357
1358 unsigned tile_config;
1359};
1360
1361struct si_asic {
1362 unsigned max_shader_engines;
1363 unsigned max_tile_pipes;
1364 unsigned max_cu_per_sh;
1365 unsigned max_sh_per_se;
1366 unsigned max_backends_per_se;
1367 unsigned max_texture_channel_caches;
1368 unsigned max_gprs;
1369 unsigned max_gs_threads;
1370 unsigned max_hw_contexts;
1371 unsigned sc_prim_fifo_size_frontend;
1372 unsigned sc_prim_fifo_size_backend;
1373 unsigned sc_hiz_tile_fifo_size;
1374 unsigned sc_earlyz_tile_fifo_size;
1375
1376 unsigned num_tile_pipes;
1377 unsigned num_backends_per_se;
1378 unsigned backend_disable_mask_per_asic;
1379 unsigned backend_map;
1380 unsigned num_texture_channel_caches;
1381 unsigned mem_max_burst_length_bytes;
1382 unsigned mem_row_size_in_kb;
1383 unsigned shader_engine_tile_size;
1384 unsigned num_gpus;
1385 unsigned multi_gpu_tile_size;
1386
1387 unsigned tile_config;
1388};
1389
1390union radeon_asic_config {
1391 struct r300_asic r300;
1392 struct r100_asic r100;
1393 struct r600_asic r600;
1394 struct rv770_asic rv770;
1395 struct evergreen_asic evergreen;
1396 struct cayman_asic cayman;
1397 struct si_asic si;
1398};
1399
1400/*
1401 * asic initizalization from radeon_asic.c
1402 */
1403void radeon_agp_disable(struct radeon_device *rdev);
1404int radeon_asic_init(struct radeon_device *rdev);
1405
1406
1407/*
1408 * IOCTL.
1409 */
1410int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1411 struct drm_file *filp);
1412int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1413 struct drm_file *filp);
1414int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1415 struct drm_file *file_priv);
1416int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1417 struct drm_file *file_priv);
1418int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1419 struct drm_file *file_priv);
1420int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1421 struct drm_file *file_priv);
1422int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1423 struct drm_file *filp);
1424int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1425 struct drm_file *filp);
1426int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1427 struct drm_file *filp);
1428int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1429 struct drm_file *filp);
1430int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1431 struct drm_file *filp);
1432int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1433int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1434 struct drm_file *filp);
1435int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1436 struct drm_file *filp);
1437
1438/* VRAM scratch page for HDP bug, default vram page */
1439struct r600_vram_scratch {
1440 struct radeon_bo *robj;
1441 volatile uint32_t *ptr;
1442 u64 gpu_addr;
1443};
1444
1445
1446/*
1447 * Core structure, functions and helpers.
1448 */
1449typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1450typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1451
1452struct radeon_device {
1453 struct device *dev;
1454 struct drm_device *ddev;
1455 struct pci_dev *pdev;
1456 /* ASIC */
1457 union radeon_asic_config config;
1458 enum radeon_family family;
1459 unsigned long flags;
1460 int usec_timeout;
1461 enum radeon_pll_errata pll_errata;
1462 int num_gb_pipes;
1463 int num_z_pipes;
1464 int disp_priority;
1465 /* BIOS */
1466 uint8_t *bios;
1467 bool is_atom_bios;
1468 uint16_t bios_header_start;
1469 struct radeon_bo *stollen_vga_memory;
1470 /* Register mmio */
1471 resource_size_t rmmio_base;
1472 resource_size_t rmmio_size;
1473 void __iomem *rmmio;
1474 radeon_rreg_t mc_rreg;
1475 radeon_wreg_t mc_wreg;
1476 radeon_rreg_t pll_rreg;
1477 radeon_wreg_t pll_wreg;
1478 uint32_t pcie_reg_mask;
1479 radeon_rreg_t pciep_rreg;
1480 radeon_wreg_t pciep_wreg;
1481 /* io port */
1482 void __iomem *rio_mem;
1483 resource_size_t rio_mem_size;
1484 struct radeon_clock clock;
1485 struct radeon_mc mc;
1486 struct radeon_gart gart;
1487 struct radeon_mode_info mode_info;
1488 struct radeon_scratch scratch;
1489 struct radeon_mman mman;
1490 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1491 wait_queue_head_t fence_queue;
1492 struct mutex ring_lock;
1493 struct radeon_ring ring[RADEON_NUM_RINGS];
1494 bool ib_pool_ready;
1495 struct radeon_sa_manager ring_tmp_bo;
1496 struct radeon_irq irq;
1497 struct radeon_asic *asic;
1498 struct radeon_gem gem;
1499 struct radeon_pm pm;
1500 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1501 struct radeon_mutex cs_mutex;
1502 struct radeon_wb wb;
1503 struct radeon_dummy_page dummy_page;
1504 bool shutdown;
1505 bool suspend;
1506 bool need_dma32;
1507 bool accel_working;
1508 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1509 const struct firmware *me_fw; /* all family ME firmware */
1510 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1511 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1512 const struct firmware *mc_fw; /* NI MC firmware */
1513 const struct firmware *ce_fw; /* SI CE firmware */
1514 struct r600_blit r600_blit;
1515 struct r600_vram_scratch vram_scratch;
1516 int msi_enabled; /* msi enabled */
1517 struct r600_ih ih; /* r6/700 interrupt ring */
1518 struct si_rlc rlc;
1519 struct work_struct hotplug_work;
1520 struct work_struct audio_work;
1521 int num_crtc; /* number of crtcs */
1522 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1523 struct mutex vram_mutex;
1524 bool audio_enabled;
1525 struct r600_audio audio_status; /* audio stuff */
1526 struct notifier_block acpi_nb;
1527 /* only one userspace can use Hyperz features or CMASK at a time */
1528 struct drm_file *hyperz_filp;
1529 struct drm_file *cmask_filp;
1530 /* i2c buses */
1531 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1532 /* debugfs */
1533 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1534 unsigned debugfs_count;
1535 /* virtual memory */
1536 struct radeon_vm_manager vm_manager;
1537};
1538
1539int radeon_device_init(struct radeon_device *rdev,
1540 struct drm_device *ddev,
1541 struct pci_dev *pdev,
1542 uint32_t flags);
1543void radeon_device_fini(struct radeon_device *rdev);
1544int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1545
1546uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1547void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1548u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1549void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1550
1551/*
1552 * Cast helper
1553 */
1554#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1555
1556/*
1557 * Registers read & write functions.
1558 */
1559#define RREG8(reg) readb((rdev->rmmio) + (reg))
1560#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1561#define RREG16(reg) readw((rdev->rmmio) + (reg))
1562#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1563#define RREG32(reg) r100_mm_rreg(rdev, (reg))
1564#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1565#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1566#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1567#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1568#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1569#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1570#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1571#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1572#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1573#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1574#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1575#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1576#define WREG32_P(reg, val, mask) \
1577 do { \
1578 uint32_t tmp_ = RREG32(reg); \
1579 tmp_ &= (mask); \
1580 tmp_ |= ((val) & ~(mask)); \
1581 WREG32(reg, tmp_); \
1582 } while (0)
1583#define WREG32_PLL_P(reg, val, mask) \
1584 do { \
1585 uint32_t tmp_ = RREG32_PLL(reg); \
1586 tmp_ &= (mask); \
1587 tmp_ |= ((val) & ~(mask)); \
1588 WREG32_PLL(reg, tmp_); \
1589 } while (0)
1590#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1591#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1592#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1593
1594/*
1595 * Indirect registers accessor
1596 */
1597static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1598{
1599 uint32_t r;
1600
1601 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1602 r = RREG32(RADEON_PCIE_DATA);
1603 return r;
1604}
1605
1606static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1607{
1608 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1609 WREG32(RADEON_PCIE_DATA, (v));
1610}
1611
1612void r100_pll_errata_after_index(struct radeon_device *rdev);
1613
1614
1615/*
1616 * ASICs helpers.
1617 */
1618#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1619 (rdev->pdev->device == 0x5969))
1620#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1621 (rdev->family == CHIP_RV200) || \
1622 (rdev->family == CHIP_RS100) || \
1623 (rdev->family == CHIP_RS200) || \
1624 (rdev->family == CHIP_RV250) || \
1625 (rdev->family == CHIP_RV280) || \
1626 (rdev->family == CHIP_RS300))
1627#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1628 (rdev->family == CHIP_RV350) || \
1629 (rdev->family == CHIP_R350) || \
1630 (rdev->family == CHIP_RV380) || \
1631 (rdev->family == CHIP_R420) || \
1632 (rdev->family == CHIP_R423) || \
1633 (rdev->family == CHIP_RV410) || \
1634 (rdev->family == CHIP_RS400) || \
1635 (rdev->family == CHIP_RS480))
1636#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1637 (rdev->ddev->pdev->device == 0x9443) || \
1638 (rdev->ddev->pdev->device == 0x944B) || \
1639 (rdev->ddev->pdev->device == 0x9506) || \
1640 (rdev->ddev->pdev->device == 0x9509) || \
1641 (rdev->ddev->pdev->device == 0x950F) || \
1642 (rdev->ddev->pdev->device == 0x689C) || \
1643 (rdev->ddev->pdev->device == 0x689D))
1644#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1645#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1646 (rdev->family == CHIP_RS690) || \
1647 (rdev->family == CHIP_RS740) || \
1648 (rdev->family >= CHIP_R600))
1649#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1650#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1651#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1652#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1653 (rdev->flags & RADEON_IS_IGP))
1654#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1655#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1656#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1657 (rdev->flags & RADEON_IS_IGP))
1658
1659/*
1660 * BIOS helpers.
1661 */
1662#define RBIOS8(i) (rdev->bios[i])
1663#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1664#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1665
1666int radeon_combios_init(struct radeon_device *rdev);
1667void radeon_combios_fini(struct radeon_device *rdev);
1668int radeon_atombios_init(struct radeon_device *rdev);
1669void radeon_atombios_fini(struct radeon_device *rdev);
1670
1671
1672/*
1673 * RING helpers.
1674 */
1675#if DRM_DEBUG_CODE == 0
1676static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1677{
1678 ring->ring[ring->wptr++] = v;
1679 ring->wptr &= ring->ptr_mask;
1680 ring->count_dw--;
1681 ring->ring_free_dw--;
1682}
1683#else
1684/* With debugging this is just too big to inline */
1685void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1686#endif
1687
1688/*
1689 * ASICs macro.
1690 */
1691#define radeon_init(rdev) (rdev)->asic->init((rdev))
1692#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1693#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1694#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1695#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1696#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1697#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1698#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
1699#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1700#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1701#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1702#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1703#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1704#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1705#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1706#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
1707#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1708#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1709#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1710#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1711#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
1712#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
1713#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
1714#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
1715#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
1716#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1717#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
1718#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
1719#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
1720#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
1721#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
1722#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
1723#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1724#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
1725#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1726#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1727#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
1728#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
1729#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
1730#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1731#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1732#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
1733#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
1734#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
1735#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
1736#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1737#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1738#define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1739#define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1740#define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1741#define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1742
1743/* Common functions */
1744/* AGP */
1745extern int radeon_gpu_reset(struct radeon_device *rdev);
1746extern void radeon_agp_disable(struct radeon_device *rdev);
1747extern int radeon_modeset_init(struct radeon_device *rdev);
1748extern void radeon_modeset_fini(struct radeon_device *rdev);
1749extern bool radeon_card_posted(struct radeon_device *rdev);
1750extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1751extern void radeon_update_display_priority(struct radeon_device *rdev);
1752extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1753extern void radeon_scratch_init(struct radeon_device *rdev);
1754extern void radeon_wb_fini(struct radeon_device *rdev);
1755extern int radeon_wb_init(struct radeon_device *rdev);
1756extern void radeon_wb_disable(struct radeon_device *rdev);
1757extern void radeon_surface_init(struct radeon_device *rdev);
1758extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1759extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1760extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1761extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1762extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1763extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1764extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1765extern int radeon_resume_kms(struct drm_device *dev);
1766extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1767extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1768
1769/*
1770 * vm
1771 */
1772int radeon_vm_manager_init(struct radeon_device *rdev);
1773void radeon_vm_manager_fini(struct radeon_device *rdev);
1774int radeon_vm_manager_start(struct radeon_device *rdev);
1775int radeon_vm_manager_suspend(struct radeon_device *rdev);
1776int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1777void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1778int radeon_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm);
1779void radeon_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm);
1780int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1781 struct radeon_vm *vm,
1782 struct radeon_bo *bo,
1783 struct ttm_mem_reg *mem);
1784void radeon_vm_bo_invalidate(struct radeon_device *rdev,
1785 struct radeon_bo *bo);
1786int radeon_vm_bo_add(struct radeon_device *rdev,
1787 struct radeon_vm *vm,
1788 struct radeon_bo *bo,
1789 uint64_t offset,
1790 uint32_t flags);
1791int radeon_vm_bo_rmv(struct radeon_device *rdev,
1792 struct radeon_vm *vm,
1793 struct radeon_bo *bo);
1794
1795/* audio */
1796void r600_audio_update_hdmi(struct work_struct *work);
1797
1798/*
1799 * R600 vram scratch functions
1800 */
1801int r600_vram_scratch_init(struct radeon_device *rdev);
1802void r600_vram_scratch_fini(struct radeon_device *rdev);
1803
1804/*
1805 * r600 cs checking helper
1806 */
1807unsigned r600_mip_minify(unsigned size, unsigned level);
1808bool r600_fmt_is_valid_color(u32 format);
1809bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
1810int r600_fmt_get_blocksize(u32 format);
1811int r600_fmt_get_nblocksx(u32 format, u32 w);
1812int r600_fmt_get_nblocksy(u32 format, u32 h);
1813
1814/*
1815 * r600 functions used by radeon_encoder.c
1816 */
1817struct radeon_hdmi_acr {
1818 u32 clock;
1819
1820 int n_32khz;
1821 int cts_32khz;
1822
1823 int n_44_1khz;
1824 int cts_44_1khz;
1825
1826 int n_48khz;
1827 int cts_48khz;
1828
1829};
1830
1831extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
1832
1833extern void r600_hdmi_enable(struct drm_encoder *encoder);
1834extern void r600_hdmi_disable(struct drm_encoder *encoder);
1835extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1836extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1837 u32 tiling_pipe_num,
1838 u32 max_rb_num,
1839 u32 total_max_rb_num,
1840 u32 enabled_rb_mask);
1841
1842/*
1843 * evergreen functions used by radeon_encoder.c
1844 */
1845
1846extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1847
1848extern int ni_init_microcode(struct radeon_device *rdev);
1849extern int ni_mc_load_microcode(struct radeon_device *rdev);
1850
1851/* radeon_acpi.c */
1852#if defined(CONFIG_ACPI)
1853extern int radeon_acpi_init(struct radeon_device *rdev);
1854#else
1855static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1856#endif
1857
1858#include "radeon_object.h"
1859
1860#endif