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1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include "drmP.h"
28#include "radeon.h"
29#include "radeon_asic.h"
30#include "radeon_drm.h"
31#include "nid.h"
32#include "atom.h"
33#include "ni_reg.h"
34#include "cayman_blit_shaders.h"
35
36extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
37extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
38extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
39extern void evergreen_mc_program(struct radeon_device *rdev);
40extern void evergreen_irq_suspend(struct radeon_device *rdev);
41extern int evergreen_mc_init(struct radeon_device *rdev);
42extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
43
44#define EVERGREEN_PFP_UCODE_SIZE 1120
45#define EVERGREEN_PM4_UCODE_SIZE 1376
46#define EVERGREEN_RLC_UCODE_SIZE 768
47#define BTC_MC_UCODE_SIZE 6024
48
49#define CAYMAN_PFP_UCODE_SIZE 2176
50#define CAYMAN_PM4_UCODE_SIZE 2176
51#define CAYMAN_RLC_UCODE_SIZE 1024
52#define CAYMAN_MC_UCODE_SIZE 6037
53
54/* Firmware Names */
55MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
56MODULE_FIRMWARE("radeon/BARTS_me.bin");
57MODULE_FIRMWARE("radeon/BARTS_mc.bin");
58MODULE_FIRMWARE("radeon/BTC_rlc.bin");
59MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
60MODULE_FIRMWARE("radeon/TURKS_me.bin");
61MODULE_FIRMWARE("radeon/TURKS_mc.bin");
62MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
63MODULE_FIRMWARE("radeon/CAICOS_me.bin");
64MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
65MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
66MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
67MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
68MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
69
70#define BTC_IO_MC_REGS_SIZE 29
71
72static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
73 {0x00000077, 0xff010100},
74 {0x00000078, 0x00000000},
75 {0x00000079, 0x00001434},
76 {0x0000007a, 0xcc08ec08},
77 {0x0000007b, 0x00040000},
78 {0x0000007c, 0x000080c0},
79 {0x0000007d, 0x09000000},
80 {0x0000007e, 0x00210404},
81 {0x00000081, 0x08a8e800},
82 {0x00000082, 0x00030444},
83 {0x00000083, 0x00000000},
84 {0x00000085, 0x00000001},
85 {0x00000086, 0x00000002},
86 {0x00000087, 0x48490000},
87 {0x00000088, 0x20244647},
88 {0x00000089, 0x00000005},
89 {0x0000008b, 0x66030000},
90 {0x0000008c, 0x00006603},
91 {0x0000008d, 0x00000100},
92 {0x0000008f, 0x00001c0a},
93 {0x00000090, 0xff000001},
94 {0x00000094, 0x00101101},
95 {0x00000095, 0x00000fff},
96 {0x00000096, 0x00116fff},
97 {0x00000097, 0x60010000},
98 {0x00000098, 0x10010000},
99 {0x00000099, 0x00006000},
100 {0x0000009a, 0x00001000},
101 {0x0000009f, 0x00946a00}
102};
103
104static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
105 {0x00000077, 0xff010100},
106 {0x00000078, 0x00000000},
107 {0x00000079, 0x00001434},
108 {0x0000007a, 0xcc08ec08},
109 {0x0000007b, 0x00040000},
110 {0x0000007c, 0x000080c0},
111 {0x0000007d, 0x09000000},
112 {0x0000007e, 0x00210404},
113 {0x00000081, 0x08a8e800},
114 {0x00000082, 0x00030444},
115 {0x00000083, 0x00000000},
116 {0x00000085, 0x00000001},
117 {0x00000086, 0x00000002},
118 {0x00000087, 0x48490000},
119 {0x00000088, 0x20244647},
120 {0x00000089, 0x00000005},
121 {0x0000008b, 0x66030000},
122 {0x0000008c, 0x00006603},
123 {0x0000008d, 0x00000100},
124 {0x0000008f, 0x00001c0a},
125 {0x00000090, 0xff000001},
126 {0x00000094, 0x00101101},
127 {0x00000095, 0x00000fff},
128 {0x00000096, 0x00116fff},
129 {0x00000097, 0x60010000},
130 {0x00000098, 0x10010000},
131 {0x00000099, 0x00006000},
132 {0x0000009a, 0x00001000},
133 {0x0000009f, 0x00936a00}
134};
135
136static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
137 {0x00000077, 0xff010100},
138 {0x00000078, 0x00000000},
139 {0x00000079, 0x00001434},
140 {0x0000007a, 0xcc08ec08},
141 {0x0000007b, 0x00040000},
142 {0x0000007c, 0x000080c0},
143 {0x0000007d, 0x09000000},
144 {0x0000007e, 0x00210404},
145 {0x00000081, 0x08a8e800},
146 {0x00000082, 0x00030444},
147 {0x00000083, 0x00000000},
148 {0x00000085, 0x00000001},
149 {0x00000086, 0x00000002},
150 {0x00000087, 0x48490000},
151 {0x00000088, 0x20244647},
152 {0x00000089, 0x00000005},
153 {0x0000008b, 0x66030000},
154 {0x0000008c, 0x00006603},
155 {0x0000008d, 0x00000100},
156 {0x0000008f, 0x00001c0a},
157 {0x00000090, 0xff000001},
158 {0x00000094, 0x00101101},
159 {0x00000095, 0x00000fff},
160 {0x00000096, 0x00116fff},
161 {0x00000097, 0x60010000},
162 {0x00000098, 0x10010000},
163 {0x00000099, 0x00006000},
164 {0x0000009a, 0x00001000},
165 {0x0000009f, 0x00916a00}
166};
167
168static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
169 {0x00000077, 0xff010100},
170 {0x00000078, 0x00000000},
171 {0x00000079, 0x00001434},
172 {0x0000007a, 0xcc08ec08},
173 {0x0000007b, 0x00040000},
174 {0x0000007c, 0x000080c0},
175 {0x0000007d, 0x09000000},
176 {0x0000007e, 0x00210404},
177 {0x00000081, 0x08a8e800},
178 {0x00000082, 0x00030444},
179 {0x00000083, 0x00000000},
180 {0x00000085, 0x00000001},
181 {0x00000086, 0x00000002},
182 {0x00000087, 0x48490000},
183 {0x00000088, 0x20244647},
184 {0x00000089, 0x00000005},
185 {0x0000008b, 0x66030000},
186 {0x0000008c, 0x00006603},
187 {0x0000008d, 0x00000100},
188 {0x0000008f, 0x00001c0a},
189 {0x00000090, 0xff000001},
190 {0x00000094, 0x00101101},
191 {0x00000095, 0x00000fff},
192 {0x00000096, 0x00116fff},
193 {0x00000097, 0x60010000},
194 {0x00000098, 0x10010000},
195 {0x00000099, 0x00006000},
196 {0x0000009a, 0x00001000},
197 {0x0000009f, 0x00976b00}
198};
199
200int ni_mc_load_microcode(struct radeon_device *rdev)
201{
202 const __be32 *fw_data;
203 u32 mem_type, running, blackout = 0;
204 u32 *io_mc_regs;
205 int i, ucode_size, regs_size;
206
207 if (!rdev->mc_fw)
208 return -EINVAL;
209
210 switch (rdev->family) {
211 case CHIP_BARTS:
212 io_mc_regs = (u32 *)&barts_io_mc_regs;
213 ucode_size = BTC_MC_UCODE_SIZE;
214 regs_size = BTC_IO_MC_REGS_SIZE;
215 break;
216 case CHIP_TURKS:
217 io_mc_regs = (u32 *)&turks_io_mc_regs;
218 ucode_size = BTC_MC_UCODE_SIZE;
219 regs_size = BTC_IO_MC_REGS_SIZE;
220 break;
221 case CHIP_CAICOS:
222 default:
223 io_mc_regs = (u32 *)&caicos_io_mc_regs;
224 ucode_size = BTC_MC_UCODE_SIZE;
225 regs_size = BTC_IO_MC_REGS_SIZE;
226 break;
227 case CHIP_CAYMAN:
228 io_mc_regs = (u32 *)&cayman_io_mc_regs;
229 ucode_size = CAYMAN_MC_UCODE_SIZE;
230 regs_size = BTC_IO_MC_REGS_SIZE;
231 break;
232 }
233
234 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
235 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
236
237 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
238 if (running) {
239 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
240 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
241 }
242
243 /* reset the engine and set to writable */
244 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
245 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
246
247 /* load mc io regs */
248 for (i = 0; i < regs_size; i++) {
249 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
250 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
251 }
252 /* load the MC ucode */
253 fw_data = (const __be32 *)rdev->mc_fw->data;
254 for (i = 0; i < ucode_size; i++)
255 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
256
257 /* put the engine back into the active state */
258 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
259 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
260 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
261
262 /* wait for training to complete */
263 while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD))
264 udelay(10);
265
266 if (running)
267 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
268 }
269
270 return 0;
271}
272
273int ni_init_microcode(struct radeon_device *rdev)
274{
275 struct platform_device *pdev;
276 const char *chip_name;
277 const char *rlc_chip_name;
278 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
279 char fw_name[30];
280 int err;
281
282 DRM_DEBUG("\n");
283
284 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
285 err = IS_ERR(pdev);
286 if (err) {
287 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
288 return -EINVAL;
289 }
290
291 switch (rdev->family) {
292 case CHIP_BARTS:
293 chip_name = "BARTS";
294 rlc_chip_name = "BTC";
295 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
296 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
297 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
298 mc_req_size = BTC_MC_UCODE_SIZE * 4;
299 break;
300 case CHIP_TURKS:
301 chip_name = "TURKS";
302 rlc_chip_name = "BTC";
303 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
304 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
305 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
306 mc_req_size = BTC_MC_UCODE_SIZE * 4;
307 break;
308 case CHIP_CAICOS:
309 chip_name = "CAICOS";
310 rlc_chip_name = "BTC";
311 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
312 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
313 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
314 mc_req_size = BTC_MC_UCODE_SIZE * 4;
315 break;
316 case CHIP_CAYMAN:
317 chip_name = "CAYMAN";
318 rlc_chip_name = "CAYMAN";
319 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
320 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
321 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
322 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
323 break;
324 default: BUG();
325 }
326
327 DRM_INFO("Loading %s Microcode\n", chip_name);
328
329 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
330 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
331 if (err)
332 goto out;
333 if (rdev->pfp_fw->size != pfp_req_size) {
334 printk(KERN_ERR
335 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
336 rdev->pfp_fw->size, fw_name);
337 err = -EINVAL;
338 goto out;
339 }
340
341 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
342 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
343 if (err)
344 goto out;
345 if (rdev->me_fw->size != me_req_size) {
346 printk(KERN_ERR
347 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
348 rdev->me_fw->size, fw_name);
349 err = -EINVAL;
350 }
351
352 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
353 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
354 if (err)
355 goto out;
356 if (rdev->rlc_fw->size != rlc_req_size) {
357 printk(KERN_ERR
358 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
359 rdev->rlc_fw->size, fw_name);
360 err = -EINVAL;
361 }
362
363 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
364 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
365 if (err)
366 goto out;
367 if (rdev->mc_fw->size != mc_req_size) {
368 printk(KERN_ERR
369 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
370 rdev->mc_fw->size, fw_name);
371 err = -EINVAL;
372 }
373out:
374 platform_device_unregister(pdev);
375
376 if (err) {
377 if (err != -EINVAL)
378 printk(KERN_ERR
379 "ni_cp: Failed to load firmware \"%s\"\n",
380 fw_name);
381 release_firmware(rdev->pfp_fw);
382 rdev->pfp_fw = NULL;
383 release_firmware(rdev->me_fw);
384 rdev->me_fw = NULL;
385 release_firmware(rdev->rlc_fw);
386 rdev->rlc_fw = NULL;
387 release_firmware(rdev->mc_fw);
388 rdev->mc_fw = NULL;
389 }
390 return err;
391}
392
393/*
394 * Core functions
395 */
396static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
397 u32 num_tile_pipes,
398 u32 num_backends_per_asic,
399 u32 *backend_disable_mask_per_asic,
400 u32 num_shader_engines)
401{
402 u32 backend_map = 0;
403 u32 enabled_backends_mask = 0;
404 u32 enabled_backends_count = 0;
405 u32 num_backends_per_se;
406 u32 cur_pipe;
407 u32 swizzle_pipe[CAYMAN_MAX_PIPES];
408 u32 cur_backend = 0;
409 u32 i;
410 bool force_no_swizzle;
411
412 /* force legal values */
413 if (num_tile_pipes < 1)
414 num_tile_pipes = 1;
415 if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
416 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
417 if (num_shader_engines < 1)
418 num_shader_engines = 1;
419 if (num_shader_engines > rdev->config.cayman.max_shader_engines)
420 num_shader_engines = rdev->config.cayman.max_shader_engines;
421 if (num_backends_per_asic < num_shader_engines)
422 num_backends_per_asic = num_shader_engines;
423 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
424 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
425
426 /* make sure we have the same number of backends per se */
427 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
428 /* set up the number of backends per se */
429 num_backends_per_se = num_backends_per_asic / num_shader_engines;
430 if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
431 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
432 num_backends_per_asic = num_backends_per_se * num_shader_engines;
433 }
434
435 /* create enable mask and count for enabled backends */
436 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
437 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
438 enabled_backends_mask |= (1 << i);
439 ++enabled_backends_count;
440 }
441 if (enabled_backends_count == num_backends_per_asic)
442 break;
443 }
444
445 /* force the backends mask to match the current number of backends */
446 if (enabled_backends_count != num_backends_per_asic) {
447 u32 this_backend_enabled;
448 u32 shader_engine;
449 u32 backend_per_se;
450
451 enabled_backends_mask = 0;
452 enabled_backends_count = 0;
453 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
454 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
455 /* calc the current se */
456 shader_engine = i / rdev->config.cayman.max_backends_per_se;
457 /* calc the backend per se */
458 backend_per_se = i % rdev->config.cayman.max_backends_per_se;
459 /* default to not enabled */
460 this_backend_enabled = 0;
461 if ((shader_engine < num_shader_engines) &&
462 (backend_per_se < num_backends_per_se))
463 this_backend_enabled = 1;
464 if (this_backend_enabled) {
465 enabled_backends_mask |= (1 << i);
466 *backend_disable_mask_per_asic &= ~(1 << i);
467 ++enabled_backends_count;
468 }
469 }
470 }
471
472
473 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
474 switch (rdev->family) {
475 case CHIP_CAYMAN:
476 force_no_swizzle = true;
477 break;
478 default:
479 force_no_swizzle = false;
480 break;
481 }
482 if (force_no_swizzle) {
483 bool last_backend_enabled = false;
484
485 force_no_swizzle = false;
486 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
487 if (((enabled_backends_mask >> i) & 1) == 1) {
488 if (last_backend_enabled)
489 force_no_swizzle = true;
490 last_backend_enabled = true;
491 } else
492 last_backend_enabled = false;
493 }
494 }
495
496 switch (num_tile_pipes) {
497 case 1:
498 case 3:
499 case 5:
500 case 7:
501 DRM_ERROR("odd number of pipes!\n");
502 break;
503 case 2:
504 swizzle_pipe[0] = 0;
505 swizzle_pipe[1] = 1;
506 break;
507 case 4:
508 if (force_no_swizzle) {
509 swizzle_pipe[0] = 0;
510 swizzle_pipe[1] = 1;
511 swizzle_pipe[2] = 2;
512 swizzle_pipe[3] = 3;
513 } else {
514 swizzle_pipe[0] = 0;
515 swizzle_pipe[1] = 2;
516 swizzle_pipe[2] = 1;
517 swizzle_pipe[3] = 3;
518 }
519 break;
520 case 6:
521 if (force_no_swizzle) {
522 swizzle_pipe[0] = 0;
523 swizzle_pipe[1] = 1;
524 swizzle_pipe[2] = 2;
525 swizzle_pipe[3] = 3;
526 swizzle_pipe[4] = 4;
527 swizzle_pipe[5] = 5;
528 } else {
529 swizzle_pipe[0] = 0;
530 swizzle_pipe[1] = 2;
531 swizzle_pipe[2] = 4;
532 swizzle_pipe[3] = 1;
533 swizzle_pipe[4] = 3;
534 swizzle_pipe[5] = 5;
535 }
536 break;
537 case 8:
538 if (force_no_swizzle) {
539 swizzle_pipe[0] = 0;
540 swizzle_pipe[1] = 1;
541 swizzle_pipe[2] = 2;
542 swizzle_pipe[3] = 3;
543 swizzle_pipe[4] = 4;
544 swizzle_pipe[5] = 5;
545 swizzle_pipe[6] = 6;
546 swizzle_pipe[7] = 7;
547 } else {
548 swizzle_pipe[0] = 0;
549 swizzle_pipe[1] = 2;
550 swizzle_pipe[2] = 4;
551 swizzle_pipe[3] = 6;
552 swizzle_pipe[4] = 1;
553 swizzle_pipe[5] = 3;
554 swizzle_pipe[6] = 5;
555 swizzle_pipe[7] = 7;
556 }
557 break;
558 }
559
560 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
561 while (((1 << cur_backend) & enabled_backends_mask) == 0)
562 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
563
564 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
565
566 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
567 }
568
569 return backend_map;
570}
571
572static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
573 u32 disable_mask_per_se,
574 u32 max_disable_mask_per_se,
575 u32 num_shader_engines)
576{
577 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
578 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
579
580 if (num_shader_engines == 1)
581 return disable_mask_per_asic;
582 else if (num_shader_engines == 2)
583 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
584 else
585 return 0xffffffff;
586}
587
588static void cayman_gpu_init(struct radeon_device *rdev)
589{
590 u32 cc_rb_backend_disable = 0;
591 u32 cc_gc_shader_pipe_config;
592 u32 gb_addr_config = 0;
593 u32 mc_shared_chmap, mc_arb_ramcfg;
594 u32 gb_backend_map;
595 u32 cgts_tcc_disable;
596 u32 sx_debug_1;
597 u32 smx_dc_ctl0;
598 u32 gc_user_shader_pipe_config;
599 u32 gc_user_rb_backend_disable;
600 u32 cgts_user_tcc_disable;
601 u32 cgts_sm_ctrl_reg;
602 u32 hdp_host_path_cntl;
603 u32 tmp;
604 int i, j;
605
606 switch (rdev->family) {
607 case CHIP_CAYMAN:
608 default:
609 rdev->config.cayman.max_shader_engines = 2;
610 rdev->config.cayman.max_pipes_per_simd = 4;
611 rdev->config.cayman.max_tile_pipes = 8;
612 rdev->config.cayman.max_simds_per_se = 12;
613 rdev->config.cayman.max_backends_per_se = 4;
614 rdev->config.cayman.max_texture_channel_caches = 8;
615 rdev->config.cayman.max_gprs = 256;
616 rdev->config.cayman.max_threads = 256;
617 rdev->config.cayman.max_gs_threads = 32;
618 rdev->config.cayman.max_stack_entries = 512;
619 rdev->config.cayman.sx_num_of_sets = 8;
620 rdev->config.cayman.sx_max_export_size = 256;
621 rdev->config.cayman.sx_max_export_pos_size = 64;
622 rdev->config.cayman.sx_max_export_smx_size = 192;
623 rdev->config.cayman.max_hw_contexts = 8;
624 rdev->config.cayman.sq_num_cf_insts = 2;
625
626 rdev->config.cayman.sc_prim_fifo_size = 0x100;
627 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
628 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
629 break;
630 }
631
632 /* Initialize HDP */
633 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
634 WREG32((0x2c14 + j), 0x00000000);
635 WREG32((0x2c18 + j), 0x00000000);
636 WREG32((0x2c1c + j), 0x00000000);
637 WREG32((0x2c20 + j), 0x00000000);
638 WREG32((0x2c24 + j), 0x00000000);
639 }
640
641 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
642
643 evergreen_fix_pci_max_read_req_size(rdev);
644
645 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
646 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
647
648 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
649 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
650 cgts_tcc_disable = 0xff000000;
651 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
652 gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
653 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
654
655 rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
656 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
657 rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
658 rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
659 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
660 rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
661 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
662 rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
663 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
664 rdev->config.cayman.backend_disable_mask_per_asic =
665 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
666 rdev->config.cayman.num_shader_engines);
667 rdev->config.cayman.backend_map =
668 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
669 rdev->config.cayman.num_backends_per_se *
670 rdev->config.cayman.num_shader_engines,
671 &rdev->config.cayman.backend_disable_mask_per_asic,
672 rdev->config.cayman.num_shader_engines);
673 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
674 rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
675 tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
676 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
677 if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
678 rdev->config.cayman.mem_max_burst_length_bytes = 512;
679 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
680 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
681 if (rdev->config.cayman.mem_row_size_in_kb > 4)
682 rdev->config.cayman.mem_row_size_in_kb = 4;
683 /* XXX use MC settings? */
684 rdev->config.cayman.shader_engine_tile_size = 32;
685 rdev->config.cayman.num_gpus = 1;
686 rdev->config.cayman.multi_gpu_tile_size = 64;
687
688 //gb_addr_config = 0x02011003
689#if 0
690 gb_addr_config = RREG32(GB_ADDR_CONFIG);
691#else
692 gb_addr_config = 0;
693 switch (rdev->config.cayman.num_tile_pipes) {
694 case 1:
695 default:
696 gb_addr_config |= NUM_PIPES(0);
697 break;
698 case 2:
699 gb_addr_config |= NUM_PIPES(1);
700 break;
701 case 4:
702 gb_addr_config |= NUM_PIPES(2);
703 break;
704 case 8:
705 gb_addr_config |= NUM_PIPES(3);
706 break;
707 }
708
709 tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
710 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
711 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
712 tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
713 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
714 switch (rdev->config.cayman.num_gpus) {
715 case 1:
716 default:
717 gb_addr_config |= NUM_GPUS(0);
718 break;
719 case 2:
720 gb_addr_config |= NUM_GPUS(1);
721 break;
722 case 4:
723 gb_addr_config |= NUM_GPUS(2);
724 break;
725 }
726 switch (rdev->config.cayman.multi_gpu_tile_size) {
727 case 16:
728 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
729 break;
730 case 32:
731 default:
732 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
733 break;
734 case 64:
735 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
736 break;
737 case 128:
738 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
739 break;
740 }
741 switch (rdev->config.cayman.mem_row_size_in_kb) {
742 case 1:
743 default:
744 gb_addr_config |= ROW_SIZE(0);
745 break;
746 case 2:
747 gb_addr_config |= ROW_SIZE(1);
748 break;
749 case 4:
750 gb_addr_config |= ROW_SIZE(2);
751 break;
752 }
753#endif
754
755 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
756 rdev->config.cayman.num_tile_pipes = (1 << tmp);
757 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
758 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
759 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
760 rdev->config.cayman.num_shader_engines = tmp + 1;
761 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
762 rdev->config.cayman.num_gpus = tmp + 1;
763 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
764 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
765 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
766 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
767
768 //gb_backend_map = 0x76541032;
769#if 0
770 gb_backend_map = RREG32(GB_BACKEND_MAP);
771#else
772 gb_backend_map =
773 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
774 rdev->config.cayman.num_backends_per_se *
775 rdev->config.cayman.num_shader_engines,
776 &rdev->config.cayman.backend_disable_mask_per_asic,
777 rdev->config.cayman.num_shader_engines);
778#endif
779 /* setup tiling info dword. gb_addr_config is not adequate since it does
780 * not have bank info, so create a custom tiling dword.
781 * bits 3:0 num_pipes
782 * bits 7:4 num_banks
783 * bits 11:8 group_size
784 * bits 15:12 row_size
785 */
786 rdev->config.cayman.tile_config = 0;
787 switch (rdev->config.cayman.num_tile_pipes) {
788 case 1:
789 default:
790 rdev->config.cayman.tile_config |= (0 << 0);
791 break;
792 case 2:
793 rdev->config.cayman.tile_config |= (1 << 0);
794 break;
795 case 4:
796 rdev->config.cayman.tile_config |= (2 << 0);
797 break;
798 case 8:
799 rdev->config.cayman.tile_config |= (3 << 0);
800 break;
801 }
802 rdev->config.cayman.tile_config |=
803 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
804 rdev->config.cayman.tile_config |=
805 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
806 rdev->config.cayman.tile_config |=
807 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
808
809 rdev->config.cayman.backend_map = gb_backend_map;
810 WREG32(GB_BACKEND_MAP, gb_backend_map);
811 WREG32(GB_ADDR_CONFIG, gb_addr_config);
812 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
813 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
814
815 /* primary versions */
816 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
817 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
818 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
819
820 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
821 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
822
823 /* user versions */
824 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
825 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
826 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
827
828 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
829 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
830
831 /* reprogram the shader complex */
832 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
833 for (i = 0; i < 16; i++)
834 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
835 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
836
837 /* set HW defaults for 3D engine */
838 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
839
840 sx_debug_1 = RREG32(SX_DEBUG_1);
841 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
842 WREG32(SX_DEBUG_1, sx_debug_1);
843
844 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
845 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
846 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
847 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
848
849 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
850
851 /* need to be explicitly zero-ed */
852 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
853 WREG32(SQ_LSTMP_RING_BASE, 0);
854 WREG32(SQ_HSTMP_RING_BASE, 0);
855 WREG32(SQ_ESTMP_RING_BASE, 0);
856 WREG32(SQ_GSTMP_RING_BASE, 0);
857 WREG32(SQ_VSTMP_RING_BASE, 0);
858 WREG32(SQ_PSTMP_RING_BASE, 0);
859
860 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
861
862 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
863 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
864 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
865
866 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
867 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
868 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
869
870
871 WREG32(VGT_NUM_INSTANCES, 1);
872
873 WREG32(CP_PERFMON_CNTL, 0);
874
875 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
876 FETCH_FIFO_HIWATER(0x4) |
877 DONE_FIFO_HIWATER(0xe0) |
878 ALU_UPDATE_FIFO_HIWATER(0x8)));
879
880 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
881 WREG32(SQ_CONFIG, (VC_ENABLE |
882 EXPORT_SRC_C |
883 GFX_PRIO(0) |
884 CS1_PRIO(0) |
885 CS2_PRIO(1)));
886 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
887
888 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
889 FORCE_EOV_MAX_REZ_CNT(255)));
890
891 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
892 AUTO_INVLD_EN(ES_AND_GS_AUTO));
893
894 WREG32(VGT_GS_VERTEX_REUSE, 16);
895 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
896
897 WREG32(CB_PERF_CTR0_SEL_0, 0);
898 WREG32(CB_PERF_CTR0_SEL_1, 0);
899 WREG32(CB_PERF_CTR1_SEL_0, 0);
900 WREG32(CB_PERF_CTR1_SEL_1, 0);
901 WREG32(CB_PERF_CTR2_SEL_0, 0);
902 WREG32(CB_PERF_CTR2_SEL_1, 0);
903 WREG32(CB_PERF_CTR3_SEL_0, 0);
904 WREG32(CB_PERF_CTR3_SEL_1, 0);
905
906 tmp = RREG32(HDP_MISC_CNTL);
907 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
908 WREG32(HDP_MISC_CNTL, tmp);
909
910 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
911 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
912
913 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
914
915 udelay(50);
916}
917
918/*
919 * GART
920 */
921void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
922{
923 /* flush hdp cache */
924 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
925
926 /* bits 0-7 are the VM contexts0-7 */
927 WREG32(VM_INVALIDATE_REQUEST, 1);
928}
929
930int cayman_pcie_gart_enable(struct radeon_device *rdev)
931{
932 int r;
933
934 if (rdev->gart.table.vram.robj == NULL) {
935 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
936 return -EINVAL;
937 }
938 r = radeon_gart_table_vram_pin(rdev);
939 if (r)
940 return r;
941 radeon_gart_restore(rdev);
942 /* Setup TLB control */
943 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB |
944 ENABLE_L1_FRAGMENT_PROCESSING |
945 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
946 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
947 /* Setup L2 cache */
948 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
949 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
950 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
951 EFFECTIVE_L2_QUEUE_SIZE(7) |
952 CONTEXT1_IDENTITY_ACCESS_MODE(1));
953 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
954 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
955 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
956 /* setup context0 */
957 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
958 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
959 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
960 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
961 (u32)(rdev->dummy_page.addr >> 12));
962 WREG32(VM_CONTEXT0_CNTL2, 0);
963 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
964 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
965 /* disable context1-7 */
966 WREG32(VM_CONTEXT1_CNTL2, 0);
967 WREG32(VM_CONTEXT1_CNTL, 0);
968
969 cayman_pcie_gart_tlb_flush(rdev);
970 rdev->gart.ready = true;
971 return 0;
972}
973
974void cayman_pcie_gart_disable(struct radeon_device *rdev)
975{
976 int r;
977
978 /* Disable all tables */
979 WREG32(VM_CONTEXT0_CNTL, 0);
980 WREG32(VM_CONTEXT1_CNTL, 0);
981 /* Setup TLB control */
982 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
983 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
984 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
985 /* Setup L2 cache */
986 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
987 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
988 EFFECTIVE_L2_QUEUE_SIZE(7) |
989 CONTEXT1_IDENTITY_ACCESS_MODE(1));
990 WREG32(VM_L2_CNTL2, 0);
991 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
992 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
993 if (rdev->gart.table.vram.robj) {
994 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
995 if (likely(r == 0)) {
996 radeon_bo_kunmap(rdev->gart.table.vram.robj);
997 radeon_bo_unpin(rdev->gart.table.vram.robj);
998 radeon_bo_unreserve(rdev->gart.table.vram.robj);
999 }
1000 }
1001}
1002
1003void cayman_pcie_gart_fini(struct radeon_device *rdev)
1004{
1005 cayman_pcie_gart_disable(rdev);
1006 radeon_gart_table_vram_free(rdev);
1007 radeon_gart_fini(rdev);
1008}
1009
1010/*
1011 * CP.
1012 */
1013static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1014{
1015 if (enable)
1016 WREG32(CP_ME_CNTL, 0);
1017 else {
1018 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1019 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1020 WREG32(SCRATCH_UMSK, 0);
1021 }
1022}
1023
1024static int cayman_cp_load_microcode(struct radeon_device *rdev)
1025{
1026 const __be32 *fw_data;
1027 int i;
1028
1029 if (!rdev->me_fw || !rdev->pfp_fw)
1030 return -EINVAL;
1031
1032 cayman_cp_enable(rdev, false);
1033
1034 fw_data = (const __be32 *)rdev->pfp_fw->data;
1035 WREG32(CP_PFP_UCODE_ADDR, 0);
1036 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1037 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1038 WREG32(CP_PFP_UCODE_ADDR, 0);
1039
1040 fw_data = (const __be32 *)rdev->me_fw->data;
1041 WREG32(CP_ME_RAM_WADDR, 0);
1042 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1043 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1044
1045 WREG32(CP_PFP_UCODE_ADDR, 0);
1046 WREG32(CP_ME_RAM_WADDR, 0);
1047 WREG32(CP_ME_RAM_RADDR, 0);
1048 return 0;
1049}
1050
1051static int cayman_cp_start(struct radeon_device *rdev)
1052{
1053 int r, i;
1054
1055 r = radeon_ring_lock(rdev, 7);
1056 if (r) {
1057 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1058 return r;
1059 }
1060 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1061 radeon_ring_write(rdev, 0x1);
1062 radeon_ring_write(rdev, 0x0);
1063 radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1);
1064 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1065 radeon_ring_write(rdev, 0);
1066 radeon_ring_write(rdev, 0);
1067 radeon_ring_unlock_commit(rdev);
1068
1069 cayman_cp_enable(rdev, true);
1070
1071 r = radeon_ring_lock(rdev, cayman_default_size + 19);
1072 if (r) {
1073 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1074 return r;
1075 }
1076
1077 /* setup clear context state */
1078 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1079 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1080
1081 for (i = 0; i < cayman_default_size; i++)
1082 radeon_ring_write(rdev, cayman_default_state[i]);
1083
1084 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1085 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1086
1087 /* set clear context state */
1088 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1089 radeon_ring_write(rdev, 0);
1090
1091 /* SQ_VTX_BASE_VTX_LOC */
1092 radeon_ring_write(rdev, 0xc0026f00);
1093 radeon_ring_write(rdev, 0x00000000);
1094 radeon_ring_write(rdev, 0x00000000);
1095 radeon_ring_write(rdev, 0x00000000);
1096
1097 /* Clear consts */
1098 radeon_ring_write(rdev, 0xc0036f00);
1099 radeon_ring_write(rdev, 0x00000bc4);
1100 radeon_ring_write(rdev, 0xffffffff);
1101 radeon_ring_write(rdev, 0xffffffff);
1102 radeon_ring_write(rdev, 0xffffffff);
1103
1104 radeon_ring_write(rdev, 0xc0026900);
1105 radeon_ring_write(rdev, 0x00000316);
1106 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1107 radeon_ring_write(rdev, 0x00000010); /* */
1108
1109 radeon_ring_unlock_commit(rdev);
1110
1111 /* XXX init other rings */
1112
1113 return 0;
1114}
1115
1116static void cayman_cp_fini(struct radeon_device *rdev)
1117{
1118 cayman_cp_enable(rdev, false);
1119 radeon_ring_fini(rdev);
1120}
1121
1122int cayman_cp_resume(struct radeon_device *rdev)
1123{
1124 u32 tmp;
1125 u32 rb_bufsz;
1126 int r;
1127
1128 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1129 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1130 SOFT_RESET_PA |
1131 SOFT_RESET_SH |
1132 SOFT_RESET_VGT |
1133 SOFT_RESET_SPI |
1134 SOFT_RESET_SX));
1135 RREG32(GRBM_SOFT_RESET);
1136 mdelay(15);
1137 WREG32(GRBM_SOFT_RESET, 0);
1138 RREG32(GRBM_SOFT_RESET);
1139
1140 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1141
1142 /* Set the write pointer delay */
1143 WREG32(CP_RB_WPTR_DELAY, 0);
1144
1145 WREG32(CP_DEBUG, (1 << 27));
1146
1147 /* ring 0 - compute and gfx */
1148 /* Set ring buffer size */
1149 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1150 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1151#ifdef __BIG_ENDIAN
1152 tmp |= BUF_SWAP_32BIT;
1153#endif
1154 WREG32(CP_RB0_CNTL, tmp);
1155
1156 /* Initialize the ring buffer's read and write pointers */
1157 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1158 rdev->cp.wptr = 0;
1159 WREG32(CP_RB0_WPTR, rdev->cp.wptr);
1160
1161 /* set the wb address wether it's enabled or not */
1162 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1163 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1164 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1165
1166 if (rdev->wb.enabled)
1167 WREG32(SCRATCH_UMSK, 0xff);
1168 else {
1169 tmp |= RB_NO_UPDATE;
1170 WREG32(SCRATCH_UMSK, 0);
1171 }
1172
1173 mdelay(1);
1174 WREG32(CP_RB0_CNTL, tmp);
1175
1176 WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);
1177
1178 rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1179
1180 /* ring1 - compute only */
1181 /* Set ring buffer size */
1182 rb_bufsz = drm_order(rdev->cp1.ring_size / 8);
1183 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1184#ifdef __BIG_ENDIAN
1185 tmp |= BUF_SWAP_32BIT;
1186#endif
1187 WREG32(CP_RB1_CNTL, tmp);
1188
1189 /* Initialize the ring buffer's read and write pointers */
1190 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1191 rdev->cp1.wptr = 0;
1192 WREG32(CP_RB1_WPTR, rdev->cp1.wptr);
1193
1194 /* set the wb address wether it's enabled or not */
1195 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1196 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1197
1198 mdelay(1);
1199 WREG32(CP_RB1_CNTL, tmp);
1200
1201 WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);
1202
1203 rdev->cp1.rptr = RREG32(CP_RB1_RPTR);
1204
1205 /* ring2 - compute only */
1206 /* Set ring buffer size */
1207 rb_bufsz = drm_order(rdev->cp2.ring_size / 8);
1208 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1209#ifdef __BIG_ENDIAN
1210 tmp |= BUF_SWAP_32BIT;
1211#endif
1212 WREG32(CP_RB2_CNTL, tmp);
1213
1214 /* Initialize the ring buffer's read and write pointers */
1215 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1216 rdev->cp2.wptr = 0;
1217 WREG32(CP_RB2_WPTR, rdev->cp2.wptr);
1218
1219 /* set the wb address wether it's enabled or not */
1220 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1221 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1222
1223 mdelay(1);
1224 WREG32(CP_RB2_CNTL, tmp);
1225
1226 WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);
1227
1228 rdev->cp2.rptr = RREG32(CP_RB2_RPTR);
1229
1230 /* start the rings */
1231 cayman_cp_start(rdev);
1232 rdev->cp.ready = true;
1233 rdev->cp1.ready = true;
1234 rdev->cp2.ready = true;
1235 /* this only test cp0 */
1236 r = radeon_ring_test(rdev);
1237 if (r) {
1238 rdev->cp.ready = false;
1239 rdev->cp1.ready = false;
1240 rdev->cp2.ready = false;
1241 return r;
1242 }
1243
1244 return 0;
1245}
1246
1247bool cayman_gpu_is_lockup(struct radeon_device *rdev)
1248{
1249 u32 srbm_status;
1250 u32 grbm_status;
1251 u32 grbm_status_se0, grbm_status_se1;
1252 struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup;
1253 int r;
1254
1255 srbm_status = RREG32(SRBM_STATUS);
1256 grbm_status = RREG32(GRBM_STATUS);
1257 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1258 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1259 if (!(grbm_status & GUI_ACTIVE)) {
1260 r100_gpu_lockup_update(lockup, &rdev->cp);
1261 return false;
1262 }
1263 /* force CP activities */
1264 r = radeon_ring_lock(rdev, 2);
1265 if (!r) {
1266 /* PACKET2 NOP */
1267 radeon_ring_write(rdev, 0x80000000);
1268 radeon_ring_write(rdev, 0x80000000);
1269 radeon_ring_unlock_commit(rdev);
1270 }
1271 /* XXX deal with CP0,1,2 */
1272 rdev->cp.rptr = RREG32(CP_RB0_RPTR);
1273 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1274}
1275
1276static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1277{
1278 struct evergreen_mc_save save;
1279 u32 grbm_reset = 0;
1280
1281 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1282 return 0;
1283
1284 dev_info(rdev->dev, "GPU softreset \n");
1285 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1286 RREG32(GRBM_STATUS));
1287 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1288 RREG32(GRBM_STATUS_SE0));
1289 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1290 RREG32(GRBM_STATUS_SE1));
1291 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1292 RREG32(SRBM_STATUS));
1293 evergreen_mc_stop(rdev, &save);
1294 if (evergreen_mc_wait_for_idle(rdev)) {
1295 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1296 }
1297 /* Disable CP parsing/prefetching */
1298 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1299
1300 /* reset all the gfx blocks */
1301 grbm_reset = (SOFT_RESET_CP |
1302 SOFT_RESET_CB |
1303 SOFT_RESET_DB |
1304 SOFT_RESET_GDS |
1305 SOFT_RESET_PA |
1306 SOFT_RESET_SC |
1307 SOFT_RESET_SPI |
1308 SOFT_RESET_SH |
1309 SOFT_RESET_SX |
1310 SOFT_RESET_TC |
1311 SOFT_RESET_TA |
1312 SOFT_RESET_VGT |
1313 SOFT_RESET_IA);
1314
1315 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1316 WREG32(GRBM_SOFT_RESET, grbm_reset);
1317 (void)RREG32(GRBM_SOFT_RESET);
1318 udelay(50);
1319 WREG32(GRBM_SOFT_RESET, 0);
1320 (void)RREG32(GRBM_SOFT_RESET);
1321 /* Wait a little for things to settle down */
1322 udelay(50);
1323 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1324 RREG32(GRBM_STATUS));
1325 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1326 RREG32(GRBM_STATUS_SE0));
1327 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1328 RREG32(GRBM_STATUS_SE1));
1329 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1330 RREG32(SRBM_STATUS));
1331 evergreen_mc_resume(rdev, &save);
1332 return 0;
1333}
1334
1335int cayman_asic_reset(struct radeon_device *rdev)
1336{
1337 return cayman_gpu_soft_reset(rdev);
1338}
1339
1340static int cayman_startup(struct radeon_device *rdev)
1341{
1342 int r;
1343
1344 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1345 r = ni_init_microcode(rdev);
1346 if (r) {
1347 DRM_ERROR("Failed to load firmware!\n");
1348 return r;
1349 }
1350 }
1351 r = ni_mc_load_microcode(rdev);
1352 if (r) {
1353 DRM_ERROR("Failed to load MC firmware!\n");
1354 return r;
1355 }
1356
1357 evergreen_mc_program(rdev);
1358 r = cayman_pcie_gart_enable(rdev);
1359 if (r)
1360 return r;
1361 cayman_gpu_init(rdev);
1362
1363 r = evergreen_blit_init(rdev);
1364 if (r) {
1365 evergreen_blit_fini(rdev);
1366 rdev->asic->copy = NULL;
1367 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1368 }
1369
1370 /* allocate wb buffer */
1371 r = radeon_wb_init(rdev);
1372 if (r)
1373 return r;
1374
1375 /* Enable IRQ */
1376 r = r600_irq_init(rdev);
1377 if (r) {
1378 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1379 radeon_irq_kms_fini(rdev);
1380 return r;
1381 }
1382 evergreen_irq_set(rdev);
1383
1384 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1385 if (r)
1386 return r;
1387 r = cayman_cp_load_microcode(rdev);
1388 if (r)
1389 return r;
1390 r = cayman_cp_resume(rdev);
1391 if (r)
1392 return r;
1393
1394 return 0;
1395}
1396
1397int cayman_resume(struct radeon_device *rdev)
1398{
1399 int r;
1400
1401 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1402 * posting will perform necessary task to bring back GPU into good
1403 * shape.
1404 */
1405 /* post card */
1406 atom_asic_init(rdev->mode_info.atom_context);
1407
1408 r = cayman_startup(rdev);
1409 if (r) {
1410 DRM_ERROR("cayman startup failed on resume\n");
1411 return r;
1412 }
1413
1414 r = r600_ib_test(rdev);
1415 if (r) {
1416 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1417 return r;
1418 }
1419
1420 return r;
1421
1422}
1423
1424int cayman_suspend(struct radeon_device *rdev)
1425{
1426 int r;
1427
1428 /* FIXME: we should wait for ring to be empty */
1429 cayman_cp_enable(rdev, false);
1430 rdev->cp.ready = false;
1431 evergreen_irq_suspend(rdev);
1432 radeon_wb_disable(rdev);
1433 cayman_pcie_gart_disable(rdev);
1434
1435 /* unpin shaders bo */
1436 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1437 if (likely(r == 0)) {
1438 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1439 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1440 }
1441
1442 return 0;
1443}
1444
1445/* Plan is to move initialization in that function and use
1446 * helper function so that radeon_device_init pretty much
1447 * do nothing more than calling asic specific function. This
1448 * should also allow to remove a bunch of callback function
1449 * like vram_info.
1450 */
1451int cayman_init(struct radeon_device *rdev)
1452{
1453 int r;
1454
1455 /* This don't do much */
1456 r = radeon_gem_init(rdev);
1457 if (r)
1458 return r;
1459 /* Read BIOS */
1460 if (!radeon_get_bios(rdev)) {
1461 if (ASIC_IS_AVIVO(rdev))
1462 return -EINVAL;
1463 }
1464 /* Must be an ATOMBIOS */
1465 if (!rdev->is_atom_bios) {
1466 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1467 return -EINVAL;
1468 }
1469 r = radeon_atombios_init(rdev);
1470 if (r)
1471 return r;
1472
1473 /* Post card if necessary */
1474 if (!radeon_card_posted(rdev)) {
1475 if (!rdev->bios) {
1476 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1477 return -EINVAL;
1478 }
1479 DRM_INFO("GPU not posted. posting now...\n");
1480 atom_asic_init(rdev->mode_info.atom_context);
1481 }
1482 /* Initialize scratch registers */
1483 r600_scratch_init(rdev);
1484 /* Initialize surface registers */
1485 radeon_surface_init(rdev);
1486 /* Initialize clocks */
1487 radeon_get_clock_info(rdev->ddev);
1488 /* Fence driver */
1489 r = radeon_fence_driver_init(rdev);
1490 if (r)
1491 return r;
1492 /* initialize memory controller */
1493 r = evergreen_mc_init(rdev);
1494 if (r)
1495 return r;
1496 /* Memory manager */
1497 r = radeon_bo_init(rdev);
1498 if (r)
1499 return r;
1500
1501 r = radeon_irq_kms_init(rdev);
1502 if (r)
1503 return r;
1504
1505 rdev->cp.ring_obj = NULL;
1506 r600_ring_init(rdev, 1024 * 1024);
1507
1508 rdev->ih.ring_obj = NULL;
1509 r600_ih_ring_init(rdev, 64 * 1024);
1510
1511 r = r600_pcie_gart_init(rdev);
1512 if (r)
1513 return r;
1514
1515 rdev->accel_working = true;
1516 r = cayman_startup(rdev);
1517 if (r) {
1518 dev_err(rdev->dev, "disabling GPU acceleration\n");
1519 cayman_cp_fini(rdev);
1520 r600_irq_fini(rdev);
1521 radeon_wb_fini(rdev);
1522 radeon_irq_kms_fini(rdev);
1523 cayman_pcie_gart_fini(rdev);
1524 rdev->accel_working = false;
1525 }
1526 if (rdev->accel_working) {
1527 r = radeon_ib_pool_init(rdev);
1528 if (r) {
1529 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
1530 rdev->accel_working = false;
1531 }
1532 r = r600_ib_test(rdev);
1533 if (r) {
1534 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1535 rdev->accel_working = false;
1536 }
1537 }
1538
1539 /* Don't start up if the MC ucode is missing.
1540 * The default clocks and voltages before the MC ucode
1541 * is loaded are not suffient for advanced operations.
1542 */
1543 if (!rdev->mc_fw) {
1544 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1545 return -EINVAL;
1546 }
1547
1548 return 0;
1549}
1550
1551void cayman_fini(struct radeon_device *rdev)
1552{
1553 evergreen_blit_fini(rdev);
1554 cayman_cp_fini(rdev);
1555 r600_irq_fini(rdev);
1556 radeon_wb_fini(rdev);
1557 radeon_ib_pool_fini(rdev);
1558 radeon_irq_kms_fini(rdev);
1559 cayman_pcie_gart_fini(rdev);
1560 radeon_gem_fini(rdev);
1561 radeon_fence_driver_fini(rdev);
1562 radeon_bo_fini(rdev);
1563 radeon_atombios_fini(rdev);
1564 kfree(rdev->bios);
1565 rdev->bios = NULL;
1566}
1567
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <drm/drmP.h>
28#include "radeon.h"
29#include "radeon_asic.h"
30#include <drm/radeon_drm.h>
31#include "nid.h"
32#include "atom.h"
33#include "ni_reg.h"
34#include "cayman_blit_shaders.h"
35#include "radeon_ucode.h"
36#include "clearstate_cayman.h"
37
38static const u32 tn_rlc_save_restore_register_list[] =
39{
40 0x98fc,
41 0x98f0,
42 0x9834,
43 0x9838,
44 0x9870,
45 0x9874,
46 0x8a14,
47 0x8b24,
48 0x8bcc,
49 0x8b10,
50 0x8c30,
51 0x8d00,
52 0x8d04,
53 0x8c00,
54 0x8c04,
55 0x8c10,
56 0x8c14,
57 0x8d8c,
58 0x8cf0,
59 0x8e38,
60 0x9508,
61 0x9688,
62 0x9608,
63 0x960c,
64 0x9610,
65 0x9614,
66 0x88c4,
67 0x8978,
68 0x88d4,
69 0x900c,
70 0x9100,
71 0x913c,
72 0x90e8,
73 0x9354,
74 0xa008,
75 0x98f8,
76 0x9148,
77 0x914c,
78 0x3f94,
79 0x98f4,
80 0x9b7c,
81 0x3f8c,
82 0x8950,
83 0x8954,
84 0x8a18,
85 0x8b28,
86 0x9144,
87 0x3f90,
88 0x915c,
89 0x9160,
90 0x9178,
91 0x917c,
92 0x9180,
93 0x918c,
94 0x9190,
95 0x9194,
96 0x9198,
97 0x919c,
98 0x91a8,
99 0x91ac,
100 0x91b0,
101 0x91b4,
102 0x91b8,
103 0x91c4,
104 0x91c8,
105 0x91cc,
106 0x91d0,
107 0x91d4,
108 0x91e0,
109 0x91e4,
110 0x91ec,
111 0x91f0,
112 0x91f4,
113 0x9200,
114 0x9204,
115 0x929c,
116 0x8030,
117 0x9150,
118 0x9a60,
119 0x920c,
120 0x9210,
121 0x9228,
122 0x922c,
123 0x9244,
124 0x9248,
125 0x91e8,
126 0x9294,
127 0x9208,
128 0x9224,
129 0x9240,
130 0x9220,
131 0x923c,
132 0x9258,
133 0x9744,
134 0xa200,
135 0xa204,
136 0xa208,
137 0xa20c,
138 0x8d58,
139 0x9030,
140 0x9034,
141 0x9038,
142 0x903c,
143 0x9040,
144 0x9654,
145 0x897c,
146 0xa210,
147 0xa214,
148 0x9868,
149 0xa02c,
150 0x9664,
151 0x9698,
152 0x949c,
153 0x8e10,
154 0x8e18,
155 0x8c50,
156 0x8c58,
157 0x8c60,
158 0x8c68,
159 0x89b4,
160 0x9830,
161 0x802c,
162};
163
164extern bool evergreen_is_display_hung(struct radeon_device *rdev);
165extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
166extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
167extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
168extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
169extern void evergreen_mc_program(struct radeon_device *rdev);
170extern void evergreen_irq_suspend(struct radeon_device *rdev);
171extern int evergreen_mc_init(struct radeon_device *rdev);
172extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
173extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
174extern void evergreen_program_aspm(struct radeon_device *rdev);
175extern void sumo_rlc_fini(struct radeon_device *rdev);
176extern int sumo_rlc_init(struct radeon_device *rdev);
177extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
178
179/* Firmware Names */
180MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
181MODULE_FIRMWARE("radeon/BARTS_me.bin");
182MODULE_FIRMWARE("radeon/BARTS_mc.bin");
183MODULE_FIRMWARE("radeon/BARTS_smc.bin");
184MODULE_FIRMWARE("radeon/BTC_rlc.bin");
185MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
186MODULE_FIRMWARE("radeon/TURKS_me.bin");
187MODULE_FIRMWARE("radeon/TURKS_mc.bin");
188MODULE_FIRMWARE("radeon/TURKS_smc.bin");
189MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
190MODULE_FIRMWARE("radeon/CAICOS_me.bin");
191MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
192MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
193MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
194MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
195MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
196MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
197MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
198MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
199MODULE_FIRMWARE("radeon/ARUBA_me.bin");
200MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
201
202
203static const u32 cayman_golden_registers2[] =
204{
205 0x3e5c, 0xffffffff, 0x00000000,
206 0x3e48, 0xffffffff, 0x00000000,
207 0x3e4c, 0xffffffff, 0x00000000,
208 0x3e64, 0xffffffff, 0x00000000,
209 0x3e50, 0xffffffff, 0x00000000,
210 0x3e60, 0xffffffff, 0x00000000
211};
212
213static const u32 cayman_golden_registers[] =
214{
215 0x5eb4, 0xffffffff, 0x00000002,
216 0x5e78, 0x8f311ff1, 0x001000f0,
217 0x3f90, 0xffff0000, 0xff000000,
218 0x9148, 0xffff0000, 0xff000000,
219 0x3f94, 0xffff0000, 0xff000000,
220 0x914c, 0xffff0000, 0xff000000,
221 0xc78, 0x00000080, 0x00000080,
222 0xbd4, 0x70073777, 0x00011003,
223 0xd02c, 0xbfffff1f, 0x08421000,
224 0xd0b8, 0x73773777, 0x02011003,
225 0x5bc0, 0x00200000, 0x50100000,
226 0x98f8, 0x33773777, 0x02011003,
227 0x98fc, 0xffffffff, 0x76541032,
228 0x7030, 0x31000311, 0x00000011,
229 0x2f48, 0x33773777, 0x42010001,
230 0x6b28, 0x00000010, 0x00000012,
231 0x7728, 0x00000010, 0x00000012,
232 0x10328, 0x00000010, 0x00000012,
233 0x10f28, 0x00000010, 0x00000012,
234 0x11b28, 0x00000010, 0x00000012,
235 0x12728, 0x00000010, 0x00000012,
236 0x240c, 0x000007ff, 0x00000000,
237 0x8a14, 0xf000001f, 0x00000007,
238 0x8b24, 0x3fff3fff, 0x00ff0fff,
239 0x8b10, 0x0000ff0f, 0x00000000,
240 0x28a4c, 0x07ffffff, 0x06000000,
241 0x10c, 0x00000001, 0x00010003,
242 0xa02c, 0xffffffff, 0x0000009b,
243 0x913c, 0x0000010f, 0x01000100,
244 0x8c04, 0xf8ff00ff, 0x40600060,
245 0x28350, 0x00000f01, 0x00000000,
246 0x9508, 0x3700001f, 0x00000002,
247 0x960c, 0xffffffff, 0x54763210,
248 0x88c4, 0x001f3ae3, 0x00000082,
249 0x88d0, 0xffffffff, 0x0f40df40,
250 0x88d4, 0x0000001f, 0x00000010,
251 0x8974, 0xffffffff, 0x00000000
252};
253
254static const u32 dvst_golden_registers2[] =
255{
256 0x8f8, 0xffffffff, 0,
257 0x8fc, 0x00380000, 0,
258 0x8f8, 0xffffffff, 1,
259 0x8fc, 0x0e000000, 0
260};
261
262static const u32 dvst_golden_registers[] =
263{
264 0x690, 0x3fff3fff, 0x20c00033,
265 0x918c, 0x0fff0fff, 0x00010006,
266 0x91a8, 0x0fff0fff, 0x00010006,
267 0x9150, 0xffffdfff, 0x6e944040,
268 0x917c, 0x0fff0fff, 0x00030002,
269 0x9198, 0x0fff0fff, 0x00030002,
270 0x915c, 0x0fff0fff, 0x00010000,
271 0x3f90, 0xffff0001, 0xff000000,
272 0x9178, 0x0fff0fff, 0x00070000,
273 0x9194, 0x0fff0fff, 0x00070000,
274 0x9148, 0xffff0001, 0xff000000,
275 0x9190, 0x0fff0fff, 0x00090008,
276 0x91ac, 0x0fff0fff, 0x00090008,
277 0x3f94, 0xffff0000, 0xff000000,
278 0x914c, 0xffff0000, 0xff000000,
279 0x929c, 0x00000fff, 0x00000001,
280 0x55e4, 0xff607fff, 0xfc000100,
281 0x8a18, 0xff000fff, 0x00000100,
282 0x8b28, 0xff000fff, 0x00000100,
283 0x9144, 0xfffc0fff, 0x00000100,
284 0x6ed8, 0x00010101, 0x00010000,
285 0x9830, 0xffffffff, 0x00000000,
286 0x9834, 0xf00fffff, 0x00000400,
287 0x9838, 0xfffffffe, 0x00000000,
288 0xd0c0, 0xff000fff, 0x00000100,
289 0xd02c, 0xbfffff1f, 0x08421000,
290 0xd0b8, 0x73773777, 0x12010001,
291 0x5bb0, 0x000000f0, 0x00000070,
292 0x98f8, 0x73773777, 0x12010001,
293 0x98fc, 0xffffffff, 0x00000010,
294 0x9b7c, 0x00ff0000, 0x00fc0000,
295 0x8030, 0x00001f0f, 0x0000100a,
296 0x2f48, 0x73773777, 0x12010001,
297 0x2408, 0x00030000, 0x000c007f,
298 0x8a14, 0xf000003f, 0x00000007,
299 0x8b24, 0x3fff3fff, 0x00ff0fff,
300 0x8b10, 0x0000ff0f, 0x00000000,
301 0x28a4c, 0x07ffffff, 0x06000000,
302 0x4d8, 0x00000fff, 0x00000100,
303 0xa008, 0xffffffff, 0x00010000,
304 0x913c, 0xffff03ff, 0x01000100,
305 0x8c00, 0x000000ff, 0x00000003,
306 0x8c04, 0xf8ff00ff, 0x40600060,
307 0x8cf0, 0x1fff1fff, 0x08e00410,
308 0x28350, 0x00000f01, 0x00000000,
309 0x9508, 0xf700071f, 0x00000002,
310 0x960c, 0xffffffff, 0x54763210,
311 0x20ef8, 0x01ff01ff, 0x00000002,
312 0x20e98, 0xfffffbff, 0x00200000,
313 0x2015c, 0xffffffff, 0x00000f40,
314 0x88c4, 0x001f3ae3, 0x00000082,
315 0x8978, 0x3fffffff, 0x04050140,
316 0x88d4, 0x0000001f, 0x00000010,
317 0x8974, 0xffffffff, 0x00000000
318};
319
320static const u32 scrapper_golden_registers[] =
321{
322 0x690, 0x3fff3fff, 0x20c00033,
323 0x918c, 0x0fff0fff, 0x00010006,
324 0x918c, 0x0fff0fff, 0x00010006,
325 0x91a8, 0x0fff0fff, 0x00010006,
326 0x91a8, 0x0fff0fff, 0x00010006,
327 0x9150, 0xffffdfff, 0x6e944040,
328 0x9150, 0xffffdfff, 0x6e944040,
329 0x917c, 0x0fff0fff, 0x00030002,
330 0x917c, 0x0fff0fff, 0x00030002,
331 0x9198, 0x0fff0fff, 0x00030002,
332 0x9198, 0x0fff0fff, 0x00030002,
333 0x915c, 0x0fff0fff, 0x00010000,
334 0x915c, 0x0fff0fff, 0x00010000,
335 0x3f90, 0xffff0001, 0xff000000,
336 0x3f90, 0xffff0001, 0xff000000,
337 0x9178, 0x0fff0fff, 0x00070000,
338 0x9178, 0x0fff0fff, 0x00070000,
339 0x9194, 0x0fff0fff, 0x00070000,
340 0x9194, 0x0fff0fff, 0x00070000,
341 0x9148, 0xffff0001, 0xff000000,
342 0x9148, 0xffff0001, 0xff000000,
343 0x9190, 0x0fff0fff, 0x00090008,
344 0x9190, 0x0fff0fff, 0x00090008,
345 0x91ac, 0x0fff0fff, 0x00090008,
346 0x91ac, 0x0fff0fff, 0x00090008,
347 0x3f94, 0xffff0000, 0xff000000,
348 0x3f94, 0xffff0000, 0xff000000,
349 0x914c, 0xffff0000, 0xff000000,
350 0x914c, 0xffff0000, 0xff000000,
351 0x929c, 0x00000fff, 0x00000001,
352 0x929c, 0x00000fff, 0x00000001,
353 0x55e4, 0xff607fff, 0xfc000100,
354 0x8a18, 0xff000fff, 0x00000100,
355 0x8a18, 0xff000fff, 0x00000100,
356 0x8b28, 0xff000fff, 0x00000100,
357 0x8b28, 0xff000fff, 0x00000100,
358 0x9144, 0xfffc0fff, 0x00000100,
359 0x9144, 0xfffc0fff, 0x00000100,
360 0x6ed8, 0x00010101, 0x00010000,
361 0x9830, 0xffffffff, 0x00000000,
362 0x9830, 0xffffffff, 0x00000000,
363 0x9834, 0xf00fffff, 0x00000400,
364 0x9834, 0xf00fffff, 0x00000400,
365 0x9838, 0xfffffffe, 0x00000000,
366 0x9838, 0xfffffffe, 0x00000000,
367 0xd0c0, 0xff000fff, 0x00000100,
368 0xd02c, 0xbfffff1f, 0x08421000,
369 0xd02c, 0xbfffff1f, 0x08421000,
370 0xd0b8, 0x73773777, 0x12010001,
371 0xd0b8, 0x73773777, 0x12010001,
372 0x5bb0, 0x000000f0, 0x00000070,
373 0x98f8, 0x73773777, 0x12010001,
374 0x98f8, 0x73773777, 0x12010001,
375 0x98fc, 0xffffffff, 0x00000010,
376 0x98fc, 0xffffffff, 0x00000010,
377 0x9b7c, 0x00ff0000, 0x00fc0000,
378 0x9b7c, 0x00ff0000, 0x00fc0000,
379 0x8030, 0x00001f0f, 0x0000100a,
380 0x8030, 0x00001f0f, 0x0000100a,
381 0x2f48, 0x73773777, 0x12010001,
382 0x2f48, 0x73773777, 0x12010001,
383 0x2408, 0x00030000, 0x000c007f,
384 0x8a14, 0xf000003f, 0x00000007,
385 0x8a14, 0xf000003f, 0x00000007,
386 0x8b24, 0x3fff3fff, 0x00ff0fff,
387 0x8b24, 0x3fff3fff, 0x00ff0fff,
388 0x8b10, 0x0000ff0f, 0x00000000,
389 0x8b10, 0x0000ff0f, 0x00000000,
390 0x28a4c, 0x07ffffff, 0x06000000,
391 0x28a4c, 0x07ffffff, 0x06000000,
392 0x4d8, 0x00000fff, 0x00000100,
393 0x4d8, 0x00000fff, 0x00000100,
394 0xa008, 0xffffffff, 0x00010000,
395 0xa008, 0xffffffff, 0x00010000,
396 0x913c, 0xffff03ff, 0x01000100,
397 0x913c, 0xffff03ff, 0x01000100,
398 0x90e8, 0x001fffff, 0x010400c0,
399 0x8c00, 0x000000ff, 0x00000003,
400 0x8c00, 0x000000ff, 0x00000003,
401 0x8c04, 0xf8ff00ff, 0x40600060,
402 0x8c04, 0xf8ff00ff, 0x40600060,
403 0x8c30, 0x0000000f, 0x00040005,
404 0x8cf0, 0x1fff1fff, 0x08e00410,
405 0x8cf0, 0x1fff1fff, 0x08e00410,
406 0x900c, 0x00ffffff, 0x0017071f,
407 0x28350, 0x00000f01, 0x00000000,
408 0x28350, 0x00000f01, 0x00000000,
409 0x9508, 0xf700071f, 0x00000002,
410 0x9508, 0xf700071f, 0x00000002,
411 0x9688, 0x00300000, 0x0017000f,
412 0x960c, 0xffffffff, 0x54763210,
413 0x960c, 0xffffffff, 0x54763210,
414 0x20ef8, 0x01ff01ff, 0x00000002,
415 0x20e98, 0xfffffbff, 0x00200000,
416 0x2015c, 0xffffffff, 0x00000f40,
417 0x88c4, 0x001f3ae3, 0x00000082,
418 0x88c4, 0x001f3ae3, 0x00000082,
419 0x8978, 0x3fffffff, 0x04050140,
420 0x8978, 0x3fffffff, 0x04050140,
421 0x88d4, 0x0000001f, 0x00000010,
422 0x88d4, 0x0000001f, 0x00000010,
423 0x8974, 0xffffffff, 0x00000000,
424 0x8974, 0xffffffff, 0x00000000
425};
426
427static void ni_init_golden_registers(struct radeon_device *rdev)
428{
429 switch (rdev->family) {
430 case CHIP_CAYMAN:
431 radeon_program_register_sequence(rdev,
432 cayman_golden_registers,
433 (const u32)ARRAY_SIZE(cayman_golden_registers));
434 radeon_program_register_sequence(rdev,
435 cayman_golden_registers2,
436 (const u32)ARRAY_SIZE(cayman_golden_registers2));
437 break;
438 case CHIP_ARUBA:
439 if ((rdev->pdev->device == 0x9900) ||
440 (rdev->pdev->device == 0x9901) ||
441 (rdev->pdev->device == 0x9903) ||
442 (rdev->pdev->device == 0x9904) ||
443 (rdev->pdev->device == 0x9905) ||
444 (rdev->pdev->device == 0x9906) ||
445 (rdev->pdev->device == 0x9907) ||
446 (rdev->pdev->device == 0x9908) ||
447 (rdev->pdev->device == 0x9909) ||
448 (rdev->pdev->device == 0x990A) ||
449 (rdev->pdev->device == 0x990B) ||
450 (rdev->pdev->device == 0x990C) ||
451 (rdev->pdev->device == 0x990D) ||
452 (rdev->pdev->device == 0x990E) ||
453 (rdev->pdev->device == 0x990F) ||
454 (rdev->pdev->device == 0x9910) ||
455 (rdev->pdev->device == 0x9913) ||
456 (rdev->pdev->device == 0x9917) ||
457 (rdev->pdev->device == 0x9918)) {
458 radeon_program_register_sequence(rdev,
459 dvst_golden_registers,
460 (const u32)ARRAY_SIZE(dvst_golden_registers));
461 radeon_program_register_sequence(rdev,
462 dvst_golden_registers2,
463 (const u32)ARRAY_SIZE(dvst_golden_registers2));
464 } else {
465 radeon_program_register_sequence(rdev,
466 scrapper_golden_registers,
467 (const u32)ARRAY_SIZE(scrapper_golden_registers));
468 radeon_program_register_sequence(rdev,
469 dvst_golden_registers2,
470 (const u32)ARRAY_SIZE(dvst_golden_registers2));
471 }
472 break;
473 default:
474 break;
475 }
476}
477
478#define BTC_IO_MC_REGS_SIZE 29
479
480static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
481 {0x00000077, 0xff010100},
482 {0x00000078, 0x00000000},
483 {0x00000079, 0x00001434},
484 {0x0000007a, 0xcc08ec08},
485 {0x0000007b, 0x00040000},
486 {0x0000007c, 0x000080c0},
487 {0x0000007d, 0x09000000},
488 {0x0000007e, 0x00210404},
489 {0x00000081, 0x08a8e800},
490 {0x00000082, 0x00030444},
491 {0x00000083, 0x00000000},
492 {0x00000085, 0x00000001},
493 {0x00000086, 0x00000002},
494 {0x00000087, 0x48490000},
495 {0x00000088, 0x20244647},
496 {0x00000089, 0x00000005},
497 {0x0000008b, 0x66030000},
498 {0x0000008c, 0x00006603},
499 {0x0000008d, 0x00000100},
500 {0x0000008f, 0x00001c0a},
501 {0x00000090, 0xff000001},
502 {0x00000094, 0x00101101},
503 {0x00000095, 0x00000fff},
504 {0x00000096, 0x00116fff},
505 {0x00000097, 0x60010000},
506 {0x00000098, 0x10010000},
507 {0x00000099, 0x00006000},
508 {0x0000009a, 0x00001000},
509 {0x0000009f, 0x00946a00}
510};
511
512static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
513 {0x00000077, 0xff010100},
514 {0x00000078, 0x00000000},
515 {0x00000079, 0x00001434},
516 {0x0000007a, 0xcc08ec08},
517 {0x0000007b, 0x00040000},
518 {0x0000007c, 0x000080c0},
519 {0x0000007d, 0x09000000},
520 {0x0000007e, 0x00210404},
521 {0x00000081, 0x08a8e800},
522 {0x00000082, 0x00030444},
523 {0x00000083, 0x00000000},
524 {0x00000085, 0x00000001},
525 {0x00000086, 0x00000002},
526 {0x00000087, 0x48490000},
527 {0x00000088, 0x20244647},
528 {0x00000089, 0x00000005},
529 {0x0000008b, 0x66030000},
530 {0x0000008c, 0x00006603},
531 {0x0000008d, 0x00000100},
532 {0x0000008f, 0x00001c0a},
533 {0x00000090, 0xff000001},
534 {0x00000094, 0x00101101},
535 {0x00000095, 0x00000fff},
536 {0x00000096, 0x00116fff},
537 {0x00000097, 0x60010000},
538 {0x00000098, 0x10010000},
539 {0x00000099, 0x00006000},
540 {0x0000009a, 0x00001000},
541 {0x0000009f, 0x00936a00}
542};
543
544static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
545 {0x00000077, 0xff010100},
546 {0x00000078, 0x00000000},
547 {0x00000079, 0x00001434},
548 {0x0000007a, 0xcc08ec08},
549 {0x0000007b, 0x00040000},
550 {0x0000007c, 0x000080c0},
551 {0x0000007d, 0x09000000},
552 {0x0000007e, 0x00210404},
553 {0x00000081, 0x08a8e800},
554 {0x00000082, 0x00030444},
555 {0x00000083, 0x00000000},
556 {0x00000085, 0x00000001},
557 {0x00000086, 0x00000002},
558 {0x00000087, 0x48490000},
559 {0x00000088, 0x20244647},
560 {0x00000089, 0x00000005},
561 {0x0000008b, 0x66030000},
562 {0x0000008c, 0x00006603},
563 {0x0000008d, 0x00000100},
564 {0x0000008f, 0x00001c0a},
565 {0x00000090, 0xff000001},
566 {0x00000094, 0x00101101},
567 {0x00000095, 0x00000fff},
568 {0x00000096, 0x00116fff},
569 {0x00000097, 0x60010000},
570 {0x00000098, 0x10010000},
571 {0x00000099, 0x00006000},
572 {0x0000009a, 0x00001000},
573 {0x0000009f, 0x00916a00}
574};
575
576static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
577 {0x00000077, 0xff010100},
578 {0x00000078, 0x00000000},
579 {0x00000079, 0x00001434},
580 {0x0000007a, 0xcc08ec08},
581 {0x0000007b, 0x00040000},
582 {0x0000007c, 0x000080c0},
583 {0x0000007d, 0x09000000},
584 {0x0000007e, 0x00210404},
585 {0x00000081, 0x08a8e800},
586 {0x00000082, 0x00030444},
587 {0x00000083, 0x00000000},
588 {0x00000085, 0x00000001},
589 {0x00000086, 0x00000002},
590 {0x00000087, 0x48490000},
591 {0x00000088, 0x20244647},
592 {0x00000089, 0x00000005},
593 {0x0000008b, 0x66030000},
594 {0x0000008c, 0x00006603},
595 {0x0000008d, 0x00000100},
596 {0x0000008f, 0x00001c0a},
597 {0x00000090, 0xff000001},
598 {0x00000094, 0x00101101},
599 {0x00000095, 0x00000fff},
600 {0x00000096, 0x00116fff},
601 {0x00000097, 0x60010000},
602 {0x00000098, 0x10010000},
603 {0x00000099, 0x00006000},
604 {0x0000009a, 0x00001000},
605 {0x0000009f, 0x00976b00}
606};
607
608int ni_mc_load_microcode(struct radeon_device *rdev)
609{
610 const __be32 *fw_data;
611 u32 mem_type, running, blackout = 0;
612 u32 *io_mc_regs;
613 int i, ucode_size, regs_size;
614
615 if (!rdev->mc_fw)
616 return -EINVAL;
617
618 switch (rdev->family) {
619 case CHIP_BARTS:
620 io_mc_regs = (u32 *)&barts_io_mc_regs;
621 ucode_size = BTC_MC_UCODE_SIZE;
622 regs_size = BTC_IO_MC_REGS_SIZE;
623 break;
624 case CHIP_TURKS:
625 io_mc_regs = (u32 *)&turks_io_mc_regs;
626 ucode_size = BTC_MC_UCODE_SIZE;
627 regs_size = BTC_IO_MC_REGS_SIZE;
628 break;
629 case CHIP_CAICOS:
630 default:
631 io_mc_regs = (u32 *)&caicos_io_mc_regs;
632 ucode_size = BTC_MC_UCODE_SIZE;
633 regs_size = BTC_IO_MC_REGS_SIZE;
634 break;
635 case CHIP_CAYMAN:
636 io_mc_regs = (u32 *)&cayman_io_mc_regs;
637 ucode_size = CAYMAN_MC_UCODE_SIZE;
638 regs_size = BTC_IO_MC_REGS_SIZE;
639 break;
640 }
641
642 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
643 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
644
645 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
646 if (running) {
647 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
648 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
649 }
650
651 /* reset the engine and set to writable */
652 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
653 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
654
655 /* load mc io regs */
656 for (i = 0; i < regs_size; i++) {
657 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
658 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
659 }
660 /* load the MC ucode */
661 fw_data = (const __be32 *)rdev->mc_fw->data;
662 for (i = 0; i < ucode_size; i++)
663 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
664
665 /* put the engine back into the active state */
666 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
667 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
668 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
669
670 /* wait for training to complete */
671 for (i = 0; i < rdev->usec_timeout; i++) {
672 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
673 break;
674 udelay(1);
675 }
676
677 if (running)
678 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
679 }
680
681 return 0;
682}
683
684int ni_init_microcode(struct radeon_device *rdev)
685{
686 const char *chip_name;
687 const char *rlc_chip_name;
688 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
689 size_t smc_req_size = 0;
690 char fw_name[30];
691 int err;
692
693 DRM_DEBUG("\n");
694
695 switch (rdev->family) {
696 case CHIP_BARTS:
697 chip_name = "BARTS";
698 rlc_chip_name = "BTC";
699 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
700 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
701 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
702 mc_req_size = BTC_MC_UCODE_SIZE * 4;
703 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
704 break;
705 case CHIP_TURKS:
706 chip_name = "TURKS";
707 rlc_chip_name = "BTC";
708 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
709 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
710 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
711 mc_req_size = BTC_MC_UCODE_SIZE * 4;
712 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
713 break;
714 case CHIP_CAICOS:
715 chip_name = "CAICOS";
716 rlc_chip_name = "BTC";
717 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
718 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
719 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
720 mc_req_size = BTC_MC_UCODE_SIZE * 4;
721 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
722 break;
723 case CHIP_CAYMAN:
724 chip_name = "CAYMAN";
725 rlc_chip_name = "CAYMAN";
726 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
727 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
728 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
729 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
730 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
731 break;
732 case CHIP_ARUBA:
733 chip_name = "ARUBA";
734 rlc_chip_name = "ARUBA";
735 /* pfp/me same size as CAYMAN */
736 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
737 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
738 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
739 mc_req_size = 0;
740 break;
741 default: BUG();
742 }
743
744 DRM_INFO("Loading %s Microcode\n", chip_name);
745
746 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
747 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
748 if (err)
749 goto out;
750 if (rdev->pfp_fw->size != pfp_req_size) {
751 printk(KERN_ERR
752 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
753 rdev->pfp_fw->size, fw_name);
754 err = -EINVAL;
755 goto out;
756 }
757
758 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
759 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
760 if (err)
761 goto out;
762 if (rdev->me_fw->size != me_req_size) {
763 printk(KERN_ERR
764 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
765 rdev->me_fw->size, fw_name);
766 err = -EINVAL;
767 }
768
769 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
770 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
771 if (err)
772 goto out;
773 if (rdev->rlc_fw->size != rlc_req_size) {
774 printk(KERN_ERR
775 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
776 rdev->rlc_fw->size, fw_name);
777 err = -EINVAL;
778 }
779
780 /* no MC ucode on TN */
781 if (!(rdev->flags & RADEON_IS_IGP)) {
782 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
783 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
784 if (err)
785 goto out;
786 if (rdev->mc_fw->size != mc_req_size) {
787 printk(KERN_ERR
788 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
789 rdev->mc_fw->size, fw_name);
790 err = -EINVAL;
791 }
792 }
793
794 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
795 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
796 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
797 if (err) {
798 printk(KERN_ERR
799 "smc: error loading firmware \"%s\"\n",
800 fw_name);
801 release_firmware(rdev->smc_fw);
802 rdev->smc_fw = NULL;
803 err = 0;
804 } else if (rdev->smc_fw->size != smc_req_size) {
805 printk(KERN_ERR
806 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
807 rdev->mc_fw->size, fw_name);
808 err = -EINVAL;
809 }
810 }
811
812out:
813 if (err) {
814 if (err != -EINVAL)
815 printk(KERN_ERR
816 "ni_cp: Failed to load firmware \"%s\"\n",
817 fw_name);
818 release_firmware(rdev->pfp_fw);
819 rdev->pfp_fw = NULL;
820 release_firmware(rdev->me_fw);
821 rdev->me_fw = NULL;
822 release_firmware(rdev->rlc_fw);
823 rdev->rlc_fw = NULL;
824 release_firmware(rdev->mc_fw);
825 rdev->mc_fw = NULL;
826 }
827 return err;
828}
829
830int tn_get_temp(struct radeon_device *rdev)
831{
832 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
833 int actual_temp = (temp / 8) - 49;
834
835 return actual_temp * 1000;
836}
837
838/*
839 * Core functions
840 */
841static void cayman_gpu_init(struct radeon_device *rdev)
842{
843 u32 gb_addr_config = 0;
844 u32 mc_shared_chmap, mc_arb_ramcfg;
845 u32 cgts_tcc_disable;
846 u32 sx_debug_1;
847 u32 smx_dc_ctl0;
848 u32 cgts_sm_ctrl_reg;
849 u32 hdp_host_path_cntl;
850 u32 tmp;
851 u32 disabled_rb_mask;
852 int i, j;
853
854 switch (rdev->family) {
855 case CHIP_CAYMAN:
856 rdev->config.cayman.max_shader_engines = 2;
857 rdev->config.cayman.max_pipes_per_simd = 4;
858 rdev->config.cayman.max_tile_pipes = 8;
859 rdev->config.cayman.max_simds_per_se = 12;
860 rdev->config.cayman.max_backends_per_se = 4;
861 rdev->config.cayman.max_texture_channel_caches = 8;
862 rdev->config.cayman.max_gprs = 256;
863 rdev->config.cayman.max_threads = 256;
864 rdev->config.cayman.max_gs_threads = 32;
865 rdev->config.cayman.max_stack_entries = 512;
866 rdev->config.cayman.sx_num_of_sets = 8;
867 rdev->config.cayman.sx_max_export_size = 256;
868 rdev->config.cayman.sx_max_export_pos_size = 64;
869 rdev->config.cayman.sx_max_export_smx_size = 192;
870 rdev->config.cayman.max_hw_contexts = 8;
871 rdev->config.cayman.sq_num_cf_insts = 2;
872
873 rdev->config.cayman.sc_prim_fifo_size = 0x100;
874 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
875 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
876 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
877 break;
878 case CHIP_ARUBA:
879 default:
880 rdev->config.cayman.max_shader_engines = 1;
881 rdev->config.cayman.max_pipes_per_simd = 4;
882 rdev->config.cayman.max_tile_pipes = 2;
883 if ((rdev->pdev->device == 0x9900) ||
884 (rdev->pdev->device == 0x9901) ||
885 (rdev->pdev->device == 0x9905) ||
886 (rdev->pdev->device == 0x9906) ||
887 (rdev->pdev->device == 0x9907) ||
888 (rdev->pdev->device == 0x9908) ||
889 (rdev->pdev->device == 0x9909) ||
890 (rdev->pdev->device == 0x990B) ||
891 (rdev->pdev->device == 0x990C) ||
892 (rdev->pdev->device == 0x990F) ||
893 (rdev->pdev->device == 0x9910) ||
894 (rdev->pdev->device == 0x9917) ||
895 (rdev->pdev->device == 0x9999) ||
896 (rdev->pdev->device == 0x999C)) {
897 rdev->config.cayman.max_simds_per_se = 6;
898 rdev->config.cayman.max_backends_per_se = 2;
899 rdev->config.cayman.max_hw_contexts = 8;
900 rdev->config.cayman.sx_max_export_size = 256;
901 rdev->config.cayman.sx_max_export_pos_size = 64;
902 rdev->config.cayman.sx_max_export_smx_size = 192;
903 } else if ((rdev->pdev->device == 0x9903) ||
904 (rdev->pdev->device == 0x9904) ||
905 (rdev->pdev->device == 0x990A) ||
906 (rdev->pdev->device == 0x990D) ||
907 (rdev->pdev->device == 0x990E) ||
908 (rdev->pdev->device == 0x9913) ||
909 (rdev->pdev->device == 0x9918) ||
910 (rdev->pdev->device == 0x999D)) {
911 rdev->config.cayman.max_simds_per_se = 4;
912 rdev->config.cayman.max_backends_per_se = 2;
913 rdev->config.cayman.max_hw_contexts = 8;
914 rdev->config.cayman.sx_max_export_size = 256;
915 rdev->config.cayman.sx_max_export_pos_size = 64;
916 rdev->config.cayman.sx_max_export_smx_size = 192;
917 } else if ((rdev->pdev->device == 0x9919) ||
918 (rdev->pdev->device == 0x9990) ||
919 (rdev->pdev->device == 0x9991) ||
920 (rdev->pdev->device == 0x9994) ||
921 (rdev->pdev->device == 0x9995) ||
922 (rdev->pdev->device == 0x9996) ||
923 (rdev->pdev->device == 0x999A) ||
924 (rdev->pdev->device == 0x99A0)) {
925 rdev->config.cayman.max_simds_per_se = 3;
926 rdev->config.cayman.max_backends_per_se = 1;
927 rdev->config.cayman.max_hw_contexts = 4;
928 rdev->config.cayman.sx_max_export_size = 128;
929 rdev->config.cayman.sx_max_export_pos_size = 32;
930 rdev->config.cayman.sx_max_export_smx_size = 96;
931 } else {
932 rdev->config.cayman.max_simds_per_se = 2;
933 rdev->config.cayman.max_backends_per_se = 1;
934 rdev->config.cayman.max_hw_contexts = 4;
935 rdev->config.cayman.sx_max_export_size = 128;
936 rdev->config.cayman.sx_max_export_pos_size = 32;
937 rdev->config.cayman.sx_max_export_smx_size = 96;
938 }
939 rdev->config.cayman.max_texture_channel_caches = 2;
940 rdev->config.cayman.max_gprs = 256;
941 rdev->config.cayman.max_threads = 256;
942 rdev->config.cayman.max_gs_threads = 32;
943 rdev->config.cayman.max_stack_entries = 512;
944 rdev->config.cayman.sx_num_of_sets = 8;
945 rdev->config.cayman.sq_num_cf_insts = 2;
946
947 rdev->config.cayman.sc_prim_fifo_size = 0x40;
948 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
949 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
950 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
951 break;
952 }
953
954 /* Initialize HDP */
955 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
956 WREG32((0x2c14 + j), 0x00000000);
957 WREG32((0x2c18 + j), 0x00000000);
958 WREG32((0x2c1c + j), 0x00000000);
959 WREG32((0x2c20 + j), 0x00000000);
960 WREG32((0x2c24 + j), 0x00000000);
961 }
962
963 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
964
965 evergreen_fix_pci_max_read_req_size(rdev);
966
967 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
968 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
969
970 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
971 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
972 if (rdev->config.cayman.mem_row_size_in_kb > 4)
973 rdev->config.cayman.mem_row_size_in_kb = 4;
974 /* XXX use MC settings? */
975 rdev->config.cayman.shader_engine_tile_size = 32;
976 rdev->config.cayman.num_gpus = 1;
977 rdev->config.cayman.multi_gpu_tile_size = 64;
978
979 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
980 rdev->config.cayman.num_tile_pipes = (1 << tmp);
981 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
982 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
983 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
984 rdev->config.cayman.num_shader_engines = tmp + 1;
985 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
986 rdev->config.cayman.num_gpus = tmp + 1;
987 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
988 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
989 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
990 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
991
992
993 /* setup tiling info dword. gb_addr_config is not adequate since it does
994 * not have bank info, so create a custom tiling dword.
995 * bits 3:0 num_pipes
996 * bits 7:4 num_banks
997 * bits 11:8 group_size
998 * bits 15:12 row_size
999 */
1000 rdev->config.cayman.tile_config = 0;
1001 switch (rdev->config.cayman.num_tile_pipes) {
1002 case 1:
1003 default:
1004 rdev->config.cayman.tile_config |= (0 << 0);
1005 break;
1006 case 2:
1007 rdev->config.cayman.tile_config |= (1 << 0);
1008 break;
1009 case 4:
1010 rdev->config.cayman.tile_config |= (2 << 0);
1011 break;
1012 case 8:
1013 rdev->config.cayman.tile_config |= (3 << 0);
1014 break;
1015 }
1016
1017 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1018 if (rdev->flags & RADEON_IS_IGP)
1019 rdev->config.cayman.tile_config |= 1 << 4;
1020 else {
1021 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1022 case 0: /* four banks */
1023 rdev->config.cayman.tile_config |= 0 << 4;
1024 break;
1025 case 1: /* eight banks */
1026 rdev->config.cayman.tile_config |= 1 << 4;
1027 break;
1028 case 2: /* sixteen banks */
1029 default:
1030 rdev->config.cayman.tile_config |= 2 << 4;
1031 break;
1032 }
1033 }
1034 rdev->config.cayman.tile_config |=
1035 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1036 rdev->config.cayman.tile_config |=
1037 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1038
1039 tmp = 0;
1040 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1041 u32 rb_disable_bitmap;
1042
1043 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1044 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1045 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1046 tmp <<= 4;
1047 tmp |= rb_disable_bitmap;
1048 }
1049 /* enabled rb are just the one not disabled :) */
1050 disabled_rb_mask = tmp;
1051 tmp = 0;
1052 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1053 tmp |= (1 << i);
1054 /* if all the backends are disabled, fix it up here */
1055 if ((disabled_rb_mask & tmp) == tmp) {
1056 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1057 disabled_rb_mask &= ~(1 << i);
1058 }
1059
1060 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1061 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1062
1063 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1064 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1065 if (ASIC_IS_DCE6(rdev))
1066 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1067 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1068 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1069 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1070 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1071 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1072 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1073
1074 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1075 (rdev->flags & RADEON_IS_IGP)) {
1076 if ((disabled_rb_mask & 3) == 1) {
1077 /* RB0 disabled, RB1 enabled */
1078 tmp = 0x11111111;
1079 } else {
1080 /* RB1 disabled, RB0 enabled */
1081 tmp = 0x00000000;
1082 }
1083 } else {
1084 tmp = gb_addr_config & NUM_PIPES_MASK;
1085 tmp = r6xx_remap_render_backend(rdev, tmp,
1086 rdev->config.cayman.max_backends_per_se *
1087 rdev->config.cayman.max_shader_engines,
1088 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1089 }
1090 WREG32(GB_BACKEND_MAP, tmp);
1091
1092 cgts_tcc_disable = 0xffff0000;
1093 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1094 cgts_tcc_disable &= ~(1 << (16 + i));
1095 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1096 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1097 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1098 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1099
1100 /* reprogram the shader complex */
1101 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1102 for (i = 0; i < 16; i++)
1103 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1104 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1105
1106 /* set HW defaults for 3D engine */
1107 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1108
1109 sx_debug_1 = RREG32(SX_DEBUG_1);
1110 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1111 WREG32(SX_DEBUG_1, sx_debug_1);
1112
1113 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1114 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1115 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1116 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1117
1118 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1119
1120 /* need to be explicitly zero-ed */
1121 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1122 WREG32(SQ_LSTMP_RING_BASE, 0);
1123 WREG32(SQ_HSTMP_RING_BASE, 0);
1124 WREG32(SQ_ESTMP_RING_BASE, 0);
1125 WREG32(SQ_GSTMP_RING_BASE, 0);
1126 WREG32(SQ_VSTMP_RING_BASE, 0);
1127 WREG32(SQ_PSTMP_RING_BASE, 0);
1128
1129 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1130
1131 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1132 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1133 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1134
1135 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1136 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1137 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1138
1139
1140 WREG32(VGT_NUM_INSTANCES, 1);
1141
1142 WREG32(CP_PERFMON_CNTL, 0);
1143
1144 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1145 FETCH_FIFO_HIWATER(0x4) |
1146 DONE_FIFO_HIWATER(0xe0) |
1147 ALU_UPDATE_FIFO_HIWATER(0x8)));
1148
1149 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1150 WREG32(SQ_CONFIG, (VC_ENABLE |
1151 EXPORT_SRC_C |
1152 GFX_PRIO(0) |
1153 CS1_PRIO(0) |
1154 CS2_PRIO(1)));
1155 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1156
1157 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1158 FORCE_EOV_MAX_REZ_CNT(255)));
1159
1160 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1161 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1162
1163 WREG32(VGT_GS_VERTEX_REUSE, 16);
1164 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1165
1166 WREG32(CB_PERF_CTR0_SEL_0, 0);
1167 WREG32(CB_PERF_CTR0_SEL_1, 0);
1168 WREG32(CB_PERF_CTR1_SEL_0, 0);
1169 WREG32(CB_PERF_CTR1_SEL_1, 0);
1170 WREG32(CB_PERF_CTR2_SEL_0, 0);
1171 WREG32(CB_PERF_CTR2_SEL_1, 0);
1172 WREG32(CB_PERF_CTR3_SEL_0, 0);
1173 WREG32(CB_PERF_CTR3_SEL_1, 0);
1174
1175 tmp = RREG32(HDP_MISC_CNTL);
1176 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1177 WREG32(HDP_MISC_CNTL, tmp);
1178
1179 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1180 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1181
1182 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1183
1184 udelay(50);
1185
1186 /* set clockgating golden values on TN */
1187 if (rdev->family == CHIP_ARUBA) {
1188 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1189 tmp &= ~0x00380000;
1190 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1191 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1192 tmp &= ~0x0e000000;
1193 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1194 }
1195}
1196
1197/*
1198 * GART
1199 */
1200void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1201{
1202 /* flush hdp cache */
1203 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1204
1205 /* bits 0-7 are the VM contexts0-7 */
1206 WREG32(VM_INVALIDATE_REQUEST, 1);
1207}
1208
1209static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1210{
1211 int i, r;
1212
1213 if (rdev->gart.robj == NULL) {
1214 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1215 return -EINVAL;
1216 }
1217 r = radeon_gart_table_vram_pin(rdev);
1218 if (r)
1219 return r;
1220 radeon_gart_restore(rdev);
1221 /* Setup TLB control */
1222 WREG32(MC_VM_MX_L1_TLB_CNTL,
1223 (0xA << 7) |
1224 ENABLE_L1_TLB |
1225 ENABLE_L1_FRAGMENT_PROCESSING |
1226 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1227 ENABLE_ADVANCED_DRIVER_MODEL |
1228 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1229 /* Setup L2 cache */
1230 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1231 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1232 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1233 EFFECTIVE_L2_QUEUE_SIZE(7) |
1234 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1235 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1236 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1237 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1238 /* setup context0 */
1239 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1240 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1241 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1242 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1243 (u32)(rdev->dummy_page.addr >> 12));
1244 WREG32(VM_CONTEXT0_CNTL2, 0);
1245 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1246 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1247
1248 WREG32(0x15D4, 0);
1249 WREG32(0x15D8, 0);
1250 WREG32(0x15DC, 0);
1251
1252 /* empty context1-7 */
1253 /* Assign the pt base to something valid for now; the pts used for
1254 * the VMs are determined by the application and setup and assigned
1255 * on the fly in the vm part of radeon_gart.c
1256 */
1257 for (i = 1; i < 8; i++) {
1258 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1259 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
1260 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1261 rdev->gart.table_addr >> 12);
1262 }
1263
1264 /* enable context1-7 */
1265 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1266 (u32)(rdev->dummy_page.addr >> 12));
1267 WREG32(VM_CONTEXT1_CNTL2, 4);
1268 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1269 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1270 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1271 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1272 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1273 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1274 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1275 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1276 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1277 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1278 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1279 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1280 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1281
1282 cayman_pcie_gart_tlb_flush(rdev);
1283 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1284 (unsigned)(rdev->mc.gtt_size >> 20),
1285 (unsigned long long)rdev->gart.table_addr);
1286 rdev->gart.ready = true;
1287 return 0;
1288}
1289
1290static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1291{
1292 /* Disable all tables */
1293 WREG32(VM_CONTEXT0_CNTL, 0);
1294 WREG32(VM_CONTEXT1_CNTL, 0);
1295 /* Setup TLB control */
1296 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1297 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1298 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1299 /* Setup L2 cache */
1300 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1301 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1302 EFFECTIVE_L2_QUEUE_SIZE(7) |
1303 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1304 WREG32(VM_L2_CNTL2, 0);
1305 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1306 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1307 radeon_gart_table_vram_unpin(rdev);
1308}
1309
1310static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1311{
1312 cayman_pcie_gart_disable(rdev);
1313 radeon_gart_table_vram_free(rdev);
1314 radeon_gart_fini(rdev);
1315}
1316
1317void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1318 int ring, u32 cp_int_cntl)
1319{
1320 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1321
1322 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1323 WREG32(CP_INT_CNTL, cp_int_cntl);
1324}
1325
1326/*
1327 * CP.
1328 */
1329void cayman_fence_ring_emit(struct radeon_device *rdev,
1330 struct radeon_fence *fence)
1331{
1332 struct radeon_ring *ring = &rdev->ring[fence->ring];
1333 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1334 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1335 PACKET3_SH_ACTION_ENA;
1336
1337 /* flush read cache over gart for this vmid */
1338 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1339 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1340 radeon_ring_write(ring, 0xFFFFFFFF);
1341 radeon_ring_write(ring, 0);
1342 radeon_ring_write(ring, 10); /* poll interval */
1343 /* EVENT_WRITE_EOP - flush caches, send int */
1344 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1345 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1346 radeon_ring_write(ring, addr & 0xffffffff);
1347 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1348 radeon_ring_write(ring, fence->seq);
1349 radeon_ring_write(ring, 0);
1350}
1351
1352void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1353{
1354 struct radeon_ring *ring = &rdev->ring[ib->ring];
1355 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1356 PACKET3_SH_ACTION_ENA;
1357
1358 /* set to DX10/11 mode */
1359 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1360 radeon_ring_write(ring, 1);
1361
1362 if (ring->rptr_save_reg) {
1363 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1364 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1365 radeon_ring_write(ring, ((ring->rptr_save_reg -
1366 PACKET3_SET_CONFIG_REG_START) >> 2));
1367 radeon_ring_write(ring, next_rptr);
1368 }
1369
1370 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1371 radeon_ring_write(ring,
1372#ifdef __BIG_ENDIAN
1373 (2 << 0) |
1374#endif
1375 (ib->gpu_addr & 0xFFFFFFFC));
1376 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1377 radeon_ring_write(ring, ib->length_dw |
1378 (ib->vm ? (ib->vm->id << 24) : 0));
1379
1380 /* flush read cache over gart for this vmid */
1381 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1382 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1383 radeon_ring_write(ring, 0xFFFFFFFF);
1384 radeon_ring_write(ring, 0);
1385 radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */
1386}
1387
1388static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1389{
1390 if (enable)
1391 WREG32(CP_ME_CNTL, 0);
1392 else {
1393 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1394 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1395 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1396 WREG32(SCRATCH_UMSK, 0);
1397 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1398 }
1399}
1400
1401u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
1402 struct radeon_ring *ring)
1403{
1404 u32 rptr;
1405
1406 if (rdev->wb.enabled)
1407 rptr = rdev->wb.wb[ring->rptr_offs/4];
1408 else {
1409 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1410 rptr = RREG32(CP_RB0_RPTR);
1411 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1412 rptr = RREG32(CP_RB1_RPTR);
1413 else
1414 rptr = RREG32(CP_RB2_RPTR);
1415 }
1416
1417 return rptr;
1418}
1419
1420u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
1421 struct radeon_ring *ring)
1422{
1423 u32 wptr;
1424
1425 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1426 wptr = RREG32(CP_RB0_WPTR);
1427 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1428 wptr = RREG32(CP_RB1_WPTR);
1429 else
1430 wptr = RREG32(CP_RB2_WPTR);
1431
1432 return wptr;
1433}
1434
1435void cayman_gfx_set_wptr(struct radeon_device *rdev,
1436 struct radeon_ring *ring)
1437{
1438 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
1439 WREG32(CP_RB0_WPTR, ring->wptr);
1440 (void)RREG32(CP_RB0_WPTR);
1441 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
1442 WREG32(CP_RB1_WPTR, ring->wptr);
1443 (void)RREG32(CP_RB1_WPTR);
1444 } else {
1445 WREG32(CP_RB2_WPTR, ring->wptr);
1446 (void)RREG32(CP_RB2_WPTR);
1447 }
1448}
1449
1450static int cayman_cp_load_microcode(struct radeon_device *rdev)
1451{
1452 const __be32 *fw_data;
1453 int i;
1454
1455 if (!rdev->me_fw || !rdev->pfp_fw)
1456 return -EINVAL;
1457
1458 cayman_cp_enable(rdev, false);
1459
1460 fw_data = (const __be32 *)rdev->pfp_fw->data;
1461 WREG32(CP_PFP_UCODE_ADDR, 0);
1462 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1463 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1464 WREG32(CP_PFP_UCODE_ADDR, 0);
1465
1466 fw_data = (const __be32 *)rdev->me_fw->data;
1467 WREG32(CP_ME_RAM_WADDR, 0);
1468 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1469 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1470
1471 WREG32(CP_PFP_UCODE_ADDR, 0);
1472 WREG32(CP_ME_RAM_WADDR, 0);
1473 WREG32(CP_ME_RAM_RADDR, 0);
1474 return 0;
1475}
1476
1477static int cayman_cp_start(struct radeon_device *rdev)
1478{
1479 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1480 int r, i;
1481
1482 r = radeon_ring_lock(rdev, ring, 7);
1483 if (r) {
1484 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1485 return r;
1486 }
1487 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1488 radeon_ring_write(ring, 0x1);
1489 radeon_ring_write(ring, 0x0);
1490 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1491 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1492 radeon_ring_write(ring, 0);
1493 radeon_ring_write(ring, 0);
1494 radeon_ring_unlock_commit(rdev, ring);
1495
1496 cayman_cp_enable(rdev, true);
1497
1498 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1499 if (r) {
1500 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1501 return r;
1502 }
1503
1504 /* setup clear context state */
1505 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1506 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1507
1508 for (i = 0; i < cayman_default_size; i++)
1509 radeon_ring_write(ring, cayman_default_state[i]);
1510
1511 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1512 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1513
1514 /* set clear context state */
1515 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1516 radeon_ring_write(ring, 0);
1517
1518 /* SQ_VTX_BASE_VTX_LOC */
1519 radeon_ring_write(ring, 0xc0026f00);
1520 radeon_ring_write(ring, 0x00000000);
1521 radeon_ring_write(ring, 0x00000000);
1522 radeon_ring_write(ring, 0x00000000);
1523
1524 /* Clear consts */
1525 radeon_ring_write(ring, 0xc0036f00);
1526 radeon_ring_write(ring, 0x00000bc4);
1527 radeon_ring_write(ring, 0xffffffff);
1528 radeon_ring_write(ring, 0xffffffff);
1529 radeon_ring_write(ring, 0xffffffff);
1530
1531 radeon_ring_write(ring, 0xc0026900);
1532 radeon_ring_write(ring, 0x00000316);
1533 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1534 radeon_ring_write(ring, 0x00000010); /* */
1535
1536 radeon_ring_unlock_commit(rdev, ring);
1537
1538 /* XXX init other rings */
1539
1540 return 0;
1541}
1542
1543static void cayman_cp_fini(struct radeon_device *rdev)
1544{
1545 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1546 cayman_cp_enable(rdev, false);
1547 radeon_ring_fini(rdev, ring);
1548 radeon_scratch_free(rdev, ring->rptr_save_reg);
1549}
1550
1551static int cayman_cp_resume(struct radeon_device *rdev)
1552{
1553 static const int ridx[] = {
1554 RADEON_RING_TYPE_GFX_INDEX,
1555 CAYMAN_RING_TYPE_CP1_INDEX,
1556 CAYMAN_RING_TYPE_CP2_INDEX
1557 };
1558 static const unsigned cp_rb_cntl[] = {
1559 CP_RB0_CNTL,
1560 CP_RB1_CNTL,
1561 CP_RB2_CNTL,
1562 };
1563 static const unsigned cp_rb_rptr_addr[] = {
1564 CP_RB0_RPTR_ADDR,
1565 CP_RB1_RPTR_ADDR,
1566 CP_RB2_RPTR_ADDR
1567 };
1568 static const unsigned cp_rb_rptr_addr_hi[] = {
1569 CP_RB0_RPTR_ADDR_HI,
1570 CP_RB1_RPTR_ADDR_HI,
1571 CP_RB2_RPTR_ADDR_HI
1572 };
1573 static const unsigned cp_rb_base[] = {
1574 CP_RB0_BASE,
1575 CP_RB1_BASE,
1576 CP_RB2_BASE
1577 };
1578 static const unsigned cp_rb_rptr[] = {
1579 CP_RB0_RPTR,
1580 CP_RB1_RPTR,
1581 CP_RB2_RPTR
1582 };
1583 static const unsigned cp_rb_wptr[] = {
1584 CP_RB0_WPTR,
1585 CP_RB1_WPTR,
1586 CP_RB2_WPTR
1587 };
1588 struct radeon_ring *ring;
1589 int i, r;
1590
1591 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1592 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1593 SOFT_RESET_PA |
1594 SOFT_RESET_SH |
1595 SOFT_RESET_VGT |
1596 SOFT_RESET_SPI |
1597 SOFT_RESET_SX));
1598 RREG32(GRBM_SOFT_RESET);
1599 mdelay(15);
1600 WREG32(GRBM_SOFT_RESET, 0);
1601 RREG32(GRBM_SOFT_RESET);
1602
1603 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1604 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1605
1606 /* Set the write pointer delay */
1607 WREG32(CP_RB_WPTR_DELAY, 0);
1608
1609 WREG32(CP_DEBUG, (1 << 27));
1610
1611 /* set the wb address whether it's enabled or not */
1612 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1613 WREG32(SCRATCH_UMSK, 0xff);
1614
1615 for (i = 0; i < 3; ++i) {
1616 uint32_t rb_cntl;
1617 uint64_t addr;
1618
1619 /* Set ring buffer size */
1620 ring = &rdev->ring[ridx[i]];
1621 rb_cntl = order_base_2(ring->ring_size / 8);
1622 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1623#ifdef __BIG_ENDIAN
1624 rb_cntl |= BUF_SWAP_32BIT;
1625#endif
1626 WREG32(cp_rb_cntl[i], rb_cntl);
1627
1628 /* set the wb address whether it's enabled or not */
1629 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1630 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1631 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1632 }
1633
1634 /* set the rb base addr, this causes an internal reset of ALL rings */
1635 for (i = 0; i < 3; ++i) {
1636 ring = &rdev->ring[ridx[i]];
1637 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1638 }
1639
1640 for (i = 0; i < 3; ++i) {
1641 /* Initialize the ring buffer's read and write pointers */
1642 ring = &rdev->ring[ridx[i]];
1643 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1644
1645 ring->wptr = 0;
1646 WREG32(cp_rb_rptr[i], 0);
1647 WREG32(cp_rb_wptr[i], ring->wptr);
1648
1649 mdelay(1);
1650 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1651 }
1652
1653 /* start the rings */
1654 cayman_cp_start(rdev);
1655 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1656 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1657 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1658 /* this only test cp0 */
1659 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1660 if (r) {
1661 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1662 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1663 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1664 return r;
1665 }
1666
1667 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1668 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1669
1670 return 0;
1671}
1672
1673u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1674{
1675 u32 reset_mask = 0;
1676 u32 tmp;
1677
1678 /* GRBM_STATUS */
1679 tmp = RREG32(GRBM_STATUS);
1680 if (tmp & (PA_BUSY | SC_BUSY |
1681 SH_BUSY | SX_BUSY |
1682 TA_BUSY | VGT_BUSY |
1683 DB_BUSY | CB_BUSY |
1684 GDS_BUSY | SPI_BUSY |
1685 IA_BUSY | IA_BUSY_NO_DMA))
1686 reset_mask |= RADEON_RESET_GFX;
1687
1688 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1689 CP_BUSY | CP_COHERENCY_BUSY))
1690 reset_mask |= RADEON_RESET_CP;
1691
1692 if (tmp & GRBM_EE_BUSY)
1693 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1694
1695 /* DMA_STATUS_REG 0 */
1696 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1697 if (!(tmp & DMA_IDLE))
1698 reset_mask |= RADEON_RESET_DMA;
1699
1700 /* DMA_STATUS_REG 1 */
1701 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1702 if (!(tmp & DMA_IDLE))
1703 reset_mask |= RADEON_RESET_DMA1;
1704
1705 /* SRBM_STATUS2 */
1706 tmp = RREG32(SRBM_STATUS2);
1707 if (tmp & DMA_BUSY)
1708 reset_mask |= RADEON_RESET_DMA;
1709
1710 if (tmp & DMA1_BUSY)
1711 reset_mask |= RADEON_RESET_DMA1;
1712
1713 /* SRBM_STATUS */
1714 tmp = RREG32(SRBM_STATUS);
1715 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1716 reset_mask |= RADEON_RESET_RLC;
1717
1718 if (tmp & IH_BUSY)
1719 reset_mask |= RADEON_RESET_IH;
1720
1721 if (tmp & SEM_BUSY)
1722 reset_mask |= RADEON_RESET_SEM;
1723
1724 if (tmp & GRBM_RQ_PENDING)
1725 reset_mask |= RADEON_RESET_GRBM;
1726
1727 if (tmp & VMC_BUSY)
1728 reset_mask |= RADEON_RESET_VMC;
1729
1730 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1731 MCC_BUSY | MCD_BUSY))
1732 reset_mask |= RADEON_RESET_MC;
1733
1734 if (evergreen_is_display_hung(rdev))
1735 reset_mask |= RADEON_RESET_DISPLAY;
1736
1737 /* VM_L2_STATUS */
1738 tmp = RREG32(VM_L2_STATUS);
1739 if (tmp & L2_BUSY)
1740 reset_mask |= RADEON_RESET_VMC;
1741
1742 /* Skip MC reset as it's mostly likely not hung, just busy */
1743 if (reset_mask & RADEON_RESET_MC) {
1744 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1745 reset_mask &= ~RADEON_RESET_MC;
1746 }
1747
1748 return reset_mask;
1749}
1750
1751static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1752{
1753 struct evergreen_mc_save save;
1754 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1755 u32 tmp;
1756
1757 if (reset_mask == 0)
1758 return;
1759
1760 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1761
1762 evergreen_print_gpu_status_regs(rdev);
1763 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1764 RREG32(0x14F8));
1765 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1766 RREG32(0x14D8));
1767 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1768 RREG32(0x14FC));
1769 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1770 RREG32(0x14DC));
1771
1772 /* Disable CP parsing/prefetching */
1773 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1774
1775 if (reset_mask & RADEON_RESET_DMA) {
1776 /* dma0 */
1777 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1778 tmp &= ~DMA_RB_ENABLE;
1779 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1780 }
1781
1782 if (reset_mask & RADEON_RESET_DMA1) {
1783 /* dma1 */
1784 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1785 tmp &= ~DMA_RB_ENABLE;
1786 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1787 }
1788
1789 udelay(50);
1790
1791 evergreen_mc_stop(rdev, &save);
1792 if (evergreen_mc_wait_for_idle(rdev)) {
1793 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1794 }
1795
1796 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1797 grbm_soft_reset = SOFT_RESET_CB |
1798 SOFT_RESET_DB |
1799 SOFT_RESET_GDS |
1800 SOFT_RESET_PA |
1801 SOFT_RESET_SC |
1802 SOFT_RESET_SPI |
1803 SOFT_RESET_SH |
1804 SOFT_RESET_SX |
1805 SOFT_RESET_TC |
1806 SOFT_RESET_TA |
1807 SOFT_RESET_VGT |
1808 SOFT_RESET_IA;
1809 }
1810
1811 if (reset_mask & RADEON_RESET_CP) {
1812 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1813
1814 srbm_soft_reset |= SOFT_RESET_GRBM;
1815 }
1816
1817 if (reset_mask & RADEON_RESET_DMA)
1818 srbm_soft_reset |= SOFT_RESET_DMA;
1819
1820 if (reset_mask & RADEON_RESET_DMA1)
1821 srbm_soft_reset |= SOFT_RESET_DMA1;
1822
1823 if (reset_mask & RADEON_RESET_DISPLAY)
1824 srbm_soft_reset |= SOFT_RESET_DC;
1825
1826 if (reset_mask & RADEON_RESET_RLC)
1827 srbm_soft_reset |= SOFT_RESET_RLC;
1828
1829 if (reset_mask & RADEON_RESET_SEM)
1830 srbm_soft_reset |= SOFT_RESET_SEM;
1831
1832 if (reset_mask & RADEON_RESET_IH)
1833 srbm_soft_reset |= SOFT_RESET_IH;
1834
1835 if (reset_mask & RADEON_RESET_GRBM)
1836 srbm_soft_reset |= SOFT_RESET_GRBM;
1837
1838 if (reset_mask & RADEON_RESET_VMC)
1839 srbm_soft_reset |= SOFT_RESET_VMC;
1840
1841 if (!(rdev->flags & RADEON_IS_IGP)) {
1842 if (reset_mask & RADEON_RESET_MC)
1843 srbm_soft_reset |= SOFT_RESET_MC;
1844 }
1845
1846 if (grbm_soft_reset) {
1847 tmp = RREG32(GRBM_SOFT_RESET);
1848 tmp |= grbm_soft_reset;
1849 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1850 WREG32(GRBM_SOFT_RESET, tmp);
1851 tmp = RREG32(GRBM_SOFT_RESET);
1852
1853 udelay(50);
1854
1855 tmp &= ~grbm_soft_reset;
1856 WREG32(GRBM_SOFT_RESET, tmp);
1857 tmp = RREG32(GRBM_SOFT_RESET);
1858 }
1859
1860 if (srbm_soft_reset) {
1861 tmp = RREG32(SRBM_SOFT_RESET);
1862 tmp |= srbm_soft_reset;
1863 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1864 WREG32(SRBM_SOFT_RESET, tmp);
1865 tmp = RREG32(SRBM_SOFT_RESET);
1866
1867 udelay(50);
1868
1869 tmp &= ~srbm_soft_reset;
1870 WREG32(SRBM_SOFT_RESET, tmp);
1871 tmp = RREG32(SRBM_SOFT_RESET);
1872 }
1873
1874 /* Wait a little for things to settle down */
1875 udelay(50);
1876
1877 evergreen_mc_resume(rdev, &save);
1878 udelay(50);
1879
1880 evergreen_print_gpu_status_regs(rdev);
1881}
1882
1883int cayman_asic_reset(struct radeon_device *rdev)
1884{
1885 u32 reset_mask;
1886
1887 reset_mask = cayman_gpu_check_soft_reset(rdev);
1888
1889 if (reset_mask)
1890 r600_set_bios_scratch_engine_hung(rdev, true);
1891
1892 cayman_gpu_soft_reset(rdev, reset_mask);
1893
1894 reset_mask = cayman_gpu_check_soft_reset(rdev);
1895
1896 if (reset_mask)
1897 evergreen_gpu_pci_config_reset(rdev);
1898
1899 r600_set_bios_scratch_engine_hung(rdev, false);
1900
1901 return 0;
1902}
1903
1904/**
1905 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1906 *
1907 * @rdev: radeon_device pointer
1908 * @ring: radeon_ring structure holding ring information
1909 *
1910 * Check if the GFX engine is locked up.
1911 * Returns true if the engine appears to be locked up, false if not.
1912 */
1913bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1914{
1915 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1916
1917 if (!(reset_mask & (RADEON_RESET_GFX |
1918 RADEON_RESET_COMPUTE |
1919 RADEON_RESET_CP))) {
1920 radeon_ring_lockup_update(rdev, ring);
1921 return false;
1922 }
1923 return radeon_ring_test_lockup(rdev, ring);
1924}
1925
1926static int cayman_startup(struct radeon_device *rdev)
1927{
1928 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1929 int r;
1930
1931 /* enable pcie gen2 link */
1932 evergreen_pcie_gen2_enable(rdev);
1933 /* enable aspm */
1934 evergreen_program_aspm(rdev);
1935
1936 /* scratch needs to be initialized before MC */
1937 r = r600_vram_scratch_init(rdev);
1938 if (r)
1939 return r;
1940
1941 evergreen_mc_program(rdev);
1942
1943 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
1944 r = ni_mc_load_microcode(rdev);
1945 if (r) {
1946 DRM_ERROR("Failed to load MC firmware!\n");
1947 return r;
1948 }
1949 }
1950
1951 r = cayman_pcie_gart_enable(rdev);
1952 if (r)
1953 return r;
1954 cayman_gpu_init(rdev);
1955
1956 /* allocate rlc buffers */
1957 if (rdev->flags & RADEON_IS_IGP) {
1958 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
1959 rdev->rlc.reg_list_size =
1960 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
1961 rdev->rlc.cs_data = cayman_cs_data;
1962 r = sumo_rlc_init(rdev);
1963 if (r) {
1964 DRM_ERROR("Failed to init rlc BOs!\n");
1965 return r;
1966 }
1967 }
1968
1969 /* allocate wb buffer */
1970 r = radeon_wb_init(rdev);
1971 if (r)
1972 return r;
1973
1974 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1975 if (r) {
1976 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1977 return r;
1978 }
1979
1980 r = uvd_v2_2_resume(rdev);
1981 if (!r) {
1982 r = radeon_fence_driver_start_ring(rdev,
1983 R600_RING_TYPE_UVD_INDEX);
1984 if (r)
1985 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1986 }
1987 if (r)
1988 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1989
1990 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1991 if (r) {
1992 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1993 return r;
1994 }
1995
1996 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1997 if (r) {
1998 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1999 return r;
2000 }
2001
2002 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2003 if (r) {
2004 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2005 return r;
2006 }
2007
2008 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
2009 if (r) {
2010 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2011 return r;
2012 }
2013
2014 /* Enable IRQ */
2015 if (!rdev->irq.installed) {
2016 r = radeon_irq_kms_init(rdev);
2017 if (r)
2018 return r;
2019 }
2020
2021 r = r600_irq_init(rdev);
2022 if (r) {
2023 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2024 radeon_irq_kms_fini(rdev);
2025 return r;
2026 }
2027 evergreen_irq_set(rdev);
2028
2029 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2030 RADEON_CP_PACKET2);
2031 if (r)
2032 return r;
2033
2034 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2035 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2036 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2037 if (r)
2038 return r;
2039
2040 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2041 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
2042 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2043 if (r)
2044 return r;
2045
2046 r = cayman_cp_load_microcode(rdev);
2047 if (r)
2048 return r;
2049 r = cayman_cp_resume(rdev);
2050 if (r)
2051 return r;
2052
2053 r = cayman_dma_resume(rdev);
2054 if (r)
2055 return r;
2056
2057 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2058 if (ring->ring_size) {
2059 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
2060 RADEON_CP_PACKET2);
2061 if (!r)
2062 r = uvd_v1_0_init(rdev);
2063 if (r)
2064 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
2065 }
2066
2067 r = radeon_ib_pool_init(rdev);
2068 if (r) {
2069 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2070 return r;
2071 }
2072
2073 r = radeon_vm_manager_init(rdev);
2074 if (r) {
2075 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2076 return r;
2077 }
2078
2079 if (ASIC_IS_DCE6(rdev)) {
2080 r = dce6_audio_init(rdev);
2081 if (r)
2082 return r;
2083 } else {
2084 r = r600_audio_init(rdev);
2085 if (r)
2086 return r;
2087 }
2088
2089 return 0;
2090}
2091
2092int cayman_resume(struct radeon_device *rdev)
2093{
2094 int r;
2095
2096 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2097 * posting will perform necessary task to bring back GPU into good
2098 * shape.
2099 */
2100 /* post card */
2101 atom_asic_init(rdev->mode_info.atom_context);
2102
2103 /* init golden registers */
2104 ni_init_golden_registers(rdev);
2105
2106 if (rdev->pm.pm_method == PM_METHOD_DPM)
2107 radeon_pm_resume(rdev);
2108
2109 rdev->accel_working = true;
2110 r = cayman_startup(rdev);
2111 if (r) {
2112 DRM_ERROR("cayman startup failed on resume\n");
2113 rdev->accel_working = false;
2114 return r;
2115 }
2116 return r;
2117}
2118
2119int cayman_suspend(struct radeon_device *rdev)
2120{
2121 radeon_pm_suspend(rdev);
2122 if (ASIC_IS_DCE6(rdev))
2123 dce6_audio_fini(rdev);
2124 else
2125 r600_audio_fini(rdev);
2126 radeon_vm_manager_fini(rdev);
2127 cayman_cp_enable(rdev, false);
2128 cayman_dma_stop(rdev);
2129 uvd_v1_0_fini(rdev);
2130 radeon_uvd_suspend(rdev);
2131 evergreen_irq_suspend(rdev);
2132 radeon_wb_disable(rdev);
2133 cayman_pcie_gart_disable(rdev);
2134 return 0;
2135}
2136
2137/* Plan is to move initialization in that function and use
2138 * helper function so that radeon_device_init pretty much
2139 * do nothing more than calling asic specific function. This
2140 * should also allow to remove a bunch of callback function
2141 * like vram_info.
2142 */
2143int cayman_init(struct radeon_device *rdev)
2144{
2145 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2146 int r;
2147
2148 /* Read BIOS */
2149 if (!radeon_get_bios(rdev)) {
2150 if (ASIC_IS_AVIVO(rdev))
2151 return -EINVAL;
2152 }
2153 /* Must be an ATOMBIOS */
2154 if (!rdev->is_atom_bios) {
2155 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2156 return -EINVAL;
2157 }
2158 r = radeon_atombios_init(rdev);
2159 if (r)
2160 return r;
2161
2162 /* Post card if necessary */
2163 if (!radeon_card_posted(rdev)) {
2164 if (!rdev->bios) {
2165 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2166 return -EINVAL;
2167 }
2168 DRM_INFO("GPU not posted. posting now...\n");
2169 atom_asic_init(rdev->mode_info.atom_context);
2170 }
2171 /* init golden registers */
2172 ni_init_golden_registers(rdev);
2173 /* Initialize scratch registers */
2174 r600_scratch_init(rdev);
2175 /* Initialize surface registers */
2176 radeon_surface_init(rdev);
2177 /* Initialize clocks */
2178 radeon_get_clock_info(rdev->ddev);
2179 /* Fence driver */
2180 r = radeon_fence_driver_init(rdev);
2181 if (r)
2182 return r;
2183 /* initialize memory controller */
2184 r = evergreen_mc_init(rdev);
2185 if (r)
2186 return r;
2187 /* Memory manager */
2188 r = radeon_bo_init(rdev);
2189 if (r)
2190 return r;
2191
2192 if (rdev->flags & RADEON_IS_IGP) {
2193 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2194 r = ni_init_microcode(rdev);
2195 if (r) {
2196 DRM_ERROR("Failed to load firmware!\n");
2197 return r;
2198 }
2199 }
2200 } else {
2201 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2202 r = ni_init_microcode(rdev);
2203 if (r) {
2204 DRM_ERROR("Failed to load firmware!\n");
2205 return r;
2206 }
2207 }
2208 }
2209
2210 /* Initialize power management */
2211 radeon_pm_init(rdev);
2212
2213 ring->ring_obj = NULL;
2214 r600_ring_init(rdev, ring, 1024 * 1024);
2215
2216 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2217 ring->ring_obj = NULL;
2218 r600_ring_init(rdev, ring, 64 * 1024);
2219
2220 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2221 ring->ring_obj = NULL;
2222 r600_ring_init(rdev, ring, 64 * 1024);
2223
2224 r = radeon_uvd_init(rdev);
2225 if (!r) {
2226 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2227 ring->ring_obj = NULL;
2228 r600_ring_init(rdev, ring, 4096);
2229 }
2230
2231 rdev->ih.ring_obj = NULL;
2232 r600_ih_ring_init(rdev, 64 * 1024);
2233
2234 r = r600_pcie_gart_init(rdev);
2235 if (r)
2236 return r;
2237
2238 rdev->accel_working = true;
2239 r = cayman_startup(rdev);
2240 if (r) {
2241 dev_err(rdev->dev, "disabling GPU acceleration\n");
2242 cayman_cp_fini(rdev);
2243 cayman_dma_fini(rdev);
2244 r600_irq_fini(rdev);
2245 if (rdev->flags & RADEON_IS_IGP)
2246 sumo_rlc_fini(rdev);
2247 radeon_wb_fini(rdev);
2248 radeon_ib_pool_fini(rdev);
2249 radeon_vm_manager_fini(rdev);
2250 radeon_irq_kms_fini(rdev);
2251 cayman_pcie_gart_fini(rdev);
2252 rdev->accel_working = false;
2253 }
2254
2255 /* Don't start up if the MC ucode is missing.
2256 * The default clocks and voltages before the MC ucode
2257 * is loaded are not suffient for advanced operations.
2258 *
2259 * We can skip this check for TN, because there is no MC
2260 * ucode.
2261 */
2262 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2263 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2264 return -EINVAL;
2265 }
2266
2267 return 0;
2268}
2269
2270void cayman_fini(struct radeon_device *rdev)
2271{
2272 radeon_pm_fini(rdev);
2273 cayman_cp_fini(rdev);
2274 cayman_dma_fini(rdev);
2275 r600_irq_fini(rdev);
2276 if (rdev->flags & RADEON_IS_IGP)
2277 sumo_rlc_fini(rdev);
2278 radeon_wb_fini(rdev);
2279 radeon_vm_manager_fini(rdev);
2280 radeon_ib_pool_fini(rdev);
2281 radeon_irq_kms_fini(rdev);
2282 uvd_v1_0_fini(rdev);
2283 radeon_uvd_fini(rdev);
2284 cayman_pcie_gart_fini(rdev);
2285 r600_vram_scratch_fini(rdev);
2286 radeon_gem_fini(rdev);
2287 radeon_fence_driver_fini(rdev);
2288 radeon_bo_fini(rdev);
2289 radeon_atombios_fini(rdev);
2290 kfree(rdev->bios);
2291 rdev->bios = NULL;
2292}
2293
2294/*
2295 * vm
2296 */
2297int cayman_vm_init(struct radeon_device *rdev)
2298{
2299 /* number of VMs */
2300 rdev->vm_manager.nvm = 8;
2301 /* base offset of vram pages */
2302 if (rdev->flags & RADEON_IS_IGP) {
2303 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2304 tmp <<= 22;
2305 rdev->vm_manager.vram_base_offset = tmp;
2306 } else
2307 rdev->vm_manager.vram_base_offset = 0;
2308 return 0;
2309}
2310
2311void cayman_vm_fini(struct radeon_device *rdev)
2312{
2313}
2314
2315/**
2316 * cayman_vm_decode_fault - print human readable fault info
2317 *
2318 * @rdev: radeon_device pointer
2319 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2320 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2321 *
2322 * Print human readable fault information (cayman/TN).
2323 */
2324void cayman_vm_decode_fault(struct radeon_device *rdev,
2325 u32 status, u32 addr)
2326{
2327 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2328 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2329 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2330 char *block;
2331
2332 switch (mc_id) {
2333 case 32:
2334 case 16:
2335 case 96:
2336 case 80:
2337 case 160:
2338 case 144:
2339 case 224:
2340 case 208:
2341 block = "CB";
2342 break;
2343 case 33:
2344 case 17:
2345 case 97:
2346 case 81:
2347 case 161:
2348 case 145:
2349 case 225:
2350 case 209:
2351 block = "CB_FMASK";
2352 break;
2353 case 34:
2354 case 18:
2355 case 98:
2356 case 82:
2357 case 162:
2358 case 146:
2359 case 226:
2360 case 210:
2361 block = "CB_CMASK";
2362 break;
2363 case 35:
2364 case 19:
2365 case 99:
2366 case 83:
2367 case 163:
2368 case 147:
2369 case 227:
2370 case 211:
2371 block = "CB_IMMED";
2372 break;
2373 case 36:
2374 case 20:
2375 case 100:
2376 case 84:
2377 case 164:
2378 case 148:
2379 case 228:
2380 case 212:
2381 block = "DB";
2382 break;
2383 case 37:
2384 case 21:
2385 case 101:
2386 case 85:
2387 case 165:
2388 case 149:
2389 case 229:
2390 case 213:
2391 block = "DB_HTILE";
2392 break;
2393 case 38:
2394 case 22:
2395 case 102:
2396 case 86:
2397 case 166:
2398 case 150:
2399 case 230:
2400 case 214:
2401 block = "SX";
2402 break;
2403 case 39:
2404 case 23:
2405 case 103:
2406 case 87:
2407 case 167:
2408 case 151:
2409 case 231:
2410 case 215:
2411 block = "DB_STEN";
2412 break;
2413 case 40:
2414 case 24:
2415 case 104:
2416 case 88:
2417 case 232:
2418 case 216:
2419 case 168:
2420 case 152:
2421 block = "TC_TFETCH";
2422 break;
2423 case 41:
2424 case 25:
2425 case 105:
2426 case 89:
2427 case 233:
2428 case 217:
2429 case 169:
2430 case 153:
2431 block = "TC_VFETCH";
2432 break;
2433 case 42:
2434 case 26:
2435 case 106:
2436 case 90:
2437 case 234:
2438 case 218:
2439 case 170:
2440 case 154:
2441 block = "VC";
2442 break;
2443 case 112:
2444 block = "CP";
2445 break;
2446 case 113:
2447 case 114:
2448 block = "SH";
2449 break;
2450 case 115:
2451 block = "VGT";
2452 break;
2453 case 178:
2454 block = "IH";
2455 break;
2456 case 51:
2457 block = "RLC";
2458 break;
2459 case 55:
2460 block = "DMA";
2461 break;
2462 case 56:
2463 block = "HDP";
2464 break;
2465 default:
2466 block = "unknown";
2467 break;
2468 }
2469
2470 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2471 protections, vmid, addr,
2472 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2473 block, mc_id);
2474}
2475
2476/**
2477 * cayman_vm_flush - vm flush using the CP
2478 *
2479 * @rdev: radeon_device pointer
2480 *
2481 * Update the page table base and flush the VM TLB
2482 * using the CP (cayman-si).
2483 */
2484void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2485{
2486 struct radeon_ring *ring = &rdev->ring[ridx];
2487
2488 if (vm == NULL)
2489 return;
2490
2491 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
2492 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2493
2494 /* flush hdp cache */
2495 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2496 radeon_ring_write(ring, 0x1);
2497
2498 /* bits 0-7 are the VM contexts0-7 */
2499 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2500 radeon_ring_write(ring, 1 << vm->id);
2501
2502 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2503 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2504 radeon_ring_write(ring, 0x0);
2505}