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1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef NI_H
25#define NI_H
26
27#define CAYMAN_MAX_SH_GPRS 256
28#define CAYMAN_MAX_TEMP_GPRS 16
29#define CAYMAN_MAX_SH_THREADS 256
30#define CAYMAN_MAX_SH_STACK_ENTRIES 4096
31#define CAYMAN_MAX_FRC_EOV_CNT 16384
32#define CAYMAN_MAX_BACKENDS 8
33#define CAYMAN_MAX_BACKENDS_MASK 0xFF
34#define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
35#define CAYMAN_MAX_SIMDS 16
36#define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37#define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
38#define CAYMAN_MAX_PIPES 8
39#define CAYMAN_MAX_PIPES_MASK 0xFF
40#define CAYMAN_MAX_LDS_NUM 0xFFFF
41#define CAYMAN_MAX_TCC 16
42#define CAYMAN_MAX_TCC_MASK 0xFF
43
44#define DMIF_ADDR_CONFIG 0xBD4
45#define SRBM_STATUS 0x0E50
46
47#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
48#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
49#define RESPONSE_TYPE_MASK 0x000000F0
50#define RESPONSE_TYPE_SHIFT 4
51#define VM_L2_CNTL 0x1400
52#define ENABLE_L2_CACHE (1 << 0)
53#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
54#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
55#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
56#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
57#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18)
58/* CONTEXT1_IDENTITY_ACCESS_MODE
59 * 0 physical = logical
60 * 1 logical via context1 page table
61 * 2 inside identity aperture use translation, outside physical = logical
62 * 3 inside identity aperture physical = logical, outside use translation
63 */
64#define VM_L2_CNTL2 0x1404
65#define INVALIDATE_ALL_L1_TLBS (1 << 0)
66#define INVALIDATE_L2_CACHE (1 << 1)
67#define VM_L2_CNTL3 0x1408
68#define BANK_SELECT(x) ((x) << 0)
69#define CACHE_UPDATE_MODE(x) ((x) << 6)
70#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
71#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
72#define VM_L2_STATUS 0x140C
73#define L2_BUSY (1 << 0)
74#define VM_CONTEXT0_CNTL 0x1410
75#define ENABLE_CONTEXT (1 << 0)
76#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
77#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
78#define VM_CONTEXT1_CNTL 0x1414
79#define VM_CONTEXT0_CNTL2 0x1430
80#define VM_CONTEXT1_CNTL2 0x1434
81#define VM_INVALIDATE_REQUEST 0x1478
82#define VM_INVALIDATE_RESPONSE 0x147c
83#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
84#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
85#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
86#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
87#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
88
89#define MC_SHARED_CHMAP 0x2004
90#define NOOFCHAN_SHIFT 12
91#define NOOFCHAN_MASK 0x00003000
92#define MC_SHARED_CHREMAP 0x2008
93
94#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
95#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
96#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
97#define MC_VM_MX_L1_TLB_CNTL 0x2064
98#define ENABLE_L1_TLB (1 << 0)
99#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
100#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
101#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
102#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
103#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
104#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
105#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
106
107#define MC_SHARED_BLACKOUT_CNTL 0x20ac
108#define MC_ARB_RAMCFG 0x2760
109#define NOOFBANK_SHIFT 0
110#define NOOFBANK_MASK 0x00000003
111#define NOOFRANK_SHIFT 2
112#define NOOFRANK_MASK 0x00000004
113#define NOOFROWS_SHIFT 3
114#define NOOFROWS_MASK 0x00000038
115#define NOOFCOLS_SHIFT 6
116#define NOOFCOLS_MASK 0x000000C0
117#define CHANSIZE_SHIFT 8
118#define CHANSIZE_MASK 0x00000100
119#define BURSTLENGTH_SHIFT 9
120#define BURSTLENGTH_MASK 0x00000200
121#define CHANSIZE_OVERRIDE (1 << 11)
122#define MC_SEQ_SUP_CNTL 0x28c8
123#define RUN_MASK (1 << 0)
124#define MC_SEQ_SUP_PGM 0x28cc
125#define MC_IO_PAD_CNTL_D0 0x29d0
126#define MEM_FALL_OUT_CMD (1 << 8)
127#define MC_SEQ_MISC0 0x2a00
128#define MC_SEQ_MISC0_GDDR5_SHIFT 28
129#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
130#define MC_SEQ_MISC0_GDDR5_VALUE 5
131#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
132#define MC_SEQ_IO_DEBUG_DATA 0x2a48
133
134#define HDP_HOST_PATH_CNTL 0x2C00
135#define HDP_NONSURFACE_BASE 0x2C04
136#define HDP_NONSURFACE_INFO 0x2C08
137#define HDP_NONSURFACE_SIZE 0x2C0C
138#define HDP_ADDR_CONFIG 0x2F48
139#define HDP_MISC_CNTL 0x2F4C
140#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
141
142#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
143#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
144#define CGTS_SYS_TCC_DISABLE 0x3F90
145#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
146
147#define CONFIG_MEMSIZE 0x5428
148
149#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
150#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
151
152#define GRBM_CNTL 0x8000
153#define GRBM_READ_TIMEOUT(x) ((x) << 0)
154#define GRBM_STATUS 0x8010
155#define CMDFIFO_AVAIL_MASK 0x0000000F
156#define RING2_RQ_PENDING (1 << 4)
157#define SRBM_RQ_PENDING (1 << 5)
158#define RING1_RQ_PENDING (1 << 6)
159#define CF_RQ_PENDING (1 << 7)
160#define PF_RQ_PENDING (1 << 8)
161#define GDS_DMA_RQ_PENDING (1 << 9)
162#define GRBM_EE_BUSY (1 << 10)
163#define SX_CLEAN (1 << 11)
164#define DB_CLEAN (1 << 12)
165#define CB_CLEAN (1 << 13)
166#define TA_BUSY (1 << 14)
167#define GDS_BUSY (1 << 15)
168#define VGT_BUSY_NO_DMA (1 << 16)
169#define VGT_BUSY (1 << 17)
170#define IA_BUSY_NO_DMA (1 << 18)
171#define IA_BUSY (1 << 19)
172#define SX_BUSY (1 << 20)
173#define SH_BUSY (1 << 21)
174#define SPI_BUSY (1 << 22)
175#define SC_BUSY (1 << 24)
176#define PA_BUSY (1 << 25)
177#define DB_BUSY (1 << 26)
178#define CP_COHERENCY_BUSY (1 << 28)
179#define CP_BUSY (1 << 29)
180#define CB_BUSY (1 << 30)
181#define GUI_ACTIVE (1 << 31)
182#define GRBM_STATUS_SE0 0x8014
183#define GRBM_STATUS_SE1 0x8018
184#define SE_SX_CLEAN (1 << 0)
185#define SE_DB_CLEAN (1 << 1)
186#define SE_CB_CLEAN (1 << 2)
187#define SE_VGT_BUSY (1 << 23)
188#define SE_PA_BUSY (1 << 24)
189#define SE_TA_BUSY (1 << 25)
190#define SE_SX_BUSY (1 << 26)
191#define SE_SPI_BUSY (1 << 27)
192#define SE_SH_BUSY (1 << 28)
193#define SE_SC_BUSY (1 << 29)
194#define SE_DB_BUSY (1 << 30)
195#define SE_CB_BUSY (1 << 31)
196#define GRBM_SOFT_RESET 0x8020
197#define SOFT_RESET_CP (1 << 0)
198#define SOFT_RESET_CB (1 << 1)
199#define SOFT_RESET_DB (1 << 3)
200#define SOFT_RESET_GDS (1 << 4)
201#define SOFT_RESET_PA (1 << 5)
202#define SOFT_RESET_SC (1 << 6)
203#define SOFT_RESET_SPI (1 << 8)
204#define SOFT_RESET_SH (1 << 9)
205#define SOFT_RESET_SX (1 << 10)
206#define SOFT_RESET_TC (1 << 11)
207#define SOFT_RESET_TA (1 << 12)
208#define SOFT_RESET_VGT (1 << 14)
209#define SOFT_RESET_IA (1 << 15)
210
211#define SCRATCH_REG0 0x8500
212#define SCRATCH_REG1 0x8504
213#define SCRATCH_REG2 0x8508
214#define SCRATCH_REG3 0x850C
215#define SCRATCH_REG4 0x8510
216#define SCRATCH_REG5 0x8514
217#define SCRATCH_REG6 0x8518
218#define SCRATCH_REG7 0x851C
219#define SCRATCH_UMSK 0x8540
220#define SCRATCH_ADDR 0x8544
221#define CP_SEM_WAIT_TIMER 0x85BC
222#define CP_ME_CNTL 0x86D8
223#define CP_ME_HALT (1 << 28)
224#define CP_PFP_HALT (1 << 26)
225#define CP_RB2_RPTR 0x86f8
226#define CP_RB1_RPTR 0x86fc
227#define CP_RB0_RPTR 0x8700
228#define CP_RB_WPTR_DELAY 0x8704
229#define CP_MEQ_THRESHOLDS 0x8764
230#define MEQ1_START(x) ((x) << 0)
231#define MEQ2_START(x) ((x) << 8)
232#define CP_PERFMON_CNTL 0x87FC
233
234#define VGT_CACHE_INVALIDATION 0x88C4
235#define CACHE_INVALIDATION(x) ((x) << 0)
236#define VC_ONLY 0
237#define TC_ONLY 1
238#define VC_AND_TC 2
239#define AUTO_INVLD_EN(x) ((x) << 6)
240#define NO_AUTO 0
241#define ES_AUTO 1
242#define GS_AUTO 2
243#define ES_AND_GS_AUTO 3
244#define VGT_GS_VERTEX_REUSE 0x88D4
245
246#define CC_GC_SHADER_PIPE_CONFIG 0x8950
247#define GC_USER_SHADER_PIPE_CONFIG 0x8954
248#define INACTIVE_QD_PIPES(x) ((x) << 8)
249#define INACTIVE_QD_PIPES_MASK 0x0000FF00
250#define INACTIVE_QD_PIPES_SHIFT 8
251#define INACTIVE_SIMDS(x) ((x) << 16)
252#define INACTIVE_SIMDS_MASK 0xFFFF0000
253#define INACTIVE_SIMDS_SHIFT 16
254
255#define VGT_PRIMITIVE_TYPE 0x8958
256#define VGT_NUM_INSTANCES 0x8974
257#define VGT_TF_RING_SIZE 0x8988
258#define VGT_OFFCHIP_LDS_BASE 0x89b4
259
260#define PA_SC_LINE_STIPPLE_STATE 0x8B10
261#define PA_CL_ENHANCE 0x8A14
262#define CLIP_VTX_REORDER_ENA (1 << 0)
263#define NUM_CLIP_SEQ(x) ((x) << 1)
264#define PA_SC_FIFO_SIZE 0x8BCC
265#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
266#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
267#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
268#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
269#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
270#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
271
272#define SQ_CONFIG 0x8C00
273#define VC_ENABLE (1 << 0)
274#define EXPORT_SRC_C (1 << 1)
275#define GFX_PRIO(x) ((x) << 2)
276#define CS1_PRIO(x) ((x) << 4)
277#define CS2_PRIO(x) ((x) << 6)
278#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
279#define NUM_PS_GPRS(x) ((x) << 0)
280#define NUM_VS_GPRS(x) ((x) << 16)
281#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
282#define SQ_ESGS_RING_SIZE 0x8c44
283#define SQ_GSVS_RING_SIZE 0x8c4c
284#define SQ_ESTMP_RING_BASE 0x8c50
285#define SQ_ESTMP_RING_SIZE 0x8c54
286#define SQ_GSTMP_RING_BASE 0x8c58
287#define SQ_GSTMP_RING_SIZE 0x8c5c
288#define SQ_VSTMP_RING_BASE 0x8c60
289#define SQ_VSTMP_RING_SIZE 0x8c64
290#define SQ_PSTMP_RING_BASE 0x8c68
291#define SQ_PSTMP_RING_SIZE 0x8c6c
292#define SQ_MS_FIFO_SIZES 0x8CF0
293#define CACHE_FIFO_SIZE(x) ((x) << 0)
294#define FETCH_FIFO_HIWATER(x) ((x) << 8)
295#define DONE_FIFO_HIWATER(x) ((x) << 16)
296#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
297#define SQ_LSTMP_RING_BASE 0x8e10
298#define SQ_LSTMP_RING_SIZE 0x8e14
299#define SQ_HSTMP_RING_BASE 0x8e18
300#define SQ_HSTMP_RING_SIZE 0x8e1c
301#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
302#define DYN_GPR_ENABLE (1 << 8)
303#define SQ_CONST_MEM_BASE 0x8df8
304
305#define SX_EXPORT_BUFFER_SIZES 0x900C
306#define COLOR_BUFFER_SIZE(x) ((x) << 0)
307#define POSITION_BUFFER_SIZE(x) ((x) << 8)
308#define SMX_BUFFER_SIZE(x) ((x) << 16)
309#define SX_DEBUG_1 0x9058
310#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
311
312#define SPI_CONFIG_CNTL 0x9100
313#define GPR_WRITE_PRIORITY(x) ((x) << 0)
314#define SPI_CONFIG_CNTL_1 0x913C
315#define VTX_DONE_DELAY(x) ((x) << 0)
316#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
317#define CRC_SIMD_ID_WADDR_DISABLE (1 << 8)
318
319#define CGTS_TCC_DISABLE 0x9148
320#define CGTS_USER_TCC_DISABLE 0x914C
321#define TCC_DISABLE_MASK 0xFFFF0000
322#define TCC_DISABLE_SHIFT 16
323#define CGTS_SM_CTRL_REG 0x9150
324#define OVERRIDE (1 << 21)
325
326#define TA_CNTL_AUX 0x9508
327#define DISABLE_CUBE_WRAP (1 << 0)
328#define DISABLE_CUBE_ANISO (1 << 1)
329
330#define TCP_CHAN_STEER_LO 0x960c
331#define TCP_CHAN_STEER_HI 0x9610
332
333#define CC_RB_BACKEND_DISABLE 0x98F4
334#define BACKEND_DISABLE(x) ((x) << 16)
335#define GB_ADDR_CONFIG 0x98F8
336#define NUM_PIPES(x) ((x) << 0)
337#define NUM_PIPES_MASK 0x00000007
338#define NUM_PIPES_SHIFT 0
339#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
340#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
341#define PIPE_INTERLEAVE_SIZE_SHIFT 4
342#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
343#define NUM_SHADER_ENGINES(x) ((x) << 12)
344#define NUM_SHADER_ENGINES_MASK 0x00003000
345#define NUM_SHADER_ENGINES_SHIFT 12
346#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
347#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
348#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
349#define NUM_GPUS(x) ((x) << 20)
350#define NUM_GPUS_MASK 0x00700000
351#define NUM_GPUS_SHIFT 20
352#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
353#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
354#define MULTI_GPU_TILE_SIZE_SHIFT 24
355#define ROW_SIZE(x) ((x) << 28)
356#define ROW_SIZE_MASK 0x30000000
357#define ROW_SIZE_SHIFT 28
358#define NUM_LOWER_PIPES(x) ((x) << 30)
359#define NUM_LOWER_PIPES_MASK 0x40000000
360#define NUM_LOWER_PIPES_SHIFT 30
361#define GB_BACKEND_MAP 0x98FC
362
363#define CB_PERF_CTR0_SEL_0 0x9A20
364#define CB_PERF_CTR0_SEL_1 0x9A24
365#define CB_PERF_CTR1_SEL_0 0x9A28
366#define CB_PERF_CTR1_SEL_1 0x9A2C
367#define CB_PERF_CTR2_SEL_0 0x9A30
368#define CB_PERF_CTR2_SEL_1 0x9A34
369#define CB_PERF_CTR3_SEL_0 0x9A38
370#define CB_PERF_CTR3_SEL_1 0x9A3C
371
372#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
373#define BACKEND_DISABLE_MASK 0x00FF0000
374#define BACKEND_DISABLE_SHIFT 16
375
376#define SMX_DC_CTL0 0xA020
377#define USE_HASH_FUNCTION (1 << 0)
378#define NUMBER_OF_SETS(x) ((x) << 1)
379#define FLUSH_ALL_ON_EVENT (1 << 10)
380#define STALL_ON_EVENT (1 << 11)
381#define SMX_EVENT_CTL 0xA02C
382#define ES_FLUSH_CTL(x) ((x) << 0)
383#define GS_FLUSH_CTL(x) ((x) << 3)
384#define ACK_FLUSH_CTL(x) ((x) << 6)
385#define SYNC_FLUSH_CTL (1 << 8)
386
387#define CP_RB0_BASE 0xC100
388#define CP_RB0_CNTL 0xC104
389#define RB_BUFSZ(x) ((x) << 0)
390#define RB_BLKSZ(x) ((x) << 8)
391#define RB_NO_UPDATE (1 << 27)
392#define RB_RPTR_WR_ENA (1 << 31)
393#define BUF_SWAP_32BIT (2 << 16)
394#define CP_RB0_RPTR_ADDR 0xC10C
395#define CP_RB0_RPTR_ADDR_HI 0xC110
396#define CP_RB0_WPTR 0xC114
397#define CP_RB1_BASE 0xC180
398#define CP_RB1_CNTL 0xC184
399#define CP_RB1_RPTR_ADDR 0xC188
400#define CP_RB1_RPTR_ADDR_HI 0xC18C
401#define CP_RB1_WPTR 0xC190
402#define CP_RB2_BASE 0xC194
403#define CP_RB2_CNTL 0xC198
404#define CP_RB2_RPTR_ADDR 0xC19C
405#define CP_RB2_RPTR_ADDR_HI 0xC1A0
406#define CP_RB2_WPTR 0xC1A4
407#define CP_PFP_UCODE_ADDR 0xC150
408#define CP_PFP_UCODE_DATA 0xC154
409#define CP_ME_RAM_RADDR 0xC158
410#define CP_ME_RAM_WADDR 0xC15C
411#define CP_ME_RAM_DATA 0xC160
412#define CP_DEBUG 0xC1FC
413
414/*
415 * PM4
416 */
417#define PACKET_TYPE0 0
418#define PACKET_TYPE1 1
419#define PACKET_TYPE2 2
420#define PACKET_TYPE3 3
421
422#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
423#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
424#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
425#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
426#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
427 (((reg) >> 2) & 0xFFFF) | \
428 ((n) & 0x3FFF) << 16)
429#define CP_PACKET2 0x80000000
430#define PACKET2_PAD_SHIFT 0
431#define PACKET2_PAD_MASK (0x3fffffff << 0)
432
433#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
434
435#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
436 (((op) & 0xFF) << 8) | \
437 ((n) & 0x3FFF) << 16)
438
439/* Packet 3 types */
440#define PACKET3_NOP 0x10
441#define PACKET3_SET_BASE 0x11
442#define PACKET3_CLEAR_STATE 0x12
443#define PACKET3_INDEX_BUFFER_SIZE 0x13
444#define PACKET3_DEALLOC_STATE 0x14
445#define PACKET3_DISPATCH_DIRECT 0x15
446#define PACKET3_DISPATCH_INDIRECT 0x16
447#define PACKET3_INDIRECT_BUFFER_END 0x17
448#define PACKET3_SET_PREDICATION 0x20
449#define PACKET3_REG_RMW 0x21
450#define PACKET3_COND_EXEC 0x22
451#define PACKET3_PRED_EXEC 0x23
452#define PACKET3_DRAW_INDIRECT 0x24
453#define PACKET3_DRAW_INDEX_INDIRECT 0x25
454#define PACKET3_INDEX_BASE 0x26
455#define PACKET3_DRAW_INDEX_2 0x27
456#define PACKET3_CONTEXT_CONTROL 0x28
457#define PACKET3_DRAW_INDEX_OFFSET 0x29
458#define PACKET3_INDEX_TYPE 0x2A
459#define PACKET3_DRAW_INDEX 0x2B
460#define PACKET3_DRAW_INDEX_AUTO 0x2D
461#define PACKET3_DRAW_INDEX_IMMD 0x2E
462#define PACKET3_NUM_INSTANCES 0x2F
463#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
464#define PACKET3_INDIRECT_BUFFER 0x32
465#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
466#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
467#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
468#define PACKET3_WRITE_DATA 0x37
469#define PACKET3_MEM_SEMAPHORE 0x39
470#define PACKET3_MPEG_INDEX 0x3A
471#define PACKET3_WAIT_REG_MEM 0x3C
472#define PACKET3_MEM_WRITE 0x3D
473#define PACKET3_SURFACE_SYNC 0x43
474# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
475# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
476# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
477# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
478# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
479# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
480# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
481# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
482# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
483# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
484# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
485# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
486# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
487# define PACKET3_FULL_CACHE_ENA (1 << 20)
488# define PACKET3_TC_ACTION_ENA (1 << 23)
489# define PACKET3_CB_ACTION_ENA (1 << 25)
490# define PACKET3_DB_ACTION_ENA (1 << 26)
491# define PACKET3_SH_ACTION_ENA (1 << 27)
492# define PACKET3_SX_ACTION_ENA (1 << 28)
493#define PACKET3_ME_INITIALIZE 0x44
494#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
495#define PACKET3_COND_WRITE 0x45
496#define PACKET3_EVENT_WRITE 0x46
497#define PACKET3_EVENT_WRITE_EOP 0x47
498#define PACKET3_EVENT_WRITE_EOS 0x48
499#define PACKET3_PREAMBLE_CNTL 0x4A
500# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
501# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
502#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
503#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
504#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
505#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
506#define PACKET3_ONE_REG_WRITE 0x57
507#define PACKET3_SET_CONFIG_REG 0x68
508#define PACKET3_SET_CONFIG_REG_START 0x00008000
509#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
510#define PACKET3_SET_CONTEXT_REG 0x69
511#define PACKET3_SET_CONTEXT_REG_START 0x00028000
512#define PACKET3_SET_CONTEXT_REG_END 0x00029000
513#define PACKET3_SET_ALU_CONST 0x6A
514/* alu const buffers only; no reg file */
515#define PACKET3_SET_BOOL_CONST 0x6B
516#define PACKET3_SET_BOOL_CONST_START 0x0003a500
517#define PACKET3_SET_BOOL_CONST_END 0x0003a518
518#define PACKET3_SET_LOOP_CONST 0x6C
519#define PACKET3_SET_LOOP_CONST_START 0x0003a200
520#define PACKET3_SET_LOOP_CONST_END 0x0003a500
521#define PACKET3_SET_RESOURCE 0x6D
522#define PACKET3_SET_RESOURCE_START 0x00030000
523#define PACKET3_SET_RESOURCE_END 0x00038000
524#define PACKET3_SET_SAMPLER 0x6E
525#define PACKET3_SET_SAMPLER_START 0x0003c000
526#define PACKET3_SET_SAMPLER_END 0x0003c600
527#define PACKET3_SET_CTL_CONST 0x6F
528#define PACKET3_SET_CTL_CONST_START 0x0003cff0
529#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
530#define PACKET3_SET_RESOURCE_OFFSET 0x70
531#define PACKET3_SET_ALU_CONST_VS 0x71
532#define PACKET3_SET_ALU_CONST_DI 0x72
533#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
534#define PACKET3_SET_RESOURCE_INDIRECT 0x74
535#define PACKET3_SET_APPEND_CNT 0x75
536
537#endif
538