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1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include "drmP.h"
31
32#include "nouveau_drm.h"
33#include "nouveau_drv.h"
34#include "nouveau_dma.h"
35#include "nouveau_mm.h"
36#include "nouveau_vm.h"
37
38#include <linux/log2.h>
39#include <linux/slab.h>
40
41static void
42nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
43{
44 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
45 struct drm_device *dev = dev_priv->dev;
46 struct nouveau_bo *nvbo = nouveau_bo(bo);
47
48 if (unlikely(nvbo->gem))
49 DRM_ERROR("bo %p still attached to GEM object\n", bo);
50
51 nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
52 kfree(nvbo);
53}
54
55static void
56nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
57 int *align, int *size)
58{
59 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
60
61 if (dev_priv->card_type < NV_50) {
62 if (nvbo->tile_mode) {
63 if (dev_priv->chipset >= 0x40) {
64 *align = 65536;
65 *size = roundup(*size, 64 * nvbo->tile_mode);
66
67 } else if (dev_priv->chipset >= 0x30) {
68 *align = 32768;
69 *size = roundup(*size, 64 * nvbo->tile_mode);
70
71 } else if (dev_priv->chipset >= 0x20) {
72 *align = 16384;
73 *size = roundup(*size, 64 * nvbo->tile_mode);
74
75 } else if (dev_priv->chipset >= 0x10) {
76 *align = 16384;
77 *size = roundup(*size, 32 * nvbo->tile_mode);
78 }
79 }
80 } else {
81 *size = roundup(*size, (1 << nvbo->page_shift));
82 *align = max((1 << nvbo->page_shift), *align);
83 }
84
85 *size = roundup(*size, PAGE_SIZE);
86}
87
88int
89nouveau_bo_new(struct drm_device *dev, int size, int align,
90 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
91 struct nouveau_bo **pnvbo)
92{
93 struct drm_nouveau_private *dev_priv = dev->dev_private;
94 struct nouveau_bo *nvbo;
95 int ret;
96
97 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
98 if (!nvbo)
99 return -ENOMEM;
100 INIT_LIST_HEAD(&nvbo->head);
101 INIT_LIST_HEAD(&nvbo->entry);
102 INIT_LIST_HEAD(&nvbo->vma_list);
103 nvbo->tile_mode = tile_mode;
104 nvbo->tile_flags = tile_flags;
105 nvbo->bo.bdev = &dev_priv->ttm.bdev;
106
107 nvbo->page_shift = 12;
108 if (dev_priv->bar1_vm) {
109 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
110 nvbo->page_shift = dev_priv->bar1_vm->lpg_shift;
111 }
112
113 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
114 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
115 nouveau_bo_placement_set(nvbo, flags, 0);
116
117 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
118 ttm_bo_type_device, &nvbo->placement,
119 align >> PAGE_SHIFT, 0, false, NULL, size,
120 nouveau_bo_del_ttm);
121 if (ret) {
122 /* ttm will call nouveau_bo_del_ttm if it fails.. */
123 return ret;
124 }
125
126 *pnvbo = nvbo;
127 return 0;
128}
129
130static void
131set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
132{
133 *n = 0;
134
135 if (type & TTM_PL_FLAG_VRAM)
136 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
137 if (type & TTM_PL_FLAG_TT)
138 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
139 if (type & TTM_PL_FLAG_SYSTEM)
140 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
141}
142
143static void
144set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
145{
146 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
147 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
148
149 if (dev_priv->card_type == NV_10 &&
150 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
151 nvbo->bo.mem.num_pages < vram_pages / 2) {
152 /*
153 * Make sure that the color and depth buffers are handled
154 * by independent memory controller units. Up to a 9x
155 * speed up when alpha-blending and depth-test are enabled
156 * at the same time.
157 */
158 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
159 nvbo->placement.fpfn = vram_pages / 2;
160 nvbo->placement.lpfn = ~0;
161 } else {
162 nvbo->placement.fpfn = 0;
163 nvbo->placement.lpfn = vram_pages / 2;
164 }
165 }
166}
167
168void
169nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
170{
171 struct ttm_placement *pl = &nvbo->placement;
172 uint32_t flags = TTM_PL_MASK_CACHING |
173 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
174
175 pl->placement = nvbo->placements;
176 set_placement_list(nvbo->placements, &pl->num_placement,
177 type, flags);
178
179 pl->busy_placement = nvbo->busy_placements;
180 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
181 type | busy, flags);
182
183 set_placement_range(nvbo, type);
184}
185
186int
187nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
188{
189 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
190 struct ttm_buffer_object *bo = &nvbo->bo;
191 int ret;
192
193 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
194 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
195 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
196 1 << bo->mem.mem_type, memtype);
197 return -EINVAL;
198 }
199
200 if (nvbo->pin_refcnt++)
201 return 0;
202
203 ret = ttm_bo_reserve(bo, false, false, false, 0);
204 if (ret)
205 goto out;
206
207 nouveau_bo_placement_set(nvbo, memtype, 0);
208
209 ret = nouveau_bo_validate(nvbo, false, false, false);
210 if (ret == 0) {
211 switch (bo->mem.mem_type) {
212 case TTM_PL_VRAM:
213 dev_priv->fb_aper_free -= bo->mem.size;
214 break;
215 case TTM_PL_TT:
216 dev_priv->gart_info.aper_free -= bo->mem.size;
217 break;
218 default:
219 break;
220 }
221 }
222 ttm_bo_unreserve(bo);
223out:
224 if (unlikely(ret))
225 nvbo->pin_refcnt--;
226 return ret;
227}
228
229int
230nouveau_bo_unpin(struct nouveau_bo *nvbo)
231{
232 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
233 struct ttm_buffer_object *bo = &nvbo->bo;
234 int ret;
235
236 if (--nvbo->pin_refcnt)
237 return 0;
238
239 ret = ttm_bo_reserve(bo, false, false, false, 0);
240 if (ret)
241 return ret;
242
243 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
244
245 ret = nouveau_bo_validate(nvbo, false, false, false);
246 if (ret == 0) {
247 switch (bo->mem.mem_type) {
248 case TTM_PL_VRAM:
249 dev_priv->fb_aper_free += bo->mem.size;
250 break;
251 case TTM_PL_TT:
252 dev_priv->gart_info.aper_free += bo->mem.size;
253 break;
254 default:
255 break;
256 }
257 }
258
259 ttm_bo_unreserve(bo);
260 return ret;
261}
262
263int
264nouveau_bo_map(struct nouveau_bo *nvbo)
265{
266 int ret;
267
268 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
269 if (ret)
270 return ret;
271
272 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
273 ttm_bo_unreserve(&nvbo->bo);
274 return ret;
275}
276
277void
278nouveau_bo_unmap(struct nouveau_bo *nvbo)
279{
280 if (nvbo)
281 ttm_bo_kunmap(&nvbo->kmap);
282}
283
284int
285nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
286 bool no_wait_reserve, bool no_wait_gpu)
287{
288 int ret;
289
290 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
291 no_wait_reserve, no_wait_gpu);
292 if (ret)
293 return ret;
294
295 return 0;
296}
297
298u16
299nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
300{
301 bool is_iomem;
302 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
303 mem = &mem[index];
304 if (is_iomem)
305 return ioread16_native((void __force __iomem *)mem);
306 else
307 return *mem;
308}
309
310void
311nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
312{
313 bool is_iomem;
314 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
315 mem = &mem[index];
316 if (is_iomem)
317 iowrite16_native(val, (void __force __iomem *)mem);
318 else
319 *mem = val;
320}
321
322u32
323nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
324{
325 bool is_iomem;
326 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
327 mem = &mem[index];
328 if (is_iomem)
329 return ioread32_native((void __force __iomem *)mem);
330 else
331 return *mem;
332}
333
334void
335nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
336{
337 bool is_iomem;
338 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
339 mem = &mem[index];
340 if (is_iomem)
341 iowrite32_native(val, (void __force __iomem *)mem);
342 else
343 *mem = val;
344}
345
346static struct ttm_backend *
347nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
348{
349 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
350 struct drm_device *dev = dev_priv->dev;
351
352 switch (dev_priv->gart_info.type) {
353#if __OS_HAS_AGP
354 case NOUVEAU_GART_AGP:
355 return ttm_agp_backend_init(bdev, dev->agp->bridge);
356#endif
357 case NOUVEAU_GART_PDMA:
358 case NOUVEAU_GART_HW:
359 return nouveau_sgdma_init_ttm(dev);
360 default:
361 NV_ERROR(dev, "Unknown GART type %d\n",
362 dev_priv->gart_info.type);
363 break;
364 }
365
366 return NULL;
367}
368
369static int
370nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
371{
372 /* We'll do this from user space. */
373 return 0;
374}
375
376static int
377nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
378 struct ttm_mem_type_manager *man)
379{
380 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
381 struct drm_device *dev = dev_priv->dev;
382
383 switch (type) {
384 case TTM_PL_SYSTEM:
385 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
386 man->available_caching = TTM_PL_MASK_CACHING;
387 man->default_caching = TTM_PL_FLAG_CACHED;
388 break;
389 case TTM_PL_VRAM:
390 if (dev_priv->card_type >= NV_50) {
391 man->func = &nouveau_vram_manager;
392 man->io_reserve_fastpath = false;
393 man->use_io_reserve_lru = true;
394 } else {
395 man->func = &ttm_bo_manager_func;
396 }
397 man->flags = TTM_MEMTYPE_FLAG_FIXED |
398 TTM_MEMTYPE_FLAG_MAPPABLE;
399 man->available_caching = TTM_PL_FLAG_UNCACHED |
400 TTM_PL_FLAG_WC;
401 man->default_caching = TTM_PL_FLAG_WC;
402 break;
403 case TTM_PL_TT:
404 if (dev_priv->card_type >= NV_50)
405 man->func = &nouveau_gart_manager;
406 else
407 man->func = &ttm_bo_manager_func;
408 switch (dev_priv->gart_info.type) {
409 case NOUVEAU_GART_AGP:
410 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
411 man->available_caching = TTM_PL_FLAG_UNCACHED |
412 TTM_PL_FLAG_WC;
413 man->default_caching = TTM_PL_FLAG_WC;
414 break;
415 case NOUVEAU_GART_PDMA:
416 case NOUVEAU_GART_HW:
417 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
418 TTM_MEMTYPE_FLAG_CMA;
419 man->available_caching = TTM_PL_MASK_CACHING;
420 man->default_caching = TTM_PL_FLAG_CACHED;
421 break;
422 default:
423 NV_ERROR(dev, "Unknown GART type: %d\n",
424 dev_priv->gart_info.type);
425 return -EINVAL;
426 }
427 break;
428 default:
429 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
430 return -EINVAL;
431 }
432 return 0;
433}
434
435static void
436nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
437{
438 struct nouveau_bo *nvbo = nouveau_bo(bo);
439
440 switch (bo->mem.mem_type) {
441 case TTM_PL_VRAM:
442 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
443 TTM_PL_FLAG_SYSTEM);
444 break;
445 default:
446 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
447 break;
448 }
449
450 *pl = nvbo->placement;
451}
452
453
454/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
455 * TTM_PL_{VRAM,TT} directly.
456 */
457
458static int
459nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
460 struct nouveau_bo *nvbo, bool evict,
461 bool no_wait_reserve, bool no_wait_gpu,
462 struct ttm_mem_reg *new_mem)
463{
464 struct nouveau_fence *fence = NULL;
465 int ret;
466
467 ret = nouveau_fence_new(chan, &fence, true);
468 if (ret)
469 return ret;
470
471 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
472 no_wait_reserve, no_wait_gpu, new_mem);
473 nouveau_fence_unref(&fence);
474 return ret;
475}
476
477static int
478nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
479 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
480{
481 struct nouveau_mem *node = old_mem->mm_node;
482 u64 src_offset = node->vma[0].offset;
483 u64 dst_offset = node->vma[1].offset;
484 u32 page_count = new_mem->num_pages;
485 int ret;
486
487 page_count = new_mem->num_pages;
488 while (page_count) {
489 int line_count = (page_count > 2047) ? 2047 : page_count;
490
491 ret = RING_SPACE(chan, 12);
492 if (ret)
493 return ret;
494
495 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0238, 2);
496 OUT_RING (chan, upper_32_bits(dst_offset));
497 OUT_RING (chan, lower_32_bits(dst_offset));
498 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x030c, 6);
499 OUT_RING (chan, upper_32_bits(src_offset));
500 OUT_RING (chan, lower_32_bits(src_offset));
501 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
502 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
503 OUT_RING (chan, PAGE_SIZE); /* line_length */
504 OUT_RING (chan, line_count);
505 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0300, 1);
506 OUT_RING (chan, 0x00100110);
507
508 page_count -= line_count;
509 src_offset += (PAGE_SIZE * line_count);
510 dst_offset += (PAGE_SIZE * line_count);
511 }
512
513 return 0;
514}
515
516static int
517nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
518 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
519{
520 struct nouveau_mem *node = old_mem->mm_node;
521 struct nouveau_bo *nvbo = nouveau_bo(bo);
522 u64 length = (new_mem->num_pages << PAGE_SHIFT);
523 u64 src_offset = node->vma[0].offset;
524 u64 dst_offset = node->vma[1].offset;
525 int ret;
526
527 while (length) {
528 u32 amount, stride, height;
529
530 amount = min(length, (u64)(4 * 1024 * 1024));
531 stride = 16 * 4;
532 height = amount / stride;
533
534 if (new_mem->mem_type == TTM_PL_VRAM &&
535 nouveau_bo_tile_layout(nvbo)) {
536 ret = RING_SPACE(chan, 8);
537 if (ret)
538 return ret;
539
540 BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
541 OUT_RING (chan, 0);
542 OUT_RING (chan, 0);
543 OUT_RING (chan, stride);
544 OUT_RING (chan, height);
545 OUT_RING (chan, 1);
546 OUT_RING (chan, 0);
547 OUT_RING (chan, 0);
548 } else {
549 ret = RING_SPACE(chan, 2);
550 if (ret)
551 return ret;
552
553 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
554 OUT_RING (chan, 1);
555 }
556 if (old_mem->mem_type == TTM_PL_VRAM &&
557 nouveau_bo_tile_layout(nvbo)) {
558 ret = RING_SPACE(chan, 8);
559 if (ret)
560 return ret;
561
562 BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
563 OUT_RING (chan, 0);
564 OUT_RING (chan, 0);
565 OUT_RING (chan, stride);
566 OUT_RING (chan, height);
567 OUT_RING (chan, 1);
568 OUT_RING (chan, 0);
569 OUT_RING (chan, 0);
570 } else {
571 ret = RING_SPACE(chan, 2);
572 if (ret)
573 return ret;
574
575 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
576 OUT_RING (chan, 1);
577 }
578
579 ret = RING_SPACE(chan, 14);
580 if (ret)
581 return ret;
582
583 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
584 OUT_RING (chan, upper_32_bits(src_offset));
585 OUT_RING (chan, upper_32_bits(dst_offset));
586 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
587 OUT_RING (chan, lower_32_bits(src_offset));
588 OUT_RING (chan, lower_32_bits(dst_offset));
589 OUT_RING (chan, stride);
590 OUT_RING (chan, stride);
591 OUT_RING (chan, stride);
592 OUT_RING (chan, height);
593 OUT_RING (chan, 0x00000101);
594 OUT_RING (chan, 0x00000000);
595 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
596 OUT_RING (chan, 0);
597
598 length -= amount;
599 src_offset += amount;
600 dst_offset += amount;
601 }
602
603 return 0;
604}
605
606static inline uint32_t
607nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
608 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
609{
610 if (mem->mem_type == TTM_PL_TT)
611 return chan->gart_handle;
612 return chan->vram_handle;
613}
614
615static int
616nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
617 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
618{
619 u32 src_offset = old_mem->start << PAGE_SHIFT;
620 u32 dst_offset = new_mem->start << PAGE_SHIFT;
621 u32 page_count = new_mem->num_pages;
622 int ret;
623
624 ret = RING_SPACE(chan, 3);
625 if (ret)
626 return ret;
627
628 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
629 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
630 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
631
632 page_count = new_mem->num_pages;
633 while (page_count) {
634 int line_count = (page_count > 2047) ? 2047 : page_count;
635
636 ret = RING_SPACE(chan, 11);
637 if (ret)
638 return ret;
639
640 BEGIN_RING(chan, NvSubM2MF,
641 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
642 OUT_RING (chan, src_offset);
643 OUT_RING (chan, dst_offset);
644 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
645 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
646 OUT_RING (chan, PAGE_SIZE); /* line_length */
647 OUT_RING (chan, line_count);
648 OUT_RING (chan, 0x00000101);
649 OUT_RING (chan, 0x00000000);
650 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
651 OUT_RING (chan, 0);
652
653 page_count -= line_count;
654 src_offset += (PAGE_SIZE * line_count);
655 dst_offset += (PAGE_SIZE * line_count);
656 }
657
658 return 0;
659}
660
661static int
662nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
663 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
664{
665 struct nouveau_mem *node = mem->mm_node;
666 int ret;
667
668 ret = nouveau_vm_get(chan->vm, mem->num_pages << PAGE_SHIFT,
669 node->page_shift, NV_MEM_ACCESS_RO, vma);
670 if (ret)
671 return ret;
672
673 if (mem->mem_type == TTM_PL_VRAM)
674 nouveau_vm_map(vma, node);
675 else
676 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT,
677 node, node->pages);
678
679 return 0;
680}
681
682static int
683nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
684 bool no_wait_reserve, bool no_wait_gpu,
685 struct ttm_mem_reg *new_mem)
686{
687 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
688 struct nouveau_bo *nvbo = nouveau_bo(bo);
689 struct ttm_mem_reg *old_mem = &bo->mem;
690 struct nouveau_channel *chan;
691 int ret;
692
693 chan = nvbo->channel;
694 if (!chan) {
695 chan = dev_priv->channel;
696 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
697 }
698
699 /* create temporary vmas for the transfer and attach them to the
700 * old nouveau_mem node, these will get cleaned up after ttm has
701 * destroyed the ttm_mem_reg
702 */
703 if (dev_priv->card_type >= NV_50) {
704 struct nouveau_mem *node = old_mem->mm_node;
705
706 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
707 if (ret)
708 goto out;
709
710 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
711 if (ret)
712 goto out;
713 }
714
715 if (dev_priv->card_type < NV_50)
716 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
717 else
718 if (dev_priv->card_type < NV_C0)
719 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
720 else
721 ret = nvc0_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
722 if (ret == 0) {
723 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
724 no_wait_reserve,
725 no_wait_gpu, new_mem);
726 }
727
728out:
729 if (chan == dev_priv->channel)
730 mutex_unlock(&chan->mutex);
731 return ret;
732}
733
734static int
735nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
736 bool no_wait_reserve, bool no_wait_gpu,
737 struct ttm_mem_reg *new_mem)
738{
739 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
740 struct ttm_placement placement;
741 struct ttm_mem_reg tmp_mem;
742 int ret;
743
744 placement.fpfn = placement.lpfn = 0;
745 placement.num_placement = placement.num_busy_placement = 1;
746 placement.placement = placement.busy_placement = &placement_memtype;
747
748 tmp_mem = *new_mem;
749 tmp_mem.mm_node = NULL;
750 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
751 if (ret)
752 return ret;
753
754 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
755 if (ret)
756 goto out;
757
758 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
759 if (ret)
760 goto out;
761
762 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
763out:
764 ttm_bo_mem_put(bo, &tmp_mem);
765 return ret;
766}
767
768static int
769nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
770 bool no_wait_reserve, bool no_wait_gpu,
771 struct ttm_mem_reg *new_mem)
772{
773 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
774 struct ttm_placement placement;
775 struct ttm_mem_reg tmp_mem;
776 int ret;
777
778 placement.fpfn = placement.lpfn = 0;
779 placement.num_placement = placement.num_busy_placement = 1;
780 placement.placement = placement.busy_placement = &placement_memtype;
781
782 tmp_mem = *new_mem;
783 tmp_mem.mm_node = NULL;
784 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
785 if (ret)
786 return ret;
787
788 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
789 if (ret)
790 goto out;
791
792 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
793 if (ret)
794 goto out;
795
796out:
797 ttm_bo_mem_put(bo, &tmp_mem);
798 return ret;
799}
800
801static void
802nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
803{
804 struct nouveau_mem *node = new_mem->mm_node;
805 struct nouveau_bo *nvbo = nouveau_bo(bo);
806 struct nouveau_vma *vma;
807
808 list_for_each_entry(vma, &nvbo->vma_list, head) {
809 if (new_mem->mem_type == TTM_PL_VRAM) {
810 nouveau_vm_map(vma, new_mem->mm_node);
811 } else
812 if (new_mem->mem_type == TTM_PL_TT &&
813 nvbo->page_shift == vma->vm->spg_shift) {
814 nouveau_vm_map_sg(vma, 0, new_mem->
815 num_pages << PAGE_SHIFT,
816 node, node->pages);
817 } else {
818 nouveau_vm_unmap(vma);
819 }
820 }
821}
822
823static int
824nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
825 struct nouveau_tile_reg **new_tile)
826{
827 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
828 struct drm_device *dev = dev_priv->dev;
829 struct nouveau_bo *nvbo = nouveau_bo(bo);
830 u64 offset = new_mem->start << PAGE_SHIFT;
831
832 *new_tile = NULL;
833 if (new_mem->mem_type != TTM_PL_VRAM)
834 return 0;
835
836 if (dev_priv->card_type >= NV_10) {
837 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
838 nvbo->tile_mode,
839 nvbo->tile_flags);
840 }
841
842 return 0;
843}
844
845static void
846nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
847 struct nouveau_tile_reg *new_tile,
848 struct nouveau_tile_reg **old_tile)
849{
850 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
851 struct drm_device *dev = dev_priv->dev;
852
853 nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
854 *old_tile = new_tile;
855}
856
857static int
858nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
859 bool no_wait_reserve, bool no_wait_gpu,
860 struct ttm_mem_reg *new_mem)
861{
862 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
863 struct nouveau_bo *nvbo = nouveau_bo(bo);
864 struct ttm_mem_reg *old_mem = &bo->mem;
865 struct nouveau_tile_reg *new_tile = NULL;
866 int ret = 0;
867
868 if (dev_priv->card_type < NV_50) {
869 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
870 if (ret)
871 return ret;
872 }
873
874 /* Fake bo copy. */
875 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
876 BUG_ON(bo->mem.mm_node != NULL);
877 bo->mem = *new_mem;
878 new_mem->mm_node = NULL;
879 goto out;
880 }
881
882 /* Software copy if the card isn't up and running yet. */
883 if (!dev_priv->channel) {
884 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
885 goto out;
886 }
887
888 /* Hardware assisted copy. */
889 if (new_mem->mem_type == TTM_PL_SYSTEM)
890 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
891 else if (old_mem->mem_type == TTM_PL_SYSTEM)
892 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
893 else
894 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
895
896 if (!ret)
897 goto out;
898
899 /* Fallback to software copy. */
900 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
901
902out:
903 if (dev_priv->card_type < NV_50) {
904 if (ret)
905 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
906 else
907 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
908 }
909
910 return ret;
911}
912
913static int
914nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
915{
916 return 0;
917}
918
919static int
920nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
921{
922 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
923 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
924 struct drm_device *dev = dev_priv->dev;
925 int ret;
926
927 mem->bus.addr = NULL;
928 mem->bus.offset = 0;
929 mem->bus.size = mem->num_pages << PAGE_SHIFT;
930 mem->bus.base = 0;
931 mem->bus.is_iomem = false;
932 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
933 return -EINVAL;
934 switch (mem->mem_type) {
935 case TTM_PL_SYSTEM:
936 /* System memory */
937 return 0;
938 case TTM_PL_TT:
939#if __OS_HAS_AGP
940 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
941 mem->bus.offset = mem->start << PAGE_SHIFT;
942 mem->bus.base = dev_priv->gart_info.aper_base;
943 mem->bus.is_iomem = true;
944 }
945#endif
946 break;
947 case TTM_PL_VRAM:
948 {
949 struct nouveau_mem *node = mem->mm_node;
950 u8 page_shift;
951
952 if (!dev_priv->bar1_vm) {
953 mem->bus.offset = mem->start << PAGE_SHIFT;
954 mem->bus.base = pci_resource_start(dev->pdev, 1);
955 mem->bus.is_iomem = true;
956 break;
957 }
958
959 if (dev_priv->card_type == NV_C0)
960 page_shift = node->page_shift;
961 else
962 page_shift = 12;
963
964 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
965 page_shift, NV_MEM_ACCESS_RW,
966 &node->bar_vma);
967 if (ret)
968 return ret;
969
970 nouveau_vm_map(&node->bar_vma, node);
971 if (ret) {
972 nouveau_vm_put(&node->bar_vma);
973 return ret;
974 }
975
976 mem->bus.offset = node->bar_vma.offset;
977 if (dev_priv->card_type == NV_50) /*XXX*/
978 mem->bus.offset -= 0x0020000000ULL;
979 mem->bus.base = pci_resource_start(dev->pdev, 1);
980 mem->bus.is_iomem = true;
981 }
982 break;
983 default:
984 return -EINVAL;
985 }
986 return 0;
987}
988
989static void
990nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
991{
992 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
993 struct nouveau_mem *node = mem->mm_node;
994
995 if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
996 return;
997
998 if (!node->bar_vma.node)
999 return;
1000
1001 nouveau_vm_unmap(&node->bar_vma);
1002 nouveau_vm_put(&node->bar_vma);
1003}
1004
1005static int
1006nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1007{
1008 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1009 struct nouveau_bo *nvbo = nouveau_bo(bo);
1010
1011 /* as long as the bo isn't in vram, and isn't tiled, we've got
1012 * nothing to do here.
1013 */
1014 if (bo->mem.mem_type != TTM_PL_VRAM) {
1015 if (dev_priv->card_type < NV_50 ||
1016 !nouveau_bo_tile_layout(nvbo))
1017 return 0;
1018 }
1019
1020 /* make sure bo is in mappable vram */
1021 if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
1022 return 0;
1023
1024
1025 nvbo->placement.fpfn = 0;
1026 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
1027 nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
1028 return nouveau_bo_validate(nvbo, false, true, false);
1029}
1030
1031void
1032nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1033{
1034 struct nouveau_fence *old_fence;
1035
1036 if (likely(fence))
1037 nouveau_fence_ref(fence);
1038
1039 spin_lock(&nvbo->bo.bdev->fence_lock);
1040 old_fence = nvbo->bo.sync_obj;
1041 nvbo->bo.sync_obj = fence;
1042 spin_unlock(&nvbo->bo.bdev->fence_lock);
1043
1044 nouveau_fence_unref(&old_fence);
1045}
1046
1047struct ttm_bo_driver nouveau_bo_driver = {
1048 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
1049 .invalidate_caches = nouveau_bo_invalidate_caches,
1050 .init_mem_type = nouveau_bo_init_mem_type,
1051 .evict_flags = nouveau_bo_evict_flags,
1052 .move_notify = nouveau_bo_move_ntfy,
1053 .move = nouveau_bo_move,
1054 .verify_access = nouveau_bo_verify_access,
1055 .sync_obj_signaled = __nouveau_fence_signalled,
1056 .sync_obj_wait = __nouveau_fence_wait,
1057 .sync_obj_flush = __nouveau_fence_flush,
1058 .sync_obj_unref = __nouveau_fence_unref,
1059 .sync_obj_ref = __nouveau_fence_ref,
1060 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1061 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1062 .io_mem_free = &nouveau_ttm_io_mem_free,
1063};
1064
1065struct nouveau_vma *
1066nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1067{
1068 struct nouveau_vma *vma;
1069 list_for_each_entry(vma, &nvbo->vma_list, head) {
1070 if (vma->vm == vm)
1071 return vma;
1072 }
1073
1074 return NULL;
1075}
1076
1077int
1078nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1079 struct nouveau_vma *vma)
1080{
1081 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1082 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1083 int ret;
1084
1085 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1086 NV_MEM_ACCESS_RW, vma);
1087 if (ret)
1088 return ret;
1089
1090 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1091 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1092 else
1093 if (nvbo->bo.mem.mem_type == TTM_PL_TT)
1094 nouveau_vm_map_sg(vma, 0, size, node, node->pages);
1095
1096 list_add_tail(&vma->head, &nvbo->vma_list);
1097 vma->refcount = 1;
1098 return 0;
1099}
1100
1101void
1102nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1103{
1104 if (vma->node) {
1105 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
1106 spin_lock(&nvbo->bo.bdev->fence_lock);
1107 ttm_bo_wait(&nvbo->bo, false, false, false);
1108 spin_unlock(&nvbo->bo.bdev->fence_lock);
1109 nouveau_vm_unmap(vma);
1110 }
1111
1112 nouveau_vm_put(vma);
1113 list_del(&vma->head);
1114 }
1115}
1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include "drmP.h"
31#include "ttm/ttm_page_alloc.h"
32
33#include "nouveau_drm.h"
34#include "nouveau_drv.h"
35#include "nouveau_dma.h"
36#include "nouveau_mm.h"
37#include "nouveau_vm.h"
38#include "nouveau_fence.h"
39#include "nouveau_ramht.h"
40
41#include <linux/log2.h>
42#include <linux/slab.h>
43
44static void
45nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
46{
47 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
48 struct drm_device *dev = dev_priv->dev;
49 struct nouveau_bo *nvbo = nouveau_bo(bo);
50
51 if (unlikely(nvbo->gem))
52 DRM_ERROR("bo %p still attached to GEM object\n", bo);
53
54 nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
55 kfree(nvbo);
56}
57
58static void
59nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
60 int *align, int *size)
61{
62 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
63
64 if (dev_priv->card_type < NV_50) {
65 if (nvbo->tile_mode) {
66 if (dev_priv->chipset >= 0x40) {
67 *align = 65536;
68 *size = roundup(*size, 64 * nvbo->tile_mode);
69
70 } else if (dev_priv->chipset >= 0x30) {
71 *align = 32768;
72 *size = roundup(*size, 64 * nvbo->tile_mode);
73
74 } else if (dev_priv->chipset >= 0x20) {
75 *align = 16384;
76 *size = roundup(*size, 64 * nvbo->tile_mode);
77
78 } else if (dev_priv->chipset >= 0x10) {
79 *align = 16384;
80 *size = roundup(*size, 32 * nvbo->tile_mode);
81 }
82 }
83 } else {
84 *size = roundup(*size, (1 << nvbo->page_shift));
85 *align = max((1 << nvbo->page_shift), *align);
86 }
87
88 *size = roundup(*size, PAGE_SIZE);
89}
90
91int
92nouveau_bo_new(struct drm_device *dev, int size, int align,
93 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
94 struct sg_table *sg,
95 struct nouveau_bo **pnvbo)
96{
97 struct drm_nouveau_private *dev_priv = dev->dev_private;
98 struct nouveau_bo *nvbo;
99 size_t acc_size;
100 int ret;
101 int type = ttm_bo_type_device;
102
103 if (sg)
104 type = ttm_bo_type_sg;
105
106 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
107 if (!nvbo)
108 return -ENOMEM;
109 INIT_LIST_HEAD(&nvbo->head);
110 INIT_LIST_HEAD(&nvbo->entry);
111 INIT_LIST_HEAD(&nvbo->vma_list);
112 nvbo->tile_mode = tile_mode;
113 nvbo->tile_flags = tile_flags;
114 nvbo->bo.bdev = &dev_priv->ttm.bdev;
115
116 nvbo->page_shift = 12;
117 if (dev_priv->bar1_vm) {
118 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
119 nvbo->page_shift = dev_priv->bar1_vm->lpg_shift;
120 }
121
122 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
123 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
124 nouveau_bo_placement_set(nvbo, flags, 0);
125
126 acc_size = ttm_bo_dma_acc_size(&dev_priv->ttm.bdev, size,
127 sizeof(struct nouveau_bo));
128
129 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
130 type, &nvbo->placement,
131 align >> PAGE_SHIFT, 0, false, NULL, acc_size, sg,
132 nouveau_bo_del_ttm);
133 if (ret) {
134 /* ttm will call nouveau_bo_del_ttm if it fails.. */
135 return ret;
136 }
137
138 *pnvbo = nvbo;
139 return 0;
140}
141
142static void
143set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
144{
145 *n = 0;
146
147 if (type & TTM_PL_FLAG_VRAM)
148 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
149 if (type & TTM_PL_FLAG_TT)
150 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
151 if (type & TTM_PL_FLAG_SYSTEM)
152 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
153}
154
155static void
156set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
157{
158 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
159 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
160
161 if (dev_priv->card_type == NV_10 &&
162 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
163 nvbo->bo.mem.num_pages < vram_pages / 4) {
164 /*
165 * Make sure that the color and depth buffers are handled
166 * by independent memory controller units. Up to a 9x
167 * speed up when alpha-blending and depth-test are enabled
168 * at the same time.
169 */
170 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
171 nvbo->placement.fpfn = vram_pages / 2;
172 nvbo->placement.lpfn = ~0;
173 } else {
174 nvbo->placement.fpfn = 0;
175 nvbo->placement.lpfn = vram_pages / 2;
176 }
177 }
178}
179
180void
181nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
182{
183 struct ttm_placement *pl = &nvbo->placement;
184 uint32_t flags = TTM_PL_MASK_CACHING |
185 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
186
187 pl->placement = nvbo->placements;
188 set_placement_list(nvbo->placements, &pl->num_placement,
189 type, flags);
190
191 pl->busy_placement = nvbo->busy_placements;
192 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
193 type | busy, flags);
194
195 set_placement_range(nvbo, type);
196}
197
198int
199nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
200{
201 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
202 struct ttm_buffer_object *bo = &nvbo->bo;
203 int ret;
204
205 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
206 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
207 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
208 1 << bo->mem.mem_type, memtype);
209 return -EINVAL;
210 }
211
212 if (nvbo->pin_refcnt++)
213 return 0;
214
215 ret = ttm_bo_reserve(bo, false, false, false, 0);
216 if (ret)
217 goto out;
218
219 nouveau_bo_placement_set(nvbo, memtype, 0);
220
221 ret = nouveau_bo_validate(nvbo, false, false, false);
222 if (ret == 0) {
223 switch (bo->mem.mem_type) {
224 case TTM_PL_VRAM:
225 dev_priv->fb_aper_free -= bo->mem.size;
226 break;
227 case TTM_PL_TT:
228 dev_priv->gart_info.aper_free -= bo->mem.size;
229 break;
230 default:
231 break;
232 }
233 }
234 ttm_bo_unreserve(bo);
235out:
236 if (unlikely(ret))
237 nvbo->pin_refcnt--;
238 return ret;
239}
240
241int
242nouveau_bo_unpin(struct nouveau_bo *nvbo)
243{
244 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
245 struct ttm_buffer_object *bo = &nvbo->bo;
246 int ret;
247
248 if (--nvbo->pin_refcnt)
249 return 0;
250
251 ret = ttm_bo_reserve(bo, false, false, false, 0);
252 if (ret)
253 return ret;
254
255 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
256
257 ret = nouveau_bo_validate(nvbo, false, false, false);
258 if (ret == 0) {
259 switch (bo->mem.mem_type) {
260 case TTM_PL_VRAM:
261 dev_priv->fb_aper_free += bo->mem.size;
262 break;
263 case TTM_PL_TT:
264 dev_priv->gart_info.aper_free += bo->mem.size;
265 break;
266 default:
267 break;
268 }
269 }
270
271 ttm_bo_unreserve(bo);
272 return ret;
273}
274
275int
276nouveau_bo_map(struct nouveau_bo *nvbo)
277{
278 int ret;
279
280 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
281 if (ret)
282 return ret;
283
284 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
285 ttm_bo_unreserve(&nvbo->bo);
286 return ret;
287}
288
289void
290nouveau_bo_unmap(struct nouveau_bo *nvbo)
291{
292 if (nvbo)
293 ttm_bo_kunmap(&nvbo->kmap);
294}
295
296int
297nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
298 bool no_wait_reserve, bool no_wait_gpu)
299{
300 int ret;
301
302 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
303 no_wait_reserve, no_wait_gpu);
304 if (ret)
305 return ret;
306
307 return 0;
308}
309
310u16
311nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
312{
313 bool is_iomem;
314 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
315 mem = &mem[index];
316 if (is_iomem)
317 return ioread16_native((void __force __iomem *)mem);
318 else
319 return *mem;
320}
321
322void
323nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
324{
325 bool is_iomem;
326 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
327 mem = &mem[index];
328 if (is_iomem)
329 iowrite16_native(val, (void __force __iomem *)mem);
330 else
331 *mem = val;
332}
333
334u32
335nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
336{
337 bool is_iomem;
338 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
339 mem = &mem[index];
340 if (is_iomem)
341 return ioread32_native((void __force __iomem *)mem);
342 else
343 return *mem;
344}
345
346void
347nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
348{
349 bool is_iomem;
350 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
351 mem = &mem[index];
352 if (is_iomem)
353 iowrite32_native(val, (void __force __iomem *)mem);
354 else
355 *mem = val;
356}
357
358static struct ttm_tt *
359nouveau_ttm_tt_create(struct ttm_bo_device *bdev,
360 unsigned long size, uint32_t page_flags,
361 struct page *dummy_read_page)
362{
363 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
364 struct drm_device *dev = dev_priv->dev;
365
366 switch (dev_priv->gart_info.type) {
367#if __OS_HAS_AGP
368 case NOUVEAU_GART_AGP:
369 return ttm_agp_tt_create(bdev, dev->agp->bridge,
370 size, page_flags, dummy_read_page);
371#endif
372 case NOUVEAU_GART_PDMA:
373 case NOUVEAU_GART_HW:
374 return nouveau_sgdma_create_ttm(bdev, size, page_flags,
375 dummy_read_page);
376 default:
377 NV_ERROR(dev, "Unknown GART type %d\n",
378 dev_priv->gart_info.type);
379 break;
380 }
381
382 return NULL;
383}
384
385static int
386nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
387{
388 /* We'll do this from user space. */
389 return 0;
390}
391
392static int
393nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
394 struct ttm_mem_type_manager *man)
395{
396 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
397 struct drm_device *dev = dev_priv->dev;
398
399 switch (type) {
400 case TTM_PL_SYSTEM:
401 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
402 man->available_caching = TTM_PL_MASK_CACHING;
403 man->default_caching = TTM_PL_FLAG_CACHED;
404 break;
405 case TTM_PL_VRAM:
406 if (dev_priv->card_type >= NV_50) {
407 man->func = &nouveau_vram_manager;
408 man->io_reserve_fastpath = false;
409 man->use_io_reserve_lru = true;
410 } else {
411 man->func = &ttm_bo_manager_func;
412 }
413 man->flags = TTM_MEMTYPE_FLAG_FIXED |
414 TTM_MEMTYPE_FLAG_MAPPABLE;
415 man->available_caching = TTM_PL_FLAG_UNCACHED |
416 TTM_PL_FLAG_WC;
417 man->default_caching = TTM_PL_FLAG_WC;
418 break;
419 case TTM_PL_TT:
420 if (dev_priv->card_type >= NV_50)
421 man->func = &nouveau_gart_manager;
422 else
423 man->func = &ttm_bo_manager_func;
424 switch (dev_priv->gart_info.type) {
425 case NOUVEAU_GART_AGP:
426 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
427 man->available_caching = TTM_PL_FLAG_UNCACHED |
428 TTM_PL_FLAG_WC;
429 man->default_caching = TTM_PL_FLAG_WC;
430 break;
431 case NOUVEAU_GART_PDMA:
432 case NOUVEAU_GART_HW:
433 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
434 TTM_MEMTYPE_FLAG_CMA;
435 man->available_caching = TTM_PL_MASK_CACHING;
436 man->default_caching = TTM_PL_FLAG_CACHED;
437 break;
438 default:
439 NV_ERROR(dev, "Unknown GART type: %d\n",
440 dev_priv->gart_info.type);
441 return -EINVAL;
442 }
443 break;
444 default:
445 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
446 return -EINVAL;
447 }
448 return 0;
449}
450
451static void
452nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
453{
454 struct nouveau_bo *nvbo = nouveau_bo(bo);
455
456 switch (bo->mem.mem_type) {
457 case TTM_PL_VRAM:
458 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
459 TTM_PL_FLAG_SYSTEM);
460 break;
461 default:
462 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
463 break;
464 }
465
466 *pl = nvbo->placement;
467}
468
469
470/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
471 * TTM_PL_{VRAM,TT} directly.
472 */
473
474static int
475nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
476 struct nouveau_bo *nvbo, bool evict,
477 bool no_wait_reserve, bool no_wait_gpu,
478 struct ttm_mem_reg *new_mem)
479{
480 struct nouveau_fence *fence = NULL;
481 int ret;
482
483 ret = nouveau_fence_new(chan, &fence);
484 if (ret)
485 return ret;
486
487 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
488 no_wait_reserve, no_wait_gpu, new_mem);
489 nouveau_fence_unref(&fence);
490 return ret;
491}
492
493static int
494nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
495 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
496{
497 struct nouveau_mem *node = old_mem->mm_node;
498 int ret = RING_SPACE(chan, 10);
499 if (ret == 0) {
500 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
501 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
502 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
503 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
504 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
505 OUT_RING (chan, PAGE_SIZE);
506 OUT_RING (chan, PAGE_SIZE);
507 OUT_RING (chan, PAGE_SIZE);
508 OUT_RING (chan, new_mem->num_pages);
509 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
510 }
511 return ret;
512}
513
514static int
515nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
516{
517 int ret = RING_SPACE(chan, 2);
518 if (ret == 0) {
519 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
520 OUT_RING (chan, handle);
521 }
522 return ret;
523}
524
525static int
526nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
527 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
528{
529 struct nouveau_mem *node = old_mem->mm_node;
530 u64 src_offset = node->vma[0].offset;
531 u64 dst_offset = node->vma[1].offset;
532 u32 page_count = new_mem->num_pages;
533 int ret;
534
535 page_count = new_mem->num_pages;
536 while (page_count) {
537 int line_count = (page_count > 8191) ? 8191 : page_count;
538
539 ret = RING_SPACE(chan, 11);
540 if (ret)
541 return ret;
542
543 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
544 OUT_RING (chan, upper_32_bits(src_offset));
545 OUT_RING (chan, lower_32_bits(src_offset));
546 OUT_RING (chan, upper_32_bits(dst_offset));
547 OUT_RING (chan, lower_32_bits(dst_offset));
548 OUT_RING (chan, PAGE_SIZE);
549 OUT_RING (chan, PAGE_SIZE);
550 OUT_RING (chan, PAGE_SIZE);
551 OUT_RING (chan, line_count);
552 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
553 OUT_RING (chan, 0x00000110);
554
555 page_count -= line_count;
556 src_offset += (PAGE_SIZE * line_count);
557 dst_offset += (PAGE_SIZE * line_count);
558 }
559
560 return 0;
561}
562
563static int
564nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
565 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
566{
567 struct nouveau_mem *node = old_mem->mm_node;
568 u64 src_offset = node->vma[0].offset;
569 u64 dst_offset = node->vma[1].offset;
570 u32 page_count = new_mem->num_pages;
571 int ret;
572
573 page_count = new_mem->num_pages;
574 while (page_count) {
575 int line_count = (page_count > 2047) ? 2047 : page_count;
576
577 ret = RING_SPACE(chan, 12);
578 if (ret)
579 return ret;
580
581 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
582 OUT_RING (chan, upper_32_bits(dst_offset));
583 OUT_RING (chan, lower_32_bits(dst_offset));
584 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
585 OUT_RING (chan, upper_32_bits(src_offset));
586 OUT_RING (chan, lower_32_bits(src_offset));
587 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
588 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
589 OUT_RING (chan, PAGE_SIZE); /* line_length */
590 OUT_RING (chan, line_count);
591 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
592 OUT_RING (chan, 0x00100110);
593
594 page_count -= line_count;
595 src_offset += (PAGE_SIZE * line_count);
596 dst_offset += (PAGE_SIZE * line_count);
597 }
598
599 return 0;
600}
601
602static int
603nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
604 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
605{
606 struct nouveau_mem *node = old_mem->mm_node;
607 u64 src_offset = node->vma[0].offset;
608 u64 dst_offset = node->vma[1].offset;
609 u32 page_count = new_mem->num_pages;
610 int ret;
611
612 page_count = new_mem->num_pages;
613 while (page_count) {
614 int line_count = (page_count > 8191) ? 8191 : page_count;
615
616 ret = RING_SPACE(chan, 11);
617 if (ret)
618 return ret;
619
620 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
621 OUT_RING (chan, upper_32_bits(src_offset));
622 OUT_RING (chan, lower_32_bits(src_offset));
623 OUT_RING (chan, upper_32_bits(dst_offset));
624 OUT_RING (chan, lower_32_bits(dst_offset));
625 OUT_RING (chan, PAGE_SIZE);
626 OUT_RING (chan, PAGE_SIZE);
627 OUT_RING (chan, PAGE_SIZE);
628 OUT_RING (chan, line_count);
629 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
630 OUT_RING (chan, 0x00000110);
631
632 page_count -= line_count;
633 src_offset += (PAGE_SIZE * line_count);
634 dst_offset += (PAGE_SIZE * line_count);
635 }
636
637 return 0;
638}
639
640static int
641nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
642 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
643{
644 struct nouveau_mem *node = old_mem->mm_node;
645 int ret = RING_SPACE(chan, 7);
646 if (ret == 0) {
647 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
648 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
649 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
650 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
651 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
652 OUT_RING (chan, 0x00000000 /* COPY */);
653 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
654 }
655 return ret;
656}
657
658static int
659nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
660 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
661{
662 struct nouveau_mem *node = old_mem->mm_node;
663 int ret = RING_SPACE(chan, 7);
664 if (ret == 0) {
665 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
666 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
667 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
668 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
669 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
670 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
671 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
672 }
673 return ret;
674}
675
676static int
677nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
678{
679 int ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
680 &chan->m2mf_ntfy);
681 if (ret == 0) {
682 ret = RING_SPACE(chan, 6);
683 if (ret == 0) {
684 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
685 OUT_RING (chan, handle);
686 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
687 OUT_RING (chan, NvNotify0);
688 OUT_RING (chan, NvDmaFB);
689 OUT_RING (chan, NvDmaFB);
690 } else {
691 nouveau_ramht_remove(chan, NvNotify0);
692 }
693 }
694
695 return ret;
696}
697
698static int
699nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
700 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
701{
702 struct nouveau_mem *node = old_mem->mm_node;
703 struct nouveau_bo *nvbo = nouveau_bo(bo);
704 u64 length = (new_mem->num_pages << PAGE_SHIFT);
705 u64 src_offset = node->vma[0].offset;
706 u64 dst_offset = node->vma[1].offset;
707 int ret;
708
709 while (length) {
710 u32 amount, stride, height;
711
712 amount = min(length, (u64)(4 * 1024 * 1024));
713 stride = 16 * 4;
714 height = amount / stride;
715
716 if (new_mem->mem_type == TTM_PL_VRAM &&
717 nouveau_bo_tile_layout(nvbo)) {
718 ret = RING_SPACE(chan, 8);
719 if (ret)
720 return ret;
721
722 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
723 OUT_RING (chan, 0);
724 OUT_RING (chan, 0);
725 OUT_RING (chan, stride);
726 OUT_RING (chan, height);
727 OUT_RING (chan, 1);
728 OUT_RING (chan, 0);
729 OUT_RING (chan, 0);
730 } else {
731 ret = RING_SPACE(chan, 2);
732 if (ret)
733 return ret;
734
735 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
736 OUT_RING (chan, 1);
737 }
738 if (old_mem->mem_type == TTM_PL_VRAM &&
739 nouveau_bo_tile_layout(nvbo)) {
740 ret = RING_SPACE(chan, 8);
741 if (ret)
742 return ret;
743
744 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
745 OUT_RING (chan, 0);
746 OUT_RING (chan, 0);
747 OUT_RING (chan, stride);
748 OUT_RING (chan, height);
749 OUT_RING (chan, 1);
750 OUT_RING (chan, 0);
751 OUT_RING (chan, 0);
752 } else {
753 ret = RING_SPACE(chan, 2);
754 if (ret)
755 return ret;
756
757 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
758 OUT_RING (chan, 1);
759 }
760
761 ret = RING_SPACE(chan, 14);
762 if (ret)
763 return ret;
764
765 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
766 OUT_RING (chan, upper_32_bits(src_offset));
767 OUT_RING (chan, upper_32_bits(dst_offset));
768 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
769 OUT_RING (chan, lower_32_bits(src_offset));
770 OUT_RING (chan, lower_32_bits(dst_offset));
771 OUT_RING (chan, stride);
772 OUT_RING (chan, stride);
773 OUT_RING (chan, stride);
774 OUT_RING (chan, height);
775 OUT_RING (chan, 0x00000101);
776 OUT_RING (chan, 0x00000000);
777 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
778 OUT_RING (chan, 0);
779
780 length -= amount;
781 src_offset += amount;
782 dst_offset += amount;
783 }
784
785 return 0;
786}
787
788static int
789nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
790{
791 int ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
792 &chan->m2mf_ntfy);
793 if (ret == 0) {
794 ret = RING_SPACE(chan, 4);
795 if (ret == 0) {
796 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
797 OUT_RING (chan, handle);
798 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
799 OUT_RING (chan, NvNotify0);
800 }
801 }
802
803 return ret;
804}
805
806static inline uint32_t
807nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
808 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
809{
810 if (mem->mem_type == TTM_PL_TT)
811 return chan->gart_handle;
812 return chan->vram_handle;
813}
814
815static int
816nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
817 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
818{
819 u32 src_offset = old_mem->start << PAGE_SHIFT;
820 u32 dst_offset = new_mem->start << PAGE_SHIFT;
821 u32 page_count = new_mem->num_pages;
822 int ret;
823
824 ret = RING_SPACE(chan, 3);
825 if (ret)
826 return ret;
827
828 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
829 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
830 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
831
832 page_count = new_mem->num_pages;
833 while (page_count) {
834 int line_count = (page_count > 2047) ? 2047 : page_count;
835
836 ret = RING_SPACE(chan, 11);
837 if (ret)
838 return ret;
839
840 BEGIN_NV04(chan, NvSubCopy,
841 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
842 OUT_RING (chan, src_offset);
843 OUT_RING (chan, dst_offset);
844 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
845 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
846 OUT_RING (chan, PAGE_SIZE); /* line_length */
847 OUT_RING (chan, line_count);
848 OUT_RING (chan, 0x00000101);
849 OUT_RING (chan, 0x00000000);
850 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
851 OUT_RING (chan, 0);
852
853 page_count -= line_count;
854 src_offset += (PAGE_SIZE * line_count);
855 dst_offset += (PAGE_SIZE * line_count);
856 }
857
858 return 0;
859}
860
861static int
862nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
863 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
864{
865 struct nouveau_mem *node = mem->mm_node;
866 int ret;
867
868 ret = nouveau_vm_get(chan->vm, mem->num_pages << PAGE_SHIFT,
869 node->page_shift, NV_MEM_ACCESS_RO, vma);
870 if (ret)
871 return ret;
872
873 if (mem->mem_type == TTM_PL_VRAM)
874 nouveau_vm_map(vma, node);
875 else
876 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
877
878 return 0;
879}
880
881static int
882nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
883 bool no_wait_reserve, bool no_wait_gpu,
884 struct ttm_mem_reg *new_mem)
885{
886 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
887 struct nouveau_channel *chan = chan = dev_priv->channel;
888 struct nouveau_bo *nvbo = nouveau_bo(bo);
889 struct ttm_mem_reg *old_mem = &bo->mem;
890 int ret;
891
892 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
893
894 /* create temporary vmas for the transfer and attach them to the
895 * old nouveau_mem node, these will get cleaned up after ttm has
896 * destroyed the ttm_mem_reg
897 */
898 if (dev_priv->card_type >= NV_50) {
899 struct nouveau_mem *node = old_mem->mm_node;
900
901 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
902 if (ret)
903 goto out;
904
905 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
906 if (ret)
907 goto out;
908 }
909
910 ret = dev_priv->ttm.move(chan, bo, &bo->mem, new_mem);
911 if (ret == 0) {
912 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
913 no_wait_reserve,
914 no_wait_gpu, new_mem);
915 }
916
917out:
918 mutex_unlock(&chan->mutex);
919 return ret;
920}
921
922void
923nouveau_bo_move_init(struct nouveau_channel *chan)
924{
925 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
926 static const struct {
927 const char *name;
928 int engine;
929 u32 oclass;
930 int (*exec)(struct nouveau_channel *,
931 struct ttm_buffer_object *,
932 struct ttm_mem_reg *, struct ttm_mem_reg *);
933 int (*init)(struct nouveau_channel *, u32 handle);
934 } _methods[] = {
935 { "COPY", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
936 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
937 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
938 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
939 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
940 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
941 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
942 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
943 {},
944 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
945 }, *mthd = _methods;
946 const char *name = "CPU";
947 int ret;
948
949 do {
950 u32 handle = (mthd->engine << 16) | mthd->oclass;
951 ret = nouveau_gpuobj_gr_new(chan, handle, mthd->oclass);
952 if (ret == 0) {
953 ret = mthd->init(chan, handle);
954 if (ret == 0) {
955 dev_priv->ttm.move = mthd->exec;
956 name = mthd->name;
957 break;
958 }
959 }
960 } while ((++mthd)->exec);
961
962 NV_INFO(chan->dev, "MM: using %s for buffer copies\n", name);
963}
964
965static int
966nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
967 bool no_wait_reserve, bool no_wait_gpu,
968 struct ttm_mem_reg *new_mem)
969{
970 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
971 struct ttm_placement placement;
972 struct ttm_mem_reg tmp_mem;
973 int ret;
974
975 placement.fpfn = placement.lpfn = 0;
976 placement.num_placement = placement.num_busy_placement = 1;
977 placement.placement = placement.busy_placement = &placement_memtype;
978
979 tmp_mem = *new_mem;
980 tmp_mem.mm_node = NULL;
981 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
982 if (ret)
983 return ret;
984
985 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
986 if (ret)
987 goto out;
988
989 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
990 if (ret)
991 goto out;
992
993 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
994out:
995 ttm_bo_mem_put(bo, &tmp_mem);
996 return ret;
997}
998
999static int
1000nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1001 bool no_wait_reserve, bool no_wait_gpu,
1002 struct ttm_mem_reg *new_mem)
1003{
1004 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1005 struct ttm_placement placement;
1006 struct ttm_mem_reg tmp_mem;
1007 int ret;
1008
1009 placement.fpfn = placement.lpfn = 0;
1010 placement.num_placement = placement.num_busy_placement = 1;
1011 placement.placement = placement.busy_placement = &placement_memtype;
1012
1013 tmp_mem = *new_mem;
1014 tmp_mem.mm_node = NULL;
1015 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
1016 if (ret)
1017 return ret;
1018
1019 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
1020 if (ret)
1021 goto out;
1022
1023 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
1024 if (ret)
1025 goto out;
1026
1027out:
1028 ttm_bo_mem_put(bo, &tmp_mem);
1029 return ret;
1030}
1031
1032static void
1033nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1034{
1035 struct nouveau_bo *nvbo = nouveau_bo(bo);
1036 struct nouveau_vma *vma;
1037
1038 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1039 if (bo->destroy != nouveau_bo_del_ttm)
1040 return;
1041
1042 list_for_each_entry(vma, &nvbo->vma_list, head) {
1043 if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
1044 nouveau_vm_map(vma, new_mem->mm_node);
1045 } else
1046 if (new_mem && new_mem->mem_type == TTM_PL_TT &&
1047 nvbo->page_shift == vma->vm->spg_shift) {
1048 if (((struct nouveau_mem *)new_mem->mm_node)->sg)
1049 nouveau_vm_map_sg_table(vma, 0, new_mem->
1050 num_pages << PAGE_SHIFT,
1051 new_mem->mm_node);
1052 else
1053 nouveau_vm_map_sg(vma, 0, new_mem->
1054 num_pages << PAGE_SHIFT,
1055 new_mem->mm_node);
1056 } else {
1057 nouveau_vm_unmap(vma);
1058 }
1059 }
1060}
1061
1062static int
1063nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1064 struct nouveau_tile_reg **new_tile)
1065{
1066 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1067 struct drm_device *dev = dev_priv->dev;
1068 struct nouveau_bo *nvbo = nouveau_bo(bo);
1069 u64 offset = new_mem->start << PAGE_SHIFT;
1070
1071 *new_tile = NULL;
1072 if (new_mem->mem_type != TTM_PL_VRAM)
1073 return 0;
1074
1075 if (dev_priv->card_type >= NV_10) {
1076 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
1077 nvbo->tile_mode,
1078 nvbo->tile_flags);
1079 }
1080
1081 return 0;
1082}
1083
1084static void
1085nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1086 struct nouveau_tile_reg *new_tile,
1087 struct nouveau_tile_reg **old_tile)
1088{
1089 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1090 struct drm_device *dev = dev_priv->dev;
1091
1092 nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
1093 *old_tile = new_tile;
1094}
1095
1096static int
1097nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1098 bool no_wait_reserve, bool no_wait_gpu,
1099 struct ttm_mem_reg *new_mem)
1100{
1101 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1102 struct nouveau_bo *nvbo = nouveau_bo(bo);
1103 struct ttm_mem_reg *old_mem = &bo->mem;
1104 struct nouveau_tile_reg *new_tile = NULL;
1105 int ret = 0;
1106
1107 if (dev_priv->card_type < NV_50) {
1108 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1109 if (ret)
1110 return ret;
1111 }
1112
1113 /* Fake bo copy. */
1114 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1115 BUG_ON(bo->mem.mm_node != NULL);
1116 bo->mem = *new_mem;
1117 new_mem->mm_node = NULL;
1118 goto out;
1119 }
1120
1121 /* CPU copy if we have no accelerated method available */
1122 if (!dev_priv->ttm.move) {
1123 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
1124 goto out;
1125 }
1126
1127 /* Hardware assisted copy. */
1128 if (new_mem->mem_type == TTM_PL_SYSTEM)
1129 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1130 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1131 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1132 else
1133 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
1134
1135 if (!ret)
1136 goto out;
1137
1138 /* Fallback to software copy. */
1139 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
1140
1141out:
1142 if (dev_priv->card_type < NV_50) {
1143 if (ret)
1144 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1145 else
1146 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1147 }
1148
1149 return ret;
1150}
1151
1152static int
1153nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1154{
1155 return 0;
1156}
1157
1158static int
1159nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1160{
1161 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1162 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
1163 struct drm_device *dev = dev_priv->dev;
1164 int ret;
1165
1166 mem->bus.addr = NULL;
1167 mem->bus.offset = 0;
1168 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1169 mem->bus.base = 0;
1170 mem->bus.is_iomem = false;
1171 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1172 return -EINVAL;
1173 switch (mem->mem_type) {
1174 case TTM_PL_SYSTEM:
1175 /* System memory */
1176 return 0;
1177 case TTM_PL_TT:
1178#if __OS_HAS_AGP
1179 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
1180 mem->bus.offset = mem->start << PAGE_SHIFT;
1181 mem->bus.base = dev_priv->gart_info.aper_base;
1182 mem->bus.is_iomem = true;
1183 }
1184#endif
1185 break;
1186 case TTM_PL_VRAM:
1187 {
1188 struct nouveau_mem *node = mem->mm_node;
1189 u8 page_shift;
1190
1191 if (!dev_priv->bar1_vm) {
1192 mem->bus.offset = mem->start << PAGE_SHIFT;
1193 mem->bus.base = pci_resource_start(dev->pdev, 1);
1194 mem->bus.is_iomem = true;
1195 break;
1196 }
1197
1198 if (dev_priv->card_type >= NV_C0)
1199 page_shift = node->page_shift;
1200 else
1201 page_shift = 12;
1202
1203 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
1204 page_shift, NV_MEM_ACCESS_RW,
1205 &node->bar_vma);
1206 if (ret)
1207 return ret;
1208
1209 nouveau_vm_map(&node->bar_vma, node);
1210 if (ret) {
1211 nouveau_vm_put(&node->bar_vma);
1212 return ret;
1213 }
1214
1215 mem->bus.offset = node->bar_vma.offset;
1216 if (dev_priv->card_type == NV_50) /*XXX*/
1217 mem->bus.offset -= 0x0020000000ULL;
1218 mem->bus.base = pci_resource_start(dev->pdev, 1);
1219 mem->bus.is_iomem = true;
1220 }
1221 break;
1222 default:
1223 return -EINVAL;
1224 }
1225 return 0;
1226}
1227
1228static void
1229nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1230{
1231 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
1232 struct nouveau_mem *node = mem->mm_node;
1233
1234 if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
1235 return;
1236
1237 if (!node->bar_vma.node)
1238 return;
1239
1240 nouveau_vm_unmap(&node->bar_vma);
1241 nouveau_vm_put(&node->bar_vma);
1242}
1243
1244static int
1245nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1246{
1247 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1248 struct nouveau_bo *nvbo = nouveau_bo(bo);
1249
1250 /* as long as the bo isn't in vram, and isn't tiled, we've got
1251 * nothing to do here.
1252 */
1253 if (bo->mem.mem_type != TTM_PL_VRAM) {
1254 if (dev_priv->card_type < NV_50 ||
1255 !nouveau_bo_tile_layout(nvbo))
1256 return 0;
1257 }
1258
1259 /* make sure bo is in mappable vram */
1260 if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
1261 return 0;
1262
1263
1264 nvbo->placement.fpfn = 0;
1265 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
1266 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1267 return nouveau_bo_validate(nvbo, false, true, false);
1268}
1269
1270static int
1271nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1272{
1273 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1274 struct drm_nouveau_private *dev_priv;
1275 struct drm_device *dev;
1276 unsigned i;
1277 int r;
1278 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1279
1280 if (ttm->state != tt_unpopulated)
1281 return 0;
1282
1283 if (slave && ttm->sg) {
1284 /* make userspace faulting work */
1285 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1286 ttm_dma->dma_address, ttm->num_pages);
1287 ttm->state = tt_unbound;
1288 return 0;
1289 }
1290
1291 dev_priv = nouveau_bdev(ttm->bdev);
1292 dev = dev_priv->dev;
1293
1294#if __OS_HAS_AGP
1295 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
1296 return ttm_agp_tt_populate(ttm);
1297 }
1298#endif
1299
1300#ifdef CONFIG_SWIOTLB
1301 if (swiotlb_nr_tbl()) {
1302 return ttm_dma_populate((void *)ttm, dev->dev);
1303 }
1304#endif
1305
1306 r = ttm_pool_populate(ttm);
1307 if (r) {
1308 return r;
1309 }
1310
1311 for (i = 0; i < ttm->num_pages; i++) {
1312 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
1313 0, PAGE_SIZE,
1314 PCI_DMA_BIDIRECTIONAL);
1315 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
1316 while (--i) {
1317 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1318 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1319 ttm_dma->dma_address[i] = 0;
1320 }
1321 ttm_pool_unpopulate(ttm);
1322 return -EFAULT;
1323 }
1324 }
1325 return 0;
1326}
1327
1328static void
1329nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1330{
1331 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1332 struct drm_nouveau_private *dev_priv;
1333 struct drm_device *dev;
1334 unsigned i;
1335 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1336
1337 if (slave)
1338 return;
1339
1340 dev_priv = nouveau_bdev(ttm->bdev);
1341 dev = dev_priv->dev;
1342
1343#if __OS_HAS_AGP
1344 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
1345 ttm_agp_tt_unpopulate(ttm);
1346 return;
1347 }
1348#endif
1349
1350#ifdef CONFIG_SWIOTLB
1351 if (swiotlb_nr_tbl()) {
1352 ttm_dma_unpopulate((void *)ttm, dev->dev);
1353 return;
1354 }
1355#endif
1356
1357 for (i = 0; i < ttm->num_pages; i++) {
1358 if (ttm_dma->dma_address[i]) {
1359 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
1360 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1361 }
1362 }
1363
1364 ttm_pool_unpopulate(ttm);
1365}
1366
1367void
1368nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1369{
1370 struct nouveau_fence *old_fence = NULL;
1371
1372 if (likely(fence))
1373 nouveau_fence_ref(fence);
1374
1375 spin_lock(&nvbo->bo.bdev->fence_lock);
1376 old_fence = nvbo->bo.sync_obj;
1377 nvbo->bo.sync_obj = fence;
1378 spin_unlock(&nvbo->bo.bdev->fence_lock);
1379
1380 nouveau_fence_unref(&old_fence);
1381}
1382
1383static void
1384nouveau_bo_fence_unref(void **sync_obj)
1385{
1386 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1387}
1388
1389static void *
1390nouveau_bo_fence_ref(void *sync_obj)
1391{
1392 return nouveau_fence_ref(sync_obj);
1393}
1394
1395static bool
1396nouveau_bo_fence_signalled(void *sync_obj, void *sync_arg)
1397{
1398 return nouveau_fence_done(sync_obj);
1399}
1400
1401static int
1402nouveau_bo_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
1403{
1404 return nouveau_fence_wait(sync_obj, lazy, intr);
1405}
1406
1407static int
1408nouveau_bo_fence_flush(void *sync_obj, void *sync_arg)
1409{
1410 return 0;
1411}
1412
1413struct ttm_bo_driver nouveau_bo_driver = {
1414 .ttm_tt_create = &nouveau_ttm_tt_create,
1415 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1416 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1417 .invalidate_caches = nouveau_bo_invalidate_caches,
1418 .init_mem_type = nouveau_bo_init_mem_type,
1419 .evict_flags = nouveau_bo_evict_flags,
1420 .move_notify = nouveau_bo_move_ntfy,
1421 .move = nouveau_bo_move,
1422 .verify_access = nouveau_bo_verify_access,
1423 .sync_obj_signaled = nouveau_bo_fence_signalled,
1424 .sync_obj_wait = nouveau_bo_fence_wait,
1425 .sync_obj_flush = nouveau_bo_fence_flush,
1426 .sync_obj_unref = nouveau_bo_fence_unref,
1427 .sync_obj_ref = nouveau_bo_fence_ref,
1428 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1429 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1430 .io_mem_free = &nouveau_ttm_io_mem_free,
1431};
1432
1433struct nouveau_vma *
1434nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1435{
1436 struct nouveau_vma *vma;
1437 list_for_each_entry(vma, &nvbo->vma_list, head) {
1438 if (vma->vm == vm)
1439 return vma;
1440 }
1441
1442 return NULL;
1443}
1444
1445int
1446nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1447 struct nouveau_vma *vma)
1448{
1449 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1450 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1451 int ret;
1452
1453 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1454 NV_MEM_ACCESS_RW, vma);
1455 if (ret)
1456 return ret;
1457
1458 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1459 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1460 else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
1461 if (node->sg)
1462 nouveau_vm_map_sg_table(vma, 0, size, node);
1463 else
1464 nouveau_vm_map_sg(vma, 0, size, node);
1465 }
1466
1467 list_add_tail(&vma->head, &nvbo->vma_list);
1468 vma->refcount = 1;
1469 return 0;
1470}
1471
1472void
1473nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1474{
1475 if (vma->node) {
1476 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
1477 spin_lock(&nvbo->bo.bdev->fence_lock);
1478 ttm_bo_wait(&nvbo->bo, false, false, false);
1479 spin_unlock(&nvbo->bo.bdev->fence_lock);
1480 nouveau_vm_unmap(vma);
1481 }
1482
1483 nouveau_vm_put(vma);
1484 list_del(&vma->head);
1485 }
1486}