Loading...
1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include "drmP.h"
31
32#include "nouveau_drm.h"
33#include "nouveau_drv.h"
34#include "nouveau_dma.h"
35#include "nouveau_mm.h"
36#include "nouveau_vm.h"
37
38#include <linux/log2.h>
39#include <linux/slab.h>
40
41static void
42nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
43{
44 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
45 struct drm_device *dev = dev_priv->dev;
46 struct nouveau_bo *nvbo = nouveau_bo(bo);
47
48 if (unlikely(nvbo->gem))
49 DRM_ERROR("bo %p still attached to GEM object\n", bo);
50
51 nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
52 kfree(nvbo);
53}
54
55static void
56nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
57 int *align, int *size)
58{
59 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
60
61 if (dev_priv->card_type < NV_50) {
62 if (nvbo->tile_mode) {
63 if (dev_priv->chipset >= 0x40) {
64 *align = 65536;
65 *size = roundup(*size, 64 * nvbo->tile_mode);
66
67 } else if (dev_priv->chipset >= 0x30) {
68 *align = 32768;
69 *size = roundup(*size, 64 * nvbo->tile_mode);
70
71 } else if (dev_priv->chipset >= 0x20) {
72 *align = 16384;
73 *size = roundup(*size, 64 * nvbo->tile_mode);
74
75 } else if (dev_priv->chipset >= 0x10) {
76 *align = 16384;
77 *size = roundup(*size, 32 * nvbo->tile_mode);
78 }
79 }
80 } else {
81 *size = roundup(*size, (1 << nvbo->page_shift));
82 *align = max((1 << nvbo->page_shift), *align);
83 }
84
85 *size = roundup(*size, PAGE_SIZE);
86}
87
88int
89nouveau_bo_new(struct drm_device *dev, int size, int align,
90 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
91 struct nouveau_bo **pnvbo)
92{
93 struct drm_nouveau_private *dev_priv = dev->dev_private;
94 struct nouveau_bo *nvbo;
95 int ret;
96
97 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
98 if (!nvbo)
99 return -ENOMEM;
100 INIT_LIST_HEAD(&nvbo->head);
101 INIT_LIST_HEAD(&nvbo->entry);
102 INIT_LIST_HEAD(&nvbo->vma_list);
103 nvbo->tile_mode = tile_mode;
104 nvbo->tile_flags = tile_flags;
105 nvbo->bo.bdev = &dev_priv->ttm.bdev;
106
107 nvbo->page_shift = 12;
108 if (dev_priv->bar1_vm) {
109 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
110 nvbo->page_shift = dev_priv->bar1_vm->lpg_shift;
111 }
112
113 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
114 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
115 nouveau_bo_placement_set(nvbo, flags, 0);
116
117 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
118 ttm_bo_type_device, &nvbo->placement,
119 align >> PAGE_SHIFT, 0, false, NULL, size,
120 nouveau_bo_del_ttm);
121 if (ret) {
122 /* ttm will call nouveau_bo_del_ttm if it fails.. */
123 return ret;
124 }
125
126 *pnvbo = nvbo;
127 return 0;
128}
129
130static void
131set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
132{
133 *n = 0;
134
135 if (type & TTM_PL_FLAG_VRAM)
136 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
137 if (type & TTM_PL_FLAG_TT)
138 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
139 if (type & TTM_PL_FLAG_SYSTEM)
140 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
141}
142
143static void
144set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
145{
146 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
147 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
148
149 if (dev_priv->card_type == NV_10 &&
150 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
151 nvbo->bo.mem.num_pages < vram_pages / 2) {
152 /*
153 * Make sure that the color and depth buffers are handled
154 * by independent memory controller units. Up to a 9x
155 * speed up when alpha-blending and depth-test are enabled
156 * at the same time.
157 */
158 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
159 nvbo->placement.fpfn = vram_pages / 2;
160 nvbo->placement.lpfn = ~0;
161 } else {
162 nvbo->placement.fpfn = 0;
163 nvbo->placement.lpfn = vram_pages / 2;
164 }
165 }
166}
167
168void
169nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
170{
171 struct ttm_placement *pl = &nvbo->placement;
172 uint32_t flags = TTM_PL_MASK_CACHING |
173 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
174
175 pl->placement = nvbo->placements;
176 set_placement_list(nvbo->placements, &pl->num_placement,
177 type, flags);
178
179 pl->busy_placement = nvbo->busy_placements;
180 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
181 type | busy, flags);
182
183 set_placement_range(nvbo, type);
184}
185
186int
187nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
188{
189 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
190 struct ttm_buffer_object *bo = &nvbo->bo;
191 int ret;
192
193 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
194 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
195 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
196 1 << bo->mem.mem_type, memtype);
197 return -EINVAL;
198 }
199
200 if (nvbo->pin_refcnt++)
201 return 0;
202
203 ret = ttm_bo_reserve(bo, false, false, false, 0);
204 if (ret)
205 goto out;
206
207 nouveau_bo_placement_set(nvbo, memtype, 0);
208
209 ret = nouveau_bo_validate(nvbo, false, false, false);
210 if (ret == 0) {
211 switch (bo->mem.mem_type) {
212 case TTM_PL_VRAM:
213 dev_priv->fb_aper_free -= bo->mem.size;
214 break;
215 case TTM_PL_TT:
216 dev_priv->gart_info.aper_free -= bo->mem.size;
217 break;
218 default:
219 break;
220 }
221 }
222 ttm_bo_unreserve(bo);
223out:
224 if (unlikely(ret))
225 nvbo->pin_refcnt--;
226 return ret;
227}
228
229int
230nouveau_bo_unpin(struct nouveau_bo *nvbo)
231{
232 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
233 struct ttm_buffer_object *bo = &nvbo->bo;
234 int ret;
235
236 if (--nvbo->pin_refcnt)
237 return 0;
238
239 ret = ttm_bo_reserve(bo, false, false, false, 0);
240 if (ret)
241 return ret;
242
243 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
244
245 ret = nouveau_bo_validate(nvbo, false, false, false);
246 if (ret == 0) {
247 switch (bo->mem.mem_type) {
248 case TTM_PL_VRAM:
249 dev_priv->fb_aper_free += bo->mem.size;
250 break;
251 case TTM_PL_TT:
252 dev_priv->gart_info.aper_free += bo->mem.size;
253 break;
254 default:
255 break;
256 }
257 }
258
259 ttm_bo_unreserve(bo);
260 return ret;
261}
262
263int
264nouveau_bo_map(struct nouveau_bo *nvbo)
265{
266 int ret;
267
268 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
269 if (ret)
270 return ret;
271
272 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
273 ttm_bo_unreserve(&nvbo->bo);
274 return ret;
275}
276
277void
278nouveau_bo_unmap(struct nouveau_bo *nvbo)
279{
280 if (nvbo)
281 ttm_bo_kunmap(&nvbo->kmap);
282}
283
284int
285nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
286 bool no_wait_reserve, bool no_wait_gpu)
287{
288 int ret;
289
290 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
291 no_wait_reserve, no_wait_gpu);
292 if (ret)
293 return ret;
294
295 return 0;
296}
297
298u16
299nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
300{
301 bool is_iomem;
302 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
303 mem = &mem[index];
304 if (is_iomem)
305 return ioread16_native((void __force __iomem *)mem);
306 else
307 return *mem;
308}
309
310void
311nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
312{
313 bool is_iomem;
314 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
315 mem = &mem[index];
316 if (is_iomem)
317 iowrite16_native(val, (void __force __iomem *)mem);
318 else
319 *mem = val;
320}
321
322u32
323nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
324{
325 bool is_iomem;
326 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
327 mem = &mem[index];
328 if (is_iomem)
329 return ioread32_native((void __force __iomem *)mem);
330 else
331 return *mem;
332}
333
334void
335nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
336{
337 bool is_iomem;
338 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
339 mem = &mem[index];
340 if (is_iomem)
341 iowrite32_native(val, (void __force __iomem *)mem);
342 else
343 *mem = val;
344}
345
346static struct ttm_backend *
347nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
348{
349 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
350 struct drm_device *dev = dev_priv->dev;
351
352 switch (dev_priv->gart_info.type) {
353#if __OS_HAS_AGP
354 case NOUVEAU_GART_AGP:
355 return ttm_agp_backend_init(bdev, dev->agp->bridge);
356#endif
357 case NOUVEAU_GART_PDMA:
358 case NOUVEAU_GART_HW:
359 return nouveau_sgdma_init_ttm(dev);
360 default:
361 NV_ERROR(dev, "Unknown GART type %d\n",
362 dev_priv->gart_info.type);
363 break;
364 }
365
366 return NULL;
367}
368
369static int
370nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
371{
372 /* We'll do this from user space. */
373 return 0;
374}
375
376static int
377nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
378 struct ttm_mem_type_manager *man)
379{
380 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
381 struct drm_device *dev = dev_priv->dev;
382
383 switch (type) {
384 case TTM_PL_SYSTEM:
385 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
386 man->available_caching = TTM_PL_MASK_CACHING;
387 man->default_caching = TTM_PL_FLAG_CACHED;
388 break;
389 case TTM_PL_VRAM:
390 if (dev_priv->card_type >= NV_50) {
391 man->func = &nouveau_vram_manager;
392 man->io_reserve_fastpath = false;
393 man->use_io_reserve_lru = true;
394 } else {
395 man->func = &ttm_bo_manager_func;
396 }
397 man->flags = TTM_MEMTYPE_FLAG_FIXED |
398 TTM_MEMTYPE_FLAG_MAPPABLE;
399 man->available_caching = TTM_PL_FLAG_UNCACHED |
400 TTM_PL_FLAG_WC;
401 man->default_caching = TTM_PL_FLAG_WC;
402 break;
403 case TTM_PL_TT:
404 if (dev_priv->card_type >= NV_50)
405 man->func = &nouveau_gart_manager;
406 else
407 man->func = &ttm_bo_manager_func;
408 switch (dev_priv->gart_info.type) {
409 case NOUVEAU_GART_AGP:
410 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
411 man->available_caching = TTM_PL_FLAG_UNCACHED |
412 TTM_PL_FLAG_WC;
413 man->default_caching = TTM_PL_FLAG_WC;
414 break;
415 case NOUVEAU_GART_PDMA:
416 case NOUVEAU_GART_HW:
417 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
418 TTM_MEMTYPE_FLAG_CMA;
419 man->available_caching = TTM_PL_MASK_CACHING;
420 man->default_caching = TTM_PL_FLAG_CACHED;
421 break;
422 default:
423 NV_ERROR(dev, "Unknown GART type: %d\n",
424 dev_priv->gart_info.type);
425 return -EINVAL;
426 }
427 break;
428 default:
429 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
430 return -EINVAL;
431 }
432 return 0;
433}
434
435static void
436nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
437{
438 struct nouveau_bo *nvbo = nouveau_bo(bo);
439
440 switch (bo->mem.mem_type) {
441 case TTM_PL_VRAM:
442 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
443 TTM_PL_FLAG_SYSTEM);
444 break;
445 default:
446 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
447 break;
448 }
449
450 *pl = nvbo->placement;
451}
452
453
454/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
455 * TTM_PL_{VRAM,TT} directly.
456 */
457
458static int
459nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
460 struct nouveau_bo *nvbo, bool evict,
461 bool no_wait_reserve, bool no_wait_gpu,
462 struct ttm_mem_reg *new_mem)
463{
464 struct nouveau_fence *fence = NULL;
465 int ret;
466
467 ret = nouveau_fence_new(chan, &fence, true);
468 if (ret)
469 return ret;
470
471 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
472 no_wait_reserve, no_wait_gpu, new_mem);
473 nouveau_fence_unref(&fence);
474 return ret;
475}
476
477static int
478nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
479 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
480{
481 struct nouveau_mem *node = old_mem->mm_node;
482 u64 src_offset = node->vma[0].offset;
483 u64 dst_offset = node->vma[1].offset;
484 u32 page_count = new_mem->num_pages;
485 int ret;
486
487 page_count = new_mem->num_pages;
488 while (page_count) {
489 int line_count = (page_count > 2047) ? 2047 : page_count;
490
491 ret = RING_SPACE(chan, 12);
492 if (ret)
493 return ret;
494
495 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0238, 2);
496 OUT_RING (chan, upper_32_bits(dst_offset));
497 OUT_RING (chan, lower_32_bits(dst_offset));
498 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x030c, 6);
499 OUT_RING (chan, upper_32_bits(src_offset));
500 OUT_RING (chan, lower_32_bits(src_offset));
501 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
502 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
503 OUT_RING (chan, PAGE_SIZE); /* line_length */
504 OUT_RING (chan, line_count);
505 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0300, 1);
506 OUT_RING (chan, 0x00100110);
507
508 page_count -= line_count;
509 src_offset += (PAGE_SIZE * line_count);
510 dst_offset += (PAGE_SIZE * line_count);
511 }
512
513 return 0;
514}
515
516static int
517nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
518 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
519{
520 struct nouveau_mem *node = old_mem->mm_node;
521 struct nouveau_bo *nvbo = nouveau_bo(bo);
522 u64 length = (new_mem->num_pages << PAGE_SHIFT);
523 u64 src_offset = node->vma[0].offset;
524 u64 dst_offset = node->vma[1].offset;
525 int ret;
526
527 while (length) {
528 u32 amount, stride, height;
529
530 amount = min(length, (u64)(4 * 1024 * 1024));
531 stride = 16 * 4;
532 height = amount / stride;
533
534 if (new_mem->mem_type == TTM_PL_VRAM &&
535 nouveau_bo_tile_layout(nvbo)) {
536 ret = RING_SPACE(chan, 8);
537 if (ret)
538 return ret;
539
540 BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
541 OUT_RING (chan, 0);
542 OUT_RING (chan, 0);
543 OUT_RING (chan, stride);
544 OUT_RING (chan, height);
545 OUT_RING (chan, 1);
546 OUT_RING (chan, 0);
547 OUT_RING (chan, 0);
548 } else {
549 ret = RING_SPACE(chan, 2);
550 if (ret)
551 return ret;
552
553 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
554 OUT_RING (chan, 1);
555 }
556 if (old_mem->mem_type == TTM_PL_VRAM &&
557 nouveau_bo_tile_layout(nvbo)) {
558 ret = RING_SPACE(chan, 8);
559 if (ret)
560 return ret;
561
562 BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
563 OUT_RING (chan, 0);
564 OUT_RING (chan, 0);
565 OUT_RING (chan, stride);
566 OUT_RING (chan, height);
567 OUT_RING (chan, 1);
568 OUT_RING (chan, 0);
569 OUT_RING (chan, 0);
570 } else {
571 ret = RING_SPACE(chan, 2);
572 if (ret)
573 return ret;
574
575 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
576 OUT_RING (chan, 1);
577 }
578
579 ret = RING_SPACE(chan, 14);
580 if (ret)
581 return ret;
582
583 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
584 OUT_RING (chan, upper_32_bits(src_offset));
585 OUT_RING (chan, upper_32_bits(dst_offset));
586 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
587 OUT_RING (chan, lower_32_bits(src_offset));
588 OUT_RING (chan, lower_32_bits(dst_offset));
589 OUT_RING (chan, stride);
590 OUT_RING (chan, stride);
591 OUT_RING (chan, stride);
592 OUT_RING (chan, height);
593 OUT_RING (chan, 0x00000101);
594 OUT_RING (chan, 0x00000000);
595 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
596 OUT_RING (chan, 0);
597
598 length -= amount;
599 src_offset += amount;
600 dst_offset += amount;
601 }
602
603 return 0;
604}
605
606static inline uint32_t
607nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
608 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
609{
610 if (mem->mem_type == TTM_PL_TT)
611 return chan->gart_handle;
612 return chan->vram_handle;
613}
614
615static int
616nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
617 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
618{
619 u32 src_offset = old_mem->start << PAGE_SHIFT;
620 u32 dst_offset = new_mem->start << PAGE_SHIFT;
621 u32 page_count = new_mem->num_pages;
622 int ret;
623
624 ret = RING_SPACE(chan, 3);
625 if (ret)
626 return ret;
627
628 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
629 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
630 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
631
632 page_count = new_mem->num_pages;
633 while (page_count) {
634 int line_count = (page_count > 2047) ? 2047 : page_count;
635
636 ret = RING_SPACE(chan, 11);
637 if (ret)
638 return ret;
639
640 BEGIN_RING(chan, NvSubM2MF,
641 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
642 OUT_RING (chan, src_offset);
643 OUT_RING (chan, dst_offset);
644 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
645 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
646 OUT_RING (chan, PAGE_SIZE); /* line_length */
647 OUT_RING (chan, line_count);
648 OUT_RING (chan, 0x00000101);
649 OUT_RING (chan, 0x00000000);
650 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
651 OUT_RING (chan, 0);
652
653 page_count -= line_count;
654 src_offset += (PAGE_SIZE * line_count);
655 dst_offset += (PAGE_SIZE * line_count);
656 }
657
658 return 0;
659}
660
661static int
662nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
663 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
664{
665 struct nouveau_mem *node = mem->mm_node;
666 int ret;
667
668 ret = nouveau_vm_get(chan->vm, mem->num_pages << PAGE_SHIFT,
669 node->page_shift, NV_MEM_ACCESS_RO, vma);
670 if (ret)
671 return ret;
672
673 if (mem->mem_type == TTM_PL_VRAM)
674 nouveau_vm_map(vma, node);
675 else
676 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT,
677 node, node->pages);
678
679 return 0;
680}
681
682static int
683nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
684 bool no_wait_reserve, bool no_wait_gpu,
685 struct ttm_mem_reg *new_mem)
686{
687 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
688 struct nouveau_bo *nvbo = nouveau_bo(bo);
689 struct ttm_mem_reg *old_mem = &bo->mem;
690 struct nouveau_channel *chan;
691 int ret;
692
693 chan = nvbo->channel;
694 if (!chan) {
695 chan = dev_priv->channel;
696 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
697 }
698
699 /* create temporary vmas for the transfer and attach them to the
700 * old nouveau_mem node, these will get cleaned up after ttm has
701 * destroyed the ttm_mem_reg
702 */
703 if (dev_priv->card_type >= NV_50) {
704 struct nouveau_mem *node = old_mem->mm_node;
705
706 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
707 if (ret)
708 goto out;
709
710 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
711 if (ret)
712 goto out;
713 }
714
715 if (dev_priv->card_type < NV_50)
716 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
717 else
718 if (dev_priv->card_type < NV_C0)
719 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
720 else
721 ret = nvc0_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
722 if (ret == 0) {
723 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
724 no_wait_reserve,
725 no_wait_gpu, new_mem);
726 }
727
728out:
729 if (chan == dev_priv->channel)
730 mutex_unlock(&chan->mutex);
731 return ret;
732}
733
734static int
735nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
736 bool no_wait_reserve, bool no_wait_gpu,
737 struct ttm_mem_reg *new_mem)
738{
739 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
740 struct ttm_placement placement;
741 struct ttm_mem_reg tmp_mem;
742 int ret;
743
744 placement.fpfn = placement.lpfn = 0;
745 placement.num_placement = placement.num_busy_placement = 1;
746 placement.placement = placement.busy_placement = &placement_memtype;
747
748 tmp_mem = *new_mem;
749 tmp_mem.mm_node = NULL;
750 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
751 if (ret)
752 return ret;
753
754 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
755 if (ret)
756 goto out;
757
758 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
759 if (ret)
760 goto out;
761
762 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
763out:
764 ttm_bo_mem_put(bo, &tmp_mem);
765 return ret;
766}
767
768static int
769nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
770 bool no_wait_reserve, bool no_wait_gpu,
771 struct ttm_mem_reg *new_mem)
772{
773 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
774 struct ttm_placement placement;
775 struct ttm_mem_reg tmp_mem;
776 int ret;
777
778 placement.fpfn = placement.lpfn = 0;
779 placement.num_placement = placement.num_busy_placement = 1;
780 placement.placement = placement.busy_placement = &placement_memtype;
781
782 tmp_mem = *new_mem;
783 tmp_mem.mm_node = NULL;
784 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
785 if (ret)
786 return ret;
787
788 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
789 if (ret)
790 goto out;
791
792 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
793 if (ret)
794 goto out;
795
796out:
797 ttm_bo_mem_put(bo, &tmp_mem);
798 return ret;
799}
800
801static void
802nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
803{
804 struct nouveau_mem *node = new_mem->mm_node;
805 struct nouveau_bo *nvbo = nouveau_bo(bo);
806 struct nouveau_vma *vma;
807
808 list_for_each_entry(vma, &nvbo->vma_list, head) {
809 if (new_mem->mem_type == TTM_PL_VRAM) {
810 nouveau_vm_map(vma, new_mem->mm_node);
811 } else
812 if (new_mem->mem_type == TTM_PL_TT &&
813 nvbo->page_shift == vma->vm->spg_shift) {
814 nouveau_vm_map_sg(vma, 0, new_mem->
815 num_pages << PAGE_SHIFT,
816 node, node->pages);
817 } else {
818 nouveau_vm_unmap(vma);
819 }
820 }
821}
822
823static int
824nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
825 struct nouveau_tile_reg **new_tile)
826{
827 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
828 struct drm_device *dev = dev_priv->dev;
829 struct nouveau_bo *nvbo = nouveau_bo(bo);
830 u64 offset = new_mem->start << PAGE_SHIFT;
831
832 *new_tile = NULL;
833 if (new_mem->mem_type != TTM_PL_VRAM)
834 return 0;
835
836 if (dev_priv->card_type >= NV_10) {
837 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
838 nvbo->tile_mode,
839 nvbo->tile_flags);
840 }
841
842 return 0;
843}
844
845static void
846nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
847 struct nouveau_tile_reg *new_tile,
848 struct nouveau_tile_reg **old_tile)
849{
850 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
851 struct drm_device *dev = dev_priv->dev;
852
853 nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
854 *old_tile = new_tile;
855}
856
857static int
858nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
859 bool no_wait_reserve, bool no_wait_gpu,
860 struct ttm_mem_reg *new_mem)
861{
862 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
863 struct nouveau_bo *nvbo = nouveau_bo(bo);
864 struct ttm_mem_reg *old_mem = &bo->mem;
865 struct nouveau_tile_reg *new_tile = NULL;
866 int ret = 0;
867
868 if (dev_priv->card_type < NV_50) {
869 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
870 if (ret)
871 return ret;
872 }
873
874 /* Fake bo copy. */
875 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
876 BUG_ON(bo->mem.mm_node != NULL);
877 bo->mem = *new_mem;
878 new_mem->mm_node = NULL;
879 goto out;
880 }
881
882 /* Software copy if the card isn't up and running yet. */
883 if (!dev_priv->channel) {
884 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
885 goto out;
886 }
887
888 /* Hardware assisted copy. */
889 if (new_mem->mem_type == TTM_PL_SYSTEM)
890 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
891 else if (old_mem->mem_type == TTM_PL_SYSTEM)
892 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
893 else
894 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
895
896 if (!ret)
897 goto out;
898
899 /* Fallback to software copy. */
900 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
901
902out:
903 if (dev_priv->card_type < NV_50) {
904 if (ret)
905 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
906 else
907 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
908 }
909
910 return ret;
911}
912
913static int
914nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
915{
916 return 0;
917}
918
919static int
920nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
921{
922 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
923 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
924 struct drm_device *dev = dev_priv->dev;
925 int ret;
926
927 mem->bus.addr = NULL;
928 mem->bus.offset = 0;
929 mem->bus.size = mem->num_pages << PAGE_SHIFT;
930 mem->bus.base = 0;
931 mem->bus.is_iomem = false;
932 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
933 return -EINVAL;
934 switch (mem->mem_type) {
935 case TTM_PL_SYSTEM:
936 /* System memory */
937 return 0;
938 case TTM_PL_TT:
939#if __OS_HAS_AGP
940 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
941 mem->bus.offset = mem->start << PAGE_SHIFT;
942 mem->bus.base = dev_priv->gart_info.aper_base;
943 mem->bus.is_iomem = true;
944 }
945#endif
946 break;
947 case TTM_PL_VRAM:
948 {
949 struct nouveau_mem *node = mem->mm_node;
950 u8 page_shift;
951
952 if (!dev_priv->bar1_vm) {
953 mem->bus.offset = mem->start << PAGE_SHIFT;
954 mem->bus.base = pci_resource_start(dev->pdev, 1);
955 mem->bus.is_iomem = true;
956 break;
957 }
958
959 if (dev_priv->card_type == NV_C0)
960 page_shift = node->page_shift;
961 else
962 page_shift = 12;
963
964 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
965 page_shift, NV_MEM_ACCESS_RW,
966 &node->bar_vma);
967 if (ret)
968 return ret;
969
970 nouveau_vm_map(&node->bar_vma, node);
971 if (ret) {
972 nouveau_vm_put(&node->bar_vma);
973 return ret;
974 }
975
976 mem->bus.offset = node->bar_vma.offset;
977 if (dev_priv->card_type == NV_50) /*XXX*/
978 mem->bus.offset -= 0x0020000000ULL;
979 mem->bus.base = pci_resource_start(dev->pdev, 1);
980 mem->bus.is_iomem = true;
981 }
982 break;
983 default:
984 return -EINVAL;
985 }
986 return 0;
987}
988
989static void
990nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
991{
992 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
993 struct nouveau_mem *node = mem->mm_node;
994
995 if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
996 return;
997
998 if (!node->bar_vma.node)
999 return;
1000
1001 nouveau_vm_unmap(&node->bar_vma);
1002 nouveau_vm_put(&node->bar_vma);
1003}
1004
1005static int
1006nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1007{
1008 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1009 struct nouveau_bo *nvbo = nouveau_bo(bo);
1010
1011 /* as long as the bo isn't in vram, and isn't tiled, we've got
1012 * nothing to do here.
1013 */
1014 if (bo->mem.mem_type != TTM_PL_VRAM) {
1015 if (dev_priv->card_type < NV_50 ||
1016 !nouveau_bo_tile_layout(nvbo))
1017 return 0;
1018 }
1019
1020 /* make sure bo is in mappable vram */
1021 if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
1022 return 0;
1023
1024
1025 nvbo->placement.fpfn = 0;
1026 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
1027 nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
1028 return nouveau_bo_validate(nvbo, false, true, false);
1029}
1030
1031void
1032nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1033{
1034 struct nouveau_fence *old_fence;
1035
1036 if (likely(fence))
1037 nouveau_fence_ref(fence);
1038
1039 spin_lock(&nvbo->bo.bdev->fence_lock);
1040 old_fence = nvbo->bo.sync_obj;
1041 nvbo->bo.sync_obj = fence;
1042 spin_unlock(&nvbo->bo.bdev->fence_lock);
1043
1044 nouveau_fence_unref(&old_fence);
1045}
1046
1047struct ttm_bo_driver nouveau_bo_driver = {
1048 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
1049 .invalidate_caches = nouveau_bo_invalidate_caches,
1050 .init_mem_type = nouveau_bo_init_mem_type,
1051 .evict_flags = nouveau_bo_evict_flags,
1052 .move_notify = nouveau_bo_move_ntfy,
1053 .move = nouveau_bo_move,
1054 .verify_access = nouveau_bo_verify_access,
1055 .sync_obj_signaled = __nouveau_fence_signalled,
1056 .sync_obj_wait = __nouveau_fence_wait,
1057 .sync_obj_flush = __nouveau_fence_flush,
1058 .sync_obj_unref = __nouveau_fence_unref,
1059 .sync_obj_ref = __nouveau_fence_ref,
1060 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1061 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1062 .io_mem_free = &nouveau_ttm_io_mem_free,
1063};
1064
1065struct nouveau_vma *
1066nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1067{
1068 struct nouveau_vma *vma;
1069 list_for_each_entry(vma, &nvbo->vma_list, head) {
1070 if (vma->vm == vm)
1071 return vma;
1072 }
1073
1074 return NULL;
1075}
1076
1077int
1078nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1079 struct nouveau_vma *vma)
1080{
1081 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1082 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1083 int ret;
1084
1085 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1086 NV_MEM_ACCESS_RW, vma);
1087 if (ret)
1088 return ret;
1089
1090 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1091 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1092 else
1093 if (nvbo->bo.mem.mem_type == TTM_PL_TT)
1094 nouveau_vm_map_sg(vma, 0, size, node, node->pages);
1095
1096 list_add_tail(&vma->head, &nvbo->vma_list);
1097 vma->refcount = 1;
1098 return 0;
1099}
1100
1101void
1102nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1103{
1104 if (vma->node) {
1105 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
1106 spin_lock(&nvbo->bo.bdev->fence_lock);
1107 ttm_bo_wait(&nvbo->bo, false, false, false);
1108 spin_unlock(&nvbo->bo.bdev->fence_lock);
1109 nouveau_vm_unmap(vma);
1110 }
1111
1112 nouveau_vm_put(vma);
1113 list_del(&vma->head);
1114 }
1115}
1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <linux/dma-mapping.h>
31
32#include "nouveau_drv.h"
33#include "nouveau_chan.h"
34#include "nouveau_fence.h"
35
36#include "nouveau_bo.h"
37#include "nouveau_ttm.h"
38#include "nouveau_gem.h"
39#include "nouveau_mem.h"
40#include "nouveau_vmm.h"
41
42#include <nvif/class.h>
43#include <nvif/if500b.h>
44#include <nvif/if900b.h>
45
46static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
47 struct ttm_resource *reg);
48static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
49
50/*
51 * NV10-NV40 tiling helpers
52 */
53
54static void
55nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
56 u32 addr, u32 size, u32 pitch, u32 flags)
57{
58 struct nouveau_drm *drm = nouveau_drm(dev);
59 int i = reg - drm->tile.reg;
60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
61 struct nvkm_fb_tile *tile = &fb->tile.region[i];
62
63 nouveau_fence_unref(®->fence);
64
65 if (tile->pitch)
66 nvkm_fb_tile_fini(fb, i, tile);
67
68 if (pitch)
69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
70
71 nvkm_fb_tile_prog(fb, i, tile);
72}
73
74static struct nouveau_drm_tile *
75nv10_bo_get_tile_region(struct drm_device *dev, int i)
76{
77 struct nouveau_drm *drm = nouveau_drm(dev);
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
79
80 spin_lock(&drm->tile.lock);
81
82 if (!tile->used &&
83 (!tile->fence || nouveau_fence_done(tile->fence)))
84 tile->used = true;
85 else
86 tile = NULL;
87
88 spin_unlock(&drm->tile.lock);
89 return tile;
90}
91
92static void
93nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 struct dma_fence *fence)
95{
96 struct nouveau_drm *drm = nouveau_drm(dev);
97
98 if (tile) {
99 spin_lock(&drm->tile.lock);
100 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
101 tile->used = false;
102 spin_unlock(&drm->tile.lock);
103 }
104}
105
106static struct nouveau_drm_tile *
107nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
108 u32 size, u32 pitch, u32 zeta)
109{
110 struct nouveau_drm *drm = nouveau_drm(dev);
111 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
112 struct nouveau_drm_tile *tile, *found = NULL;
113 int i;
114
115 for (i = 0; i < fb->tile.regions; i++) {
116 tile = nv10_bo_get_tile_region(dev, i);
117
118 if (pitch && !found) {
119 found = tile;
120 continue;
121
122 } else if (tile && fb->tile.region[i].pitch) {
123 /* Kill an unused tile region. */
124 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
125 }
126
127 nv10_bo_put_tile_region(dev, tile, NULL);
128 }
129
130 if (found)
131 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
132 return found;
133}
134
135static void
136nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
137{
138 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
139 struct drm_device *dev = drm->dev;
140 struct nouveau_bo *nvbo = nouveau_bo(bo);
141
142 WARN_ON(nvbo->bo.pin_count > 0);
143 nouveau_bo_del_io_reserve_lru(bo);
144 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
145
146 /*
147 * If nouveau_bo_new() allocated this buffer, the GEM object was never
148 * initialized, so don't attempt to release it.
149 */
150 if (bo->base.dev)
151 drm_gem_object_release(&bo->base);
152 else
153 dma_resv_fini(&bo->base._resv);
154
155 kfree(nvbo);
156}
157
158static inline u64
159roundup_64(u64 x, u32 y)
160{
161 x += y - 1;
162 do_div(x, y);
163 return x * y;
164}
165
166static void
167nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
168{
169 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
170 struct nvif_device *device = &drm->client.device;
171
172 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
173 if (nvbo->mode) {
174 if (device->info.chipset >= 0x40) {
175 *align = 65536;
176 *size = roundup_64(*size, 64 * nvbo->mode);
177
178 } else if (device->info.chipset >= 0x30) {
179 *align = 32768;
180 *size = roundup_64(*size, 64 * nvbo->mode);
181
182 } else if (device->info.chipset >= 0x20) {
183 *align = 16384;
184 *size = roundup_64(*size, 64 * nvbo->mode);
185
186 } else if (device->info.chipset >= 0x10) {
187 *align = 16384;
188 *size = roundup_64(*size, 32 * nvbo->mode);
189 }
190 }
191 } else {
192 *size = roundup_64(*size, (1 << nvbo->page));
193 *align = max((1 << nvbo->page), *align);
194 }
195
196 *size = roundup_64(*size, PAGE_SIZE);
197}
198
199struct nouveau_bo *
200nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
201 u32 tile_mode, u32 tile_flags)
202{
203 struct nouveau_drm *drm = cli->drm;
204 struct nouveau_bo *nvbo;
205 struct nvif_mmu *mmu = &cli->mmu;
206 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
207 int i, pi = -1;
208
209 if (!*size) {
210 NV_WARN(drm, "skipped size %016llx\n", *size);
211 return ERR_PTR(-EINVAL);
212 }
213
214 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
215 if (!nvbo)
216 return ERR_PTR(-ENOMEM);
217 INIT_LIST_HEAD(&nvbo->head);
218 INIT_LIST_HEAD(&nvbo->entry);
219 INIT_LIST_HEAD(&nvbo->vma_list);
220 nvbo->bo.bdev = &drm->ttm.bdev;
221
222 /* This is confusing, and doesn't actually mean we want an uncached
223 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
224 * into in nouveau_gem_new().
225 */
226 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
227 /* Determine if we can get a cache-coherent map, forcing
228 * uncached mapping if we can't.
229 */
230 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
231 nvbo->force_coherent = true;
232 }
233
234 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
235 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
236 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
237 kfree(nvbo);
238 return ERR_PTR(-EINVAL);
239 }
240
241 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
242 } else
243 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
244 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
245 nvbo->comp = (tile_flags & 0x00030000) >> 16;
246 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
247 kfree(nvbo);
248 return ERR_PTR(-EINVAL);
249 }
250 } else {
251 nvbo->zeta = (tile_flags & 0x00000007);
252 }
253 nvbo->mode = tile_mode;
254 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
255
256 /* Determine the desirable target GPU page size for the buffer. */
257 for (i = 0; i < vmm->page_nr; i++) {
258 /* Because we cannot currently allow VMM maps to fail
259 * during buffer migration, we need to determine page
260 * size for the buffer up-front, and pre-allocate its
261 * page tables.
262 *
263 * Skip page sizes that can't support needed domains.
264 */
265 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
266 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
267 continue;
268 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
269 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
270 continue;
271
272 /* Select this page size if it's the first that supports
273 * the potential memory domains, or when it's compatible
274 * with the requested compression settings.
275 */
276 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
277 pi = i;
278
279 /* Stop once the buffer is larger than the current page size. */
280 if (*size >= 1ULL << vmm->page[i].shift)
281 break;
282 }
283
284 if (WARN_ON(pi < 0))
285 return ERR_PTR(-EINVAL);
286
287 /* Disable compression if suitable settings couldn't be found. */
288 if (nvbo->comp && !vmm->page[pi].comp) {
289 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
290 nvbo->kind = mmu->kind[nvbo->kind];
291 nvbo->comp = 0;
292 }
293 nvbo->page = vmm->page[pi].shift;
294
295 nouveau_bo_fixup_align(nvbo, align, size);
296
297 return nvbo;
298}
299
300int
301nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
302 struct sg_table *sg, struct dma_resv *robj)
303{
304 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
305 int ret;
306
307 nouveau_bo_placement_set(nvbo, domain, 0);
308 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
309
310 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
311 &nvbo->placement, align >> PAGE_SHIFT, false, sg,
312 robj, nouveau_bo_del_ttm);
313 if (ret) {
314 /* ttm will call nouveau_bo_del_ttm if it fails.. */
315 return ret;
316 }
317
318 return 0;
319}
320
321int
322nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
323 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
324 struct sg_table *sg, struct dma_resv *robj,
325 struct nouveau_bo **pnvbo)
326{
327 struct nouveau_bo *nvbo;
328 int ret;
329
330 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
331 tile_flags);
332 if (IS_ERR(nvbo))
333 return PTR_ERR(nvbo);
334
335 nvbo->bo.base.size = size;
336 dma_resv_init(&nvbo->bo.base._resv);
337 drm_vma_node_reset(&nvbo->bo.base.vma_node);
338
339 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
340 if (ret)
341 return ret;
342
343 *pnvbo = nvbo;
344 return 0;
345}
346
347static void
348set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain)
349{
350 *n = 0;
351
352 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
353 pl[*n].mem_type = TTM_PL_VRAM;
354 pl[*n].flags = 0;
355 (*n)++;
356 }
357 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
358 pl[*n].mem_type = TTM_PL_TT;
359 pl[*n].flags = 0;
360 (*n)++;
361 }
362 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
363 pl[*n].mem_type = TTM_PL_SYSTEM;
364 pl[(*n)++].flags = 0;
365 }
366}
367
368static void
369set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
370{
371 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
372 u64 vram_size = drm->client.device.info.ram_size;
373 unsigned i, fpfn, lpfn;
374
375 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
376 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
377 nvbo->bo.base.size < vram_size / 4) {
378 /*
379 * Make sure that the color and depth buffers are handled
380 * by independent memory controller units. Up to a 9x
381 * speed up when alpha-blending and depth-test are enabled
382 * at the same time.
383 */
384 if (nvbo->zeta) {
385 fpfn = (vram_size / 2) >> PAGE_SHIFT;
386 lpfn = ~0;
387 } else {
388 fpfn = 0;
389 lpfn = (vram_size / 2) >> PAGE_SHIFT;
390 }
391 for (i = 0; i < nvbo->placement.num_placement; ++i) {
392 nvbo->placements[i].fpfn = fpfn;
393 nvbo->placements[i].lpfn = lpfn;
394 }
395 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
396 nvbo->busy_placements[i].fpfn = fpfn;
397 nvbo->busy_placements[i].lpfn = lpfn;
398 }
399 }
400}
401
402void
403nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
404 uint32_t busy)
405{
406 struct ttm_placement *pl = &nvbo->placement;
407
408 pl->placement = nvbo->placements;
409 set_placement_list(nvbo->placements, &pl->num_placement, domain);
410
411 pl->busy_placement = nvbo->busy_placements;
412 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
413 domain | busy);
414
415 set_placement_range(nvbo, domain);
416}
417
418int
419nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
420{
421 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
422 struct ttm_buffer_object *bo = &nvbo->bo;
423 bool force = false, evict = false;
424 int ret;
425
426 ret = ttm_bo_reserve(bo, false, false, NULL);
427 if (ret)
428 return ret;
429
430 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
431 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
432 if (!nvbo->contig) {
433 nvbo->contig = true;
434 force = true;
435 evict = true;
436 }
437 }
438
439 if (nvbo->bo.pin_count) {
440 bool error = evict;
441
442 switch (bo->resource->mem_type) {
443 case TTM_PL_VRAM:
444 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
445 break;
446 case TTM_PL_TT:
447 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
448 break;
449 default:
450 break;
451 }
452
453 if (error) {
454 NV_ERROR(drm, "bo %p pinned elsewhere: "
455 "0x%08x vs 0x%08x\n", bo,
456 bo->resource->mem_type, domain);
457 ret = -EBUSY;
458 }
459 ttm_bo_pin(&nvbo->bo);
460 goto out;
461 }
462
463 if (evict) {
464 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
465 ret = nouveau_bo_validate(nvbo, false, false);
466 if (ret)
467 goto out;
468 }
469
470 nouveau_bo_placement_set(nvbo, domain, 0);
471 ret = nouveau_bo_validate(nvbo, false, false);
472 if (ret)
473 goto out;
474
475 ttm_bo_pin(&nvbo->bo);
476
477 switch (bo->resource->mem_type) {
478 case TTM_PL_VRAM:
479 drm->gem.vram_available -= bo->base.size;
480 break;
481 case TTM_PL_TT:
482 drm->gem.gart_available -= bo->base.size;
483 break;
484 default:
485 break;
486 }
487
488out:
489 if (force && ret)
490 nvbo->contig = false;
491 ttm_bo_unreserve(bo);
492 return ret;
493}
494
495int
496nouveau_bo_unpin(struct nouveau_bo *nvbo)
497{
498 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
499 struct ttm_buffer_object *bo = &nvbo->bo;
500 int ret;
501
502 ret = ttm_bo_reserve(bo, false, false, NULL);
503 if (ret)
504 return ret;
505
506 ttm_bo_unpin(&nvbo->bo);
507 if (!nvbo->bo.pin_count) {
508 switch (bo->resource->mem_type) {
509 case TTM_PL_VRAM:
510 drm->gem.vram_available += bo->base.size;
511 break;
512 case TTM_PL_TT:
513 drm->gem.gart_available += bo->base.size;
514 break;
515 default:
516 break;
517 }
518 }
519
520 ttm_bo_unreserve(bo);
521 return 0;
522}
523
524int
525nouveau_bo_map(struct nouveau_bo *nvbo)
526{
527 int ret;
528
529 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
530 if (ret)
531 return ret;
532
533 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.resource->num_pages, &nvbo->kmap);
534
535 ttm_bo_unreserve(&nvbo->bo);
536 return ret;
537}
538
539void
540nouveau_bo_unmap(struct nouveau_bo *nvbo)
541{
542 if (!nvbo)
543 return;
544
545 ttm_bo_kunmap(&nvbo->kmap);
546}
547
548void
549nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
550{
551 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
552 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
553 int i, j;
554
555 if (!ttm_dma || !ttm_dma->dma_address)
556 return;
557 if (!ttm_dma->pages) {
558 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
559 return;
560 }
561
562 /* Don't waste time looping if the object is coherent */
563 if (nvbo->force_coherent)
564 return;
565
566 i = 0;
567 while (i < ttm_dma->num_pages) {
568 struct page *p = ttm_dma->pages[i];
569 size_t num_pages = 1;
570
571 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
572 if (++p != ttm_dma->pages[j])
573 break;
574
575 ++num_pages;
576 }
577 dma_sync_single_for_device(drm->dev->dev,
578 ttm_dma->dma_address[i],
579 num_pages * PAGE_SIZE, DMA_TO_DEVICE);
580 i += num_pages;
581 }
582}
583
584void
585nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
586{
587 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
588 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
589 int i, j;
590
591 if (!ttm_dma || !ttm_dma->dma_address)
592 return;
593 if (!ttm_dma->pages) {
594 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
595 return;
596 }
597
598 /* Don't waste time looping if the object is coherent */
599 if (nvbo->force_coherent)
600 return;
601
602 i = 0;
603 while (i < ttm_dma->num_pages) {
604 struct page *p = ttm_dma->pages[i];
605 size_t num_pages = 1;
606
607 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
608 if (++p != ttm_dma->pages[j])
609 break;
610
611 ++num_pages;
612 }
613
614 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
615 num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
616 i += num_pages;
617 }
618}
619
620void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
621{
622 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
623 struct nouveau_bo *nvbo = nouveau_bo(bo);
624
625 mutex_lock(&drm->ttm.io_reserve_mutex);
626 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
627 mutex_unlock(&drm->ttm.io_reserve_mutex);
628}
629
630void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
631{
632 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
633 struct nouveau_bo *nvbo = nouveau_bo(bo);
634
635 mutex_lock(&drm->ttm.io_reserve_mutex);
636 list_del_init(&nvbo->io_reserve_lru);
637 mutex_unlock(&drm->ttm.io_reserve_mutex);
638}
639
640int
641nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
642 bool no_wait_gpu)
643{
644 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
645 int ret;
646
647 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
648 if (ret)
649 return ret;
650
651 nouveau_bo_sync_for_device(nvbo);
652
653 return 0;
654}
655
656void
657nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
658{
659 bool is_iomem;
660 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
661
662 mem += index;
663
664 if (is_iomem)
665 iowrite16_native(val, (void __force __iomem *)mem);
666 else
667 *mem = val;
668}
669
670u32
671nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
672{
673 bool is_iomem;
674 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
675
676 mem += index;
677
678 if (is_iomem)
679 return ioread32_native((void __force __iomem *)mem);
680 else
681 return *mem;
682}
683
684void
685nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
686{
687 bool is_iomem;
688 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
689
690 mem += index;
691
692 if (is_iomem)
693 iowrite32_native(val, (void __force __iomem *)mem);
694 else
695 *mem = val;
696}
697
698static struct ttm_tt *
699nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
700{
701#if IS_ENABLED(CONFIG_AGP)
702 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
703
704 if (drm->agp.bridge) {
705 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
706 }
707#endif
708
709 return nouveau_sgdma_create_ttm(bo, page_flags);
710}
711
712static int
713nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
714 struct ttm_resource *reg)
715{
716#if IS_ENABLED(CONFIG_AGP)
717 struct nouveau_drm *drm = nouveau_bdev(bdev);
718#endif
719 if (!reg)
720 return -EINVAL;
721#if IS_ENABLED(CONFIG_AGP)
722 if (drm->agp.bridge)
723 return ttm_agp_bind(ttm, reg);
724#endif
725 return nouveau_sgdma_bind(bdev, ttm, reg);
726}
727
728static void
729nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
730{
731#if IS_ENABLED(CONFIG_AGP)
732 struct nouveau_drm *drm = nouveau_bdev(bdev);
733
734 if (drm->agp.bridge) {
735 ttm_agp_unbind(ttm);
736 return;
737 }
738#endif
739 nouveau_sgdma_unbind(bdev, ttm);
740}
741
742static void
743nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
744{
745 struct nouveau_bo *nvbo = nouveau_bo(bo);
746
747 switch (bo->resource->mem_type) {
748 case TTM_PL_VRAM:
749 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
750 NOUVEAU_GEM_DOMAIN_CPU);
751 break;
752 default:
753 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
754 break;
755 }
756
757 *pl = nvbo->placement;
758}
759
760static int
761nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
762 struct ttm_resource *reg)
763{
764 struct nouveau_mem *old_mem = nouveau_mem(bo->resource);
765 struct nouveau_mem *new_mem = nouveau_mem(reg);
766 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
767 int ret;
768
769 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
770 old_mem->mem.size, &old_mem->vma[0]);
771 if (ret)
772 return ret;
773
774 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
775 new_mem->mem.size, &old_mem->vma[1]);
776 if (ret)
777 goto done;
778
779 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
780 if (ret)
781 goto done;
782
783 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
784done:
785 if (ret) {
786 nvif_vmm_put(vmm, &old_mem->vma[1]);
787 nvif_vmm_put(vmm, &old_mem->vma[0]);
788 }
789 return 0;
790}
791
792static int
793nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
794 struct ttm_operation_ctx *ctx,
795 struct ttm_resource *new_reg)
796{
797 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
798 struct nouveau_channel *chan = drm->ttm.chan;
799 struct nouveau_cli *cli = (void *)chan->user.client;
800 struct nouveau_fence *fence;
801 int ret;
802
803 /* create temporary vmas for the transfer and attach them to the
804 * old nvkm_mem node, these will get cleaned up after ttm has
805 * destroyed the ttm_resource
806 */
807 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
808 ret = nouveau_bo_move_prep(drm, bo, new_reg);
809 if (ret)
810 return ret;
811 }
812
813 if (drm_drv_uses_atomic_modeset(drm->dev))
814 mutex_lock(&cli->mutex);
815 else
816 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
817 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
818 if (ret == 0) {
819 ret = drm->ttm.move(chan, bo, bo->resource, new_reg);
820 if (ret == 0) {
821 ret = nouveau_fence_new(chan, false, &fence);
822 if (ret == 0) {
823 ret = ttm_bo_move_accel_cleanup(bo,
824 &fence->base,
825 evict, false,
826 new_reg);
827 nouveau_fence_unref(&fence);
828 }
829 }
830 }
831 mutex_unlock(&cli->mutex);
832 return ret;
833}
834
835void
836nouveau_bo_move_init(struct nouveau_drm *drm)
837{
838 static const struct _method_table {
839 const char *name;
840 int engine;
841 s32 oclass;
842 int (*exec)(struct nouveau_channel *,
843 struct ttm_buffer_object *,
844 struct ttm_resource *, struct ttm_resource *);
845 int (*init)(struct nouveau_channel *, u32 handle);
846 } _methods[] = {
847 { "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },
848 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
849 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
850 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
851 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
852 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
853 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
854 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
855 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
856 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
857 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
858 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
859 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
860 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
861 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
862 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
863 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
864 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
865 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
866 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
867 {},
868 };
869 const struct _method_table *mthd = _methods;
870 const char *name = "CPU";
871 int ret;
872
873 do {
874 struct nouveau_channel *chan;
875
876 if (mthd->engine)
877 chan = drm->cechan;
878 else
879 chan = drm->channel;
880 if (chan == NULL)
881 continue;
882
883 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
884 mthd->oclass | (mthd->engine << 16),
885 mthd->oclass, NULL, 0,
886 &drm->ttm.copy);
887 if (ret == 0) {
888 ret = mthd->init(chan, drm->ttm.copy.handle);
889 if (ret) {
890 nvif_object_dtor(&drm->ttm.copy);
891 continue;
892 }
893
894 drm->ttm.move = mthd->exec;
895 drm->ttm.chan = chan;
896 name = mthd->name;
897 break;
898 }
899 } while ((++mthd)->exec);
900
901 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
902}
903
904static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
905 struct ttm_resource *new_reg)
906{
907 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
908 struct nouveau_bo *nvbo = nouveau_bo(bo);
909 struct nouveau_vma *vma;
910
911 /* ttm can now (stupidly) pass the driver bos it didn't create... */
912 if (bo->destroy != nouveau_bo_del_ttm)
913 return;
914
915 nouveau_bo_del_io_reserve_lru(bo);
916
917 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
918 mem->mem.page == nvbo->page) {
919 list_for_each_entry(vma, &nvbo->vma_list, head) {
920 nouveau_vma_map(vma, mem);
921 }
922 } else {
923 list_for_each_entry(vma, &nvbo->vma_list, head) {
924 WARN_ON(ttm_bo_wait(bo, false, false));
925 nouveau_vma_unmap(vma);
926 }
927 }
928
929 if (new_reg)
930 nvbo->offset = (new_reg->start << PAGE_SHIFT);
931
932}
933
934static int
935nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
936 struct nouveau_drm_tile **new_tile)
937{
938 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
939 struct drm_device *dev = drm->dev;
940 struct nouveau_bo *nvbo = nouveau_bo(bo);
941 u64 offset = new_reg->start << PAGE_SHIFT;
942
943 *new_tile = NULL;
944 if (new_reg->mem_type != TTM_PL_VRAM)
945 return 0;
946
947 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
948 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
949 nvbo->mode, nvbo->zeta);
950 }
951
952 return 0;
953}
954
955static void
956nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
957 struct nouveau_drm_tile *new_tile,
958 struct nouveau_drm_tile **old_tile)
959{
960 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
961 struct drm_device *dev = drm->dev;
962 struct dma_fence *fence = dma_resv_excl_fence(bo->base.resv);
963
964 nv10_bo_put_tile_region(dev, *old_tile, fence);
965 *old_tile = new_tile;
966}
967
968static int
969nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
970 struct ttm_operation_ctx *ctx,
971 struct ttm_resource *new_reg,
972 struct ttm_place *hop)
973{
974 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
975 struct nouveau_bo *nvbo = nouveau_bo(bo);
976 struct ttm_resource *old_reg = bo->resource;
977 struct nouveau_drm_tile *new_tile = NULL;
978 int ret = 0;
979
980
981 if (new_reg->mem_type == TTM_PL_TT) {
982 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
983 if (ret)
984 return ret;
985 }
986
987 nouveau_bo_move_ntfy(bo, new_reg);
988 ret = ttm_bo_wait_ctx(bo, ctx);
989 if (ret)
990 goto out_ntfy;
991
992 if (nvbo->bo.pin_count)
993 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
994
995 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
996 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
997 if (ret)
998 goto out_ntfy;
999 }
1000
1001 /* Fake bo copy. */
1002 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1003 ttm_bo_move_null(bo, new_reg);
1004 goto out;
1005 }
1006
1007 if (old_reg->mem_type == TTM_PL_SYSTEM &&
1008 new_reg->mem_type == TTM_PL_TT) {
1009 ttm_bo_move_null(bo, new_reg);
1010 goto out;
1011 }
1012
1013 if (old_reg->mem_type == TTM_PL_TT &&
1014 new_reg->mem_type == TTM_PL_SYSTEM) {
1015 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1016 ttm_resource_free(bo, &bo->resource);
1017 ttm_bo_assign_mem(bo, new_reg);
1018 goto out;
1019 }
1020
1021 /* Hardware assisted copy. */
1022 if (drm->ttm.move) {
1023 if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1024 new_reg->mem_type == TTM_PL_VRAM) ||
1025 (old_reg->mem_type == TTM_PL_VRAM &&
1026 new_reg->mem_type == TTM_PL_SYSTEM)) {
1027 hop->fpfn = 0;
1028 hop->lpfn = 0;
1029 hop->mem_type = TTM_PL_TT;
1030 hop->flags = 0;
1031 return -EMULTIHOP;
1032 }
1033 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1034 new_reg);
1035 } else
1036 ret = -ENODEV;
1037
1038 if (ret) {
1039 /* Fallback to software copy. */
1040 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1041 }
1042
1043out:
1044 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1045 if (ret)
1046 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1047 else
1048 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1049 }
1050out_ntfy:
1051 if (ret) {
1052 nouveau_bo_move_ntfy(bo, bo->resource);
1053 }
1054 return ret;
1055}
1056
1057static void
1058nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1059 struct ttm_resource *reg)
1060{
1061 struct nouveau_mem *mem = nouveau_mem(reg);
1062
1063 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1064 switch (reg->mem_type) {
1065 case TTM_PL_TT:
1066 if (mem->kind)
1067 nvif_object_unmap_handle(&mem->mem.object);
1068 break;
1069 case TTM_PL_VRAM:
1070 nvif_object_unmap_handle(&mem->mem.object);
1071 break;
1072 default:
1073 break;
1074 }
1075 }
1076}
1077
1078static int
1079nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1080{
1081 struct nouveau_drm *drm = nouveau_bdev(bdev);
1082 struct nvkm_device *device = nvxx_device(&drm->client.device);
1083 struct nouveau_mem *mem = nouveau_mem(reg);
1084 struct nvif_mmu *mmu = &drm->client.mmu;
1085 int ret;
1086
1087 mutex_lock(&drm->ttm.io_reserve_mutex);
1088retry:
1089 switch (reg->mem_type) {
1090 case TTM_PL_SYSTEM:
1091 /* System memory */
1092 ret = 0;
1093 goto out;
1094 case TTM_PL_TT:
1095#if IS_ENABLED(CONFIG_AGP)
1096 if (drm->agp.bridge) {
1097 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1098 drm->agp.base;
1099 reg->bus.is_iomem = !drm->agp.cma;
1100 reg->bus.caching = ttm_write_combined;
1101 }
1102#endif
1103 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1104 !mem->kind) {
1105 /* untiled */
1106 ret = 0;
1107 break;
1108 }
1109 fallthrough; /* tiled memory */
1110 case TTM_PL_VRAM:
1111 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1112 device->func->resource_addr(device, 1);
1113 reg->bus.is_iomem = true;
1114
1115 /* Some BARs do not support being ioremapped WC */
1116 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1117 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1118 reg->bus.caching = ttm_uncached;
1119 else
1120 reg->bus.caching = ttm_write_combined;
1121
1122 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1123 union {
1124 struct nv50_mem_map_v0 nv50;
1125 struct gf100_mem_map_v0 gf100;
1126 } args;
1127 u64 handle, length;
1128 u32 argc = 0;
1129
1130 switch (mem->mem.object.oclass) {
1131 case NVIF_CLASS_MEM_NV50:
1132 args.nv50.version = 0;
1133 args.nv50.ro = 0;
1134 args.nv50.kind = mem->kind;
1135 args.nv50.comp = mem->comp;
1136 argc = sizeof(args.nv50);
1137 break;
1138 case NVIF_CLASS_MEM_GF100:
1139 args.gf100.version = 0;
1140 args.gf100.ro = 0;
1141 args.gf100.kind = mem->kind;
1142 argc = sizeof(args.gf100);
1143 break;
1144 default:
1145 WARN_ON(1);
1146 break;
1147 }
1148
1149 ret = nvif_object_map_handle(&mem->mem.object,
1150 &args, argc,
1151 &handle, &length);
1152 if (ret != 1) {
1153 if (WARN_ON(ret == 0))
1154 ret = -EINVAL;
1155 goto out;
1156 }
1157
1158 reg->bus.offset = handle;
1159 }
1160 ret = 0;
1161 break;
1162 default:
1163 ret = -EINVAL;
1164 }
1165
1166out:
1167 if (ret == -ENOSPC) {
1168 struct nouveau_bo *nvbo;
1169
1170 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1171 typeof(*nvbo),
1172 io_reserve_lru);
1173 if (nvbo) {
1174 list_del_init(&nvbo->io_reserve_lru);
1175 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1176 bdev->dev_mapping);
1177 nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource);
1178 goto retry;
1179 }
1180
1181 }
1182 mutex_unlock(&drm->ttm.io_reserve_mutex);
1183 return ret;
1184}
1185
1186static void
1187nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1188{
1189 struct nouveau_drm *drm = nouveau_bdev(bdev);
1190
1191 mutex_lock(&drm->ttm.io_reserve_mutex);
1192 nouveau_ttm_io_mem_free_locked(drm, reg);
1193 mutex_unlock(&drm->ttm.io_reserve_mutex);
1194}
1195
1196vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1197{
1198 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1199 struct nouveau_bo *nvbo = nouveau_bo(bo);
1200 struct nvkm_device *device = nvxx_device(&drm->client.device);
1201 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1202 int i, ret;
1203
1204 /* as long as the bo isn't in vram, and isn't tiled, we've got
1205 * nothing to do here.
1206 */
1207 if (bo->resource->mem_type != TTM_PL_VRAM) {
1208 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1209 !nvbo->kind)
1210 return 0;
1211
1212 if (bo->resource->mem_type != TTM_PL_SYSTEM)
1213 return 0;
1214
1215 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1216
1217 } else {
1218 /* make sure bo is in mappable vram */
1219 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1220 bo->resource->start + bo->resource->num_pages < mappable)
1221 return 0;
1222
1223 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1224 nvbo->placements[i].fpfn = 0;
1225 nvbo->placements[i].lpfn = mappable;
1226 }
1227
1228 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1229 nvbo->busy_placements[i].fpfn = 0;
1230 nvbo->busy_placements[i].lpfn = mappable;
1231 }
1232
1233 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1234 }
1235
1236 ret = nouveau_bo_validate(nvbo, false, false);
1237 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1238 return VM_FAULT_NOPAGE;
1239 else if (unlikely(ret))
1240 return VM_FAULT_SIGBUS;
1241
1242 ttm_bo_move_to_lru_tail_unlocked(bo);
1243 return 0;
1244}
1245
1246static int
1247nouveau_ttm_tt_populate(struct ttm_device *bdev,
1248 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1249{
1250 struct ttm_tt *ttm_dma = (void *)ttm;
1251 struct nouveau_drm *drm;
1252 struct device *dev;
1253 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1254
1255 if (ttm_tt_is_populated(ttm))
1256 return 0;
1257
1258 if (slave && ttm->sg) {
1259 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1260 ttm->num_pages);
1261 return 0;
1262 }
1263
1264 drm = nouveau_bdev(bdev);
1265 dev = drm->dev->dev;
1266
1267 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1268}
1269
1270static void
1271nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1272 struct ttm_tt *ttm)
1273{
1274 struct nouveau_drm *drm;
1275 struct device *dev;
1276 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1277
1278 if (slave)
1279 return;
1280
1281 drm = nouveau_bdev(bdev);
1282 dev = drm->dev->dev;
1283
1284 return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1285}
1286
1287static void
1288nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1289 struct ttm_tt *ttm)
1290{
1291#if IS_ENABLED(CONFIG_AGP)
1292 struct nouveau_drm *drm = nouveau_bdev(bdev);
1293 if (drm->agp.bridge) {
1294 ttm_agp_unbind(ttm);
1295 ttm_tt_destroy_common(bdev, ttm);
1296 ttm_agp_destroy(ttm);
1297 return;
1298 }
1299#endif
1300 nouveau_sgdma_destroy(bdev, ttm);
1301}
1302
1303void
1304nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1305{
1306 struct dma_resv *resv = nvbo->bo.base.resv;
1307
1308 if (exclusive)
1309 dma_resv_add_excl_fence(resv, &fence->base);
1310 else if (fence)
1311 dma_resv_add_shared_fence(resv, &fence->base);
1312}
1313
1314static void
1315nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1316{
1317 nouveau_bo_move_ntfy(bo, NULL);
1318}
1319
1320struct ttm_device_funcs nouveau_bo_driver = {
1321 .ttm_tt_create = &nouveau_ttm_tt_create,
1322 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1323 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1324 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1325 .eviction_valuable = ttm_bo_eviction_valuable,
1326 .evict_flags = nouveau_bo_evict_flags,
1327 .delete_mem_notify = nouveau_bo_delete_mem_notify,
1328 .move = nouveau_bo_move,
1329 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1330 .io_mem_free = &nouveau_ttm_io_mem_free,
1331};