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1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include "drmP.h"
31
32#include "nouveau_drm.h"
33#include "nouveau_drv.h"
34#include "nouveau_dma.h"
35#include "nouveau_mm.h"
36#include "nouveau_vm.h"
37
38#include <linux/log2.h>
39#include <linux/slab.h>
40
41static void
42nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
43{
44 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
45 struct drm_device *dev = dev_priv->dev;
46 struct nouveau_bo *nvbo = nouveau_bo(bo);
47
48 if (unlikely(nvbo->gem))
49 DRM_ERROR("bo %p still attached to GEM object\n", bo);
50
51 nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
52 kfree(nvbo);
53}
54
55static void
56nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
57 int *align, int *size)
58{
59 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
60
61 if (dev_priv->card_type < NV_50) {
62 if (nvbo->tile_mode) {
63 if (dev_priv->chipset >= 0x40) {
64 *align = 65536;
65 *size = roundup(*size, 64 * nvbo->tile_mode);
66
67 } else if (dev_priv->chipset >= 0x30) {
68 *align = 32768;
69 *size = roundup(*size, 64 * nvbo->tile_mode);
70
71 } else if (dev_priv->chipset >= 0x20) {
72 *align = 16384;
73 *size = roundup(*size, 64 * nvbo->tile_mode);
74
75 } else if (dev_priv->chipset >= 0x10) {
76 *align = 16384;
77 *size = roundup(*size, 32 * nvbo->tile_mode);
78 }
79 }
80 } else {
81 *size = roundup(*size, (1 << nvbo->page_shift));
82 *align = max((1 << nvbo->page_shift), *align);
83 }
84
85 *size = roundup(*size, PAGE_SIZE);
86}
87
88int
89nouveau_bo_new(struct drm_device *dev, int size, int align,
90 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
91 struct nouveau_bo **pnvbo)
92{
93 struct drm_nouveau_private *dev_priv = dev->dev_private;
94 struct nouveau_bo *nvbo;
95 int ret;
96
97 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
98 if (!nvbo)
99 return -ENOMEM;
100 INIT_LIST_HEAD(&nvbo->head);
101 INIT_LIST_HEAD(&nvbo->entry);
102 INIT_LIST_HEAD(&nvbo->vma_list);
103 nvbo->tile_mode = tile_mode;
104 nvbo->tile_flags = tile_flags;
105 nvbo->bo.bdev = &dev_priv->ttm.bdev;
106
107 nvbo->page_shift = 12;
108 if (dev_priv->bar1_vm) {
109 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
110 nvbo->page_shift = dev_priv->bar1_vm->lpg_shift;
111 }
112
113 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
114 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
115 nouveau_bo_placement_set(nvbo, flags, 0);
116
117 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
118 ttm_bo_type_device, &nvbo->placement,
119 align >> PAGE_SHIFT, 0, false, NULL, size,
120 nouveau_bo_del_ttm);
121 if (ret) {
122 /* ttm will call nouveau_bo_del_ttm if it fails.. */
123 return ret;
124 }
125
126 *pnvbo = nvbo;
127 return 0;
128}
129
130static void
131set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
132{
133 *n = 0;
134
135 if (type & TTM_PL_FLAG_VRAM)
136 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
137 if (type & TTM_PL_FLAG_TT)
138 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
139 if (type & TTM_PL_FLAG_SYSTEM)
140 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
141}
142
143static void
144set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
145{
146 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
147 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
148
149 if (dev_priv->card_type == NV_10 &&
150 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
151 nvbo->bo.mem.num_pages < vram_pages / 2) {
152 /*
153 * Make sure that the color and depth buffers are handled
154 * by independent memory controller units. Up to a 9x
155 * speed up when alpha-blending and depth-test are enabled
156 * at the same time.
157 */
158 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
159 nvbo->placement.fpfn = vram_pages / 2;
160 nvbo->placement.lpfn = ~0;
161 } else {
162 nvbo->placement.fpfn = 0;
163 nvbo->placement.lpfn = vram_pages / 2;
164 }
165 }
166}
167
168void
169nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
170{
171 struct ttm_placement *pl = &nvbo->placement;
172 uint32_t flags = TTM_PL_MASK_CACHING |
173 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
174
175 pl->placement = nvbo->placements;
176 set_placement_list(nvbo->placements, &pl->num_placement,
177 type, flags);
178
179 pl->busy_placement = nvbo->busy_placements;
180 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
181 type | busy, flags);
182
183 set_placement_range(nvbo, type);
184}
185
186int
187nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
188{
189 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
190 struct ttm_buffer_object *bo = &nvbo->bo;
191 int ret;
192
193 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
194 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
195 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
196 1 << bo->mem.mem_type, memtype);
197 return -EINVAL;
198 }
199
200 if (nvbo->pin_refcnt++)
201 return 0;
202
203 ret = ttm_bo_reserve(bo, false, false, false, 0);
204 if (ret)
205 goto out;
206
207 nouveau_bo_placement_set(nvbo, memtype, 0);
208
209 ret = nouveau_bo_validate(nvbo, false, false, false);
210 if (ret == 0) {
211 switch (bo->mem.mem_type) {
212 case TTM_PL_VRAM:
213 dev_priv->fb_aper_free -= bo->mem.size;
214 break;
215 case TTM_PL_TT:
216 dev_priv->gart_info.aper_free -= bo->mem.size;
217 break;
218 default:
219 break;
220 }
221 }
222 ttm_bo_unreserve(bo);
223out:
224 if (unlikely(ret))
225 nvbo->pin_refcnt--;
226 return ret;
227}
228
229int
230nouveau_bo_unpin(struct nouveau_bo *nvbo)
231{
232 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
233 struct ttm_buffer_object *bo = &nvbo->bo;
234 int ret;
235
236 if (--nvbo->pin_refcnt)
237 return 0;
238
239 ret = ttm_bo_reserve(bo, false, false, false, 0);
240 if (ret)
241 return ret;
242
243 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
244
245 ret = nouveau_bo_validate(nvbo, false, false, false);
246 if (ret == 0) {
247 switch (bo->mem.mem_type) {
248 case TTM_PL_VRAM:
249 dev_priv->fb_aper_free += bo->mem.size;
250 break;
251 case TTM_PL_TT:
252 dev_priv->gart_info.aper_free += bo->mem.size;
253 break;
254 default:
255 break;
256 }
257 }
258
259 ttm_bo_unreserve(bo);
260 return ret;
261}
262
263int
264nouveau_bo_map(struct nouveau_bo *nvbo)
265{
266 int ret;
267
268 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
269 if (ret)
270 return ret;
271
272 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
273 ttm_bo_unreserve(&nvbo->bo);
274 return ret;
275}
276
277void
278nouveau_bo_unmap(struct nouveau_bo *nvbo)
279{
280 if (nvbo)
281 ttm_bo_kunmap(&nvbo->kmap);
282}
283
284int
285nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
286 bool no_wait_reserve, bool no_wait_gpu)
287{
288 int ret;
289
290 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
291 no_wait_reserve, no_wait_gpu);
292 if (ret)
293 return ret;
294
295 return 0;
296}
297
298u16
299nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
300{
301 bool is_iomem;
302 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
303 mem = &mem[index];
304 if (is_iomem)
305 return ioread16_native((void __force __iomem *)mem);
306 else
307 return *mem;
308}
309
310void
311nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
312{
313 bool is_iomem;
314 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
315 mem = &mem[index];
316 if (is_iomem)
317 iowrite16_native(val, (void __force __iomem *)mem);
318 else
319 *mem = val;
320}
321
322u32
323nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
324{
325 bool is_iomem;
326 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
327 mem = &mem[index];
328 if (is_iomem)
329 return ioread32_native((void __force __iomem *)mem);
330 else
331 return *mem;
332}
333
334void
335nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
336{
337 bool is_iomem;
338 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
339 mem = &mem[index];
340 if (is_iomem)
341 iowrite32_native(val, (void __force __iomem *)mem);
342 else
343 *mem = val;
344}
345
346static struct ttm_backend *
347nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
348{
349 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
350 struct drm_device *dev = dev_priv->dev;
351
352 switch (dev_priv->gart_info.type) {
353#if __OS_HAS_AGP
354 case NOUVEAU_GART_AGP:
355 return ttm_agp_backend_init(bdev, dev->agp->bridge);
356#endif
357 case NOUVEAU_GART_PDMA:
358 case NOUVEAU_GART_HW:
359 return nouveau_sgdma_init_ttm(dev);
360 default:
361 NV_ERROR(dev, "Unknown GART type %d\n",
362 dev_priv->gart_info.type);
363 break;
364 }
365
366 return NULL;
367}
368
369static int
370nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
371{
372 /* We'll do this from user space. */
373 return 0;
374}
375
376static int
377nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
378 struct ttm_mem_type_manager *man)
379{
380 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
381 struct drm_device *dev = dev_priv->dev;
382
383 switch (type) {
384 case TTM_PL_SYSTEM:
385 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
386 man->available_caching = TTM_PL_MASK_CACHING;
387 man->default_caching = TTM_PL_FLAG_CACHED;
388 break;
389 case TTM_PL_VRAM:
390 if (dev_priv->card_type >= NV_50) {
391 man->func = &nouveau_vram_manager;
392 man->io_reserve_fastpath = false;
393 man->use_io_reserve_lru = true;
394 } else {
395 man->func = &ttm_bo_manager_func;
396 }
397 man->flags = TTM_MEMTYPE_FLAG_FIXED |
398 TTM_MEMTYPE_FLAG_MAPPABLE;
399 man->available_caching = TTM_PL_FLAG_UNCACHED |
400 TTM_PL_FLAG_WC;
401 man->default_caching = TTM_PL_FLAG_WC;
402 break;
403 case TTM_PL_TT:
404 if (dev_priv->card_type >= NV_50)
405 man->func = &nouveau_gart_manager;
406 else
407 man->func = &ttm_bo_manager_func;
408 switch (dev_priv->gart_info.type) {
409 case NOUVEAU_GART_AGP:
410 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
411 man->available_caching = TTM_PL_FLAG_UNCACHED |
412 TTM_PL_FLAG_WC;
413 man->default_caching = TTM_PL_FLAG_WC;
414 break;
415 case NOUVEAU_GART_PDMA:
416 case NOUVEAU_GART_HW:
417 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
418 TTM_MEMTYPE_FLAG_CMA;
419 man->available_caching = TTM_PL_MASK_CACHING;
420 man->default_caching = TTM_PL_FLAG_CACHED;
421 break;
422 default:
423 NV_ERROR(dev, "Unknown GART type: %d\n",
424 dev_priv->gart_info.type);
425 return -EINVAL;
426 }
427 break;
428 default:
429 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
430 return -EINVAL;
431 }
432 return 0;
433}
434
435static void
436nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
437{
438 struct nouveau_bo *nvbo = nouveau_bo(bo);
439
440 switch (bo->mem.mem_type) {
441 case TTM_PL_VRAM:
442 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
443 TTM_PL_FLAG_SYSTEM);
444 break;
445 default:
446 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
447 break;
448 }
449
450 *pl = nvbo->placement;
451}
452
453
454/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
455 * TTM_PL_{VRAM,TT} directly.
456 */
457
458static int
459nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
460 struct nouveau_bo *nvbo, bool evict,
461 bool no_wait_reserve, bool no_wait_gpu,
462 struct ttm_mem_reg *new_mem)
463{
464 struct nouveau_fence *fence = NULL;
465 int ret;
466
467 ret = nouveau_fence_new(chan, &fence, true);
468 if (ret)
469 return ret;
470
471 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
472 no_wait_reserve, no_wait_gpu, new_mem);
473 nouveau_fence_unref(&fence);
474 return ret;
475}
476
477static int
478nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
479 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
480{
481 struct nouveau_mem *node = old_mem->mm_node;
482 u64 src_offset = node->vma[0].offset;
483 u64 dst_offset = node->vma[1].offset;
484 u32 page_count = new_mem->num_pages;
485 int ret;
486
487 page_count = new_mem->num_pages;
488 while (page_count) {
489 int line_count = (page_count > 2047) ? 2047 : page_count;
490
491 ret = RING_SPACE(chan, 12);
492 if (ret)
493 return ret;
494
495 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0238, 2);
496 OUT_RING (chan, upper_32_bits(dst_offset));
497 OUT_RING (chan, lower_32_bits(dst_offset));
498 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x030c, 6);
499 OUT_RING (chan, upper_32_bits(src_offset));
500 OUT_RING (chan, lower_32_bits(src_offset));
501 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
502 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
503 OUT_RING (chan, PAGE_SIZE); /* line_length */
504 OUT_RING (chan, line_count);
505 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0300, 1);
506 OUT_RING (chan, 0x00100110);
507
508 page_count -= line_count;
509 src_offset += (PAGE_SIZE * line_count);
510 dst_offset += (PAGE_SIZE * line_count);
511 }
512
513 return 0;
514}
515
516static int
517nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
518 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
519{
520 struct nouveau_mem *node = old_mem->mm_node;
521 struct nouveau_bo *nvbo = nouveau_bo(bo);
522 u64 length = (new_mem->num_pages << PAGE_SHIFT);
523 u64 src_offset = node->vma[0].offset;
524 u64 dst_offset = node->vma[1].offset;
525 int ret;
526
527 while (length) {
528 u32 amount, stride, height;
529
530 amount = min(length, (u64)(4 * 1024 * 1024));
531 stride = 16 * 4;
532 height = amount / stride;
533
534 if (new_mem->mem_type == TTM_PL_VRAM &&
535 nouveau_bo_tile_layout(nvbo)) {
536 ret = RING_SPACE(chan, 8);
537 if (ret)
538 return ret;
539
540 BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
541 OUT_RING (chan, 0);
542 OUT_RING (chan, 0);
543 OUT_RING (chan, stride);
544 OUT_RING (chan, height);
545 OUT_RING (chan, 1);
546 OUT_RING (chan, 0);
547 OUT_RING (chan, 0);
548 } else {
549 ret = RING_SPACE(chan, 2);
550 if (ret)
551 return ret;
552
553 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
554 OUT_RING (chan, 1);
555 }
556 if (old_mem->mem_type == TTM_PL_VRAM &&
557 nouveau_bo_tile_layout(nvbo)) {
558 ret = RING_SPACE(chan, 8);
559 if (ret)
560 return ret;
561
562 BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
563 OUT_RING (chan, 0);
564 OUT_RING (chan, 0);
565 OUT_RING (chan, stride);
566 OUT_RING (chan, height);
567 OUT_RING (chan, 1);
568 OUT_RING (chan, 0);
569 OUT_RING (chan, 0);
570 } else {
571 ret = RING_SPACE(chan, 2);
572 if (ret)
573 return ret;
574
575 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
576 OUT_RING (chan, 1);
577 }
578
579 ret = RING_SPACE(chan, 14);
580 if (ret)
581 return ret;
582
583 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
584 OUT_RING (chan, upper_32_bits(src_offset));
585 OUT_RING (chan, upper_32_bits(dst_offset));
586 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
587 OUT_RING (chan, lower_32_bits(src_offset));
588 OUT_RING (chan, lower_32_bits(dst_offset));
589 OUT_RING (chan, stride);
590 OUT_RING (chan, stride);
591 OUT_RING (chan, stride);
592 OUT_RING (chan, height);
593 OUT_RING (chan, 0x00000101);
594 OUT_RING (chan, 0x00000000);
595 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
596 OUT_RING (chan, 0);
597
598 length -= amount;
599 src_offset += amount;
600 dst_offset += amount;
601 }
602
603 return 0;
604}
605
606static inline uint32_t
607nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
608 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
609{
610 if (mem->mem_type == TTM_PL_TT)
611 return chan->gart_handle;
612 return chan->vram_handle;
613}
614
615static int
616nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
617 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
618{
619 u32 src_offset = old_mem->start << PAGE_SHIFT;
620 u32 dst_offset = new_mem->start << PAGE_SHIFT;
621 u32 page_count = new_mem->num_pages;
622 int ret;
623
624 ret = RING_SPACE(chan, 3);
625 if (ret)
626 return ret;
627
628 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
629 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
630 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
631
632 page_count = new_mem->num_pages;
633 while (page_count) {
634 int line_count = (page_count > 2047) ? 2047 : page_count;
635
636 ret = RING_SPACE(chan, 11);
637 if (ret)
638 return ret;
639
640 BEGIN_RING(chan, NvSubM2MF,
641 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
642 OUT_RING (chan, src_offset);
643 OUT_RING (chan, dst_offset);
644 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
645 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
646 OUT_RING (chan, PAGE_SIZE); /* line_length */
647 OUT_RING (chan, line_count);
648 OUT_RING (chan, 0x00000101);
649 OUT_RING (chan, 0x00000000);
650 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
651 OUT_RING (chan, 0);
652
653 page_count -= line_count;
654 src_offset += (PAGE_SIZE * line_count);
655 dst_offset += (PAGE_SIZE * line_count);
656 }
657
658 return 0;
659}
660
661static int
662nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
663 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
664{
665 struct nouveau_mem *node = mem->mm_node;
666 int ret;
667
668 ret = nouveau_vm_get(chan->vm, mem->num_pages << PAGE_SHIFT,
669 node->page_shift, NV_MEM_ACCESS_RO, vma);
670 if (ret)
671 return ret;
672
673 if (mem->mem_type == TTM_PL_VRAM)
674 nouveau_vm_map(vma, node);
675 else
676 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT,
677 node, node->pages);
678
679 return 0;
680}
681
682static int
683nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
684 bool no_wait_reserve, bool no_wait_gpu,
685 struct ttm_mem_reg *new_mem)
686{
687 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
688 struct nouveau_bo *nvbo = nouveau_bo(bo);
689 struct ttm_mem_reg *old_mem = &bo->mem;
690 struct nouveau_channel *chan;
691 int ret;
692
693 chan = nvbo->channel;
694 if (!chan) {
695 chan = dev_priv->channel;
696 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
697 }
698
699 /* create temporary vmas for the transfer and attach them to the
700 * old nouveau_mem node, these will get cleaned up after ttm has
701 * destroyed the ttm_mem_reg
702 */
703 if (dev_priv->card_type >= NV_50) {
704 struct nouveau_mem *node = old_mem->mm_node;
705
706 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
707 if (ret)
708 goto out;
709
710 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
711 if (ret)
712 goto out;
713 }
714
715 if (dev_priv->card_type < NV_50)
716 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
717 else
718 if (dev_priv->card_type < NV_C0)
719 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
720 else
721 ret = nvc0_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
722 if (ret == 0) {
723 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
724 no_wait_reserve,
725 no_wait_gpu, new_mem);
726 }
727
728out:
729 if (chan == dev_priv->channel)
730 mutex_unlock(&chan->mutex);
731 return ret;
732}
733
734static int
735nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
736 bool no_wait_reserve, bool no_wait_gpu,
737 struct ttm_mem_reg *new_mem)
738{
739 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
740 struct ttm_placement placement;
741 struct ttm_mem_reg tmp_mem;
742 int ret;
743
744 placement.fpfn = placement.lpfn = 0;
745 placement.num_placement = placement.num_busy_placement = 1;
746 placement.placement = placement.busy_placement = &placement_memtype;
747
748 tmp_mem = *new_mem;
749 tmp_mem.mm_node = NULL;
750 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
751 if (ret)
752 return ret;
753
754 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
755 if (ret)
756 goto out;
757
758 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
759 if (ret)
760 goto out;
761
762 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
763out:
764 ttm_bo_mem_put(bo, &tmp_mem);
765 return ret;
766}
767
768static int
769nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
770 bool no_wait_reserve, bool no_wait_gpu,
771 struct ttm_mem_reg *new_mem)
772{
773 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
774 struct ttm_placement placement;
775 struct ttm_mem_reg tmp_mem;
776 int ret;
777
778 placement.fpfn = placement.lpfn = 0;
779 placement.num_placement = placement.num_busy_placement = 1;
780 placement.placement = placement.busy_placement = &placement_memtype;
781
782 tmp_mem = *new_mem;
783 tmp_mem.mm_node = NULL;
784 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
785 if (ret)
786 return ret;
787
788 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
789 if (ret)
790 goto out;
791
792 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
793 if (ret)
794 goto out;
795
796out:
797 ttm_bo_mem_put(bo, &tmp_mem);
798 return ret;
799}
800
801static void
802nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
803{
804 struct nouveau_mem *node = new_mem->mm_node;
805 struct nouveau_bo *nvbo = nouveau_bo(bo);
806 struct nouveau_vma *vma;
807
808 list_for_each_entry(vma, &nvbo->vma_list, head) {
809 if (new_mem->mem_type == TTM_PL_VRAM) {
810 nouveau_vm_map(vma, new_mem->mm_node);
811 } else
812 if (new_mem->mem_type == TTM_PL_TT &&
813 nvbo->page_shift == vma->vm->spg_shift) {
814 nouveau_vm_map_sg(vma, 0, new_mem->
815 num_pages << PAGE_SHIFT,
816 node, node->pages);
817 } else {
818 nouveau_vm_unmap(vma);
819 }
820 }
821}
822
823static int
824nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
825 struct nouveau_tile_reg **new_tile)
826{
827 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
828 struct drm_device *dev = dev_priv->dev;
829 struct nouveau_bo *nvbo = nouveau_bo(bo);
830 u64 offset = new_mem->start << PAGE_SHIFT;
831
832 *new_tile = NULL;
833 if (new_mem->mem_type != TTM_PL_VRAM)
834 return 0;
835
836 if (dev_priv->card_type >= NV_10) {
837 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
838 nvbo->tile_mode,
839 nvbo->tile_flags);
840 }
841
842 return 0;
843}
844
845static void
846nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
847 struct nouveau_tile_reg *new_tile,
848 struct nouveau_tile_reg **old_tile)
849{
850 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
851 struct drm_device *dev = dev_priv->dev;
852
853 nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
854 *old_tile = new_tile;
855}
856
857static int
858nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
859 bool no_wait_reserve, bool no_wait_gpu,
860 struct ttm_mem_reg *new_mem)
861{
862 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
863 struct nouveau_bo *nvbo = nouveau_bo(bo);
864 struct ttm_mem_reg *old_mem = &bo->mem;
865 struct nouveau_tile_reg *new_tile = NULL;
866 int ret = 0;
867
868 if (dev_priv->card_type < NV_50) {
869 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
870 if (ret)
871 return ret;
872 }
873
874 /* Fake bo copy. */
875 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
876 BUG_ON(bo->mem.mm_node != NULL);
877 bo->mem = *new_mem;
878 new_mem->mm_node = NULL;
879 goto out;
880 }
881
882 /* Software copy if the card isn't up and running yet. */
883 if (!dev_priv->channel) {
884 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
885 goto out;
886 }
887
888 /* Hardware assisted copy. */
889 if (new_mem->mem_type == TTM_PL_SYSTEM)
890 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
891 else if (old_mem->mem_type == TTM_PL_SYSTEM)
892 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
893 else
894 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
895
896 if (!ret)
897 goto out;
898
899 /* Fallback to software copy. */
900 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
901
902out:
903 if (dev_priv->card_type < NV_50) {
904 if (ret)
905 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
906 else
907 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
908 }
909
910 return ret;
911}
912
913static int
914nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
915{
916 return 0;
917}
918
919static int
920nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
921{
922 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
923 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
924 struct drm_device *dev = dev_priv->dev;
925 int ret;
926
927 mem->bus.addr = NULL;
928 mem->bus.offset = 0;
929 mem->bus.size = mem->num_pages << PAGE_SHIFT;
930 mem->bus.base = 0;
931 mem->bus.is_iomem = false;
932 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
933 return -EINVAL;
934 switch (mem->mem_type) {
935 case TTM_PL_SYSTEM:
936 /* System memory */
937 return 0;
938 case TTM_PL_TT:
939#if __OS_HAS_AGP
940 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
941 mem->bus.offset = mem->start << PAGE_SHIFT;
942 mem->bus.base = dev_priv->gart_info.aper_base;
943 mem->bus.is_iomem = true;
944 }
945#endif
946 break;
947 case TTM_PL_VRAM:
948 {
949 struct nouveau_mem *node = mem->mm_node;
950 u8 page_shift;
951
952 if (!dev_priv->bar1_vm) {
953 mem->bus.offset = mem->start << PAGE_SHIFT;
954 mem->bus.base = pci_resource_start(dev->pdev, 1);
955 mem->bus.is_iomem = true;
956 break;
957 }
958
959 if (dev_priv->card_type == NV_C0)
960 page_shift = node->page_shift;
961 else
962 page_shift = 12;
963
964 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
965 page_shift, NV_MEM_ACCESS_RW,
966 &node->bar_vma);
967 if (ret)
968 return ret;
969
970 nouveau_vm_map(&node->bar_vma, node);
971 if (ret) {
972 nouveau_vm_put(&node->bar_vma);
973 return ret;
974 }
975
976 mem->bus.offset = node->bar_vma.offset;
977 if (dev_priv->card_type == NV_50) /*XXX*/
978 mem->bus.offset -= 0x0020000000ULL;
979 mem->bus.base = pci_resource_start(dev->pdev, 1);
980 mem->bus.is_iomem = true;
981 }
982 break;
983 default:
984 return -EINVAL;
985 }
986 return 0;
987}
988
989static void
990nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
991{
992 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
993 struct nouveau_mem *node = mem->mm_node;
994
995 if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
996 return;
997
998 if (!node->bar_vma.node)
999 return;
1000
1001 nouveau_vm_unmap(&node->bar_vma);
1002 nouveau_vm_put(&node->bar_vma);
1003}
1004
1005static int
1006nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1007{
1008 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1009 struct nouveau_bo *nvbo = nouveau_bo(bo);
1010
1011 /* as long as the bo isn't in vram, and isn't tiled, we've got
1012 * nothing to do here.
1013 */
1014 if (bo->mem.mem_type != TTM_PL_VRAM) {
1015 if (dev_priv->card_type < NV_50 ||
1016 !nouveau_bo_tile_layout(nvbo))
1017 return 0;
1018 }
1019
1020 /* make sure bo is in mappable vram */
1021 if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
1022 return 0;
1023
1024
1025 nvbo->placement.fpfn = 0;
1026 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
1027 nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
1028 return nouveau_bo_validate(nvbo, false, true, false);
1029}
1030
1031void
1032nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1033{
1034 struct nouveau_fence *old_fence;
1035
1036 if (likely(fence))
1037 nouveau_fence_ref(fence);
1038
1039 spin_lock(&nvbo->bo.bdev->fence_lock);
1040 old_fence = nvbo->bo.sync_obj;
1041 nvbo->bo.sync_obj = fence;
1042 spin_unlock(&nvbo->bo.bdev->fence_lock);
1043
1044 nouveau_fence_unref(&old_fence);
1045}
1046
1047struct ttm_bo_driver nouveau_bo_driver = {
1048 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
1049 .invalidate_caches = nouveau_bo_invalidate_caches,
1050 .init_mem_type = nouveau_bo_init_mem_type,
1051 .evict_flags = nouveau_bo_evict_flags,
1052 .move_notify = nouveau_bo_move_ntfy,
1053 .move = nouveau_bo_move,
1054 .verify_access = nouveau_bo_verify_access,
1055 .sync_obj_signaled = __nouveau_fence_signalled,
1056 .sync_obj_wait = __nouveau_fence_wait,
1057 .sync_obj_flush = __nouveau_fence_flush,
1058 .sync_obj_unref = __nouveau_fence_unref,
1059 .sync_obj_ref = __nouveau_fence_ref,
1060 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1061 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1062 .io_mem_free = &nouveau_ttm_io_mem_free,
1063};
1064
1065struct nouveau_vma *
1066nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1067{
1068 struct nouveau_vma *vma;
1069 list_for_each_entry(vma, &nvbo->vma_list, head) {
1070 if (vma->vm == vm)
1071 return vma;
1072 }
1073
1074 return NULL;
1075}
1076
1077int
1078nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1079 struct nouveau_vma *vma)
1080{
1081 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1082 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1083 int ret;
1084
1085 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1086 NV_MEM_ACCESS_RW, vma);
1087 if (ret)
1088 return ret;
1089
1090 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1091 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1092 else
1093 if (nvbo->bo.mem.mem_type == TTM_PL_TT)
1094 nouveau_vm_map_sg(vma, 0, size, node, node->pages);
1095
1096 list_add_tail(&vma->head, &nvbo->vma_list);
1097 vma->refcount = 1;
1098 return 0;
1099}
1100
1101void
1102nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1103{
1104 if (vma->node) {
1105 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
1106 spin_lock(&nvbo->bo.bdev->fence_lock);
1107 ttm_bo_wait(&nvbo->bo, false, false, false);
1108 spin_unlock(&nvbo->bo.bdev->fence_lock);
1109 nouveau_vm_unmap(vma);
1110 }
1111
1112 nouveau_vm_put(vma);
1113 list_del(&vma->head);
1114 }
1115}
1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <core/engine.h>
31#include <linux/swiotlb.h>
32
33#include <subdev/fb.h>
34#include <subdev/vm.h>
35#include <subdev/bar.h>
36
37#include "nouveau_drm.h"
38#include "nouveau_dma.h"
39#include "nouveau_fence.h"
40
41#include "nouveau_bo.h"
42#include "nouveau_ttm.h"
43#include "nouveau_gem.h"
44
45/*
46 * NV10-NV40 tiling helpers
47 */
48
49static void
50nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
51 u32 addr, u32 size, u32 pitch, u32 flags)
52{
53 struct nouveau_drm *drm = nouveau_drm(dev);
54 int i = reg - drm->tile.reg;
55 struct nouveau_fb *pfb = nouveau_fb(drm->device);
56 struct nouveau_fb_tile *tile = &pfb->tile.region[i];
57 struct nouveau_engine *engine;
58
59 nouveau_fence_unref(®->fence);
60
61 if (tile->pitch)
62 pfb->tile.fini(pfb, i, tile);
63
64 if (pitch)
65 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
66
67 pfb->tile.prog(pfb, i, tile);
68
69 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
70 engine->tile_prog(engine, i);
71 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
72 engine->tile_prog(engine, i);
73}
74
75static struct nouveau_drm_tile *
76nv10_bo_get_tile_region(struct drm_device *dev, int i)
77{
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80
81 spin_lock(&drm->tile.lock);
82
83 if (!tile->used &&
84 (!tile->fence || nouveau_fence_done(tile->fence)))
85 tile->used = true;
86 else
87 tile = NULL;
88
89 spin_unlock(&drm->tile.lock);
90 return tile;
91}
92
93static void
94nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct nouveau_fence *fence)
96{
97 struct nouveau_drm *drm = nouveau_drm(dev);
98
99 if (tile) {
100 spin_lock(&drm->tile.lock);
101 tile->fence = nouveau_fence_ref(fence);
102 tile->used = false;
103 spin_unlock(&drm->tile.lock);
104 }
105}
106
107static struct nouveau_drm_tile *
108nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
109 u32 size, u32 pitch, u32 flags)
110{
111 struct nouveau_drm *drm = nouveau_drm(dev);
112 struct nouveau_fb *pfb = nouveau_fb(drm->device);
113 struct nouveau_drm_tile *tile, *found = NULL;
114 int i;
115
116 for (i = 0; i < pfb->tile.regions; i++) {
117 tile = nv10_bo_get_tile_region(dev, i);
118
119 if (pitch && !found) {
120 found = tile;
121 continue;
122
123 } else if (tile && pfb->tile.region[i].pitch) {
124 /* Kill an unused tile region. */
125 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
126 }
127
128 nv10_bo_put_tile_region(dev, tile, NULL);
129 }
130
131 if (found)
132 nv10_bo_update_tile_region(dev, found, addr, size,
133 pitch, flags);
134 return found;
135}
136
137static void
138nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
139{
140 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
141 struct drm_device *dev = drm->dev;
142 struct nouveau_bo *nvbo = nouveau_bo(bo);
143
144 if (unlikely(nvbo->gem.filp))
145 DRM_ERROR("bo %p still attached to GEM object\n", bo);
146 WARN_ON(nvbo->pin_refcnt > 0);
147 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
148 kfree(nvbo);
149}
150
151static void
152nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
153 int *align, int *size)
154{
155 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
156 struct nouveau_device *device = nv_device(drm->device);
157
158 if (device->card_type < NV_50) {
159 if (nvbo->tile_mode) {
160 if (device->chipset >= 0x40) {
161 *align = 65536;
162 *size = roundup(*size, 64 * nvbo->tile_mode);
163
164 } else if (device->chipset >= 0x30) {
165 *align = 32768;
166 *size = roundup(*size, 64 * nvbo->tile_mode);
167
168 } else if (device->chipset >= 0x20) {
169 *align = 16384;
170 *size = roundup(*size, 64 * nvbo->tile_mode);
171
172 } else if (device->chipset >= 0x10) {
173 *align = 16384;
174 *size = roundup(*size, 32 * nvbo->tile_mode);
175 }
176 }
177 } else {
178 *size = roundup(*size, (1 << nvbo->page_shift));
179 *align = max((1 << nvbo->page_shift), *align);
180 }
181
182 *size = roundup(*size, PAGE_SIZE);
183}
184
185int
186nouveau_bo_new(struct drm_device *dev, int size, int align,
187 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
188 struct sg_table *sg,
189 struct nouveau_bo **pnvbo)
190{
191 struct nouveau_drm *drm = nouveau_drm(dev);
192 struct nouveau_bo *nvbo;
193 size_t acc_size;
194 int ret;
195 int type = ttm_bo_type_device;
196 int lpg_shift = 12;
197 int max_size;
198
199 if (drm->client.base.vm)
200 lpg_shift = drm->client.base.vm->vmm->lpg_shift;
201 max_size = INT_MAX & ~((1 << lpg_shift) - 1);
202
203 if (size <= 0 || size > max_size) {
204 nv_warn(drm, "skipped size %x\n", (u32)size);
205 return -EINVAL;
206 }
207
208 if (sg)
209 type = ttm_bo_type_sg;
210
211 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
212 if (!nvbo)
213 return -ENOMEM;
214 INIT_LIST_HEAD(&nvbo->head);
215 INIT_LIST_HEAD(&nvbo->entry);
216 INIT_LIST_HEAD(&nvbo->vma_list);
217 nvbo->tile_mode = tile_mode;
218 nvbo->tile_flags = tile_flags;
219 nvbo->bo.bdev = &drm->ttm.bdev;
220
221 nvbo->page_shift = 12;
222 if (drm->client.base.vm) {
223 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
224 nvbo->page_shift = drm->client.base.vm->vmm->lpg_shift;
225 }
226
227 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
228 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
229 nouveau_bo_placement_set(nvbo, flags, 0);
230
231 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
232 sizeof(struct nouveau_bo));
233
234 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
235 type, &nvbo->placement,
236 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
237 nouveau_bo_del_ttm);
238 if (ret) {
239 /* ttm will call nouveau_bo_del_ttm if it fails.. */
240 return ret;
241 }
242
243 *pnvbo = nvbo;
244 return 0;
245}
246
247static void
248set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
249{
250 *n = 0;
251
252 if (type & TTM_PL_FLAG_VRAM)
253 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
254 if (type & TTM_PL_FLAG_TT)
255 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
256 if (type & TTM_PL_FLAG_SYSTEM)
257 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
258}
259
260static void
261set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
262{
263 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
264 struct nouveau_fb *pfb = nouveau_fb(drm->device);
265 u32 vram_pages = pfb->ram->size >> PAGE_SHIFT;
266
267 if ((nv_device(drm->device)->card_type == NV_10 ||
268 nv_device(drm->device)->card_type == NV_11) &&
269 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
270 nvbo->bo.mem.num_pages < vram_pages / 4) {
271 /*
272 * Make sure that the color and depth buffers are handled
273 * by independent memory controller units. Up to a 9x
274 * speed up when alpha-blending and depth-test are enabled
275 * at the same time.
276 */
277 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
278 nvbo->placement.fpfn = vram_pages / 2;
279 nvbo->placement.lpfn = ~0;
280 } else {
281 nvbo->placement.fpfn = 0;
282 nvbo->placement.lpfn = vram_pages / 2;
283 }
284 }
285}
286
287void
288nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
289{
290 struct ttm_placement *pl = &nvbo->placement;
291 uint32_t flags = TTM_PL_MASK_CACHING |
292 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
293
294 pl->placement = nvbo->placements;
295 set_placement_list(nvbo->placements, &pl->num_placement,
296 type, flags);
297
298 pl->busy_placement = nvbo->busy_placements;
299 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
300 type | busy, flags);
301
302 set_placement_range(nvbo, type);
303}
304
305int
306nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
307{
308 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
309 struct ttm_buffer_object *bo = &nvbo->bo;
310 int ret;
311
312 ret = ttm_bo_reserve(bo, false, false, false, 0);
313 if (ret)
314 goto out;
315
316 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
317 NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
318 1 << bo->mem.mem_type, memtype);
319 ret = -EINVAL;
320 goto out;
321 }
322
323 if (nvbo->pin_refcnt++)
324 goto out;
325
326 nouveau_bo_placement_set(nvbo, memtype, 0);
327
328 ret = nouveau_bo_validate(nvbo, false, false);
329 if (ret == 0) {
330 switch (bo->mem.mem_type) {
331 case TTM_PL_VRAM:
332 drm->gem.vram_available -= bo->mem.size;
333 break;
334 case TTM_PL_TT:
335 drm->gem.gart_available -= bo->mem.size;
336 break;
337 default:
338 break;
339 }
340 }
341out:
342 ttm_bo_unreserve(bo);
343 return ret;
344}
345
346int
347nouveau_bo_unpin(struct nouveau_bo *nvbo)
348{
349 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
350 struct ttm_buffer_object *bo = &nvbo->bo;
351 int ret, ref;
352
353 ret = ttm_bo_reserve(bo, false, false, false, 0);
354 if (ret)
355 return ret;
356
357 ref = --nvbo->pin_refcnt;
358 WARN_ON_ONCE(ref < 0);
359 if (ref)
360 goto out;
361
362 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
363
364 ret = nouveau_bo_validate(nvbo, false, false);
365 if (ret == 0) {
366 switch (bo->mem.mem_type) {
367 case TTM_PL_VRAM:
368 drm->gem.vram_available += bo->mem.size;
369 break;
370 case TTM_PL_TT:
371 drm->gem.gart_available += bo->mem.size;
372 break;
373 default:
374 break;
375 }
376 }
377
378out:
379 ttm_bo_unreserve(bo);
380 return ret;
381}
382
383int
384nouveau_bo_map(struct nouveau_bo *nvbo)
385{
386 int ret;
387
388 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
389 if (ret)
390 return ret;
391
392 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
393 ttm_bo_unreserve(&nvbo->bo);
394 return ret;
395}
396
397void
398nouveau_bo_unmap(struct nouveau_bo *nvbo)
399{
400 if (nvbo)
401 ttm_bo_kunmap(&nvbo->kmap);
402}
403
404int
405nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
406 bool no_wait_gpu)
407{
408 int ret;
409
410 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
411 interruptible, no_wait_gpu);
412 if (ret)
413 return ret;
414
415 return 0;
416}
417
418u16
419nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
420{
421 bool is_iomem;
422 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
423 mem = &mem[index];
424 if (is_iomem)
425 return ioread16_native((void __force __iomem *)mem);
426 else
427 return *mem;
428}
429
430void
431nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
432{
433 bool is_iomem;
434 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
435 mem = &mem[index];
436 if (is_iomem)
437 iowrite16_native(val, (void __force __iomem *)mem);
438 else
439 *mem = val;
440}
441
442u32
443nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
444{
445 bool is_iomem;
446 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
447 mem = &mem[index];
448 if (is_iomem)
449 return ioread32_native((void __force __iomem *)mem);
450 else
451 return *mem;
452}
453
454void
455nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
456{
457 bool is_iomem;
458 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
459 mem = &mem[index];
460 if (is_iomem)
461 iowrite32_native(val, (void __force __iomem *)mem);
462 else
463 *mem = val;
464}
465
466static struct ttm_tt *
467nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
468 uint32_t page_flags, struct page *dummy_read)
469{
470#if __OS_HAS_AGP
471 struct nouveau_drm *drm = nouveau_bdev(bdev);
472 struct drm_device *dev = drm->dev;
473
474 if (drm->agp.stat == ENABLED) {
475 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
476 page_flags, dummy_read);
477 }
478#endif
479
480 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
481}
482
483static int
484nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
485{
486 /* We'll do this from user space. */
487 return 0;
488}
489
490static int
491nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
492 struct ttm_mem_type_manager *man)
493{
494 struct nouveau_drm *drm = nouveau_bdev(bdev);
495
496 switch (type) {
497 case TTM_PL_SYSTEM:
498 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
499 man->available_caching = TTM_PL_MASK_CACHING;
500 man->default_caching = TTM_PL_FLAG_CACHED;
501 break;
502 case TTM_PL_VRAM:
503 if (nv_device(drm->device)->card_type >= NV_50) {
504 man->func = &nouveau_vram_manager;
505 man->io_reserve_fastpath = false;
506 man->use_io_reserve_lru = true;
507 } else {
508 man->func = &ttm_bo_manager_func;
509 }
510 man->flags = TTM_MEMTYPE_FLAG_FIXED |
511 TTM_MEMTYPE_FLAG_MAPPABLE;
512 man->available_caching = TTM_PL_FLAG_UNCACHED |
513 TTM_PL_FLAG_WC;
514 man->default_caching = TTM_PL_FLAG_WC;
515 break;
516 case TTM_PL_TT:
517 if (nv_device(drm->device)->card_type >= NV_50)
518 man->func = &nouveau_gart_manager;
519 else
520 if (drm->agp.stat != ENABLED)
521 man->func = &nv04_gart_manager;
522 else
523 man->func = &ttm_bo_manager_func;
524
525 if (drm->agp.stat == ENABLED) {
526 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
527 man->available_caching = TTM_PL_FLAG_UNCACHED |
528 TTM_PL_FLAG_WC;
529 man->default_caching = TTM_PL_FLAG_WC;
530 } else {
531 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
532 TTM_MEMTYPE_FLAG_CMA;
533 man->available_caching = TTM_PL_MASK_CACHING;
534 man->default_caching = TTM_PL_FLAG_CACHED;
535 }
536
537 break;
538 default:
539 return -EINVAL;
540 }
541 return 0;
542}
543
544static void
545nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
546{
547 struct nouveau_bo *nvbo = nouveau_bo(bo);
548
549 switch (bo->mem.mem_type) {
550 case TTM_PL_VRAM:
551 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
552 TTM_PL_FLAG_SYSTEM);
553 break;
554 default:
555 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
556 break;
557 }
558
559 *pl = nvbo->placement;
560}
561
562
563static int
564nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
565{
566 int ret = RING_SPACE(chan, 2);
567 if (ret == 0) {
568 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
569 OUT_RING (chan, handle & 0x0000ffff);
570 FIRE_RING (chan);
571 }
572 return ret;
573}
574
575static int
576nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
577 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
578{
579 struct nouveau_mem *node = old_mem->mm_node;
580 int ret = RING_SPACE(chan, 10);
581 if (ret == 0) {
582 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
583 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
584 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
585 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
586 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
587 OUT_RING (chan, PAGE_SIZE);
588 OUT_RING (chan, PAGE_SIZE);
589 OUT_RING (chan, PAGE_SIZE);
590 OUT_RING (chan, new_mem->num_pages);
591 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
592 }
593 return ret;
594}
595
596static int
597nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
598{
599 int ret = RING_SPACE(chan, 2);
600 if (ret == 0) {
601 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
602 OUT_RING (chan, handle);
603 }
604 return ret;
605}
606
607static int
608nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
609 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
610{
611 struct nouveau_mem *node = old_mem->mm_node;
612 u64 src_offset = node->vma[0].offset;
613 u64 dst_offset = node->vma[1].offset;
614 u32 page_count = new_mem->num_pages;
615 int ret;
616
617 page_count = new_mem->num_pages;
618 while (page_count) {
619 int line_count = (page_count > 8191) ? 8191 : page_count;
620
621 ret = RING_SPACE(chan, 11);
622 if (ret)
623 return ret;
624
625 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
626 OUT_RING (chan, upper_32_bits(src_offset));
627 OUT_RING (chan, lower_32_bits(src_offset));
628 OUT_RING (chan, upper_32_bits(dst_offset));
629 OUT_RING (chan, lower_32_bits(dst_offset));
630 OUT_RING (chan, PAGE_SIZE);
631 OUT_RING (chan, PAGE_SIZE);
632 OUT_RING (chan, PAGE_SIZE);
633 OUT_RING (chan, line_count);
634 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
635 OUT_RING (chan, 0x00000110);
636
637 page_count -= line_count;
638 src_offset += (PAGE_SIZE * line_count);
639 dst_offset += (PAGE_SIZE * line_count);
640 }
641
642 return 0;
643}
644
645static int
646nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
647 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
648{
649 struct nouveau_mem *node = old_mem->mm_node;
650 u64 src_offset = node->vma[0].offset;
651 u64 dst_offset = node->vma[1].offset;
652 u32 page_count = new_mem->num_pages;
653 int ret;
654
655 page_count = new_mem->num_pages;
656 while (page_count) {
657 int line_count = (page_count > 2047) ? 2047 : page_count;
658
659 ret = RING_SPACE(chan, 12);
660 if (ret)
661 return ret;
662
663 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
664 OUT_RING (chan, upper_32_bits(dst_offset));
665 OUT_RING (chan, lower_32_bits(dst_offset));
666 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
667 OUT_RING (chan, upper_32_bits(src_offset));
668 OUT_RING (chan, lower_32_bits(src_offset));
669 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
670 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
671 OUT_RING (chan, PAGE_SIZE); /* line_length */
672 OUT_RING (chan, line_count);
673 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
674 OUT_RING (chan, 0x00100110);
675
676 page_count -= line_count;
677 src_offset += (PAGE_SIZE * line_count);
678 dst_offset += (PAGE_SIZE * line_count);
679 }
680
681 return 0;
682}
683
684static int
685nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
686 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
687{
688 struct nouveau_mem *node = old_mem->mm_node;
689 u64 src_offset = node->vma[0].offset;
690 u64 dst_offset = node->vma[1].offset;
691 u32 page_count = new_mem->num_pages;
692 int ret;
693
694 page_count = new_mem->num_pages;
695 while (page_count) {
696 int line_count = (page_count > 8191) ? 8191 : page_count;
697
698 ret = RING_SPACE(chan, 11);
699 if (ret)
700 return ret;
701
702 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
703 OUT_RING (chan, upper_32_bits(src_offset));
704 OUT_RING (chan, lower_32_bits(src_offset));
705 OUT_RING (chan, upper_32_bits(dst_offset));
706 OUT_RING (chan, lower_32_bits(dst_offset));
707 OUT_RING (chan, PAGE_SIZE);
708 OUT_RING (chan, PAGE_SIZE);
709 OUT_RING (chan, PAGE_SIZE);
710 OUT_RING (chan, line_count);
711 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
712 OUT_RING (chan, 0x00000110);
713
714 page_count -= line_count;
715 src_offset += (PAGE_SIZE * line_count);
716 dst_offset += (PAGE_SIZE * line_count);
717 }
718
719 return 0;
720}
721
722static int
723nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
724 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
725{
726 struct nouveau_mem *node = old_mem->mm_node;
727 int ret = RING_SPACE(chan, 7);
728 if (ret == 0) {
729 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
730 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
731 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
732 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
733 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
734 OUT_RING (chan, 0x00000000 /* COPY */);
735 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
736 }
737 return ret;
738}
739
740static int
741nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
742 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
743{
744 struct nouveau_mem *node = old_mem->mm_node;
745 int ret = RING_SPACE(chan, 7);
746 if (ret == 0) {
747 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
748 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
749 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
750 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
751 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
752 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
753 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
754 }
755 return ret;
756}
757
758static int
759nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
760{
761 int ret = RING_SPACE(chan, 6);
762 if (ret == 0) {
763 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
764 OUT_RING (chan, handle);
765 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
766 OUT_RING (chan, NvNotify0);
767 OUT_RING (chan, NvDmaFB);
768 OUT_RING (chan, NvDmaFB);
769 }
770
771 return ret;
772}
773
774static int
775nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
776 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
777{
778 struct nouveau_mem *node = old_mem->mm_node;
779 u64 length = (new_mem->num_pages << PAGE_SHIFT);
780 u64 src_offset = node->vma[0].offset;
781 u64 dst_offset = node->vma[1].offset;
782 int src_tiled = !!node->memtype;
783 int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype;
784 int ret;
785
786 while (length) {
787 u32 amount, stride, height;
788
789 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
790 if (ret)
791 return ret;
792
793 amount = min(length, (u64)(4 * 1024 * 1024));
794 stride = 16 * 4;
795 height = amount / stride;
796
797 if (src_tiled) {
798 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
799 OUT_RING (chan, 0);
800 OUT_RING (chan, 0);
801 OUT_RING (chan, stride);
802 OUT_RING (chan, height);
803 OUT_RING (chan, 1);
804 OUT_RING (chan, 0);
805 OUT_RING (chan, 0);
806 } else {
807 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
808 OUT_RING (chan, 1);
809 }
810 if (dst_tiled) {
811 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
812 OUT_RING (chan, 0);
813 OUT_RING (chan, 0);
814 OUT_RING (chan, stride);
815 OUT_RING (chan, height);
816 OUT_RING (chan, 1);
817 OUT_RING (chan, 0);
818 OUT_RING (chan, 0);
819 } else {
820 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
821 OUT_RING (chan, 1);
822 }
823
824 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
825 OUT_RING (chan, upper_32_bits(src_offset));
826 OUT_RING (chan, upper_32_bits(dst_offset));
827 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
828 OUT_RING (chan, lower_32_bits(src_offset));
829 OUT_RING (chan, lower_32_bits(dst_offset));
830 OUT_RING (chan, stride);
831 OUT_RING (chan, stride);
832 OUT_RING (chan, stride);
833 OUT_RING (chan, height);
834 OUT_RING (chan, 0x00000101);
835 OUT_RING (chan, 0x00000000);
836 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
837 OUT_RING (chan, 0);
838
839 length -= amount;
840 src_offset += amount;
841 dst_offset += amount;
842 }
843
844 return 0;
845}
846
847static int
848nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
849{
850 int ret = RING_SPACE(chan, 4);
851 if (ret == 0) {
852 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
853 OUT_RING (chan, handle);
854 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
855 OUT_RING (chan, NvNotify0);
856 }
857
858 return ret;
859}
860
861static inline uint32_t
862nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
863 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
864{
865 if (mem->mem_type == TTM_PL_TT)
866 return NvDmaTT;
867 return NvDmaFB;
868}
869
870static int
871nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
872 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
873{
874 u32 src_offset = old_mem->start << PAGE_SHIFT;
875 u32 dst_offset = new_mem->start << PAGE_SHIFT;
876 u32 page_count = new_mem->num_pages;
877 int ret;
878
879 ret = RING_SPACE(chan, 3);
880 if (ret)
881 return ret;
882
883 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
884 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
885 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
886
887 page_count = new_mem->num_pages;
888 while (page_count) {
889 int line_count = (page_count > 2047) ? 2047 : page_count;
890
891 ret = RING_SPACE(chan, 11);
892 if (ret)
893 return ret;
894
895 BEGIN_NV04(chan, NvSubCopy,
896 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
897 OUT_RING (chan, src_offset);
898 OUT_RING (chan, dst_offset);
899 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
900 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
901 OUT_RING (chan, PAGE_SIZE); /* line_length */
902 OUT_RING (chan, line_count);
903 OUT_RING (chan, 0x00000101);
904 OUT_RING (chan, 0x00000000);
905 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
906 OUT_RING (chan, 0);
907
908 page_count -= line_count;
909 src_offset += (PAGE_SIZE * line_count);
910 dst_offset += (PAGE_SIZE * line_count);
911 }
912
913 return 0;
914}
915
916static int
917nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
918 struct ttm_mem_reg *mem)
919{
920 struct nouveau_mem *old_node = bo->mem.mm_node;
921 struct nouveau_mem *new_node = mem->mm_node;
922 u64 size = (u64)mem->num_pages << PAGE_SHIFT;
923 int ret;
924
925 ret = nouveau_vm_get(nv_client(drm)->vm, size, old_node->page_shift,
926 NV_MEM_ACCESS_RW, &old_node->vma[0]);
927 if (ret)
928 return ret;
929
930 ret = nouveau_vm_get(nv_client(drm)->vm, size, new_node->page_shift,
931 NV_MEM_ACCESS_RW, &old_node->vma[1]);
932 if (ret) {
933 nouveau_vm_put(&old_node->vma[0]);
934 return ret;
935 }
936
937 nouveau_vm_map(&old_node->vma[0], old_node);
938 nouveau_vm_map(&old_node->vma[1], new_node);
939 return 0;
940}
941
942static int
943nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
944 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
945{
946 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
947 struct nouveau_channel *chan = drm->ttm.chan;
948 struct nouveau_fence *fence;
949 int ret;
950
951 /* create temporary vmas for the transfer and attach them to the
952 * old nouveau_mem node, these will get cleaned up after ttm has
953 * destroyed the ttm_mem_reg
954 */
955 if (nv_device(drm->device)->card_type >= NV_50) {
956 ret = nouveau_bo_move_prep(drm, bo, new_mem);
957 if (ret)
958 return ret;
959 }
960
961 mutex_lock_nested(&chan->cli->mutex, SINGLE_DEPTH_NESTING);
962 ret = nouveau_fence_sync(bo->sync_obj, chan);
963 if (ret == 0) {
964 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
965 if (ret == 0) {
966 ret = nouveau_fence_new(chan, false, &fence);
967 if (ret == 0) {
968 ret = ttm_bo_move_accel_cleanup(bo, fence,
969 evict,
970 no_wait_gpu,
971 new_mem);
972 nouveau_fence_unref(&fence);
973 }
974 }
975 }
976 mutex_unlock(&chan->cli->mutex);
977 return ret;
978}
979
980void
981nouveau_bo_move_init(struct nouveau_drm *drm)
982{
983 static const struct {
984 const char *name;
985 int engine;
986 u32 oclass;
987 int (*exec)(struct nouveau_channel *,
988 struct ttm_buffer_object *,
989 struct ttm_mem_reg *, struct ttm_mem_reg *);
990 int (*init)(struct nouveau_channel *, u32 handle);
991 } _methods[] = {
992 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
993 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
994 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
995 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
996 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
997 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
998 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
999 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1000 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1001 {},
1002 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1003 }, *mthd = _methods;
1004 const char *name = "CPU";
1005 int ret;
1006
1007 do {
1008 struct nouveau_object *object;
1009 struct nouveau_channel *chan;
1010 u32 handle = (mthd->engine << 16) | mthd->oclass;
1011
1012 if (mthd->engine)
1013 chan = drm->cechan;
1014 else
1015 chan = drm->channel;
1016 if (chan == NULL)
1017 continue;
1018
1019 ret = nouveau_object_new(nv_object(drm), chan->handle, handle,
1020 mthd->oclass, NULL, 0, &object);
1021 if (ret == 0) {
1022 ret = mthd->init(chan, handle);
1023 if (ret) {
1024 nouveau_object_del(nv_object(drm),
1025 chan->handle, handle);
1026 continue;
1027 }
1028
1029 drm->ttm.move = mthd->exec;
1030 drm->ttm.chan = chan;
1031 name = mthd->name;
1032 break;
1033 }
1034 } while ((++mthd)->exec);
1035
1036 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1037}
1038
1039static int
1040nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1041 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1042{
1043 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1044 struct ttm_placement placement;
1045 struct ttm_mem_reg tmp_mem;
1046 int ret;
1047
1048 placement.fpfn = placement.lpfn = 0;
1049 placement.num_placement = placement.num_busy_placement = 1;
1050 placement.placement = placement.busy_placement = &placement_memtype;
1051
1052 tmp_mem = *new_mem;
1053 tmp_mem.mm_node = NULL;
1054 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1055 if (ret)
1056 return ret;
1057
1058 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1059 if (ret)
1060 goto out;
1061
1062 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1063 if (ret)
1064 goto out;
1065
1066 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1067out:
1068 ttm_bo_mem_put(bo, &tmp_mem);
1069 return ret;
1070}
1071
1072static int
1073nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1074 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1075{
1076 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
1077 struct ttm_placement placement;
1078 struct ttm_mem_reg tmp_mem;
1079 int ret;
1080
1081 placement.fpfn = placement.lpfn = 0;
1082 placement.num_placement = placement.num_busy_placement = 1;
1083 placement.placement = placement.busy_placement = &placement_memtype;
1084
1085 tmp_mem = *new_mem;
1086 tmp_mem.mm_node = NULL;
1087 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1088 if (ret)
1089 return ret;
1090
1091 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1092 if (ret)
1093 goto out;
1094
1095 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1096 if (ret)
1097 goto out;
1098
1099out:
1100 ttm_bo_mem_put(bo, &tmp_mem);
1101 return ret;
1102}
1103
1104static void
1105nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1106{
1107 struct nouveau_bo *nvbo = nouveau_bo(bo);
1108 struct nouveau_vma *vma;
1109
1110 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1111 if (bo->destroy != nouveau_bo_del_ttm)
1112 return;
1113
1114 list_for_each_entry(vma, &nvbo->vma_list, head) {
1115 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1116 (new_mem->mem_type == TTM_PL_VRAM ||
1117 nvbo->page_shift != vma->vm->vmm->lpg_shift)) {
1118 nouveau_vm_map(vma, new_mem->mm_node);
1119 } else {
1120 nouveau_vm_unmap(vma);
1121 }
1122 }
1123}
1124
1125static int
1126nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1127 struct nouveau_drm_tile **new_tile)
1128{
1129 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1130 struct drm_device *dev = drm->dev;
1131 struct nouveau_bo *nvbo = nouveau_bo(bo);
1132 u64 offset = new_mem->start << PAGE_SHIFT;
1133
1134 *new_tile = NULL;
1135 if (new_mem->mem_type != TTM_PL_VRAM)
1136 return 0;
1137
1138 if (nv_device(drm->device)->card_type >= NV_10) {
1139 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1140 nvbo->tile_mode,
1141 nvbo->tile_flags);
1142 }
1143
1144 return 0;
1145}
1146
1147static void
1148nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1149 struct nouveau_drm_tile *new_tile,
1150 struct nouveau_drm_tile **old_tile)
1151{
1152 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1153 struct drm_device *dev = drm->dev;
1154
1155 nv10_bo_put_tile_region(dev, *old_tile, bo->sync_obj);
1156 *old_tile = new_tile;
1157}
1158
1159static int
1160nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1161 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1162{
1163 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1164 struct nouveau_bo *nvbo = nouveau_bo(bo);
1165 struct ttm_mem_reg *old_mem = &bo->mem;
1166 struct nouveau_drm_tile *new_tile = NULL;
1167 int ret = 0;
1168
1169 if (nv_device(drm->device)->card_type < NV_50) {
1170 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1171 if (ret)
1172 return ret;
1173 }
1174
1175 /* Fake bo copy. */
1176 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1177 BUG_ON(bo->mem.mm_node != NULL);
1178 bo->mem = *new_mem;
1179 new_mem->mm_node = NULL;
1180 goto out;
1181 }
1182
1183 /* Hardware assisted copy. */
1184 if (drm->ttm.move) {
1185 if (new_mem->mem_type == TTM_PL_SYSTEM)
1186 ret = nouveau_bo_move_flipd(bo, evict, intr,
1187 no_wait_gpu, new_mem);
1188 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1189 ret = nouveau_bo_move_flips(bo, evict, intr,
1190 no_wait_gpu, new_mem);
1191 else
1192 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1193 no_wait_gpu, new_mem);
1194 if (!ret)
1195 goto out;
1196 }
1197
1198 /* Fallback to software copy. */
1199 spin_lock(&bo->bdev->fence_lock);
1200 ret = ttm_bo_wait(bo, true, intr, no_wait_gpu);
1201 spin_unlock(&bo->bdev->fence_lock);
1202 if (ret == 0)
1203 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1204
1205out:
1206 if (nv_device(drm->device)->card_type < NV_50) {
1207 if (ret)
1208 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1209 else
1210 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1211 }
1212
1213 return ret;
1214}
1215
1216static int
1217nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1218{
1219 struct nouveau_bo *nvbo = nouveau_bo(bo);
1220
1221 return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp);
1222}
1223
1224static int
1225nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1226{
1227 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1228 struct nouveau_drm *drm = nouveau_bdev(bdev);
1229 struct nouveau_mem *node = mem->mm_node;
1230 struct drm_device *dev = drm->dev;
1231 int ret;
1232
1233 mem->bus.addr = NULL;
1234 mem->bus.offset = 0;
1235 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1236 mem->bus.base = 0;
1237 mem->bus.is_iomem = false;
1238 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1239 return -EINVAL;
1240 switch (mem->mem_type) {
1241 case TTM_PL_SYSTEM:
1242 /* System memory */
1243 return 0;
1244 case TTM_PL_TT:
1245#if __OS_HAS_AGP
1246 if (drm->agp.stat == ENABLED) {
1247 mem->bus.offset = mem->start << PAGE_SHIFT;
1248 mem->bus.base = drm->agp.base;
1249 mem->bus.is_iomem = !dev->agp->cant_use_aperture;
1250 }
1251#endif
1252 if (nv_device(drm->device)->card_type < NV_50 || !node->memtype)
1253 /* untiled */
1254 break;
1255 /* fallthrough, tiled memory */
1256 case TTM_PL_VRAM:
1257 mem->bus.offset = mem->start << PAGE_SHIFT;
1258 mem->bus.base = nv_device_resource_start(nouveau_dev(dev), 1);
1259 mem->bus.is_iomem = true;
1260 if (nv_device(drm->device)->card_type >= NV_50) {
1261 struct nouveau_bar *bar = nouveau_bar(drm->device);
1262
1263 ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1264 &node->bar_vma);
1265 if (ret)
1266 return ret;
1267
1268 mem->bus.offset = node->bar_vma.offset;
1269 }
1270 break;
1271 default:
1272 return -EINVAL;
1273 }
1274 return 0;
1275}
1276
1277static void
1278nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1279{
1280 struct nouveau_drm *drm = nouveau_bdev(bdev);
1281 struct nouveau_bar *bar = nouveau_bar(drm->device);
1282 struct nouveau_mem *node = mem->mm_node;
1283
1284 if (!node->bar_vma.node)
1285 return;
1286
1287 bar->unmap(bar, &node->bar_vma);
1288}
1289
1290static int
1291nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1292{
1293 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1294 struct nouveau_bo *nvbo = nouveau_bo(bo);
1295 struct nouveau_device *device = nv_device(drm->device);
1296 u32 mappable = nv_device_resource_len(device, 1) >> PAGE_SHIFT;
1297 int ret;
1298
1299 /* as long as the bo isn't in vram, and isn't tiled, we've got
1300 * nothing to do here.
1301 */
1302 if (bo->mem.mem_type != TTM_PL_VRAM) {
1303 if (nv_device(drm->device)->card_type < NV_50 ||
1304 !nouveau_bo_tile_layout(nvbo))
1305 return 0;
1306
1307 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1308 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1309
1310 ret = nouveau_bo_validate(nvbo, false, false);
1311 if (ret)
1312 return ret;
1313 }
1314 return 0;
1315 }
1316
1317 /* make sure bo is in mappable vram */
1318 if (nv_device(drm->device)->card_type >= NV_50 ||
1319 bo->mem.start + bo->mem.num_pages < mappable)
1320 return 0;
1321
1322
1323 nvbo->placement.fpfn = 0;
1324 nvbo->placement.lpfn = mappable;
1325 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1326 return nouveau_bo_validate(nvbo, false, false);
1327}
1328
1329static int
1330nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1331{
1332 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1333 struct nouveau_drm *drm;
1334 struct nouveau_device *device;
1335 struct drm_device *dev;
1336 unsigned i;
1337 int r;
1338 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1339
1340 if (ttm->state != tt_unpopulated)
1341 return 0;
1342
1343 if (slave && ttm->sg) {
1344 /* make userspace faulting work */
1345 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1346 ttm_dma->dma_address, ttm->num_pages);
1347 ttm->state = tt_unbound;
1348 return 0;
1349 }
1350
1351 drm = nouveau_bdev(ttm->bdev);
1352 device = nv_device(drm->device);
1353 dev = drm->dev;
1354
1355#if __OS_HAS_AGP
1356 if (drm->agp.stat == ENABLED) {
1357 return ttm_agp_tt_populate(ttm);
1358 }
1359#endif
1360
1361#ifdef CONFIG_SWIOTLB
1362 if (swiotlb_nr_tbl()) {
1363 return ttm_dma_populate((void *)ttm, dev->dev);
1364 }
1365#endif
1366
1367 r = ttm_pool_populate(ttm);
1368 if (r) {
1369 return r;
1370 }
1371
1372 for (i = 0; i < ttm->num_pages; i++) {
1373 ttm_dma->dma_address[i] = nv_device_map_page(device,
1374 ttm->pages[i]);
1375 if (!ttm_dma->dma_address[i]) {
1376 while (--i) {
1377 nv_device_unmap_page(device,
1378 ttm_dma->dma_address[i]);
1379 ttm_dma->dma_address[i] = 0;
1380 }
1381 ttm_pool_unpopulate(ttm);
1382 return -EFAULT;
1383 }
1384 }
1385 return 0;
1386}
1387
1388static void
1389nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1390{
1391 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1392 struct nouveau_drm *drm;
1393 struct nouveau_device *device;
1394 struct drm_device *dev;
1395 unsigned i;
1396 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1397
1398 if (slave)
1399 return;
1400
1401 drm = nouveau_bdev(ttm->bdev);
1402 device = nv_device(drm->device);
1403 dev = drm->dev;
1404
1405#if __OS_HAS_AGP
1406 if (drm->agp.stat == ENABLED) {
1407 ttm_agp_tt_unpopulate(ttm);
1408 return;
1409 }
1410#endif
1411
1412#ifdef CONFIG_SWIOTLB
1413 if (swiotlb_nr_tbl()) {
1414 ttm_dma_unpopulate((void *)ttm, dev->dev);
1415 return;
1416 }
1417#endif
1418
1419 for (i = 0; i < ttm->num_pages; i++) {
1420 if (ttm_dma->dma_address[i]) {
1421 nv_device_unmap_page(device, ttm_dma->dma_address[i]);
1422 }
1423 }
1424
1425 ttm_pool_unpopulate(ttm);
1426}
1427
1428void
1429nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1430{
1431 struct nouveau_fence *new_fence = nouveau_fence_ref(fence);
1432 struct nouveau_fence *old_fence = NULL;
1433
1434 spin_lock(&nvbo->bo.bdev->fence_lock);
1435 old_fence = nvbo->bo.sync_obj;
1436 nvbo->bo.sync_obj = new_fence;
1437 spin_unlock(&nvbo->bo.bdev->fence_lock);
1438
1439 nouveau_fence_unref(&old_fence);
1440}
1441
1442static void
1443nouveau_bo_fence_unref(void **sync_obj)
1444{
1445 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1446}
1447
1448static void *
1449nouveau_bo_fence_ref(void *sync_obj)
1450{
1451 return nouveau_fence_ref(sync_obj);
1452}
1453
1454static bool
1455nouveau_bo_fence_signalled(void *sync_obj)
1456{
1457 return nouveau_fence_done(sync_obj);
1458}
1459
1460static int
1461nouveau_bo_fence_wait(void *sync_obj, bool lazy, bool intr)
1462{
1463 return nouveau_fence_wait(sync_obj, lazy, intr);
1464}
1465
1466static int
1467nouveau_bo_fence_flush(void *sync_obj)
1468{
1469 return 0;
1470}
1471
1472struct ttm_bo_driver nouveau_bo_driver = {
1473 .ttm_tt_create = &nouveau_ttm_tt_create,
1474 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1475 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1476 .invalidate_caches = nouveau_bo_invalidate_caches,
1477 .init_mem_type = nouveau_bo_init_mem_type,
1478 .evict_flags = nouveau_bo_evict_flags,
1479 .move_notify = nouveau_bo_move_ntfy,
1480 .move = nouveau_bo_move,
1481 .verify_access = nouveau_bo_verify_access,
1482 .sync_obj_signaled = nouveau_bo_fence_signalled,
1483 .sync_obj_wait = nouveau_bo_fence_wait,
1484 .sync_obj_flush = nouveau_bo_fence_flush,
1485 .sync_obj_unref = nouveau_bo_fence_unref,
1486 .sync_obj_ref = nouveau_bo_fence_ref,
1487 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1488 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1489 .io_mem_free = &nouveau_ttm_io_mem_free,
1490};
1491
1492struct nouveau_vma *
1493nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1494{
1495 struct nouveau_vma *vma;
1496 list_for_each_entry(vma, &nvbo->vma_list, head) {
1497 if (vma->vm == vm)
1498 return vma;
1499 }
1500
1501 return NULL;
1502}
1503
1504int
1505nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1506 struct nouveau_vma *vma)
1507{
1508 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1509 int ret;
1510
1511 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1512 NV_MEM_ACCESS_RW, vma);
1513 if (ret)
1514 return ret;
1515
1516 if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1517 (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1518 nvbo->page_shift != vma->vm->vmm->lpg_shift))
1519 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1520
1521 list_add_tail(&vma->head, &nvbo->vma_list);
1522 vma->refcount = 1;
1523 return 0;
1524}
1525
1526void
1527nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1528{
1529 if (vma->node) {
1530 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1531 nouveau_vm_unmap(vma);
1532 nouveau_vm_put(vma);
1533 list_del(&vma->head);
1534 }
1535}