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1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20120316"
34
35#define DRIVER_MAJOR 1
36#define DRIVER_MINOR 0
37#define DRIVER_PATCHLEVEL 0
38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 spinlock_t lock;
50 struct list_head channels;
51 struct nouveau_vm *vm;
52};
53
54static inline struct nouveau_fpriv *
55nouveau_fpriv(struct drm_file *file_priv)
56{
57 return file_priv ? file_priv->driver_priv : NULL;
58}
59
60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
61
62#include "nouveau_drm.h"
63#include "nouveau_reg.h"
64#include "nouveau_bios.h"
65#include "nouveau_util.h"
66
67struct nouveau_grctx;
68struct nouveau_mem;
69#include "nouveau_vm.h"
70
71#define MAX_NUM_DCB_ENTRIES 16
72
73#define NOUVEAU_MAX_CHANNEL_NR 4096
74#define NOUVEAU_MAX_TILE_NR 15
75
76struct nouveau_mem {
77 struct drm_device *dev;
78
79 struct nouveau_vma bar_vma;
80 struct nouveau_vma vma[2];
81 u8 page_shift;
82
83 struct drm_mm_node *tag;
84 struct list_head regions;
85 dma_addr_t *pages;
86 u32 memtype;
87 u64 offset;
88 u64 size;
89 struct sg_table *sg;
90};
91
92struct nouveau_tile_reg {
93 bool used;
94 uint32_t addr;
95 uint32_t limit;
96 uint32_t pitch;
97 uint32_t zcomp;
98 struct drm_mm_node *tag_mem;
99 struct nouveau_fence *fence;
100};
101
102struct nouveau_bo {
103 struct ttm_buffer_object bo;
104 struct ttm_placement placement;
105 u32 valid_domains;
106 u32 placements[3];
107 u32 busy_placements[3];
108 struct ttm_bo_kmap_obj kmap;
109 struct list_head head;
110
111 /* protected by ttm_bo_reserve() */
112 struct drm_file *reserved_by;
113 struct list_head entry;
114 int pbbo_index;
115 bool validate_mapped;
116
117 struct list_head vma_list;
118 unsigned page_shift;
119
120 uint32_t tile_mode;
121 uint32_t tile_flags;
122 struct nouveau_tile_reg *tile;
123
124 struct drm_gem_object *gem;
125 int pin_refcnt;
126
127 struct ttm_bo_kmap_obj dma_buf_vmap;
128 int vmapping_count;
129};
130
131#define nouveau_bo_tile_layout(nvbo) \
132 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
133
134static inline struct nouveau_bo *
135nouveau_bo(struct ttm_buffer_object *bo)
136{
137 return container_of(bo, struct nouveau_bo, bo);
138}
139
140static inline struct nouveau_bo *
141nouveau_gem_object(struct drm_gem_object *gem)
142{
143 return gem ? gem->driver_private : NULL;
144}
145
146/* TODO: submit equivalent to TTM generic API upstream? */
147static inline void __iomem *
148nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
149{
150 bool is_iomem;
151 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
152 &nvbo->kmap, &is_iomem);
153 WARN_ON_ONCE(ioptr && !is_iomem);
154 return ioptr;
155}
156
157enum nouveau_flags {
158 NV_NFORCE = 0x10000000,
159 NV_NFORCE2 = 0x20000000
160};
161
162#define NVOBJ_ENGINE_SW 0
163#define NVOBJ_ENGINE_GR 1
164#define NVOBJ_ENGINE_CRYPT 2
165#define NVOBJ_ENGINE_COPY0 3
166#define NVOBJ_ENGINE_COPY1 4
167#define NVOBJ_ENGINE_MPEG 5
168#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG
169#define NVOBJ_ENGINE_BSP 6
170#define NVOBJ_ENGINE_VP 7
171#define NVOBJ_ENGINE_FIFO 14
172#define NVOBJ_ENGINE_FENCE 15
173#define NVOBJ_ENGINE_NR 16
174#define NVOBJ_ENGINE_DISPLAY (NVOBJ_ENGINE_NR + 0) /*XXX*/
175
176#define NVOBJ_FLAG_DONT_MAP (1 << 0)
177#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
178#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
179#define NVOBJ_FLAG_VM (1 << 3)
180#define NVOBJ_FLAG_VM_USER (1 << 4)
181
182#define NVOBJ_CINST_GLOBAL 0xdeadbeef
183
184struct nouveau_gpuobj {
185 struct drm_device *dev;
186 struct kref refcount;
187 struct list_head list;
188
189 void *node;
190 u32 *suspend;
191
192 uint32_t flags;
193
194 u32 size;
195 u32 pinst; /* PRAMIN BAR offset */
196 u32 cinst; /* Channel offset */
197 u64 vinst; /* VRAM address */
198 u64 linst; /* VM address */
199
200 uint32_t engine;
201 uint32_t class;
202
203 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
204 void *priv;
205};
206
207struct nouveau_page_flip_state {
208 struct list_head head;
209 struct drm_pending_vblank_event *event;
210 int crtc, bpp, pitch, x, y;
211 uint64_t offset;
212};
213
214enum nouveau_channel_mutex_class {
215 NOUVEAU_UCHANNEL_MUTEX,
216 NOUVEAU_KCHANNEL_MUTEX
217};
218
219struct nouveau_channel {
220 struct drm_device *dev;
221 struct list_head list;
222 int id;
223
224 /* references to the channel data structure */
225 struct kref ref;
226 /* users of the hardware channel resources, the hardware
227 * context will be kicked off when it reaches zero. */
228 atomic_t users;
229 struct mutex mutex;
230
231 /* owner of this fifo */
232 struct drm_file *file_priv;
233 /* mapping of the fifo itself */
234 struct drm_local_map *map;
235
236 /* mapping of the regs controlling the fifo */
237 void __iomem *user;
238 uint32_t user_get;
239 uint32_t user_get_hi;
240 uint32_t user_put;
241
242 /* DMA push buffer */
243 struct nouveau_gpuobj *pushbuf;
244 struct nouveau_bo *pushbuf_bo;
245 struct nouveau_vma pushbuf_vma;
246 uint64_t pushbuf_base;
247
248 /* Notifier memory */
249 struct nouveau_bo *notifier_bo;
250 struct nouveau_vma notifier_vma;
251 struct drm_mm notifier_heap;
252
253 /* PFIFO context */
254 struct nouveau_gpuobj *ramfc;
255
256 /* Execution engine contexts */
257 void *engctx[NVOBJ_ENGINE_NR];
258
259 /* NV50 VM */
260 struct nouveau_vm *vm;
261 struct nouveau_gpuobj *vm_pd;
262
263 /* Objects */
264 struct nouveau_gpuobj *ramin; /* Private instmem */
265 struct drm_mm ramin_heap; /* Private PRAMIN heap */
266 struct nouveau_ramht *ramht; /* Hash table */
267
268 /* GPU object info for stuff used in-kernel (mm_enabled) */
269 uint32_t m2mf_ntfy;
270 uint32_t vram_handle;
271 uint32_t gart_handle;
272 bool accel_done;
273
274 /* Push buffer state (only for drm's channel on !mm_enabled) */
275 struct {
276 int max;
277 int free;
278 int cur;
279 int put;
280 /* access via pushbuf_bo */
281
282 int ib_base;
283 int ib_max;
284 int ib_free;
285 int ib_put;
286 } dma;
287
288 struct {
289 bool active;
290 char name[32];
291 struct drm_info_list info;
292 } debugfs;
293};
294
295struct nouveau_exec_engine {
296 void (*destroy)(struct drm_device *, int engine);
297 int (*init)(struct drm_device *, int engine);
298 int (*fini)(struct drm_device *, int engine, bool suspend);
299 int (*context_new)(struct nouveau_channel *, int engine);
300 void (*context_del)(struct nouveau_channel *, int engine);
301 int (*object_new)(struct nouveau_channel *, int engine,
302 u32 handle, u16 class);
303 void (*set_tile_region)(struct drm_device *dev, int i);
304 void (*tlb_flush)(struct drm_device *, int engine);
305};
306
307struct nouveau_instmem_engine {
308 void *priv;
309
310 int (*init)(struct drm_device *dev);
311 void (*takedown)(struct drm_device *dev);
312 int (*suspend)(struct drm_device *dev);
313 void (*resume)(struct drm_device *dev);
314
315 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *,
316 u32 size, u32 align);
317 void (*put)(struct nouveau_gpuobj *);
318 int (*map)(struct nouveau_gpuobj *);
319 void (*unmap)(struct nouveau_gpuobj *);
320
321 void (*flush)(struct drm_device *);
322};
323
324struct nouveau_mc_engine {
325 int (*init)(struct drm_device *dev);
326 void (*takedown)(struct drm_device *dev);
327};
328
329struct nouveau_timer_engine {
330 int (*init)(struct drm_device *dev);
331 void (*takedown)(struct drm_device *dev);
332 uint64_t (*read)(struct drm_device *dev);
333};
334
335struct nouveau_fb_engine {
336 int num_tiles;
337 struct drm_mm tag_heap;
338 void *priv;
339
340 int (*init)(struct drm_device *dev);
341 void (*takedown)(struct drm_device *dev);
342
343 void (*init_tile_region)(struct drm_device *dev, int i,
344 uint32_t addr, uint32_t size,
345 uint32_t pitch, uint32_t flags);
346 void (*set_tile_region)(struct drm_device *dev, int i);
347 void (*free_tile_region)(struct drm_device *dev, int i);
348};
349
350struct nouveau_display_engine {
351 void *priv;
352 int (*early_init)(struct drm_device *);
353 void (*late_takedown)(struct drm_device *);
354 int (*create)(struct drm_device *);
355 void (*destroy)(struct drm_device *);
356 int (*init)(struct drm_device *);
357 void (*fini)(struct drm_device *);
358
359 struct drm_property *dithering_mode;
360 struct drm_property *dithering_depth;
361 struct drm_property *underscan_property;
362 struct drm_property *underscan_hborder_property;
363 struct drm_property *underscan_vborder_property;
364 /* not really hue and saturation: */
365 struct drm_property *vibrant_hue_property;
366 struct drm_property *color_vibrance_property;
367};
368
369struct nouveau_gpio_engine {
370 spinlock_t lock;
371 struct list_head isr;
372 int (*init)(struct drm_device *);
373 void (*fini)(struct drm_device *);
374 int (*drive)(struct drm_device *, int line, int dir, int out);
375 int (*sense)(struct drm_device *, int line);
376 void (*irq_enable)(struct drm_device *, int line, bool);
377};
378
379struct nouveau_pm_voltage_level {
380 u32 voltage; /* microvolts */
381 u8 vid;
382};
383
384struct nouveau_pm_voltage {
385 bool supported;
386 u8 version;
387 u8 vid_mask;
388
389 struct nouveau_pm_voltage_level *level;
390 int nr_level;
391};
392
393/* Exclusive upper limits */
394#define NV_MEM_CL_DDR2_MAX 8
395#define NV_MEM_WR_DDR2_MAX 9
396#define NV_MEM_CL_DDR3_MAX 17
397#define NV_MEM_WR_DDR3_MAX 17
398#define NV_MEM_CL_GDDR3_MAX 16
399#define NV_MEM_WR_GDDR3_MAX 18
400#define NV_MEM_CL_GDDR5_MAX 21
401#define NV_MEM_WR_GDDR5_MAX 20
402
403struct nouveau_pm_memtiming {
404 int id;
405
406 u32 reg[9];
407 u32 mr[4];
408
409 u8 tCWL;
410
411 u8 odt;
412 u8 drive_strength;
413};
414
415struct nouveau_pm_tbl_header {
416 u8 version;
417 u8 header_len;
418 u8 entry_cnt;
419 u8 entry_len;
420};
421
422struct nouveau_pm_tbl_entry {
423 u8 tWR;
424 u8 tWTR;
425 u8 tCL;
426 u8 tRC;
427 u8 empty_4;
428 u8 tRFC; /* Byte 5 */
429 u8 empty_6;
430 u8 tRAS; /* Byte 7 */
431 u8 empty_8;
432 u8 tRP; /* Byte 9 */
433 u8 tRCDRD;
434 u8 tRCDWR;
435 u8 tRRD;
436 u8 tUNK_13;
437 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
438 u8 empty_15;
439 u8 tUNK_16;
440 u8 empty_17;
441 u8 tUNK_18;
442 u8 tCWL;
443 u8 tUNK_20, tUNK_21;
444};
445
446struct nouveau_pm_profile;
447struct nouveau_pm_profile_func {
448 void (*destroy)(struct nouveau_pm_profile *);
449 void (*init)(struct nouveau_pm_profile *);
450 void (*fini)(struct nouveau_pm_profile *);
451 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
452};
453
454struct nouveau_pm_profile {
455 const struct nouveau_pm_profile_func *func;
456 struct list_head head;
457 char name[8];
458};
459
460#define NOUVEAU_PM_MAX_LEVEL 8
461struct nouveau_pm_level {
462 struct nouveau_pm_profile profile;
463 struct device_attribute dev_attr;
464 char name[32];
465 int id;
466
467 struct nouveau_pm_memtiming timing;
468 u32 memory;
469 u16 memscript;
470
471 u32 core;
472 u32 shader;
473 u32 rop;
474 u32 copy;
475 u32 daemon;
476 u32 vdec;
477 u32 dom6;
478 u32 unka0; /* nva3:nvc0 */
479 u32 hub01; /* nvc0- */
480 u32 hub06; /* nvc0- */
481 u32 hub07; /* nvc0- */
482
483 u32 volt_min; /* microvolts */
484 u32 volt_max;
485 u8 fanspeed;
486};
487
488struct nouveau_pm_temp_sensor_constants {
489 u16 offset_constant;
490 s16 offset_mult;
491 s16 offset_div;
492 s16 slope_mult;
493 s16 slope_div;
494};
495
496struct nouveau_pm_threshold_temp {
497 s16 critical;
498 s16 down_clock;
499 s16 fan_boost;
500};
501
502struct nouveau_pm_fan {
503 u32 percent;
504 u32 min_duty;
505 u32 max_duty;
506 u32 pwm_freq;
507 u32 pwm_divisor;
508};
509
510struct nouveau_pm_engine {
511 struct nouveau_pm_voltage voltage;
512 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
513 int nr_perflvl;
514 struct nouveau_pm_temp_sensor_constants sensor_constants;
515 struct nouveau_pm_threshold_temp threshold_temp;
516 struct nouveau_pm_fan fan;
517
518 struct nouveau_pm_profile *profile_ac;
519 struct nouveau_pm_profile *profile_dc;
520 struct nouveau_pm_profile *profile;
521 struct list_head profiles;
522
523 struct nouveau_pm_level boot;
524 struct nouveau_pm_level *cur;
525
526 struct device *hwmon;
527 struct notifier_block acpi_nb;
528
529 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
530 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
531 int (*clocks_set)(struct drm_device *, void *);
532
533 int (*voltage_get)(struct drm_device *);
534 int (*voltage_set)(struct drm_device *, int voltage);
535 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
536 int (*pwm_set)(struct drm_device *, int line, u32, u32);
537 int (*temp_get)(struct drm_device *);
538};
539
540struct nouveau_vram_engine {
541 struct nouveau_mm mm;
542
543 int (*init)(struct drm_device *);
544 void (*takedown)(struct drm_device *dev);
545 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
546 u32 type, struct nouveau_mem **);
547 void (*put)(struct drm_device *, struct nouveau_mem **);
548
549 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
550};
551
552struct nouveau_engine {
553 struct nouveau_instmem_engine instmem;
554 struct nouveau_mc_engine mc;
555 struct nouveau_timer_engine timer;
556 struct nouveau_fb_engine fb;
557 struct nouveau_display_engine display;
558 struct nouveau_gpio_engine gpio;
559 struct nouveau_pm_engine pm;
560 struct nouveau_vram_engine vram;
561};
562
563struct nouveau_pll_vals {
564 union {
565 struct {
566#ifdef __BIG_ENDIAN
567 uint8_t N1, M1, N2, M2;
568#else
569 uint8_t M1, N1, M2, N2;
570#endif
571 };
572 struct {
573 uint16_t NM1, NM2;
574 } __attribute__((packed));
575 };
576 int log2P;
577
578 int refclk;
579};
580
581enum nv04_fp_display_regs {
582 FP_DISPLAY_END,
583 FP_TOTAL,
584 FP_CRTC,
585 FP_SYNC_START,
586 FP_SYNC_END,
587 FP_VALID_START,
588 FP_VALID_END
589};
590
591struct nv04_crtc_reg {
592 unsigned char MiscOutReg;
593 uint8_t CRTC[0xa0];
594 uint8_t CR58[0x10];
595 uint8_t Sequencer[5];
596 uint8_t Graphics[9];
597 uint8_t Attribute[21];
598 unsigned char DAC[768];
599
600 /* PCRTC regs */
601 uint32_t fb_start;
602 uint32_t crtc_cfg;
603 uint32_t cursor_cfg;
604 uint32_t gpio_ext;
605 uint32_t crtc_830;
606 uint32_t crtc_834;
607 uint32_t crtc_850;
608 uint32_t crtc_eng_ctrl;
609
610 /* PRAMDAC regs */
611 uint32_t nv10_cursync;
612 struct nouveau_pll_vals pllvals;
613 uint32_t ramdac_gen_ctrl;
614 uint32_t ramdac_630;
615 uint32_t ramdac_634;
616 uint32_t tv_setup;
617 uint32_t tv_vtotal;
618 uint32_t tv_vskew;
619 uint32_t tv_vsync_delay;
620 uint32_t tv_htotal;
621 uint32_t tv_hskew;
622 uint32_t tv_hsync_delay;
623 uint32_t tv_hsync_delay2;
624 uint32_t fp_horiz_regs[7];
625 uint32_t fp_vert_regs[7];
626 uint32_t dither;
627 uint32_t fp_control;
628 uint32_t dither_regs[6];
629 uint32_t fp_debug_0;
630 uint32_t fp_debug_1;
631 uint32_t fp_debug_2;
632 uint32_t fp_margin_color;
633 uint32_t ramdac_8c0;
634 uint32_t ramdac_a20;
635 uint32_t ramdac_a24;
636 uint32_t ramdac_a34;
637 uint32_t ctv_regs[38];
638};
639
640struct nv04_output_reg {
641 uint32_t output;
642 int head;
643};
644
645struct nv04_mode_state {
646 struct nv04_crtc_reg crtc_reg[2];
647 uint32_t pllsel;
648 uint32_t sel_clk;
649};
650
651enum nouveau_card_type {
652 NV_04 = 0x04,
653 NV_10 = 0x10,
654 NV_20 = 0x20,
655 NV_30 = 0x30,
656 NV_40 = 0x40,
657 NV_50 = 0x50,
658 NV_C0 = 0xc0,
659 NV_D0 = 0xd0,
660 NV_E0 = 0xe0,
661};
662
663struct drm_nouveau_private {
664 struct drm_device *dev;
665 bool noaccel;
666
667 /* the card type, takes NV_* as values */
668 enum nouveau_card_type card_type;
669 /* exact chipset, derived from NV_PMC_BOOT_0 */
670 int chipset;
671 int flags;
672 u32 crystal;
673
674 void __iomem *mmio;
675
676 spinlock_t ramin_lock;
677 void __iomem *ramin;
678 u32 ramin_size;
679 u32 ramin_base;
680 bool ramin_available;
681 struct drm_mm ramin_heap;
682 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
683 struct list_head gpuobj_list;
684 struct list_head classes;
685
686 struct nouveau_bo *vga_ram;
687
688 /* interrupt handling */
689 void (*irq_handler[32])(struct drm_device *);
690 bool msi_enabled;
691
692 struct {
693 struct drm_global_reference mem_global_ref;
694 struct ttm_bo_global_ref bo_global_ref;
695 struct ttm_bo_device bdev;
696 atomic_t validate_sequence;
697 int (*move)(struct nouveau_channel *,
698 struct ttm_buffer_object *,
699 struct ttm_mem_reg *, struct ttm_mem_reg *);
700 } ttm;
701
702 struct {
703 spinlock_t lock;
704 struct drm_mm heap;
705 struct nouveau_bo *bo;
706 } fence;
707
708 struct {
709 spinlock_t lock;
710 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
711 } channels;
712
713 struct nouveau_engine engine;
714 struct nouveau_channel *channel;
715
716 /* For PFIFO and PGRAPH. */
717 spinlock_t context_switch_lock;
718
719 /* VM/PRAMIN flush, legacy PRAMIN aperture */
720 spinlock_t vm_lock;
721
722 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
723 struct nouveau_ramht *ramht;
724 struct nouveau_gpuobj *ramfc;
725 struct nouveau_gpuobj *ramro;
726
727 uint32_t ramin_rsvd_vram;
728
729 struct {
730 enum {
731 NOUVEAU_GART_NONE = 0,
732 NOUVEAU_GART_AGP, /* AGP */
733 NOUVEAU_GART_PDMA, /* paged dma object */
734 NOUVEAU_GART_HW /* on-chip gart/vm */
735 } type;
736 uint64_t aper_base;
737 uint64_t aper_size;
738 uint64_t aper_free;
739
740 struct ttm_backend_func *func;
741
742 struct {
743 struct page *page;
744 dma_addr_t addr;
745 } dummy;
746
747 struct nouveau_gpuobj *sg_ctxdma;
748 } gart_info;
749
750 /* nv10-nv40 tiling regions */
751 struct {
752 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
753 spinlock_t lock;
754 } tile;
755
756 /* VRAM/fb configuration */
757 enum {
758 NV_MEM_TYPE_UNKNOWN = 0,
759 NV_MEM_TYPE_STOLEN,
760 NV_MEM_TYPE_SGRAM,
761 NV_MEM_TYPE_SDRAM,
762 NV_MEM_TYPE_DDR1,
763 NV_MEM_TYPE_DDR2,
764 NV_MEM_TYPE_DDR3,
765 NV_MEM_TYPE_GDDR2,
766 NV_MEM_TYPE_GDDR3,
767 NV_MEM_TYPE_GDDR4,
768 NV_MEM_TYPE_GDDR5
769 } vram_type;
770 uint64_t vram_size;
771 uint64_t vram_sys_base;
772 bool vram_rank_B;
773
774 uint64_t fb_available_size;
775 uint64_t fb_mappable_pages;
776 uint64_t fb_aper_free;
777 int fb_mtrr;
778
779 /* BAR control (NV50-) */
780 struct nouveau_vm *bar1_vm;
781 struct nouveau_vm *bar3_vm;
782
783 /* G8x/G9x virtual address space */
784 struct nouveau_vm *chan_vm;
785
786 struct nvbios vbios;
787 u8 *mxms;
788 struct list_head i2c_ports;
789
790 struct nv04_mode_state mode_reg;
791 struct nv04_mode_state saved_reg;
792 uint32_t saved_vga_font[4][16384];
793 uint32_t crtc_owner;
794 uint32_t dac_users[4];
795
796 struct backlight_device *backlight;
797
798 struct {
799 struct dentry *channel_root;
800 } debugfs;
801
802 struct nouveau_fbdev *nfbdev;
803 struct apertures_struct *apertures;
804};
805
806static inline struct drm_nouveau_private *
807nouveau_private(struct drm_device *dev)
808{
809 return dev->dev_private;
810}
811
812static inline struct drm_nouveau_private *
813nouveau_bdev(struct ttm_bo_device *bd)
814{
815 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
816}
817
818static inline int
819nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
820{
821 struct nouveau_bo *prev;
822
823 if (!pnvbo)
824 return -EINVAL;
825 prev = *pnvbo;
826
827 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
828 if (prev) {
829 struct ttm_buffer_object *bo = &prev->bo;
830
831 ttm_bo_unref(&bo);
832 }
833
834 return 0;
835}
836
837/* nouveau_drv.c */
838extern int nouveau_modeset;
839extern int nouveau_agpmode;
840extern int nouveau_duallink;
841extern int nouveau_uscript_lvds;
842extern int nouveau_uscript_tmds;
843extern int nouveau_vram_pushbuf;
844extern int nouveau_vram_notify;
845extern char *nouveau_vram_type;
846extern int nouveau_fbpercrtc;
847extern int nouveau_tv_disable;
848extern char *nouveau_tv_norm;
849extern int nouveau_reg_debug;
850extern char *nouveau_vbios;
851extern int nouveau_ignorelid;
852extern int nouveau_nofbaccel;
853extern int nouveau_noaccel;
854extern int nouveau_force_post;
855extern int nouveau_override_conntype;
856extern char *nouveau_perflvl;
857extern int nouveau_perflvl_wr;
858extern int nouveau_msi;
859extern int nouveau_ctxfw;
860extern int nouveau_mxmdcb;
861
862extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
863extern int nouveau_pci_resume(struct pci_dev *pdev);
864
865/* nouveau_state.c */
866extern int nouveau_open(struct drm_device *, struct drm_file *);
867extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
868extern void nouveau_postclose(struct drm_device *, struct drm_file *);
869extern int nouveau_load(struct drm_device *, unsigned long flags);
870extern int nouveau_firstopen(struct drm_device *);
871extern void nouveau_lastclose(struct drm_device *);
872extern int nouveau_unload(struct drm_device *);
873extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
874 struct drm_file *);
875extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
876 struct drm_file *);
877extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
878 uint32_t reg, uint32_t mask, uint32_t val);
879extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
880 uint32_t reg, uint32_t mask, uint32_t val);
881extern bool nouveau_wait_cb(struct drm_device *, u64 timeout,
882 bool (*cond)(void *), void *);
883extern bool nouveau_wait_for_idle(struct drm_device *);
884extern int nouveau_card_init(struct drm_device *);
885
886/* nouveau_mem.c */
887extern int nouveau_mem_vram_init(struct drm_device *);
888extern void nouveau_mem_vram_fini(struct drm_device *);
889extern int nouveau_mem_gart_init(struct drm_device *);
890extern void nouveau_mem_gart_fini(struct drm_device *);
891extern int nouveau_mem_init_agp(struct drm_device *);
892extern int nouveau_mem_reset_agp(struct drm_device *);
893extern void nouveau_mem_close(struct drm_device *);
894extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
895extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
896 struct nouveau_pm_memtiming *);
897extern void nouveau_mem_timing_read(struct drm_device *,
898 struct nouveau_pm_memtiming *);
899extern int nouveau_mem_vbios_type(struct drm_device *);
900extern struct nouveau_tile_reg *nv10_mem_set_tiling(
901 struct drm_device *dev, uint32_t addr, uint32_t size,
902 uint32_t pitch, uint32_t flags);
903extern void nv10_mem_put_tile_region(struct drm_device *dev,
904 struct nouveau_tile_reg *tile,
905 struct nouveau_fence *fence);
906extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
907extern const struct ttm_mem_type_manager_func nouveau_gart_manager;
908
909/* nouveau_notifier.c */
910extern int nouveau_notifier_init_channel(struct nouveau_channel *);
911extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
912extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
913 int cout, uint32_t start, uint32_t end,
914 uint32_t *offset);
915extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
916extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
917 struct drm_file *);
918extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
919 struct drm_file *);
920
921/* nouveau_channel.c */
922extern struct drm_ioctl_desc nouveau_ioctls[];
923extern int nouveau_max_ioctl;
924extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
925extern int nouveau_channel_alloc(struct drm_device *dev,
926 struct nouveau_channel **chan,
927 struct drm_file *file_priv,
928 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
929extern struct nouveau_channel *
930nouveau_channel_get_unlocked(struct nouveau_channel *);
931extern struct nouveau_channel *
932nouveau_channel_get(struct drm_file *, int id);
933extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
934extern void nouveau_channel_put(struct nouveau_channel **);
935extern void nouveau_channel_ref(struct nouveau_channel *chan,
936 struct nouveau_channel **pchan);
937extern int nouveau_channel_idle(struct nouveau_channel *chan);
938
939/* nouveau_object.c */
940#define NVOBJ_ENGINE_ADD(d, e, p) do { \
941 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
942 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
943} while (0)
944
945#define NVOBJ_ENGINE_DEL(d, e) do { \
946 struct drm_nouveau_private *dev_priv = (d)->dev_private; \
947 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
948} while (0)
949
950#define NVOBJ_CLASS(d, c, e) do { \
951 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
952 if (ret) \
953 return ret; \
954} while (0)
955
956#define NVOBJ_MTHD(d, c, m, e) do { \
957 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
958 if (ret) \
959 return ret; \
960} while (0)
961
962extern int nouveau_gpuobj_early_init(struct drm_device *);
963extern int nouveau_gpuobj_init(struct drm_device *);
964extern void nouveau_gpuobj_takedown(struct drm_device *);
965extern int nouveau_gpuobj_suspend(struct drm_device *dev);
966extern void nouveau_gpuobj_resume(struct drm_device *dev);
967extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
968extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
969 int (*exec)(struct nouveau_channel *,
970 u32 class, u32 mthd, u32 data));
971extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
972extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
973extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
974 uint32_t vram_h, uint32_t tt_h);
975extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
976extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
977 uint32_t size, int align, uint32_t flags,
978 struct nouveau_gpuobj **);
979extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
980 struct nouveau_gpuobj **);
981extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
982 u32 size, u32 flags,
983 struct nouveau_gpuobj **);
984extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
985 uint64_t offset, uint64_t size, int access,
986 int target, struct nouveau_gpuobj **);
987extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
988extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
989 u64 size, int target, int access, u32 type,
990 u32 comp, struct nouveau_gpuobj **pobj);
991extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
992 int class, u64 base, u64 size, int target,
993 int access, u32 type, u32 comp);
994extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
995 struct drm_file *);
996extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
997 struct drm_file *);
998
999/* nouveau_irq.c */
1000extern int nouveau_irq_init(struct drm_device *);
1001extern void nouveau_irq_fini(struct drm_device *);
1002extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
1003extern void nouveau_irq_register(struct drm_device *, int status_bit,
1004 void (*)(struct drm_device *));
1005extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
1006extern void nouveau_irq_preinstall(struct drm_device *);
1007extern int nouveau_irq_postinstall(struct drm_device *);
1008extern void nouveau_irq_uninstall(struct drm_device *);
1009
1010/* nouveau_sgdma.c */
1011extern int nouveau_sgdma_init(struct drm_device *);
1012extern void nouveau_sgdma_takedown(struct drm_device *);
1013extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
1014 uint32_t offset);
1015extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev,
1016 unsigned long size,
1017 uint32_t page_flags,
1018 struct page *dummy_read_page);
1019
1020/* nouveau_debugfs.c */
1021#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
1022extern int nouveau_debugfs_init(struct drm_minor *);
1023extern void nouveau_debugfs_takedown(struct drm_minor *);
1024extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
1025extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
1026#else
1027static inline int
1028nouveau_debugfs_init(struct drm_minor *minor)
1029{
1030 return 0;
1031}
1032
1033static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
1034{
1035}
1036
1037static inline int
1038nouveau_debugfs_channel_init(struct nouveau_channel *chan)
1039{
1040 return 0;
1041}
1042
1043static inline void
1044nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
1045{
1046}
1047#endif
1048
1049/* nouveau_dma.c */
1050extern void nouveau_dma_init(struct nouveau_channel *);
1051extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
1052
1053/* nouveau_acpi.c */
1054#define ROM_BIOS_PAGE 4096
1055#if defined(CONFIG_ACPI)
1056void nouveau_register_dsm_handler(void);
1057void nouveau_unregister_dsm_handler(void);
1058void nouveau_switcheroo_optimus_dsm(void);
1059int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
1060bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
1061int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
1062#else
1063static inline void nouveau_register_dsm_handler(void) {}
1064static inline void nouveau_unregister_dsm_handler(void) {}
1065static inline void nouveau_switcheroo_optimus_dsm(void) {}
1066static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
1067static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
1068static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
1069#endif
1070
1071/* nouveau_backlight.c */
1072#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1073extern int nouveau_backlight_init(struct drm_device *);
1074extern void nouveau_backlight_exit(struct drm_device *);
1075#else
1076static inline int nouveau_backlight_init(struct drm_device *dev)
1077{
1078 return 0;
1079}
1080
1081static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1082#endif
1083
1084/* nouveau_bios.c */
1085extern int nouveau_bios_init(struct drm_device *);
1086extern void nouveau_bios_takedown(struct drm_device *dev);
1087extern int nouveau_run_vbios_init(struct drm_device *);
1088extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1089 struct dcb_entry *, int crtc);
1090extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table);
1091extern struct dcb_connector_table_entry *
1092nouveau_bios_connector_entry(struct drm_device *, int index);
1093extern u32 get_pll_register(struct drm_device *, enum pll_types);
1094extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1095 struct pll_lims *);
1096extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
1097 struct dcb_entry *, int crtc);
1098extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1099extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1100extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1101 bool *dl, bool *if_is_24bit);
1102extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1103 int head, int pxclk);
1104extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1105 enum LVDS_script, int pxclk);
1106bool bios_encoder_match(struct dcb_entry *, u32 hash);
1107
1108/* nouveau_mxm.c */
1109int nouveau_mxm_init(struct drm_device *dev);
1110void nouveau_mxm_fini(struct drm_device *dev);
1111
1112/* nouveau_ttm.c */
1113int nouveau_ttm_global_init(struct drm_nouveau_private *);
1114void nouveau_ttm_global_release(struct drm_nouveau_private *);
1115int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1116
1117/* nouveau_hdmi.c */
1118void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
1119
1120/* nv04_fb.c */
1121extern int nv04_fb_vram_init(struct drm_device *);
1122extern int nv04_fb_init(struct drm_device *);
1123extern void nv04_fb_takedown(struct drm_device *);
1124
1125/* nv10_fb.c */
1126extern int nv10_fb_vram_init(struct drm_device *dev);
1127extern int nv1a_fb_vram_init(struct drm_device *dev);
1128extern int nv10_fb_init(struct drm_device *);
1129extern void nv10_fb_takedown(struct drm_device *);
1130extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1131 uint32_t addr, uint32_t size,
1132 uint32_t pitch, uint32_t flags);
1133extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1134extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
1135
1136/* nv20_fb.c */
1137extern int nv20_fb_vram_init(struct drm_device *dev);
1138extern int nv20_fb_init(struct drm_device *);
1139extern void nv20_fb_takedown(struct drm_device *);
1140extern void nv20_fb_init_tile_region(struct drm_device *dev, int i,
1141 uint32_t addr, uint32_t size,
1142 uint32_t pitch, uint32_t flags);
1143extern void nv20_fb_set_tile_region(struct drm_device *dev, int i);
1144extern void nv20_fb_free_tile_region(struct drm_device *dev, int i);
1145
1146/* nv30_fb.c */
1147extern int nv30_fb_init(struct drm_device *);
1148extern void nv30_fb_takedown(struct drm_device *);
1149extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1150 uint32_t addr, uint32_t size,
1151 uint32_t pitch, uint32_t flags);
1152extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
1153
1154/* nv40_fb.c */
1155extern int nv40_fb_vram_init(struct drm_device *dev);
1156extern int nv40_fb_init(struct drm_device *);
1157extern void nv40_fb_takedown(struct drm_device *);
1158extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1159
1160/* nv50_fb.c */
1161extern int nv50_fb_init(struct drm_device *);
1162extern void nv50_fb_takedown(struct drm_device *);
1163extern void nv50_fb_vm_trap(struct drm_device *, int display);
1164
1165/* nvc0_fb.c */
1166extern int nvc0_fb_init(struct drm_device *);
1167extern void nvc0_fb_takedown(struct drm_device *);
1168
1169/* nv04_graph.c */
1170extern int nv04_graph_create(struct drm_device *);
1171extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
1172extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1173 u32 class, u32 mthd, u32 data);
1174extern struct nouveau_bitfield nv04_graph_nsource[];
1175
1176/* nv10_graph.c */
1177extern int nv10_graph_create(struct drm_device *);
1178extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1179extern struct nouveau_bitfield nv10_graph_intr[];
1180extern struct nouveau_bitfield nv10_graph_nstatus[];
1181
1182/* nv20_graph.c */
1183extern int nv20_graph_create(struct drm_device *);
1184
1185/* nv40_graph.c */
1186extern int nv40_graph_create(struct drm_device *);
1187extern void nv40_grctx_init(struct drm_device *, u32 *size);
1188extern void nv40_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
1189
1190/* nv50_graph.c */
1191extern int nv50_graph_create(struct drm_device *);
1192extern struct nouveau_enum nv50_data_error_names[];
1193extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
1194extern int nv50_grctx_init(struct drm_device *, u32 *, u32, u32 *, u32 *);
1195extern void nv50_grctx_fill(struct drm_device *, struct nouveau_gpuobj *);
1196
1197/* nvc0_graph.c */
1198extern int nvc0_graph_create(struct drm_device *);
1199extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
1200
1201/* nve0_graph.c */
1202extern int nve0_graph_create(struct drm_device *);
1203
1204/* nv84_crypt.c */
1205extern int nv84_crypt_create(struct drm_device *);
1206
1207/* nv98_crypt.c */
1208extern int nv98_crypt_create(struct drm_device *dev);
1209
1210/* nva3_copy.c */
1211extern int nva3_copy_create(struct drm_device *dev);
1212
1213/* nvc0_copy.c */
1214extern int nvc0_copy_create(struct drm_device *dev, int engine);
1215
1216/* nv31_mpeg.c */
1217extern int nv31_mpeg_create(struct drm_device *dev);
1218
1219/* nv50_mpeg.c */
1220extern int nv50_mpeg_create(struct drm_device *dev);
1221
1222/* nv84_bsp.c */
1223/* nv98_bsp.c */
1224extern int nv84_bsp_create(struct drm_device *dev);
1225
1226/* nv84_vp.c */
1227/* nv98_vp.c */
1228extern int nv84_vp_create(struct drm_device *dev);
1229
1230/* nv98_ppp.c */
1231extern int nv98_ppp_create(struct drm_device *dev);
1232
1233/* nv04_instmem.c */
1234extern int nv04_instmem_init(struct drm_device *);
1235extern void nv04_instmem_takedown(struct drm_device *);
1236extern int nv04_instmem_suspend(struct drm_device *);
1237extern void nv04_instmem_resume(struct drm_device *);
1238extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1239 u32 size, u32 align);
1240extern void nv04_instmem_put(struct nouveau_gpuobj *);
1241extern int nv04_instmem_map(struct nouveau_gpuobj *);
1242extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
1243extern void nv04_instmem_flush(struct drm_device *);
1244
1245/* nv50_instmem.c */
1246extern int nv50_instmem_init(struct drm_device *);
1247extern void nv50_instmem_takedown(struct drm_device *);
1248extern int nv50_instmem_suspend(struct drm_device *);
1249extern void nv50_instmem_resume(struct drm_device *);
1250extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *,
1251 u32 size, u32 align);
1252extern void nv50_instmem_put(struct nouveau_gpuobj *);
1253extern int nv50_instmem_map(struct nouveau_gpuobj *);
1254extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
1255extern void nv50_instmem_flush(struct drm_device *);
1256extern void nv84_instmem_flush(struct drm_device *);
1257
1258/* nvc0_instmem.c */
1259extern int nvc0_instmem_init(struct drm_device *);
1260extern void nvc0_instmem_takedown(struct drm_device *);
1261extern int nvc0_instmem_suspend(struct drm_device *);
1262extern void nvc0_instmem_resume(struct drm_device *);
1263
1264/* nv04_mc.c */
1265extern int nv04_mc_init(struct drm_device *);
1266extern void nv04_mc_takedown(struct drm_device *);
1267
1268/* nv40_mc.c */
1269extern int nv40_mc_init(struct drm_device *);
1270extern void nv40_mc_takedown(struct drm_device *);
1271
1272/* nv50_mc.c */
1273extern int nv50_mc_init(struct drm_device *);
1274extern void nv50_mc_takedown(struct drm_device *);
1275
1276/* nv04_timer.c */
1277extern int nv04_timer_init(struct drm_device *);
1278extern uint64_t nv04_timer_read(struct drm_device *);
1279extern void nv04_timer_takedown(struct drm_device *);
1280
1281extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1282 unsigned long arg);
1283
1284/* nv04_dac.c */
1285extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1286extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1287extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1288extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1289extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1290
1291/* nv04_dfp.c */
1292extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1293extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1294extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1295 int head, bool dl);
1296extern void nv04_dfp_disable(struct drm_device *dev, int head);
1297extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1298
1299/* nv04_tv.c */
1300extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1301extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1302
1303/* nv17_tv.c */
1304extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1305
1306/* nv04_display.c */
1307extern int nv04_display_early_init(struct drm_device *);
1308extern void nv04_display_late_takedown(struct drm_device *);
1309extern int nv04_display_create(struct drm_device *);
1310extern void nv04_display_destroy(struct drm_device *);
1311extern int nv04_display_init(struct drm_device *);
1312extern void nv04_display_fini(struct drm_device *);
1313
1314/* nvd0_display.c */
1315extern int nvd0_display_create(struct drm_device *);
1316extern void nvd0_display_destroy(struct drm_device *);
1317extern int nvd0_display_init(struct drm_device *);
1318extern void nvd0_display_fini(struct drm_device *);
1319struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
1320void nvd0_display_flip_stop(struct drm_crtc *);
1321int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
1322 struct nouveau_channel *, u32 swap_interval);
1323
1324/* nv04_crtc.c */
1325extern int nv04_crtc_create(struct drm_device *, int index);
1326
1327/* nouveau_bo.c */
1328extern struct ttm_bo_driver nouveau_bo_driver;
1329extern void nouveau_bo_move_init(struct nouveau_channel *);
1330extern int nouveau_bo_new(struct drm_device *, int size, int align,
1331 uint32_t flags, uint32_t tile_mode,
1332 uint32_t tile_flags,
1333 struct sg_table *sg,
1334 struct nouveau_bo **);
1335extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1336extern int nouveau_bo_unpin(struct nouveau_bo *);
1337extern int nouveau_bo_map(struct nouveau_bo *);
1338extern void nouveau_bo_unmap(struct nouveau_bo *);
1339extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1340 uint32_t busy);
1341extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1342extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1343extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1344extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1345extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
1346extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1347 bool no_wait_reserve, bool no_wait_gpu);
1348
1349extern struct nouveau_vma *
1350nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *);
1351extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *,
1352 struct nouveau_vma *);
1353extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *);
1354
1355/* nouveau_gem.c */
1356extern int nouveau_gem_new(struct drm_device *, int size, int align,
1357 uint32_t domain, uint32_t tile_mode,
1358 uint32_t tile_flags, struct nouveau_bo **);
1359extern int nouveau_gem_object_new(struct drm_gem_object *);
1360extern void nouveau_gem_object_del(struct drm_gem_object *);
1361extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *);
1362extern void nouveau_gem_object_close(struct drm_gem_object *,
1363 struct drm_file *);
1364extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1365 struct drm_file *);
1366extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1367 struct drm_file *);
1368extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1369 struct drm_file *);
1370extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1371 struct drm_file *);
1372extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1373 struct drm_file *);
1374
1375extern struct dma_buf *nouveau_gem_prime_export(struct drm_device *dev,
1376 struct drm_gem_object *obj, int flags);
1377extern struct drm_gem_object *nouveau_gem_prime_import(struct drm_device *dev,
1378 struct dma_buf *dma_buf);
1379
1380/* nouveau_display.c */
1381int nouveau_display_create(struct drm_device *dev);
1382void nouveau_display_destroy(struct drm_device *dev);
1383int nouveau_display_init(struct drm_device *dev);
1384void nouveau_display_fini(struct drm_device *dev);
1385int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1386void nouveau_vblank_disable(struct drm_device *dev, int crtc);
1387int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1388 struct drm_pending_vblank_event *event);
1389int nouveau_finish_page_flip(struct nouveau_channel *,
1390 struct nouveau_page_flip_state *);
1391int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
1392 struct drm_mode_create_dumb *args);
1393int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
1394 uint32_t handle, uint64_t *offset);
1395int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
1396 uint32_t handle);
1397
1398/* nv10_gpio.c */
1399int nv10_gpio_init(struct drm_device *dev);
1400void nv10_gpio_fini(struct drm_device *dev);
1401int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1402int nv10_gpio_sense(struct drm_device *dev, int line);
1403void nv10_gpio_irq_enable(struct drm_device *, int line, bool on);
1404
1405/* nv50_gpio.c */
1406int nv50_gpio_init(struct drm_device *dev);
1407void nv50_gpio_fini(struct drm_device *dev);
1408int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1409int nv50_gpio_sense(struct drm_device *dev, int line);
1410void nv50_gpio_irq_enable(struct drm_device *, int line, bool on);
1411int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out);
1412int nvd0_gpio_sense(struct drm_device *dev, int line);
1413
1414/* nv50_calc.c */
1415int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1416 int *N1, int *M1, int *N2, int *M2, int *P);
1417int nva3_calc_pll(struct drm_device *, struct pll_lims *,
1418 int clk, int *N, int *fN, int *M, int *P);
1419
1420#ifndef ioread32_native
1421#ifdef __BIG_ENDIAN
1422#define ioread16_native ioread16be
1423#define iowrite16_native iowrite16be
1424#define ioread32_native ioread32be
1425#define iowrite32_native iowrite32be
1426#else /* def __BIG_ENDIAN */
1427#define ioread16_native ioread16
1428#define iowrite16_native iowrite16
1429#define ioread32_native ioread32
1430#define iowrite32_native iowrite32
1431#endif /* def __BIG_ENDIAN else */
1432#endif /* !ioread32_native */
1433
1434/* channel control reg access */
1435static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1436{
1437 return ioread32_native(chan->user + reg);
1438}
1439
1440static inline void nvchan_wr32(struct nouveau_channel *chan,
1441 unsigned reg, u32 val)
1442{
1443 iowrite32_native(val, chan->user + reg);
1444}
1445
1446/* register access */
1447static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1448{
1449 struct drm_nouveau_private *dev_priv = dev->dev_private;
1450 return ioread32_native(dev_priv->mmio + reg);
1451}
1452
1453static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1454{
1455 struct drm_nouveau_private *dev_priv = dev->dev_private;
1456 iowrite32_native(val, dev_priv->mmio + reg);
1457}
1458
1459static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1460{
1461 u32 tmp = nv_rd32(dev, reg);
1462 nv_wr32(dev, reg, (tmp & ~mask) | val);
1463 return tmp;
1464}
1465
1466static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1467{
1468 struct drm_nouveau_private *dev_priv = dev->dev_private;
1469 return ioread8(dev_priv->mmio + reg);
1470}
1471
1472static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1473{
1474 struct drm_nouveau_private *dev_priv = dev->dev_private;
1475 iowrite8(val, dev_priv->mmio + reg);
1476}
1477
1478#define nv_wait(dev, reg, mask, val) \
1479 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1480#define nv_wait_ne(dev, reg, mask, val) \
1481 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
1482#define nv_wait_cb(dev, func, data) \
1483 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
1484
1485/* PRAMIN access */
1486static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1487{
1488 struct drm_nouveau_private *dev_priv = dev->dev_private;
1489 return ioread32_native(dev_priv->ramin + offset);
1490}
1491
1492static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1493{
1494 struct drm_nouveau_private *dev_priv = dev->dev_private;
1495 iowrite32_native(val, dev_priv->ramin + offset);
1496}
1497
1498/* object access */
1499extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1500extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1501
1502/*
1503 * Logging
1504 * Argument d is (struct drm_device *).
1505 */
1506#define NV_PRINTK(level, d, fmt, arg...) \
1507 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1508 pci_name(d->pdev), ##arg)
1509#ifndef NV_DEBUG_NOTRACE
1510#define NV_DEBUG(d, fmt, arg...) do { \
1511 if (drm_debug & DRM_UT_DRIVER) { \
1512 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1513 __LINE__, ##arg); \
1514 } \
1515} while (0)
1516#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1517 if (drm_debug & DRM_UT_KMS) { \
1518 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1519 __LINE__, ##arg); \
1520 } \
1521} while (0)
1522#else
1523#define NV_DEBUG(d, fmt, arg...) do { \
1524 if (drm_debug & DRM_UT_DRIVER) \
1525 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1526} while (0)
1527#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1528 if (drm_debug & DRM_UT_KMS) \
1529 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1530} while (0)
1531#endif
1532#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1533#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1534#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1535#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1536#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1537#define NV_WARNONCE(d, fmt, arg...) do { \
1538 static int _warned = 0; \
1539 if (!_warned) { \
1540 NV_WARN(d, fmt, ##arg); \
1541 _warned = 1; \
1542 } \
1543} while(0)
1544
1545/* nouveau_reg_debug bitmask */
1546enum {
1547 NOUVEAU_REG_DEBUG_MC = 0x1,
1548 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1549 NOUVEAU_REG_DEBUG_FB = 0x4,
1550 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1551 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1552 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1553 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1554 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1555 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1556 NOUVEAU_REG_DEBUG_EVO = 0x200,
1557 NOUVEAU_REG_DEBUG_AUXCH = 0x400
1558};
1559
1560#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1561 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1562 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1563} while (0)
1564
1565static inline bool
1566nv_two_heads(struct drm_device *dev)
1567{
1568 struct drm_nouveau_private *dev_priv = dev->dev_private;
1569 const int impl = dev->pci_device & 0x0ff0;
1570
1571 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1572 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1573 return true;
1574
1575 return false;
1576}
1577
1578static inline bool
1579nv_gf4_disp_arch(struct drm_device *dev)
1580{
1581 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1582}
1583
1584static inline bool
1585nv_two_reg_pll(struct drm_device *dev)
1586{
1587 struct drm_nouveau_private *dev_priv = dev->dev_private;
1588 const int impl = dev->pci_device & 0x0ff0;
1589
1590 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1591 return true;
1592 return false;
1593}
1594
1595static inline bool
1596nv_match_device(struct drm_device *dev, unsigned device,
1597 unsigned sub_vendor, unsigned sub_device)
1598{
1599 return dev->pdev->device == device &&
1600 dev->pdev->subsystem_vendor == sub_vendor &&
1601 dev->pdev->subsystem_device == sub_device;
1602}
1603
1604static inline void *
1605nv_engine(struct drm_device *dev, int engine)
1606{
1607 struct drm_nouveau_private *dev_priv = dev->dev_private;
1608 return (void *)dev_priv->eng[engine];
1609}
1610
1611/* returns 1 if device is one of the nv4x using the 0x4497 object class,
1612 * helpful to determine a number of other hardware features
1613 */
1614static inline int
1615nv44_graph_class(struct drm_device *dev)
1616{
1617 struct drm_nouveau_private *dev_priv = dev->dev_private;
1618
1619 if ((dev_priv->chipset & 0xf0) == 0x60)
1620 return 1;
1621
1622 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
1623}
1624
1625/* memory type/access flags, do not match hardware values */
1626#define NV_MEM_ACCESS_RO 1
1627#define NV_MEM_ACCESS_WO 2
1628#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
1629#define NV_MEM_ACCESS_SYS 4
1630#define NV_MEM_ACCESS_VM 8
1631#define NV_MEM_ACCESS_NOSNOOP 16
1632
1633#define NV_MEM_TARGET_VRAM 0
1634#define NV_MEM_TARGET_PCI 1
1635#define NV_MEM_TARGET_PCI_NOSNOOP 2
1636#define NV_MEM_TARGET_VM 3
1637#define NV_MEM_TARGET_GART 4
1638
1639#define NV_MEM_TYPE_VM 0x7f
1640#define NV_MEM_COMP_VM 0x03
1641
1642/* FIFO methods */
1643#define NV01_SUBCHAN_OBJECT 0x00000000
1644#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
1645#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
1646#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
1647#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
1648#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
1649#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
1650#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
1651#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
1652#define NV84_SUBCHAN_NOTIFY_INTR 0x00000020
1653#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
1654#define NV10_SUBCHAN_REF_CNT 0x00000050
1655#define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
1656#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
1657#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
1658#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
1659#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
1660#define NV40_SUBCHAN_YIELD 0x00000080
1661
1662/* NV_SW object class */
1663#define NV_SW 0x0000506e
1664#define NV_SW_DMA_VBLSEM 0x0000018c
1665#define NV_SW_VBLSEM_OFFSET 0x00000400
1666#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1667#define NV_SW_VBLSEM_RELEASE 0x00000408
1668#define NV_SW_PAGE_FLIP 0x00000500
1669
1670#endif /* __NOUVEAU_DRV_H__ */