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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include <linux/dma-buf.h>
24#include <linux/list.h>
25#include <linux/pagemap.h>
26#include <linux/sched/mm.h>
27#include <linux/sched/task.h>
28#include <linux/fdtable.h>
29#include <drm/ttm/ttm_tt.h>
30
31#include <drm/drm_exec.h>
32
33#include "amdgpu_object.h"
34#include "amdgpu_gem.h"
35#include "amdgpu_vm.h"
36#include "amdgpu_hmm.h"
37#include "amdgpu_amdkfd.h"
38#include "amdgpu_dma_buf.h"
39#include <uapi/linux/kfd_ioctl.h>
40#include "amdgpu_xgmi.h"
41#include "kfd_priv.h"
42#include "kfd_smi_events.h"
43
44/* Userptr restore delay, just long enough to allow consecutive VM
45 * changes to accumulate
46 */
47#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
48#define AMDGPU_RESERVE_MEM_LIMIT (3UL << 29)
49
50/*
51 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
52 * BO chunk
53 */
54#define VRAM_AVAILABLITY_ALIGN (1 << 21)
55
56/* Impose limit on how much memory KFD can use */
57static struct {
58 uint64_t max_system_mem_limit;
59 uint64_t max_ttm_mem_limit;
60 int64_t system_mem_used;
61 int64_t ttm_mem_used;
62 spinlock_t mem_limit_lock;
63} kfd_mem_limit;
64
65static const char * const domain_bit_to_string[] = {
66 "CPU",
67 "GTT",
68 "VRAM",
69 "GDS",
70 "GWS",
71 "OA"
72};
73
74#define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
75
76static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
77
78static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
79 struct kgd_mem *mem)
80{
81 struct kfd_mem_attachment *entry;
82
83 list_for_each_entry(entry, &mem->attachments, list)
84 if (entry->bo_va->base.vm == avm)
85 return true;
86
87 return false;
88}
89
90/**
91 * reuse_dmamap() - Check whether adev can share the original
92 * userptr BO
93 *
94 * If both adev and bo_adev are in direct mapping or
95 * in the same iommu group, they can share the original BO.
96 *
97 * @adev: Device to which can or cannot share the original BO
98 * @bo_adev: Device to which allocated BO belongs to
99 *
100 * Return: returns true if adev can share original userptr BO,
101 * false otherwise.
102 */
103static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
104{
105 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
106 (adev->dev->iommu_group == bo_adev->dev->iommu_group);
107}
108
109/* Set memory usage limits. Current, limits are
110 * System (TTM + userptr) memory - 15/16th System RAM
111 * TTM memory - 3/8th System RAM
112 */
113void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
114{
115 struct sysinfo si;
116 uint64_t mem;
117
118 if (kfd_mem_limit.max_system_mem_limit)
119 return;
120
121 si_meminfo(&si);
122 mem = si.totalram - si.totalhigh;
123 mem *= si.mem_unit;
124
125 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
126 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6);
127 if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT)
128 kfd_mem_limit.max_system_mem_limit >>= 1;
129 else
130 kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT;
131
132 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
133 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
134 (kfd_mem_limit.max_system_mem_limit >> 20),
135 (kfd_mem_limit.max_ttm_mem_limit >> 20));
136}
137
138void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
139{
140 kfd_mem_limit.system_mem_used += size;
141}
142
143/* Estimate page table size needed to represent a given memory size
144 *
145 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
146 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
147 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
148 * for 2MB pages for TLB efficiency. However, small allocations and
149 * fragmented system memory still need some 4KB pages. We choose a
150 * compromise that should work in most cases without reserving too
151 * much memory for page tables unnecessarily (factor 16K, >> 14).
152 */
153
154#define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
155
156/**
157 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
158 * of buffer.
159 *
160 * @adev: Device to which allocated BO belongs to
161 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
162 * equivalent to amdgpu_bo_size(BO)
163 * @alloc_flag: Flag used in allocating a BO as noted above
164 * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
165 * managed as one compute node in driver for app
166 *
167 * Return:
168 * returns -ENOMEM in case of error, ZERO otherwise
169 */
170int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
171 uint64_t size, u32 alloc_flag, int8_t xcp_id)
172{
173 uint64_t reserved_for_pt =
174 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
175 size_t system_mem_needed, ttm_mem_needed, vram_needed;
176 int ret = 0;
177 uint64_t vram_size = 0;
178
179 system_mem_needed = 0;
180 ttm_mem_needed = 0;
181 vram_needed = 0;
182 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
183 system_mem_needed = size;
184 ttm_mem_needed = size;
185 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
186 /*
187 * Conservatively round up the allocation requirement to 2 MB
188 * to avoid fragmentation caused by 4K allocations in the tail
189 * 2M BO chunk.
190 */
191 vram_needed = size;
192 /*
193 * For GFX 9.4.3, get the VRAM size from XCP structs
194 */
195 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
196 return -EINVAL;
197
198 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
199 if (adev->gmc.is_app_apu) {
200 system_mem_needed = size;
201 ttm_mem_needed = size;
202 }
203 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
204 system_mem_needed = size;
205 } else if (!(alloc_flag &
206 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
207 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
208 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
209 return -ENOMEM;
210 }
211
212 spin_lock(&kfd_mem_limit.mem_limit_lock);
213
214 if (kfd_mem_limit.system_mem_used + system_mem_needed >
215 kfd_mem_limit.max_system_mem_limit)
216 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
217
218 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
219 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
220 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
221 kfd_mem_limit.max_ttm_mem_limit) ||
222 (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
223 vram_size - reserved_for_pt - atomic64_read(&adev->vram_pin_size))) {
224 ret = -ENOMEM;
225 goto release;
226 }
227
228 /* Update memory accounting by decreasing available system
229 * memory, TTM memory and GPU memory as computed above
230 */
231 WARN_ONCE(vram_needed && !adev,
232 "adev reference can't be null when vram is used");
233 if (adev && xcp_id >= 0) {
234 adev->kfd.vram_used[xcp_id] += vram_needed;
235 adev->kfd.vram_used_aligned[xcp_id] += adev->gmc.is_app_apu ?
236 vram_needed :
237 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
238 }
239 kfd_mem_limit.system_mem_used += system_mem_needed;
240 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
241
242release:
243 spin_unlock(&kfd_mem_limit.mem_limit_lock);
244 return ret;
245}
246
247void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
248 uint64_t size, u32 alloc_flag, int8_t xcp_id)
249{
250 spin_lock(&kfd_mem_limit.mem_limit_lock);
251
252 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
253 kfd_mem_limit.system_mem_used -= size;
254 kfd_mem_limit.ttm_mem_used -= size;
255 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
256 WARN_ONCE(!adev,
257 "adev reference can't be null when alloc mem flags vram is set");
258 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
259 goto release;
260
261 if (adev) {
262 adev->kfd.vram_used[xcp_id] -= size;
263 if (adev->gmc.is_app_apu) {
264 adev->kfd.vram_used_aligned[xcp_id] -= size;
265 kfd_mem_limit.system_mem_used -= size;
266 kfd_mem_limit.ttm_mem_used -= size;
267 } else {
268 adev->kfd.vram_used_aligned[xcp_id] -=
269 ALIGN(size, VRAM_AVAILABLITY_ALIGN);
270 }
271 }
272 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
273 kfd_mem_limit.system_mem_used -= size;
274 } else if (!(alloc_flag &
275 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
276 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
277 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
278 goto release;
279 }
280 WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
281 "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
282 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
283 "KFD TTM memory accounting unbalanced");
284 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
285 "KFD system memory accounting unbalanced");
286
287release:
288 spin_unlock(&kfd_mem_limit.mem_limit_lock);
289}
290
291void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
292{
293 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
294 u32 alloc_flags = bo->kfd_bo->alloc_flags;
295 u64 size = amdgpu_bo_size(bo);
296
297 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
298 bo->xcp_id);
299
300 kfree(bo->kfd_bo);
301}
302
303/**
304 * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
305 * about USERPTR or DOOREBELL or MMIO BO.
306 *
307 * @adev: Device for which dmamap BO is being created
308 * @mem: BO of peer device that is being DMA mapped. Provides parameters
309 * in building the dmamap BO
310 * @bo_out: Output parameter updated with handle of dmamap BO
311 */
312static int
313create_dmamap_sg_bo(struct amdgpu_device *adev,
314 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
315{
316 struct drm_gem_object *gem_obj;
317 int ret;
318 uint64_t flags = 0;
319
320 ret = amdgpu_bo_reserve(mem->bo, false);
321 if (ret)
322 return ret;
323
324 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
325 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
326 AMDGPU_GEM_CREATE_UNCACHED);
327
328 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
329 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
330 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
331
332 amdgpu_bo_unreserve(mem->bo);
333
334 if (ret) {
335 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
336 return -EINVAL;
337 }
338
339 *bo_out = gem_to_amdgpu_bo(gem_obj);
340 (*bo_out)->parent = amdgpu_bo_ref(mem->bo);
341 return ret;
342}
343
344/* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
345 * reservation object.
346 *
347 * @bo: [IN] Remove eviction fence(s) from this BO
348 * @ef: [IN] This eviction fence is removed if it
349 * is present in the shared list.
350 *
351 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
352 */
353static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
354 struct amdgpu_amdkfd_fence *ef)
355{
356 struct dma_fence *replacement;
357
358 if (!ef)
359 return -EINVAL;
360
361 /* TODO: Instead of block before we should use the fence of the page
362 * table update and TLB flush here directly.
363 */
364 replacement = dma_fence_get_stub();
365 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
366 replacement, DMA_RESV_USAGE_BOOKKEEP);
367 dma_fence_put(replacement);
368 return 0;
369}
370
371int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
372{
373 struct amdgpu_bo *root = bo;
374 struct amdgpu_vm_bo_base *vm_bo;
375 struct amdgpu_vm *vm;
376 struct amdkfd_process_info *info;
377 struct amdgpu_amdkfd_fence *ef;
378 int ret;
379
380 /* we can always get vm_bo from root PD bo.*/
381 while (root->parent)
382 root = root->parent;
383
384 vm_bo = root->vm_bo;
385 if (!vm_bo)
386 return 0;
387
388 vm = vm_bo->vm;
389 if (!vm)
390 return 0;
391
392 info = vm->process_info;
393 if (!info || !info->eviction_fence)
394 return 0;
395
396 ef = container_of(dma_fence_get(&info->eviction_fence->base),
397 struct amdgpu_amdkfd_fence, base);
398
399 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
400 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
401 dma_resv_unlock(bo->tbo.base.resv);
402
403 dma_fence_put(&ef->base);
404 return ret;
405}
406
407static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
408 bool wait)
409{
410 struct ttm_operation_ctx ctx = { false, false };
411 int ret;
412
413 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
414 "Called with userptr BO"))
415 return -EINVAL;
416
417 amdgpu_bo_placement_from_domain(bo, domain);
418
419 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
420 if (ret)
421 goto validate_fail;
422 if (wait)
423 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
424
425validate_fail:
426 return ret;
427}
428
429int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
430 uint32_t domain,
431 struct dma_fence *fence)
432{
433 int ret = amdgpu_bo_reserve(bo, false);
434
435 if (ret)
436 return ret;
437
438 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
439 if (ret)
440 goto unreserve_out;
441
442 ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
443 if (ret)
444 goto unreserve_out;
445
446 dma_resv_add_fence(bo->tbo.base.resv, fence,
447 DMA_RESV_USAGE_BOOKKEEP);
448
449unreserve_out:
450 amdgpu_bo_unreserve(bo);
451
452 return ret;
453}
454
455static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
456{
457 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
458}
459
460/* vm_validate_pt_pd_bos - Validate page table and directory BOs
461 *
462 * Page directories are not updated here because huge page handling
463 * during page table updates can invalidate page directory entries
464 * again. Page directories are only updated after updating page
465 * tables.
466 */
467static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm,
468 struct ww_acquire_ctx *ticket)
469{
470 struct amdgpu_bo *pd = vm->root.bo;
471 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
472 int ret;
473
474 ret = amdgpu_vm_validate(adev, vm, ticket,
475 amdgpu_amdkfd_validate_vm_bo, NULL);
476 if (ret) {
477 pr_err("failed to validate PT BOs\n");
478 return ret;
479 }
480
481 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
482
483 return 0;
484}
485
486static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
487{
488 struct amdgpu_bo *pd = vm->root.bo;
489 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
490 int ret;
491
492 ret = amdgpu_vm_update_pdes(adev, vm, false);
493 if (ret)
494 return ret;
495
496 return amdgpu_sync_fence(sync, vm->last_update);
497}
498
499static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
500{
501 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
502 AMDGPU_VM_MTYPE_DEFAULT;
503
504 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
505 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
506 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
507 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
508
509 return amdgpu_gem_va_map_flags(adev, mapping_flags);
510}
511
512/**
513 * create_sg_table() - Create an sg_table for a contiguous DMA addr range
514 * @addr: The starting address to point to
515 * @size: Size of memory area in bytes being pointed to
516 *
517 * Allocates an instance of sg_table and initializes it to point to memory
518 * area specified by input parameters. The address used to build is assumed
519 * to be DMA mapped, if needed.
520 *
521 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
522 * because they are physically contiguous.
523 *
524 * Return: Initialized instance of SG Table or NULL
525 */
526static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
527{
528 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
529
530 if (!sg)
531 return NULL;
532 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
533 kfree(sg);
534 return NULL;
535 }
536 sg_dma_address(sg->sgl) = addr;
537 sg->sgl->length = size;
538#ifdef CONFIG_NEED_SG_DMA_LENGTH
539 sg->sgl->dma_length = size;
540#endif
541 return sg;
542}
543
544static int
545kfd_mem_dmamap_userptr(struct kgd_mem *mem,
546 struct kfd_mem_attachment *attachment)
547{
548 enum dma_data_direction direction =
549 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
550 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
551 struct ttm_operation_ctx ctx = {.interruptible = true};
552 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
553 struct amdgpu_device *adev = attachment->adev;
554 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
555 struct ttm_tt *ttm = bo->tbo.ttm;
556 int ret;
557
558 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
559 return -EINVAL;
560
561 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
562 if (unlikely(!ttm->sg))
563 return -ENOMEM;
564
565 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
566 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
567 ttm->num_pages, 0,
568 (u64)ttm->num_pages << PAGE_SHIFT,
569 GFP_KERNEL);
570 if (unlikely(ret))
571 goto free_sg;
572
573 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
574 if (unlikely(ret))
575 goto release_sg;
576
577 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
578 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
579 if (ret)
580 goto unmap_sg;
581
582 return 0;
583
584unmap_sg:
585 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
586release_sg:
587 pr_err("DMA map userptr failed: %d\n", ret);
588 sg_free_table(ttm->sg);
589free_sg:
590 kfree(ttm->sg);
591 ttm->sg = NULL;
592 return ret;
593}
594
595static int
596kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
597{
598 struct ttm_operation_ctx ctx = {.interruptible = true};
599 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
600 int ret;
601
602 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
603 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
604 if (ret)
605 return ret;
606
607 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
608 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
609}
610
611/**
612 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
613 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
614 * @attachment: Virtual address attachment of the BO on accessing device
615 *
616 * An access request from the device that owns DOORBELL does not require DMA mapping.
617 * This is because the request doesn't go through PCIe root complex i.e. it instead
618 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
619 *
620 * In contrast, all access requests for MMIO need to be DMA mapped without regard to
621 * device ownership. This is because access requests for MMIO go through PCIe root
622 * complex.
623 *
624 * This is accomplished in two steps:
625 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
626 * in updating requesting device's page table
627 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU
628 * accessible. This allows an update of requesting device's page table
629 * with entries associated with DOOREBELL or MMIO memory
630 *
631 * This method is invoked in the following contexts:
632 * - Mapping of DOORBELL or MMIO BO of same or peer device
633 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access
634 *
635 * Return: ZERO if successful, NON-ZERO otherwise
636 */
637static int
638kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
639 struct kfd_mem_attachment *attachment)
640{
641 struct ttm_operation_ctx ctx = {.interruptible = true};
642 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
643 struct amdgpu_device *adev = attachment->adev;
644 struct ttm_tt *ttm = bo->tbo.ttm;
645 enum dma_data_direction dir;
646 dma_addr_t dma_addr;
647 bool mmio;
648 int ret;
649
650 /* Expect SG Table of dmapmap BO to be NULL */
651 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
652 if (unlikely(ttm->sg)) {
653 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
654 return -EINVAL;
655 }
656
657 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
658 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
659 dma_addr = mem->bo->tbo.sg->sgl->dma_address;
660 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
661 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
662 dma_addr = dma_map_resource(adev->dev, dma_addr,
663 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
664 ret = dma_mapping_error(adev->dev, dma_addr);
665 if (unlikely(ret))
666 return ret;
667 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
668
669 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
670 if (unlikely(!ttm->sg)) {
671 ret = -ENOMEM;
672 goto unmap_sg;
673 }
674
675 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
676 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
677 if (unlikely(ret))
678 goto free_sg;
679
680 return ret;
681
682free_sg:
683 sg_free_table(ttm->sg);
684 kfree(ttm->sg);
685 ttm->sg = NULL;
686unmap_sg:
687 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
688 dir, DMA_ATTR_SKIP_CPU_SYNC);
689 return ret;
690}
691
692static int
693kfd_mem_dmamap_attachment(struct kgd_mem *mem,
694 struct kfd_mem_attachment *attachment)
695{
696 switch (attachment->type) {
697 case KFD_MEM_ATT_SHARED:
698 return 0;
699 case KFD_MEM_ATT_USERPTR:
700 return kfd_mem_dmamap_userptr(mem, attachment);
701 case KFD_MEM_ATT_DMABUF:
702 return kfd_mem_dmamap_dmabuf(attachment);
703 case KFD_MEM_ATT_SG:
704 return kfd_mem_dmamap_sg_bo(mem, attachment);
705 default:
706 WARN_ON_ONCE(1);
707 }
708 return -EINVAL;
709}
710
711static void
712kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
713 struct kfd_mem_attachment *attachment)
714{
715 enum dma_data_direction direction =
716 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
717 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
718 struct ttm_operation_ctx ctx = {.interruptible = false};
719 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
720 struct amdgpu_device *adev = attachment->adev;
721 struct ttm_tt *ttm = bo->tbo.ttm;
722
723 if (unlikely(!ttm->sg))
724 return;
725
726 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
727 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
728
729 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
730 sg_free_table(ttm->sg);
731 kfree(ttm->sg);
732 ttm->sg = NULL;
733}
734
735static void
736kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
737{
738 /* This is a no-op. We don't want to trigger eviction fences when
739 * unmapping DMABufs. Therefore the invalidation (moving to system
740 * domain) is done in kfd_mem_dmamap_dmabuf.
741 */
742}
743
744/**
745 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
746 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
747 * @attachment: Virtual address attachment of the BO on accessing device
748 *
749 * The method performs following steps:
750 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible
751 * - Free SG Table that is used to encapsulate DMA mapped memory of
752 * peer device's DOORBELL or MMIO memory
753 *
754 * This method is invoked in the following contexts:
755 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory
756 * Eviction of DOOREBELL or MMIO BO on device having access to its memory
757 *
758 * Return: void
759 */
760static void
761kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
762 struct kfd_mem_attachment *attachment)
763{
764 struct ttm_operation_ctx ctx = {.interruptible = true};
765 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
766 struct amdgpu_device *adev = attachment->adev;
767 struct ttm_tt *ttm = bo->tbo.ttm;
768 enum dma_data_direction dir;
769
770 if (unlikely(!ttm->sg)) {
771 pr_debug("SG Table of BO is NULL");
772 return;
773 }
774
775 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
776 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
777
778 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
779 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
780 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
781 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
782 sg_free_table(ttm->sg);
783 kfree(ttm->sg);
784 ttm->sg = NULL;
785 bo->tbo.sg = NULL;
786}
787
788static void
789kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
790 struct kfd_mem_attachment *attachment)
791{
792 switch (attachment->type) {
793 case KFD_MEM_ATT_SHARED:
794 break;
795 case KFD_MEM_ATT_USERPTR:
796 kfd_mem_dmaunmap_userptr(mem, attachment);
797 break;
798 case KFD_MEM_ATT_DMABUF:
799 kfd_mem_dmaunmap_dmabuf(attachment);
800 break;
801 case KFD_MEM_ATT_SG:
802 kfd_mem_dmaunmap_sg_bo(mem, attachment);
803 break;
804 default:
805 WARN_ON_ONCE(1);
806 }
807}
808
809static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
810{
811 if (!mem->dmabuf) {
812 struct amdgpu_device *bo_adev;
813 struct dma_buf *dmabuf;
814 int r, fd;
815
816 bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
817 r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file,
818 mem->gem_handle,
819 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
820 DRM_RDWR : 0, &fd);
821 if (r)
822 return r;
823 dmabuf = dma_buf_get(fd);
824 close_fd(fd);
825 if (WARN_ON_ONCE(IS_ERR(dmabuf)))
826 return PTR_ERR(dmabuf);
827 mem->dmabuf = dmabuf;
828 }
829
830 return 0;
831}
832
833static int
834kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
835 struct amdgpu_bo **bo)
836{
837 struct drm_gem_object *gobj;
838 int ret;
839
840 ret = kfd_mem_export_dmabuf(mem);
841 if (ret)
842 return ret;
843
844 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
845 if (IS_ERR(gobj))
846 return PTR_ERR(gobj);
847
848 *bo = gem_to_amdgpu_bo(gobj);
849 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
850
851 return 0;
852}
853
854/* kfd_mem_attach - Add a BO to a VM
855 *
856 * Everything that needs to bo done only once when a BO is first added
857 * to a VM. It can later be mapped and unmapped many times without
858 * repeating these steps.
859 *
860 * 0. Create BO for DMA mapping, if needed
861 * 1. Allocate and initialize BO VA entry data structure
862 * 2. Add BO to the VM
863 * 3. Determine ASIC-specific PTE flags
864 * 4. Alloc page tables and directories if needed
865 * 4a. Validate new page tables and directories
866 */
867static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
868 struct amdgpu_vm *vm, bool is_aql)
869{
870 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
871 unsigned long bo_size = mem->bo->tbo.base.size;
872 uint64_t va = mem->va;
873 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
874 struct amdgpu_bo *bo[2] = {NULL, NULL};
875 struct amdgpu_bo_va *bo_va;
876 bool same_hive = false;
877 int i, ret;
878
879 if (!va) {
880 pr_err("Invalid VA when adding BO to VM\n");
881 return -EINVAL;
882 }
883
884 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
885 *
886 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
887 * In contrast the access path of VRAM BOs depens upon the type of
888 * link that connects the peer device. Access over PCIe is allowed
889 * if peer device has large BAR. In contrast, access over xGMI is
890 * allowed for both small and large BAR configurations of peer device
891 */
892 if ((adev != bo_adev && !adev->gmc.is_app_apu) &&
893 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
894 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
895 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
896 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
897 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
898 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
899 return -EINVAL;
900 }
901
902 for (i = 0; i <= is_aql; i++) {
903 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
904 if (unlikely(!attachment[i])) {
905 ret = -ENOMEM;
906 goto unwind;
907 }
908
909 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
910 va + bo_size, vm);
911
912 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
913 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
914 (mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) ||
915 same_hive) {
916 /* Mappings on the local GPU, or VRAM mappings in the
917 * local hive, or userptr, or GTT mapping can reuse dma map
918 * address space share the original BO
919 */
920 attachment[i]->type = KFD_MEM_ATT_SHARED;
921 bo[i] = mem->bo;
922 drm_gem_object_get(&bo[i]->tbo.base);
923 } else if (i > 0) {
924 /* Multiple mappings on the same GPU share the BO */
925 attachment[i]->type = KFD_MEM_ATT_SHARED;
926 bo[i] = bo[0];
927 drm_gem_object_get(&bo[i]->tbo.base);
928 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
929 /* Create an SG BO to DMA-map userptrs on other GPUs */
930 attachment[i]->type = KFD_MEM_ATT_USERPTR;
931 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
932 if (ret)
933 goto unwind;
934 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
935 } else if (mem->bo->tbo.type == ttm_bo_type_sg) {
936 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
937 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
938 "Handing invalid SG BO in ATTACH request");
939 attachment[i]->type = KFD_MEM_ATT_SG;
940 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
941 if (ret)
942 goto unwind;
943 /* Enable acces to GTT and VRAM BOs of peer devices */
944 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
945 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
946 attachment[i]->type = KFD_MEM_ATT_DMABUF;
947 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
948 if (ret)
949 goto unwind;
950 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
951 } else {
952 WARN_ONCE(true, "Handling invalid ATTACH request");
953 ret = -EINVAL;
954 goto unwind;
955 }
956
957 /* Add BO to VM internal data structures */
958 ret = amdgpu_bo_reserve(bo[i], false);
959 if (ret) {
960 pr_debug("Unable to reserve BO during memory attach");
961 goto unwind;
962 }
963 bo_va = amdgpu_vm_bo_find(vm, bo[i]);
964 if (!bo_va)
965 bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
966 else
967 ++bo_va->ref_count;
968 attachment[i]->bo_va = bo_va;
969 amdgpu_bo_unreserve(bo[i]);
970 if (unlikely(!attachment[i]->bo_va)) {
971 ret = -ENOMEM;
972 pr_err("Failed to add BO object to VM. ret == %d\n",
973 ret);
974 goto unwind;
975 }
976 attachment[i]->va = va;
977 attachment[i]->pte_flags = get_pte_flags(adev, mem);
978 attachment[i]->adev = adev;
979 list_add(&attachment[i]->list, &mem->attachments);
980
981 va += bo_size;
982 }
983
984 return 0;
985
986unwind:
987 for (; i >= 0; i--) {
988 if (!attachment[i])
989 continue;
990 if (attachment[i]->bo_va) {
991 amdgpu_bo_reserve(bo[i], true);
992 if (--attachment[i]->bo_va->ref_count == 0)
993 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
994 amdgpu_bo_unreserve(bo[i]);
995 list_del(&attachment[i]->list);
996 }
997 if (bo[i])
998 drm_gem_object_put(&bo[i]->tbo.base);
999 kfree(attachment[i]);
1000 }
1001 return ret;
1002}
1003
1004static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
1005{
1006 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
1007
1008 pr_debug("\t remove VA 0x%llx in entry %p\n",
1009 attachment->va, attachment);
1010 if (--attachment->bo_va->ref_count == 0)
1011 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
1012 drm_gem_object_put(&bo->tbo.base);
1013 list_del(&attachment->list);
1014 kfree(attachment);
1015}
1016
1017static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
1018 struct amdkfd_process_info *process_info,
1019 bool userptr)
1020{
1021 mutex_lock(&process_info->lock);
1022 if (userptr)
1023 list_add_tail(&mem->validate_list,
1024 &process_info->userptr_valid_list);
1025 else
1026 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
1027 mutex_unlock(&process_info->lock);
1028}
1029
1030static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
1031 struct amdkfd_process_info *process_info)
1032{
1033 mutex_lock(&process_info->lock);
1034 list_del(&mem->validate_list);
1035 mutex_unlock(&process_info->lock);
1036}
1037
1038/* Initializes user pages. It registers the MMU notifier and validates
1039 * the userptr BO in the GTT domain.
1040 *
1041 * The BO must already be on the userptr_valid_list. Otherwise an
1042 * eviction and restore may happen that leaves the new BO unmapped
1043 * with the user mode queues running.
1044 *
1045 * Takes the process_info->lock to protect against concurrent restore
1046 * workers.
1047 *
1048 * Returns 0 for success, negative errno for errors.
1049 */
1050static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1051 bool criu_resume)
1052{
1053 struct amdkfd_process_info *process_info = mem->process_info;
1054 struct amdgpu_bo *bo = mem->bo;
1055 struct ttm_operation_ctx ctx = { true, false };
1056 struct hmm_range *range;
1057 int ret = 0;
1058
1059 mutex_lock(&process_info->lock);
1060
1061 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1062 if (ret) {
1063 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1064 goto out;
1065 }
1066
1067 ret = amdgpu_hmm_register(bo, user_addr);
1068 if (ret) {
1069 pr_err("%s: Failed to register MMU notifier: %d\n",
1070 __func__, ret);
1071 goto out;
1072 }
1073
1074 if (criu_resume) {
1075 /*
1076 * During a CRIU restore operation, the userptr buffer objects
1077 * will be validated in the restore_userptr_work worker at a
1078 * later stage when it is scheduled by another ioctl called by
1079 * CRIU master process for the target pid for restore.
1080 */
1081 mutex_lock(&process_info->notifier_lock);
1082 mem->invalid++;
1083 mutex_unlock(&process_info->notifier_lock);
1084 mutex_unlock(&process_info->lock);
1085 return 0;
1086 }
1087
1088 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1089 if (ret) {
1090 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1091 goto unregister_out;
1092 }
1093
1094 ret = amdgpu_bo_reserve(bo, true);
1095 if (ret) {
1096 pr_err("%s: Failed to reserve BO\n", __func__);
1097 goto release_out;
1098 }
1099 amdgpu_bo_placement_from_domain(bo, mem->domain);
1100 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1101 if (ret)
1102 pr_err("%s: failed to validate BO\n", __func__);
1103 amdgpu_bo_unreserve(bo);
1104
1105release_out:
1106 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1107unregister_out:
1108 if (ret)
1109 amdgpu_hmm_unregister(bo);
1110out:
1111 mutex_unlock(&process_info->lock);
1112 return ret;
1113}
1114
1115/* Reserving a BO and its page table BOs must happen atomically to
1116 * avoid deadlocks. Some operations update multiple VMs at once. Track
1117 * all the reservation info in a context structure. Optionally a sync
1118 * object can track VM updates.
1119 */
1120struct bo_vm_reservation_context {
1121 /* DRM execution context for the reservation */
1122 struct drm_exec exec;
1123 /* Number of VMs reserved */
1124 unsigned int n_vms;
1125 /* Pointer to sync object */
1126 struct amdgpu_sync *sync;
1127};
1128
1129enum bo_vm_match {
1130 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
1131 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
1132 BO_VM_ALL, /* Match all VMs a BO was added to */
1133};
1134
1135/**
1136 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1137 * @mem: KFD BO structure.
1138 * @vm: the VM to reserve.
1139 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1140 */
1141static int reserve_bo_and_vm(struct kgd_mem *mem,
1142 struct amdgpu_vm *vm,
1143 struct bo_vm_reservation_context *ctx)
1144{
1145 struct amdgpu_bo *bo = mem->bo;
1146 int ret;
1147
1148 WARN_ON(!vm);
1149
1150 ctx->n_vms = 1;
1151 ctx->sync = &mem->sync;
1152 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1153 drm_exec_until_all_locked(&ctx->exec) {
1154 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1155 drm_exec_retry_on_contention(&ctx->exec);
1156 if (unlikely(ret))
1157 goto error;
1158
1159 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1160 drm_exec_retry_on_contention(&ctx->exec);
1161 if (unlikely(ret))
1162 goto error;
1163 }
1164 return 0;
1165
1166error:
1167 pr_err("Failed to reserve buffers in ttm.\n");
1168 drm_exec_fini(&ctx->exec);
1169 return ret;
1170}
1171
1172/**
1173 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1174 * @mem: KFD BO structure.
1175 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1176 * is used. Otherwise, a single VM associated with the BO.
1177 * @map_type: the mapping status that will be used to filter the VMs.
1178 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1179 *
1180 * Returns 0 for success, negative for failure.
1181 */
1182static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1183 struct amdgpu_vm *vm, enum bo_vm_match map_type,
1184 struct bo_vm_reservation_context *ctx)
1185{
1186 struct kfd_mem_attachment *entry;
1187 struct amdgpu_bo *bo = mem->bo;
1188 int ret;
1189
1190 ctx->sync = &mem->sync;
1191 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1192 drm_exec_until_all_locked(&ctx->exec) {
1193 ctx->n_vms = 0;
1194 list_for_each_entry(entry, &mem->attachments, list) {
1195 if ((vm && vm != entry->bo_va->base.vm) ||
1196 (entry->is_mapped != map_type
1197 && map_type != BO_VM_ALL))
1198 continue;
1199
1200 ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1201 &ctx->exec, 2);
1202 drm_exec_retry_on_contention(&ctx->exec);
1203 if (unlikely(ret))
1204 goto error;
1205 ++ctx->n_vms;
1206 }
1207
1208 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1209 drm_exec_retry_on_contention(&ctx->exec);
1210 if (unlikely(ret))
1211 goto error;
1212 }
1213 return 0;
1214
1215error:
1216 pr_err("Failed to reserve buffers in ttm.\n");
1217 drm_exec_fini(&ctx->exec);
1218 return ret;
1219}
1220
1221/**
1222 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1223 * @ctx: Reservation context to unreserve
1224 * @wait: Optionally wait for a sync object representing pending VM updates
1225 * @intr: Whether the wait is interruptible
1226 *
1227 * Also frees any resources allocated in
1228 * reserve_bo_and_(cond_)vm(s). Returns the status from
1229 * amdgpu_sync_wait.
1230 */
1231static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1232 bool wait, bool intr)
1233{
1234 int ret = 0;
1235
1236 if (wait)
1237 ret = amdgpu_sync_wait(ctx->sync, intr);
1238
1239 drm_exec_fini(&ctx->exec);
1240 ctx->sync = NULL;
1241 return ret;
1242}
1243
1244static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1245 struct kfd_mem_attachment *entry,
1246 struct amdgpu_sync *sync)
1247{
1248 struct amdgpu_bo_va *bo_va = entry->bo_va;
1249 struct amdgpu_device *adev = entry->adev;
1250 struct amdgpu_vm *vm = bo_va->base.vm;
1251
1252 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1253
1254 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1255
1256 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1257}
1258
1259static int update_gpuvm_pte(struct kgd_mem *mem,
1260 struct kfd_mem_attachment *entry,
1261 struct amdgpu_sync *sync)
1262{
1263 struct amdgpu_bo_va *bo_va = entry->bo_va;
1264 struct amdgpu_device *adev = entry->adev;
1265 int ret;
1266
1267 ret = kfd_mem_dmamap_attachment(mem, entry);
1268 if (ret)
1269 return ret;
1270
1271 /* Update the page tables */
1272 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1273 if (ret) {
1274 pr_err("amdgpu_vm_bo_update failed\n");
1275 return ret;
1276 }
1277
1278 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1279}
1280
1281static int map_bo_to_gpuvm(struct kgd_mem *mem,
1282 struct kfd_mem_attachment *entry,
1283 struct amdgpu_sync *sync,
1284 bool no_update_pte)
1285{
1286 int ret;
1287
1288 /* Set virtual address for the allocation */
1289 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1290 amdgpu_bo_size(entry->bo_va->base.bo),
1291 entry->pte_flags);
1292 if (ret) {
1293 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1294 entry->va, ret);
1295 return ret;
1296 }
1297
1298 if (no_update_pte)
1299 return 0;
1300
1301 ret = update_gpuvm_pte(mem, entry, sync);
1302 if (ret) {
1303 pr_err("update_gpuvm_pte() failed\n");
1304 goto update_gpuvm_pte_failed;
1305 }
1306
1307 return 0;
1308
1309update_gpuvm_pte_failed:
1310 unmap_bo_from_gpuvm(mem, entry, sync);
1311 kfd_mem_dmaunmap_attachment(mem, entry);
1312 return ret;
1313}
1314
1315static int process_validate_vms(struct amdkfd_process_info *process_info,
1316 struct ww_acquire_ctx *ticket)
1317{
1318 struct amdgpu_vm *peer_vm;
1319 int ret;
1320
1321 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1322 vm_list_node) {
1323 ret = vm_validate_pt_pd_bos(peer_vm, ticket);
1324 if (ret)
1325 return ret;
1326 }
1327
1328 return 0;
1329}
1330
1331static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1332 struct amdgpu_sync *sync)
1333{
1334 struct amdgpu_vm *peer_vm;
1335 int ret;
1336
1337 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1338 vm_list_node) {
1339 struct amdgpu_bo *pd = peer_vm->root.bo;
1340
1341 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1342 AMDGPU_SYNC_NE_OWNER,
1343 AMDGPU_FENCE_OWNER_KFD);
1344 if (ret)
1345 return ret;
1346 }
1347
1348 return 0;
1349}
1350
1351static int process_update_pds(struct amdkfd_process_info *process_info,
1352 struct amdgpu_sync *sync)
1353{
1354 struct amdgpu_vm *peer_vm;
1355 int ret;
1356
1357 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1358 vm_list_node) {
1359 ret = vm_update_pds(peer_vm, sync);
1360 if (ret)
1361 return ret;
1362 }
1363
1364 return 0;
1365}
1366
1367static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1368 struct dma_fence **ef)
1369{
1370 struct amdkfd_process_info *info = NULL;
1371 int ret;
1372
1373 if (!*process_info) {
1374 info = kzalloc(sizeof(*info), GFP_KERNEL);
1375 if (!info)
1376 return -ENOMEM;
1377
1378 mutex_init(&info->lock);
1379 mutex_init(&info->notifier_lock);
1380 INIT_LIST_HEAD(&info->vm_list_head);
1381 INIT_LIST_HEAD(&info->kfd_bo_list);
1382 INIT_LIST_HEAD(&info->userptr_valid_list);
1383 INIT_LIST_HEAD(&info->userptr_inval_list);
1384
1385 info->eviction_fence =
1386 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1387 current->mm,
1388 NULL);
1389 if (!info->eviction_fence) {
1390 pr_err("Failed to create eviction fence\n");
1391 ret = -ENOMEM;
1392 goto create_evict_fence_fail;
1393 }
1394
1395 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1396 INIT_DELAYED_WORK(&info->restore_userptr_work,
1397 amdgpu_amdkfd_restore_userptr_worker);
1398
1399 *process_info = info;
1400 }
1401
1402 vm->process_info = *process_info;
1403
1404 /* Validate page directory and attach eviction fence */
1405 ret = amdgpu_bo_reserve(vm->root.bo, true);
1406 if (ret)
1407 goto reserve_pd_fail;
1408 ret = vm_validate_pt_pd_bos(vm, NULL);
1409 if (ret) {
1410 pr_err("validate_pt_pd_bos() failed\n");
1411 goto validate_pd_fail;
1412 }
1413 ret = amdgpu_bo_sync_wait(vm->root.bo,
1414 AMDGPU_FENCE_OWNER_KFD, false);
1415 if (ret)
1416 goto wait_pd_fail;
1417 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1418 if (ret)
1419 goto reserve_shared_fail;
1420 dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1421 &vm->process_info->eviction_fence->base,
1422 DMA_RESV_USAGE_BOOKKEEP);
1423 amdgpu_bo_unreserve(vm->root.bo);
1424
1425 /* Update process info */
1426 mutex_lock(&vm->process_info->lock);
1427 list_add_tail(&vm->vm_list_node,
1428 &(vm->process_info->vm_list_head));
1429 vm->process_info->n_vms++;
1430
1431 *ef = dma_fence_get(&vm->process_info->eviction_fence->base);
1432 mutex_unlock(&vm->process_info->lock);
1433
1434 return 0;
1435
1436reserve_shared_fail:
1437wait_pd_fail:
1438validate_pd_fail:
1439 amdgpu_bo_unreserve(vm->root.bo);
1440reserve_pd_fail:
1441 vm->process_info = NULL;
1442 if (info) {
1443 dma_fence_put(&info->eviction_fence->base);
1444 *process_info = NULL;
1445 put_pid(info->pid);
1446create_evict_fence_fail:
1447 mutex_destroy(&info->lock);
1448 mutex_destroy(&info->notifier_lock);
1449 kfree(info);
1450 }
1451 return ret;
1452}
1453
1454/**
1455 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1456 * @bo: Handle of buffer object being pinned
1457 * @domain: Domain into which BO should be pinned
1458 *
1459 * - USERPTR BOs are UNPINNABLE and will return error
1460 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1461 * PIN count incremented. It is valid to PIN a BO multiple times
1462 *
1463 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1464 */
1465static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1466{
1467 int ret = 0;
1468
1469 ret = amdgpu_bo_reserve(bo, false);
1470 if (unlikely(ret))
1471 return ret;
1472
1473 ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1474 if (ret)
1475 pr_err("Error in Pinning BO to domain: %d\n", domain);
1476
1477 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1478 amdgpu_bo_unreserve(bo);
1479
1480 return ret;
1481}
1482
1483/**
1484 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1485 * @bo: Handle of buffer object being unpinned
1486 *
1487 * - Is a illegal request for USERPTR BOs and is ignored
1488 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1489 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1490 */
1491static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1492{
1493 int ret = 0;
1494
1495 ret = amdgpu_bo_reserve(bo, false);
1496 if (unlikely(ret))
1497 return;
1498
1499 amdgpu_bo_unpin(bo);
1500 amdgpu_bo_unreserve(bo);
1501}
1502
1503int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1504 struct amdgpu_vm *avm, u32 pasid)
1505
1506{
1507 int ret;
1508
1509 /* Free the original amdgpu allocated pasid,
1510 * will be replaced with kfd allocated pasid.
1511 */
1512 if (avm->pasid) {
1513 amdgpu_pasid_free(avm->pasid);
1514 amdgpu_vm_set_pasid(adev, avm, 0);
1515 }
1516
1517 ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1518 if (ret)
1519 return ret;
1520
1521 return 0;
1522}
1523
1524int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1525 struct amdgpu_vm *avm,
1526 void **process_info,
1527 struct dma_fence **ef)
1528{
1529 int ret;
1530
1531 /* Already a compute VM? */
1532 if (avm->process_info)
1533 return -EINVAL;
1534
1535 /* Convert VM into a compute VM */
1536 ret = amdgpu_vm_make_compute(adev, avm);
1537 if (ret)
1538 return ret;
1539
1540 /* Initialize KFD part of the VM and process info */
1541 ret = init_kfd_vm(avm, process_info, ef);
1542 if (ret)
1543 return ret;
1544
1545 amdgpu_vm_set_task_info(avm);
1546
1547 return 0;
1548}
1549
1550void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1551 struct amdgpu_vm *vm)
1552{
1553 struct amdkfd_process_info *process_info = vm->process_info;
1554
1555 if (!process_info)
1556 return;
1557
1558 /* Update process info */
1559 mutex_lock(&process_info->lock);
1560 process_info->n_vms--;
1561 list_del(&vm->vm_list_node);
1562 mutex_unlock(&process_info->lock);
1563
1564 vm->process_info = NULL;
1565
1566 /* Release per-process resources when last compute VM is destroyed */
1567 if (!process_info->n_vms) {
1568 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1569 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1570 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1571
1572 dma_fence_put(&process_info->eviction_fence->base);
1573 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1574 put_pid(process_info->pid);
1575 mutex_destroy(&process_info->lock);
1576 mutex_destroy(&process_info->notifier_lock);
1577 kfree(process_info);
1578 }
1579}
1580
1581void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1582 void *drm_priv)
1583{
1584 struct amdgpu_vm *avm;
1585
1586 if (WARN_ON(!adev || !drm_priv))
1587 return;
1588
1589 avm = drm_priv_to_vm(drm_priv);
1590
1591 pr_debug("Releasing process vm %p\n", avm);
1592
1593 /* The original pasid of amdgpu vm has already been
1594 * released during making a amdgpu vm to a compute vm
1595 * The current pasid is managed by kfd and will be
1596 * released on kfd process destroy. Set amdgpu pasid
1597 * to 0 to avoid duplicate release.
1598 */
1599 amdgpu_vm_release_compute(adev, avm);
1600}
1601
1602uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1603{
1604 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1605 struct amdgpu_bo *pd = avm->root.bo;
1606 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1607
1608 if (adev->asic_type < CHIP_VEGA10)
1609 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1610 return avm->pd_phys_addr;
1611}
1612
1613void amdgpu_amdkfd_block_mmu_notifications(void *p)
1614{
1615 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1616
1617 mutex_lock(&pinfo->lock);
1618 WRITE_ONCE(pinfo->block_mmu_notifications, true);
1619 mutex_unlock(&pinfo->lock);
1620}
1621
1622int amdgpu_amdkfd_criu_resume(void *p)
1623{
1624 int ret = 0;
1625 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1626
1627 mutex_lock(&pinfo->lock);
1628 pr_debug("scheduling work\n");
1629 mutex_lock(&pinfo->notifier_lock);
1630 pinfo->evicted_bos++;
1631 mutex_unlock(&pinfo->notifier_lock);
1632 if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1633 ret = -EINVAL;
1634 goto out_unlock;
1635 }
1636 WRITE_ONCE(pinfo->block_mmu_notifications, false);
1637 queue_delayed_work(system_freezable_wq,
1638 &pinfo->restore_userptr_work, 0);
1639
1640out_unlock:
1641 mutex_unlock(&pinfo->lock);
1642 return ret;
1643}
1644
1645size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1646 uint8_t xcp_id)
1647{
1648 uint64_t reserved_for_pt =
1649 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1650 ssize_t available;
1651 uint64_t vram_available, system_mem_available, ttm_mem_available;
1652
1653 spin_lock(&kfd_mem_limit.mem_limit_lock);
1654 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1655 - adev->kfd.vram_used_aligned[xcp_id]
1656 - atomic64_read(&adev->vram_pin_size)
1657 - reserved_for_pt;
1658
1659 if (adev->gmc.is_app_apu) {
1660 system_mem_available = no_system_mem_limit ?
1661 kfd_mem_limit.max_system_mem_limit :
1662 kfd_mem_limit.max_system_mem_limit -
1663 kfd_mem_limit.system_mem_used;
1664
1665 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1666 kfd_mem_limit.ttm_mem_used;
1667
1668 available = min3(system_mem_available, ttm_mem_available,
1669 vram_available);
1670 available = ALIGN_DOWN(available, PAGE_SIZE);
1671 } else {
1672 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1673 }
1674
1675 spin_unlock(&kfd_mem_limit.mem_limit_lock);
1676
1677 if (available < 0)
1678 available = 0;
1679
1680 return available;
1681}
1682
1683int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1684 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1685 void *drm_priv, struct kgd_mem **mem,
1686 uint64_t *offset, uint32_t flags, bool criu_resume)
1687{
1688 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1689 struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1690 enum ttm_bo_type bo_type = ttm_bo_type_device;
1691 struct sg_table *sg = NULL;
1692 uint64_t user_addr = 0;
1693 struct amdgpu_bo *bo;
1694 struct drm_gem_object *gobj = NULL;
1695 u32 domain, alloc_domain;
1696 uint64_t aligned_size;
1697 int8_t xcp_id = -1;
1698 u64 alloc_flags;
1699 int ret;
1700
1701 /*
1702 * Check on which domain to allocate BO
1703 */
1704 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1705 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1706
1707 if (adev->gmc.is_app_apu) {
1708 domain = AMDGPU_GEM_DOMAIN_GTT;
1709 alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1710 alloc_flags = 0;
1711 } else {
1712 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1713 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1714 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1715 }
1716 xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1717 0 : fpriv->xcp_id;
1718 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1719 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1720 alloc_flags = 0;
1721 } else {
1722 domain = AMDGPU_GEM_DOMAIN_GTT;
1723 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1724 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1725
1726 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1727 if (!offset || !*offset)
1728 return -EINVAL;
1729 user_addr = untagged_addr(*offset);
1730 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1731 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1732 bo_type = ttm_bo_type_sg;
1733 if (size > UINT_MAX)
1734 return -EINVAL;
1735 sg = create_sg_table(*offset, size);
1736 if (!sg)
1737 return -ENOMEM;
1738 } else {
1739 return -EINVAL;
1740 }
1741 }
1742
1743 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1744 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1745 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT)
1746 alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT;
1747 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1748 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1749
1750 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1751 if (!*mem) {
1752 ret = -ENOMEM;
1753 goto err;
1754 }
1755 INIT_LIST_HEAD(&(*mem)->attachments);
1756 mutex_init(&(*mem)->lock);
1757 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1758
1759 /* Workaround for AQL queue wraparound bug. Map the same
1760 * memory twice. That means we only actually allocate half
1761 * the memory.
1762 */
1763 if ((*mem)->aql_queue)
1764 size >>= 1;
1765 aligned_size = PAGE_ALIGN(size);
1766
1767 (*mem)->alloc_flags = flags;
1768
1769 amdgpu_sync_create(&(*mem)->sync);
1770
1771 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1772 xcp_id);
1773 if (ret) {
1774 pr_debug("Insufficient memory\n");
1775 goto err_reserve_limit;
1776 }
1777
1778 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1779 va, (*mem)->aql_queue ? size << 1 : size,
1780 domain_string(alloc_domain), xcp_id);
1781
1782 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1783 bo_type, NULL, &gobj, xcp_id + 1);
1784 if (ret) {
1785 pr_debug("Failed to create BO on domain %s. ret %d\n",
1786 domain_string(alloc_domain), ret);
1787 goto err_bo_create;
1788 }
1789 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1790 if (ret) {
1791 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1792 goto err_node_allow;
1793 }
1794 ret = drm_gem_handle_create(adev->kfd.client.file, gobj, &(*mem)->gem_handle);
1795 if (ret)
1796 goto err_gem_handle_create;
1797 bo = gem_to_amdgpu_bo(gobj);
1798 if (bo_type == ttm_bo_type_sg) {
1799 bo->tbo.sg = sg;
1800 bo->tbo.ttm->sg = sg;
1801 }
1802 bo->kfd_bo = *mem;
1803 (*mem)->bo = bo;
1804 if (user_addr)
1805 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1806
1807 (*mem)->va = va;
1808 (*mem)->domain = domain;
1809 (*mem)->mapped_to_gpu_memory = 0;
1810 (*mem)->process_info = avm->process_info;
1811
1812 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1813
1814 if (user_addr) {
1815 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1816 ret = init_user_pages(*mem, user_addr, criu_resume);
1817 if (ret)
1818 goto allocate_init_user_pages_failed;
1819 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1820 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1821 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1822 if (ret) {
1823 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1824 goto err_pin_bo;
1825 }
1826 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1827 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1828 } else {
1829 mutex_lock(&avm->process_info->lock);
1830 if (avm->process_info->eviction_fence &&
1831 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
1832 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain,
1833 &avm->process_info->eviction_fence->base);
1834 mutex_unlock(&avm->process_info->lock);
1835 if (ret)
1836 goto err_validate_bo;
1837 }
1838
1839 if (offset)
1840 *offset = amdgpu_bo_mmap_offset(bo);
1841
1842 return 0;
1843
1844allocate_init_user_pages_failed:
1845err_pin_bo:
1846err_validate_bo:
1847 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1848 drm_gem_handle_delete(adev->kfd.client.file, (*mem)->gem_handle);
1849err_gem_handle_create:
1850 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1851err_node_allow:
1852 /* Don't unreserve system mem limit twice */
1853 goto err_reserve_limit;
1854err_bo_create:
1855 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1856err_reserve_limit:
1857 amdgpu_sync_free(&(*mem)->sync);
1858 mutex_destroy(&(*mem)->lock);
1859 if (gobj)
1860 drm_gem_object_put(gobj);
1861 else
1862 kfree(*mem);
1863err:
1864 if (sg) {
1865 sg_free_table(sg);
1866 kfree(sg);
1867 }
1868 return ret;
1869}
1870
1871int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1872 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1873 uint64_t *size)
1874{
1875 struct amdkfd_process_info *process_info = mem->process_info;
1876 unsigned long bo_size = mem->bo->tbo.base.size;
1877 bool use_release_notifier = (mem->bo->kfd_bo == mem);
1878 struct kfd_mem_attachment *entry, *tmp;
1879 struct bo_vm_reservation_context ctx;
1880 unsigned int mapped_to_gpu_memory;
1881 int ret;
1882 bool is_imported = false;
1883
1884 mutex_lock(&mem->lock);
1885
1886 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1887 if (mem->alloc_flags &
1888 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1889 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1890 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1891 }
1892
1893 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1894 is_imported = mem->is_imported;
1895 mutex_unlock(&mem->lock);
1896 /* lock is not needed after this, since mem is unused and will
1897 * be freed anyway
1898 */
1899
1900 if (mapped_to_gpu_memory > 0) {
1901 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1902 mem->va, bo_size);
1903 return -EBUSY;
1904 }
1905
1906 /* Make sure restore workers don't access the BO any more */
1907 mutex_lock(&process_info->lock);
1908 list_del(&mem->validate_list);
1909 mutex_unlock(&process_info->lock);
1910
1911 /* Cleanup user pages and MMU notifiers */
1912 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1913 amdgpu_hmm_unregister(mem->bo);
1914 mutex_lock(&process_info->notifier_lock);
1915 amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1916 mutex_unlock(&process_info->notifier_lock);
1917 }
1918
1919 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1920 if (unlikely(ret))
1921 return ret;
1922
1923 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1924 process_info->eviction_fence);
1925 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1926 mem->va + bo_size * (1 + mem->aql_queue));
1927
1928 /* Remove from VM internal data structures */
1929 list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
1930 kfd_mem_dmaunmap_attachment(mem, entry);
1931 kfd_mem_detach(entry);
1932 }
1933
1934 ret = unreserve_bo_and_vms(&ctx, false, false);
1935
1936 /* Free the sync object */
1937 amdgpu_sync_free(&mem->sync);
1938
1939 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1940 * remap BO. We need to free it.
1941 */
1942 if (mem->bo->tbo.sg) {
1943 sg_free_table(mem->bo->tbo.sg);
1944 kfree(mem->bo->tbo.sg);
1945 }
1946
1947 /* Update the size of the BO being freed if it was allocated from
1948 * VRAM and is not imported. For APP APU VRAM allocations are done
1949 * in GTT domain
1950 */
1951 if (size) {
1952 if (!is_imported &&
1953 (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1954 (adev->gmc.is_app_apu &&
1955 mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1956 *size = bo_size;
1957 else
1958 *size = 0;
1959 }
1960
1961 /* Free the BO*/
1962 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1963 drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle);
1964 if (mem->dmabuf) {
1965 dma_buf_put(mem->dmabuf);
1966 mem->dmabuf = NULL;
1967 }
1968 mutex_destroy(&mem->lock);
1969
1970 /* If this releases the last reference, it will end up calling
1971 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1972 * this needs to be the last call here.
1973 */
1974 drm_gem_object_put(&mem->bo->tbo.base);
1975
1976 /*
1977 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
1978 * explicitly free it here.
1979 */
1980 if (!use_release_notifier)
1981 kfree(mem);
1982
1983 return ret;
1984}
1985
1986int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1987 struct amdgpu_device *adev, struct kgd_mem *mem,
1988 void *drm_priv)
1989{
1990 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1991 int ret;
1992 struct amdgpu_bo *bo;
1993 uint32_t domain;
1994 struct kfd_mem_attachment *entry;
1995 struct bo_vm_reservation_context ctx;
1996 unsigned long bo_size;
1997 bool is_invalid_userptr = false;
1998
1999 bo = mem->bo;
2000 if (!bo) {
2001 pr_err("Invalid BO when mapping memory to GPU\n");
2002 return -EINVAL;
2003 }
2004
2005 /* Make sure restore is not running concurrently. Since we
2006 * don't map invalid userptr BOs, we rely on the next restore
2007 * worker to do the mapping
2008 */
2009 mutex_lock(&mem->process_info->lock);
2010
2011 /* Lock notifier lock. If we find an invalid userptr BO, we can be
2012 * sure that the MMU notifier is no longer running
2013 * concurrently and the queues are actually stopped
2014 */
2015 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2016 mutex_lock(&mem->process_info->notifier_lock);
2017 is_invalid_userptr = !!mem->invalid;
2018 mutex_unlock(&mem->process_info->notifier_lock);
2019 }
2020
2021 mutex_lock(&mem->lock);
2022
2023 domain = mem->domain;
2024 bo_size = bo->tbo.base.size;
2025
2026 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
2027 mem->va,
2028 mem->va + bo_size * (1 + mem->aql_queue),
2029 avm, domain_string(domain));
2030
2031 if (!kfd_mem_is_attached(avm, mem)) {
2032 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
2033 if (ret)
2034 goto out;
2035 }
2036
2037 ret = reserve_bo_and_vm(mem, avm, &ctx);
2038 if (unlikely(ret))
2039 goto out;
2040
2041 /* Userptr can be marked as "not invalid", but not actually be
2042 * validated yet (still in the system domain). In that case
2043 * the queues are still stopped and we can leave mapping for
2044 * the next restore worker
2045 */
2046 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
2047 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
2048 is_invalid_userptr = true;
2049
2050 ret = vm_validate_pt_pd_bos(avm, NULL);
2051 if (unlikely(ret))
2052 goto out_unreserve;
2053
2054 list_for_each_entry(entry, &mem->attachments, list) {
2055 if (entry->bo_va->base.vm != avm || entry->is_mapped)
2056 continue;
2057
2058 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2059 entry->va, entry->va + bo_size, entry);
2060
2061 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2062 is_invalid_userptr);
2063 if (ret) {
2064 pr_err("Failed to map bo to gpuvm\n");
2065 goto out_unreserve;
2066 }
2067
2068 ret = vm_update_pds(avm, ctx.sync);
2069 if (ret) {
2070 pr_err("Failed to update page directories\n");
2071 goto out_unreserve;
2072 }
2073
2074 entry->is_mapped = true;
2075 mem->mapped_to_gpu_memory++;
2076 pr_debug("\t INC mapping count %d\n",
2077 mem->mapped_to_gpu_memory);
2078 }
2079
2080 ret = unreserve_bo_and_vms(&ctx, false, false);
2081
2082 goto out;
2083
2084out_unreserve:
2085 unreserve_bo_and_vms(&ctx, false, false);
2086out:
2087 mutex_unlock(&mem->process_info->lock);
2088 mutex_unlock(&mem->lock);
2089 return ret;
2090}
2091
2092int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv)
2093{
2094 struct kfd_mem_attachment *entry;
2095 struct amdgpu_vm *vm;
2096 int ret;
2097
2098 vm = drm_priv_to_vm(drm_priv);
2099
2100 mutex_lock(&mem->lock);
2101
2102 ret = amdgpu_bo_reserve(mem->bo, true);
2103 if (ret)
2104 goto out;
2105
2106 list_for_each_entry(entry, &mem->attachments, list) {
2107 if (entry->bo_va->base.vm != vm)
2108 continue;
2109 if (entry->bo_va->base.bo->tbo.ttm &&
2110 !entry->bo_va->base.bo->tbo.ttm->sg)
2111 continue;
2112
2113 kfd_mem_dmaunmap_attachment(mem, entry);
2114 }
2115
2116 amdgpu_bo_unreserve(mem->bo);
2117out:
2118 mutex_unlock(&mem->lock);
2119
2120 return ret;
2121}
2122
2123int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2124 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2125{
2126 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2127 unsigned long bo_size = mem->bo->tbo.base.size;
2128 struct kfd_mem_attachment *entry;
2129 struct bo_vm_reservation_context ctx;
2130 int ret;
2131
2132 mutex_lock(&mem->lock);
2133
2134 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2135 if (unlikely(ret))
2136 goto out;
2137 /* If no VMs were reserved, it means the BO wasn't actually mapped */
2138 if (ctx.n_vms == 0) {
2139 ret = -EINVAL;
2140 goto unreserve_out;
2141 }
2142
2143 ret = vm_validate_pt_pd_bos(avm, NULL);
2144 if (unlikely(ret))
2145 goto unreserve_out;
2146
2147 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2148 mem->va,
2149 mem->va + bo_size * (1 + mem->aql_queue),
2150 avm);
2151
2152 list_for_each_entry(entry, &mem->attachments, list) {
2153 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2154 continue;
2155
2156 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2157 entry->va, entry->va + bo_size, entry);
2158
2159 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2160 entry->is_mapped = false;
2161
2162 mem->mapped_to_gpu_memory--;
2163 pr_debug("\t DEC mapping count %d\n",
2164 mem->mapped_to_gpu_memory);
2165 }
2166
2167unreserve_out:
2168 unreserve_bo_and_vms(&ctx, false, false);
2169out:
2170 mutex_unlock(&mem->lock);
2171 return ret;
2172}
2173
2174int amdgpu_amdkfd_gpuvm_sync_memory(
2175 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2176{
2177 struct amdgpu_sync sync;
2178 int ret;
2179
2180 amdgpu_sync_create(&sync);
2181
2182 mutex_lock(&mem->lock);
2183 amdgpu_sync_clone(&mem->sync, &sync);
2184 mutex_unlock(&mem->lock);
2185
2186 ret = amdgpu_sync_wait(&sync, intr);
2187 amdgpu_sync_free(&sync);
2188 return ret;
2189}
2190
2191/**
2192 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2193 * @bo: Buffer object to be mapped
2194 *
2195 * Before return, bo reference count is incremented. To release the reference and unpin/
2196 * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2197 */
2198int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
2199{
2200 int ret;
2201
2202 ret = amdgpu_bo_reserve(bo, true);
2203 if (ret) {
2204 pr_err("Failed to reserve bo. ret %d\n", ret);
2205 goto err_reserve_bo_failed;
2206 }
2207
2208 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2209 if (ret) {
2210 pr_err("Failed to pin bo. ret %d\n", ret);
2211 goto err_pin_bo_failed;
2212 }
2213
2214 ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2215 if (ret) {
2216 pr_err("Failed to bind bo to GART. ret %d\n", ret);
2217 goto err_map_bo_gart_failed;
2218 }
2219
2220 amdgpu_amdkfd_remove_eviction_fence(
2221 bo, bo->vm_bo->vm->process_info->eviction_fence);
2222
2223 amdgpu_bo_unreserve(bo);
2224
2225 bo = amdgpu_bo_ref(bo);
2226
2227 return 0;
2228
2229err_map_bo_gart_failed:
2230 amdgpu_bo_unpin(bo);
2231err_pin_bo_failed:
2232 amdgpu_bo_unreserve(bo);
2233err_reserve_bo_failed:
2234
2235 return ret;
2236}
2237
2238/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2239 *
2240 * @mem: Buffer object to be mapped for CPU access
2241 * @kptr[out]: pointer in kernel CPU address space
2242 * @size[out]: size of the buffer
2243 *
2244 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2245 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2246 * validate_list, so the GPU mapping can be restored after a page table was
2247 * evicted.
2248 *
2249 * Return: 0 on success, error code on failure
2250 */
2251int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2252 void **kptr, uint64_t *size)
2253{
2254 int ret;
2255 struct amdgpu_bo *bo = mem->bo;
2256
2257 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2258 pr_err("userptr can't be mapped to kernel\n");
2259 return -EINVAL;
2260 }
2261
2262 mutex_lock(&mem->process_info->lock);
2263
2264 ret = amdgpu_bo_reserve(bo, true);
2265 if (ret) {
2266 pr_err("Failed to reserve bo. ret %d\n", ret);
2267 goto bo_reserve_failed;
2268 }
2269
2270 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2271 if (ret) {
2272 pr_err("Failed to pin bo. ret %d\n", ret);
2273 goto pin_failed;
2274 }
2275
2276 ret = amdgpu_bo_kmap(bo, kptr);
2277 if (ret) {
2278 pr_err("Failed to map bo to kernel. ret %d\n", ret);
2279 goto kmap_failed;
2280 }
2281
2282 amdgpu_amdkfd_remove_eviction_fence(
2283 bo, mem->process_info->eviction_fence);
2284
2285 if (size)
2286 *size = amdgpu_bo_size(bo);
2287
2288 amdgpu_bo_unreserve(bo);
2289
2290 mutex_unlock(&mem->process_info->lock);
2291 return 0;
2292
2293kmap_failed:
2294 amdgpu_bo_unpin(bo);
2295pin_failed:
2296 amdgpu_bo_unreserve(bo);
2297bo_reserve_failed:
2298 mutex_unlock(&mem->process_info->lock);
2299
2300 return ret;
2301}
2302
2303/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2304 *
2305 * @mem: Buffer object to be unmapped for CPU access
2306 *
2307 * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2308 * eviction fence, so this function should only be used for cleanup before the
2309 * BO is destroyed.
2310 */
2311void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2312{
2313 struct amdgpu_bo *bo = mem->bo;
2314
2315 amdgpu_bo_reserve(bo, true);
2316 amdgpu_bo_kunmap(bo);
2317 amdgpu_bo_unpin(bo);
2318 amdgpu_bo_unreserve(bo);
2319}
2320
2321int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2322 struct kfd_vm_fault_info *mem)
2323{
2324 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2325 *mem = *adev->gmc.vm_fault_info;
2326 mb(); /* make sure read happened */
2327 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2328 }
2329 return 0;
2330}
2331
2332static int import_obj_create(struct amdgpu_device *adev,
2333 struct dma_buf *dma_buf,
2334 struct drm_gem_object *obj,
2335 uint64_t va, void *drm_priv,
2336 struct kgd_mem **mem, uint64_t *size,
2337 uint64_t *mmap_offset)
2338{
2339 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2340 struct amdgpu_bo *bo;
2341 int ret;
2342
2343 bo = gem_to_amdgpu_bo(obj);
2344 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2345 AMDGPU_GEM_DOMAIN_GTT)))
2346 /* Only VRAM and GTT BOs are supported */
2347 return -EINVAL;
2348
2349 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2350 if (!*mem)
2351 return -ENOMEM;
2352
2353 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2354 if (ret)
2355 goto err_free_mem;
2356
2357 if (size)
2358 *size = amdgpu_bo_size(bo);
2359
2360 if (mmap_offset)
2361 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2362
2363 INIT_LIST_HEAD(&(*mem)->attachments);
2364 mutex_init(&(*mem)->lock);
2365
2366 (*mem)->alloc_flags =
2367 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2368 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2369 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2370 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2371
2372 get_dma_buf(dma_buf);
2373 (*mem)->dmabuf = dma_buf;
2374 (*mem)->bo = bo;
2375 (*mem)->va = va;
2376 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->gmc.is_app_apu ?
2377 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2378
2379 (*mem)->mapped_to_gpu_memory = 0;
2380 (*mem)->process_info = avm->process_info;
2381 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2382 amdgpu_sync_create(&(*mem)->sync);
2383 (*mem)->is_imported = true;
2384
2385 mutex_lock(&avm->process_info->lock);
2386 if (avm->process_info->eviction_fence &&
2387 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
2388 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, (*mem)->domain,
2389 &avm->process_info->eviction_fence->base);
2390 mutex_unlock(&avm->process_info->lock);
2391 if (ret)
2392 goto err_remove_mem;
2393
2394 return 0;
2395
2396err_remove_mem:
2397 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
2398 drm_vma_node_revoke(&obj->vma_node, drm_priv);
2399err_free_mem:
2400 kfree(*mem);
2401 return ret;
2402}
2403
2404int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
2405 uint64_t va, void *drm_priv,
2406 struct kgd_mem **mem, uint64_t *size,
2407 uint64_t *mmap_offset)
2408{
2409 struct drm_gem_object *obj;
2410 uint32_t handle;
2411 int ret;
2412
2413 ret = drm_gem_prime_fd_to_handle(&adev->ddev, adev->kfd.client.file, fd,
2414 &handle);
2415 if (ret)
2416 return ret;
2417 obj = drm_gem_object_lookup(adev->kfd.client.file, handle);
2418 if (!obj) {
2419 ret = -EINVAL;
2420 goto err_release_handle;
2421 }
2422
2423 ret = import_obj_create(adev, obj->dma_buf, obj, va, drm_priv, mem, size,
2424 mmap_offset);
2425 if (ret)
2426 goto err_put_obj;
2427
2428 (*mem)->gem_handle = handle;
2429
2430 return 0;
2431
2432err_put_obj:
2433 drm_gem_object_put(obj);
2434err_release_handle:
2435 drm_gem_handle_delete(adev->kfd.client.file, handle);
2436 return ret;
2437}
2438
2439int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2440 struct dma_buf **dma_buf)
2441{
2442 int ret;
2443
2444 mutex_lock(&mem->lock);
2445 ret = kfd_mem_export_dmabuf(mem);
2446 if (ret)
2447 goto out;
2448
2449 get_dma_buf(mem->dmabuf);
2450 *dma_buf = mem->dmabuf;
2451out:
2452 mutex_unlock(&mem->lock);
2453 return ret;
2454}
2455
2456/* Evict a userptr BO by stopping the queues if necessary
2457 *
2458 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2459 * cannot do any memory allocations, and cannot take any locks that
2460 * are held elsewhere while allocating memory.
2461 *
2462 * It doesn't do anything to the BO itself. The real work happens in
2463 * restore, where we get updated page addresses. This function only
2464 * ensures that GPU access to the BO is stopped.
2465 */
2466int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2467 unsigned long cur_seq, struct kgd_mem *mem)
2468{
2469 struct amdkfd_process_info *process_info = mem->process_info;
2470 int r = 0;
2471
2472 /* Do not process MMU notifications during CRIU restore until
2473 * KFD_CRIU_OP_RESUME IOCTL is received
2474 */
2475 if (READ_ONCE(process_info->block_mmu_notifications))
2476 return 0;
2477
2478 mutex_lock(&process_info->notifier_lock);
2479 mmu_interval_set_seq(mni, cur_seq);
2480
2481 mem->invalid++;
2482 if (++process_info->evicted_bos == 1) {
2483 /* First eviction, stop the queues */
2484 r = kgd2kfd_quiesce_mm(mni->mm,
2485 KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2486 if (r)
2487 pr_err("Failed to quiesce KFD\n");
2488 queue_delayed_work(system_freezable_wq,
2489 &process_info->restore_userptr_work,
2490 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2491 }
2492 mutex_unlock(&process_info->notifier_lock);
2493
2494 return r;
2495}
2496
2497/* Update invalid userptr BOs
2498 *
2499 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2500 * userptr_inval_list and updates user pages for all BOs that have
2501 * been invalidated since their last update.
2502 */
2503static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2504 struct mm_struct *mm)
2505{
2506 struct kgd_mem *mem, *tmp_mem;
2507 struct amdgpu_bo *bo;
2508 struct ttm_operation_ctx ctx = { false, false };
2509 uint32_t invalid;
2510 int ret = 0;
2511
2512 mutex_lock(&process_info->notifier_lock);
2513
2514 /* Move all invalidated BOs to the userptr_inval_list */
2515 list_for_each_entry_safe(mem, tmp_mem,
2516 &process_info->userptr_valid_list,
2517 validate_list)
2518 if (mem->invalid)
2519 list_move_tail(&mem->validate_list,
2520 &process_info->userptr_inval_list);
2521
2522 /* Go through userptr_inval_list and update any invalid user_pages */
2523 list_for_each_entry(mem, &process_info->userptr_inval_list,
2524 validate_list) {
2525 invalid = mem->invalid;
2526 if (!invalid)
2527 /* BO hasn't been invalidated since the last
2528 * revalidation attempt. Keep its page list.
2529 */
2530 continue;
2531
2532 bo = mem->bo;
2533
2534 amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2535 mem->range = NULL;
2536
2537 /* BO reservations and getting user pages (hmm_range_fault)
2538 * must happen outside the notifier lock
2539 */
2540 mutex_unlock(&process_info->notifier_lock);
2541
2542 /* Move the BO to system (CPU) domain if necessary to unmap
2543 * and free the SG table
2544 */
2545 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2546 if (amdgpu_bo_reserve(bo, true))
2547 return -EAGAIN;
2548 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2549 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2550 amdgpu_bo_unreserve(bo);
2551 if (ret) {
2552 pr_err("%s: Failed to invalidate userptr BO\n",
2553 __func__);
2554 return -EAGAIN;
2555 }
2556 }
2557
2558 /* Get updated user pages */
2559 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2560 &mem->range);
2561 if (ret) {
2562 pr_debug("Failed %d to get user pages\n", ret);
2563
2564 /* Return -EFAULT bad address error as success. It will
2565 * fail later with a VM fault if the GPU tries to access
2566 * it. Better than hanging indefinitely with stalled
2567 * user mode queues.
2568 *
2569 * Return other error -EBUSY or -ENOMEM to retry restore
2570 */
2571 if (ret != -EFAULT)
2572 return ret;
2573
2574 ret = 0;
2575 }
2576
2577 mutex_lock(&process_info->notifier_lock);
2578
2579 /* Mark the BO as valid unless it was invalidated
2580 * again concurrently.
2581 */
2582 if (mem->invalid != invalid) {
2583 ret = -EAGAIN;
2584 goto unlock_out;
2585 }
2586 /* set mem valid if mem has hmm range associated */
2587 if (mem->range)
2588 mem->invalid = 0;
2589 }
2590
2591unlock_out:
2592 mutex_unlock(&process_info->notifier_lock);
2593
2594 return ret;
2595}
2596
2597/* Validate invalid userptr BOs
2598 *
2599 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2600 * with new page addresses and waits for the page table updates to complete.
2601 */
2602static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2603{
2604 struct ttm_operation_ctx ctx = { false, false };
2605 struct amdgpu_sync sync;
2606 struct drm_exec exec;
2607
2608 struct amdgpu_vm *peer_vm;
2609 struct kgd_mem *mem, *tmp_mem;
2610 struct amdgpu_bo *bo;
2611 int ret;
2612
2613 amdgpu_sync_create(&sync);
2614
2615 drm_exec_init(&exec, 0, 0);
2616 /* Reserve all BOs and page tables for validation */
2617 drm_exec_until_all_locked(&exec) {
2618 /* Reserve all the page directories */
2619 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2620 vm_list_node) {
2621 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2622 drm_exec_retry_on_contention(&exec);
2623 if (unlikely(ret))
2624 goto unreserve_out;
2625 }
2626
2627 /* Reserve the userptr_inval_list entries to resv_list */
2628 list_for_each_entry(mem, &process_info->userptr_inval_list,
2629 validate_list) {
2630 struct drm_gem_object *gobj;
2631
2632 gobj = &mem->bo->tbo.base;
2633 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2634 drm_exec_retry_on_contention(&exec);
2635 if (unlikely(ret))
2636 goto unreserve_out;
2637 }
2638 }
2639
2640 ret = process_validate_vms(process_info, NULL);
2641 if (ret)
2642 goto unreserve_out;
2643
2644 /* Validate BOs and update GPUVM page tables */
2645 list_for_each_entry_safe(mem, tmp_mem,
2646 &process_info->userptr_inval_list,
2647 validate_list) {
2648 struct kfd_mem_attachment *attachment;
2649
2650 bo = mem->bo;
2651
2652 /* Validate the BO if we got user pages */
2653 if (bo->tbo.ttm->pages[0]) {
2654 amdgpu_bo_placement_from_domain(bo, mem->domain);
2655 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2656 if (ret) {
2657 pr_err("%s: failed to validate BO\n", __func__);
2658 goto unreserve_out;
2659 }
2660 }
2661
2662 /* Update mapping. If the BO was not validated
2663 * (because we couldn't get user pages), this will
2664 * clear the page table entries, which will result in
2665 * VM faults if the GPU tries to access the invalid
2666 * memory.
2667 */
2668 list_for_each_entry(attachment, &mem->attachments, list) {
2669 if (!attachment->is_mapped)
2670 continue;
2671
2672 kfd_mem_dmaunmap_attachment(mem, attachment);
2673 ret = update_gpuvm_pte(mem, attachment, &sync);
2674 if (ret) {
2675 pr_err("%s: update PTE failed\n", __func__);
2676 /* make sure this gets validated again */
2677 mutex_lock(&process_info->notifier_lock);
2678 mem->invalid++;
2679 mutex_unlock(&process_info->notifier_lock);
2680 goto unreserve_out;
2681 }
2682 }
2683 }
2684
2685 /* Update page directories */
2686 ret = process_update_pds(process_info, &sync);
2687
2688unreserve_out:
2689 drm_exec_fini(&exec);
2690 amdgpu_sync_wait(&sync, false);
2691 amdgpu_sync_free(&sync);
2692
2693 return ret;
2694}
2695
2696/* Confirm that all user pages are valid while holding the notifier lock
2697 *
2698 * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2699 */
2700static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2701{
2702 struct kgd_mem *mem, *tmp_mem;
2703 int ret = 0;
2704
2705 list_for_each_entry_safe(mem, tmp_mem,
2706 &process_info->userptr_inval_list,
2707 validate_list) {
2708 bool valid;
2709
2710 /* keep mem without hmm range at userptr_inval_list */
2711 if (!mem->range)
2712 continue;
2713
2714 /* Only check mem with hmm range associated */
2715 valid = amdgpu_ttm_tt_get_user_pages_done(
2716 mem->bo->tbo.ttm, mem->range);
2717
2718 mem->range = NULL;
2719 if (!valid) {
2720 WARN(!mem->invalid, "Invalid BO not marked invalid");
2721 ret = -EAGAIN;
2722 continue;
2723 }
2724
2725 if (mem->invalid) {
2726 WARN(1, "Valid BO is marked invalid");
2727 ret = -EAGAIN;
2728 continue;
2729 }
2730
2731 list_move_tail(&mem->validate_list,
2732 &process_info->userptr_valid_list);
2733 }
2734
2735 return ret;
2736}
2737
2738/* Worker callback to restore evicted userptr BOs
2739 *
2740 * Tries to update and validate all userptr BOs. If successful and no
2741 * concurrent evictions happened, the queues are restarted. Otherwise,
2742 * reschedule for another attempt later.
2743 */
2744static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2745{
2746 struct delayed_work *dwork = to_delayed_work(work);
2747 struct amdkfd_process_info *process_info =
2748 container_of(dwork, struct amdkfd_process_info,
2749 restore_userptr_work);
2750 struct task_struct *usertask;
2751 struct mm_struct *mm;
2752 uint32_t evicted_bos;
2753
2754 mutex_lock(&process_info->notifier_lock);
2755 evicted_bos = process_info->evicted_bos;
2756 mutex_unlock(&process_info->notifier_lock);
2757 if (!evicted_bos)
2758 return;
2759
2760 /* Reference task and mm in case of concurrent process termination */
2761 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2762 if (!usertask)
2763 return;
2764 mm = get_task_mm(usertask);
2765 if (!mm) {
2766 put_task_struct(usertask);
2767 return;
2768 }
2769
2770 mutex_lock(&process_info->lock);
2771
2772 if (update_invalid_user_pages(process_info, mm))
2773 goto unlock_out;
2774 /* userptr_inval_list can be empty if all evicted userptr BOs
2775 * have been freed. In that case there is nothing to validate
2776 * and we can just restart the queues.
2777 */
2778 if (!list_empty(&process_info->userptr_inval_list)) {
2779 if (validate_invalid_user_pages(process_info))
2780 goto unlock_out;
2781 }
2782 /* Final check for concurrent evicton and atomic update. If
2783 * another eviction happens after successful update, it will
2784 * be a first eviction that calls quiesce_mm. The eviction
2785 * reference counting inside KFD will handle this case.
2786 */
2787 mutex_lock(&process_info->notifier_lock);
2788 if (process_info->evicted_bos != evicted_bos)
2789 goto unlock_notifier_out;
2790
2791 if (confirm_valid_user_pages_locked(process_info)) {
2792 WARN(1, "User pages unexpectedly invalid");
2793 goto unlock_notifier_out;
2794 }
2795
2796 process_info->evicted_bos = evicted_bos = 0;
2797
2798 if (kgd2kfd_resume_mm(mm)) {
2799 pr_err("%s: Failed to resume KFD\n", __func__);
2800 /* No recovery from this failure. Probably the CP is
2801 * hanging. No point trying again.
2802 */
2803 }
2804
2805unlock_notifier_out:
2806 mutex_unlock(&process_info->notifier_lock);
2807unlock_out:
2808 mutex_unlock(&process_info->lock);
2809
2810 /* If validation failed, reschedule another attempt */
2811 if (evicted_bos) {
2812 queue_delayed_work(system_freezable_wq,
2813 &process_info->restore_userptr_work,
2814 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2815
2816 kfd_smi_event_queue_restore_rescheduled(mm);
2817 }
2818 mmput(mm);
2819 put_task_struct(usertask);
2820}
2821
2822static void replace_eviction_fence(struct dma_fence __rcu **ef,
2823 struct dma_fence *new_ef)
2824{
2825 struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true
2826 /* protected by process_info->lock */);
2827
2828 /* If we're replacing an unsignaled eviction fence, that fence will
2829 * never be signaled, and if anyone is still waiting on that fence,
2830 * they will hang forever. This should never happen. We should only
2831 * replace the fence in restore_work that only gets scheduled after
2832 * eviction work signaled the fence.
2833 */
2834 WARN_ONCE(!dma_fence_is_signaled(old_ef),
2835 "Replacing unsignaled eviction fence");
2836 dma_fence_put(old_ef);
2837}
2838
2839/** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2840 * KFD process identified by process_info
2841 *
2842 * @process_info: amdkfd_process_info of the KFD process
2843 *
2844 * After memory eviction, restore thread calls this function. The function
2845 * should be called when the Process is still valid. BO restore involves -
2846 *
2847 * 1. Release old eviction fence and create new one
2848 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2849 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2850 * BOs that need to be reserved.
2851 * 4. Reserve all the BOs
2852 * 5. Validate of PD and PT BOs.
2853 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2854 * 7. Add fence to all PD and PT BOs.
2855 * 8. Unreserve all BOs
2856 */
2857int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu **ef)
2858{
2859 struct amdkfd_process_info *process_info = info;
2860 struct amdgpu_vm *peer_vm;
2861 struct kgd_mem *mem;
2862 struct list_head duplicate_save;
2863 struct amdgpu_sync sync_obj;
2864 unsigned long failed_size = 0;
2865 unsigned long total_size = 0;
2866 struct drm_exec exec;
2867 int ret;
2868
2869 INIT_LIST_HEAD(&duplicate_save);
2870
2871 mutex_lock(&process_info->lock);
2872
2873 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
2874 drm_exec_until_all_locked(&exec) {
2875 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2876 vm_list_node) {
2877 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2878 drm_exec_retry_on_contention(&exec);
2879 if (unlikely(ret)) {
2880 pr_err("Locking VM PD failed, ret: %d\n", ret);
2881 goto ttm_reserve_fail;
2882 }
2883 }
2884
2885 /* Reserve all BOs and page tables/directory. Add all BOs from
2886 * kfd_bo_list to ctx.list
2887 */
2888 list_for_each_entry(mem, &process_info->kfd_bo_list,
2889 validate_list) {
2890 struct drm_gem_object *gobj;
2891
2892 gobj = &mem->bo->tbo.base;
2893 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2894 drm_exec_retry_on_contention(&exec);
2895 if (unlikely(ret)) {
2896 pr_err("drm_exec_prepare_obj failed, ret: %d\n", ret);
2897 goto ttm_reserve_fail;
2898 }
2899 }
2900 }
2901
2902 amdgpu_sync_create(&sync_obj);
2903
2904 /* Validate BOs managed by KFD */
2905 list_for_each_entry(mem, &process_info->kfd_bo_list,
2906 validate_list) {
2907
2908 struct amdgpu_bo *bo = mem->bo;
2909 uint32_t domain = mem->domain;
2910 struct dma_resv_iter cursor;
2911 struct dma_fence *fence;
2912
2913 total_size += amdgpu_bo_size(bo);
2914
2915 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2916 if (ret) {
2917 pr_debug("Memory eviction: Validate BOs failed\n");
2918 failed_size += amdgpu_bo_size(bo);
2919 ret = amdgpu_amdkfd_bo_validate(bo,
2920 AMDGPU_GEM_DOMAIN_GTT, false);
2921 if (ret) {
2922 pr_debug("Memory eviction: Try again\n");
2923 goto validate_map_fail;
2924 }
2925 }
2926 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2927 DMA_RESV_USAGE_KERNEL, fence) {
2928 ret = amdgpu_sync_fence(&sync_obj, fence);
2929 if (ret) {
2930 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2931 goto validate_map_fail;
2932 }
2933 }
2934 }
2935
2936 if (failed_size)
2937 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2938
2939 /* Validate PDs, PTs and evicted DMABuf imports last. Otherwise BO
2940 * validations above would invalidate DMABuf imports again.
2941 */
2942 ret = process_validate_vms(process_info, &exec.ticket);
2943 if (ret) {
2944 pr_debug("Validating VMs failed, ret: %d\n", ret);
2945 goto validate_map_fail;
2946 }
2947
2948 /* Update mappings managed by KFD. */
2949 list_for_each_entry(mem, &process_info->kfd_bo_list,
2950 validate_list) {
2951 struct kfd_mem_attachment *attachment;
2952
2953 list_for_each_entry(attachment, &mem->attachments, list) {
2954 if (!attachment->is_mapped)
2955 continue;
2956
2957 if (attachment->bo_va->base.bo->tbo.pin_count)
2958 continue;
2959
2960 kfd_mem_dmaunmap_attachment(mem, attachment);
2961 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2962 if (ret) {
2963 pr_debug("Memory eviction: update PTE failed. Try again\n");
2964 goto validate_map_fail;
2965 }
2966 }
2967 }
2968
2969 /* Update mappings not managed by KFD */
2970 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2971 vm_list_node) {
2972 struct amdgpu_device *adev = amdgpu_ttm_adev(
2973 peer_vm->root.bo->tbo.bdev);
2974
2975 ret = amdgpu_vm_handle_moved(adev, peer_vm, &exec.ticket);
2976 if (ret) {
2977 pr_debug("Memory eviction: handle moved failed. Try again\n");
2978 goto validate_map_fail;
2979 }
2980 }
2981
2982 /* Update page directories */
2983 ret = process_update_pds(process_info, &sync_obj);
2984 if (ret) {
2985 pr_debug("Memory eviction: update PDs failed. Try again\n");
2986 goto validate_map_fail;
2987 }
2988
2989 /* Sync with fences on all the page tables. They implicitly depend on any
2990 * move fences from amdgpu_vm_handle_moved above.
2991 */
2992 ret = process_sync_pds_resv(process_info, &sync_obj);
2993 if (ret) {
2994 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2995 goto validate_map_fail;
2996 }
2997
2998 /* Wait for validate and PT updates to finish */
2999 amdgpu_sync_wait(&sync_obj, false);
3000
3001 /* The old eviction fence may be unsignaled if restore happens
3002 * after a GPU reset or suspend/resume. Keep the old fence in that
3003 * case. Otherwise release the old eviction fence and create new
3004 * one, because fence only goes from unsignaled to signaled once
3005 * and cannot be reused. Use context and mm from the old fence.
3006 *
3007 * If an old eviction fence signals after this check, that's OK.
3008 * Anyone signaling an eviction fence must stop the queues first
3009 * and schedule another restore worker.
3010 */
3011 if (dma_fence_is_signaled(&process_info->eviction_fence->base)) {
3012 struct amdgpu_amdkfd_fence *new_fence =
3013 amdgpu_amdkfd_fence_create(
3014 process_info->eviction_fence->base.context,
3015 process_info->eviction_fence->mm,
3016 NULL);
3017
3018 if (!new_fence) {
3019 pr_err("Failed to create eviction fence\n");
3020 ret = -ENOMEM;
3021 goto validate_map_fail;
3022 }
3023 dma_fence_put(&process_info->eviction_fence->base);
3024 process_info->eviction_fence = new_fence;
3025 replace_eviction_fence(ef, dma_fence_get(&new_fence->base));
3026 } else {
3027 WARN_ONCE(*ef != &process_info->eviction_fence->base,
3028 "KFD eviction fence doesn't match KGD process_info");
3029 }
3030
3031 /* Attach new eviction fence to all BOs except pinned ones */
3032 list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
3033 if (mem->bo->tbo.pin_count)
3034 continue;
3035
3036 dma_resv_add_fence(mem->bo->tbo.base.resv,
3037 &process_info->eviction_fence->base,
3038 DMA_RESV_USAGE_BOOKKEEP);
3039 }
3040 /* Attach eviction fence to PD / PT BOs and DMABuf imports */
3041 list_for_each_entry(peer_vm, &process_info->vm_list_head,
3042 vm_list_node) {
3043 struct amdgpu_bo *bo = peer_vm->root.bo;
3044
3045 dma_resv_add_fence(bo->tbo.base.resv,
3046 &process_info->eviction_fence->base,
3047 DMA_RESV_USAGE_BOOKKEEP);
3048 }
3049
3050validate_map_fail:
3051 amdgpu_sync_free(&sync_obj);
3052ttm_reserve_fail:
3053 drm_exec_fini(&exec);
3054 mutex_unlock(&process_info->lock);
3055 return ret;
3056}
3057
3058int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
3059{
3060 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3061 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
3062 int ret;
3063
3064 if (!info || !gws)
3065 return -EINVAL;
3066
3067 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
3068 if (!*mem)
3069 return -ENOMEM;
3070
3071 mutex_init(&(*mem)->lock);
3072 INIT_LIST_HEAD(&(*mem)->attachments);
3073 (*mem)->bo = amdgpu_bo_ref(gws_bo);
3074 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
3075 (*mem)->process_info = process_info;
3076 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
3077 amdgpu_sync_create(&(*mem)->sync);
3078
3079
3080 /* Validate gws bo the first time it is added to process */
3081 mutex_lock(&(*mem)->process_info->lock);
3082 ret = amdgpu_bo_reserve(gws_bo, false);
3083 if (unlikely(ret)) {
3084 pr_err("Reserve gws bo failed %d\n", ret);
3085 goto bo_reservation_failure;
3086 }
3087
3088 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
3089 if (ret) {
3090 pr_err("GWS BO validate failed %d\n", ret);
3091 goto bo_validation_failure;
3092 }
3093 /* GWS resource is shared b/t amdgpu and amdkfd
3094 * Add process eviction fence to bo so they can
3095 * evict each other.
3096 */
3097 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
3098 if (ret)
3099 goto reserve_shared_fail;
3100 dma_resv_add_fence(gws_bo->tbo.base.resv,
3101 &process_info->eviction_fence->base,
3102 DMA_RESV_USAGE_BOOKKEEP);
3103 amdgpu_bo_unreserve(gws_bo);
3104 mutex_unlock(&(*mem)->process_info->lock);
3105
3106 return ret;
3107
3108reserve_shared_fail:
3109bo_validation_failure:
3110 amdgpu_bo_unreserve(gws_bo);
3111bo_reservation_failure:
3112 mutex_unlock(&(*mem)->process_info->lock);
3113 amdgpu_sync_free(&(*mem)->sync);
3114 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
3115 amdgpu_bo_unref(&gws_bo);
3116 mutex_destroy(&(*mem)->lock);
3117 kfree(*mem);
3118 *mem = NULL;
3119 return ret;
3120}
3121
3122int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
3123{
3124 int ret;
3125 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3126 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
3127 struct amdgpu_bo *gws_bo = kgd_mem->bo;
3128
3129 /* Remove BO from process's validate list so restore worker won't touch
3130 * it anymore
3131 */
3132 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
3133
3134 ret = amdgpu_bo_reserve(gws_bo, false);
3135 if (unlikely(ret)) {
3136 pr_err("Reserve gws bo failed %d\n", ret);
3137 //TODO add BO back to validate_list?
3138 return ret;
3139 }
3140 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
3141 process_info->eviction_fence);
3142 amdgpu_bo_unreserve(gws_bo);
3143 amdgpu_sync_free(&kgd_mem->sync);
3144 amdgpu_bo_unref(&gws_bo);
3145 mutex_destroy(&kgd_mem->lock);
3146 kfree(mem);
3147 return 0;
3148}
3149
3150/* Returns GPU-specific tiling mode information */
3151int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
3152 struct tile_config *config)
3153{
3154 config->gb_addr_config = adev->gfx.config.gb_addr_config;
3155 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
3156 config->num_tile_configs =
3157 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
3158 config->macro_tile_config_ptr =
3159 adev->gfx.config.macrotile_mode_array;
3160 config->num_macro_tile_configs =
3161 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
3162
3163 /* Those values are not set from GFX9 onwards */
3164 config->num_banks = adev->gfx.config.num_banks;
3165 config->num_ranks = adev->gfx.config.num_ranks;
3166
3167 return 0;
3168}
3169
3170bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
3171{
3172 struct kfd_mem_attachment *entry;
3173
3174 list_for_each_entry(entry, &mem->attachments, list) {
3175 if (entry->is_mapped && entry->adev == adev)
3176 return true;
3177 }
3178 return false;
3179}
3180
3181#if defined(CONFIG_DEBUG_FS)
3182
3183int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3184{
3185
3186 spin_lock(&kfd_mem_limit.mem_limit_lock);
3187 seq_printf(m, "System mem used %lldM out of %lluM\n",
3188 (kfd_mem_limit.system_mem_used >> 20),
3189 (kfd_mem_limit.max_system_mem_limit >> 20));
3190 seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3191 (kfd_mem_limit.ttm_mem_used >> 20),
3192 (kfd_mem_limit.max_ttm_mem_limit >> 20));
3193 spin_unlock(&kfd_mem_limit.mem_limit_lock);
3194
3195 return 0;
3196}
3197
3198#endif
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include <linux/dma-buf.h>
24#include <linux/list.h>
25#include <linux/pagemap.h>
26#include <linux/sched/mm.h>
27#include <linux/sched/task.h>
28#include <linux/fdtable.h>
29#include <drm/ttm/ttm_tt.h>
30
31#include <drm/drm_exec.h>
32
33#include "amdgpu_object.h"
34#include "amdgpu_gem.h"
35#include "amdgpu_vm.h"
36#include "amdgpu_hmm.h"
37#include "amdgpu_amdkfd.h"
38#include "amdgpu_dma_buf.h"
39#include <uapi/linux/kfd_ioctl.h>
40#include "amdgpu_xgmi.h"
41#include "kfd_priv.h"
42#include "kfd_smi_events.h"
43
44/* Userptr restore delay, just long enough to allow consecutive VM
45 * changes to accumulate
46 */
47#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
48#define AMDGPU_RESERVE_MEM_LIMIT (3UL << 29)
49
50/*
51 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
52 * BO chunk
53 */
54#define VRAM_AVAILABLITY_ALIGN (1 << 21)
55
56/* Impose limit on how much memory KFD can use */
57static struct {
58 uint64_t max_system_mem_limit;
59 uint64_t max_ttm_mem_limit;
60 int64_t system_mem_used;
61 int64_t ttm_mem_used;
62 spinlock_t mem_limit_lock;
63} kfd_mem_limit;
64
65static const char * const domain_bit_to_string[] = {
66 "CPU",
67 "GTT",
68 "VRAM",
69 "GDS",
70 "GWS",
71 "OA"
72};
73
74#define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
75
76static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
77
78static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
79 struct kgd_mem *mem)
80{
81 struct kfd_mem_attachment *entry;
82
83 list_for_each_entry(entry, &mem->attachments, list)
84 if (entry->bo_va->base.vm == avm)
85 return true;
86
87 return false;
88}
89
90/**
91 * reuse_dmamap() - Check whether adev can share the original
92 * userptr BO
93 *
94 * If both adev and bo_adev are in direct mapping or
95 * in the same iommu group, they can share the original BO.
96 *
97 * @adev: Device to which can or cannot share the original BO
98 * @bo_adev: Device to which allocated BO belongs to
99 *
100 * Return: returns true if adev can share original userptr BO,
101 * false otherwise.
102 */
103static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
104{
105 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
106 (adev->dev->iommu_group == bo_adev->dev->iommu_group);
107}
108
109/* Set memory usage limits. Current, limits are
110 * System (TTM + userptr) memory - 15/16th System RAM
111 * TTM memory - 3/8th System RAM
112 */
113void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
114{
115 struct sysinfo si;
116 uint64_t mem;
117
118 if (kfd_mem_limit.max_system_mem_limit)
119 return;
120
121 si_meminfo(&si);
122 mem = si.totalram - si.totalhigh;
123 mem *= si.mem_unit;
124
125 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
126 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6);
127 if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT)
128 kfd_mem_limit.max_system_mem_limit >>= 1;
129 else
130 kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT;
131
132 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
133 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
134 (kfd_mem_limit.max_system_mem_limit >> 20),
135 (kfd_mem_limit.max_ttm_mem_limit >> 20));
136}
137
138void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
139{
140 kfd_mem_limit.system_mem_used += size;
141}
142
143/* Estimate page table size needed to represent a given memory size
144 *
145 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
146 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
147 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
148 * for 2MB pages for TLB efficiency. However, small allocations and
149 * fragmented system memory still need some 4KB pages. We choose a
150 * compromise that should work in most cases without reserving too
151 * much memory for page tables unnecessarily (factor 16K, >> 14).
152 */
153
154#define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
155
156/**
157 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
158 * of buffer.
159 *
160 * @adev: Device to which allocated BO belongs to
161 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
162 * equivalent to amdgpu_bo_size(BO)
163 * @alloc_flag: Flag used in allocating a BO as noted above
164 * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
165 * managed as one compute node in driver for app
166 *
167 * Return:
168 * returns -ENOMEM in case of error, ZERO otherwise
169 */
170int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
171 uint64_t size, u32 alloc_flag, int8_t xcp_id)
172{
173 uint64_t reserved_for_pt =
174 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
175 size_t system_mem_needed, ttm_mem_needed, vram_needed;
176 int ret = 0;
177 uint64_t vram_size = 0;
178
179 system_mem_needed = 0;
180 ttm_mem_needed = 0;
181 vram_needed = 0;
182 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
183 system_mem_needed = size;
184 ttm_mem_needed = size;
185 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
186 /*
187 * Conservatively round up the allocation requirement to 2 MB
188 * to avoid fragmentation caused by 4K allocations in the tail
189 * 2M BO chunk.
190 */
191 vram_needed = size;
192 /*
193 * For GFX 9.4.3, get the VRAM size from XCP structs
194 */
195 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
196 return -EINVAL;
197
198 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
199 if (adev->gmc.is_app_apu) {
200 system_mem_needed = size;
201 ttm_mem_needed = size;
202 }
203 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
204 system_mem_needed = size;
205 } else if (!(alloc_flag &
206 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
207 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
208 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
209 return -ENOMEM;
210 }
211
212 spin_lock(&kfd_mem_limit.mem_limit_lock);
213
214 if (kfd_mem_limit.system_mem_used + system_mem_needed >
215 kfd_mem_limit.max_system_mem_limit)
216 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
217
218 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
219 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
220 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
221 kfd_mem_limit.max_ttm_mem_limit) ||
222 (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
223 vram_size - reserved_for_pt)) {
224 ret = -ENOMEM;
225 goto release;
226 }
227
228 /* Update memory accounting by decreasing available system
229 * memory, TTM memory and GPU memory as computed above
230 */
231 WARN_ONCE(vram_needed && !adev,
232 "adev reference can't be null when vram is used");
233 if (adev && xcp_id >= 0) {
234 adev->kfd.vram_used[xcp_id] += vram_needed;
235 adev->kfd.vram_used_aligned[xcp_id] += adev->gmc.is_app_apu ?
236 vram_needed :
237 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
238 }
239 kfd_mem_limit.system_mem_used += system_mem_needed;
240 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
241
242release:
243 spin_unlock(&kfd_mem_limit.mem_limit_lock);
244 return ret;
245}
246
247void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
248 uint64_t size, u32 alloc_flag, int8_t xcp_id)
249{
250 spin_lock(&kfd_mem_limit.mem_limit_lock);
251
252 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
253 kfd_mem_limit.system_mem_used -= size;
254 kfd_mem_limit.ttm_mem_used -= size;
255 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
256 WARN_ONCE(!adev,
257 "adev reference can't be null when alloc mem flags vram is set");
258 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
259 goto release;
260
261 if (adev) {
262 adev->kfd.vram_used[xcp_id] -= size;
263 if (adev->gmc.is_app_apu) {
264 adev->kfd.vram_used_aligned[xcp_id] -= size;
265 kfd_mem_limit.system_mem_used -= size;
266 kfd_mem_limit.ttm_mem_used -= size;
267 } else {
268 adev->kfd.vram_used_aligned[xcp_id] -=
269 ALIGN(size, VRAM_AVAILABLITY_ALIGN);
270 }
271 }
272 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
273 kfd_mem_limit.system_mem_used -= size;
274 } else if (!(alloc_flag &
275 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
276 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
277 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
278 goto release;
279 }
280 WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
281 "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
282 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
283 "KFD TTM memory accounting unbalanced");
284 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
285 "KFD system memory accounting unbalanced");
286
287release:
288 spin_unlock(&kfd_mem_limit.mem_limit_lock);
289}
290
291void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
292{
293 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
294 u32 alloc_flags = bo->kfd_bo->alloc_flags;
295 u64 size = amdgpu_bo_size(bo);
296
297 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
298 bo->xcp_id);
299
300 kfree(bo->kfd_bo);
301}
302
303/**
304 * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
305 * about USERPTR or DOOREBELL or MMIO BO.
306 *
307 * @adev: Device for which dmamap BO is being created
308 * @mem: BO of peer device that is being DMA mapped. Provides parameters
309 * in building the dmamap BO
310 * @bo_out: Output parameter updated with handle of dmamap BO
311 */
312static int
313create_dmamap_sg_bo(struct amdgpu_device *adev,
314 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
315{
316 struct drm_gem_object *gem_obj;
317 int ret;
318 uint64_t flags = 0;
319
320 ret = amdgpu_bo_reserve(mem->bo, false);
321 if (ret)
322 return ret;
323
324 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
325 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
326 AMDGPU_GEM_CREATE_UNCACHED);
327
328 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
329 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
330 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
331
332 amdgpu_bo_unreserve(mem->bo);
333
334 if (ret) {
335 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
336 return -EINVAL;
337 }
338
339 *bo_out = gem_to_amdgpu_bo(gem_obj);
340 (*bo_out)->parent = amdgpu_bo_ref(mem->bo);
341 return ret;
342}
343
344/* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
345 * reservation object.
346 *
347 * @bo: [IN] Remove eviction fence(s) from this BO
348 * @ef: [IN] This eviction fence is removed if it
349 * is present in the shared list.
350 *
351 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
352 */
353static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
354 struct amdgpu_amdkfd_fence *ef)
355{
356 struct dma_fence *replacement;
357
358 if (!ef)
359 return -EINVAL;
360
361 /* TODO: Instead of block before we should use the fence of the page
362 * table update and TLB flush here directly.
363 */
364 replacement = dma_fence_get_stub();
365 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
366 replacement, DMA_RESV_USAGE_BOOKKEEP);
367 dma_fence_put(replacement);
368 return 0;
369}
370
371int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
372{
373 struct amdgpu_bo *root = bo;
374 struct amdgpu_vm_bo_base *vm_bo;
375 struct amdgpu_vm *vm;
376 struct amdkfd_process_info *info;
377 struct amdgpu_amdkfd_fence *ef;
378 int ret;
379
380 /* we can always get vm_bo from root PD bo.*/
381 while (root->parent)
382 root = root->parent;
383
384 vm_bo = root->vm_bo;
385 if (!vm_bo)
386 return 0;
387
388 vm = vm_bo->vm;
389 if (!vm)
390 return 0;
391
392 info = vm->process_info;
393 if (!info || !info->eviction_fence)
394 return 0;
395
396 ef = container_of(dma_fence_get(&info->eviction_fence->base),
397 struct amdgpu_amdkfd_fence, base);
398
399 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
400 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
401 dma_resv_unlock(bo->tbo.base.resv);
402
403 dma_fence_put(&ef->base);
404 return ret;
405}
406
407static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
408 bool wait)
409{
410 struct ttm_operation_ctx ctx = { false, false };
411 int ret;
412
413 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
414 "Called with userptr BO"))
415 return -EINVAL;
416
417 amdgpu_bo_placement_from_domain(bo, domain);
418
419 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
420 if (ret)
421 goto validate_fail;
422 if (wait)
423 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
424
425validate_fail:
426 return ret;
427}
428
429static int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
430 uint32_t domain,
431 struct dma_fence *fence)
432{
433 int ret = amdgpu_bo_reserve(bo, false);
434
435 if (ret)
436 return ret;
437
438 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
439 if (ret)
440 goto unreserve_out;
441
442 ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
443 if (ret)
444 goto unreserve_out;
445
446 dma_resv_add_fence(bo->tbo.base.resv, fence,
447 DMA_RESV_USAGE_BOOKKEEP);
448
449unreserve_out:
450 amdgpu_bo_unreserve(bo);
451
452 return ret;
453}
454
455static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
456{
457 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
458}
459
460/* vm_validate_pt_pd_bos - Validate page table and directory BOs
461 *
462 * Page directories are not updated here because huge page handling
463 * during page table updates can invalidate page directory entries
464 * again. Page directories are only updated after updating page
465 * tables.
466 */
467static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
468{
469 struct amdgpu_bo *pd = vm->root.bo;
470 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
471 int ret;
472
473 ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
474 if (ret) {
475 pr_err("failed to validate PT BOs\n");
476 return ret;
477 }
478
479 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
480
481 return 0;
482}
483
484static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
485{
486 struct amdgpu_bo *pd = vm->root.bo;
487 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
488 int ret;
489
490 ret = amdgpu_vm_update_pdes(adev, vm, false);
491 if (ret)
492 return ret;
493
494 return amdgpu_sync_fence(sync, vm->last_update);
495}
496
497static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
498{
499 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
500 AMDGPU_VM_MTYPE_DEFAULT;
501
502 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
503 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
504 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
505 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
506
507 return amdgpu_gem_va_map_flags(adev, mapping_flags);
508}
509
510/**
511 * create_sg_table() - Create an sg_table for a contiguous DMA addr range
512 * @addr: The starting address to point to
513 * @size: Size of memory area in bytes being pointed to
514 *
515 * Allocates an instance of sg_table and initializes it to point to memory
516 * area specified by input parameters. The address used to build is assumed
517 * to be DMA mapped, if needed.
518 *
519 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
520 * because they are physically contiguous.
521 *
522 * Return: Initialized instance of SG Table or NULL
523 */
524static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
525{
526 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
527
528 if (!sg)
529 return NULL;
530 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
531 kfree(sg);
532 return NULL;
533 }
534 sg_dma_address(sg->sgl) = addr;
535 sg->sgl->length = size;
536#ifdef CONFIG_NEED_SG_DMA_LENGTH
537 sg->sgl->dma_length = size;
538#endif
539 return sg;
540}
541
542static int
543kfd_mem_dmamap_userptr(struct kgd_mem *mem,
544 struct kfd_mem_attachment *attachment)
545{
546 enum dma_data_direction direction =
547 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
548 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
549 struct ttm_operation_ctx ctx = {.interruptible = true};
550 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
551 struct amdgpu_device *adev = attachment->adev;
552 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
553 struct ttm_tt *ttm = bo->tbo.ttm;
554 int ret;
555
556 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
557 return -EINVAL;
558
559 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
560 if (unlikely(!ttm->sg))
561 return -ENOMEM;
562
563 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
564 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
565 ttm->num_pages, 0,
566 (u64)ttm->num_pages << PAGE_SHIFT,
567 GFP_KERNEL);
568 if (unlikely(ret))
569 goto free_sg;
570
571 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
572 if (unlikely(ret))
573 goto release_sg;
574
575 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
576 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
577 if (ret)
578 goto unmap_sg;
579
580 return 0;
581
582unmap_sg:
583 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
584release_sg:
585 pr_err("DMA map userptr failed: %d\n", ret);
586 sg_free_table(ttm->sg);
587free_sg:
588 kfree(ttm->sg);
589 ttm->sg = NULL;
590 return ret;
591}
592
593static int
594kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
595{
596 struct ttm_operation_ctx ctx = {.interruptible = true};
597 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
598 int ret;
599
600 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
601 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
602 if (ret)
603 return ret;
604
605 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
606 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
607}
608
609/**
610 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
611 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
612 * @attachment: Virtual address attachment of the BO on accessing device
613 *
614 * An access request from the device that owns DOORBELL does not require DMA mapping.
615 * This is because the request doesn't go through PCIe root complex i.e. it instead
616 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
617 *
618 * In contrast, all access requests for MMIO need to be DMA mapped without regard to
619 * device ownership. This is because access requests for MMIO go through PCIe root
620 * complex.
621 *
622 * This is accomplished in two steps:
623 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
624 * in updating requesting device's page table
625 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU
626 * accessible. This allows an update of requesting device's page table
627 * with entries associated with DOOREBELL or MMIO memory
628 *
629 * This method is invoked in the following contexts:
630 * - Mapping of DOORBELL or MMIO BO of same or peer device
631 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access
632 *
633 * Return: ZERO if successful, NON-ZERO otherwise
634 */
635static int
636kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
637 struct kfd_mem_attachment *attachment)
638{
639 struct ttm_operation_ctx ctx = {.interruptible = true};
640 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
641 struct amdgpu_device *adev = attachment->adev;
642 struct ttm_tt *ttm = bo->tbo.ttm;
643 enum dma_data_direction dir;
644 dma_addr_t dma_addr;
645 bool mmio;
646 int ret;
647
648 /* Expect SG Table of dmapmap BO to be NULL */
649 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
650 if (unlikely(ttm->sg)) {
651 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
652 return -EINVAL;
653 }
654
655 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
656 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
657 dma_addr = mem->bo->tbo.sg->sgl->dma_address;
658 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
659 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
660 dma_addr = dma_map_resource(adev->dev, dma_addr,
661 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
662 ret = dma_mapping_error(adev->dev, dma_addr);
663 if (unlikely(ret))
664 return ret;
665 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
666
667 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
668 if (unlikely(!ttm->sg)) {
669 ret = -ENOMEM;
670 goto unmap_sg;
671 }
672
673 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
674 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
675 if (unlikely(ret))
676 goto free_sg;
677
678 return ret;
679
680free_sg:
681 sg_free_table(ttm->sg);
682 kfree(ttm->sg);
683 ttm->sg = NULL;
684unmap_sg:
685 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
686 dir, DMA_ATTR_SKIP_CPU_SYNC);
687 return ret;
688}
689
690static int
691kfd_mem_dmamap_attachment(struct kgd_mem *mem,
692 struct kfd_mem_attachment *attachment)
693{
694 switch (attachment->type) {
695 case KFD_MEM_ATT_SHARED:
696 return 0;
697 case KFD_MEM_ATT_USERPTR:
698 return kfd_mem_dmamap_userptr(mem, attachment);
699 case KFD_MEM_ATT_DMABUF:
700 return kfd_mem_dmamap_dmabuf(attachment);
701 case KFD_MEM_ATT_SG:
702 return kfd_mem_dmamap_sg_bo(mem, attachment);
703 default:
704 WARN_ON_ONCE(1);
705 }
706 return -EINVAL;
707}
708
709static void
710kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
711 struct kfd_mem_attachment *attachment)
712{
713 enum dma_data_direction direction =
714 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
715 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
716 struct ttm_operation_ctx ctx = {.interruptible = false};
717 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
718 struct amdgpu_device *adev = attachment->adev;
719 struct ttm_tt *ttm = bo->tbo.ttm;
720
721 if (unlikely(!ttm->sg))
722 return;
723
724 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
725 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
726
727 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
728 sg_free_table(ttm->sg);
729 kfree(ttm->sg);
730 ttm->sg = NULL;
731}
732
733static void
734kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
735{
736 /* This is a no-op. We don't want to trigger eviction fences when
737 * unmapping DMABufs. Therefore the invalidation (moving to system
738 * domain) is done in kfd_mem_dmamap_dmabuf.
739 */
740}
741
742/**
743 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
744 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
745 * @attachment: Virtual address attachment of the BO on accessing device
746 *
747 * The method performs following steps:
748 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible
749 * - Free SG Table that is used to encapsulate DMA mapped memory of
750 * peer device's DOORBELL or MMIO memory
751 *
752 * This method is invoked in the following contexts:
753 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory
754 * Eviction of DOOREBELL or MMIO BO on device having access to its memory
755 *
756 * Return: void
757 */
758static void
759kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
760 struct kfd_mem_attachment *attachment)
761{
762 struct ttm_operation_ctx ctx = {.interruptible = true};
763 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
764 struct amdgpu_device *adev = attachment->adev;
765 struct ttm_tt *ttm = bo->tbo.ttm;
766 enum dma_data_direction dir;
767
768 if (unlikely(!ttm->sg)) {
769 pr_debug("SG Table of BO is NULL");
770 return;
771 }
772
773 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
774 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
775
776 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
777 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
778 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
779 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
780 sg_free_table(ttm->sg);
781 kfree(ttm->sg);
782 ttm->sg = NULL;
783 bo->tbo.sg = NULL;
784}
785
786static void
787kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
788 struct kfd_mem_attachment *attachment)
789{
790 switch (attachment->type) {
791 case KFD_MEM_ATT_SHARED:
792 break;
793 case KFD_MEM_ATT_USERPTR:
794 kfd_mem_dmaunmap_userptr(mem, attachment);
795 break;
796 case KFD_MEM_ATT_DMABUF:
797 kfd_mem_dmaunmap_dmabuf(attachment);
798 break;
799 case KFD_MEM_ATT_SG:
800 kfd_mem_dmaunmap_sg_bo(mem, attachment);
801 break;
802 default:
803 WARN_ON_ONCE(1);
804 }
805}
806
807static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
808{
809 if (!mem->dmabuf) {
810 struct amdgpu_device *bo_adev;
811 struct dma_buf *dmabuf;
812 int r, fd;
813
814 bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
815 r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file,
816 mem->gem_handle,
817 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
818 DRM_RDWR : 0, &fd);
819 if (r)
820 return r;
821 dmabuf = dma_buf_get(fd);
822 close_fd(fd);
823 if (WARN_ON_ONCE(IS_ERR(dmabuf)))
824 return PTR_ERR(dmabuf);
825 mem->dmabuf = dmabuf;
826 }
827
828 return 0;
829}
830
831static int
832kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
833 struct amdgpu_bo **bo)
834{
835 struct drm_gem_object *gobj;
836 int ret;
837
838 ret = kfd_mem_export_dmabuf(mem);
839 if (ret)
840 return ret;
841
842 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
843 if (IS_ERR(gobj))
844 return PTR_ERR(gobj);
845
846 *bo = gem_to_amdgpu_bo(gobj);
847 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
848
849 return 0;
850}
851
852/* kfd_mem_attach - Add a BO to a VM
853 *
854 * Everything that needs to bo done only once when a BO is first added
855 * to a VM. It can later be mapped and unmapped many times without
856 * repeating these steps.
857 *
858 * 0. Create BO for DMA mapping, if needed
859 * 1. Allocate and initialize BO VA entry data structure
860 * 2. Add BO to the VM
861 * 3. Determine ASIC-specific PTE flags
862 * 4. Alloc page tables and directories if needed
863 * 4a. Validate new page tables and directories
864 */
865static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
866 struct amdgpu_vm *vm, bool is_aql)
867{
868 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
869 unsigned long bo_size = mem->bo->tbo.base.size;
870 uint64_t va = mem->va;
871 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
872 struct amdgpu_bo *bo[2] = {NULL, NULL};
873 struct amdgpu_bo_va *bo_va;
874 bool same_hive = false;
875 int i, ret;
876
877 if (!va) {
878 pr_err("Invalid VA when adding BO to VM\n");
879 return -EINVAL;
880 }
881
882 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
883 *
884 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
885 * In contrast the access path of VRAM BOs depens upon the type of
886 * link that connects the peer device. Access over PCIe is allowed
887 * if peer device has large BAR. In contrast, access over xGMI is
888 * allowed for both small and large BAR configurations of peer device
889 */
890 if ((adev != bo_adev && !adev->gmc.is_app_apu) &&
891 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
892 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
893 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
894 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
895 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
896 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
897 return -EINVAL;
898 }
899
900 for (i = 0; i <= is_aql; i++) {
901 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
902 if (unlikely(!attachment[i])) {
903 ret = -ENOMEM;
904 goto unwind;
905 }
906
907 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
908 va + bo_size, vm);
909
910 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
911 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
912 (mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) ||
913 same_hive) {
914 /* Mappings on the local GPU, or VRAM mappings in the
915 * local hive, or userptr, or GTT mapping can reuse dma map
916 * address space share the original BO
917 */
918 attachment[i]->type = KFD_MEM_ATT_SHARED;
919 bo[i] = mem->bo;
920 drm_gem_object_get(&bo[i]->tbo.base);
921 } else if (i > 0) {
922 /* Multiple mappings on the same GPU share the BO */
923 attachment[i]->type = KFD_MEM_ATT_SHARED;
924 bo[i] = bo[0];
925 drm_gem_object_get(&bo[i]->tbo.base);
926 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
927 /* Create an SG BO to DMA-map userptrs on other GPUs */
928 attachment[i]->type = KFD_MEM_ATT_USERPTR;
929 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
930 if (ret)
931 goto unwind;
932 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
933 } else if (mem->bo->tbo.type == ttm_bo_type_sg) {
934 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
935 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
936 "Handing invalid SG BO in ATTACH request");
937 attachment[i]->type = KFD_MEM_ATT_SG;
938 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
939 if (ret)
940 goto unwind;
941 /* Enable acces to GTT and VRAM BOs of peer devices */
942 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
943 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
944 attachment[i]->type = KFD_MEM_ATT_DMABUF;
945 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
946 if (ret)
947 goto unwind;
948 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
949 } else {
950 WARN_ONCE(true, "Handling invalid ATTACH request");
951 ret = -EINVAL;
952 goto unwind;
953 }
954
955 /* Add BO to VM internal data structures */
956 ret = amdgpu_bo_reserve(bo[i], false);
957 if (ret) {
958 pr_debug("Unable to reserve BO during memory attach");
959 goto unwind;
960 }
961 bo_va = amdgpu_vm_bo_find(vm, bo[i]);
962 if (!bo_va)
963 bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
964 else
965 ++bo_va->ref_count;
966 attachment[i]->bo_va = bo_va;
967 amdgpu_bo_unreserve(bo[i]);
968 if (unlikely(!attachment[i]->bo_va)) {
969 ret = -ENOMEM;
970 pr_err("Failed to add BO object to VM. ret == %d\n",
971 ret);
972 goto unwind;
973 }
974 attachment[i]->va = va;
975 attachment[i]->pte_flags = get_pte_flags(adev, mem);
976 attachment[i]->adev = adev;
977 list_add(&attachment[i]->list, &mem->attachments);
978
979 va += bo_size;
980 }
981
982 return 0;
983
984unwind:
985 for (; i >= 0; i--) {
986 if (!attachment[i])
987 continue;
988 if (attachment[i]->bo_va) {
989 amdgpu_bo_reserve(bo[i], true);
990 if (--attachment[i]->bo_va->ref_count == 0)
991 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
992 amdgpu_bo_unreserve(bo[i]);
993 list_del(&attachment[i]->list);
994 }
995 if (bo[i])
996 drm_gem_object_put(&bo[i]->tbo.base);
997 kfree(attachment[i]);
998 }
999 return ret;
1000}
1001
1002static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
1003{
1004 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
1005
1006 pr_debug("\t remove VA 0x%llx in entry %p\n",
1007 attachment->va, attachment);
1008 if (--attachment->bo_va->ref_count == 0)
1009 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
1010 drm_gem_object_put(&bo->tbo.base);
1011 list_del(&attachment->list);
1012 kfree(attachment);
1013}
1014
1015static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
1016 struct amdkfd_process_info *process_info,
1017 bool userptr)
1018{
1019 mutex_lock(&process_info->lock);
1020 if (userptr)
1021 list_add_tail(&mem->validate_list,
1022 &process_info->userptr_valid_list);
1023 else
1024 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
1025 mutex_unlock(&process_info->lock);
1026}
1027
1028static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
1029 struct amdkfd_process_info *process_info)
1030{
1031 mutex_lock(&process_info->lock);
1032 list_del(&mem->validate_list);
1033 mutex_unlock(&process_info->lock);
1034}
1035
1036/* Initializes user pages. It registers the MMU notifier and validates
1037 * the userptr BO in the GTT domain.
1038 *
1039 * The BO must already be on the userptr_valid_list. Otherwise an
1040 * eviction and restore may happen that leaves the new BO unmapped
1041 * with the user mode queues running.
1042 *
1043 * Takes the process_info->lock to protect against concurrent restore
1044 * workers.
1045 *
1046 * Returns 0 for success, negative errno for errors.
1047 */
1048static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1049 bool criu_resume)
1050{
1051 struct amdkfd_process_info *process_info = mem->process_info;
1052 struct amdgpu_bo *bo = mem->bo;
1053 struct ttm_operation_ctx ctx = { true, false };
1054 struct hmm_range *range;
1055 int ret = 0;
1056
1057 mutex_lock(&process_info->lock);
1058
1059 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1060 if (ret) {
1061 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1062 goto out;
1063 }
1064
1065 ret = amdgpu_hmm_register(bo, user_addr);
1066 if (ret) {
1067 pr_err("%s: Failed to register MMU notifier: %d\n",
1068 __func__, ret);
1069 goto out;
1070 }
1071
1072 if (criu_resume) {
1073 /*
1074 * During a CRIU restore operation, the userptr buffer objects
1075 * will be validated in the restore_userptr_work worker at a
1076 * later stage when it is scheduled by another ioctl called by
1077 * CRIU master process for the target pid for restore.
1078 */
1079 mutex_lock(&process_info->notifier_lock);
1080 mem->invalid++;
1081 mutex_unlock(&process_info->notifier_lock);
1082 mutex_unlock(&process_info->lock);
1083 return 0;
1084 }
1085
1086 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1087 if (ret) {
1088 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1089 goto unregister_out;
1090 }
1091
1092 ret = amdgpu_bo_reserve(bo, true);
1093 if (ret) {
1094 pr_err("%s: Failed to reserve BO\n", __func__);
1095 goto release_out;
1096 }
1097 amdgpu_bo_placement_from_domain(bo, mem->domain);
1098 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1099 if (ret)
1100 pr_err("%s: failed to validate BO\n", __func__);
1101 amdgpu_bo_unreserve(bo);
1102
1103release_out:
1104 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1105unregister_out:
1106 if (ret)
1107 amdgpu_hmm_unregister(bo);
1108out:
1109 mutex_unlock(&process_info->lock);
1110 return ret;
1111}
1112
1113/* Reserving a BO and its page table BOs must happen atomically to
1114 * avoid deadlocks. Some operations update multiple VMs at once. Track
1115 * all the reservation info in a context structure. Optionally a sync
1116 * object can track VM updates.
1117 */
1118struct bo_vm_reservation_context {
1119 /* DRM execution context for the reservation */
1120 struct drm_exec exec;
1121 /* Number of VMs reserved */
1122 unsigned int n_vms;
1123 /* Pointer to sync object */
1124 struct amdgpu_sync *sync;
1125};
1126
1127enum bo_vm_match {
1128 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
1129 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
1130 BO_VM_ALL, /* Match all VMs a BO was added to */
1131};
1132
1133/**
1134 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1135 * @mem: KFD BO structure.
1136 * @vm: the VM to reserve.
1137 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1138 */
1139static int reserve_bo_and_vm(struct kgd_mem *mem,
1140 struct amdgpu_vm *vm,
1141 struct bo_vm_reservation_context *ctx)
1142{
1143 struct amdgpu_bo *bo = mem->bo;
1144 int ret;
1145
1146 WARN_ON(!vm);
1147
1148 ctx->n_vms = 1;
1149 ctx->sync = &mem->sync;
1150 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1151 drm_exec_until_all_locked(&ctx->exec) {
1152 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1153 drm_exec_retry_on_contention(&ctx->exec);
1154 if (unlikely(ret))
1155 goto error;
1156
1157 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1158 drm_exec_retry_on_contention(&ctx->exec);
1159 if (unlikely(ret))
1160 goto error;
1161 }
1162 return 0;
1163
1164error:
1165 pr_err("Failed to reserve buffers in ttm.\n");
1166 drm_exec_fini(&ctx->exec);
1167 return ret;
1168}
1169
1170/**
1171 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1172 * @mem: KFD BO structure.
1173 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1174 * is used. Otherwise, a single VM associated with the BO.
1175 * @map_type: the mapping status that will be used to filter the VMs.
1176 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1177 *
1178 * Returns 0 for success, negative for failure.
1179 */
1180static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1181 struct amdgpu_vm *vm, enum bo_vm_match map_type,
1182 struct bo_vm_reservation_context *ctx)
1183{
1184 struct kfd_mem_attachment *entry;
1185 struct amdgpu_bo *bo = mem->bo;
1186 int ret;
1187
1188 ctx->sync = &mem->sync;
1189 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1190 drm_exec_until_all_locked(&ctx->exec) {
1191 ctx->n_vms = 0;
1192 list_for_each_entry(entry, &mem->attachments, list) {
1193 if ((vm && vm != entry->bo_va->base.vm) ||
1194 (entry->is_mapped != map_type
1195 && map_type != BO_VM_ALL))
1196 continue;
1197
1198 ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1199 &ctx->exec, 2);
1200 drm_exec_retry_on_contention(&ctx->exec);
1201 if (unlikely(ret))
1202 goto error;
1203 ++ctx->n_vms;
1204 }
1205
1206 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1207 drm_exec_retry_on_contention(&ctx->exec);
1208 if (unlikely(ret))
1209 goto error;
1210 }
1211 return 0;
1212
1213error:
1214 pr_err("Failed to reserve buffers in ttm.\n");
1215 drm_exec_fini(&ctx->exec);
1216 return ret;
1217}
1218
1219/**
1220 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1221 * @ctx: Reservation context to unreserve
1222 * @wait: Optionally wait for a sync object representing pending VM updates
1223 * @intr: Whether the wait is interruptible
1224 *
1225 * Also frees any resources allocated in
1226 * reserve_bo_and_(cond_)vm(s). Returns the status from
1227 * amdgpu_sync_wait.
1228 */
1229static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1230 bool wait, bool intr)
1231{
1232 int ret = 0;
1233
1234 if (wait)
1235 ret = amdgpu_sync_wait(ctx->sync, intr);
1236
1237 drm_exec_fini(&ctx->exec);
1238 ctx->sync = NULL;
1239 return ret;
1240}
1241
1242static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1243 struct kfd_mem_attachment *entry,
1244 struct amdgpu_sync *sync)
1245{
1246 struct amdgpu_bo_va *bo_va = entry->bo_va;
1247 struct amdgpu_device *adev = entry->adev;
1248 struct amdgpu_vm *vm = bo_va->base.vm;
1249
1250 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1251
1252 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1253
1254 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1255}
1256
1257static int update_gpuvm_pte(struct kgd_mem *mem,
1258 struct kfd_mem_attachment *entry,
1259 struct amdgpu_sync *sync)
1260{
1261 struct amdgpu_bo_va *bo_va = entry->bo_va;
1262 struct amdgpu_device *adev = entry->adev;
1263 int ret;
1264
1265 ret = kfd_mem_dmamap_attachment(mem, entry);
1266 if (ret)
1267 return ret;
1268
1269 /* Update the page tables */
1270 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1271 if (ret) {
1272 pr_err("amdgpu_vm_bo_update failed\n");
1273 return ret;
1274 }
1275
1276 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1277}
1278
1279static int map_bo_to_gpuvm(struct kgd_mem *mem,
1280 struct kfd_mem_attachment *entry,
1281 struct amdgpu_sync *sync,
1282 bool no_update_pte)
1283{
1284 int ret;
1285
1286 /* Set virtual address for the allocation */
1287 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1288 amdgpu_bo_size(entry->bo_va->base.bo),
1289 entry->pte_flags);
1290 if (ret) {
1291 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1292 entry->va, ret);
1293 return ret;
1294 }
1295
1296 if (no_update_pte)
1297 return 0;
1298
1299 ret = update_gpuvm_pte(mem, entry, sync);
1300 if (ret) {
1301 pr_err("update_gpuvm_pte() failed\n");
1302 goto update_gpuvm_pte_failed;
1303 }
1304
1305 return 0;
1306
1307update_gpuvm_pte_failed:
1308 unmap_bo_from_gpuvm(mem, entry, sync);
1309 kfd_mem_dmaunmap_attachment(mem, entry);
1310 return ret;
1311}
1312
1313static int process_validate_vms(struct amdkfd_process_info *process_info)
1314{
1315 struct amdgpu_vm *peer_vm;
1316 int ret;
1317
1318 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1319 vm_list_node) {
1320 ret = vm_validate_pt_pd_bos(peer_vm);
1321 if (ret)
1322 return ret;
1323 }
1324
1325 return 0;
1326}
1327
1328static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1329 struct amdgpu_sync *sync)
1330{
1331 struct amdgpu_vm *peer_vm;
1332 int ret;
1333
1334 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1335 vm_list_node) {
1336 struct amdgpu_bo *pd = peer_vm->root.bo;
1337
1338 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1339 AMDGPU_SYNC_NE_OWNER,
1340 AMDGPU_FENCE_OWNER_KFD);
1341 if (ret)
1342 return ret;
1343 }
1344
1345 return 0;
1346}
1347
1348static int process_update_pds(struct amdkfd_process_info *process_info,
1349 struct amdgpu_sync *sync)
1350{
1351 struct amdgpu_vm *peer_vm;
1352 int ret;
1353
1354 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1355 vm_list_node) {
1356 ret = vm_update_pds(peer_vm, sync);
1357 if (ret)
1358 return ret;
1359 }
1360
1361 return 0;
1362}
1363
1364static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1365 struct dma_fence **ef)
1366{
1367 struct amdkfd_process_info *info = NULL;
1368 int ret;
1369
1370 if (!*process_info) {
1371 info = kzalloc(sizeof(*info), GFP_KERNEL);
1372 if (!info)
1373 return -ENOMEM;
1374
1375 mutex_init(&info->lock);
1376 mutex_init(&info->notifier_lock);
1377 INIT_LIST_HEAD(&info->vm_list_head);
1378 INIT_LIST_HEAD(&info->kfd_bo_list);
1379 INIT_LIST_HEAD(&info->userptr_valid_list);
1380 INIT_LIST_HEAD(&info->userptr_inval_list);
1381
1382 info->eviction_fence =
1383 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1384 current->mm,
1385 NULL);
1386 if (!info->eviction_fence) {
1387 pr_err("Failed to create eviction fence\n");
1388 ret = -ENOMEM;
1389 goto create_evict_fence_fail;
1390 }
1391
1392 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1393 INIT_DELAYED_WORK(&info->restore_userptr_work,
1394 amdgpu_amdkfd_restore_userptr_worker);
1395
1396 *process_info = info;
1397 }
1398
1399 vm->process_info = *process_info;
1400
1401 /* Validate page directory and attach eviction fence */
1402 ret = amdgpu_bo_reserve(vm->root.bo, true);
1403 if (ret)
1404 goto reserve_pd_fail;
1405 ret = vm_validate_pt_pd_bos(vm);
1406 if (ret) {
1407 pr_err("validate_pt_pd_bos() failed\n");
1408 goto validate_pd_fail;
1409 }
1410 ret = amdgpu_bo_sync_wait(vm->root.bo,
1411 AMDGPU_FENCE_OWNER_KFD, false);
1412 if (ret)
1413 goto wait_pd_fail;
1414 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1415 if (ret)
1416 goto reserve_shared_fail;
1417 dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1418 &vm->process_info->eviction_fence->base,
1419 DMA_RESV_USAGE_BOOKKEEP);
1420 amdgpu_bo_unreserve(vm->root.bo);
1421
1422 /* Update process info */
1423 mutex_lock(&vm->process_info->lock);
1424 list_add_tail(&vm->vm_list_node,
1425 &(vm->process_info->vm_list_head));
1426 vm->process_info->n_vms++;
1427
1428 *ef = dma_fence_get(&vm->process_info->eviction_fence->base);
1429 mutex_unlock(&vm->process_info->lock);
1430
1431 return 0;
1432
1433reserve_shared_fail:
1434wait_pd_fail:
1435validate_pd_fail:
1436 amdgpu_bo_unreserve(vm->root.bo);
1437reserve_pd_fail:
1438 vm->process_info = NULL;
1439 if (info) {
1440 dma_fence_put(&info->eviction_fence->base);
1441 *process_info = NULL;
1442 put_pid(info->pid);
1443create_evict_fence_fail:
1444 mutex_destroy(&info->lock);
1445 mutex_destroy(&info->notifier_lock);
1446 kfree(info);
1447 }
1448 return ret;
1449}
1450
1451/**
1452 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1453 * @bo: Handle of buffer object being pinned
1454 * @domain: Domain into which BO should be pinned
1455 *
1456 * - USERPTR BOs are UNPINNABLE and will return error
1457 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1458 * PIN count incremented. It is valid to PIN a BO multiple times
1459 *
1460 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1461 */
1462static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1463{
1464 int ret = 0;
1465
1466 ret = amdgpu_bo_reserve(bo, false);
1467 if (unlikely(ret))
1468 return ret;
1469
1470 ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1471 if (ret)
1472 pr_err("Error in Pinning BO to domain: %d\n", domain);
1473
1474 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1475 amdgpu_bo_unreserve(bo);
1476
1477 return ret;
1478}
1479
1480/**
1481 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1482 * @bo: Handle of buffer object being unpinned
1483 *
1484 * - Is a illegal request for USERPTR BOs and is ignored
1485 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1486 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1487 */
1488static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1489{
1490 int ret = 0;
1491
1492 ret = amdgpu_bo_reserve(bo, false);
1493 if (unlikely(ret))
1494 return;
1495
1496 amdgpu_bo_unpin(bo);
1497 amdgpu_bo_unreserve(bo);
1498}
1499
1500int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1501 struct amdgpu_vm *avm, u32 pasid)
1502
1503{
1504 int ret;
1505
1506 /* Free the original amdgpu allocated pasid,
1507 * will be replaced with kfd allocated pasid.
1508 */
1509 if (avm->pasid) {
1510 amdgpu_pasid_free(avm->pasid);
1511 amdgpu_vm_set_pasid(adev, avm, 0);
1512 }
1513
1514 ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1515 if (ret)
1516 return ret;
1517
1518 return 0;
1519}
1520
1521int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1522 struct amdgpu_vm *avm,
1523 void **process_info,
1524 struct dma_fence **ef)
1525{
1526 int ret;
1527
1528 /* Already a compute VM? */
1529 if (avm->process_info)
1530 return -EINVAL;
1531
1532 /* Convert VM into a compute VM */
1533 ret = amdgpu_vm_make_compute(adev, avm);
1534 if (ret)
1535 return ret;
1536
1537 /* Initialize KFD part of the VM and process info */
1538 ret = init_kfd_vm(avm, process_info, ef);
1539 if (ret)
1540 return ret;
1541
1542 amdgpu_vm_set_task_info(avm);
1543
1544 return 0;
1545}
1546
1547void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1548 struct amdgpu_vm *vm)
1549{
1550 struct amdkfd_process_info *process_info = vm->process_info;
1551
1552 if (!process_info)
1553 return;
1554
1555 /* Update process info */
1556 mutex_lock(&process_info->lock);
1557 process_info->n_vms--;
1558 list_del(&vm->vm_list_node);
1559 mutex_unlock(&process_info->lock);
1560
1561 vm->process_info = NULL;
1562
1563 /* Release per-process resources when last compute VM is destroyed */
1564 if (!process_info->n_vms) {
1565 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1566 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1567 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1568
1569 dma_fence_put(&process_info->eviction_fence->base);
1570 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1571 put_pid(process_info->pid);
1572 mutex_destroy(&process_info->lock);
1573 mutex_destroy(&process_info->notifier_lock);
1574 kfree(process_info);
1575 }
1576}
1577
1578void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1579 void *drm_priv)
1580{
1581 struct amdgpu_vm *avm;
1582
1583 if (WARN_ON(!adev || !drm_priv))
1584 return;
1585
1586 avm = drm_priv_to_vm(drm_priv);
1587
1588 pr_debug("Releasing process vm %p\n", avm);
1589
1590 /* The original pasid of amdgpu vm has already been
1591 * released during making a amdgpu vm to a compute vm
1592 * The current pasid is managed by kfd and will be
1593 * released on kfd process destroy. Set amdgpu pasid
1594 * to 0 to avoid duplicate release.
1595 */
1596 amdgpu_vm_release_compute(adev, avm);
1597}
1598
1599uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1600{
1601 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1602 struct amdgpu_bo *pd = avm->root.bo;
1603 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1604
1605 if (adev->asic_type < CHIP_VEGA10)
1606 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1607 return avm->pd_phys_addr;
1608}
1609
1610void amdgpu_amdkfd_block_mmu_notifications(void *p)
1611{
1612 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1613
1614 mutex_lock(&pinfo->lock);
1615 WRITE_ONCE(pinfo->block_mmu_notifications, true);
1616 mutex_unlock(&pinfo->lock);
1617}
1618
1619int amdgpu_amdkfd_criu_resume(void *p)
1620{
1621 int ret = 0;
1622 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1623
1624 mutex_lock(&pinfo->lock);
1625 pr_debug("scheduling work\n");
1626 mutex_lock(&pinfo->notifier_lock);
1627 pinfo->evicted_bos++;
1628 mutex_unlock(&pinfo->notifier_lock);
1629 if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1630 ret = -EINVAL;
1631 goto out_unlock;
1632 }
1633 WRITE_ONCE(pinfo->block_mmu_notifications, false);
1634 queue_delayed_work(system_freezable_wq,
1635 &pinfo->restore_userptr_work, 0);
1636
1637out_unlock:
1638 mutex_unlock(&pinfo->lock);
1639 return ret;
1640}
1641
1642size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1643 uint8_t xcp_id)
1644{
1645 uint64_t reserved_for_pt =
1646 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1647 ssize_t available;
1648 uint64_t vram_available, system_mem_available, ttm_mem_available;
1649
1650 spin_lock(&kfd_mem_limit.mem_limit_lock);
1651 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1652 - adev->kfd.vram_used_aligned[xcp_id]
1653 - atomic64_read(&adev->vram_pin_size)
1654 - reserved_for_pt;
1655
1656 if (adev->gmc.is_app_apu) {
1657 system_mem_available = no_system_mem_limit ?
1658 kfd_mem_limit.max_system_mem_limit :
1659 kfd_mem_limit.max_system_mem_limit -
1660 kfd_mem_limit.system_mem_used;
1661
1662 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1663 kfd_mem_limit.ttm_mem_used;
1664
1665 available = min3(system_mem_available, ttm_mem_available,
1666 vram_available);
1667 available = ALIGN_DOWN(available, PAGE_SIZE);
1668 } else {
1669 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1670 }
1671
1672 spin_unlock(&kfd_mem_limit.mem_limit_lock);
1673
1674 if (available < 0)
1675 available = 0;
1676
1677 return available;
1678}
1679
1680int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1681 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1682 void *drm_priv, struct kgd_mem **mem,
1683 uint64_t *offset, uint32_t flags, bool criu_resume)
1684{
1685 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1686 struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1687 enum ttm_bo_type bo_type = ttm_bo_type_device;
1688 struct sg_table *sg = NULL;
1689 uint64_t user_addr = 0;
1690 struct amdgpu_bo *bo;
1691 struct drm_gem_object *gobj = NULL;
1692 u32 domain, alloc_domain;
1693 uint64_t aligned_size;
1694 int8_t xcp_id = -1;
1695 u64 alloc_flags;
1696 int ret;
1697
1698 /*
1699 * Check on which domain to allocate BO
1700 */
1701 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1702 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1703
1704 if (adev->gmc.is_app_apu) {
1705 domain = AMDGPU_GEM_DOMAIN_GTT;
1706 alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1707 alloc_flags = 0;
1708 } else {
1709 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1710 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1711 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1712 }
1713 xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1714 0 : fpriv->xcp_id;
1715 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1716 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1717 alloc_flags = 0;
1718 } else {
1719 domain = AMDGPU_GEM_DOMAIN_GTT;
1720 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1721 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1722
1723 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1724 if (!offset || !*offset)
1725 return -EINVAL;
1726 user_addr = untagged_addr(*offset);
1727 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1728 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1729 bo_type = ttm_bo_type_sg;
1730 if (size > UINT_MAX)
1731 return -EINVAL;
1732 sg = create_sg_table(*offset, size);
1733 if (!sg)
1734 return -ENOMEM;
1735 } else {
1736 return -EINVAL;
1737 }
1738 }
1739
1740 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1741 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1742 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT)
1743 alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT;
1744 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1745 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1746
1747 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1748 if (!*mem) {
1749 ret = -ENOMEM;
1750 goto err;
1751 }
1752 INIT_LIST_HEAD(&(*mem)->attachments);
1753 mutex_init(&(*mem)->lock);
1754 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1755
1756 /* Workaround for AQL queue wraparound bug. Map the same
1757 * memory twice. That means we only actually allocate half
1758 * the memory.
1759 */
1760 if ((*mem)->aql_queue)
1761 size >>= 1;
1762 aligned_size = PAGE_ALIGN(size);
1763
1764 (*mem)->alloc_flags = flags;
1765
1766 amdgpu_sync_create(&(*mem)->sync);
1767
1768 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1769 xcp_id);
1770 if (ret) {
1771 pr_debug("Insufficient memory\n");
1772 goto err_reserve_limit;
1773 }
1774
1775 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1776 va, (*mem)->aql_queue ? size << 1 : size,
1777 domain_string(alloc_domain), xcp_id);
1778
1779 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1780 bo_type, NULL, &gobj, xcp_id + 1);
1781 if (ret) {
1782 pr_debug("Failed to create BO on domain %s. ret %d\n",
1783 domain_string(alloc_domain), ret);
1784 goto err_bo_create;
1785 }
1786 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1787 if (ret) {
1788 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1789 goto err_node_allow;
1790 }
1791 ret = drm_gem_handle_create(adev->kfd.client.file, gobj, &(*mem)->gem_handle);
1792 if (ret)
1793 goto err_gem_handle_create;
1794 bo = gem_to_amdgpu_bo(gobj);
1795 if (bo_type == ttm_bo_type_sg) {
1796 bo->tbo.sg = sg;
1797 bo->tbo.ttm->sg = sg;
1798 }
1799 bo->kfd_bo = *mem;
1800 (*mem)->bo = bo;
1801 if (user_addr)
1802 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1803
1804 (*mem)->va = va;
1805 (*mem)->domain = domain;
1806 (*mem)->mapped_to_gpu_memory = 0;
1807 (*mem)->process_info = avm->process_info;
1808
1809 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1810
1811 if (user_addr) {
1812 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1813 ret = init_user_pages(*mem, user_addr, criu_resume);
1814 if (ret)
1815 goto allocate_init_user_pages_failed;
1816 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1817 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1818 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1819 if (ret) {
1820 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1821 goto err_pin_bo;
1822 }
1823 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1824 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1825 } else {
1826 mutex_lock(&avm->process_info->lock);
1827 if (avm->process_info->eviction_fence &&
1828 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
1829 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain,
1830 &avm->process_info->eviction_fence->base);
1831 mutex_unlock(&avm->process_info->lock);
1832 if (ret)
1833 goto err_validate_bo;
1834 }
1835
1836 if (offset)
1837 *offset = amdgpu_bo_mmap_offset(bo);
1838
1839 return 0;
1840
1841allocate_init_user_pages_failed:
1842err_pin_bo:
1843err_validate_bo:
1844 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1845 drm_gem_handle_delete(adev->kfd.client.file, (*mem)->gem_handle);
1846err_gem_handle_create:
1847 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1848err_node_allow:
1849 /* Don't unreserve system mem limit twice */
1850 goto err_reserve_limit;
1851err_bo_create:
1852 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1853err_reserve_limit:
1854 mutex_destroy(&(*mem)->lock);
1855 if (gobj)
1856 drm_gem_object_put(gobj);
1857 else
1858 kfree(*mem);
1859err:
1860 if (sg) {
1861 sg_free_table(sg);
1862 kfree(sg);
1863 }
1864 return ret;
1865}
1866
1867int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1868 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1869 uint64_t *size)
1870{
1871 struct amdkfd_process_info *process_info = mem->process_info;
1872 unsigned long bo_size = mem->bo->tbo.base.size;
1873 bool use_release_notifier = (mem->bo->kfd_bo == mem);
1874 struct kfd_mem_attachment *entry, *tmp;
1875 struct bo_vm_reservation_context ctx;
1876 unsigned int mapped_to_gpu_memory;
1877 int ret;
1878 bool is_imported = false;
1879
1880 mutex_lock(&mem->lock);
1881
1882 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1883 if (mem->alloc_flags &
1884 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1885 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1886 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1887 }
1888
1889 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1890 is_imported = mem->is_imported;
1891 mutex_unlock(&mem->lock);
1892 /* lock is not needed after this, since mem is unused and will
1893 * be freed anyway
1894 */
1895
1896 if (mapped_to_gpu_memory > 0) {
1897 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1898 mem->va, bo_size);
1899 return -EBUSY;
1900 }
1901
1902 /* Make sure restore workers don't access the BO any more */
1903 mutex_lock(&process_info->lock);
1904 list_del(&mem->validate_list);
1905 mutex_unlock(&process_info->lock);
1906
1907 /* Cleanup user pages and MMU notifiers */
1908 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1909 amdgpu_hmm_unregister(mem->bo);
1910 mutex_lock(&process_info->notifier_lock);
1911 amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1912 mutex_unlock(&process_info->notifier_lock);
1913 }
1914
1915 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1916 if (unlikely(ret))
1917 return ret;
1918
1919 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1920 process_info->eviction_fence);
1921 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1922 mem->va + bo_size * (1 + mem->aql_queue));
1923
1924 /* Remove from VM internal data structures */
1925 list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
1926 kfd_mem_dmaunmap_attachment(mem, entry);
1927 kfd_mem_detach(entry);
1928 }
1929
1930 ret = unreserve_bo_and_vms(&ctx, false, false);
1931
1932 /* Free the sync object */
1933 amdgpu_sync_free(&mem->sync);
1934
1935 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1936 * remap BO. We need to free it.
1937 */
1938 if (mem->bo->tbo.sg) {
1939 sg_free_table(mem->bo->tbo.sg);
1940 kfree(mem->bo->tbo.sg);
1941 }
1942
1943 /* Update the size of the BO being freed if it was allocated from
1944 * VRAM and is not imported. For APP APU VRAM allocations are done
1945 * in GTT domain
1946 */
1947 if (size) {
1948 if (!is_imported &&
1949 (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1950 (adev->gmc.is_app_apu &&
1951 mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1952 *size = bo_size;
1953 else
1954 *size = 0;
1955 }
1956
1957 /* Free the BO*/
1958 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1959 drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle);
1960 if (mem->dmabuf) {
1961 dma_buf_put(mem->dmabuf);
1962 mem->dmabuf = NULL;
1963 }
1964 mutex_destroy(&mem->lock);
1965
1966 /* If this releases the last reference, it will end up calling
1967 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1968 * this needs to be the last call here.
1969 */
1970 drm_gem_object_put(&mem->bo->tbo.base);
1971
1972 /*
1973 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
1974 * explicitly free it here.
1975 */
1976 if (!use_release_notifier)
1977 kfree(mem);
1978
1979 return ret;
1980}
1981
1982int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1983 struct amdgpu_device *adev, struct kgd_mem *mem,
1984 void *drm_priv)
1985{
1986 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1987 int ret;
1988 struct amdgpu_bo *bo;
1989 uint32_t domain;
1990 struct kfd_mem_attachment *entry;
1991 struct bo_vm_reservation_context ctx;
1992 unsigned long bo_size;
1993 bool is_invalid_userptr = false;
1994
1995 bo = mem->bo;
1996 if (!bo) {
1997 pr_err("Invalid BO when mapping memory to GPU\n");
1998 return -EINVAL;
1999 }
2000
2001 /* Make sure restore is not running concurrently. Since we
2002 * don't map invalid userptr BOs, we rely on the next restore
2003 * worker to do the mapping
2004 */
2005 mutex_lock(&mem->process_info->lock);
2006
2007 /* Lock notifier lock. If we find an invalid userptr BO, we can be
2008 * sure that the MMU notifier is no longer running
2009 * concurrently and the queues are actually stopped
2010 */
2011 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2012 mutex_lock(&mem->process_info->notifier_lock);
2013 is_invalid_userptr = !!mem->invalid;
2014 mutex_unlock(&mem->process_info->notifier_lock);
2015 }
2016
2017 mutex_lock(&mem->lock);
2018
2019 domain = mem->domain;
2020 bo_size = bo->tbo.base.size;
2021
2022 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
2023 mem->va,
2024 mem->va + bo_size * (1 + mem->aql_queue),
2025 avm, domain_string(domain));
2026
2027 if (!kfd_mem_is_attached(avm, mem)) {
2028 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
2029 if (ret)
2030 goto out;
2031 }
2032
2033 ret = reserve_bo_and_vm(mem, avm, &ctx);
2034 if (unlikely(ret))
2035 goto out;
2036
2037 /* Userptr can be marked as "not invalid", but not actually be
2038 * validated yet (still in the system domain). In that case
2039 * the queues are still stopped and we can leave mapping for
2040 * the next restore worker
2041 */
2042 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
2043 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
2044 is_invalid_userptr = true;
2045
2046 ret = vm_validate_pt_pd_bos(avm);
2047 if (unlikely(ret))
2048 goto out_unreserve;
2049
2050 list_for_each_entry(entry, &mem->attachments, list) {
2051 if (entry->bo_va->base.vm != avm || entry->is_mapped)
2052 continue;
2053
2054 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2055 entry->va, entry->va + bo_size, entry);
2056
2057 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2058 is_invalid_userptr);
2059 if (ret) {
2060 pr_err("Failed to map bo to gpuvm\n");
2061 goto out_unreserve;
2062 }
2063
2064 ret = vm_update_pds(avm, ctx.sync);
2065 if (ret) {
2066 pr_err("Failed to update page directories\n");
2067 goto out_unreserve;
2068 }
2069
2070 entry->is_mapped = true;
2071 mem->mapped_to_gpu_memory++;
2072 pr_debug("\t INC mapping count %d\n",
2073 mem->mapped_to_gpu_memory);
2074 }
2075
2076 ret = unreserve_bo_and_vms(&ctx, false, false);
2077
2078 goto out;
2079
2080out_unreserve:
2081 unreserve_bo_and_vms(&ctx, false, false);
2082out:
2083 mutex_unlock(&mem->process_info->lock);
2084 mutex_unlock(&mem->lock);
2085 return ret;
2086}
2087
2088int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv)
2089{
2090 struct kfd_mem_attachment *entry;
2091 struct amdgpu_vm *vm;
2092 int ret;
2093
2094 vm = drm_priv_to_vm(drm_priv);
2095
2096 mutex_lock(&mem->lock);
2097
2098 ret = amdgpu_bo_reserve(mem->bo, true);
2099 if (ret)
2100 goto out;
2101
2102 list_for_each_entry(entry, &mem->attachments, list) {
2103 if (entry->bo_va->base.vm != vm)
2104 continue;
2105 if (entry->bo_va->base.bo->tbo.ttm &&
2106 !entry->bo_va->base.bo->tbo.ttm->sg)
2107 continue;
2108
2109 kfd_mem_dmaunmap_attachment(mem, entry);
2110 }
2111
2112 amdgpu_bo_unreserve(mem->bo);
2113out:
2114 mutex_unlock(&mem->lock);
2115
2116 return ret;
2117}
2118
2119int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2120 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2121{
2122 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2123 unsigned long bo_size = mem->bo->tbo.base.size;
2124 struct kfd_mem_attachment *entry;
2125 struct bo_vm_reservation_context ctx;
2126 int ret;
2127
2128 mutex_lock(&mem->lock);
2129
2130 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2131 if (unlikely(ret))
2132 goto out;
2133 /* If no VMs were reserved, it means the BO wasn't actually mapped */
2134 if (ctx.n_vms == 0) {
2135 ret = -EINVAL;
2136 goto unreserve_out;
2137 }
2138
2139 ret = vm_validate_pt_pd_bos(avm);
2140 if (unlikely(ret))
2141 goto unreserve_out;
2142
2143 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2144 mem->va,
2145 mem->va + bo_size * (1 + mem->aql_queue),
2146 avm);
2147
2148 list_for_each_entry(entry, &mem->attachments, list) {
2149 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2150 continue;
2151
2152 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2153 entry->va, entry->va + bo_size, entry);
2154
2155 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2156 entry->is_mapped = false;
2157
2158 mem->mapped_to_gpu_memory--;
2159 pr_debug("\t DEC mapping count %d\n",
2160 mem->mapped_to_gpu_memory);
2161 }
2162
2163unreserve_out:
2164 unreserve_bo_and_vms(&ctx, false, false);
2165out:
2166 mutex_unlock(&mem->lock);
2167 return ret;
2168}
2169
2170int amdgpu_amdkfd_gpuvm_sync_memory(
2171 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2172{
2173 struct amdgpu_sync sync;
2174 int ret;
2175
2176 amdgpu_sync_create(&sync);
2177
2178 mutex_lock(&mem->lock);
2179 amdgpu_sync_clone(&mem->sync, &sync);
2180 mutex_unlock(&mem->lock);
2181
2182 ret = amdgpu_sync_wait(&sync, intr);
2183 amdgpu_sync_free(&sync);
2184 return ret;
2185}
2186
2187/**
2188 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2189 * @adev: Device to which allocated BO belongs
2190 * @bo: Buffer object to be mapped
2191 *
2192 * Before return, bo reference count is incremented. To release the reference and unpin/
2193 * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2194 */
2195int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo)
2196{
2197 int ret;
2198
2199 ret = amdgpu_bo_reserve(bo, true);
2200 if (ret) {
2201 pr_err("Failed to reserve bo. ret %d\n", ret);
2202 goto err_reserve_bo_failed;
2203 }
2204
2205 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2206 if (ret) {
2207 pr_err("Failed to pin bo. ret %d\n", ret);
2208 goto err_pin_bo_failed;
2209 }
2210
2211 ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2212 if (ret) {
2213 pr_err("Failed to bind bo to GART. ret %d\n", ret);
2214 goto err_map_bo_gart_failed;
2215 }
2216
2217 amdgpu_amdkfd_remove_eviction_fence(
2218 bo, bo->vm_bo->vm->process_info->eviction_fence);
2219
2220 amdgpu_bo_unreserve(bo);
2221
2222 bo = amdgpu_bo_ref(bo);
2223
2224 return 0;
2225
2226err_map_bo_gart_failed:
2227 amdgpu_bo_unpin(bo);
2228err_pin_bo_failed:
2229 amdgpu_bo_unreserve(bo);
2230err_reserve_bo_failed:
2231
2232 return ret;
2233}
2234
2235/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2236 *
2237 * @mem: Buffer object to be mapped for CPU access
2238 * @kptr[out]: pointer in kernel CPU address space
2239 * @size[out]: size of the buffer
2240 *
2241 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2242 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2243 * validate_list, so the GPU mapping can be restored after a page table was
2244 * evicted.
2245 *
2246 * Return: 0 on success, error code on failure
2247 */
2248int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2249 void **kptr, uint64_t *size)
2250{
2251 int ret;
2252 struct amdgpu_bo *bo = mem->bo;
2253
2254 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2255 pr_err("userptr can't be mapped to kernel\n");
2256 return -EINVAL;
2257 }
2258
2259 mutex_lock(&mem->process_info->lock);
2260
2261 ret = amdgpu_bo_reserve(bo, true);
2262 if (ret) {
2263 pr_err("Failed to reserve bo. ret %d\n", ret);
2264 goto bo_reserve_failed;
2265 }
2266
2267 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2268 if (ret) {
2269 pr_err("Failed to pin bo. ret %d\n", ret);
2270 goto pin_failed;
2271 }
2272
2273 ret = amdgpu_bo_kmap(bo, kptr);
2274 if (ret) {
2275 pr_err("Failed to map bo to kernel. ret %d\n", ret);
2276 goto kmap_failed;
2277 }
2278
2279 amdgpu_amdkfd_remove_eviction_fence(
2280 bo, mem->process_info->eviction_fence);
2281
2282 if (size)
2283 *size = amdgpu_bo_size(bo);
2284
2285 amdgpu_bo_unreserve(bo);
2286
2287 mutex_unlock(&mem->process_info->lock);
2288 return 0;
2289
2290kmap_failed:
2291 amdgpu_bo_unpin(bo);
2292pin_failed:
2293 amdgpu_bo_unreserve(bo);
2294bo_reserve_failed:
2295 mutex_unlock(&mem->process_info->lock);
2296
2297 return ret;
2298}
2299
2300/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2301 *
2302 * @mem: Buffer object to be unmapped for CPU access
2303 *
2304 * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2305 * eviction fence, so this function should only be used for cleanup before the
2306 * BO is destroyed.
2307 */
2308void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2309{
2310 struct amdgpu_bo *bo = mem->bo;
2311
2312 amdgpu_bo_reserve(bo, true);
2313 amdgpu_bo_kunmap(bo);
2314 amdgpu_bo_unpin(bo);
2315 amdgpu_bo_unreserve(bo);
2316}
2317
2318int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2319 struct kfd_vm_fault_info *mem)
2320{
2321 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2322 *mem = *adev->gmc.vm_fault_info;
2323 mb(); /* make sure read happened */
2324 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2325 }
2326 return 0;
2327}
2328
2329static int import_obj_create(struct amdgpu_device *adev,
2330 struct dma_buf *dma_buf,
2331 struct drm_gem_object *obj,
2332 uint64_t va, void *drm_priv,
2333 struct kgd_mem **mem, uint64_t *size,
2334 uint64_t *mmap_offset)
2335{
2336 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2337 struct amdgpu_bo *bo;
2338 int ret;
2339
2340 bo = gem_to_amdgpu_bo(obj);
2341 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2342 AMDGPU_GEM_DOMAIN_GTT)))
2343 /* Only VRAM and GTT BOs are supported */
2344 return -EINVAL;
2345
2346 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2347 if (!*mem)
2348 return -ENOMEM;
2349
2350 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2351 if (ret)
2352 goto err_free_mem;
2353
2354 if (size)
2355 *size = amdgpu_bo_size(bo);
2356
2357 if (mmap_offset)
2358 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2359
2360 INIT_LIST_HEAD(&(*mem)->attachments);
2361 mutex_init(&(*mem)->lock);
2362
2363 (*mem)->alloc_flags =
2364 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2365 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2366 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2367 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2368
2369 get_dma_buf(dma_buf);
2370 (*mem)->dmabuf = dma_buf;
2371 (*mem)->bo = bo;
2372 (*mem)->va = va;
2373 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->gmc.is_app_apu ?
2374 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2375
2376 (*mem)->mapped_to_gpu_memory = 0;
2377 (*mem)->process_info = avm->process_info;
2378 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2379 amdgpu_sync_create(&(*mem)->sync);
2380 (*mem)->is_imported = true;
2381
2382 mutex_lock(&avm->process_info->lock);
2383 if (avm->process_info->eviction_fence &&
2384 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
2385 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, (*mem)->domain,
2386 &avm->process_info->eviction_fence->base);
2387 mutex_unlock(&avm->process_info->lock);
2388 if (ret)
2389 goto err_remove_mem;
2390
2391 return 0;
2392
2393err_remove_mem:
2394 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
2395 drm_vma_node_revoke(&obj->vma_node, drm_priv);
2396err_free_mem:
2397 kfree(*mem);
2398 return ret;
2399}
2400
2401int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
2402 uint64_t va, void *drm_priv,
2403 struct kgd_mem **mem, uint64_t *size,
2404 uint64_t *mmap_offset)
2405{
2406 struct drm_gem_object *obj;
2407 uint32_t handle;
2408 int ret;
2409
2410 ret = drm_gem_prime_fd_to_handle(&adev->ddev, adev->kfd.client.file, fd,
2411 &handle);
2412 if (ret)
2413 return ret;
2414 obj = drm_gem_object_lookup(adev->kfd.client.file, handle);
2415 if (!obj) {
2416 ret = -EINVAL;
2417 goto err_release_handle;
2418 }
2419
2420 ret = import_obj_create(adev, obj->dma_buf, obj, va, drm_priv, mem, size,
2421 mmap_offset);
2422 if (ret)
2423 goto err_put_obj;
2424
2425 (*mem)->gem_handle = handle;
2426
2427 return 0;
2428
2429err_put_obj:
2430 drm_gem_object_put(obj);
2431err_release_handle:
2432 drm_gem_handle_delete(adev->kfd.client.file, handle);
2433 return ret;
2434}
2435
2436int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2437 struct dma_buf **dma_buf)
2438{
2439 int ret;
2440
2441 mutex_lock(&mem->lock);
2442 ret = kfd_mem_export_dmabuf(mem);
2443 if (ret)
2444 goto out;
2445
2446 get_dma_buf(mem->dmabuf);
2447 *dma_buf = mem->dmabuf;
2448out:
2449 mutex_unlock(&mem->lock);
2450 return ret;
2451}
2452
2453/* Evict a userptr BO by stopping the queues if necessary
2454 *
2455 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2456 * cannot do any memory allocations, and cannot take any locks that
2457 * are held elsewhere while allocating memory.
2458 *
2459 * It doesn't do anything to the BO itself. The real work happens in
2460 * restore, where we get updated page addresses. This function only
2461 * ensures that GPU access to the BO is stopped.
2462 */
2463int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2464 unsigned long cur_seq, struct kgd_mem *mem)
2465{
2466 struct amdkfd_process_info *process_info = mem->process_info;
2467 int r = 0;
2468
2469 /* Do not process MMU notifications during CRIU restore until
2470 * KFD_CRIU_OP_RESUME IOCTL is received
2471 */
2472 if (READ_ONCE(process_info->block_mmu_notifications))
2473 return 0;
2474
2475 mutex_lock(&process_info->notifier_lock);
2476 mmu_interval_set_seq(mni, cur_seq);
2477
2478 mem->invalid++;
2479 if (++process_info->evicted_bos == 1) {
2480 /* First eviction, stop the queues */
2481 r = kgd2kfd_quiesce_mm(mni->mm,
2482 KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2483 if (r)
2484 pr_err("Failed to quiesce KFD\n");
2485 queue_delayed_work(system_freezable_wq,
2486 &process_info->restore_userptr_work,
2487 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2488 }
2489 mutex_unlock(&process_info->notifier_lock);
2490
2491 return r;
2492}
2493
2494/* Update invalid userptr BOs
2495 *
2496 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2497 * userptr_inval_list and updates user pages for all BOs that have
2498 * been invalidated since their last update.
2499 */
2500static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2501 struct mm_struct *mm)
2502{
2503 struct kgd_mem *mem, *tmp_mem;
2504 struct amdgpu_bo *bo;
2505 struct ttm_operation_ctx ctx = { false, false };
2506 uint32_t invalid;
2507 int ret = 0;
2508
2509 mutex_lock(&process_info->notifier_lock);
2510
2511 /* Move all invalidated BOs to the userptr_inval_list */
2512 list_for_each_entry_safe(mem, tmp_mem,
2513 &process_info->userptr_valid_list,
2514 validate_list)
2515 if (mem->invalid)
2516 list_move_tail(&mem->validate_list,
2517 &process_info->userptr_inval_list);
2518
2519 /* Go through userptr_inval_list and update any invalid user_pages */
2520 list_for_each_entry(mem, &process_info->userptr_inval_list,
2521 validate_list) {
2522 invalid = mem->invalid;
2523 if (!invalid)
2524 /* BO hasn't been invalidated since the last
2525 * revalidation attempt. Keep its page list.
2526 */
2527 continue;
2528
2529 bo = mem->bo;
2530
2531 amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2532 mem->range = NULL;
2533
2534 /* BO reservations and getting user pages (hmm_range_fault)
2535 * must happen outside the notifier lock
2536 */
2537 mutex_unlock(&process_info->notifier_lock);
2538
2539 /* Move the BO to system (CPU) domain if necessary to unmap
2540 * and free the SG table
2541 */
2542 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2543 if (amdgpu_bo_reserve(bo, true))
2544 return -EAGAIN;
2545 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2546 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2547 amdgpu_bo_unreserve(bo);
2548 if (ret) {
2549 pr_err("%s: Failed to invalidate userptr BO\n",
2550 __func__);
2551 return -EAGAIN;
2552 }
2553 }
2554
2555 /* Get updated user pages */
2556 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2557 &mem->range);
2558 if (ret) {
2559 pr_debug("Failed %d to get user pages\n", ret);
2560
2561 /* Return -EFAULT bad address error as success. It will
2562 * fail later with a VM fault if the GPU tries to access
2563 * it. Better than hanging indefinitely with stalled
2564 * user mode queues.
2565 *
2566 * Return other error -EBUSY or -ENOMEM to retry restore
2567 */
2568 if (ret != -EFAULT)
2569 return ret;
2570
2571 ret = 0;
2572 }
2573
2574 mutex_lock(&process_info->notifier_lock);
2575
2576 /* Mark the BO as valid unless it was invalidated
2577 * again concurrently.
2578 */
2579 if (mem->invalid != invalid) {
2580 ret = -EAGAIN;
2581 goto unlock_out;
2582 }
2583 /* set mem valid if mem has hmm range associated */
2584 if (mem->range)
2585 mem->invalid = 0;
2586 }
2587
2588unlock_out:
2589 mutex_unlock(&process_info->notifier_lock);
2590
2591 return ret;
2592}
2593
2594/* Validate invalid userptr BOs
2595 *
2596 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2597 * with new page addresses and waits for the page table updates to complete.
2598 */
2599static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2600{
2601 struct ttm_operation_ctx ctx = { false, false };
2602 struct amdgpu_sync sync;
2603 struct drm_exec exec;
2604
2605 struct amdgpu_vm *peer_vm;
2606 struct kgd_mem *mem, *tmp_mem;
2607 struct amdgpu_bo *bo;
2608 int ret;
2609
2610 amdgpu_sync_create(&sync);
2611
2612 drm_exec_init(&exec, 0, 0);
2613 /* Reserve all BOs and page tables for validation */
2614 drm_exec_until_all_locked(&exec) {
2615 /* Reserve all the page directories */
2616 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2617 vm_list_node) {
2618 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2619 drm_exec_retry_on_contention(&exec);
2620 if (unlikely(ret))
2621 goto unreserve_out;
2622 }
2623
2624 /* Reserve the userptr_inval_list entries to resv_list */
2625 list_for_each_entry(mem, &process_info->userptr_inval_list,
2626 validate_list) {
2627 struct drm_gem_object *gobj;
2628
2629 gobj = &mem->bo->tbo.base;
2630 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2631 drm_exec_retry_on_contention(&exec);
2632 if (unlikely(ret))
2633 goto unreserve_out;
2634 }
2635 }
2636
2637 ret = process_validate_vms(process_info);
2638 if (ret)
2639 goto unreserve_out;
2640
2641 /* Validate BOs and update GPUVM page tables */
2642 list_for_each_entry_safe(mem, tmp_mem,
2643 &process_info->userptr_inval_list,
2644 validate_list) {
2645 struct kfd_mem_attachment *attachment;
2646
2647 bo = mem->bo;
2648
2649 /* Validate the BO if we got user pages */
2650 if (bo->tbo.ttm->pages[0]) {
2651 amdgpu_bo_placement_from_domain(bo, mem->domain);
2652 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2653 if (ret) {
2654 pr_err("%s: failed to validate BO\n", __func__);
2655 goto unreserve_out;
2656 }
2657 }
2658
2659 /* Update mapping. If the BO was not validated
2660 * (because we couldn't get user pages), this will
2661 * clear the page table entries, which will result in
2662 * VM faults if the GPU tries to access the invalid
2663 * memory.
2664 */
2665 list_for_each_entry(attachment, &mem->attachments, list) {
2666 if (!attachment->is_mapped)
2667 continue;
2668
2669 kfd_mem_dmaunmap_attachment(mem, attachment);
2670 ret = update_gpuvm_pte(mem, attachment, &sync);
2671 if (ret) {
2672 pr_err("%s: update PTE failed\n", __func__);
2673 /* make sure this gets validated again */
2674 mutex_lock(&process_info->notifier_lock);
2675 mem->invalid++;
2676 mutex_unlock(&process_info->notifier_lock);
2677 goto unreserve_out;
2678 }
2679 }
2680 }
2681
2682 /* Update page directories */
2683 ret = process_update_pds(process_info, &sync);
2684
2685unreserve_out:
2686 drm_exec_fini(&exec);
2687 amdgpu_sync_wait(&sync, false);
2688 amdgpu_sync_free(&sync);
2689
2690 return ret;
2691}
2692
2693/* Confirm that all user pages are valid while holding the notifier lock
2694 *
2695 * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2696 */
2697static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2698{
2699 struct kgd_mem *mem, *tmp_mem;
2700 int ret = 0;
2701
2702 list_for_each_entry_safe(mem, tmp_mem,
2703 &process_info->userptr_inval_list,
2704 validate_list) {
2705 bool valid;
2706
2707 /* keep mem without hmm range at userptr_inval_list */
2708 if (!mem->range)
2709 continue;
2710
2711 /* Only check mem with hmm range associated */
2712 valid = amdgpu_ttm_tt_get_user_pages_done(
2713 mem->bo->tbo.ttm, mem->range);
2714
2715 mem->range = NULL;
2716 if (!valid) {
2717 WARN(!mem->invalid, "Invalid BO not marked invalid");
2718 ret = -EAGAIN;
2719 continue;
2720 }
2721
2722 if (mem->invalid) {
2723 WARN(1, "Valid BO is marked invalid");
2724 ret = -EAGAIN;
2725 continue;
2726 }
2727
2728 list_move_tail(&mem->validate_list,
2729 &process_info->userptr_valid_list);
2730 }
2731
2732 return ret;
2733}
2734
2735/* Worker callback to restore evicted userptr BOs
2736 *
2737 * Tries to update and validate all userptr BOs. If successful and no
2738 * concurrent evictions happened, the queues are restarted. Otherwise,
2739 * reschedule for another attempt later.
2740 */
2741static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2742{
2743 struct delayed_work *dwork = to_delayed_work(work);
2744 struct amdkfd_process_info *process_info =
2745 container_of(dwork, struct amdkfd_process_info,
2746 restore_userptr_work);
2747 struct task_struct *usertask;
2748 struct mm_struct *mm;
2749 uint32_t evicted_bos;
2750
2751 mutex_lock(&process_info->notifier_lock);
2752 evicted_bos = process_info->evicted_bos;
2753 mutex_unlock(&process_info->notifier_lock);
2754 if (!evicted_bos)
2755 return;
2756
2757 /* Reference task and mm in case of concurrent process termination */
2758 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2759 if (!usertask)
2760 return;
2761 mm = get_task_mm(usertask);
2762 if (!mm) {
2763 put_task_struct(usertask);
2764 return;
2765 }
2766
2767 mutex_lock(&process_info->lock);
2768
2769 if (update_invalid_user_pages(process_info, mm))
2770 goto unlock_out;
2771 /* userptr_inval_list can be empty if all evicted userptr BOs
2772 * have been freed. In that case there is nothing to validate
2773 * and we can just restart the queues.
2774 */
2775 if (!list_empty(&process_info->userptr_inval_list)) {
2776 if (validate_invalid_user_pages(process_info))
2777 goto unlock_out;
2778 }
2779 /* Final check for concurrent evicton and atomic update. If
2780 * another eviction happens after successful update, it will
2781 * be a first eviction that calls quiesce_mm. The eviction
2782 * reference counting inside KFD will handle this case.
2783 */
2784 mutex_lock(&process_info->notifier_lock);
2785 if (process_info->evicted_bos != evicted_bos)
2786 goto unlock_notifier_out;
2787
2788 if (confirm_valid_user_pages_locked(process_info)) {
2789 WARN(1, "User pages unexpectedly invalid");
2790 goto unlock_notifier_out;
2791 }
2792
2793 process_info->evicted_bos = evicted_bos = 0;
2794
2795 if (kgd2kfd_resume_mm(mm)) {
2796 pr_err("%s: Failed to resume KFD\n", __func__);
2797 /* No recovery from this failure. Probably the CP is
2798 * hanging. No point trying again.
2799 */
2800 }
2801
2802unlock_notifier_out:
2803 mutex_unlock(&process_info->notifier_lock);
2804unlock_out:
2805 mutex_unlock(&process_info->lock);
2806
2807 /* If validation failed, reschedule another attempt */
2808 if (evicted_bos) {
2809 queue_delayed_work(system_freezable_wq,
2810 &process_info->restore_userptr_work,
2811 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2812
2813 kfd_smi_event_queue_restore_rescheduled(mm);
2814 }
2815 mmput(mm);
2816 put_task_struct(usertask);
2817}
2818
2819static void replace_eviction_fence(struct dma_fence __rcu **ef,
2820 struct dma_fence *new_ef)
2821{
2822 struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true
2823 /* protected by process_info->lock */);
2824
2825 /* If we're replacing an unsignaled eviction fence, that fence will
2826 * never be signaled, and if anyone is still waiting on that fence,
2827 * they will hang forever. This should never happen. We should only
2828 * replace the fence in restore_work that only gets scheduled after
2829 * eviction work signaled the fence.
2830 */
2831 WARN_ONCE(!dma_fence_is_signaled(old_ef),
2832 "Replacing unsignaled eviction fence");
2833 dma_fence_put(old_ef);
2834}
2835
2836/** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2837 * KFD process identified by process_info
2838 *
2839 * @process_info: amdkfd_process_info of the KFD process
2840 *
2841 * After memory eviction, restore thread calls this function. The function
2842 * should be called when the Process is still valid. BO restore involves -
2843 *
2844 * 1. Release old eviction fence and create new one
2845 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2846 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2847 * BOs that need to be reserved.
2848 * 4. Reserve all the BOs
2849 * 5. Validate of PD and PT BOs.
2850 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2851 * 7. Add fence to all PD and PT BOs.
2852 * 8. Unreserve all BOs
2853 */
2854int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu **ef)
2855{
2856 struct amdkfd_process_info *process_info = info;
2857 struct amdgpu_vm *peer_vm;
2858 struct kgd_mem *mem;
2859 struct list_head duplicate_save;
2860 struct amdgpu_sync sync_obj;
2861 unsigned long failed_size = 0;
2862 unsigned long total_size = 0;
2863 struct drm_exec exec;
2864 int ret;
2865
2866 INIT_LIST_HEAD(&duplicate_save);
2867
2868 mutex_lock(&process_info->lock);
2869
2870 drm_exec_init(&exec, 0, 0);
2871 drm_exec_until_all_locked(&exec) {
2872 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2873 vm_list_node) {
2874 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2875 drm_exec_retry_on_contention(&exec);
2876 if (unlikely(ret))
2877 goto ttm_reserve_fail;
2878 }
2879
2880 /* Reserve all BOs and page tables/directory. Add all BOs from
2881 * kfd_bo_list to ctx.list
2882 */
2883 list_for_each_entry(mem, &process_info->kfd_bo_list,
2884 validate_list) {
2885 struct drm_gem_object *gobj;
2886
2887 gobj = &mem->bo->tbo.base;
2888 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2889 drm_exec_retry_on_contention(&exec);
2890 if (unlikely(ret))
2891 goto ttm_reserve_fail;
2892 }
2893 }
2894
2895 amdgpu_sync_create(&sync_obj);
2896
2897 /* Validate PDs and PTs */
2898 ret = process_validate_vms(process_info);
2899 if (ret)
2900 goto validate_map_fail;
2901
2902 /* Validate BOs and map them to GPUVM (update VM page tables). */
2903 list_for_each_entry(mem, &process_info->kfd_bo_list,
2904 validate_list) {
2905
2906 struct amdgpu_bo *bo = mem->bo;
2907 uint32_t domain = mem->domain;
2908 struct kfd_mem_attachment *attachment;
2909 struct dma_resv_iter cursor;
2910 struct dma_fence *fence;
2911
2912 total_size += amdgpu_bo_size(bo);
2913
2914 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2915 if (ret) {
2916 pr_debug("Memory eviction: Validate BOs failed\n");
2917 failed_size += amdgpu_bo_size(bo);
2918 ret = amdgpu_amdkfd_bo_validate(bo,
2919 AMDGPU_GEM_DOMAIN_GTT, false);
2920 if (ret) {
2921 pr_debug("Memory eviction: Try again\n");
2922 goto validate_map_fail;
2923 }
2924 }
2925 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2926 DMA_RESV_USAGE_KERNEL, fence) {
2927 ret = amdgpu_sync_fence(&sync_obj, fence);
2928 if (ret) {
2929 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2930 goto validate_map_fail;
2931 }
2932 }
2933 list_for_each_entry(attachment, &mem->attachments, list) {
2934 if (!attachment->is_mapped)
2935 continue;
2936
2937 if (attachment->bo_va->base.bo->tbo.pin_count)
2938 continue;
2939
2940 kfd_mem_dmaunmap_attachment(mem, attachment);
2941 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2942 if (ret) {
2943 pr_debug("Memory eviction: update PTE failed. Try again\n");
2944 goto validate_map_fail;
2945 }
2946 }
2947 }
2948
2949 if (failed_size)
2950 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2951
2952 /* Update mappings not managed by KFD */
2953 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2954 vm_list_node) {
2955 struct amdgpu_device *adev = amdgpu_ttm_adev(
2956 peer_vm->root.bo->tbo.bdev);
2957
2958 ret = amdgpu_vm_handle_moved(adev, peer_vm, &exec.ticket);
2959 if (ret) {
2960 pr_debug("Memory eviction: handle moved failed. Try again\n");
2961 goto validate_map_fail;
2962 }
2963 }
2964
2965 /* Update page directories */
2966 ret = process_update_pds(process_info, &sync_obj);
2967 if (ret) {
2968 pr_debug("Memory eviction: update PDs failed. Try again\n");
2969 goto validate_map_fail;
2970 }
2971
2972 /* Sync with fences on all the page tables. They implicitly depend on any
2973 * move fences from amdgpu_vm_handle_moved above.
2974 */
2975 ret = process_sync_pds_resv(process_info, &sync_obj);
2976 if (ret) {
2977 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2978 goto validate_map_fail;
2979 }
2980
2981 /* Wait for validate and PT updates to finish */
2982 amdgpu_sync_wait(&sync_obj, false);
2983
2984 /* The old eviction fence may be unsignaled if restore happens
2985 * after a GPU reset or suspend/resume. Keep the old fence in that
2986 * case. Otherwise release the old eviction fence and create new
2987 * one, because fence only goes from unsignaled to signaled once
2988 * and cannot be reused. Use context and mm from the old fence.
2989 *
2990 * If an old eviction fence signals after this check, that's OK.
2991 * Anyone signaling an eviction fence must stop the queues first
2992 * and schedule another restore worker.
2993 */
2994 if (dma_fence_is_signaled(&process_info->eviction_fence->base)) {
2995 struct amdgpu_amdkfd_fence *new_fence =
2996 amdgpu_amdkfd_fence_create(
2997 process_info->eviction_fence->base.context,
2998 process_info->eviction_fence->mm,
2999 NULL);
3000
3001 if (!new_fence) {
3002 pr_err("Failed to create eviction fence\n");
3003 ret = -ENOMEM;
3004 goto validate_map_fail;
3005 }
3006 dma_fence_put(&process_info->eviction_fence->base);
3007 process_info->eviction_fence = new_fence;
3008 replace_eviction_fence(ef, dma_fence_get(&new_fence->base));
3009 } else {
3010 WARN_ONCE(*ef != &process_info->eviction_fence->base,
3011 "KFD eviction fence doesn't match KGD process_info");
3012 }
3013
3014 /* Attach new eviction fence to all BOs except pinned ones */
3015 list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
3016 if (mem->bo->tbo.pin_count)
3017 continue;
3018
3019 dma_resv_add_fence(mem->bo->tbo.base.resv,
3020 &process_info->eviction_fence->base,
3021 DMA_RESV_USAGE_BOOKKEEP);
3022 }
3023 /* Attach eviction fence to PD / PT BOs */
3024 list_for_each_entry(peer_vm, &process_info->vm_list_head,
3025 vm_list_node) {
3026 struct amdgpu_bo *bo = peer_vm->root.bo;
3027
3028 dma_resv_add_fence(bo->tbo.base.resv,
3029 &process_info->eviction_fence->base,
3030 DMA_RESV_USAGE_BOOKKEEP);
3031 }
3032
3033validate_map_fail:
3034 amdgpu_sync_free(&sync_obj);
3035ttm_reserve_fail:
3036 drm_exec_fini(&exec);
3037 mutex_unlock(&process_info->lock);
3038 return ret;
3039}
3040
3041int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
3042{
3043 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3044 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
3045 int ret;
3046
3047 if (!info || !gws)
3048 return -EINVAL;
3049
3050 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
3051 if (!*mem)
3052 return -ENOMEM;
3053
3054 mutex_init(&(*mem)->lock);
3055 INIT_LIST_HEAD(&(*mem)->attachments);
3056 (*mem)->bo = amdgpu_bo_ref(gws_bo);
3057 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
3058 (*mem)->process_info = process_info;
3059 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
3060 amdgpu_sync_create(&(*mem)->sync);
3061
3062
3063 /* Validate gws bo the first time it is added to process */
3064 mutex_lock(&(*mem)->process_info->lock);
3065 ret = amdgpu_bo_reserve(gws_bo, false);
3066 if (unlikely(ret)) {
3067 pr_err("Reserve gws bo failed %d\n", ret);
3068 goto bo_reservation_failure;
3069 }
3070
3071 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
3072 if (ret) {
3073 pr_err("GWS BO validate failed %d\n", ret);
3074 goto bo_validation_failure;
3075 }
3076 /* GWS resource is shared b/t amdgpu and amdkfd
3077 * Add process eviction fence to bo so they can
3078 * evict each other.
3079 */
3080 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
3081 if (ret)
3082 goto reserve_shared_fail;
3083 dma_resv_add_fence(gws_bo->tbo.base.resv,
3084 &process_info->eviction_fence->base,
3085 DMA_RESV_USAGE_BOOKKEEP);
3086 amdgpu_bo_unreserve(gws_bo);
3087 mutex_unlock(&(*mem)->process_info->lock);
3088
3089 return ret;
3090
3091reserve_shared_fail:
3092bo_validation_failure:
3093 amdgpu_bo_unreserve(gws_bo);
3094bo_reservation_failure:
3095 mutex_unlock(&(*mem)->process_info->lock);
3096 amdgpu_sync_free(&(*mem)->sync);
3097 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
3098 amdgpu_bo_unref(&gws_bo);
3099 mutex_destroy(&(*mem)->lock);
3100 kfree(*mem);
3101 *mem = NULL;
3102 return ret;
3103}
3104
3105int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
3106{
3107 int ret;
3108 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3109 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
3110 struct amdgpu_bo *gws_bo = kgd_mem->bo;
3111
3112 /* Remove BO from process's validate list so restore worker won't touch
3113 * it anymore
3114 */
3115 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
3116
3117 ret = amdgpu_bo_reserve(gws_bo, false);
3118 if (unlikely(ret)) {
3119 pr_err("Reserve gws bo failed %d\n", ret);
3120 //TODO add BO back to validate_list?
3121 return ret;
3122 }
3123 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
3124 process_info->eviction_fence);
3125 amdgpu_bo_unreserve(gws_bo);
3126 amdgpu_sync_free(&kgd_mem->sync);
3127 amdgpu_bo_unref(&gws_bo);
3128 mutex_destroy(&kgd_mem->lock);
3129 kfree(mem);
3130 return 0;
3131}
3132
3133/* Returns GPU-specific tiling mode information */
3134int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
3135 struct tile_config *config)
3136{
3137 config->gb_addr_config = adev->gfx.config.gb_addr_config;
3138 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
3139 config->num_tile_configs =
3140 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
3141 config->macro_tile_config_ptr =
3142 adev->gfx.config.macrotile_mode_array;
3143 config->num_macro_tile_configs =
3144 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
3145
3146 /* Those values are not set from GFX9 onwards */
3147 config->num_banks = adev->gfx.config.num_banks;
3148 config->num_ranks = adev->gfx.config.num_ranks;
3149
3150 return 0;
3151}
3152
3153bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
3154{
3155 struct kfd_mem_attachment *entry;
3156
3157 list_for_each_entry(entry, &mem->attachments, list) {
3158 if (entry->is_mapped && entry->adev == adev)
3159 return true;
3160 }
3161 return false;
3162}
3163
3164#if defined(CONFIG_DEBUG_FS)
3165
3166int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3167{
3168
3169 spin_lock(&kfd_mem_limit.mem_limit_lock);
3170 seq_printf(m, "System mem used %lldM out of %lluM\n",
3171 (kfd_mem_limit.system_mem_used >> 20),
3172 (kfd_mem_limit.max_system_mem_limit >> 20));
3173 seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3174 (kfd_mem_limit.ttm_mem_used >> 20),
3175 (kfd_mem_limit.max_ttm_mem_limit >> 20));
3176 spin_unlock(&kfd_mem_limit.mem_limit_lock);
3177
3178 return 0;
3179}
3180
3181#endif