Loading...
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include <linux/dma-buf.h>
24#include <linux/list.h>
25#include <linux/pagemap.h>
26#include <linux/sched/mm.h>
27#include <linux/sched/task.h>
28#include <linux/fdtable.h>
29#include <drm/ttm/ttm_tt.h>
30
31#include <drm/drm_exec.h>
32
33#include "amdgpu_object.h"
34#include "amdgpu_gem.h"
35#include "amdgpu_vm.h"
36#include "amdgpu_hmm.h"
37#include "amdgpu_amdkfd.h"
38#include "amdgpu_dma_buf.h"
39#include <uapi/linux/kfd_ioctl.h>
40#include "amdgpu_xgmi.h"
41#include "kfd_priv.h"
42#include "kfd_smi_events.h"
43
44/* Userptr restore delay, just long enough to allow consecutive VM
45 * changes to accumulate
46 */
47#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
48#define AMDGPU_RESERVE_MEM_LIMIT (3UL << 29)
49
50/*
51 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
52 * BO chunk
53 */
54#define VRAM_AVAILABLITY_ALIGN (1 << 21)
55
56/* Impose limit on how much memory KFD can use */
57static struct {
58 uint64_t max_system_mem_limit;
59 uint64_t max_ttm_mem_limit;
60 int64_t system_mem_used;
61 int64_t ttm_mem_used;
62 spinlock_t mem_limit_lock;
63} kfd_mem_limit;
64
65static const char * const domain_bit_to_string[] = {
66 "CPU",
67 "GTT",
68 "VRAM",
69 "GDS",
70 "GWS",
71 "OA"
72};
73
74#define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
75
76static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
77
78static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
79 struct kgd_mem *mem)
80{
81 struct kfd_mem_attachment *entry;
82
83 list_for_each_entry(entry, &mem->attachments, list)
84 if (entry->bo_va->base.vm == avm)
85 return true;
86
87 return false;
88}
89
90/**
91 * reuse_dmamap() - Check whether adev can share the original
92 * userptr BO
93 *
94 * If both adev and bo_adev are in direct mapping or
95 * in the same iommu group, they can share the original BO.
96 *
97 * @adev: Device to which can or cannot share the original BO
98 * @bo_adev: Device to which allocated BO belongs to
99 *
100 * Return: returns true if adev can share original userptr BO,
101 * false otherwise.
102 */
103static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
104{
105 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
106 (adev->dev->iommu_group == bo_adev->dev->iommu_group);
107}
108
109/* Set memory usage limits. Current, limits are
110 * System (TTM + userptr) memory - 15/16th System RAM
111 * TTM memory - 3/8th System RAM
112 */
113void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
114{
115 struct sysinfo si;
116 uint64_t mem;
117
118 if (kfd_mem_limit.max_system_mem_limit)
119 return;
120
121 si_meminfo(&si);
122 mem = si.totalram - si.totalhigh;
123 mem *= si.mem_unit;
124
125 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
126 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6);
127 if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT)
128 kfd_mem_limit.max_system_mem_limit >>= 1;
129 else
130 kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT;
131
132 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
133 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
134 (kfd_mem_limit.max_system_mem_limit >> 20),
135 (kfd_mem_limit.max_ttm_mem_limit >> 20));
136}
137
138void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
139{
140 kfd_mem_limit.system_mem_used += size;
141}
142
143/* Estimate page table size needed to represent a given memory size
144 *
145 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
146 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
147 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
148 * for 2MB pages for TLB efficiency. However, small allocations and
149 * fragmented system memory still need some 4KB pages. We choose a
150 * compromise that should work in most cases without reserving too
151 * much memory for page tables unnecessarily (factor 16K, >> 14).
152 */
153
154#define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
155
156/**
157 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
158 * of buffer.
159 *
160 * @adev: Device to which allocated BO belongs to
161 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
162 * equivalent to amdgpu_bo_size(BO)
163 * @alloc_flag: Flag used in allocating a BO as noted above
164 * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
165 * managed as one compute node in driver for app
166 *
167 * Return:
168 * returns -ENOMEM in case of error, ZERO otherwise
169 */
170int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
171 uint64_t size, u32 alloc_flag, int8_t xcp_id)
172{
173 uint64_t reserved_for_pt =
174 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
175 size_t system_mem_needed, ttm_mem_needed, vram_needed;
176 int ret = 0;
177 uint64_t vram_size = 0;
178
179 system_mem_needed = 0;
180 ttm_mem_needed = 0;
181 vram_needed = 0;
182 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
183 system_mem_needed = size;
184 ttm_mem_needed = size;
185 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
186 /*
187 * Conservatively round up the allocation requirement to 2 MB
188 * to avoid fragmentation caused by 4K allocations in the tail
189 * 2M BO chunk.
190 */
191 vram_needed = size;
192 /*
193 * For GFX 9.4.3, get the VRAM size from XCP structs
194 */
195 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
196 return -EINVAL;
197
198 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
199 if (adev->gmc.is_app_apu) {
200 system_mem_needed = size;
201 ttm_mem_needed = size;
202 }
203 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
204 system_mem_needed = size;
205 } else if (!(alloc_flag &
206 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
207 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
208 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
209 return -ENOMEM;
210 }
211
212 spin_lock(&kfd_mem_limit.mem_limit_lock);
213
214 if (kfd_mem_limit.system_mem_used + system_mem_needed >
215 kfd_mem_limit.max_system_mem_limit)
216 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
217
218 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
219 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
220 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
221 kfd_mem_limit.max_ttm_mem_limit) ||
222 (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
223 vram_size - reserved_for_pt - atomic64_read(&adev->vram_pin_size))) {
224 ret = -ENOMEM;
225 goto release;
226 }
227
228 /* Update memory accounting by decreasing available system
229 * memory, TTM memory and GPU memory as computed above
230 */
231 WARN_ONCE(vram_needed && !adev,
232 "adev reference can't be null when vram is used");
233 if (adev && xcp_id >= 0) {
234 adev->kfd.vram_used[xcp_id] += vram_needed;
235 adev->kfd.vram_used_aligned[xcp_id] += adev->gmc.is_app_apu ?
236 vram_needed :
237 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
238 }
239 kfd_mem_limit.system_mem_used += system_mem_needed;
240 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
241
242release:
243 spin_unlock(&kfd_mem_limit.mem_limit_lock);
244 return ret;
245}
246
247void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
248 uint64_t size, u32 alloc_flag, int8_t xcp_id)
249{
250 spin_lock(&kfd_mem_limit.mem_limit_lock);
251
252 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
253 kfd_mem_limit.system_mem_used -= size;
254 kfd_mem_limit.ttm_mem_used -= size;
255 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
256 WARN_ONCE(!adev,
257 "adev reference can't be null when alloc mem flags vram is set");
258 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
259 goto release;
260
261 if (adev) {
262 adev->kfd.vram_used[xcp_id] -= size;
263 if (adev->gmc.is_app_apu) {
264 adev->kfd.vram_used_aligned[xcp_id] -= size;
265 kfd_mem_limit.system_mem_used -= size;
266 kfd_mem_limit.ttm_mem_used -= size;
267 } else {
268 adev->kfd.vram_used_aligned[xcp_id] -=
269 ALIGN(size, VRAM_AVAILABLITY_ALIGN);
270 }
271 }
272 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
273 kfd_mem_limit.system_mem_used -= size;
274 } else if (!(alloc_flag &
275 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
276 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
277 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
278 goto release;
279 }
280 WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
281 "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
282 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
283 "KFD TTM memory accounting unbalanced");
284 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
285 "KFD system memory accounting unbalanced");
286
287release:
288 spin_unlock(&kfd_mem_limit.mem_limit_lock);
289}
290
291void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
292{
293 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
294 u32 alloc_flags = bo->kfd_bo->alloc_flags;
295 u64 size = amdgpu_bo_size(bo);
296
297 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
298 bo->xcp_id);
299
300 kfree(bo->kfd_bo);
301}
302
303/**
304 * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
305 * about USERPTR or DOOREBELL or MMIO BO.
306 *
307 * @adev: Device for which dmamap BO is being created
308 * @mem: BO of peer device that is being DMA mapped. Provides parameters
309 * in building the dmamap BO
310 * @bo_out: Output parameter updated with handle of dmamap BO
311 */
312static int
313create_dmamap_sg_bo(struct amdgpu_device *adev,
314 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
315{
316 struct drm_gem_object *gem_obj;
317 int ret;
318 uint64_t flags = 0;
319
320 ret = amdgpu_bo_reserve(mem->bo, false);
321 if (ret)
322 return ret;
323
324 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
325 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
326 AMDGPU_GEM_CREATE_UNCACHED);
327
328 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
329 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
330 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
331
332 amdgpu_bo_unreserve(mem->bo);
333
334 if (ret) {
335 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
336 return -EINVAL;
337 }
338
339 *bo_out = gem_to_amdgpu_bo(gem_obj);
340 (*bo_out)->parent = amdgpu_bo_ref(mem->bo);
341 return ret;
342}
343
344/* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
345 * reservation object.
346 *
347 * @bo: [IN] Remove eviction fence(s) from this BO
348 * @ef: [IN] This eviction fence is removed if it
349 * is present in the shared list.
350 *
351 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
352 */
353static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
354 struct amdgpu_amdkfd_fence *ef)
355{
356 struct dma_fence *replacement;
357
358 if (!ef)
359 return -EINVAL;
360
361 /* TODO: Instead of block before we should use the fence of the page
362 * table update and TLB flush here directly.
363 */
364 replacement = dma_fence_get_stub();
365 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
366 replacement, DMA_RESV_USAGE_BOOKKEEP);
367 dma_fence_put(replacement);
368 return 0;
369}
370
371int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
372{
373 struct amdgpu_bo *root = bo;
374 struct amdgpu_vm_bo_base *vm_bo;
375 struct amdgpu_vm *vm;
376 struct amdkfd_process_info *info;
377 struct amdgpu_amdkfd_fence *ef;
378 int ret;
379
380 /* we can always get vm_bo from root PD bo.*/
381 while (root->parent)
382 root = root->parent;
383
384 vm_bo = root->vm_bo;
385 if (!vm_bo)
386 return 0;
387
388 vm = vm_bo->vm;
389 if (!vm)
390 return 0;
391
392 info = vm->process_info;
393 if (!info || !info->eviction_fence)
394 return 0;
395
396 ef = container_of(dma_fence_get(&info->eviction_fence->base),
397 struct amdgpu_amdkfd_fence, base);
398
399 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
400 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
401 dma_resv_unlock(bo->tbo.base.resv);
402
403 dma_fence_put(&ef->base);
404 return ret;
405}
406
407static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
408 bool wait)
409{
410 struct ttm_operation_ctx ctx = { false, false };
411 int ret;
412
413 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
414 "Called with userptr BO"))
415 return -EINVAL;
416
417 amdgpu_bo_placement_from_domain(bo, domain);
418
419 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
420 if (ret)
421 goto validate_fail;
422 if (wait)
423 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
424
425validate_fail:
426 return ret;
427}
428
429int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
430 uint32_t domain,
431 struct dma_fence *fence)
432{
433 int ret = amdgpu_bo_reserve(bo, false);
434
435 if (ret)
436 return ret;
437
438 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
439 if (ret)
440 goto unreserve_out;
441
442 ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
443 if (ret)
444 goto unreserve_out;
445
446 dma_resv_add_fence(bo->tbo.base.resv, fence,
447 DMA_RESV_USAGE_BOOKKEEP);
448
449unreserve_out:
450 amdgpu_bo_unreserve(bo);
451
452 return ret;
453}
454
455static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
456{
457 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
458}
459
460/* vm_validate_pt_pd_bos - Validate page table and directory BOs
461 *
462 * Page directories are not updated here because huge page handling
463 * during page table updates can invalidate page directory entries
464 * again. Page directories are only updated after updating page
465 * tables.
466 */
467static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm,
468 struct ww_acquire_ctx *ticket)
469{
470 struct amdgpu_bo *pd = vm->root.bo;
471 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
472 int ret;
473
474 ret = amdgpu_vm_validate(adev, vm, ticket,
475 amdgpu_amdkfd_validate_vm_bo, NULL);
476 if (ret) {
477 pr_err("failed to validate PT BOs\n");
478 return ret;
479 }
480
481 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
482
483 return 0;
484}
485
486static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
487{
488 struct amdgpu_bo *pd = vm->root.bo;
489 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
490 int ret;
491
492 ret = amdgpu_vm_update_pdes(adev, vm, false);
493 if (ret)
494 return ret;
495
496 return amdgpu_sync_fence(sync, vm->last_update);
497}
498
499static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
500{
501 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
502 AMDGPU_VM_MTYPE_DEFAULT;
503
504 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
505 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
506 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
507 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
508
509 return amdgpu_gem_va_map_flags(adev, mapping_flags);
510}
511
512/**
513 * create_sg_table() - Create an sg_table for a contiguous DMA addr range
514 * @addr: The starting address to point to
515 * @size: Size of memory area in bytes being pointed to
516 *
517 * Allocates an instance of sg_table and initializes it to point to memory
518 * area specified by input parameters. The address used to build is assumed
519 * to be DMA mapped, if needed.
520 *
521 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
522 * because they are physically contiguous.
523 *
524 * Return: Initialized instance of SG Table or NULL
525 */
526static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
527{
528 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
529
530 if (!sg)
531 return NULL;
532 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
533 kfree(sg);
534 return NULL;
535 }
536 sg_dma_address(sg->sgl) = addr;
537 sg->sgl->length = size;
538#ifdef CONFIG_NEED_SG_DMA_LENGTH
539 sg->sgl->dma_length = size;
540#endif
541 return sg;
542}
543
544static int
545kfd_mem_dmamap_userptr(struct kgd_mem *mem,
546 struct kfd_mem_attachment *attachment)
547{
548 enum dma_data_direction direction =
549 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
550 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
551 struct ttm_operation_ctx ctx = {.interruptible = true};
552 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
553 struct amdgpu_device *adev = attachment->adev;
554 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
555 struct ttm_tt *ttm = bo->tbo.ttm;
556 int ret;
557
558 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
559 return -EINVAL;
560
561 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
562 if (unlikely(!ttm->sg))
563 return -ENOMEM;
564
565 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
566 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
567 ttm->num_pages, 0,
568 (u64)ttm->num_pages << PAGE_SHIFT,
569 GFP_KERNEL);
570 if (unlikely(ret))
571 goto free_sg;
572
573 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
574 if (unlikely(ret))
575 goto release_sg;
576
577 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
578 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
579 if (ret)
580 goto unmap_sg;
581
582 return 0;
583
584unmap_sg:
585 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
586release_sg:
587 pr_err("DMA map userptr failed: %d\n", ret);
588 sg_free_table(ttm->sg);
589free_sg:
590 kfree(ttm->sg);
591 ttm->sg = NULL;
592 return ret;
593}
594
595static int
596kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
597{
598 struct ttm_operation_ctx ctx = {.interruptible = true};
599 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
600 int ret;
601
602 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
603 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
604 if (ret)
605 return ret;
606
607 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
608 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
609}
610
611/**
612 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
613 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
614 * @attachment: Virtual address attachment of the BO on accessing device
615 *
616 * An access request from the device that owns DOORBELL does not require DMA mapping.
617 * This is because the request doesn't go through PCIe root complex i.e. it instead
618 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
619 *
620 * In contrast, all access requests for MMIO need to be DMA mapped without regard to
621 * device ownership. This is because access requests for MMIO go through PCIe root
622 * complex.
623 *
624 * This is accomplished in two steps:
625 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
626 * in updating requesting device's page table
627 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU
628 * accessible. This allows an update of requesting device's page table
629 * with entries associated with DOOREBELL or MMIO memory
630 *
631 * This method is invoked in the following contexts:
632 * - Mapping of DOORBELL or MMIO BO of same or peer device
633 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access
634 *
635 * Return: ZERO if successful, NON-ZERO otherwise
636 */
637static int
638kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
639 struct kfd_mem_attachment *attachment)
640{
641 struct ttm_operation_ctx ctx = {.interruptible = true};
642 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
643 struct amdgpu_device *adev = attachment->adev;
644 struct ttm_tt *ttm = bo->tbo.ttm;
645 enum dma_data_direction dir;
646 dma_addr_t dma_addr;
647 bool mmio;
648 int ret;
649
650 /* Expect SG Table of dmapmap BO to be NULL */
651 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
652 if (unlikely(ttm->sg)) {
653 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
654 return -EINVAL;
655 }
656
657 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
658 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
659 dma_addr = mem->bo->tbo.sg->sgl->dma_address;
660 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
661 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
662 dma_addr = dma_map_resource(adev->dev, dma_addr,
663 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
664 ret = dma_mapping_error(adev->dev, dma_addr);
665 if (unlikely(ret))
666 return ret;
667 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
668
669 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
670 if (unlikely(!ttm->sg)) {
671 ret = -ENOMEM;
672 goto unmap_sg;
673 }
674
675 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
676 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
677 if (unlikely(ret))
678 goto free_sg;
679
680 return ret;
681
682free_sg:
683 sg_free_table(ttm->sg);
684 kfree(ttm->sg);
685 ttm->sg = NULL;
686unmap_sg:
687 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
688 dir, DMA_ATTR_SKIP_CPU_SYNC);
689 return ret;
690}
691
692static int
693kfd_mem_dmamap_attachment(struct kgd_mem *mem,
694 struct kfd_mem_attachment *attachment)
695{
696 switch (attachment->type) {
697 case KFD_MEM_ATT_SHARED:
698 return 0;
699 case KFD_MEM_ATT_USERPTR:
700 return kfd_mem_dmamap_userptr(mem, attachment);
701 case KFD_MEM_ATT_DMABUF:
702 return kfd_mem_dmamap_dmabuf(attachment);
703 case KFD_MEM_ATT_SG:
704 return kfd_mem_dmamap_sg_bo(mem, attachment);
705 default:
706 WARN_ON_ONCE(1);
707 }
708 return -EINVAL;
709}
710
711static void
712kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
713 struct kfd_mem_attachment *attachment)
714{
715 enum dma_data_direction direction =
716 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
717 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
718 struct ttm_operation_ctx ctx = {.interruptible = false};
719 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
720 struct amdgpu_device *adev = attachment->adev;
721 struct ttm_tt *ttm = bo->tbo.ttm;
722
723 if (unlikely(!ttm->sg))
724 return;
725
726 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
727 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
728
729 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
730 sg_free_table(ttm->sg);
731 kfree(ttm->sg);
732 ttm->sg = NULL;
733}
734
735static void
736kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
737{
738 /* This is a no-op. We don't want to trigger eviction fences when
739 * unmapping DMABufs. Therefore the invalidation (moving to system
740 * domain) is done in kfd_mem_dmamap_dmabuf.
741 */
742}
743
744/**
745 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
746 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
747 * @attachment: Virtual address attachment of the BO on accessing device
748 *
749 * The method performs following steps:
750 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible
751 * - Free SG Table that is used to encapsulate DMA mapped memory of
752 * peer device's DOORBELL or MMIO memory
753 *
754 * This method is invoked in the following contexts:
755 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory
756 * Eviction of DOOREBELL or MMIO BO on device having access to its memory
757 *
758 * Return: void
759 */
760static void
761kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
762 struct kfd_mem_attachment *attachment)
763{
764 struct ttm_operation_ctx ctx = {.interruptible = true};
765 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
766 struct amdgpu_device *adev = attachment->adev;
767 struct ttm_tt *ttm = bo->tbo.ttm;
768 enum dma_data_direction dir;
769
770 if (unlikely(!ttm->sg)) {
771 pr_debug("SG Table of BO is NULL");
772 return;
773 }
774
775 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
776 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
777
778 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
779 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
780 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
781 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
782 sg_free_table(ttm->sg);
783 kfree(ttm->sg);
784 ttm->sg = NULL;
785 bo->tbo.sg = NULL;
786}
787
788static void
789kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
790 struct kfd_mem_attachment *attachment)
791{
792 switch (attachment->type) {
793 case KFD_MEM_ATT_SHARED:
794 break;
795 case KFD_MEM_ATT_USERPTR:
796 kfd_mem_dmaunmap_userptr(mem, attachment);
797 break;
798 case KFD_MEM_ATT_DMABUF:
799 kfd_mem_dmaunmap_dmabuf(attachment);
800 break;
801 case KFD_MEM_ATT_SG:
802 kfd_mem_dmaunmap_sg_bo(mem, attachment);
803 break;
804 default:
805 WARN_ON_ONCE(1);
806 }
807}
808
809static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
810{
811 if (!mem->dmabuf) {
812 struct amdgpu_device *bo_adev;
813 struct dma_buf *dmabuf;
814 int r, fd;
815
816 bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
817 r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file,
818 mem->gem_handle,
819 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
820 DRM_RDWR : 0, &fd);
821 if (r)
822 return r;
823 dmabuf = dma_buf_get(fd);
824 close_fd(fd);
825 if (WARN_ON_ONCE(IS_ERR(dmabuf)))
826 return PTR_ERR(dmabuf);
827 mem->dmabuf = dmabuf;
828 }
829
830 return 0;
831}
832
833static int
834kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
835 struct amdgpu_bo **bo)
836{
837 struct drm_gem_object *gobj;
838 int ret;
839
840 ret = kfd_mem_export_dmabuf(mem);
841 if (ret)
842 return ret;
843
844 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
845 if (IS_ERR(gobj))
846 return PTR_ERR(gobj);
847
848 *bo = gem_to_amdgpu_bo(gobj);
849 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
850
851 return 0;
852}
853
854/* kfd_mem_attach - Add a BO to a VM
855 *
856 * Everything that needs to bo done only once when a BO is first added
857 * to a VM. It can later be mapped and unmapped many times without
858 * repeating these steps.
859 *
860 * 0. Create BO for DMA mapping, if needed
861 * 1. Allocate and initialize BO VA entry data structure
862 * 2. Add BO to the VM
863 * 3. Determine ASIC-specific PTE flags
864 * 4. Alloc page tables and directories if needed
865 * 4a. Validate new page tables and directories
866 */
867static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
868 struct amdgpu_vm *vm, bool is_aql)
869{
870 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
871 unsigned long bo_size = mem->bo->tbo.base.size;
872 uint64_t va = mem->va;
873 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
874 struct amdgpu_bo *bo[2] = {NULL, NULL};
875 struct amdgpu_bo_va *bo_va;
876 bool same_hive = false;
877 int i, ret;
878
879 if (!va) {
880 pr_err("Invalid VA when adding BO to VM\n");
881 return -EINVAL;
882 }
883
884 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
885 *
886 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
887 * In contrast the access path of VRAM BOs depens upon the type of
888 * link that connects the peer device. Access over PCIe is allowed
889 * if peer device has large BAR. In contrast, access over xGMI is
890 * allowed for both small and large BAR configurations of peer device
891 */
892 if ((adev != bo_adev && !adev->gmc.is_app_apu) &&
893 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
894 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
895 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
896 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
897 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
898 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
899 return -EINVAL;
900 }
901
902 for (i = 0; i <= is_aql; i++) {
903 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
904 if (unlikely(!attachment[i])) {
905 ret = -ENOMEM;
906 goto unwind;
907 }
908
909 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
910 va + bo_size, vm);
911
912 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
913 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
914 (mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) ||
915 same_hive) {
916 /* Mappings on the local GPU, or VRAM mappings in the
917 * local hive, or userptr, or GTT mapping can reuse dma map
918 * address space share the original BO
919 */
920 attachment[i]->type = KFD_MEM_ATT_SHARED;
921 bo[i] = mem->bo;
922 drm_gem_object_get(&bo[i]->tbo.base);
923 } else if (i > 0) {
924 /* Multiple mappings on the same GPU share the BO */
925 attachment[i]->type = KFD_MEM_ATT_SHARED;
926 bo[i] = bo[0];
927 drm_gem_object_get(&bo[i]->tbo.base);
928 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
929 /* Create an SG BO to DMA-map userptrs on other GPUs */
930 attachment[i]->type = KFD_MEM_ATT_USERPTR;
931 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
932 if (ret)
933 goto unwind;
934 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
935 } else if (mem->bo->tbo.type == ttm_bo_type_sg) {
936 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
937 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
938 "Handing invalid SG BO in ATTACH request");
939 attachment[i]->type = KFD_MEM_ATT_SG;
940 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
941 if (ret)
942 goto unwind;
943 /* Enable acces to GTT and VRAM BOs of peer devices */
944 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
945 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
946 attachment[i]->type = KFD_MEM_ATT_DMABUF;
947 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
948 if (ret)
949 goto unwind;
950 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
951 } else {
952 WARN_ONCE(true, "Handling invalid ATTACH request");
953 ret = -EINVAL;
954 goto unwind;
955 }
956
957 /* Add BO to VM internal data structures */
958 ret = amdgpu_bo_reserve(bo[i], false);
959 if (ret) {
960 pr_debug("Unable to reserve BO during memory attach");
961 goto unwind;
962 }
963 bo_va = amdgpu_vm_bo_find(vm, bo[i]);
964 if (!bo_va)
965 bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
966 else
967 ++bo_va->ref_count;
968 attachment[i]->bo_va = bo_va;
969 amdgpu_bo_unreserve(bo[i]);
970 if (unlikely(!attachment[i]->bo_va)) {
971 ret = -ENOMEM;
972 pr_err("Failed to add BO object to VM. ret == %d\n",
973 ret);
974 goto unwind;
975 }
976 attachment[i]->va = va;
977 attachment[i]->pte_flags = get_pte_flags(adev, mem);
978 attachment[i]->adev = adev;
979 list_add(&attachment[i]->list, &mem->attachments);
980
981 va += bo_size;
982 }
983
984 return 0;
985
986unwind:
987 for (; i >= 0; i--) {
988 if (!attachment[i])
989 continue;
990 if (attachment[i]->bo_va) {
991 amdgpu_bo_reserve(bo[i], true);
992 if (--attachment[i]->bo_va->ref_count == 0)
993 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
994 amdgpu_bo_unreserve(bo[i]);
995 list_del(&attachment[i]->list);
996 }
997 if (bo[i])
998 drm_gem_object_put(&bo[i]->tbo.base);
999 kfree(attachment[i]);
1000 }
1001 return ret;
1002}
1003
1004static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
1005{
1006 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
1007
1008 pr_debug("\t remove VA 0x%llx in entry %p\n",
1009 attachment->va, attachment);
1010 if (--attachment->bo_va->ref_count == 0)
1011 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
1012 drm_gem_object_put(&bo->tbo.base);
1013 list_del(&attachment->list);
1014 kfree(attachment);
1015}
1016
1017static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
1018 struct amdkfd_process_info *process_info,
1019 bool userptr)
1020{
1021 mutex_lock(&process_info->lock);
1022 if (userptr)
1023 list_add_tail(&mem->validate_list,
1024 &process_info->userptr_valid_list);
1025 else
1026 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
1027 mutex_unlock(&process_info->lock);
1028}
1029
1030static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
1031 struct amdkfd_process_info *process_info)
1032{
1033 mutex_lock(&process_info->lock);
1034 list_del(&mem->validate_list);
1035 mutex_unlock(&process_info->lock);
1036}
1037
1038/* Initializes user pages. It registers the MMU notifier and validates
1039 * the userptr BO in the GTT domain.
1040 *
1041 * The BO must already be on the userptr_valid_list. Otherwise an
1042 * eviction and restore may happen that leaves the new BO unmapped
1043 * with the user mode queues running.
1044 *
1045 * Takes the process_info->lock to protect against concurrent restore
1046 * workers.
1047 *
1048 * Returns 0 for success, negative errno for errors.
1049 */
1050static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1051 bool criu_resume)
1052{
1053 struct amdkfd_process_info *process_info = mem->process_info;
1054 struct amdgpu_bo *bo = mem->bo;
1055 struct ttm_operation_ctx ctx = { true, false };
1056 struct hmm_range *range;
1057 int ret = 0;
1058
1059 mutex_lock(&process_info->lock);
1060
1061 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1062 if (ret) {
1063 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1064 goto out;
1065 }
1066
1067 ret = amdgpu_hmm_register(bo, user_addr);
1068 if (ret) {
1069 pr_err("%s: Failed to register MMU notifier: %d\n",
1070 __func__, ret);
1071 goto out;
1072 }
1073
1074 if (criu_resume) {
1075 /*
1076 * During a CRIU restore operation, the userptr buffer objects
1077 * will be validated in the restore_userptr_work worker at a
1078 * later stage when it is scheduled by another ioctl called by
1079 * CRIU master process for the target pid for restore.
1080 */
1081 mutex_lock(&process_info->notifier_lock);
1082 mem->invalid++;
1083 mutex_unlock(&process_info->notifier_lock);
1084 mutex_unlock(&process_info->lock);
1085 return 0;
1086 }
1087
1088 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1089 if (ret) {
1090 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1091 goto unregister_out;
1092 }
1093
1094 ret = amdgpu_bo_reserve(bo, true);
1095 if (ret) {
1096 pr_err("%s: Failed to reserve BO\n", __func__);
1097 goto release_out;
1098 }
1099 amdgpu_bo_placement_from_domain(bo, mem->domain);
1100 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1101 if (ret)
1102 pr_err("%s: failed to validate BO\n", __func__);
1103 amdgpu_bo_unreserve(bo);
1104
1105release_out:
1106 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1107unregister_out:
1108 if (ret)
1109 amdgpu_hmm_unregister(bo);
1110out:
1111 mutex_unlock(&process_info->lock);
1112 return ret;
1113}
1114
1115/* Reserving a BO and its page table BOs must happen atomically to
1116 * avoid deadlocks. Some operations update multiple VMs at once. Track
1117 * all the reservation info in a context structure. Optionally a sync
1118 * object can track VM updates.
1119 */
1120struct bo_vm_reservation_context {
1121 /* DRM execution context for the reservation */
1122 struct drm_exec exec;
1123 /* Number of VMs reserved */
1124 unsigned int n_vms;
1125 /* Pointer to sync object */
1126 struct amdgpu_sync *sync;
1127};
1128
1129enum bo_vm_match {
1130 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
1131 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
1132 BO_VM_ALL, /* Match all VMs a BO was added to */
1133};
1134
1135/**
1136 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1137 * @mem: KFD BO structure.
1138 * @vm: the VM to reserve.
1139 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1140 */
1141static int reserve_bo_and_vm(struct kgd_mem *mem,
1142 struct amdgpu_vm *vm,
1143 struct bo_vm_reservation_context *ctx)
1144{
1145 struct amdgpu_bo *bo = mem->bo;
1146 int ret;
1147
1148 WARN_ON(!vm);
1149
1150 ctx->n_vms = 1;
1151 ctx->sync = &mem->sync;
1152 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1153 drm_exec_until_all_locked(&ctx->exec) {
1154 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1155 drm_exec_retry_on_contention(&ctx->exec);
1156 if (unlikely(ret))
1157 goto error;
1158
1159 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1160 drm_exec_retry_on_contention(&ctx->exec);
1161 if (unlikely(ret))
1162 goto error;
1163 }
1164 return 0;
1165
1166error:
1167 pr_err("Failed to reserve buffers in ttm.\n");
1168 drm_exec_fini(&ctx->exec);
1169 return ret;
1170}
1171
1172/**
1173 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1174 * @mem: KFD BO structure.
1175 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1176 * is used. Otherwise, a single VM associated with the BO.
1177 * @map_type: the mapping status that will be used to filter the VMs.
1178 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1179 *
1180 * Returns 0 for success, negative for failure.
1181 */
1182static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1183 struct amdgpu_vm *vm, enum bo_vm_match map_type,
1184 struct bo_vm_reservation_context *ctx)
1185{
1186 struct kfd_mem_attachment *entry;
1187 struct amdgpu_bo *bo = mem->bo;
1188 int ret;
1189
1190 ctx->sync = &mem->sync;
1191 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1192 drm_exec_until_all_locked(&ctx->exec) {
1193 ctx->n_vms = 0;
1194 list_for_each_entry(entry, &mem->attachments, list) {
1195 if ((vm && vm != entry->bo_va->base.vm) ||
1196 (entry->is_mapped != map_type
1197 && map_type != BO_VM_ALL))
1198 continue;
1199
1200 ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1201 &ctx->exec, 2);
1202 drm_exec_retry_on_contention(&ctx->exec);
1203 if (unlikely(ret))
1204 goto error;
1205 ++ctx->n_vms;
1206 }
1207
1208 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1209 drm_exec_retry_on_contention(&ctx->exec);
1210 if (unlikely(ret))
1211 goto error;
1212 }
1213 return 0;
1214
1215error:
1216 pr_err("Failed to reserve buffers in ttm.\n");
1217 drm_exec_fini(&ctx->exec);
1218 return ret;
1219}
1220
1221/**
1222 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1223 * @ctx: Reservation context to unreserve
1224 * @wait: Optionally wait for a sync object representing pending VM updates
1225 * @intr: Whether the wait is interruptible
1226 *
1227 * Also frees any resources allocated in
1228 * reserve_bo_and_(cond_)vm(s). Returns the status from
1229 * amdgpu_sync_wait.
1230 */
1231static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1232 bool wait, bool intr)
1233{
1234 int ret = 0;
1235
1236 if (wait)
1237 ret = amdgpu_sync_wait(ctx->sync, intr);
1238
1239 drm_exec_fini(&ctx->exec);
1240 ctx->sync = NULL;
1241 return ret;
1242}
1243
1244static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1245 struct kfd_mem_attachment *entry,
1246 struct amdgpu_sync *sync)
1247{
1248 struct amdgpu_bo_va *bo_va = entry->bo_va;
1249 struct amdgpu_device *adev = entry->adev;
1250 struct amdgpu_vm *vm = bo_va->base.vm;
1251
1252 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1253
1254 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1255
1256 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1257}
1258
1259static int update_gpuvm_pte(struct kgd_mem *mem,
1260 struct kfd_mem_attachment *entry,
1261 struct amdgpu_sync *sync)
1262{
1263 struct amdgpu_bo_va *bo_va = entry->bo_va;
1264 struct amdgpu_device *adev = entry->adev;
1265 int ret;
1266
1267 ret = kfd_mem_dmamap_attachment(mem, entry);
1268 if (ret)
1269 return ret;
1270
1271 /* Update the page tables */
1272 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1273 if (ret) {
1274 pr_err("amdgpu_vm_bo_update failed\n");
1275 return ret;
1276 }
1277
1278 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1279}
1280
1281static int map_bo_to_gpuvm(struct kgd_mem *mem,
1282 struct kfd_mem_attachment *entry,
1283 struct amdgpu_sync *sync,
1284 bool no_update_pte)
1285{
1286 int ret;
1287
1288 /* Set virtual address for the allocation */
1289 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1290 amdgpu_bo_size(entry->bo_va->base.bo),
1291 entry->pte_flags);
1292 if (ret) {
1293 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1294 entry->va, ret);
1295 return ret;
1296 }
1297
1298 if (no_update_pte)
1299 return 0;
1300
1301 ret = update_gpuvm_pte(mem, entry, sync);
1302 if (ret) {
1303 pr_err("update_gpuvm_pte() failed\n");
1304 goto update_gpuvm_pte_failed;
1305 }
1306
1307 return 0;
1308
1309update_gpuvm_pte_failed:
1310 unmap_bo_from_gpuvm(mem, entry, sync);
1311 kfd_mem_dmaunmap_attachment(mem, entry);
1312 return ret;
1313}
1314
1315static int process_validate_vms(struct amdkfd_process_info *process_info,
1316 struct ww_acquire_ctx *ticket)
1317{
1318 struct amdgpu_vm *peer_vm;
1319 int ret;
1320
1321 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1322 vm_list_node) {
1323 ret = vm_validate_pt_pd_bos(peer_vm, ticket);
1324 if (ret)
1325 return ret;
1326 }
1327
1328 return 0;
1329}
1330
1331static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1332 struct amdgpu_sync *sync)
1333{
1334 struct amdgpu_vm *peer_vm;
1335 int ret;
1336
1337 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1338 vm_list_node) {
1339 struct amdgpu_bo *pd = peer_vm->root.bo;
1340
1341 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1342 AMDGPU_SYNC_NE_OWNER,
1343 AMDGPU_FENCE_OWNER_KFD);
1344 if (ret)
1345 return ret;
1346 }
1347
1348 return 0;
1349}
1350
1351static int process_update_pds(struct amdkfd_process_info *process_info,
1352 struct amdgpu_sync *sync)
1353{
1354 struct amdgpu_vm *peer_vm;
1355 int ret;
1356
1357 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1358 vm_list_node) {
1359 ret = vm_update_pds(peer_vm, sync);
1360 if (ret)
1361 return ret;
1362 }
1363
1364 return 0;
1365}
1366
1367static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1368 struct dma_fence **ef)
1369{
1370 struct amdkfd_process_info *info = NULL;
1371 int ret;
1372
1373 if (!*process_info) {
1374 info = kzalloc(sizeof(*info), GFP_KERNEL);
1375 if (!info)
1376 return -ENOMEM;
1377
1378 mutex_init(&info->lock);
1379 mutex_init(&info->notifier_lock);
1380 INIT_LIST_HEAD(&info->vm_list_head);
1381 INIT_LIST_HEAD(&info->kfd_bo_list);
1382 INIT_LIST_HEAD(&info->userptr_valid_list);
1383 INIT_LIST_HEAD(&info->userptr_inval_list);
1384
1385 info->eviction_fence =
1386 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1387 current->mm,
1388 NULL);
1389 if (!info->eviction_fence) {
1390 pr_err("Failed to create eviction fence\n");
1391 ret = -ENOMEM;
1392 goto create_evict_fence_fail;
1393 }
1394
1395 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1396 INIT_DELAYED_WORK(&info->restore_userptr_work,
1397 amdgpu_amdkfd_restore_userptr_worker);
1398
1399 *process_info = info;
1400 }
1401
1402 vm->process_info = *process_info;
1403
1404 /* Validate page directory and attach eviction fence */
1405 ret = amdgpu_bo_reserve(vm->root.bo, true);
1406 if (ret)
1407 goto reserve_pd_fail;
1408 ret = vm_validate_pt_pd_bos(vm, NULL);
1409 if (ret) {
1410 pr_err("validate_pt_pd_bos() failed\n");
1411 goto validate_pd_fail;
1412 }
1413 ret = amdgpu_bo_sync_wait(vm->root.bo,
1414 AMDGPU_FENCE_OWNER_KFD, false);
1415 if (ret)
1416 goto wait_pd_fail;
1417 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1418 if (ret)
1419 goto reserve_shared_fail;
1420 dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1421 &vm->process_info->eviction_fence->base,
1422 DMA_RESV_USAGE_BOOKKEEP);
1423 amdgpu_bo_unreserve(vm->root.bo);
1424
1425 /* Update process info */
1426 mutex_lock(&vm->process_info->lock);
1427 list_add_tail(&vm->vm_list_node,
1428 &(vm->process_info->vm_list_head));
1429 vm->process_info->n_vms++;
1430
1431 *ef = dma_fence_get(&vm->process_info->eviction_fence->base);
1432 mutex_unlock(&vm->process_info->lock);
1433
1434 return 0;
1435
1436reserve_shared_fail:
1437wait_pd_fail:
1438validate_pd_fail:
1439 amdgpu_bo_unreserve(vm->root.bo);
1440reserve_pd_fail:
1441 vm->process_info = NULL;
1442 if (info) {
1443 dma_fence_put(&info->eviction_fence->base);
1444 *process_info = NULL;
1445 put_pid(info->pid);
1446create_evict_fence_fail:
1447 mutex_destroy(&info->lock);
1448 mutex_destroy(&info->notifier_lock);
1449 kfree(info);
1450 }
1451 return ret;
1452}
1453
1454/**
1455 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1456 * @bo: Handle of buffer object being pinned
1457 * @domain: Domain into which BO should be pinned
1458 *
1459 * - USERPTR BOs are UNPINNABLE and will return error
1460 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1461 * PIN count incremented. It is valid to PIN a BO multiple times
1462 *
1463 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1464 */
1465static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1466{
1467 int ret = 0;
1468
1469 ret = amdgpu_bo_reserve(bo, false);
1470 if (unlikely(ret))
1471 return ret;
1472
1473 ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1474 if (ret)
1475 pr_err("Error in Pinning BO to domain: %d\n", domain);
1476
1477 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1478 amdgpu_bo_unreserve(bo);
1479
1480 return ret;
1481}
1482
1483/**
1484 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1485 * @bo: Handle of buffer object being unpinned
1486 *
1487 * - Is a illegal request for USERPTR BOs and is ignored
1488 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1489 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1490 */
1491static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1492{
1493 int ret = 0;
1494
1495 ret = amdgpu_bo_reserve(bo, false);
1496 if (unlikely(ret))
1497 return;
1498
1499 amdgpu_bo_unpin(bo);
1500 amdgpu_bo_unreserve(bo);
1501}
1502
1503int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1504 struct amdgpu_vm *avm, u32 pasid)
1505
1506{
1507 int ret;
1508
1509 /* Free the original amdgpu allocated pasid,
1510 * will be replaced with kfd allocated pasid.
1511 */
1512 if (avm->pasid) {
1513 amdgpu_pasid_free(avm->pasid);
1514 amdgpu_vm_set_pasid(adev, avm, 0);
1515 }
1516
1517 ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1518 if (ret)
1519 return ret;
1520
1521 return 0;
1522}
1523
1524int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1525 struct amdgpu_vm *avm,
1526 void **process_info,
1527 struct dma_fence **ef)
1528{
1529 int ret;
1530
1531 /* Already a compute VM? */
1532 if (avm->process_info)
1533 return -EINVAL;
1534
1535 /* Convert VM into a compute VM */
1536 ret = amdgpu_vm_make_compute(adev, avm);
1537 if (ret)
1538 return ret;
1539
1540 /* Initialize KFD part of the VM and process info */
1541 ret = init_kfd_vm(avm, process_info, ef);
1542 if (ret)
1543 return ret;
1544
1545 amdgpu_vm_set_task_info(avm);
1546
1547 return 0;
1548}
1549
1550void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1551 struct amdgpu_vm *vm)
1552{
1553 struct amdkfd_process_info *process_info = vm->process_info;
1554
1555 if (!process_info)
1556 return;
1557
1558 /* Update process info */
1559 mutex_lock(&process_info->lock);
1560 process_info->n_vms--;
1561 list_del(&vm->vm_list_node);
1562 mutex_unlock(&process_info->lock);
1563
1564 vm->process_info = NULL;
1565
1566 /* Release per-process resources when last compute VM is destroyed */
1567 if (!process_info->n_vms) {
1568 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1569 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1570 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1571
1572 dma_fence_put(&process_info->eviction_fence->base);
1573 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1574 put_pid(process_info->pid);
1575 mutex_destroy(&process_info->lock);
1576 mutex_destroy(&process_info->notifier_lock);
1577 kfree(process_info);
1578 }
1579}
1580
1581void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1582 void *drm_priv)
1583{
1584 struct amdgpu_vm *avm;
1585
1586 if (WARN_ON(!adev || !drm_priv))
1587 return;
1588
1589 avm = drm_priv_to_vm(drm_priv);
1590
1591 pr_debug("Releasing process vm %p\n", avm);
1592
1593 /* The original pasid of amdgpu vm has already been
1594 * released during making a amdgpu vm to a compute vm
1595 * The current pasid is managed by kfd and will be
1596 * released on kfd process destroy. Set amdgpu pasid
1597 * to 0 to avoid duplicate release.
1598 */
1599 amdgpu_vm_release_compute(adev, avm);
1600}
1601
1602uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1603{
1604 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1605 struct amdgpu_bo *pd = avm->root.bo;
1606 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1607
1608 if (adev->asic_type < CHIP_VEGA10)
1609 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1610 return avm->pd_phys_addr;
1611}
1612
1613void amdgpu_amdkfd_block_mmu_notifications(void *p)
1614{
1615 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1616
1617 mutex_lock(&pinfo->lock);
1618 WRITE_ONCE(pinfo->block_mmu_notifications, true);
1619 mutex_unlock(&pinfo->lock);
1620}
1621
1622int amdgpu_amdkfd_criu_resume(void *p)
1623{
1624 int ret = 0;
1625 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1626
1627 mutex_lock(&pinfo->lock);
1628 pr_debug("scheduling work\n");
1629 mutex_lock(&pinfo->notifier_lock);
1630 pinfo->evicted_bos++;
1631 mutex_unlock(&pinfo->notifier_lock);
1632 if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1633 ret = -EINVAL;
1634 goto out_unlock;
1635 }
1636 WRITE_ONCE(pinfo->block_mmu_notifications, false);
1637 queue_delayed_work(system_freezable_wq,
1638 &pinfo->restore_userptr_work, 0);
1639
1640out_unlock:
1641 mutex_unlock(&pinfo->lock);
1642 return ret;
1643}
1644
1645size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1646 uint8_t xcp_id)
1647{
1648 uint64_t reserved_for_pt =
1649 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1650 ssize_t available;
1651 uint64_t vram_available, system_mem_available, ttm_mem_available;
1652
1653 spin_lock(&kfd_mem_limit.mem_limit_lock);
1654 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1655 - adev->kfd.vram_used_aligned[xcp_id]
1656 - atomic64_read(&adev->vram_pin_size)
1657 - reserved_for_pt;
1658
1659 if (adev->gmc.is_app_apu) {
1660 system_mem_available = no_system_mem_limit ?
1661 kfd_mem_limit.max_system_mem_limit :
1662 kfd_mem_limit.max_system_mem_limit -
1663 kfd_mem_limit.system_mem_used;
1664
1665 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1666 kfd_mem_limit.ttm_mem_used;
1667
1668 available = min3(system_mem_available, ttm_mem_available,
1669 vram_available);
1670 available = ALIGN_DOWN(available, PAGE_SIZE);
1671 } else {
1672 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1673 }
1674
1675 spin_unlock(&kfd_mem_limit.mem_limit_lock);
1676
1677 if (available < 0)
1678 available = 0;
1679
1680 return available;
1681}
1682
1683int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1684 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1685 void *drm_priv, struct kgd_mem **mem,
1686 uint64_t *offset, uint32_t flags, bool criu_resume)
1687{
1688 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1689 struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1690 enum ttm_bo_type bo_type = ttm_bo_type_device;
1691 struct sg_table *sg = NULL;
1692 uint64_t user_addr = 0;
1693 struct amdgpu_bo *bo;
1694 struct drm_gem_object *gobj = NULL;
1695 u32 domain, alloc_domain;
1696 uint64_t aligned_size;
1697 int8_t xcp_id = -1;
1698 u64 alloc_flags;
1699 int ret;
1700
1701 /*
1702 * Check on which domain to allocate BO
1703 */
1704 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1705 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1706
1707 if (adev->gmc.is_app_apu) {
1708 domain = AMDGPU_GEM_DOMAIN_GTT;
1709 alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1710 alloc_flags = 0;
1711 } else {
1712 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1713 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1714 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1715 }
1716 xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1717 0 : fpriv->xcp_id;
1718 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1719 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1720 alloc_flags = 0;
1721 } else {
1722 domain = AMDGPU_GEM_DOMAIN_GTT;
1723 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1724 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1725
1726 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1727 if (!offset || !*offset)
1728 return -EINVAL;
1729 user_addr = untagged_addr(*offset);
1730 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1731 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1732 bo_type = ttm_bo_type_sg;
1733 if (size > UINT_MAX)
1734 return -EINVAL;
1735 sg = create_sg_table(*offset, size);
1736 if (!sg)
1737 return -ENOMEM;
1738 } else {
1739 return -EINVAL;
1740 }
1741 }
1742
1743 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1744 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1745 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT)
1746 alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT;
1747 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1748 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1749
1750 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1751 if (!*mem) {
1752 ret = -ENOMEM;
1753 goto err;
1754 }
1755 INIT_LIST_HEAD(&(*mem)->attachments);
1756 mutex_init(&(*mem)->lock);
1757 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1758
1759 /* Workaround for AQL queue wraparound bug. Map the same
1760 * memory twice. That means we only actually allocate half
1761 * the memory.
1762 */
1763 if ((*mem)->aql_queue)
1764 size >>= 1;
1765 aligned_size = PAGE_ALIGN(size);
1766
1767 (*mem)->alloc_flags = flags;
1768
1769 amdgpu_sync_create(&(*mem)->sync);
1770
1771 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1772 xcp_id);
1773 if (ret) {
1774 pr_debug("Insufficient memory\n");
1775 goto err_reserve_limit;
1776 }
1777
1778 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1779 va, (*mem)->aql_queue ? size << 1 : size,
1780 domain_string(alloc_domain), xcp_id);
1781
1782 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1783 bo_type, NULL, &gobj, xcp_id + 1);
1784 if (ret) {
1785 pr_debug("Failed to create BO on domain %s. ret %d\n",
1786 domain_string(alloc_domain), ret);
1787 goto err_bo_create;
1788 }
1789 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1790 if (ret) {
1791 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1792 goto err_node_allow;
1793 }
1794 ret = drm_gem_handle_create(adev->kfd.client.file, gobj, &(*mem)->gem_handle);
1795 if (ret)
1796 goto err_gem_handle_create;
1797 bo = gem_to_amdgpu_bo(gobj);
1798 if (bo_type == ttm_bo_type_sg) {
1799 bo->tbo.sg = sg;
1800 bo->tbo.ttm->sg = sg;
1801 }
1802 bo->kfd_bo = *mem;
1803 (*mem)->bo = bo;
1804 if (user_addr)
1805 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1806
1807 (*mem)->va = va;
1808 (*mem)->domain = domain;
1809 (*mem)->mapped_to_gpu_memory = 0;
1810 (*mem)->process_info = avm->process_info;
1811
1812 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1813
1814 if (user_addr) {
1815 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1816 ret = init_user_pages(*mem, user_addr, criu_resume);
1817 if (ret)
1818 goto allocate_init_user_pages_failed;
1819 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1820 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1821 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1822 if (ret) {
1823 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1824 goto err_pin_bo;
1825 }
1826 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1827 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1828 } else {
1829 mutex_lock(&avm->process_info->lock);
1830 if (avm->process_info->eviction_fence &&
1831 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
1832 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain,
1833 &avm->process_info->eviction_fence->base);
1834 mutex_unlock(&avm->process_info->lock);
1835 if (ret)
1836 goto err_validate_bo;
1837 }
1838
1839 if (offset)
1840 *offset = amdgpu_bo_mmap_offset(bo);
1841
1842 return 0;
1843
1844allocate_init_user_pages_failed:
1845err_pin_bo:
1846err_validate_bo:
1847 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1848 drm_gem_handle_delete(adev->kfd.client.file, (*mem)->gem_handle);
1849err_gem_handle_create:
1850 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1851err_node_allow:
1852 /* Don't unreserve system mem limit twice */
1853 goto err_reserve_limit;
1854err_bo_create:
1855 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1856err_reserve_limit:
1857 amdgpu_sync_free(&(*mem)->sync);
1858 mutex_destroy(&(*mem)->lock);
1859 if (gobj)
1860 drm_gem_object_put(gobj);
1861 else
1862 kfree(*mem);
1863err:
1864 if (sg) {
1865 sg_free_table(sg);
1866 kfree(sg);
1867 }
1868 return ret;
1869}
1870
1871int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1872 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1873 uint64_t *size)
1874{
1875 struct amdkfd_process_info *process_info = mem->process_info;
1876 unsigned long bo_size = mem->bo->tbo.base.size;
1877 bool use_release_notifier = (mem->bo->kfd_bo == mem);
1878 struct kfd_mem_attachment *entry, *tmp;
1879 struct bo_vm_reservation_context ctx;
1880 unsigned int mapped_to_gpu_memory;
1881 int ret;
1882 bool is_imported = false;
1883
1884 mutex_lock(&mem->lock);
1885
1886 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1887 if (mem->alloc_flags &
1888 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1889 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1890 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1891 }
1892
1893 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1894 is_imported = mem->is_imported;
1895 mutex_unlock(&mem->lock);
1896 /* lock is not needed after this, since mem is unused and will
1897 * be freed anyway
1898 */
1899
1900 if (mapped_to_gpu_memory > 0) {
1901 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1902 mem->va, bo_size);
1903 return -EBUSY;
1904 }
1905
1906 /* Make sure restore workers don't access the BO any more */
1907 mutex_lock(&process_info->lock);
1908 list_del(&mem->validate_list);
1909 mutex_unlock(&process_info->lock);
1910
1911 /* Cleanup user pages and MMU notifiers */
1912 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1913 amdgpu_hmm_unregister(mem->bo);
1914 mutex_lock(&process_info->notifier_lock);
1915 amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1916 mutex_unlock(&process_info->notifier_lock);
1917 }
1918
1919 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1920 if (unlikely(ret))
1921 return ret;
1922
1923 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1924 process_info->eviction_fence);
1925 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1926 mem->va + bo_size * (1 + mem->aql_queue));
1927
1928 /* Remove from VM internal data structures */
1929 list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
1930 kfd_mem_dmaunmap_attachment(mem, entry);
1931 kfd_mem_detach(entry);
1932 }
1933
1934 ret = unreserve_bo_and_vms(&ctx, false, false);
1935
1936 /* Free the sync object */
1937 amdgpu_sync_free(&mem->sync);
1938
1939 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1940 * remap BO. We need to free it.
1941 */
1942 if (mem->bo->tbo.sg) {
1943 sg_free_table(mem->bo->tbo.sg);
1944 kfree(mem->bo->tbo.sg);
1945 }
1946
1947 /* Update the size of the BO being freed if it was allocated from
1948 * VRAM and is not imported. For APP APU VRAM allocations are done
1949 * in GTT domain
1950 */
1951 if (size) {
1952 if (!is_imported &&
1953 (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1954 (adev->gmc.is_app_apu &&
1955 mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1956 *size = bo_size;
1957 else
1958 *size = 0;
1959 }
1960
1961 /* Free the BO*/
1962 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1963 drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle);
1964 if (mem->dmabuf) {
1965 dma_buf_put(mem->dmabuf);
1966 mem->dmabuf = NULL;
1967 }
1968 mutex_destroy(&mem->lock);
1969
1970 /* If this releases the last reference, it will end up calling
1971 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1972 * this needs to be the last call here.
1973 */
1974 drm_gem_object_put(&mem->bo->tbo.base);
1975
1976 /*
1977 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
1978 * explicitly free it here.
1979 */
1980 if (!use_release_notifier)
1981 kfree(mem);
1982
1983 return ret;
1984}
1985
1986int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1987 struct amdgpu_device *adev, struct kgd_mem *mem,
1988 void *drm_priv)
1989{
1990 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1991 int ret;
1992 struct amdgpu_bo *bo;
1993 uint32_t domain;
1994 struct kfd_mem_attachment *entry;
1995 struct bo_vm_reservation_context ctx;
1996 unsigned long bo_size;
1997 bool is_invalid_userptr = false;
1998
1999 bo = mem->bo;
2000 if (!bo) {
2001 pr_err("Invalid BO when mapping memory to GPU\n");
2002 return -EINVAL;
2003 }
2004
2005 /* Make sure restore is not running concurrently. Since we
2006 * don't map invalid userptr BOs, we rely on the next restore
2007 * worker to do the mapping
2008 */
2009 mutex_lock(&mem->process_info->lock);
2010
2011 /* Lock notifier lock. If we find an invalid userptr BO, we can be
2012 * sure that the MMU notifier is no longer running
2013 * concurrently and the queues are actually stopped
2014 */
2015 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2016 mutex_lock(&mem->process_info->notifier_lock);
2017 is_invalid_userptr = !!mem->invalid;
2018 mutex_unlock(&mem->process_info->notifier_lock);
2019 }
2020
2021 mutex_lock(&mem->lock);
2022
2023 domain = mem->domain;
2024 bo_size = bo->tbo.base.size;
2025
2026 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
2027 mem->va,
2028 mem->va + bo_size * (1 + mem->aql_queue),
2029 avm, domain_string(domain));
2030
2031 if (!kfd_mem_is_attached(avm, mem)) {
2032 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
2033 if (ret)
2034 goto out;
2035 }
2036
2037 ret = reserve_bo_and_vm(mem, avm, &ctx);
2038 if (unlikely(ret))
2039 goto out;
2040
2041 /* Userptr can be marked as "not invalid", but not actually be
2042 * validated yet (still in the system domain). In that case
2043 * the queues are still stopped and we can leave mapping for
2044 * the next restore worker
2045 */
2046 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
2047 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
2048 is_invalid_userptr = true;
2049
2050 ret = vm_validate_pt_pd_bos(avm, NULL);
2051 if (unlikely(ret))
2052 goto out_unreserve;
2053
2054 list_for_each_entry(entry, &mem->attachments, list) {
2055 if (entry->bo_va->base.vm != avm || entry->is_mapped)
2056 continue;
2057
2058 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2059 entry->va, entry->va + bo_size, entry);
2060
2061 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2062 is_invalid_userptr);
2063 if (ret) {
2064 pr_err("Failed to map bo to gpuvm\n");
2065 goto out_unreserve;
2066 }
2067
2068 ret = vm_update_pds(avm, ctx.sync);
2069 if (ret) {
2070 pr_err("Failed to update page directories\n");
2071 goto out_unreserve;
2072 }
2073
2074 entry->is_mapped = true;
2075 mem->mapped_to_gpu_memory++;
2076 pr_debug("\t INC mapping count %d\n",
2077 mem->mapped_to_gpu_memory);
2078 }
2079
2080 ret = unreserve_bo_and_vms(&ctx, false, false);
2081
2082 goto out;
2083
2084out_unreserve:
2085 unreserve_bo_and_vms(&ctx, false, false);
2086out:
2087 mutex_unlock(&mem->process_info->lock);
2088 mutex_unlock(&mem->lock);
2089 return ret;
2090}
2091
2092int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv)
2093{
2094 struct kfd_mem_attachment *entry;
2095 struct amdgpu_vm *vm;
2096 int ret;
2097
2098 vm = drm_priv_to_vm(drm_priv);
2099
2100 mutex_lock(&mem->lock);
2101
2102 ret = amdgpu_bo_reserve(mem->bo, true);
2103 if (ret)
2104 goto out;
2105
2106 list_for_each_entry(entry, &mem->attachments, list) {
2107 if (entry->bo_va->base.vm != vm)
2108 continue;
2109 if (entry->bo_va->base.bo->tbo.ttm &&
2110 !entry->bo_va->base.bo->tbo.ttm->sg)
2111 continue;
2112
2113 kfd_mem_dmaunmap_attachment(mem, entry);
2114 }
2115
2116 amdgpu_bo_unreserve(mem->bo);
2117out:
2118 mutex_unlock(&mem->lock);
2119
2120 return ret;
2121}
2122
2123int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2124 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2125{
2126 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2127 unsigned long bo_size = mem->bo->tbo.base.size;
2128 struct kfd_mem_attachment *entry;
2129 struct bo_vm_reservation_context ctx;
2130 int ret;
2131
2132 mutex_lock(&mem->lock);
2133
2134 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2135 if (unlikely(ret))
2136 goto out;
2137 /* If no VMs were reserved, it means the BO wasn't actually mapped */
2138 if (ctx.n_vms == 0) {
2139 ret = -EINVAL;
2140 goto unreserve_out;
2141 }
2142
2143 ret = vm_validate_pt_pd_bos(avm, NULL);
2144 if (unlikely(ret))
2145 goto unreserve_out;
2146
2147 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2148 mem->va,
2149 mem->va + bo_size * (1 + mem->aql_queue),
2150 avm);
2151
2152 list_for_each_entry(entry, &mem->attachments, list) {
2153 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2154 continue;
2155
2156 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2157 entry->va, entry->va + bo_size, entry);
2158
2159 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2160 entry->is_mapped = false;
2161
2162 mem->mapped_to_gpu_memory--;
2163 pr_debug("\t DEC mapping count %d\n",
2164 mem->mapped_to_gpu_memory);
2165 }
2166
2167unreserve_out:
2168 unreserve_bo_and_vms(&ctx, false, false);
2169out:
2170 mutex_unlock(&mem->lock);
2171 return ret;
2172}
2173
2174int amdgpu_amdkfd_gpuvm_sync_memory(
2175 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2176{
2177 struct amdgpu_sync sync;
2178 int ret;
2179
2180 amdgpu_sync_create(&sync);
2181
2182 mutex_lock(&mem->lock);
2183 amdgpu_sync_clone(&mem->sync, &sync);
2184 mutex_unlock(&mem->lock);
2185
2186 ret = amdgpu_sync_wait(&sync, intr);
2187 amdgpu_sync_free(&sync);
2188 return ret;
2189}
2190
2191/**
2192 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2193 * @bo: Buffer object to be mapped
2194 *
2195 * Before return, bo reference count is incremented. To release the reference and unpin/
2196 * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2197 */
2198int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
2199{
2200 int ret;
2201
2202 ret = amdgpu_bo_reserve(bo, true);
2203 if (ret) {
2204 pr_err("Failed to reserve bo. ret %d\n", ret);
2205 goto err_reserve_bo_failed;
2206 }
2207
2208 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2209 if (ret) {
2210 pr_err("Failed to pin bo. ret %d\n", ret);
2211 goto err_pin_bo_failed;
2212 }
2213
2214 ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2215 if (ret) {
2216 pr_err("Failed to bind bo to GART. ret %d\n", ret);
2217 goto err_map_bo_gart_failed;
2218 }
2219
2220 amdgpu_amdkfd_remove_eviction_fence(
2221 bo, bo->vm_bo->vm->process_info->eviction_fence);
2222
2223 amdgpu_bo_unreserve(bo);
2224
2225 bo = amdgpu_bo_ref(bo);
2226
2227 return 0;
2228
2229err_map_bo_gart_failed:
2230 amdgpu_bo_unpin(bo);
2231err_pin_bo_failed:
2232 amdgpu_bo_unreserve(bo);
2233err_reserve_bo_failed:
2234
2235 return ret;
2236}
2237
2238/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2239 *
2240 * @mem: Buffer object to be mapped for CPU access
2241 * @kptr[out]: pointer in kernel CPU address space
2242 * @size[out]: size of the buffer
2243 *
2244 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2245 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2246 * validate_list, so the GPU mapping can be restored after a page table was
2247 * evicted.
2248 *
2249 * Return: 0 on success, error code on failure
2250 */
2251int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2252 void **kptr, uint64_t *size)
2253{
2254 int ret;
2255 struct amdgpu_bo *bo = mem->bo;
2256
2257 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2258 pr_err("userptr can't be mapped to kernel\n");
2259 return -EINVAL;
2260 }
2261
2262 mutex_lock(&mem->process_info->lock);
2263
2264 ret = amdgpu_bo_reserve(bo, true);
2265 if (ret) {
2266 pr_err("Failed to reserve bo. ret %d\n", ret);
2267 goto bo_reserve_failed;
2268 }
2269
2270 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2271 if (ret) {
2272 pr_err("Failed to pin bo. ret %d\n", ret);
2273 goto pin_failed;
2274 }
2275
2276 ret = amdgpu_bo_kmap(bo, kptr);
2277 if (ret) {
2278 pr_err("Failed to map bo to kernel. ret %d\n", ret);
2279 goto kmap_failed;
2280 }
2281
2282 amdgpu_amdkfd_remove_eviction_fence(
2283 bo, mem->process_info->eviction_fence);
2284
2285 if (size)
2286 *size = amdgpu_bo_size(bo);
2287
2288 amdgpu_bo_unreserve(bo);
2289
2290 mutex_unlock(&mem->process_info->lock);
2291 return 0;
2292
2293kmap_failed:
2294 amdgpu_bo_unpin(bo);
2295pin_failed:
2296 amdgpu_bo_unreserve(bo);
2297bo_reserve_failed:
2298 mutex_unlock(&mem->process_info->lock);
2299
2300 return ret;
2301}
2302
2303/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2304 *
2305 * @mem: Buffer object to be unmapped for CPU access
2306 *
2307 * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2308 * eviction fence, so this function should only be used for cleanup before the
2309 * BO is destroyed.
2310 */
2311void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2312{
2313 struct amdgpu_bo *bo = mem->bo;
2314
2315 amdgpu_bo_reserve(bo, true);
2316 amdgpu_bo_kunmap(bo);
2317 amdgpu_bo_unpin(bo);
2318 amdgpu_bo_unreserve(bo);
2319}
2320
2321int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2322 struct kfd_vm_fault_info *mem)
2323{
2324 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2325 *mem = *adev->gmc.vm_fault_info;
2326 mb(); /* make sure read happened */
2327 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2328 }
2329 return 0;
2330}
2331
2332static int import_obj_create(struct amdgpu_device *adev,
2333 struct dma_buf *dma_buf,
2334 struct drm_gem_object *obj,
2335 uint64_t va, void *drm_priv,
2336 struct kgd_mem **mem, uint64_t *size,
2337 uint64_t *mmap_offset)
2338{
2339 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2340 struct amdgpu_bo *bo;
2341 int ret;
2342
2343 bo = gem_to_amdgpu_bo(obj);
2344 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2345 AMDGPU_GEM_DOMAIN_GTT)))
2346 /* Only VRAM and GTT BOs are supported */
2347 return -EINVAL;
2348
2349 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2350 if (!*mem)
2351 return -ENOMEM;
2352
2353 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2354 if (ret)
2355 goto err_free_mem;
2356
2357 if (size)
2358 *size = amdgpu_bo_size(bo);
2359
2360 if (mmap_offset)
2361 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2362
2363 INIT_LIST_HEAD(&(*mem)->attachments);
2364 mutex_init(&(*mem)->lock);
2365
2366 (*mem)->alloc_flags =
2367 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2368 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2369 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2370 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2371
2372 get_dma_buf(dma_buf);
2373 (*mem)->dmabuf = dma_buf;
2374 (*mem)->bo = bo;
2375 (*mem)->va = va;
2376 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->gmc.is_app_apu ?
2377 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2378
2379 (*mem)->mapped_to_gpu_memory = 0;
2380 (*mem)->process_info = avm->process_info;
2381 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2382 amdgpu_sync_create(&(*mem)->sync);
2383 (*mem)->is_imported = true;
2384
2385 mutex_lock(&avm->process_info->lock);
2386 if (avm->process_info->eviction_fence &&
2387 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
2388 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, (*mem)->domain,
2389 &avm->process_info->eviction_fence->base);
2390 mutex_unlock(&avm->process_info->lock);
2391 if (ret)
2392 goto err_remove_mem;
2393
2394 return 0;
2395
2396err_remove_mem:
2397 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
2398 drm_vma_node_revoke(&obj->vma_node, drm_priv);
2399err_free_mem:
2400 kfree(*mem);
2401 return ret;
2402}
2403
2404int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
2405 uint64_t va, void *drm_priv,
2406 struct kgd_mem **mem, uint64_t *size,
2407 uint64_t *mmap_offset)
2408{
2409 struct drm_gem_object *obj;
2410 uint32_t handle;
2411 int ret;
2412
2413 ret = drm_gem_prime_fd_to_handle(&adev->ddev, adev->kfd.client.file, fd,
2414 &handle);
2415 if (ret)
2416 return ret;
2417 obj = drm_gem_object_lookup(adev->kfd.client.file, handle);
2418 if (!obj) {
2419 ret = -EINVAL;
2420 goto err_release_handle;
2421 }
2422
2423 ret = import_obj_create(adev, obj->dma_buf, obj, va, drm_priv, mem, size,
2424 mmap_offset);
2425 if (ret)
2426 goto err_put_obj;
2427
2428 (*mem)->gem_handle = handle;
2429
2430 return 0;
2431
2432err_put_obj:
2433 drm_gem_object_put(obj);
2434err_release_handle:
2435 drm_gem_handle_delete(adev->kfd.client.file, handle);
2436 return ret;
2437}
2438
2439int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2440 struct dma_buf **dma_buf)
2441{
2442 int ret;
2443
2444 mutex_lock(&mem->lock);
2445 ret = kfd_mem_export_dmabuf(mem);
2446 if (ret)
2447 goto out;
2448
2449 get_dma_buf(mem->dmabuf);
2450 *dma_buf = mem->dmabuf;
2451out:
2452 mutex_unlock(&mem->lock);
2453 return ret;
2454}
2455
2456/* Evict a userptr BO by stopping the queues if necessary
2457 *
2458 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2459 * cannot do any memory allocations, and cannot take any locks that
2460 * are held elsewhere while allocating memory.
2461 *
2462 * It doesn't do anything to the BO itself. The real work happens in
2463 * restore, where we get updated page addresses. This function only
2464 * ensures that GPU access to the BO is stopped.
2465 */
2466int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2467 unsigned long cur_seq, struct kgd_mem *mem)
2468{
2469 struct amdkfd_process_info *process_info = mem->process_info;
2470 int r = 0;
2471
2472 /* Do not process MMU notifications during CRIU restore until
2473 * KFD_CRIU_OP_RESUME IOCTL is received
2474 */
2475 if (READ_ONCE(process_info->block_mmu_notifications))
2476 return 0;
2477
2478 mutex_lock(&process_info->notifier_lock);
2479 mmu_interval_set_seq(mni, cur_seq);
2480
2481 mem->invalid++;
2482 if (++process_info->evicted_bos == 1) {
2483 /* First eviction, stop the queues */
2484 r = kgd2kfd_quiesce_mm(mni->mm,
2485 KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2486 if (r)
2487 pr_err("Failed to quiesce KFD\n");
2488 queue_delayed_work(system_freezable_wq,
2489 &process_info->restore_userptr_work,
2490 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2491 }
2492 mutex_unlock(&process_info->notifier_lock);
2493
2494 return r;
2495}
2496
2497/* Update invalid userptr BOs
2498 *
2499 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2500 * userptr_inval_list and updates user pages for all BOs that have
2501 * been invalidated since their last update.
2502 */
2503static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2504 struct mm_struct *mm)
2505{
2506 struct kgd_mem *mem, *tmp_mem;
2507 struct amdgpu_bo *bo;
2508 struct ttm_operation_ctx ctx = { false, false };
2509 uint32_t invalid;
2510 int ret = 0;
2511
2512 mutex_lock(&process_info->notifier_lock);
2513
2514 /* Move all invalidated BOs to the userptr_inval_list */
2515 list_for_each_entry_safe(mem, tmp_mem,
2516 &process_info->userptr_valid_list,
2517 validate_list)
2518 if (mem->invalid)
2519 list_move_tail(&mem->validate_list,
2520 &process_info->userptr_inval_list);
2521
2522 /* Go through userptr_inval_list and update any invalid user_pages */
2523 list_for_each_entry(mem, &process_info->userptr_inval_list,
2524 validate_list) {
2525 invalid = mem->invalid;
2526 if (!invalid)
2527 /* BO hasn't been invalidated since the last
2528 * revalidation attempt. Keep its page list.
2529 */
2530 continue;
2531
2532 bo = mem->bo;
2533
2534 amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2535 mem->range = NULL;
2536
2537 /* BO reservations and getting user pages (hmm_range_fault)
2538 * must happen outside the notifier lock
2539 */
2540 mutex_unlock(&process_info->notifier_lock);
2541
2542 /* Move the BO to system (CPU) domain if necessary to unmap
2543 * and free the SG table
2544 */
2545 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2546 if (amdgpu_bo_reserve(bo, true))
2547 return -EAGAIN;
2548 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2549 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2550 amdgpu_bo_unreserve(bo);
2551 if (ret) {
2552 pr_err("%s: Failed to invalidate userptr BO\n",
2553 __func__);
2554 return -EAGAIN;
2555 }
2556 }
2557
2558 /* Get updated user pages */
2559 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2560 &mem->range);
2561 if (ret) {
2562 pr_debug("Failed %d to get user pages\n", ret);
2563
2564 /* Return -EFAULT bad address error as success. It will
2565 * fail later with a VM fault if the GPU tries to access
2566 * it. Better than hanging indefinitely with stalled
2567 * user mode queues.
2568 *
2569 * Return other error -EBUSY or -ENOMEM to retry restore
2570 */
2571 if (ret != -EFAULT)
2572 return ret;
2573
2574 ret = 0;
2575 }
2576
2577 mutex_lock(&process_info->notifier_lock);
2578
2579 /* Mark the BO as valid unless it was invalidated
2580 * again concurrently.
2581 */
2582 if (mem->invalid != invalid) {
2583 ret = -EAGAIN;
2584 goto unlock_out;
2585 }
2586 /* set mem valid if mem has hmm range associated */
2587 if (mem->range)
2588 mem->invalid = 0;
2589 }
2590
2591unlock_out:
2592 mutex_unlock(&process_info->notifier_lock);
2593
2594 return ret;
2595}
2596
2597/* Validate invalid userptr BOs
2598 *
2599 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2600 * with new page addresses and waits for the page table updates to complete.
2601 */
2602static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2603{
2604 struct ttm_operation_ctx ctx = { false, false };
2605 struct amdgpu_sync sync;
2606 struct drm_exec exec;
2607
2608 struct amdgpu_vm *peer_vm;
2609 struct kgd_mem *mem, *tmp_mem;
2610 struct amdgpu_bo *bo;
2611 int ret;
2612
2613 amdgpu_sync_create(&sync);
2614
2615 drm_exec_init(&exec, 0, 0);
2616 /* Reserve all BOs and page tables for validation */
2617 drm_exec_until_all_locked(&exec) {
2618 /* Reserve all the page directories */
2619 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2620 vm_list_node) {
2621 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2622 drm_exec_retry_on_contention(&exec);
2623 if (unlikely(ret))
2624 goto unreserve_out;
2625 }
2626
2627 /* Reserve the userptr_inval_list entries to resv_list */
2628 list_for_each_entry(mem, &process_info->userptr_inval_list,
2629 validate_list) {
2630 struct drm_gem_object *gobj;
2631
2632 gobj = &mem->bo->tbo.base;
2633 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2634 drm_exec_retry_on_contention(&exec);
2635 if (unlikely(ret))
2636 goto unreserve_out;
2637 }
2638 }
2639
2640 ret = process_validate_vms(process_info, NULL);
2641 if (ret)
2642 goto unreserve_out;
2643
2644 /* Validate BOs and update GPUVM page tables */
2645 list_for_each_entry_safe(mem, tmp_mem,
2646 &process_info->userptr_inval_list,
2647 validate_list) {
2648 struct kfd_mem_attachment *attachment;
2649
2650 bo = mem->bo;
2651
2652 /* Validate the BO if we got user pages */
2653 if (bo->tbo.ttm->pages[0]) {
2654 amdgpu_bo_placement_from_domain(bo, mem->domain);
2655 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2656 if (ret) {
2657 pr_err("%s: failed to validate BO\n", __func__);
2658 goto unreserve_out;
2659 }
2660 }
2661
2662 /* Update mapping. If the BO was not validated
2663 * (because we couldn't get user pages), this will
2664 * clear the page table entries, which will result in
2665 * VM faults if the GPU tries to access the invalid
2666 * memory.
2667 */
2668 list_for_each_entry(attachment, &mem->attachments, list) {
2669 if (!attachment->is_mapped)
2670 continue;
2671
2672 kfd_mem_dmaunmap_attachment(mem, attachment);
2673 ret = update_gpuvm_pte(mem, attachment, &sync);
2674 if (ret) {
2675 pr_err("%s: update PTE failed\n", __func__);
2676 /* make sure this gets validated again */
2677 mutex_lock(&process_info->notifier_lock);
2678 mem->invalid++;
2679 mutex_unlock(&process_info->notifier_lock);
2680 goto unreserve_out;
2681 }
2682 }
2683 }
2684
2685 /* Update page directories */
2686 ret = process_update_pds(process_info, &sync);
2687
2688unreserve_out:
2689 drm_exec_fini(&exec);
2690 amdgpu_sync_wait(&sync, false);
2691 amdgpu_sync_free(&sync);
2692
2693 return ret;
2694}
2695
2696/* Confirm that all user pages are valid while holding the notifier lock
2697 *
2698 * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2699 */
2700static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2701{
2702 struct kgd_mem *mem, *tmp_mem;
2703 int ret = 0;
2704
2705 list_for_each_entry_safe(mem, tmp_mem,
2706 &process_info->userptr_inval_list,
2707 validate_list) {
2708 bool valid;
2709
2710 /* keep mem without hmm range at userptr_inval_list */
2711 if (!mem->range)
2712 continue;
2713
2714 /* Only check mem with hmm range associated */
2715 valid = amdgpu_ttm_tt_get_user_pages_done(
2716 mem->bo->tbo.ttm, mem->range);
2717
2718 mem->range = NULL;
2719 if (!valid) {
2720 WARN(!mem->invalid, "Invalid BO not marked invalid");
2721 ret = -EAGAIN;
2722 continue;
2723 }
2724
2725 if (mem->invalid) {
2726 WARN(1, "Valid BO is marked invalid");
2727 ret = -EAGAIN;
2728 continue;
2729 }
2730
2731 list_move_tail(&mem->validate_list,
2732 &process_info->userptr_valid_list);
2733 }
2734
2735 return ret;
2736}
2737
2738/* Worker callback to restore evicted userptr BOs
2739 *
2740 * Tries to update and validate all userptr BOs. If successful and no
2741 * concurrent evictions happened, the queues are restarted. Otherwise,
2742 * reschedule for another attempt later.
2743 */
2744static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2745{
2746 struct delayed_work *dwork = to_delayed_work(work);
2747 struct amdkfd_process_info *process_info =
2748 container_of(dwork, struct amdkfd_process_info,
2749 restore_userptr_work);
2750 struct task_struct *usertask;
2751 struct mm_struct *mm;
2752 uint32_t evicted_bos;
2753
2754 mutex_lock(&process_info->notifier_lock);
2755 evicted_bos = process_info->evicted_bos;
2756 mutex_unlock(&process_info->notifier_lock);
2757 if (!evicted_bos)
2758 return;
2759
2760 /* Reference task and mm in case of concurrent process termination */
2761 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2762 if (!usertask)
2763 return;
2764 mm = get_task_mm(usertask);
2765 if (!mm) {
2766 put_task_struct(usertask);
2767 return;
2768 }
2769
2770 mutex_lock(&process_info->lock);
2771
2772 if (update_invalid_user_pages(process_info, mm))
2773 goto unlock_out;
2774 /* userptr_inval_list can be empty if all evicted userptr BOs
2775 * have been freed. In that case there is nothing to validate
2776 * and we can just restart the queues.
2777 */
2778 if (!list_empty(&process_info->userptr_inval_list)) {
2779 if (validate_invalid_user_pages(process_info))
2780 goto unlock_out;
2781 }
2782 /* Final check for concurrent evicton and atomic update. If
2783 * another eviction happens after successful update, it will
2784 * be a first eviction that calls quiesce_mm. The eviction
2785 * reference counting inside KFD will handle this case.
2786 */
2787 mutex_lock(&process_info->notifier_lock);
2788 if (process_info->evicted_bos != evicted_bos)
2789 goto unlock_notifier_out;
2790
2791 if (confirm_valid_user_pages_locked(process_info)) {
2792 WARN(1, "User pages unexpectedly invalid");
2793 goto unlock_notifier_out;
2794 }
2795
2796 process_info->evicted_bos = evicted_bos = 0;
2797
2798 if (kgd2kfd_resume_mm(mm)) {
2799 pr_err("%s: Failed to resume KFD\n", __func__);
2800 /* No recovery from this failure. Probably the CP is
2801 * hanging. No point trying again.
2802 */
2803 }
2804
2805unlock_notifier_out:
2806 mutex_unlock(&process_info->notifier_lock);
2807unlock_out:
2808 mutex_unlock(&process_info->lock);
2809
2810 /* If validation failed, reschedule another attempt */
2811 if (evicted_bos) {
2812 queue_delayed_work(system_freezable_wq,
2813 &process_info->restore_userptr_work,
2814 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2815
2816 kfd_smi_event_queue_restore_rescheduled(mm);
2817 }
2818 mmput(mm);
2819 put_task_struct(usertask);
2820}
2821
2822static void replace_eviction_fence(struct dma_fence __rcu **ef,
2823 struct dma_fence *new_ef)
2824{
2825 struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true
2826 /* protected by process_info->lock */);
2827
2828 /* If we're replacing an unsignaled eviction fence, that fence will
2829 * never be signaled, and if anyone is still waiting on that fence,
2830 * they will hang forever. This should never happen. We should only
2831 * replace the fence in restore_work that only gets scheduled after
2832 * eviction work signaled the fence.
2833 */
2834 WARN_ONCE(!dma_fence_is_signaled(old_ef),
2835 "Replacing unsignaled eviction fence");
2836 dma_fence_put(old_ef);
2837}
2838
2839/** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2840 * KFD process identified by process_info
2841 *
2842 * @process_info: amdkfd_process_info of the KFD process
2843 *
2844 * After memory eviction, restore thread calls this function. The function
2845 * should be called when the Process is still valid. BO restore involves -
2846 *
2847 * 1. Release old eviction fence and create new one
2848 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2849 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2850 * BOs that need to be reserved.
2851 * 4. Reserve all the BOs
2852 * 5. Validate of PD and PT BOs.
2853 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2854 * 7. Add fence to all PD and PT BOs.
2855 * 8. Unreserve all BOs
2856 */
2857int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu **ef)
2858{
2859 struct amdkfd_process_info *process_info = info;
2860 struct amdgpu_vm *peer_vm;
2861 struct kgd_mem *mem;
2862 struct list_head duplicate_save;
2863 struct amdgpu_sync sync_obj;
2864 unsigned long failed_size = 0;
2865 unsigned long total_size = 0;
2866 struct drm_exec exec;
2867 int ret;
2868
2869 INIT_LIST_HEAD(&duplicate_save);
2870
2871 mutex_lock(&process_info->lock);
2872
2873 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
2874 drm_exec_until_all_locked(&exec) {
2875 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2876 vm_list_node) {
2877 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2878 drm_exec_retry_on_contention(&exec);
2879 if (unlikely(ret)) {
2880 pr_err("Locking VM PD failed, ret: %d\n", ret);
2881 goto ttm_reserve_fail;
2882 }
2883 }
2884
2885 /* Reserve all BOs and page tables/directory. Add all BOs from
2886 * kfd_bo_list to ctx.list
2887 */
2888 list_for_each_entry(mem, &process_info->kfd_bo_list,
2889 validate_list) {
2890 struct drm_gem_object *gobj;
2891
2892 gobj = &mem->bo->tbo.base;
2893 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2894 drm_exec_retry_on_contention(&exec);
2895 if (unlikely(ret)) {
2896 pr_err("drm_exec_prepare_obj failed, ret: %d\n", ret);
2897 goto ttm_reserve_fail;
2898 }
2899 }
2900 }
2901
2902 amdgpu_sync_create(&sync_obj);
2903
2904 /* Validate BOs managed by KFD */
2905 list_for_each_entry(mem, &process_info->kfd_bo_list,
2906 validate_list) {
2907
2908 struct amdgpu_bo *bo = mem->bo;
2909 uint32_t domain = mem->domain;
2910 struct dma_resv_iter cursor;
2911 struct dma_fence *fence;
2912
2913 total_size += amdgpu_bo_size(bo);
2914
2915 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2916 if (ret) {
2917 pr_debug("Memory eviction: Validate BOs failed\n");
2918 failed_size += amdgpu_bo_size(bo);
2919 ret = amdgpu_amdkfd_bo_validate(bo,
2920 AMDGPU_GEM_DOMAIN_GTT, false);
2921 if (ret) {
2922 pr_debug("Memory eviction: Try again\n");
2923 goto validate_map_fail;
2924 }
2925 }
2926 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2927 DMA_RESV_USAGE_KERNEL, fence) {
2928 ret = amdgpu_sync_fence(&sync_obj, fence);
2929 if (ret) {
2930 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2931 goto validate_map_fail;
2932 }
2933 }
2934 }
2935
2936 if (failed_size)
2937 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2938
2939 /* Validate PDs, PTs and evicted DMABuf imports last. Otherwise BO
2940 * validations above would invalidate DMABuf imports again.
2941 */
2942 ret = process_validate_vms(process_info, &exec.ticket);
2943 if (ret) {
2944 pr_debug("Validating VMs failed, ret: %d\n", ret);
2945 goto validate_map_fail;
2946 }
2947
2948 /* Update mappings managed by KFD. */
2949 list_for_each_entry(mem, &process_info->kfd_bo_list,
2950 validate_list) {
2951 struct kfd_mem_attachment *attachment;
2952
2953 list_for_each_entry(attachment, &mem->attachments, list) {
2954 if (!attachment->is_mapped)
2955 continue;
2956
2957 if (attachment->bo_va->base.bo->tbo.pin_count)
2958 continue;
2959
2960 kfd_mem_dmaunmap_attachment(mem, attachment);
2961 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2962 if (ret) {
2963 pr_debug("Memory eviction: update PTE failed. Try again\n");
2964 goto validate_map_fail;
2965 }
2966 }
2967 }
2968
2969 /* Update mappings not managed by KFD */
2970 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2971 vm_list_node) {
2972 struct amdgpu_device *adev = amdgpu_ttm_adev(
2973 peer_vm->root.bo->tbo.bdev);
2974
2975 ret = amdgpu_vm_handle_moved(adev, peer_vm, &exec.ticket);
2976 if (ret) {
2977 pr_debug("Memory eviction: handle moved failed. Try again\n");
2978 goto validate_map_fail;
2979 }
2980 }
2981
2982 /* Update page directories */
2983 ret = process_update_pds(process_info, &sync_obj);
2984 if (ret) {
2985 pr_debug("Memory eviction: update PDs failed. Try again\n");
2986 goto validate_map_fail;
2987 }
2988
2989 /* Sync with fences on all the page tables. They implicitly depend on any
2990 * move fences from amdgpu_vm_handle_moved above.
2991 */
2992 ret = process_sync_pds_resv(process_info, &sync_obj);
2993 if (ret) {
2994 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2995 goto validate_map_fail;
2996 }
2997
2998 /* Wait for validate and PT updates to finish */
2999 amdgpu_sync_wait(&sync_obj, false);
3000
3001 /* The old eviction fence may be unsignaled if restore happens
3002 * after a GPU reset or suspend/resume. Keep the old fence in that
3003 * case. Otherwise release the old eviction fence and create new
3004 * one, because fence only goes from unsignaled to signaled once
3005 * and cannot be reused. Use context and mm from the old fence.
3006 *
3007 * If an old eviction fence signals after this check, that's OK.
3008 * Anyone signaling an eviction fence must stop the queues first
3009 * and schedule another restore worker.
3010 */
3011 if (dma_fence_is_signaled(&process_info->eviction_fence->base)) {
3012 struct amdgpu_amdkfd_fence *new_fence =
3013 amdgpu_amdkfd_fence_create(
3014 process_info->eviction_fence->base.context,
3015 process_info->eviction_fence->mm,
3016 NULL);
3017
3018 if (!new_fence) {
3019 pr_err("Failed to create eviction fence\n");
3020 ret = -ENOMEM;
3021 goto validate_map_fail;
3022 }
3023 dma_fence_put(&process_info->eviction_fence->base);
3024 process_info->eviction_fence = new_fence;
3025 replace_eviction_fence(ef, dma_fence_get(&new_fence->base));
3026 } else {
3027 WARN_ONCE(*ef != &process_info->eviction_fence->base,
3028 "KFD eviction fence doesn't match KGD process_info");
3029 }
3030
3031 /* Attach new eviction fence to all BOs except pinned ones */
3032 list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
3033 if (mem->bo->tbo.pin_count)
3034 continue;
3035
3036 dma_resv_add_fence(mem->bo->tbo.base.resv,
3037 &process_info->eviction_fence->base,
3038 DMA_RESV_USAGE_BOOKKEEP);
3039 }
3040 /* Attach eviction fence to PD / PT BOs and DMABuf imports */
3041 list_for_each_entry(peer_vm, &process_info->vm_list_head,
3042 vm_list_node) {
3043 struct amdgpu_bo *bo = peer_vm->root.bo;
3044
3045 dma_resv_add_fence(bo->tbo.base.resv,
3046 &process_info->eviction_fence->base,
3047 DMA_RESV_USAGE_BOOKKEEP);
3048 }
3049
3050validate_map_fail:
3051 amdgpu_sync_free(&sync_obj);
3052ttm_reserve_fail:
3053 drm_exec_fini(&exec);
3054 mutex_unlock(&process_info->lock);
3055 return ret;
3056}
3057
3058int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
3059{
3060 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3061 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
3062 int ret;
3063
3064 if (!info || !gws)
3065 return -EINVAL;
3066
3067 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
3068 if (!*mem)
3069 return -ENOMEM;
3070
3071 mutex_init(&(*mem)->lock);
3072 INIT_LIST_HEAD(&(*mem)->attachments);
3073 (*mem)->bo = amdgpu_bo_ref(gws_bo);
3074 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
3075 (*mem)->process_info = process_info;
3076 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
3077 amdgpu_sync_create(&(*mem)->sync);
3078
3079
3080 /* Validate gws bo the first time it is added to process */
3081 mutex_lock(&(*mem)->process_info->lock);
3082 ret = amdgpu_bo_reserve(gws_bo, false);
3083 if (unlikely(ret)) {
3084 pr_err("Reserve gws bo failed %d\n", ret);
3085 goto bo_reservation_failure;
3086 }
3087
3088 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
3089 if (ret) {
3090 pr_err("GWS BO validate failed %d\n", ret);
3091 goto bo_validation_failure;
3092 }
3093 /* GWS resource is shared b/t amdgpu and amdkfd
3094 * Add process eviction fence to bo so they can
3095 * evict each other.
3096 */
3097 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
3098 if (ret)
3099 goto reserve_shared_fail;
3100 dma_resv_add_fence(gws_bo->tbo.base.resv,
3101 &process_info->eviction_fence->base,
3102 DMA_RESV_USAGE_BOOKKEEP);
3103 amdgpu_bo_unreserve(gws_bo);
3104 mutex_unlock(&(*mem)->process_info->lock);
3105
3106 return ret;
3107
3108reserve_shared_fail:
3109bo_validation_failure:
3110 amdgpu_bo_unreserve(gws_bo);
3111bo_reservation_failure:
3112 mutex_unlock(&(*mem)->process_info->lock);
3113 amdgpu_sync_free(&(*mem)->sync);
3114 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
3115 amdgpu_bo_unref(&gws_bo);
3116 mutex_destroy(&(*mem)->lock);
3117 kfree(*mem);
3118 *mem = NULL;
3119 return ret;
3120}
3121
3122int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
3123{
3124 int ret;
3125 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3126 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
3127 struct amdgpu_bo *gws_bo = kgd_mem->bo;
3128
3129 /* Remove BO from process's validate list so restore worker won't touch
3130 * it anymore
3131 */
3132 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
3133
3134 ret = amdgpu_bo_reserve(gws_bo, false);
3135 if (unlikely(ret)) {
3136 pr_err("Reserve gws bo failed %d\n", ret);
3137 //TODO add BO back to validate_list?
3138 return ret;
3139 }
3140 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
3141 process_info->eviction_fence);
3142 amdgpu_bo_unreserve(gws_bo);
3143 amdgpu_sync_free(&kgd_mem->sync);
3144 amdgpu_bo_unref(&gws_bo);
3145 mutex_destroy(&kgd_mem->lock);
3146 kfree(mem);
3147 return 0;
3148}
3149
3150/* Returns GPU-specific tiling mode information */
3151int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
3152 struct tile_config *config)
3153{
3154 config->gb_addr_config = adev->gfx.config.gb_addr_config;
3155 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
3156 config->num_tile_configs =
3157 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
3158 config->macro_tile_config_ptr =
3159 adev->gfx.config.macrotile_mode_array;
3160 config->num_macro_tile_configs =
3161 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
3162
3163 /* Those values are not set from GFX9 onwards */
3164 config->num_banks = adev->gfx.config.num_banks;
3165 config->num_ranks = adev->gfx.config.num_ranks;
3166
3167 return 0;
3168}
3169
3170bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
3171{
3172 struct kfd_mem_attachment *entry;
3173
3174 list_for_each_entry(entry, &mem->attachments, list) {
3175 if (entry->is_mapped && entry->adev == adev)
3176 return true;
3177 }
3178 return false;
3179}
3180
3181#if defined(CONFIG_DEBUG_FS)
3182
3183int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3184{
3185
3186 spin_lock(&kfd_mem_limit.mem_limit_lock);
3187 seq_printf(m, "System mem used %lldM out of %lluM\n",
3188 (kfd_mem_limit.system_mem_used >> 20),
3189 (kfd_mem_limit.max_system_mem_limit >> 20));
3190 seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3191 (kfd_mem_limit.ttm_mem_used >> 20),
3192 (kfd_mem_limit.max_ttm_mem_limit >> 20));
3193 spin_unlock(&kfd_mem_limit.mem_limit_lock);
3194
3195 return 0;
3196}
3197
3198#endif
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include <linux/dma-buf.h>
24#include <linux/list.h>
25#include <linux/pagemap.h>
26#include <linux/sched/mm.h>
27#include <linux/sched/task.h>
28#include <drm/ttm/ttm_tt.h>
29
30#include <drm/drm_exec.h>
31
32#include "amdgpu_object.h"
33#include "amdgpu_gem.h"
34#include "amdgpu_vm.h"
35#include "amdgpu_hmm.h"
36#include "amdgpu_amdkfd.h"
37#include "amdgpu_dma_buf.h"
38#include <uapi/linux/kfd_ioctl.h>
39#include "amdgpu_xgmi.h"
40#include "kfd_priv.h"
41#include "kfd_smi_events.h"
42
43/* Userptr restore delay, just long enough to allow consecutive VM
44 * changes to accumulate
45 */
46#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
47#define AMDGPU_RESERVE_MEM_LIMIT (3UL << 29)
48
49/*
50 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
51 * BO chunk
52 */
53#define VRAM_AVAILABLITY_ALIGN (1 << 21)
54
55/* Impose limit on how much memory KFD can use */
56static struct {
57 uint64_t max_system_mem_limit;
58 uint64_t max_ttm_mem_limit;
59 int64_t system_mem_used;
60 int64_t ttm_mem_used;
61 spinlock_t mem_limit_lock;
62} kfd_mem_limit;
63
64static const char * const domain_bit_to_string[] = {
65 "CPU",
66 "GTT",
67 "VRAM",
68 "GDS",
69 "GWS",
70 "OA"
71};
72
73#define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
74
75static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
76
77static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
78 struct kgd_mem *mem)
79{
80 struct kfd_mem_attachment *entry;
81
82 list_for_each_entry(entry, &mem->attachments, list)
83 if (entry->bo_va->base.vm == avm)
84 return true;
85
86 return false;
87}
88
89/**
90 * reuse_dmamap() - Check whether adev can share the original
91 * userptr BO
92 *
93 * If both adev and bo_adev are in direct mapping or
94 * in the same iommu group, they can share the original BO.
95 *
96 * @adev: Device to which can or cannot share the original BO
97 * @bo_adev: Device to which allocated BO belongs to
98 *
99 * Return: returns true if adev can share original userptr BO,
100 * false otherwise.
101 */
102static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
103{
104 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
105 (adev->dev->iommu_group == bo_adev->dev->iommu_group);
106}
107
108/* Set memory usage limits. Current, limits are
109 * System (TTM + userptr) memory - 15/16th System RAM
110 * TTM memory - 3/8th System RAM
111 */
112void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
113{
114 struct sysinfo si;
115 uint64_t mem;
116
117 if (kfd_mem_limit.max_system_mem_limit)
118 return;
119
120 si_meminfo(&si);
121 mem = si.totalram - si.totalhigh;
122 mem *= si.mem_unit;
123
124 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
125 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6);
126 if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT)
127 kfd_mem_limit.max_system_mem_limit >>= 1;
128 else
129 kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT;
130
131 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
132 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
133 (kfd_mem_limit.max_system_mem_limit >> 20),
134 (kfd_mem_limit.max_ttm_mem_limit >> 20));
135}
136
137void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
138{
139 kfd_mem_limit.system_mem_used += size;
140}
141
142/* Estimate page table size needed to represent a given memory size
143 *
144 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
145 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
146 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
147 * for 2MB pages for TLB efficiency. However, small allocations and
148 * fragmented system memory still need some 4KB pages. We choose a
149 * compromise that should work in most cases without reserving too
150 * much memory for page tables unnecessarily (factor 16K, >> 14).
151 */
152
153#define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
154
155/**
156 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
157 * of buffer.
158 *
159 * @adev: Device to which allocated BO belongs to
160 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
161 * equivalent to amdgpu_bo_size(BO)
162 * @alloc_flag: Flag used in allocating a BO as noted above
163 * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
164 * managed as one compute node in driver for app
165 *
166 * Return:
167 * returns -ENOMEM in case of error, ZERO otherwise
168 */
169int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
170 uint64_t size, u32 alloc_flag, int8_t xcp_id)
171{
172 uint64_t reserved_for_pt =
173 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
174 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
175 uint64_t reserved_for_ras = (con ? con->reserved_pages_in_bytes : 0);
176 size_t system_mem_needed, ttm_mem_needed, vram_needed;
177 int ret = 0;
178 uint64_t vram_size = 0;
179
180 system_mem_needed = 0;
181 ttm_mem_needed = 0;
182 vram_needed = 0;
183 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
184 system_mem_needed = size;
185 ttm_mem_needed = size;
186 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
187 /*
188 * Conservatively round up the allocation requirement to 2 MB
189 * to avoid fragmentation caused by 4K allocations in the tail
190 * 2M BO chunk.
191 */
192 vram_needed = size;
193 /*
194 * For GFX 9.4.3, get the VRAM size from XCP structs
195 */
196 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
197 return -EINVAL;
198
199 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
200 if (adev->flags & AMD_IS_APU) {
201 system_mem_needed = size;
202 ttm_mem_needed = size;
203 }
204 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
205 system_mem_needed = size;
206 } else if (!(alloc_flag &
207 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
208 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
209 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
210 return -ENOMEM;
211 }
212
213 spin_lock(&kfd_mem_limit.mem_limit_lock);
214
215 if (kfd_mem_limit.system_mem_used + system_mem_needed >
216 kfd_mem_limit.max_system_mem_limit)
217 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
218
219 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
220 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
221 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
222 kfd_mem_limit.max_ttm_mem_limit) ||
223 (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
224 vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size))) {
225 ret = -ENOMEM;
226 goto release;
227 }
228
229 /* Update memory accounting by decreasing available system
230 * memory, TTM memory and GPU memory as computed above
231 */
232 WARN_ONCE(vram_needed && !adev,
233 "adev reference can't be null when vram is used");
234 if (adev && xcp_id >= 0) {
235 adev->kfd.vram_used[xcp_id] += vram_needed;
236 adev->kfd.vram_used_aligned[xcp_id] +=
237 (adev->flags & AMD_IS_APU) ?
238 vram_needed :
239 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
240 }
241 kfd_mem_limit.system_mem_used += system_mem_needed;
242 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
243
244release:
245 spin_unlock(&kfd_mem_limit.mem_limit_lock);
246 return ret;
247}
248
249void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
250 uint64_t size, u32 alloc_flag, int8_t xcp_id)
251{
252 spin_lock(&kfd_mem_limit.mem_limit_lock);
253
254 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
255 kfd_mem_limit.system_mem_used -= size;
256 kfd_mem_limit.ttm_mem_used -= size;
257 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
258 WARN_ONCE(!adev,
259 "adev reference can't be null when alloc mem flags vram is set");
260 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
261 goto release;
262
263 if (adev) {
264 adev->kfd.vram_used[xcp_id] -= size;
265 if (adev->flags & AMD_IS_APU) {
266 adev->kfd.vram_used_aligned[xcp_id] -= size;
267 kfd_mem_limit.system_mem_used -= size;
268 kfd_mem_limit.ttm_mem_used -= size;
269 } else {
270 adev->kfd.vram_used_aligned[xcp_id] -=
271 ALIGN(size, VRAM_AVAILABLITY_ALIGN);
272 }
273 }
274 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
275 kfd_mem_limit.system_mem_used -= size;
276 } else if (!(alloc_flag &
277 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
278 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
279 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
280 goto release;
281 }
282 WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
283 "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
284 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
285 "KFD TTM memory accounting unbalanced");
286 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
287 "KFD system memory accounting unbalanced");
288
289release:
290 spin_unlock(&kfd_mem_limit.mem_limit_lock);
291}
292
293void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
294{
295 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
296 u32 alloc_flags = bo->kfd_bo->alloc_flags;
297 u64 size = amdgpu_bo_size(bo);
298
299 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
300 bo->xcp_id);
301
302 kfree(bo->kfd_bo);
303}
304
305/**
306 * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
307 * about USERPTR or DOOREBELL or MMIO BO.
308 *
309 * @adev: Device for which dmamap BO is being created
310 * @mem: BO of peer device that is being DMA mapped. Provides parameters
311 * in building the dmamap BO
312 * @bo_out: Output parameter updated with handle of dmamap BO
313 */
314static int
315create_dmamap_sg_bo(struct amdgpu_device *adev,
316 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
317{
318 struct drm_gem_object *gem_obj;
319 int ret;
320 uint64_t flags = 0;
321
322 ret = amdgpu_bo_reserve(mem->bo, false);
323 if (ret)
324 return ret;
325
326 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
327 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
328 AMDGPU_GEM_CREATE_UNCACHED);
329
330 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
331 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
332 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
333
334 amdgpu_bo_unreserve(mem->bo);
335
336 if (ret) {
337 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
338 return -EINVAL;
339 }
340
341 *bo_out = gem_to_amdgpu_bo(gem_obj);
342 (*bo_out)->parent = amdgpu_bo_ref(mem->bo);
343 return ret;
344}
345
346/* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
347 * reservation object.
348 *
349 * @bo: [IN] Remove eviction fence(s) from this BO
350 * @ef: [IN] This eviction fence is removed if it
351 * is present in the shared list.
352 *
353 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
354 */
355static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
356 struct amdgpu_amdkfd_fence *ef)
357{
358 struct dma_fence *replacement;
359
360 if (!ef)
361 return -EINVAL;
362
363 /* TODO: Instead of block before we should use the fence of the page
364 * table update and TLB flush here directly.
365 */
366 replacement = dma_fence_get_stub();
367 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
368 replacement, DMA_RESV_USAGE_BOOKKEEP);
369 dma_fence_put(replacement);
370 return 0;
371}
372
373int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
374{
375 struct amdgpu_bo *root = bo;
376 struct amdgpu_vm_bo_base *vm_bo;
377 struct amdgpu_vm *vm;
378 struct amdkfd_process_info *info;
379 struct amdgpu_amdkfd_fence *ef;
380 int ret;
381
382 /* we can always get vm_bo from root PD bo.*/
383 while (root->parent)
384 root = root->parent;
385
386 vm_bo = root->vm_bo;
387 if (!vm_bo)
388 return 0;
389
390 vm = vm_bo->vm;
391 if (!vm)
392 return 0;
393
394 info = vm->process_info;
395 if (!info || !info->eviction_fence)
396 return 0;
397
398 ef = container_of(dma_fence_get(&info->eviction_fence->base),
399 struct amdgpu_amdkfd_fence, base);
400
401 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
402 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
403 dma_resv_unlock(bo->tbo.base.resv);
404
405 dma_fence_put(&ef->base);
406 return ret;
407}
408
409static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
410 bool wait)
411{
412 struct ttm_operation_ctx ctx = { false, false };
413 int ret;
414
415 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
416 "Called with userptr BO"))
417 return -EINVAL;
418
419 /* bo has been pinned, not need validate it */
420 if (bo->tbo.pin_count)
421 return 0;
422
423 amdgpu_bo_placement_from_domain(bo, domain);
424
425 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
426 if (ret)
427 goto validate_fail;
428 if (wait)
429 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
430
431validate_fail:
432 return ret;
433}
434
435int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
436 uint32_t domain,
437 struct dma_fence *fence)
438{
439 int ret = amdgpu_bo_reserve(bo, false);
440
441 if (ret)
442 return ret;
443
444 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
445 if (ret)
446 goto unreserve_out;
447
448 ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
449 if (ret)
450 goto unreserve_out;
451
452 dma_resv_add_fence(bo->tbo.base.resv, fence,
453 DMA_RESV_USAGE_BOOKKEEP);
454
455unreserve_out:
456 amdgpu_bo_unreserve(bo);
457
458 return ret;
459}
460
461static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
462{
463 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
464}
465
466/* vm_validate_pt_pd_bos - Validate page table and directory BOs
467 *
468 * Page directories are not updated here because huge page handling
469 * during page table updates can invalidate page directory entries
470 * again. Page directories are only updated after updating page
471 * tables.
472 */
473static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm,
474 struct ww_acquire_ctx *ticket)
475{
476 struct amdgpu_bo *pd = vm->root.bo;
477 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
478 int ret;
479
480 ret = amdgpu_vm_validate(adev, vm, ticket,
481 amdgpu_amdkfd_validate_vm_bo, NULL);
482 if (ret) {
483 pr_err("failed to validate PT BOs\n");
484 return ret;
485 }
486
487 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
488
489 return 0;
490}
491
492static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
493{
494 struct amdgpu_bo *pd = vm->root.bo;
495 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
496 int ret;
497
498 ret = amdgpu_vm_update_pdes(adev, vm, false);
499 if (ret)
500 return ret;
501
502 return amdgpu_sync_fence(sync, vm->last_update);
503}
504
505static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
506{
507 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
508 AMDGPU_VM_MTYPE_DEFAULT;
509
510 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
511 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
512 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
513 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
514
515 return amdgpu_gem_va_map_flags(adev, mapping_flags);
516}
517
518/**
519 * create_sg_table() - Create an sg_table for a contiguous DMA addr range
520 * @addr: The starting address to point to
521 * @size: Size of memory area in bytes being pointed to
522 *
523 * Allocates an instance of sg_table and initializes it to point to memory
524 * area specified by input parameters. The address used to build is assumed
525 * to be DMA mapped, if needed.
526 *
527 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
528 * because they are physically contiguous.
529 *
530 * Return: Initialized instance of SG Table or NULL
531 */
532static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
533{
534 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
535
536 if (!sg)
537 return NULL;
538 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
539 kfree(sg);
540 return NULL;
541 }
542 sg_dma_address(sg->sgl) = addr;
543 sg->sgl->length = size;
544#ifdef CONFIG_NEED_SG_DMA_LENGTH
545 sg->sgl->dma_length = size;
546#endif
547 return sg;
548}
549
550static int
551kfd_mem_dmamap_userptr(struct kgd_mem *mem,
552 struct kfd_mem_attachment *attachment)
553{
554 enum dma_data_direction direction =
555 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
556 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
557 struct ttm_operation_ctx ctx = {.interruptible = true};
558 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
559 struct amdgpu_device *adev = attachment->adev;
560 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
561 struct ttm_tt *ttm = bo->tbo.ttm;
562 int ret;
563
564 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
565 return -EINVAL;
566
567 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
568 if (unlikely(!ttm->sg))
569 return -ENOMEM;
570
571 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
572 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
573 ttm->num_pages, 0,
574 (u64)ttm->num_pages << PAGE_SHIFT,
575 GFP_KERNEL);
576 if (unlikely(ret))
577 goto free_sg;
578
579 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
580 if (unlikely(ret))
581 goto release_sg;
582
583 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
584 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
585 if (ret)
586 goto unmap_sg;
587
588 return 0;
589
590unmap_sg:
591 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
592release_sg:
593 pr_err("DMA map userptr failed: %d\n", ret);
594 sg_free_table(ttm->sg);
595free_sg:
596 kfree(ttm->sg);
597 ttm->sg = NULL;
598 return ret;
599}
600
601static int
602kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
603{
604 struct ttm_operation_ctx ctx = {.interruptible = true};
605 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
606 int ret;
607
608 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
609 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
610 if (ret)
611 return ret;
612
613 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
614 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
615}
616
617/**
618 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
619 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
620 * @attachment: Virtual address attachment of the BO on accessing device
621 *
622 * An access request from the device that owns DOORBELL does not require DMA mapping.
623 * This is because the request doesn't go through PCIe root complex i.e. it instead
624 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
625 *
626 * In contrast, all access requests for MMIO need to be DMA mapped without regard to
627 * device ownership. This is because access requests for MMIO go through PCIe root
628 * complex.
629 *
630 * This is accomplished in two steps:
631 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
632 * in updating requesting device's page table
633 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU
634 * accessible. This allows an update of requesting device's page table
635 * with entries associated with DOOREBELL or MMIO memory
636 *
637 * This method is invoked in the following contexts:
638 * - Mapping of DOORBELL or MMIO BO of same or peer device
639 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access
640 *
641 * Return: ZERO if successful, NON-ZERO otherwise
642 */
643static int
644kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
645 struct kfd_mem_attachment *attachment)
646{
647 struct ttm_operation_ctx ctx = {.interruptible = true};
648 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
649 struct amdgpu_device *adev = attachment->adev;
650 struct ttm_tt *ttm = bo->tbo.ttm;
651 enum dma_data_direction dir;
652 dma_addr_t dma_addr;
653 bool mmio;
654 int ret;
655
656 /* Expect SG Table of dmapmap BO to be NULL */
657 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
658 if (unlikely(ttm->sg)) {
659 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
660 return -EINVAL;
661 }
662
663 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
664 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
665 dma_addr = mem->bo->tbo.sg->sgl->dma_address;
666 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
667 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
668 dma_addr = dma_map_resource(adev->dev, dma_addr,
669 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
670 ret = dma_mapping_error(adev->dev, dma_addr);
671 if (unlikely(ret))
672 return ret;
673 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
674
675 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
676 if (unlikely(!ttm->sg)) {
677 ret = -ENOMEM;
678 goto unmap_sg;
679 }
680
681 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
682 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
683 if (unlikely(ret))
684 goto free_sg;
685
686 return ret;
687
688free_sg:
689 sg_free_table(ttm->sg);
690 kfree(ttm->sg);
691 ttm->sg = NULL;
692unmap_sg:
693 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
694 dir, DMA_ATTR_SKIP_CPU_SYNC);
695 return ret;
696}
697
698static int
699kfd_mem_dmamap_attachment(struct kgd_mem *mem,
700 struct kfd_mem_attachment *attachment)
701{
702 switch (attachment->type) {
703 case KFD_MEM_ATT_SHARED:
704 return 0;
705 case KFD_MEM_ATT_USERPTR:
706 return kfd_mem_dmamap_userptr(mem, attachment);
707 case KFD_MEM_ATT_DMABUF:
708 return kfd_mem_dmamap_dmabuf(attachment);
709 case KFD_MEM_ATT_SG:
710 return kfd_mem_dmamap_sg_bo(mem, attachment);
711 default:
712 WARN_ON_ONCE(1);
713 }
714 return -EINVAL;
715}
716
717static void
718kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
719 struct kfd_mem_attachment *attachment)
720{
721 enum dma_data_direction direction =
722 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
723 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
724 struct ttm_operation_ctx ctx = {.interruptible = false};
725 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
726 struct amdgpu_device *adev = attachment->adev;
727 struct ttm_tt *ttm = bo->tbo.ttm;
728
729 if (unlikely(!ttm->sg))
730 return;
731
732 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
733 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
734
735 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
736 sg_free_table(ttm->sg);
737 kfree(ttm->sg);
738 ttm->sg = NULL;
739}
740
741static void
742kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
743{
744 /* This is a no-op. We don't want to trigger eviction fences when
745 * unmapping DMABufs. Therefore the invalidation (moving to system
746 * domain) is done in kfd_mem_dmamap_dmabuf.
747 */
748}
749
750/**
751 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
752 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
753 * @attachment: Virtual address attachment of the BO on accessing device
754 *
755 * The method performs following steps:
756 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible
757 * - Free SG Table that is used to encapsulate DMA mapped memory of
758 * peer device's DOORBELL or MMIO memory
759 *
760 * This method is invoked in the following contexts:
761 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory
762 * Eviction of DOOREBELL or MMIO BO on device having access to its memory
763 *
764 * Return: void
765 */
766static void
767kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
768 struct kfd_mem_attachment *attachment)
769{
770 struct ttm_operation_ctx ctx = {.interruptible = true};
771 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
772 struct amdgpu_device *adev = attachment->adev;
773 struct ttm_tt *ttm = bo->tbo.ttm;
774 enum dma_data_direction dir;
775
776 if (unlikely(!ttm->sg)) {
777 pr_debug("SG Table of BO is NULL");
778 return;
779 }
780
781 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
782 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
783
784 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
785 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
786 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
787 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
788 sg_free_table(ttm->sg);
789 kfree(ttm->sg);
790 ttm->sg = NULL;
791 bo->tbo.sg = NULL;
792}
793
794static void
795kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
796 struct kfd_mem_attachment *attachment)
797{
798 switch (attachment->type) {
799 case KFD_MEM_ATT_SHARED:
800 break;
801 case KFD_MEM_ATT_USERPTR:
802 kfd_mem_dmaunmap_userptr(mem, attachment);
803 break;
804 case KFD_MEM_ATT_DMABUF:
805 kfd_mem_dmaunmap_dmabuf(attachment);
806 break;
807 case KFD_MEM_ATT_SG:
808 kfd_mem_dmaunmap_sg_bo(mem, attachment);
809 break;
810 default:
811 WARN_ON_ONCE(1);
812 }
813}
814
815static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
816{
817 if (!mem->dmabuf) {
818 struct amdgpu_device *bo_adev;
819 struct dma_buf *dmabuf;
820
821 bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
822 dmabuf = drm_gem_prime_handle_to_dmabuf(&bo_adev->ddev, bo_adev->kfd.client.file,
823 mem->gem_handle,
824 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
825 DRM_RDWR : 0);
826 if (IS_ERR(dmabuf))
827 return PTR_ERR(dmabuf);
828 mem->dmabuf = dmabuf;
829 }
830
831 return 0;
832}
833
834static int
835kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
836 struct amdgpu_bo **bo)
837{
838 struct drm_gem_object *gobj;
839 int ret;
840
841 ret = kfd_mem_export_dmabuf(mem);
842 if (ret)
843 return ret;
844
845 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
846 if (IS_ERR(gobj))
847 return PTR_ERR(gobj);
848
849 *bo = gem_to_amdgpu_bo(gobj);
850 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
851
852 return 0;
853}
854
855/* kfd_mem_attach - Add a BO to a VM
856 *
857 * Everything that needs to bo done only once when a BO is first added
858 * to a VM. It can later be mapped and unmapped many times without
859 * repeating these steps.
860 *
861 * 0. Create BO for DMA mapping, if needed
862 * 1. Allocate and initialize BO VA entry data structure
863 * 2. Add BO to the VM
864 * 3. Determine ASIC-specific PTE flags
865 * 4. Alloc page tables and directories if needed
866 * 4a. Validate new page tables and directories
867 */
868static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
869 struct amdgpu_vm *vm, bool is_aql)
870{
871 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
872 unsigned long bo_size = mem->bo->tbo.base.size;
873 uint64_t va = mem->va;
874 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
875 struct amdgpu_bo *bo[2] = {NULL, NULL};
876 struct amdgpu_bo_va *bo_va;
877 bool same_hive = false;
878 int i, ret;
879
880 if (!va) {
881 pr_err("Invalid VA when adding BO to VM\n");
882 return -EINVAL;
883 }
884
885 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
886 *
887 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
888 * In contrast the access path of VRAM BOs depens upon the type of
889 * link that connects the peer device. Access over PCIe is allowed
890 * if peer device has large BAR. In contrast, access over xGMI is
891 * allowed for both small and large BAR configurations of peer device
892 */
893 if ((adev != bo_adev && !(adev->flags & AMD_IS_APU)) &&
894 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
895 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
896 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
897 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
898 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
899 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
900 return -EINVAL;
901 }
902
903 for (i = 0; i <= is_aql; i++) {
904 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
905 if (unlikely(!attachment[i])) {
906 ret = -ENOMEM;
907 goto unwind;
908 }
909
910 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
911 va + bo_size, vm);
912
913 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
914 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
915 (mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) ||
916 same_hive) {
917 /* Mappings on the local GPU, or VRAM mappings in the
918 * local hive, or userptr, or GTT mapping can reuse dma map
919 * address space share the original BO
920 */
921 attachment[i]->type = KFD_MEM_ATT_SHARED;
922 bo[i] = mem->bo;
923 drm_gem_object_get(&bo[i]->tbo.base);
924 } else if (i > 0) {
925 /* Multiple mappings on the same GPU share the BO */
926 attachment[i]->type = KFD_MEM_ATT_SHARED;
927 bo[i] = bo[0];
928 drm_gem_object_get(&bo[i]->tbo.base);
929 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
930 /* Create an SG BO to DMA-map userptrs on other GPUs */
931 attachment[i]->type = KFD_MEM_ATT_USERPTR;
932 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
933 if (ret)
934 goto unwind;
935 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
936 } else if (mem->bo->tbo.type == ttm_bo_type_sg) {
937 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
938 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
939 "Handing invalid SG BO in ATTACH request");
940 attachment[i]->type = KFD_MEM_ATT_SG;
941 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
942 if (ret)
943 goto unwind;
944 /* Enable acces to GTT and VRAM BOs of peer devices */
945 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
946 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
947 attachment[i]->type = KFD_MEM_ATT_DMABUF;
948 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
949 if (ret)
950 goto unwind;
951 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
952 } else {
953 WARN_ONCE(true, "Handling invalid ATTACH request");
954 ret = -EINVAL;
955 goto unwind;
956 }
957
958 /* Add BO to VM internal data structures */
959 ret = amdgpu_bo_reserve(bo[i], false);
960 if (ret) {
961 pr_debug("Unable to reserve BO during memory attach");
962 goto unwind;
963 }
964 bo_va = amdgpu_vm_bo_find(vm, bo[i]);
965 if (!bo_va)
966 bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
967 else
968 ++bo_va->ref_count;
969 attachment[i]->bo_va = bo_va;
970 amdgpu_bo_unreserve(bo[i]);
971 if (unlikely(!attachment[i]->bo_va)) {
972 ret = -ENOMEM;
973 pr_err("Failed to add BO object to VM. ret == %d\n",
974 ret);
975 goto unwind;
976 }
977 attachment[i]->va = va;
978 attachment[i]->pte_flags = get_pte_flags(adev, mem);
979 attachment[i]->adev = adev;
980 list_add(&attachment[i]->list, &mem->attachments);
981
982 va += bo_size;
983 }
984
985 return 0;
986
987unwind:
988 for (; i >= 0; i--) {
989 if (!attachment[i])
990 continue;
991 if (attachment[i]->bo_va) {
992 amdgpu_bo_reserve(bo[i], true);
993 if (--attachment[i]->bo_va->ref_count == 0)
994 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
995 amdgpu_bo_unreserve(bo[i]);
996 list_del(&attachment[i]->list);
997 }
998 if (bo[i])
999 drm_gem_object_put(&bo[i]->tbo.base);
1000 kfree(attachment[i]);
1001 }
1002 return ret;
1003}
1004
1005static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
1006{
1007 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
1008
1009 pr_debug("\t remove VA 0x%llx in entry %p\n",
1010 attachment->va, attachment);
1011 if (--attachment->bo_va->ref_count == 0)
1012 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
1013 drm_gem_object_put(&bo->tbo.base);
1014 list_del(&attachment->list);
1015 kfree(attachment);
1016}
1017
1018static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
1019 struct amdkfd_process_info *process_info,
1020 bool userptr)
1021{
1022 mutex_lock(&process_info->lock);
1023 if (userptr)
1024 list_add_tail(&mem->validate_list,
1025 &process_info->userptr_valid_list);
1026 else
1027 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
1028 mutex_unlock(&process_info->lock);
1029}
1030
1031static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
1032 struct amdkfd_process_info *process_info)
1033{
1034 mutex_lock(&process_info->lock);
1035 list_del(&mem->validate_list);
1036 mutex_unlock(&process_info->lock);
1037}
1038
1039/* Initializes user pages. It registers the MMU notifier and validates
1040 * the userptr BO in the GTT domain.
1041 *
1042 * The BO must already be on the userptr_valid_list. Otherwise an
1043 * eviction and restore may happen that leaves the new BO unmapped
1044 * with the user mode queues running.
1045 *
1046 * Takes the process_info->lock to protect against concurrent restore
1047 * workers.
1048 *
1049 * Returns 0 for success, negative errno for errors.
1050 */
1051static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1052 bool criu_resume)
1053{
1054 struct amdkfd_process_info *process_info = mem->process_info;
1055 struct amdgpu_bo *bo = mem->bo;
1056 struct ttm_operation_ctx ctx = { true, false };
1057 struct hmm_range *range;
1058 int ret = 0;
1059
1060 mutex_lock(&process_info->lock);
1061
1062 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1063 if (ret) {
1064 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1065 goto out;
1066 }
1067
1068 ret = amdgpu_hmm_register(bo, user_addr);
1069 if (ret) {
1070 pr_err("%s: Failed to register MMU notifier: %d\n",
1071 __func__, ret);
1072 goto out;
1073 }
1074
1075 if (criu_resume) {
1076 /*
1077 * During a CRIU restore operation, the userptr buffer objects
1078 * will be validated in the restore_userptr_work worker at a
1079 * later stage when it is scheduled by another ioctl called by
1080 * CRIU master process for the target pid for restore.
1081 */
1082 mutex_lock(&process_info->notifier_lock);
1083 mem->invalid++;
1084 mutex_unlock(&process_info->notifier_lock);
1085 mutex_unlock(&process_info->lock);
1086 return 0;
1087 }
1088
1089 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1090 if (ret) {
1091 if (ret == -EAGAIN)
1092 pr_debug("Failed to get user pages, try again\n");
1093 else
1094 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1095 goto unregister_out;
1096 }
1097
1098 ret = amdgpu_bo_reserve(bo, true);
1099 if (ret) {
1100 pr_err("%s: Failed to reserve BO\n", __func__);
1101 goto release_out;
1102 }
1103 amdgpu_bo_placement_from_domain(bo, mem->domain);
1104 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1105 if (ret)
1106 pr_err("%s: failed to validate BO\n", __func__);
1107 amdgpu_bo_unreserve(bo);
1108
1109release_out:
1110 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1111unregister_out:
1112 if (ret)
1113 amdgpu_hmm_unregister(bo);
1114out:
1115 mutex_unlock(&process_info->lock);
1116 return ret;
1117}
1118
1119/* Reserving a BO and its page table BOs must happen atomically to
1120 * avoid deadlocks. Some operations update multiple VMs at once. Track
1121 * all the reservation info in a context structure. Optionally a sync
1122 * object can track VM updates.
1123 */
1124struct bo_vm_reservation_context {
1125 /* DRM execution context for the reservation */
1126 struct drm_exec exec;
1127 /* Number of VMs reserved */
1128 unsigned int n_vms;
1129 /* Pointer to sync object */
1130 struct amdgpu_sync *sync;
1131};
1132
1133enum bo_vm_match {
1134 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
1135 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
1136 BO_VM_ALL, /* Match all VMs a BO was added to */
1137};
1138
1139/**
1140 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1141 * @mem: KFD BO structure.
1142 * @vm: the VM to reserve.
1143 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1144 */
1145static int reserve_bo_and_vm(struct kgd_mem *mem,
1146 struct amdgpu_vm *vm,
1147 struct bo_vm_reservation_context *ctx)
1148{
1149 struct amdgpu_bo *bo = mem->bo;
1150 int ret;
1151
1152 WARN_ON(!vm);
1153
1154 ctx->n_vms = 1;
1155 ctx->sync = &mem->sync;
1156 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1157 drm_exec_until_all_locked(&ctx->exec) {
1158 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1159 drm_exec_retry_on_contention(&ctx->exec);
1160 if (unlikely(ret))
1161 goto error;
1162
1163 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1164 drm_exec_retry_on_contention(&ctx->exec);
1165 if (unlikely(ret))
1166 goto error;
1167 }
1168 return 0;
1169
1170error:
1171 pr_err("Failed to reserve buffers in ttm.\n");
1172 drm_exec_fini(&ctx->exec);
1173 return ret;
1174}
1175
1176/**
1177 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1178 * @mem: KFD BO structure.
1179 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1180 * is used. Otherwise, a single VM associated with the BO.
1181 * @map_type: the mapping status that will be used to filter the VMs.
1182 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1183 *
1184 * Returns 0 for success, negative for failure.
1185 */
1186static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1187 struct amdgpu_vm *vm, enum bo_vm_match map_type,
1188 struct bo_vm_reservation_context *ctx)
1189{
1190 struct kfd_mem_attachment *entry;
1191 struct amdgpu_bo *bo = mem->bo;
1192 int ret;
1193
1194 ctx->sync = &mem->sync;
1195 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
1196 DRM_EXEC_IGNORE_DUPLICATES, 0);
1197 drm_exec_until_all_locked(&ctx->exec) {
1198 ctx->n_vms = 0;
1199 list_for_each_entry(entry, &mem->attachments, list) {
1200 if ((vm && vm != entry->bo_va->base.vm) ||
1201 (entry->is_mapped != map_type
1202 && map_type != BO_VM_ALL))
1203 continue;
1204
1205 ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1206 &ctx->exec, 2);
1207 drm_exec_retry_on_contention(&ctx->exec);
1208 if (unlikely(ret))
1209 goto error;
1210 ++ctx->n_vms;
1211 }
1212
1213 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1214 drm_exec_retry_on_contention(&ctx->exec);
1215 if (unlikely(ret))
1216 goto error;
1217 }
1218 return 0;
1219
1220error:
1221 pr_err("Failed to reserve buffers in ttm.\n");
1222 drm_exec_fini(&ctx->exec);
1223 return ret;
1224}
1225
1226/**
1227 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1228 * @ctx: Reservation context to unreserve
1229 * @wait: Optionally wait for a sync object representing pending VM updates
1230 * @intr: Whether the wait is interruptible
1231 *
1232 * Also frees any resources allocated in
1233 * reserve_bo_and_(cond_)vm(s). Returns the status from
1234 * amdgpu_sync_wait.
1235 */
1236static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1237 bool wait, bool intr)
1238{
1239 int ret = 0;
1240
1241 if (wait)
1242 ret = amdgpu_sync_wait(ctx->sync, intr);
1243
1244 drm_exec_fini(&ctx->exec);
1245 ctx->sync = NULL;
1246 return ret;
1247}
1248
1249static int unmap_bo_from_gpuvm(struct kgd_mem *mem,
1250 struct kfd_mem_attachment *entry,
1251 struct amdgpu_sync *sync)
1252{
1253 struct amdgpu_bo_va *bo_va = entry->bo_va;
1254 struct amdgpu_device *adev = entry->adev;
1255 struct amdgpu_vm *vm = bo_va->base.vm;
1256
1257 if (bo_va->queue_refcount) {
1258 pr_debug("bo_va->queue_refcount %d\n", bo_va->queue_refcount);
1259 return -EBUSY;
1260 }
1261
1262 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1263
1264 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1265
1266 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1267
1268 return 0;
1269}
1270
1271static int update_gpuvm_pte(struct kgd_mem *mem,
1272 struct kfd_mem_attachment *entry,
1273 struct amdgpu_sync *sync)
1274{
1275 struct amdgpu_bo_va *bo_va = entry->bo_va;
1276 struct amdgpu_device *adev = entry->adev;
1277 int ret;
1278
1279 ret = kfd_mem_dmamap_attachment(mem, entry);
1280 if (ret)
1281 return ret;
1282
1283 /* Update the page tables */
1284 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1285 if (ret) {
1286 pr_err("amdgpu_vm_bo_update failed\n");
1287 return ret;
1288 }
1289
1290 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1291}
1292
1293static int map_bo_to_gpuvm(struct kgd_mem *mem,
1294 struct kfd_mem_attachment *entry,
1295 struct amdgpu_sync *sync,
1296 bool no_update_pte)
1297{
1298 int ret;
1299
1300 /* Set virtual address for the allocation */
1301 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1302 amdgpu_bo_size(entry->bo_va->base.bo),
1303 entry->pte_flags);
1304 if (ret) {
1305 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1306 entry->va, ret);
1307 return ret;
1308 }
1309
1310 if (no_update_pte)
1311 return 0;
1312
1313 ret = update_gpuvm_pte(mem, entry, sync);
1314 if (ret) {
1315 pr_err("update_gpuvm_pte() failed\n");
1316 goto update_gpuvm_pte_failed;
1317 }
1318
1319 return 0;
1320
1321update_gpuvm_pte_failed:
1322 unmap_bo_from_gpuvm(mem, entry, sync);
1323 kfd_mem_dmaunmap_attachment(mem, entry);
1324 return ret;
1325}
1326
1327static int process_validate_vms(struct amdkfd_process_info *process_info,
1328 struct ww_acquire_ctx *ticket)
1329{
1330 struct amdgpu_vm *peer_vm;
1331 int ret;
1332
1333 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1334 vm_list_node) {
1335 ret = vm_validate_pt_pd_bos(peer_vm, ticket);
1336 if (ret)
1337 return ret;
1338 }
1339
1340 return 0;
1341}
1342
1343static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1344 struct amdgpu_sync *sync)
1345{
1346 struct amdgpu_vm *peer_vm;
1347 int ret;
1348
1349 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1350 vm_list_node) {
1351 struct amdgpu_bo *pd = peer_vm->root.bo;
1352
1353 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1354 AMDGPU_SYNC_NE_OWNER,
1355 AMDGPU_FENCE_OWNER_KFD);
1356 if (ret)
1357 return ret;
1358 }
1359
1360 return 0;
1361}
1362
1363static int process_update_pds(struct amdkfd_process_info *process_info,
1364 struct amdgpu_sync *sync)
1365{
1366 struct amdgpu_vm *peer_vm;
1367 int ret;
1368
1369 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1370 vm_list_node) {
1371 ret = vm_update_pds(peer_vm, sync);
1372 if (ret)
1373 return ret;
1374 }
1375
1376 return 0;
1377}
1378
1379static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1380 struct dma_fence **ef)
1381{
1382 struct amdkfd_process_info *info = NULL;
1383 int ret;
1384
1385 if (!*process_info) {
1386 info = kzalloc(sizeof(*info), GFP_KERNEL);
1387 if (!info)
1388 return -ENOMEM;
1389
1390 mutex_init(&info->lock);
1391 mutex_init(&info->notifier_lock);
1392 INIT_LIST_HEAD(&info->vm_list_head);
1393 INIT_LIST_HEAD(&info->kfd_bo_list);
1394 INIT_LIST_HEAD(&info->userptr_valid_list);
1395 INIT_LIST_HEAD(&info->userptr_inval_list);
1396
1397 info->eviction_fence =
1398 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1399 current->mm,
1400 NULL);
1401 if (!info->eviction_fence) {
1402 pr_err("Failed to create eviction fence\n");
1403 ret = -ENOMEM;
1404 goto create_evict_fence_fail;
1405 }
1406
1407 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1408 INIT_DELAYED_WORK(&info->restore_userptr_work,
1409 amdgpu_amdkfd_restore_userptr_worker);
1410
1411 *process_info = info;
1412 }
1413
1414 vm->process_info = *process_info;
1415
1416 /* Validate page directory and attach eviction fence */
1417 ret = amdgpu_bo_reserve(vm->root.bo, true);
1418 if (ret)
1419 goto reserve_pd_fail;
1420 ret = vm_validate_pt_pd_bos(vm, NULL);
1421 if (ret) {
1422 pr_err("validate_pt_pd_bos() failed\n");
1423 goto validate_pd_fail;
1424 }
1425 ret = amdgpu_bo_sync_wait(vm->root.bo,
1426 AMDGPU_FENCE_OWNER_KFD, false);
1427 if (ret)
1428 goto wait_pd_fail;
1429 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1430 if (ret)
1431 goto reserve_shared_fail;
1432 dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1433 &vm->process_info->eviction_fence->base,
1434 DMA_RESV_USAGE_BOOKKEEP);
1435 amdgpu_bo_unreserve(vm->root.bo);
1436
1437 /* Update process info */
1438 mutex_lock(&vm->process_info->lock);
1439 list_add_tail(&vm->vm_list_node,
1440 &(vm->process_info->vm_list_head));
1441 vm->process_info->n_vms++;
1442 if (ef)
1443 *ef = dma_fence_get(&vm->process_info->eviction_fence->base);
1444 mutex_unlock(&vm->process_info->lock);
1445
1446 return 0;
1447
1448reserve_shared_fail:
1449wait_pd_fail:
1450validate_pd_fail:
1451 amdgpu_bo_unreserve(vm->root.bo);
1452reserve_pd_fail:
1453 vm->process_info = NULL;
1454 if (info) {
1455 dma_fence_put(&info->eviction_fence->base);
1456 *process_info = NULL;
1457 put_pid(info->pid);
1458create_evict_fence_fail:
1459 mutex_destroy(&info->lock);
1460 mutex_destroy(&info->notifier_lock);
1461 kfree(info);
1462 }
1463 return ret;
1464}
1465
1466/**
1467 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1468 * @bo: Handle of buffer object being pinned
1469 * @domain: Domain into which BO should be pinned
1470 *
1471 * - USERPTR BOs are UNPINNABLE and will return error
1472 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1473 * PIN count incremented. It is valid to PIN a BO multiple times
1474 *
1475 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1476 */
1477static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1478{
1479 int ret = 0;
1480
1481 ret = amdgpu_bo_reserve(bo, false);
1482 if (unlikely(ret))
1483 return ret;
1484
1485 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) {
1486 /*
1487 * If bo is not contiguous on VRAM, move to system memory first to ensure
1488 * we can get contiguous VRAM space after evicting other BOs.
1489 */
1490 if (!(bo->tbo.resource->placement & TTM_PL_FLAG_CONTIGUOUS)) {
1491 struct ttm_operation_ctx ctx = { true, false };
1492
1493 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
1494 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1495 if (unlikely(ret)) {
1496 pr_debug("validate bo 0x%p to GTT failed %d\n", &bo->tbo, ret);
1497 goto out;
1498 }
1499 }
1500 }
1501
1502 ret = amdgpu_bo_pin(bo, domain);
1503 if (ret)
1504 pr_err("Error in Pinning BO to domain: %d\n", domain);
1505
1506 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1507out:
1508 amdgpu_bo_unreserve(bo);
1509 return ret;
1510}
1511
1512/**
1513 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1514 * @bo: Handle of buffer object being unpinned
1515 *
1516 * - Is a illegal request for USERPTR BOs and is ignored
1517 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1518 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1519 */
1520static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1521{
1522 int ret = 0;
1523
1524 ret = amdgpu_bo_reserve(bo, false);
1525 if (unlikely(ret))
1526 return;
1527
1528 amdgpu_bo_unpin(bo);
1529 amdgpu_bo_unreserve(bo);
1530}
1531
1532int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1533 struct amdgpu_vm *avm, u32 pasid)
1534
1535{
1536 int ret;
1537
1538 /* Free the original amdgpu allocated pasid,
1539 * will be replaced with kfd allocated pasid.
1540 */
1541 if (avm->pasid) {
1542 amdgpu_pasid_free(avm->pasid);
1543 amdgpu_vm_set_pasid(adev, avm, 0);
1544 }
1545
1546 ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1547 if (ret)
1548 return ret;
1549
1550 return 0;
1551}
1552
1553int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1554 struct amdgpu_vm *avm,
1555 void **process_info,
1556 struct dma_fence **ef)
1557{
1558 int ret;
1559
1560 /* Already a compute VM? */
1561 if (avm->process_info)
1562 return -EINVAL;
1563
1564 /* Convert VM into a compute VM */
1565 ret = amdgpu_vm_make_compute(adev, avm);
1566 if (ret)
1567 return ret;
1568
1569 /* Initialize KFD part of the VM and process info */
1570 ret = init_kfd_vm(avm, process_info, ef);
1571 if (ret)
1572 return ret;
1573
1574 amdgpu_vm_set_task_info(avm);
1575
1576 return 0;
1577}
1578
1579void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1580 struct amdgpu_vm *vm)
1581{
1582 struct amdkfd_process_info *process_info = vm->process_info;
1583
1584 if (!process_info)
1585 return;
1586
1587 /* Update process info */
1588 mutex_lock(&process_info->lock);
1589 process_info->n_vms--;
1590 list_del(&vm->vm_list_node);
1591 mutex_unlock(&process_info->lock);
1592
1593 vm->process_info = NULL;
1594
1595 /* Release per-process resources when last compute VM is destroyed */
1596 if (!process_info->n_vms) {
1597 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1598 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1599 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1600
1601 dma_fence_put(&process_info->eviction_fence->base);
1602 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1603 put_pid(process_info->pid);
1604 mutex_destroy(&process_info->lock);
1605 mutex_destroy(&process_info->notifier_lock);
1606 kfree(process_info);
1607 }
1608}
1609
1610void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1611 void *drm_priv)
1612{
1613 struct amdgpu_vm *avm;
1614
1615 if (WARN_ON(!adev || !drm_priv))
1616 return;
1617
1618 avm = drm_priv_to_vm(drm_priv);
1619
1620 pr_debug("Releasing process vm %p\n", avm);
1621
1622 /* The original pasid of amdgpu vm has already been
1623 * released during making a amdgpu vm to a compute vm
1624 * The current pasid is managed by kfd and will be
1625 * released on kfd process destroy. Set amdgpu pasid
1626 * to 0 to avoid duplicate release.
1627 */
1628 amdgpu_vm_release_compute(adev, avm);
1629}
1630
1631uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1632{
1633 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1634 struct amdgpu_bo *pd = avm->root.bo;
1635 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1636
1637 if (adev->asic_type < CHIP_VEGA10)
1638 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1639 return avm->pd_phys_addr;
1640}
1641
1642void amdgpu_amdkfd_block_mmu_notifications(void *p)
1643{
1644 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1645
1646 mutex_lock(&pinfo->lock);
1647 WRITE_ONCE(pinfo->block_mmu_notifications, true);
1648 mutex_unlock(&pinfo->lock);
1649}
1650
1651int amdgpu_amdkfd_criu_resume(void *p)
1652{
1653 int ret = 0;
1654 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1655
1656 mutex_lock(&pinfo->lock);
1657 pr_debug("scheduling work\n");
1658 mutex_lock(&pinfo->notifier_lock);
1659 pinfo->evicted_bos++;
1660 mutex_unlock(&pinfo->notifier_lock);
1661 if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1662 ret = -EINVAL;
1663 goto out_unlock;
1664 }
1665 WRITE_ONCE(pinfo->block_mmu_notifications, false);
1666 queue_delayed_work(system_freezable_wq,
1667 &pinfo->restore_userptr_work, 0);
1668
1669out_unlock:
1670 mutex_unlock(&pinfo->lock);
1671 return ret;
1672}
1673
1674size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1675 uint8_t xcp_id)
1676{
1677 uint64_t reserved_for_pt =
1678 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1679 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1680 uint64_t reserved_for_ras = (con ? con->reserved_pages_in_bytes : 0);
1681 ssize_t available;
1682 uint64_t vram_available, system_mem_available, ttm_mem_available;
1683
1684 spin_lock(&kfd_mem_limit.mem_limit_lock);
1685 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1686 - adev->kfd.vram_used_aligned[xcp_id]
1687 - atomic64_read(&adev->vram_pin_size)
1688 - reserved_for_pt
1689 - reserved_for_ras;
1690
1691 if (adev->flags & AMD_IS_APU) {
1692 system_mem_available = no_system_mem_limit ?
1693 kfd_mem_limit.max_system_mem_limit :
1694 kfd_mem_limit.max_system_mem_limit -
1695 kfd_mem_limit.system_mem_used;
1696
1697 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1698 kfd_mem_limit.ttm_mem_used;
1699
1700 available = min3(system_mem_available, ttm_mem_available,
1701 vram_available);
1702 available = ALIGN_DOWN(available, PAGE_SIZE);
1703 } else {
1704 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1705 }
1706
1707 spin_unlock(&kfd_mem_limit.mem_limit_lock);
1708
1709 if (available < 0)
1710 available = 0;
1711
1712 return available;
1713}
1714
1715int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1716 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1717 void *drm_priv, struct kgd_mem **mem,
1718 uint64_t *offset, uint32_t flags, bool criu_resume)
1719{
1720 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1721 struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1722 enum ttm_bo_type bo_type = ttm_bo_type_device;
1723 struct sg_table *sg = NULL;
1724 uint64_t user_addr = 0;
1725 struct amdgpu_bo *bo;
1726 struct drm_gem_object *gobj = NULL;
1727 u32 domain, alloc_domain;
1728 uint64_t aligned_size;
1729 int8_t xcp_id = -1;
1730 u64 alloc_flags;
1731 int ret;
1732
1733 /*
1734 * Check on which domain to allocate BO
1735 */
1736 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1737 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1738
1739 if (adev->flags & AMD_IS_APU) {
1740 domain = AMDGPU_GEM_DOMAIN_GTT;
1741 alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1742 alloc_flags = 0;
1743 } else {
1744 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1745 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1746 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1747
1748 /* For contiguous VRAM allocation */
1749 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_CONTIGUOUS)
1750 alloc_flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1751 }
1752 xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1753 0 : fpriv->xcp_id;
1754 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1755 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1756 alloc_flags = 0;
1757 } else {
1758 domain = AMDGPU_GEM_DOMAIN_GTT;
1759 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1760 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1761
1762 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1763 if (!offset || !*offset)
1764 return -EINVAL;
1765 user_addr = untagged_addr(*offset);
1766 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1767 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1768 bo_type = ttm_bo_type_sg;
1769 if (size > UINT_MAX)
1770 return -EINVAL;
1771 sg = create_sg_table(*offset, size);
1772 if (!sg)
1773 return -ENOMEM;
1774 } else {
1775 return -EINVAL;
1776 }
1777 }
1778
1779 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1780 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1781 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT)
1782 alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT;
1783 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1784 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1785
1786 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1787 if (!*mem) {
1788 ret = -ENOMEM;
1789 goto err;
1790 }
1791 INIT_LIST_HEAD(&(*mem)->attachments);
1792 mutex_init(&(*mem)->lock);
1793 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1794
1795 /* Workaround for AQL queue wraparound bug. Map the same
1796 * memory twice. That means we only actually allocate half
1797 * the memory.
1798 */
1799 if ((*mem)->aql_queue)
1800 size >>= 1;
1801 aligned_size = PAGE_ALIGN(size);
1802
1803 (*mem)->alloc_flags = flags;
1804
1805 amdgpu_sync_create(&(*mem)->sync);
1806
1807 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1808 xcp_id);
1809 if (ret) {
1810 pr_debug("Insufficient memory\n");
1811 goto err_reserve_limit;
1812 }
1813
1814 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1815 va, (*mem)->aql_queue ? size << 1 : size,
1816 domain_string(alloc_domain), xcp_id);
1817
1818 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1819 bo_type, NULL, &gobj, xcp_id + 1);
1820 if (ret) {
1821 pr_debug("Failed to create BO on domain %s. ret %d\n",
1822 domain_string(alloc_domain), ret);
1823 goto err_bo_create;
1824 }
1825 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1826 if (ret) {
1827 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1828 goto err_node_allow;
1829 }
1830 ret = drm_gem_handle_create(adev->kfd.client.file, gobj, &(*mem)->gem_handle);
1831 if (ret)
1832 goto err_gem_handle_create;
1833 bo = gem_to_amdgpu_bo(gobj);
1834 if (bo_type == ttm_bo_type_sg) {
1835 bo->tbo.sg = sg;
1836 bo->tbo.ttm->sg = sg;
1837 }
1838 bo->kfd_bo = *mem;
1839 (*mem)->bo = bo;
1840 if (user_addr)
1841 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1842
1843 (*mem)->va = va;
1844 (*mem)->domain = domain;
1845 (*mem)->mapped_to_gpu_memory = 0;
1846 (*mem)->process_info = avm->process_info;
1847
1848 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1849
1850 if (user_addr) {
1851 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1852 ret = init_user_pages(*mem, user_addr, criu_resume);
1853 if (ret)
1854 goto allocate_init_user_pages_failed;
1855 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1856 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1857 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1858 if (ret) {
1859 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1860 goto err_pin_bo;
1861 }
1862 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1863 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1864 } else {
1865 mutex_lock(&avm->process_info->lock);
1866 if (avm->process_info->eviction_fence &&
1867 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
1868 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain,
1869 &avm->process_info->eviction_fence->base);
1870 mutex_unlock(&avm->process_info->lock);
1871 if (ret)
1872 goto err_validate_bo;
1873 }
1874
1875 if (offset)
1876 *offset = amdgpu_bo_mmap_offset(bo);
1877
1878 return 0;
1879
1880allocate_init_user_pages_failed:
1881err_pin_bo:
1882err_validate_bo:
1883 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1884 drm_gem_handle_delete(adev->kfd.client.file, (*mem)->gem_handle);
1885err_gem_handle_create:
1886 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1887err_node_allow:
1888 /* Don't unreserve system mem limit twice */
1889 goto err_reserve_limit;
1890err_bo_create:
1891 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1892err_reserve_limit:
1893 amdgpu_sync_free(&(*mem)->sync);
1894 mutex_destroy(&(*mem)->lock);
1895 if (gobj)
1896 drm_gem_object_put(gobj);
1897 else
1898 kfree(*mem);
1899err:
1900 if (sg) {
1901 sg_free_table(sg);
1902 kfree(sg);
1903 }
1904 return ret;
1905}
1906
1907int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1908 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1909 uint64_t *size)
1910{
1911 struct amdkfd_process_info *process_info = mem->process_info;
1912 unsigned long bo_size = mem->bo->tbo.base.size;
1913 bool use_release_notifier = (mem->bo->kfd_bo == mem);
1914 struct kfd_mem_attachment *entry, *tmp;
1915 struct bo_vm_reservation_context ctx;
1916 unsigned int mapped_to_gpu_memory;
1917 int ret;
1918 bool is_imported = false;
1919
1920 mutex_lock(&mem->lock);
1921
1922 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1923 if (mem->alloc_flags &
1924 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1925 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1926 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1927 }
1928
1929 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1930 is_imported = mem->is_imported;
1931 mutex_unlock(&mem->lock);
1932 /* lock is not needed after this, since mem is unused and will
1933 * be freed anyway
1934 */
1935
1936 if (mapped_to_gpu_memory > 0) {
1937 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1938 mem->va, bo_size);
1939 return -EBUSY;
1940 }
1941
1942 /* Make sure restore workers don't access the BO any more */
1943 mutex_lock(&process_info->lock);
1944 list_del(&mem->validate_list);
1945 mutex_unlock(&process_info->lock);
1946
1947 /* Cleanup user pages and MMU notifiers */
1948 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1949 amdgpu_hmm_unregister(mem->bo);
1950 mutex_lock(&process_info->notifier_lock);
1951 amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1952 mutex_unlock(&process_info->notifier_lock);
1953 }
1954
1955 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1956 if (unlikely(ret))
1957 return ret;
1958
1959 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1960 process_info->eviction_fence);
1961 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1962 mem->va + bo_size * (1 + mem->aql_queue));
1963
1964 /* Remove from VM internal data structures */
1965 list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
1966 kfd_mem_dmaunmap_attachment(mem, entry);
1967 kfd_mem_detach(entry);
1968 }
1969
1970 ret = unreserve_bo_and_vms(&ctx, false, false);
1971
1972 /* Free the sync object */
1973 amdgpu_sync_free(&mem->sync);
1974
1975 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1976 * remap BO. We need to free it.
1977 */
1978 if (mem->bo->tbo.sg) {
1979 sg_free_table(mem->bo->tbo.sg);
1980 kfree(mem->bo->tbo.sg);
1981 }
1982
1983 /* Update the size of the BO being freed if it was allocated from
1984 * VRAM and is not imported. For APP APU VRAM allocations are done
1985 * in GTT domain
1986 */
1987 if (size) {
1988 if (!is_imported &&
1989 (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1990 ((adev->flags & AMD_IS_APU) &&
1991 mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1992 *size = bo_size;
1993 else
1994 *size = 0;
1995 }
1996
1997 /* Free the BO*/
1998 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1999 drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle);
2000 if (mem->dmabuf) {
2001 dma_buf_put(mem->dmabuf);
2002 mem->dmabuf = NULL;
2003 }
2004 mutex_destroy(&mem->lock);
2005
2006 /* If this releases the last reference, it will end up calling
2007 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
2008 * this needs to be the last call here.
2009 */
2010 drm_gem_object_put(&mem->bo->tbo.base);
2011
2012 /*
2013 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
2014 * explicitly free it here.
2015 */
2016 if (!use_release_notifier)
2017 kfree(mem);
2018
2019 return ret;
2020}
2021
2022int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
2023 struct amdgpu_device *adev, struct kgd_mem *mem,
2024 void *drm_priv)
2025{
2026 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2027 int ret;
2028 struct amdgpu_bo *bo;
2029 uint32_t domain;
2030 struct kfd_mem_attachment *entry;
2031 struct bo_vm_reservation_context ctx;
2032 unsigned long bo_size;
2033 bool is_invalid_userptr = false;
2034
2035 bo = mem->bo;
2036 if (!bo) {
2037 pr_err("Invalid BO when mapping memory to GPU\n");
2038 return -EINVAL;
2039 }
2040
2041 /* Make sure restore is not running concurrently. Since we
2042 * don't map invalid userptr BOs, we rely on the next restore
2043 * worker to do the mapping
2044 */
2045 mutex_lock(&mem->process_info->lock);
2046
2047 /* Lock notifier lock. If we find an invalid userptr BO, we can be
2048 * sure that the MMU notifier is no longer running
2049 * concurrently and the queues are actually stopped
2050 */
2051 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2052 mutex_lock(&mem->process_info->notifier_lock);
2053 is_invalid_userptr = !!mem->invalid;
2054 mutex_unlock(&mem->process_info->notifier_lock);
2055 }
2056
2057 mutex_lock(&mem->lock);
2058
2059 domain = mem->domain;
2060 bo_size = bo->tbo.base.size;
2061
2062 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
2063 mem->va,
2064 mem->va + bo_size * (1 + mem->aql_queue),
2065 avm, domain_string(domain));
2066
2067 if (!kfd_mem_is_attached(avm, mem)) {
2068 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
2069 if (ret)
2070 goto out;
2071 }
2072
2073 ret = reserve_bo_and_vm(mem, avm, &ctx);
2074 if (unlikely(ret))
2075 goto out;
2076
2077 /* Userptr can be marked as "not invalid", but not actually be
2078 * validated yet (still in the system domain). In that case
2079 * the queues are still stopped and we can leave mapping for
2080 * the next restore worker
2081 */
2082 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
2083 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
2084 is_invalid_userptr = true;
2085
2086 ret = vm_validate_pt_pd_bos(avm, NULL);
2087 if (unlikely(ret))
2088 goto out_unreserve;
2089
2090 list_for_each_entry(entry, &mem->attachments, list) {
2091 if (entry->bo_va->base.vm != avm || entry->is_mapped)
2092 continue;
2093
2094 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2095 entry->va, entry->va + bo_size, entry);
2096
2097 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2098 is_invalid_userptr);
2099 if (ret) {
2100 pr_err("Failed to map bo to gpuvm\n");
2101 goto out_unreserve;
2102 }
2103
2104 ret = vm_update_pds(avm, ctx.sync);
2105 if (ret) {
2106 pr_err("Failed to update page directories\n");
2107 goto out_unreserve;
2108 }
2109
2110 entry->is_mapped = true;
2111 mem->mapped_to_gpu_memory++;
2112 pr_debug("\t INC mapping count %d\n",
2113 mem->mapped_to_gpu_memory);
2114 }
2115
2116 ret = unreserve_bo_and_vms(&ctx, false, false);
2117
2118 goto out;
2119
2120out_unreserve:
2121 unreserve_bo_and_vms(&ctx, false, false);
2122out:
2123 mutex_unlock(&mem->process_info->lock);
2124 mutex_unlock(&mem->lock);
2125 return ret;
2126}
2127
2128int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv)
2129{
2130 struct kfd_mem_attachment *entry;
2131 struct amdgpu_vm *vm;
2132 int ret;
2133
2134 vm = drm_priv_to_vm(drm_priv);
2135
2136 mutex_lock(&mem->lock);
2137
2138 ret = amdgpu_bo_reserve(mem->bo, true);
2139 if (ret)
2140 goto out;
2141
2142 list_for_each_entry(entry, &mem->attachments, list) {
2143 if (entry->bo_va->base.vm != vm)
2144 continue;
2145 if (entry->bo_va->base.bo->tbo.ttm &&
2146 !entry->bo_va->base.bo->tbo.ttm->sg)
2147 continue;
2148
2149 kfd_mem_dmaunmap_attachment(mem, entry);
2150 }
2151
2152 amdgpu_bo_unreserve(mem->bo);
2153out:
2154 mutex_unlock(&mem->lock);
2155
2156 return ret;
2157}
2158
2159int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2160 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2161{
2162 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2163 unsigned long bo_size = mem->bo->tbo.base.size;
2164 struct kfd_mem_attachment *entry;
2165 struct bo_vm_reservation_context ctx;
2166 int ret;
2167
2168 mutex_lock(&mem->lock);
2169
2170 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2171 if (unlikely(ret))
2172 goto out;
2173 /* If no VMs were reserved, it means the BO wasn't actually mapped */
2174 if (ctx.n_vms == 0) {
2175 ret = -EINVAL;
2176 goto unreserve_out;
2177 }
2178
2179 ret = vm_validate_pt_pd_bos(avm, NULL);
2180 if (unlikely(ret))
2181 goto unreserve_out;
2182
2183 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2184 mem->va,
2185 mem->va + bo_size * (1 + mem->aql_queue),
2186 avm);
2187
2188 list_for_each_entry(entry, &mem->attachments, list) {
2189 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2190 continue;
2191
2192 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2193 entry->va, entry->va + bo_size, entry);
2194
2195 ret = unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2196 if (ret)
2197 goto unreserve_out;
2198
2199 entry->is_mapped = false;
2200
2201 mem->mapped_to_gpu_memory--;
2202 pr_debug("\t DEC mapping count %d\n",
2203 mem->mapped_to_gpu_memory);
2204 }
2205
2206unreserve_out:
2207 unreserve_bo_and_vms(&ctx, false, false);
2208out:
2209 mutex_unlock(&mem->lock);
2210 return ret;
2211}
2212
2213int amdgpu_amdkfd_gpuvm_sync_memory(
2214 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2215{
2216 struct amdgpu_sync sync;
2217 int ret;
2218
2219 amdgpu_sync_create(&sync);
2220
2221 mutex_lock(&mem->lock);
2222 amdgpu_sync_clone(&mem->sync, &sync);
2223 mutex_unlock(&mem->lock);
2224
2225 ret = amdgpu_sync_wait(&sync, intr);
2226 amdgpu_sync_free(&sync);
2227 return ret;
2228}
2229
2230/**
2231 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2232 * @bo: Buffer object to be mapped
2233 * @bo_gart: Return bo reference
2234 *
2235 * Before return, bo reference count is incremented. To release the reference and unpin/
2236 * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2237 */
2238int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart)
2239{
2240 int ret;
2241
2242 ret = amdgpu_bo_reserve(bo, true);
2243 if (ret) {
2244 pr_err("Failed to reserve bo. ret %d\n", ret);
2245 goto err_reserve_bo_failed;
2246 }
2247
2248 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2249 if (ret) {
2250 pr_err("Failed to pin bo. ret %d\n", ret);
2251 goto err_pin_bo_failed;
2252 }
2253
2254 ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2255 if (ret) {
2256 pr_err("Failed to bind bo to GART. ret %d\n", ret);
2257 goto err_map_bo_gart_failed;
2258 }
2259
2260 amdgpu_amdkfd_remove_eviction_fence(
2261 bo, bo->vm_bo->vm->process_info->eviction_fence);
2262
2263 amdgpu_bo_unreserve(bo);
2264
2265 *bo_gart = amdgpu_bo_ref(bo);
2266
2267 return 0;
2268
2269err_map_bo_gart_failed:
2270 amdgpu_bo_unpin(bo);
2271err_pin_bo_failed:
2272 amdgpu_bo_unreserve(bo);
2273err_reserve_bo_failed:
2274
2275 return ret;
2276}
2277
2278/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2279 *
2280 * @mem: Buffer object to be mapped for CPU access
2281 * @kptr[out]: pointer in kernel CPU address space
2282 * @size[out]: size of the buffer
2283 *
2284 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2285 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2286 * validate_list, so the GPU mapping can be restored after a page table was
2287 * evicted.
2288 *
2289 * Return: 0 on success, error code on failure
2290 */
2291int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2292 void **kptr, uint64_t *size)
2293{
2294 int ret;
2295 struct amdgpu_bo *bo = mem->bo;
2296
2297 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2298 pr_err("userptr can't be mapped to kernel\n");
2299 return -EINVAL;
2300 }
2301
2302 mutex_lock(&mem->process_info->lock);
2303
2304 ret = amdgpu_bo_reserve(bo, true);
2305 if (ret) {
2306 pr_err("Failed to reserve bo. ret %d\n", ret);
2307 goto bo_reserve_failed;
2308 }
2309
2310 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2311 if (ret) {
2312 pr_err("Failed to pin bo. ret %d\n", ret);
2313 goto pin_failed;
2314 }
2315
2316 ret = amdgpu_bo_kmap(bo, kptr);
2317 if (ret) {
2318 pr_err("Failed to map bo to kernel. ret %d\n", ret);
2319 goto kmap_failed;
2320 }
2321
2322 amdgpu_amdkfd_remove_eviction_fence(
2323 bo, mem->process_info->eviction_fence);
2324
2325 if (size)
2326 *size = amdgpu_bo_size(bo);
2327
2328 amdgpu_bo_unreserve(bo);
2329
2330 mutex_unlock(&mem->process_info->lock);
2331 return 0;
2332
2333kmap_failed:
2334 amdgpu_bo_unpin(bo);
2335pin_failed:
2336 amdgpu_bo_unreserve(bo);
2337bo_reserve_failed:
2338 mutex_unlock(&mem->process_info->lock);
2339
2340 return ret;
2341}
2342
2343/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2344 *
2345 * @mem: Buffer object to be unmapped for CPU access
2346 *
2347 * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2348 * eviction fence, so this function should only be used for cleanup before the
2349 * BO is destroyed.
2350 */
2351void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2352{
2353 struct amdgpu_bo *bo = mem->bo;
2354
2355 amdgpu_bo_reserve(bo, true);
2356 amdgpu_bo_kunmap(bo);
2357 amdgpu_bo_unpin(bo);
2358 amdgpu_bo_unreserve(bo);
2359}
2360
2361int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2362 struct kfd_vm_fault_info *mem)
2363{
2364 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2365 *mem = *adev->gmc.vm_fault_info;
2366 mb(); /* make sure read happened */
2367 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2368 }
2369 return 0;
2370}
2371
2372static int import_obj_create(struct amdgpu_device *adev,
2373 struct dma_buf *dma_buf,
2374 struct drm_gem_object *obj,
2375 uint64_t va, void *drm_priv,
2376 struct kgd_mem **mem, uint64_t *size,
2377 uint64_t *mmap_offset)
2378{
2379 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2380 struct amdgpu_bo *bo;
2381 int ret;
2382
2383 bo = gem_to_amdgpu_bo(obj);
2384 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2385 AMDGPU_GEM_DOMAIN_GTT)))
2386 /* Only VRAM and GTT BOs are supported */
2387 return -EINVAL;
2388
2389 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2390 if (!*mem)
2391 return -ENOMEM;
2392
2393 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2394 if (ret)
2395 goto err_free_mem;
2396
2397 if (size)
2398 *size = amdgpu_bo_size(bo);
2399
2400 if (mmap_offset)
2401 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2402
2403 INIT_LIST_HEAD(&(*mem)->attachments);
2404 mutex_init(&(*mem)->lock);
2405
2406 (*mem)->alloc_flags =
2407 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2408 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2409 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2410 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2411
2412 get_dma_buf(dma_buf);
2413 (*mem)->dmabuf = dma_buf;
2414 (*mem)->bo = bo;
2415 (*mem)->va = va;
2416 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) &&
2417 !(adev->flags & AMD_IS_APU) ?
2418 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2419
2420 (*mem)->mapped_to_gpu_memory = 0;
2421 (*mem)->process_info = avm->process_info;
2422 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2423 amdgpu_sync_create(&(*mem)->sync);
2424 (*mem)->is_imported = true;
2425
2426 mutex_lock(&avm->process_info->lock);
2427 if (avm->process_info->eviction_fence &&
2428 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
2429 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, (*mem)->domain,
2430 &avm->process_info->eviction_fence->base);
2431 mutex_unlock(&avm->process_info->lock);
2432 if (ret)
2433 goto err_remove_mem;
2434
2435 return 0;
2436
2437err_remove_mem:
2438 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
2439 drm_vma_node_revoke(&obj->vma_node, drm_priv);
2440err_free_mem:
2441 kfree(*mem);
2442 return ret;
2443}
2444
2445int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
2446 uint64_t va, void *drm_priv,
2447 struct kgd_mem **mem, uint64_t *size,
2448 uint64_t *mmap_offset)
2449{
2450 struct drm_gem_object *obj;
2451 uint32_t handle;
2452 int ret;
2453
2454 ret = drm_gem_prime_fd_to_handle(&adev->ddev, adev->kfd.client.file, fd,
2455 &handle);
2456 if (ret)
2457 return ret;
2458 obj = drm_gem_object_lookup(adev->kfd.client.file, handle);
2459 if (!obj) {
2460 ret = -EINVAL;
2461 goto err_release_handle;
2462 }
2463
2464 ret = import_obj_create(adev, obj->dma_buf, obj, va, drm_priv, mem, size,
2465 mmap_offset);
2466 if (ret)
2467 goto err_put_obj;
2468
2469 (*mem)->gem_handle = handle;
2470
2471 return 0;
2472
2473err_put_obj:
2474 drm_gem_object_put(obj);
2475err_release_handle:
2476 drm_gem_handle_delete(adev->kfd.client.file, handle);
2477 return ret;
2478}
2479
2480int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2481 struct dma_buf **dma_buf)
2482{
2483 int ret;
2484
2485 mutex_lock(&mem->lock);
2486 ret = kfd_mem_export_dmabuf(mem);
2487 if (ret)
2488 goto out;
2489
2490 get_dma_buf(mem->dmabuf);
2491 *dma_buf = mem->dmabuf;
2492out:
2493 mutex_unlock(&mem->lock);
2494 return ret;
2495}
2496
2497/* Evict a userptr BO by stopping the queues if necessary
2498 *
2499 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2500 * cannot do any memory allocations, and cannot take any locks that
2501 * are held elsewhere while allocating memory.
2502 *
2503 * It doesn't do anything to the BO itself. The real work happens in
2504 * restore, where we get updated page addresses. This function only
2505 * ensures that GPU access to the BO is stopped.
2506 */
2507int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2508 unsigned long cur_seq, struct kgd_mem *mem)
2509{
2510 struct amdkfd_process_info *process_info = mem->process_info;
2511 int r = 0;
2512
2513 /* Do not process MMU notifications during CRIU restore until
2514 * KFD_CRIU_OP_RESUME IOCTL is received
2515 */
2516 if (READ_ONCE(process_info->block_mmu_notifications))
2517 return 0;
2518
2519 mutex_lock(&process_info->notifier_lock);
2520 mmu_interval_set_seq(mni, cur_seq);
2521
2522 mem->invalid++;
2523 if (++process_info->evicted_bos == 1) {
2524 /* First eviction, stop the queues */
2525 r = kgd2kfd_quiesce_mm(mni->mm,
2526 KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2527
2528 if (r && r != -ESRCH)
2529 pr_err("Failed to quiesce KFD\n");
2530
2531 if (r != -ESRCH)
2532 queue_delayed_work(system_freezable_wq,
2533 &process_info->restore_userptr_work,
2534 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2535 }
2536 mutex_unlock(&process_info->notifier_lock);
2537
2538 return r;
2539}
2540
2541/* Update invalid userptr BOs
2542 *
2543 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2544 * userptr_inval_list and updates user pages for all BOs that have
2545 * been invalidated since their last update.
2546 */
2547static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2548 struct mm_struct *mm)
2549{
2550 struct kgd_mem *mem, *tmp_mem;
2551 struct amdgpu_bo *bo;
2552 struct ttm_operation_ctx ctx = { false, false };
2553 uint32_t invalid;
2554 int ret = 0;
2555
2556 mutex_lock(&process_info->notifier_lock);
2557
2558 /* Move all invalidated BOs to the userptr_inval_list */
2559 list_for_each_entry_safe(mem, tmp_mem,
2560 &process_info->userptr_valid_list,
2561 validate_list)
2562 if (mem->invalid)
2563 list_move_tail(&mem->validate_list,
2564 &process_info->userptr_inval_list);
2565
2566 /* Go through userptr_inval_list and update any invalid user_pages */
2567 list_for_each_entry(mem, &process_info->userptr_inval_list,
2568 validate_list) {
2569 invalid = mem->invalid;
2570 if (!invalid)
2571 /* BO hasn't been invalidated since the last
2572 * revalidation attempt. Keep its page list.
2573 */
2574 continue;
2575
2576 bo = mem->bo;
2577
2578 amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2579 mem->range = NULL;
2580
2581 /* BO reservations and getting user pages (hmm_range_fault)
2582 * must happen outside the notifier lock
2583 */
2584 mutex_unlock(&process_info->notifier_lock);
2585
2586 /* Move the BO to system (CPU) domain if necessary to unmap
2587 * and free the SG table
2588 */
2589 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2590 if (amdgpu_bo_reserve(bo, true))
2591 return -EAGAIN;
2592 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2593 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2594 amdgpu_bo_unreserve(bo);
2595 if (ret) {
2596 pr_err("%s: Failed to invalidate userptr BO\n",
2597 __func__);
2598 return -EAGAIN;
2599 }
2600 }
2601
2602 /* Get updated user pages */
2603 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2604 &mem->range);
2605 if (ret) {
2606 pr_debug("Failed %d to get user pages\n", ret);
2607
2608 /* Return -EFAULT bad address error as success. It will
2609 * fail later with a VM fault if the GPU tries to access
2610 * it. Better than hanging indefinitely with stalled
2611 * user mode queues.
2612 *
2613 * Return other error -EBUSY or -ENOMEM to retry restore
2614 */
2615 if (ret != -EFAULT)
2616 return ret;
2617
2618 ret = 0;
2619 }
2620
2621 mutex_lock(&process_info->notifier_lock);
2622
2623 /* Mark the BO as valid unless it was invalidated
2624 * again concurrently.
2625 */
2626 if (mem->invalid != invalid) {
2627 ret = -EAGAIN;
2628 goto unlock_out;
2629 }
2630 /* set mem valid if mem has hmm range associated */
2631 if (mem->range)
2632 mem->invalid = 0;
2633 }
2634
2635unlock_out:
2636 mutex_unlock(&process_info->notifier_lock);
2637
2638 return ret;
2639}
2640
2641/* Validate invalid userptr BOs
2642 *
2643 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2644 * with new page addresses and waits for the page table updates to complete.
2645 */
2646static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2647{
2648 struct ttm_operation_ctx ctx = { false, false };
2649 struct amdgpu_sync sync;
2650 struct drm_exec exec;
2651
2652 struct amdgpu_vm *peer_vm;
2653 struct kgd_mem *mem, *tmp_mem;
2654 struct amdgpu_bo *bo;
2655 int ret;
2656
2657 amdgpu_sync_create(&sync);
2658
2659 drm_exec_init(&exec, 0, 0);
2660 /* Reserve all BOs and page tables for validation */
2661 drm_exec_until_all_locked(&exec) {
2662 /* Reserve all the page directories */
2663 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2664 vm_list_node) {
2665 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2666 drm_exec_retry_on_contention(&exec);
2667 if (unlikely(ret))
2668 goto unreserve_out;
2669 }
2670
2671 /* Reserve the userptr_inval_list entries to resv_list */
2672 list_for_each_entry(mem, &process_info->userptr_inval_list,
2673 validate_list) {
2674 struct drm_gem_object *gobj;
2675
2676 gobj = &mem->bo->tbo.base;
2677 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2678 drm_exec_retry_on_contention(&exec);
2679 if (unlikely(ret))
2680 goto unreserve_out;
2681 }
2682 }
2683
2684 ret = process_validate_vms(process_info, NULL);
2685 if (ret)
2686 goto unreserve_out;
2687
2688 /* Validate BOs and update GPUVM page tables */
2689 list_for_each_entry_safe(mem, tmp_mem,
2690 &process_info->userptr_inval_list,
2691 validate_list) {
2692 struct kfd_mem_attachment *attachment;
2693
2694 bo = mem->bo;
2695
2696 /* Validate the BO if we got user pages */
2697 if (bo->tbo.ttm->pages[0]) {
2698 amdgpu_bo_placement_from_domain(bo, mem->domain);
2699 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2700 if (ret) {
2701 pr_err("%s: failed to validate BO\n", __func__);
2702 goto unreserve_out;
2703 }
2704 }
2705
2706 /* Update mapping. If the BO was not validated
2707 * (because we couldn't get user pages), this will
2708 * clear the page table entries, which will result in
2709 * VM faults if the GPU tries to access the invalid
2710 * memory.
2711 */
2712 list_for_each_entry(attachment, &mem->attachments, list) {
2713 if (!attachment->is_mapped)
2714 continue;
2715
2716 kfd_mem_dmaunmap_attachment(mem, attachment);
2717 ret = update_gpuvm_pte(mem, attachment, &sync);
2718 if (ret) {
2719 pr_err("%s: update PTE failed\n", __func__);
2720 /* make sure this gets validated again */
2721 mutex_lock(&process_info->notifier_lock);
2722 mem->invalid++;
2723 mutex_unlock(&process_info->notifier_lock);
2724 goto unreserve_out;
2725 }
2726 }
2727 }
2728
2729 /* Update page directories */
2730 ret = process_update_pds(process_info, &sync);
2731
2732unreserve_out:
2733 drm_exec_fini(&exec);
2734 amdgpu_sync_wait(&sync, false);
2735 amdgpu_sync_free(&sync);
2736
2737 return ret;
2738}
2739
2740/* Confirm that all user pages are valid while holding the notifier lock
2741 *
2742 * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2743 */
2744static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2745{
2746 struct kgd_mem *mem, *tmp_mem;
2747 int ret = 0;
2748
2749 list_for_each_entry_safe(mem, tmp_mem,
2750 &process_info->userptr_inval_list,
2751 validate_list) {
2752 bool valid;
2753
2754 /* keep mem without hmm range at userptr_inval_list */
2755 if (!mem->range)
2756 continue;
2757
2758 /* Only check mem with hmm range associated */
2759 valid = amdgpu_ttm_tt_get_user_pages_done(
2760 mem->bo->tbo.ttm, mem->range);
2761
2762 mem->range = NULL;
2763 if (!valid) {
2764 WARN(!mem->invalid, "Invalid BO not marked invalid");
2765 ret = -EAGAIN;
2766 continue;
2767 }
2768
2769 if (mem->invalid) {
2770 WARN(1, "Valid BO is marked invalid");
2771 ret = -EAGAIN;
2772 continue;
2773 }
2774
2775 list_move_tail(&mem->validate_list,
2776 &process_info->userptr_valid_list);
2777 }
2778
2779 return ret;
2780}
2781
2782/* Worker callback to restore evicted userptr BOs
2783 *
2784 * Tries to update and validate all userptr BOs. If successful and no
2785 * concurrent evictions happened, the queues are restarted. Otherwise,
2786 * reschedule for another attempt later.
2787 */
2788static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2789{
2790 struct delayed_work *dwork = to_delayed_work(work);
2791 struct amdkfd_process_info *process_info =
2792 container_of(dwork, struct amdkfd_process_info,
2793 restore_userptr_work);
2794 struct task_struct *usertask;
2795 struct mm_struct *mm;
2796 uint32_t evicted_bos;
2797
2798 mutex_lock(&process_info->notifier_lock);
2799 evicted_bos = process_info->evicted_bos;
2800 mutex_unlock(&process_info->notifier_lock);
2801 if (!evicted_bos)
2802 return;
2803
2804 /* Reference task and mm in case of concurrent process termination */
2805 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2806 if (!usertask)
2807 return;
2808 mm = get_task_mm(usertask);
2809 if (!mm) {
2810 put_task_struct(usertask);
2811 return;
2812 }
2813
2814 mutex_lock(&process_info->lock);
2815
2816 if (update_invalid_user_pages(process_info, mm))
2817 goto unlock_out;
2818 /* userptr_inval_list can be empty if all evicted userptr BOs
2819 * have been freed. In that case there is nothing to validate
2820 * and we can just restart the queues.
2821 */
2822 if (!list_empty(&process_info->userptr_inval_list)) {
2823 if (validate_invalid_user_pages(process_info))
2824 goto unlock_out;
2825 }
2826 /* Final check for concurrent evicton and atomic update. If
2827 * another eviction happens after successful update, it will
2828 * be a first eviction that calls quiesce_mm. The eviction
2829 * reference counting inside KFD will handle this case.
2830 */
2831 mutex_lock(&process_info->notifier_lock);
2832 if (process_info->evicted_bos != evicted_bos)
2833 goto unlock_notifier_out;
2834
2835 if (confirm_valid_user_pages_locked(process_info)) {
2836 WARN(1, "User pages unexpectedly invalid");
2837 goto unlock_notifier_out;
2838 }
2839
2840 process_info->evicted_bos = evicted_bos = 0;
2841
2842 if (kgd2kfd_resume_mm(mm)) {
2843 pr_err("%s: Failed to resume KFD\n", __func__);
2844 /* No recovery from this failure. Probably the CP is
2845 * hanging. No point trying again.
2846 */
2847 }
2848
2849unlock_notifier_out:
2850 mutex_unlock(&process_info->notifier_lock);
2851unlock_out:
2852 mutex_unlock(&process_info->lock);
2853
2854 /* If validation failed, reschedule another attempt */
2855 if (evicted_bos) {
2856 queue_delayed_work(system_freezable_wq,
2857 &process_info->restore_userptr_work,
2858 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2859
2860 kfd_smi_event_queue_restore_rescheduled(mm);
2861 }
2862 mmput(mm);
2863 put_task_struct(usertask);
2864}
2865
2866static void replace_eviction_fence(struct dma_fence __rcu **ef,
2867 struct dma_fence *new_ef)
2868{
2869 struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true
2870 /* protected by process_info->lock */);
2871
2872 /* If we're replacing an unsignaled eviction fence, that fence will
2873 * never be signaled, and if anyone is still waiting on that fence,
2874 * they will hang forever. This should never happen. We should only
2875 * replace the fence in restore_work that only gets scheduled after
2876 * eviction work signaled the fence.
2877 */
2878 WARN_ONCE(!dma_fence_is_signaled(old_ef),
2879 "Replacing unsignaled eviction fence");
2880 dma_fence_put(old_ef);
2881}
2882
2883/** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2884 * KFD process identified by process_info
2885 *
2886 * @process_info: amdkfd_process_info of the KFD process
2887 *
2888 * After memory eviction, restore thread calls this function. The function
2889 * should be called when the Process is still valid. BO restore involves -
2890 *
2891 * 1. Release old eviction fence and create new one
2892 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2893 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2894 * BOs that need to be reserved.
2895 * 4. Reserve all the BOs
2896 * 5. Validate of PD and PT BOs.
2897 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2898 * 7. Add fence to all PD and PT BOs.
2899 * 8. Unreserve all BOs
2900 */
2901int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu **ef)
2902{
2903 struct amdkfd_process_info *process_info = info;
2904 struct amdgpu_vm *peer_vm;
2905 struct kgd_mem *mem;
2906 struct list_head duplicate_save;
2907 struct amdgpu_sync sync_obj;
2908 unsigned long failed_size = 0;
2909 unsigned long total_size = 0;
2910 struct drm_exec exec;
2911 int ret;
2912
2913 INIT_LIST_HEAD(&duplicate_save);
2914
2915 mutex_lock(&process_info->lock);
2916
2917 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
2918 drm_exec_until_all_locked(&exec) {
2919 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2920 vm_list_node) {
2921 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2922 drm_exec_retry_on_contention(&exec);
2923 if (unlikely(ret)) {
2924 pr_err("Locking VM PD failed, ret: %d\n", ret);
2925 goto ttm_reserve_fail;
2926 }
2927 }
2928
2929 /* Reserve all BOs and page tables/directory. Add all BOs from
2930 * kfd_bo_list to ctx.list
2931 */
2932 list_for_each_entry(mem, &process_info->kfd_bo_list,
2933 validate_list) {
2934 struct drm_gem_object *gobj;
2935
2936 gobj = &mem->bo->tbo.base;
2937 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2938 drm_exec_retry_on_contention(&exec);
2939 if (unlikely(ret)) {
2940 pr_err("drm_exec_prepare_obj failed, ret: %d\n", ret);
2941 goto ttm_reserve_fail;
2942 }
2943 }
2944 }
2945
2946 amdgpu_sync_create(&sync_obj);
2947
2948 /* Validate BOs managed by KFD */
2949 list_for_each_entry(mem, &process_info->kfd_bo_list,
2950 validate_list) {
2951
2952 struct amdgpu_bo *bo = mem->bo;
2953 uint32_t domain = mem->domain;
2954 struct dma_resv_iter cursor;
2955 struct dma_fence *fence;
2956
2957 total_size += amdgpu_bo_size(bo);
2958
2959 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2960 if (ret) {
2961 pr_debug("Memory eviction: Validate BOs failed\n");
2962 failed_size += amdgpu_bo_size(bo);
2963 ret = amdgpu_amdkfd_bo_validate(bo,
2964 AMDGPU_GEM_DOMAIN_GTT, false);
2965 if (ret) {
2966 pr_debug("Memory eviction: Try again\n");
2967 goto validate_map_fail;
2968 }
2969 }
2970 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2971 DMA_RESV_USAGE_KERNEL, fence) {
2972 ret = amdgpu_sync_fence(&sync_obj, fence);
2973 if (ret) {
2974 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2975 goto validate_map_fail;
2976 }
2977 }
2978 }
2979
2980 if (failed_size)
2981 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2982
2983 /* Validate PDs, PTs and evicted DMABuf imports last. Otherwise BO
2984 * validations above would invalidate DMABuf imports again.
2985 */
2986 ret = process_validate_vms(process_info, &exec.ticket);
2987 if (ret) {
2988 pr_debug("Validating VMs failed, ret: %d\n", ret);
2989 goto validate_map_fail;
2990 }
2991
2992 /* Update mappings managed by KFD. */
2993 list_for_each_entry(mem, &process_info->kfd_bo_list,
2994 validate_list) {
2995 struct kfd_mem_attachment *attachment;
2996
2997 list_for_each_entry(attachment, &mem->attachments, list) {
2998 if (!attachment->is_mapped)
2999 continue;
3000
3001 kfd_mem_dmaunmap_attachment(mem, attachment);
3002 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
3003 if (ret) {
3004 pr_debug("Memory eviction: update PTE failed. Try again\n");
3005 goto validate_map_fail;
3006 }
3007 }
3008 }
3009
3010 /* Update mappings not managed by KFD */
3011 list_for_each_entry(peer_vm, &process_info->vm_list_head,
3012 vm_list_node) {
3013 struct amdgpu_device *adev = amdgpu_ttm_adev(
3014 peer_vm->root.bo->tbo.bdev);
3015
3016 ret = amdgpu_vm_handle_moved(adev, peer_vm, &exec.ticket);
3017 if (ret) {
3018 pr_debug("Memory eviction: handle moved failed. Try again\n");
3019 goto validate_map_fail;
3020 }
3021 }
3022
3023 /* Update page directories */
3024 ret = process_update_pds(process_info, &sync_obj);
3025 if (ret) {
3026 pr_debug("Memory eviction: update PDs failed. Try again\n");
3027 goto validate_map_fail;
3028 }
3029
3030 /* Sync with fences on all the page tables. They implicitly depend on any
3031 * move fences from amdgpu_vm_handle_moved above.
3032 */
3033 ret = process_sync_pds_resv(process_info, &sync_obj);
3034 if (ret) {
3035 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
3036 goto validate_map_fail;
3037 }
3038
3039 /* Wait for validate and PT updates to finish */
3040 amdgpu_sync_wait(&sync_obj, false);
3041
3042 /* The old eviction fence may be unsignaled if restore happens
3043 * after a GPU reset or suspend/resume. Keep the old fence in that
3044 * case. Otherwise release the old eviction fence and create new
3045 * one, because fence only goes from unsignaled to signaled once
3046 * and cannot be reused. Use context and mm from the old fence.
3047 *
3048 * If an old eviction fence signals after this check, that's OK.
3049 * Anyone signaling an eviction fence must stop the queues first
3050 * and schedule another restore worker.
3051 */
3052 if (dma_fence_is_signaled(&process_info->eviction_fence->base)) {
3053 struct amdgpu_amdkfd_fence *new_fence =
3054 amdgpu_amdkfd_fence_create(
3055 process_info->eviction_fence->base.context,
3056 process_info->eviction_fence->mm,
3057 NULL);
3058
3059 if (!new_fence) {
3060 pr_err("Failed to create eviction fence\n");
3061 ret = -ENOMEM;
3062 goto validate_map_fail;
3063 }
3064 dma_fence_put(&process_info->eviction_fence->base);
3065 process_info->eviction_fence = new_fence;
3066 replace_eviction_fence(ef, dma_fence_get(&new_fence->base));
3067 } else {
3068 WARN_ONCE(*ef != &process_info->eviction_fence->base,
3069 "KFD eviction fence doesn't match KGD process_info");
3070 }
3071
3072 /* Attach new eviction fence to all BOs except pinned ones */
3073 list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
3074 if (mem->bo->tbo.pin_count)
3075 continue;
3076
3077 dma_resv_add_fence(mem->bo->tbo.base.resv,
3078 &process_info->eviction_fence->base,
3079 DMA_RESV_USAGE_BOOKKEEP);
3080 }
3081 /* Attach eviction fence to PD / PT BOs and DMABuf imports */
3082 list_for_each_entry(peer_vm, &process_info->vm_list_head,
3083 vm_list_node) {
3084 struct amdgpu_bo *bo = peer_vm->root.bo;
3085
3086 dma_resv_add_fence(bo->tbo.base.resv,
3087 &process_info->eviction_fence->base,
3088 DMA_RESV_USAGE_BOOKKEEP);
3089 }
3090
3091validate_map_fail:
3092 amdgpu_sync_free(&sync_obj);
3093ttm_reserve_fail:
3094 drm_exec_fini(&exec);
3095 mutex_unlock(&process_info->lock);
3096 return ret;
3097}
3098
3099int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
3100{
3101 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3102 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
3103 int ret;
3104
3105 if (!info || !gws)
3106 return -EINVAL;
3107
3108 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
3109 if (!*mem)
3110 return -ENOMEM;
3111
3112 mutex_init(&(*mem)->lock);
3113 INIT_LIST_HEAD(&(*mem)->attachments);
3114 (*mem)->bo = amdgpu_bo_ref(gws_bo);
3115 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
3116 (*mem)->process_info = process_info;
3117 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
3118 amdgpu_sync_create(&(*mem)->sync);
3119
3120
3121 /* Validate gws bo the first time it is added to process */
3122 mutex_lock(&(*mem)->process_info->lock);
3123 ret = amdgpu_bo_reserve(gws_bo, false);
3124 if (unlikely(ret)) {
3125 pr_err("Reserve gws bo failed %d\n", ret);
3126 goto bo_reservation_failure;
3127 }
3128
3129 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
3130 if (ret) {
3131 pr_err("GWS BO validate failed %d\n", ret);
3132 goto bo_validation_failure;
3133 }
3134 /* GWS resource is shared b/t amdgpu and amdkfd
3135 * Add process eviction fence to bo so they can
3136 * evict each other.
3137 */
3138 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
3139 if (ret)
3140 goto reserve_shared_fail;
3141 dma_resv_add_fence(gws_bo->tbo.base.resv,
3142 &process_info->eviction_fence->base,
3143 DMA_RESV_USAGE_BOOKKEEP);
3144 amdgpu_bo_unreserve(gws_bo);
3145 mutex_unlock(&(*mem)->process_info->lock);
3146
3147 return ret;
3148
3149reserve_shared_fail:
3150bo_validation_failure:
3151 amdgpu_bo_unreserve(gws_bo);
3152bo_reservation_failure:
3153 mutex_unlock(&(*mem)->process_info->lock);
3154 amdgpu_sync_free(&(*mem)->sync);
3155 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
3156 amdgpu_bo_unref(&gws_bo);
3157 mutex_destroy(&(*mem)->lock);
3158 kfree(*mem);
3159 *mem = NULL;
3160 return ret;
3161}
3162
3163int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
3164{
3165 int ret;
3166 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3167 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
3168 struct amdgpu_bo *gws_bo = kgd_mem->bo;
3169
3170 /* Remove BO from process's validate list so restore worker won't touch
3171 * it anymore
3172 */
3173 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
3174
3175 ret = amdgpu_bo_reserve(gws_bo, false);
3176 if (unlikely(ret)) {
3177 pr_err("Reserve gws bo failed %d\n", ret);
3178 //TODO add BO back to validate_list?
3179 return ret;
3180 }
3181 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
3182 process_info->eviction_fence);
3183 amdgpu_bo_unreserve(gws_bo);
3184 amdgpu_sync_free(&kgd_mem->sync);
3185 amdgpu_bo_unref(&gws_bo);
3186 mutex_destroy(&kgd_mem->lock);
3187 kfree(mem);
3188 return 0;
3189}
3190
3191/* Returns GPU-specific tiling mode information */
3192int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
3193 struct tile_config *config)
3194{
3195 config->gb_addr_config = adev->gfx.config.gb_addr_config;
3196 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
3197 config->num_tile_configs =
3198 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
3199 config->macro_tile_config_ptr =
3200 adev->gfx.config.macrotile_mode_array;
3201 config->num_macro_tile_configs =
3202 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
3203
3204 /* Those values are not set from GFX9 onwards */
3205 config->num_banks = adev->gfx.config.num_banks;
3206 config->num_ranks = adev->gfx.config.num_ranks;
3207
3208 return 0;
3209}
3210
3211bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem)
3212{
3213 struct amdgpu_vm *vm = drm_priv_to_vm(drm_priv);
3214 struct kfd_mem_attachment *entry;
3215
3216 list_for_each_entry(entry, &mem->attachments, list) {
3217 if (entry->is_mapped && entry->bo_va->base.vm == vm)
3218 return true;
3219 }
3220 return false;
3221}
3222
3223#if defined(CONFIG_DEBUG_FS)
3224
3225int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3226{
3227
3228 spin_lock(&kfd_mem_limit.mem_limit_lock);
3229 seq_printf(m, "System mem used %lldM out of %lluM\n",
3230 (kfd_mem_limit.system_mem_used >> 20),
3231 (kfd_mem_limit.max_system_mem_limit >> 20));
3232 seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3233 (kfd_mem_limit.ttm_mem_used >> 20),
3234 (kfd_mem_limit.max_ttm_mem_limit >> 20));
3235 spin_unlock(&kfd_mem_limit.mem_limit_lock);
3236
3237 return 0;
3238}
3239
3240#endif