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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DC_HW_SEQUENCER_H__
27#define __DC_HW_SEQUENCER_H__
28#include "dc_types.h"
29#include "clock_source.h"
30#include "inc/hw/timing_generator.h"
31#include "inc/hw/opp.h"
32#include "inc/hw/link_encoder.h"
33#include "core_status.h"
34
35enum pipe_gating_control {
36 PIPE_GATING_CONTROL_DISABLE = 0,
37 PIPE_GATING_CONTROL_ENABLE,
38 PIPE_GATING_CONTROL_INIT
39};
40
41enum vline_select {
42 VLINE0,
43 VLINE1
44};
45
46struct dce_hwseq_wa {
47 bool blnd_crtc_trigger;
48 bool DEGVIDCN10_253;
49 bool false_optc_underflow;
50 bool DEGVIDCN10_254;
51 bool DEGVIDCN21;
52};
53
54struct hwseq_wa_state {
55 bool DEGVIDCN10_253_applied;
56};
57
58struct dce_hwseq {
59 struct dc_context *ctx;
60 const struct dce_hwseq_registers *regs;
61 const struct dce_hwseq_shift *shifts;
62 const struct dce_hwseq_mask *masks;
63 struct dce_hwseq_wa wa;
64 struct hwseq_wa_state wa_state;
65};
66
67struct pipe_ctx;
68struct dc_state;
69#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
70struct dc_stream_status;
71struct dc_writeback_info;
72#endif
73struct dchub_init_data;
74struct dc_static_screen_events;
75struct resource_pool;
76struct resource_context;
77struct stream_resource;
78#ifdef CONFIG_DRM_AMD_DC_DCN2_0
79struct dc_phy_addr_space_config;
80struct dc_virtual_addr_space_config;
81#endif
82struct hubp;
83struct dpp;
84
85struct hw_sequencer_funcs {
86
87 void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
88
89 void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
90
91 void (*init_hw)(struct dc *dc);
92
93 void (*init_pipes)(struct dc *dc, struct dc_state *context);
94
95 enum dc_status (*apply_ctx_to_hw)(
96 struct dc *dc, struct dc_state *context);
97
98 void (*reset_hw_ctx_wrap)(
99 struct dc *dc, struct dc_state *context);
100
101 void (*apply_ctx_for_surface)(
102 struct dc *dc,
103 const struct dc_stream_state *stream,
104 int num_planes,
105 struct dc_state *context);
106
107 void (*program_gamut_remap)(
108 struct pipe_ctx *pipe_ctx);
109
110 void (*program_output_csc)(struct dc *dc,
111 struct pipe_ctx *pipe_ctx,
112 enum dc_color_space colorspace,
113 uint16_t *matrix,
114 int opp_id);
115
116#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
117 void (*program_triplebuffer)(
118 const struct dc *dc,
119 struct pipe_ctx *pipe_ctx,
120 bool enableTripleBuffer);
121 void (*set_flip_control_gsl)(
122 struct pipe_ctx *pipe_ctx,
123 bool flip_immediate);
124#endif
125
126 void (*update_plane_addr)(
127 const struct dc *dc,
128 struct pipe_ctx *pipe_ctx);
129
130 void (*plane_atomic_disconnect)(
131 struct dc *dc,
132 struct pipe_ctx *pipe_ctx);
133
134 void (*update_dchub)(
135 struct dce_hwseq *hws,
136 struct dchub_init_data *dh_data);
137
138#ifdef CONFIG_DRM_AMD_DC_DCN2_0
139 int (*init_sys_ctx)(
140 struct dce_hwseq *hws,
141 struct dc *dc,
142 struct dc_phy_addr_space_config *pa_config);
143 void (*init_vm_ctx)(
144 struct dce_hwseq *hws,
145 struct dc *dc,
146 struct dc_virtual_addr_space_config *va_config,
147 int vmid);
148#endif
149 void (*update_mpcc)(
150 struct dc *dc,
151 struct pipe_ctx *pipe_ctx);
152
153 void (*update_pending_status)(
154 struct pipe_ctx *pipe_ctx);
155
156 bool (*set_input_transfer_func)(
157 struct pipe_ctx *pipe_ctx,
158 const struct dc_plane_state *plane_state);
159
160 bool (*set_output_transfer_func)(
161 struct pipe_ctx *pipe_ctx,
162 const struct dc_stream_state *stream);
163
164 void (*power_down)(struct dc *dc);
165
166 void (*enable_accelerated_mode)(struct dc *dc, struct dc_state *context);
167
168 void (*enable_timing_synchronization)(
169 struct dc *dc,
170 int group_index,
171 int group_size,
172 struct pipe_ctx *grouped_pipes[]);
173
174 void (*enable_per_frame_crtc_position_reset)(
175 struct dc *dc,
176 int group_size,
177 struct pipe_ctx *grouped_pipes[]);
178
179 void (*enable_display_pipe_clock_gating)(
180 struct dc_context *ctx,
181 bool clock_gating);
182
183 bool (*enable_display_power_gating)(
184 struct dc *dc,
185 uint8_t controller_id,
186 struct dc_bios *dcb,
187 enum pipe_gating_control power_gating);
188
189 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx);
190
191 void (*update_info_frame)(struct pipe_ctx *pipe_ctx);
192
193 void (*send_immediate_sdp_message)(
194 struct pipe_ctx *pipe_ctx,
195 const uint8_t *custom_sdp_message,
196 unsigned int sdp_message_size);
197
198 void (*enable_stream)(struct pipe_ctx *pipe_ctx);
199
200 void (*disable_stream)(struct pipe_ctx *pipe_ctx);
201
202 void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
203 struct dc_link_settings *link_settings);
204
205 void (*blank_stream)(struct pipe_ctx *pipe_ctx);
206
207 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
208
209 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
210
211 void (*pipe_control_lock)(
212 struct dc *dc,
213 struct pipe_ctx *pipe,
214 bool lock);
215
216 void (*pipe_control_lock_global)(
217 struct dc *dc,
218 struct pipe_ctx *pipe,
219 bool lock);
220 void (*blank_pixel_data)(
221 struct dc *dc,
222 struct pipe_ctx *pipe_ctx,
223 bool blank);
224
225 void (*prepare_bandwidth)(
226 struct dc *dc,
227 struct dc_state *context);
228 void (*optimize_bandwidth)(
229 struct dc *dc,
230 struct dc_state *context);
231
232#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
233 bool (*update_bandwidth)(
234 struct dc *dc,
235 struct dc_state *context);
236 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
237 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
238#endif
239
240 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
241 unsigned int vmin, unsigned int vmax,
242 unsigned int vmid, unsigned int vmid_frame_number);
243
244 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
245 struct crtc_position *position);
246
247 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
248 int num_pipes, const struct dc_static_screen_events *events);
249
250 enum dc_status (*enable_stream_timing)(
251 struct pipe_ctx *pipe_ctx,
252 struct dc_state *context,
253 struct dc *dc);
254
255 void (*setup_stereo)(
256 struct pipe_ctx *pipe_ctx,
257 struct dc *dc);
258
259 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable);
260
261 void (*log_hw_state)(struct dc *dc,
262 struct dc_log_buffer_ctx *log_ctx);
263 void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask);
264 void (*clear_status_bits)(struct dc *dc, unsigned int mask);
265
266 void (*wait_for_mpcc_disconnect)(struct dc *dc,
267 struct resource_pool *res_pool,
268 struct pipe_ctx *pipe_ctx);
269
270 void (*edp_power_control)(
271 struct dc_link *link,
272 bool enable);
273 void (*edp_backlight_control)(
274 struct dc_link *link,
275 bool enable);
276 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
277
278 void (*set_cursor_position)(struct pipe_ctx *pipe);
279 void (*set_cursor_attribute)(struct pipe_ctx *pipe);
280 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
281
282 void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
283 void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
284 bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
285
286 void (*init_blank)(struct dc *dc, struct timing_generator *tg);
287 void (*disable_vga)(struct dce_hwseq *hws);
288 void (*bios_golden_init)(struct dc *dc);
289 void (*plane_atomic_power_down)(struct dc *dc,
290 struct dpp *dpp,
291 struct hubp *hubp);
292
293 void (*plane_atomic_disable)(
294 struct dc *dc, struct pipe_ctx *pipe_ctx);
295
296 void (*enable_power_gating_plane)(
297 struct dce_hwseq *hws,
298 bool enable);
299
300 void (*dpp_pg_control)(
301 struct dce_hwseq *hws,
302 unsigned int dpp_inst,
303 bool power_on);
304
305 void (*hubp_pg_control)(
306 struct dce_hwseq *hws,
307 unsigned int hubp_inst,
308 bool power_on);
309
310 void (*dsc_pg_control)(
311 struct dce_hwseq *hws,
312 unsigned int dsc_inst,
313 bool power_on);
314
315
316#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
317 void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
318 void (*program_all_writeback_pipes_in_tree)(
319 struct dc *dc,
320 const struct dc_stream_state *stream,
321 struct dc_state *context);
322 void (*update_writeback)(struct dc *dc,
323 const struct dc_stream_status *stream_status,
324 struct dc_writeback_info *wb_info);
325 void (*enable_writeback)(struct dc *dc,
326 const struct dc_stream_status *stream_status,
327 struct dc_writeback_info *wb_info);
328 void (*disable_writeback)(struct dc *dc,
329 unsigned int dwb_pipe_inst);
330#endif
331 enum dc_status (*set_clock)(struct dc *dc,
332 enum dc_clock_type clock_type,
333 uint32_t clk_khz,
334 uint32_t stepping);
335
336 void (*get_clock)(struct dc *dc,
337 enum dc_clock_type clock_type,
338 struct dc_clock_config *clock_cfg);
339
340};
341
342void color_space_to_black_color(
343 const struct dc *dc,
344 enum dc_color_space colorspace,
345 struct tg_color *black_color);
346
347bool hwss_wait_for_blank_complete(
348 struct timing_generator *tg);
349
350const uint16_t *find_color_matrix(
351 enum dc_color_space color_space,
352 uint32_t *array_size);
353
354#endif /* __DC_HW_SEQUENCER_H__ */