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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include <linux/dma-buf.h>
24#include <linux/list.h>
25#include <linux/pagemap.h>
26#include <linux/sched/mm.h>
27#include <linux/sched/task.h>
28#include <linux/fdtable.h>
29#include <drm/ttm/ttm_tt.h>
30
31#include <drm/drm_exec.h>
32
33#include "amdgpu_object.h"
34#include "amdgpu_gem.h"
35#include "amdgpu_vm.h"
36#include "amdgpu_hmm.h"
37#include "amdgpu_amdkfd.h"
38#include "amdgpu_dma_buf.h"
39#include <uapi/linux/kfd_ioctl.h>
40#include "amdgpu_xgmi.h"
41#include "kfd_priv.h"
42#include "kfd_smi_events.h"
43
44/* Userptr restore delay, just long enough to allow consecutive VM
45 * changes to accumulate
46 */
47#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
48#define AMDGPU_RESERVE_MEM_LIMIT (3UL << 29)
49
50/*
51 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
52 * BO chunk
53 */
54#define VRAM_AVAILABLITY_ALIGN (1 << 21)
55
56/* Impose limit on how much memory KFD can use */
57static struct {
58 uint64_t max_system_mem_limit;
59 uint64_t max_ttm_mem_limit;
60 int64_t system_mem_used;
61 int64_t ttm_mem_used;
62 spinlock_t mem_limit_lock;
63} kfd_mem_limit;
64
65static const char * const domain_bit_to_string[] = {
66 "CPU",
67 "GTT",
68 "VRAM",
69 "GDS",
70 "GWS",
71 "OA"
72};
73
74#define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
75
76static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
77
78static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
79 struct kgd_mem *mem)
80{
81 struct kfd_mem_attachment *entry;
82
83 list_for_each_entry(entry, &mem->attachments, list)
84 if (entry->bo_va->base.vm == avm)
85 return true;
86
87 return false;
88}
89
90/**
91 * reuse_dmamap() - Check whether adev can share the original
92 * userptr BO
93 *
94 * If both adev and bo_adev are in direct mapping or
95 * in the same iommu group, they can share the original BO.
96 *
97 * @adev: Device to which can or cannot share the original BO
98 * @bo_adev: Device to which allocated BO belongs to
99 *
100 * Return: returns true if adev can share original userptr BO,
101 * false otherwise.
102 */
103static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
104{
105 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
106 (adev->dev->iommu_group == bo_adev->dev->iommu_group);
107}
108
109/* Set memory usage limits. Current, limits are
110 * System (TTM + userptr) memory - 15/16th System RAM
111 * TTM memory - 3/8th System RAM
112 */
113void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
114{
115 struct sysinfo si;
116 uint64_t mem;
117
118 if (kfd_mem_limit.max_system_mem_limit)
119 return;
120
121 si_meminfo(&si);
122 mem = si.totalram - si.totalhigh;
123 mem *= si.mem_unit;
124
125 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
126 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6);
127 if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT)
128 kfd_mem_limit.max_system_mem_limit >>= 1;
129 else
130 kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT;
131
132 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
133 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
134 (kfd_mem_limit.max_system_mem_limit >> 20),
135 (kfd_mem_limit.max_ttm_mem_limit >> 20));
136}
137
138void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
139{
140 kfd_mem_limit.system_mem_used += size;
141}
142
143/* Estimate page table size needed to represent a given memory size
144 *
145 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
146 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
147 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
148 * for 2MB pages for TLB efficiency. However, small allocations and
149 * fragmented system memory still need some 4KB pages. We choose a
150 * compromise that should work in most cases without reserving too
151 * much memory for page tables unnecessarily (factor 16K, >> 14).
152 */
153
154#define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
155
156/**
157 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
158 * of buffer.
159 *
160 * @adev: Device to which allocated BO belongs to
161 * @size: Size of buffer, in bytes, encapsulated by B0. This should be
162 * equivalent to amdgpu_bo_size(BO)
163 * @alloc_flag: Flag used in allocating a BO as noted above
164 * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
165 * managed as one compute node in driver for app
166 *
167 * Return:
168 * returns -ENOMEM in case of error, ZERO otherwise
169 */
170int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
171 uint64_t size, u32 alloc_flag, int8_t xcp_id)
172{
173 uint64_t reserved_for_pt =
174 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
175 size_t system_mem_needed, ttm_mem_needed, vram_needed;
176 int ret = 0;
177 uint64_t vram_size = 0;
178
179 system_mem_needed = 0;
180 ttm_mem_needed = 0;
181 vram_needed = 0;
182 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
183 system_mem_needed = size;
184 ttm_mem_needed = size;
185 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
186 /*
187 * Conservatively round up the allocation requirement to 2 MB
188 * to avoid fragmentation caused by 4K allocations in the tail
189 * 2M BO chunk.
190 */
191 vram_needed = size;
192 /*
193 * For GFX 9.4.3, get the VRAM size from XCP structs
194 */
195 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
196 return -EINVAL;
197
198 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
199 if (adev->gmc.is_app_apu) {
200 system_mem_needed = size;
201 ttm_mem_needed = size;
202 }
203 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
204 system_mem_needed = size;
205 } else if (!(alloc_flag &
206 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
207 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
208 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
209 return -ENOMEM;
210 }
211
212 spin_lock(&kfd_mem_limit.mem_limit_lock);
213
214 if (kfd_mem_limit.system_mem_used + system_mem_needed >
215 kfd_mem_limit.max_system_mem_limit)
216 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
217
218 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
219 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
220 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
221 kfd_mem_limit.max_ttm_mem_limit) ||
222 (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
223 vram_size - reserved_for_pt - atomic64_read(&adev->vram_pin_size))) {
224 ret = -ENOMEM;
225 goto release;
226 }
227
228 /* Update memory accounting by decreasing available system
229 * memory, TTM memory and GPU memory as computed above
230 */
231 WARN_ONCE(vram_needed && !adev,
232 "adev reference can't be null when vram is used");
233 if (adev && xcp_id >= 0) {
234 adev->kfd.vram_used[xcp_id] += vram_needed;
235 adev->kfd.vram_used_aligned[xcp_id] += adev->gmc.is_app_apu ?
236 vram_needed :
237 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
238 }
239 kfd_mem_limit.system_mem_used += system_mem_needed;
240 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
241
242release:
243 spin_unlock(&kfd_mem_limit.mem_limit_lock);
244 return ret;
245}
246
247void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
248 uint64_t size, u32 alloc_flag, int8_t xcp_id)
249{
250 spin_lock(&kfd_mem_limit.mem_limit_lock);
251
252 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
253 kfd_mem_limit.system_mem_used -= size;
254 kfd_mem_limit.ttm_mem_used -= size;
255 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
256 WARN_ONCE(!adev,
257 "adev reference can't be null when alloc mem flags vram is set");
258 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
259 goto release;
260
261 if (adev) {
262 adev->kfd.vram_used[xcp_id] -= size;
263 if (adev->gmc.is_app_apu) {
264 adev->kfd.vram_used_aligned[xcp_id] -= size;
265 kfd_mem_limit.system_mem_used -= size;
266 kfd_mem_limit.ttm_mem_used -= size;
267 } else {
268 adev->kfd.vram_used_aligned[xcp_id] -=
269 ALIGN(size, VRAM_AVAILABLITY_ALIGN);
270 }
271 }
272 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
273 kfd_mem_limit.system_mem_used -= size;
274 } else if (!(alloc_flag &
275 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
276 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
277 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
278 goto release;
279 }
280 WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
281 "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
282 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
283 "KFD TTM memory accounting unbalanced");
284 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
285 "KFD system memory accounting unbalanced");
286
287release:
288 spin_unlock(&kfd_mem_limit.mem_limit_lock);
289}
290
291void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
292{
293 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
294 u32 alloc_flags = bo->kfd_bo->alloc_flags;
295 u64 size = amdgpu_bo_size(bo);
296
297 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
298 bo->xcp_id);
299
300 kfree(bo->kfd_bo);
301}
302
303/**
304 * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
305 * about USERPTR or DOOREBELL or MMIO BO.
306 *
307 * @adev: Device for which dmamap BO is being created
308 * @mem: BO of peer device that is being DMA mapped. Provides parameters
309 * in building the dmamap BO
310 * @bo_out: Output parameter updated with handle of dmamap BO
311 */
312static int
313create_dmamap_sg_bo(struct amdgpu_device *adev,
314 struct kgd_mem *mem, struct amdgpu_bo **bo_out)
315{
316 struct drm_gem_object *gem_obj;
317 int ret;
318 uint64_t flags = 0;
319
320 ret = amdgpu_bo_reserve(mem->bo, false);
321 if (ret)
322 return ret;
323
324 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
325 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
326 AMDGPU_GEM_CREATE_UNCACHED);
327
328 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
329 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
330 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
331
332 amdgpu_bo_unreserve(mem->bo);
333
334 if (ret) {
335 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
336 return -EINVAL;
337 }
338
339 *bo_out = gem_to_amdgpu_bo(gem_obj);
340 (*bo_out)->parent = amdgpu_bo_ref(mem->bo);
341 return ret;
342}
343
344/* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
345 * reservation object.
346 *
347 * @bo: [IN] Remove eviction fence(s) from this BO
348 * @ef: [IN] This eviction fence is removed if it
349 * is present in the shared list.
350 *
351 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
352 */
353static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
354 struct amdgpu_amdkfd_fence *ef)
355{
356 struct dma_fence *replacement;
357
358 if (!ef)
359 return -EINVAL;
360
361 /* TODO: Instead of block before we should use the fence of the page
362 * table update and TLB flush here directly.
363 */
364 replacement = dma_fence_get_stub();
365 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
366 replacement, DMA_RESV_USAGE_BOOKKEEP);
367 dma_fence_put(replacement);
368 return 0;
369}
370
371int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
372{
373 struct amdgpu_bo *root = bo;
374 struct amdgpu_vm_bo_base *vm_bo;
375 struct amdgpu_vm *vm;
376 struct amdkfd_process_info *info;
377 struct amdgpu_amdkfd_fence *ef;
378 int ret;
379
380 /* we can always get vm_bo from root PD bo.*/
381 while (root->parent)
382 root = root->parent;
383
384 vm_bo = root->vm_bo;
385 if (!vm_bo)
386 return 0;
387
388 vm = vm_bo->vm;
389 if (!vm)
390 return 0;
391
392 info = vm->process_info;
393 if (!info || !info->eviction_fence)
394 return 0;
395
396 ef = container_of(dma_fence_get(&info->eviction_fence->base),
397 struct amdgpu_amdkfd_fence, base);
398
399 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
400 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
401 dma_resv_unlock(bo->tbo.base.resv);
402
403 dma_fence_put(&ef->base);
404 return ret;
405}
406
407static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
408 bool wait)
409{
410 struct ttm_operation_ctx ctx = { false, false };
411 int ret;
412
413 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
414 "Called with userptr BO"))
415 return -EINVAL;
416
417 amdgpu_bo_placement_from_domain(bo, domain);
418
419 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
420 if (ret)
421 goto validate_fail;
422 if (wait)
423 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
424
425validate_fail:
426 return ret;
427}
428
429int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
430 uint32_t domain,
431 struct dma_fence *fence)
432{
433 int ret = amdgpu_bo_reserve(bo, false);
434
435 if (ret)
436 return ret;
437
438 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
439 if (ret)
440 goto unreserve_out;
441
442 ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
443 if (ret)
444 goto unreserve_out;
445
446 dma_resv_add_fence(bo->tbo.base.resv, fence,
447 DMA_RESV_USAGE_BOOKKEEP);
448
449unreserve_out:
450 amdgpu_bo_unreserve(bo);
451
452 return ret;
453}
454
455static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
456{
457 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
458}
459
460/* vm_validate_pt_pd_bos - Validate page table and directory BOs
461 *
462 * Page directories are not updated here because huge page handling
463 * during page table updates can invalidate page directory entries
464 * again. Page directories are only updated after updating page
465 * tables.
466 */
467static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm,
468 struct ww_acquire_ctx *ticket)
469{
470 struct amdgpu_bo *pd = vm->root.bo;
471 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
472 int ret;
473
474 ret = amdgpu_vm_validate(adev, vm, ticket,
475 amdgpu_amdkfd_validate_vm_bo, NULL);
476 if (ret) {
477 pr_err("failed to validate PT BOs\n");
478 return ret;
479 }
480
481 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
482
483 return 0;
484}
485
486static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
487{
488 struct amdgpu_bo *pd = vm->root.bo;
489 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
490 int ret;
491
492 ret = amdgpu_vm_update_pdes(adev, vm, false);
493 if (ret)
494 return ret;
495
496 return amdgpu_sync_fence(sync, vm->last_update);
497}
498
499static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
500{
501 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
502 AMDGPU_VM_MTYPE_DEFAULT;
503
504 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
505 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
506 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
507 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
508
509 return amdgpu_gem_va_map_flags(adev, mapping_flags);
510}
511
512/**
513 * create_sg_table() - Create an sg_table for a contiguous DMA addr range
514 * @addr: The starting address to point to
515 * @size: Size of memory area in bytes being pointed to
516 *
517 * Allocates an instance of sg_table and initializes it to point to memory
518 * area specified by input parameters. The address used to build is assumed
519 * to be DMA mapped, if needed.
520 *
521 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
522 * because they are physically contiguous.
523 *
524 * Return: Initialized instance of SG Table or NULL
525 */
526static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
527{
528 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
529
530 if (!sg)
531 return NULL;
532 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
533 kfree(sg);
534 return NULL;
535 }
536 sg_dma_address(sg->sgl) = addr;
537 sg->sgl->length = size;
538#ifdef CONFIG_NEED_SG_DMA_LENGTH
539 sg->sgl->dma_length = size;
540#endif
541 return sg;
542}
543
544static int
545kfd_mem_dmamap_userptr(struct kgd_mem *mem,
546 struct kfd_mem_attachment *attachment)
547{
548 enum dma_data_direction direction =
549 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
550 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
551 struct ttm_operation_ctx ctx = {.interruptible = true};
552 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
553 struct amdgpu_device *adev = attachment->adev;
554 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
555 struct ttm_tt *ttm = bo->tbo.ttm;
556 int ret;
557
558 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
559 return -EINVAL;
560
561 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
562 if (unlikely(!ttm->sg))
563 return -ENOMEM;
564
565 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
566 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
567 ttm->num_pages, 0,
568 (u64)ttm->num_pages << PAGE_SHIFT,
569 GFP_KERNEL);
570 if (unlikely(ret))
571 goto free_sg;
572
573 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
574 if (unlikely(ret))
575 goto release_sg;
576
577 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
578 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
579 if (ret)
580 goto unmap_sg;
581
582 return 0;
583
584unmap_sg:
585 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
586release_sg:
587 pr_err("DMA map userptr failed: %d\n", ret);
588 sg_free_table(ttm->sg);
589free_sg:
590 kfree(ttm->sg);
591 ttm->sg = NULL;
592 return ret;
593}
594
595static int
596kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
597{
598 struct ttm_operation_ctx ctx = {.interruptible = true};
599 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
600 int ret;
601
602 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
603 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
604 if (ret)
605 return ret;
606
607 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
608 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
609}
610
611/**
612 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
613 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
614 * @attachment: Virtual address attachment of the BO on accessing device
615 *
616 * An access request from the device that owns DOORBELL does not require DMA mapping.
617 * This is because the request doesn't go through PCIe root complex i.e. it instead
618 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
619 *
620 * In contrast, all access requests for MMIO need to be DMA mapped without regard to
621 * device ownership. This is because access requests for MMIO go through PCIe root
622 * complex.
623 *
624 * This is accomplished in two steps:
625 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
626 * in updating requesting device's page table
627 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU
628 * accessible. This allows an update of requesting device's page table
629 * with entries associated with DOOREBELL or MMIO memory
630 *
631 * This method is invoked in the following contexts:
632 * - Mapping of DOORBELL or MMIO BO of same or peer device
633 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access
634 *
635 * Return: ZERO if successful, NON-ZERO otherwise
636 */
637static int
638kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
639 struct kfd_mem_attachment *attachment)
640{
641 struct ttm_operation_ctx ctx = {.interruptible = true};
642 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
643 struct amdgpu_device *adev = attachment->adev;
644 struct ttm_tt *ttm = bo->tbo.ttm;
645 enum dma_data_direction dir;
646 dma_addr_t dma_addr;
647 bool mmio;
648 int ret;
649
650 /* Expect SG Table of dmapmap BO to be NULL */
651 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
652 if (unlikely(ttm->sg)) {
653 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
654 return -EINVAL;
655 }
656
657 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
658 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
659 dma_addr = mem->bo->tbo.sg->sgl->dma_address;
660 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
661 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
662 dma_addr = dma_map_resource(adev->dev, dma_addr,
663 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
664 ret = dma_mapping_error(adev->dev, dma_addr);
665 if (unlikely(ret))
666 return ret;
667 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
668
669 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
670 if (unlikely(!ttm->sg)) {
671 ret = -ENOMEM;
672 goto unmap_sg;
673 }
674
675 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
676 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
677 if (unlikely(ret))
678 goto free_sg;
679
680 return ret;
681
682free_sg:
683 sg_free_table(ttm->sg);
684 kfree(ttm->sg);
685 ttm->sg = NULL;
686unmap_sg:
687 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
688 dir, DMA_ATTR_SKIP_CPU_SYNC);
689 return ret;
690}
691
692static int
693kfd_mem_dmamap_attachment(struct kgd_mem *mem,
694 struct kfd_mem_attachment *attachment)
695{
696 switch (attachment->type) {
697 case KFD_MEM_ATT_SHARED:
698 return 0;
699 case KFD_MEM_ATT_USERPTR:
700 return kfd_mem_dmamap_userptr(mem, attachment);
701 case KFD_MEM_ATT_DMABUF:
702 return kfd_mem_dmamap_dmabuf(attachment);
703 case KFD_MEM_ATT_SG:
704 return kfd_mem_dmamap_sg_bo(mem, attachment);
705 default:
706 WARN_ON_ONCE(1);
707 }
708 return -EINVAL;
709}
710
711static void
712kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
713 struct kfd_mem_attachment *attachment)
714{
715 enum dma_data_direction direction =
716 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
717 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
718 struct ttm_operation_ctx ctx = {.interruptible = false};
719 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
720 struct amdgpu_device *adev = attachment->adev;
721 struct ttm_tt *ttm = bo->tbo.ttm;
722
723 if (unlikely(!ttm->sg))
724 return;
725
726 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
727 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
728
729 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
730 sg_free_table(ttm->sg);
731 kfree(ttm->sg);
732 ttm->sg = NULL;
733}
734
735static void
736kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
737{
738 /* This is a no-op. We don't want to trigger eviction fences when
739 * unmapping DMABufs. Therefore the invalidation (moving to system
740 * domain) is done in kfd_mem_dmamap_dmabuf.
741 */
742}
743
744/**
745 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
746 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
747 * @attachment: Virtual address attachment of the BO on accessing device
748 *
749 * The method performs following steps:
750 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible
751 * - Free SG Table that is used to encapsulate DMA mapped memory of
752 * peer device's DOORBELL or MMIO memory
753 *
754 * This method is invoked in the following contexts:
755 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory
756 * Eviction of DOOREBELL or MMIO BO on device having access to its memory
757 *
758 * Return: void
759 */
760static void
761kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
762 struct kfd_mem_attachment *attachment)
763{
764 struct ttm_operation_ctx ctx = {.interruptible = true};
765 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
766 struct amdgpu_device *adev = attachment->adev;
767 struct ttm_tt *ttm = bo->tbo.ttm;
768 enum dma_data_direction dir;
769
770 if (unlikely(!ttm->sg)) {
771 pr_debug("SG Table of BO is NULL");
772 return;
773 }
774
775 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
776 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
777
778 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
779 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
780 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
781 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
782 sg_free_table(ttm->sg);
783 kfree(ttm->sg);
784 ttm->sg = NULL;
785 bo->tbo.sg = NULL;
786}
787
788static void
789kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
790 struct kfd_mem_attachment *attachment)
791{
792 switch (attachment->type) {
793 case KFD_MEM_ATT_SHARED:
794 break;
795 case KFD_MEM_ATT_USERPTR:
796 kfd_mem_dmaunmap_userptr(mem, attachment);
797 break;
798 case KFD_MEM_ATT_DMABUF:
799 kfd_mem_dmaunmap_dmabuf(attachment);
800 break;
801 case KFD_MEM_ATT_SG:
802 kfd_mem_dmaunmap_sg_bo(mem, attachment);
803 break;
804 default:
805 WARN_ON_ONCE(1);
806 }
807}
808
809static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
810{
811 if (!mem->dmabuf) {
812 struct amdgpu_device *bo_adev;
813 struct dma_buf *dmabuf;
814 int r, fd;
815
816 bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
817 r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file,
818 mem->gem_handle,
819 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
820 DRM_RDWR : 0, &fd);
821 if (r)
822 return r;
823 dmabuf = dma_buf_get(fd);
824 close_fd(fd);
825 if (WARN_ON_ONCE(IS_ERR(dmabuf)))
826 return PTR_ERR(dmabuf);
827 mem->dmabuf = dmabuf;
828 }
829
830 return 0;
831}
832
833static int
834kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
835 struct amdgpu_bo **bo)
836{
837 struct drm_gem_object *gobj;
838 int ret;
839
840 ret = kfd_mem_export_dmabuf(mem);
841 if (ret)
842 return ret;
843
844 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
845 if (IS_ERR(gobj))
846 return PTR_ERR(gobj);
847
848 *bo = gem_to_amdgpu_bo(gobj);
849 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
850
851 return 0;
852}
853
854/* kfd_mem_attach - Add a BO to a VM
855 *
856 * Everything that needs to bo done only once when a BO is first added
857 * to a VM. It can later be mapped and unmapped many times without
858 * repeating these steps.
859 *
860 * 0. Create BO for DMA mapping, if needed
861 * 1. Allocate and initialize BO VA entry data structure
862 * 2. Add BO to the VM
863 * 3. Determine ASIC-specific PTE flags
864 * 4. Alloc page tables and directories if needed
865 * 4a. Validate new page tables and directories
866 */
867static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
868 struct amdgpu_vm *vm, bool is_aql)
869{
870 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
871 unsigned long bo_size = mem->bo->tbo.base.size;
872 uint64_t va = mem->va;
873 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
874 struct amdgpu_bo *bo[2] = {NULL, NULL};
875 struct amdgpu_bo_va *bo_va;
876 bool same_hive = false;
877 int i, ret;
878
879 if (!va) {
880 pr_err("Invalid VA when adding BO to VM\n");
881 return -EINVAL;
882 }
883
884 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
885 *
886 * The access path of MMIO and DOORBELL BOs of is always over PCIe.
887 * In contrast the access path of VRAM BOs depens upon the type of
888 * link that connects the peer device. Access over PCIe is allowed
889 * if peer device has large BAR. In contrast, access over xGMI is
890 * allowed for both small and large BAR configurations of peer device
891 */
892 if ((adev != bo_adev && !adev->gmc.is_app_apu) &&
893 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
894 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
895 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
896 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
897 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
898 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
899 return -EINVAL;
900 }
901
902 for (i = 0; i <= is_aql; i++) {
903 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
904 if (unlikely(!attachment[i])) {
905 ret = -ENOMEM;
906 goto unwind;
907 }
908
909 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
910 va + bo_size, vm);
911
912 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
913 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
914 (mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) ||
915 same_hive) {
916 /* Mappings on the local GPU, or VRAM mappings in the
917 * local hive, or userptr, or GTT mapping can reuse dma map
918 * address space share the original BO
919 */
920 attachment[i]->type = KFD_MEM_ATT_SHARED;
921 bo[i] = mem->bo;
922 drm_gem_object_get(&bo[i]->tbo.base);
923 } else if (i > 0) {
924 /* Multiple mappings on the same GPU share the BO */
925 attachment[i]->type = KFD_MEM_ATT_SHARED;
926 bo[i] = bo[0];
927 drm_gem_object_get(&bo[i]->tbo.base);
928 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
929 /* Create an SG BO to DMA-map userptrs on other GPUs */
930 attachment[i]->type = KFD_MEM_ATT_USERPTR;
931 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
932 if (ret)
933 goto unwind;
934 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
935 } else if (mem->bo->tbo.type == ttm_bo_type_sg) {
936 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
937 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
938 "Handing invalid SG BO in ATTACH request");
939 attachment[i]->type = KFD_MEM_ATT_SG;
940 ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
941 if (ret)
942 goto unwind;
943 /* Enable acces to GTT and VRAM BOs of peer devices */
944 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
945 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
946 attachment[i]->type = KFD_MEM_ATT_DMABUF;
947 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
948 if (ret)
949 goto unwind;
950 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
951 } else {
952 WARN_ONCE(true, "Handling invalid ATTACH request");
953 ret = -EINVAL;
954 goto unwind;
955 }
956
957 /* Add BO to VM internal data structures */
958 ret = amdgpu_bo_reserve(bo[i], false);
959 if (ret) {
960 pr_debug("Unable to reserve BO during memory attach");
961 goto unwind;
962 }
963 bo_va = amdgpu_vm_bo_find(vm, bo[i]);
964 if (!bo_va)
965 bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
966 else
967 ++bo_va->ref_count;
968 attachment[i]->bo_va = bo_va;
969 amdgpu_bo_unreserve(bo[i]);
970 if (unlikely(!attachment[i]->bo_va)) {
971 ret = -ENOMEM;
972 pr_err("Failed to add BO object to VM. ret == %d\n",
973 ret);
974 goto unwind;
975 }
976 attachment[i]->va = va;
977 attachment[i]->pte_flags = get_pte_flags(adev, mem);
978 attachment[i]->adev = adev;
979 list_add(&attachment[i]->list, &mem->attachments);
980
981 va += bo_size;
982 }
983
984 return 0;
985
986unwind:
987 for (; i >= 0; i--) {
988 if (!attachment[i])
989 continue;
990 if (attachment[i]->bo_va) {
991 amdgpu_bo_reserve(bo[i], true);
992 if (--attachment[i]->bo_va->ref_count == 0)
993 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
994 amdgpu_bo_unreserve(bo[i]);
995 list_del(&attachment[i]->list);
996 }
997 if (bo[i])
998 drm_gem_object_put(&bo[i]->tbo.base);
999 kfree(attachment[i]);
1000 }
1001 return ret;
1002}
1003
1004static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
1005{
1006 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
1007
1008 pr_debug("\t remove VA 0x%llx in entry %p\n",
1009 attachment->va, attachment);
1010 if (--attachment->bo_va->ref_count == 0)
1011 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
1012 drm_gem_object_put(&bo->tbo.base);
1013 list_del(&attachment->list);
1014 kfree(attachment);
1015}
1016
1017static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
1018 struct amdkfd_process_info *process_info,
1019 bool userptr)
1020{
1021 mutex_lock(&process_info->lock);
1022 if (userptr)
1023 list_add_tail(&mem->validate_list,
1024 &process_info->userptr_valid_list);
1025 else
1026 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
1027 mutex_unlock(&process_info->lock);
1028}
1029
1030static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
1031 struct amdkfd_process_info *process_info)
1032{
1033 mutex_lock(&process_info->lock);
1034 list_del(&mem->validate_list);
1035 mutex_unlock(&process_info->lock);
1036}
1037
1038/* Initializes user pages. It registers the MMU notifier and validates
1039 * the userptr BO in the GTT domain.
1040 *
1041 * The BO must already be on the userptr_valid_list. Otherwise an
1042 * eviction and restore may happen that leaves the new BO unmapped
1043 * with the user mode queues running.
1044 *
1045 * Takes the process_info->lock to protect against concurrent restore
1046 * workers.
1047 *
1048 * Returns 0 for success, negative errno for errors.
1049 */
1050static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1051 bool criu_resume)
1052{
1053 struct amdkfd_process_info *process_info = mem->process_info;
1054 struct amdgpu_bo *bo = mem->bo;
1055 struct ttm_operation_ctx ctx = { true, false };
1056 struct hmm_range *range;
1057 int ret = 0;
1058
1059 mutex_lock(&process_info->lock);
1060
1061 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1062 if (ret) {
1063 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1064 goto out;
1065 }
1066
1067 ret = amdgpu_hmm_register(bo, user_addr);
1068 if (ret) {
1069 pr_err("%s: Failed to register MMU notifier: %d\n",
1070 __func__, ret);
1071 goto out;
1072 }
1073
1074 if (criu_resume) {
1075 /*
1076 * During a CRIU restore operation, the userptr buffer objects
1077 * will be validated in the restore_userptr_work worker at a
1078 * later stage when it is scheduled by another ioctl called by
1079 * CRIU master process for the target pid for restore.
1080 */
1081 mutex_lock(&process_info->notifier_lock);
1082 mem->invalid++;
1083 mutex_unlock(&process_info->notifier_lock);
1084 mutex_unlock(&process_info->lock);
1085 return 0;
1086 }
1087
1088 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1089 if (ret) {
1090 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1091 goto unregister_out;
1092 }
1093
1094 ret = amdgpu_bo_reserve(bo, true);
1095 if (ret) {
1096 pr_err("%s: Failed to reserve BO\n", __func__);
1097 goto release_out;
1098 }
1099 amdgpu_bo_placement_from_domain(bo, mem->domain);
1100 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1101 if (ret)
1102 pr_err("%s: failed to validate BO\n", __func__);
1103 amdgpu_bo_unreserve(bo);
1104
1105release_out:
1106 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1107unregister_out:
1108 if (ret)
1109 amdgpu_hmm_unregister(bo);
1110out:
1111 mutex_unlock(&process_info->lock);
1112 return ret;
1113}
1114
1115/* Reserving a BO and its page table BOs must happen atomically to
1116 * avoid deadlocks. Some operations update multiple VMs at once. Track
1117 * all the reservation info in a context structure. Optionally a sync
1118 * object can track VM updates.
1119 */
1120struct bo_vm_reservation_context {
1121 /* DRM execution context for the reservation */
1122 struct drm_exec exec;
1123 /* Number of VMs reserved */
1124 unsigned int n_vms;
1125 /* Pointer to sync object */
1126 struct amdgpu_sync *sync;
1127};
1128
1129enum bo_vm_match {
1130 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
1131 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
1132 BO_VM_ALL, /* Match all VMs a BO was added to */
1133};
1134
1135/**
1136 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1137 * @mem: KFD BO structure.
1138 * @vm: the VM to reserve.
1139 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1140 */
1141static int reserve_bo_and_vm(struct kgd_mem *mem,
1142 struct amdgpu_vm *vm,
1143 struct bo_vm_reservation_context *ctx)
1144{
1145 struct amdgpu_bo *bo = mem->bo;
1146 int ret;
1147
1148 WARN_ON(!vm);
1149
1150 ctx->n_vms = 1;
1151 ctx->sync = &mem->sync;
1152 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1153 drm_exec_until_all_locked(&ctx->exec) {
1154 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1155 drm_exec_retry_on_contention(&ctx->exec);
1156 if (unlikely(ret))
1157 goto error;
1158
1159 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1160 drm_exec_retry_on_contention(&ctx->exec);
1161 if (unlikely(ret))
1162 goto error;
1163 }
1164 return 0;
1165
1166error:
1167 pr_err("Failed to reserve buffers in ttm.\n");
1168 drm_exec_fini(&ctx->exec);
1169 return ret;
1170}
1171
1172/**
1173 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1174 * @mem: KFD BO structure.
1175 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1176 * is used. Otherwise, a single VM associated with the BO.
1177 * @map_type: the mapping status that will be used to filter the VMs.
1178 * @ctx: the struct that will be used in unreserve_bo_and_vms().
1179 *
1180 * Returns 0 for success, negative for failure.
1181 */
1182static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1183 struct amdgpu_vm *vm, enum bo_vm_match map_type,
1184 struct bo_vm_reservation_context *ctx)
1185{
1186 struct kfd_mem_attachment *entry;
1187 struct amdgpu_bo *bo = mem->bo;
1188 int ret;
1189
1190 ctx->sync = &mem->sync;
1191 drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1192 drm_exec_until_all_locked(&ctx->exec) {
1193 ctx->n_vms = 0;
1194 list_for_each_entry(entry, &mem->attachments, list) {
1195 if ((vm && vm != entry->bo_va->base.vm) ||
1196 (entry->is_mapped != map_type
1197 && map_type != BO_VM_ALL))
1198 continue;
1199
1200 ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1201 &ctx->exec, 2);
1202 drm_exec_retry_on_contention(&ctx->exec);
1203 if (unlikely(ret))
1204 goto error;
1205 ++ctx->n_vms;
1206 }
1207
1208 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1209 drm_exec_retry_on_contention(&ctx->exec);
1210 if (unlikely(ret))
1211 goto error;
1212 }
1213 return 0;
1214
1215error:
1216 pr_err("Failed to reserve buffers in ttm.\n");
1217 drm_exec_fini(&ctx->exec);
1218 return ret;
1219}
1220
1221/**
1222 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1223 * @ctx: Reservation context to unreserve
1224 * @wait: Optionally wait for a sync object representing pending VM updates
1225 * @intr: Whether the wait is interruptible
1226 *
1227 * Also frees any resources allocated in
1228 * reserve_bo_and_(cond_)vm(s). Returns the status from
1229 * amdgpu_sync_wait.
1230 */
1231static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1232 bool wait, bool intr)
1233{
1234 int ret = 0;
1235
1236 if (wait)
1237 ret = amdgpu_sync_wait(ctx->sync, intr);
1238
1239 drm_exec_fini(&ctx->exec);
1240 ctx->sync = NULL;
1241 return ret;
1242}
1243
1244static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1245 struct kfd_mem_attachment *entry,
1246 struct amdgpu_sync *sync)
1247{
1248 struct amdgpu_bo_va *bo_va = entry->bo_va;
1249 struct amdgpu_device *adev = entry->adev;
1250 struct amdgpu_vm *vm = bo_va->base.vm;
1251
1252 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1253
1254 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1255
1256 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1257}
1258
1259static int update_gpuvm_pte(struct kgd_mem *mem,
1260 struct kfd_mem_attachment *entry,
1261 struct amdgpu_sync *sync)
1262{
1263 struct amdgpu_bo_va *bo_va = entry->bo_va;
1264 struct amdgpu_device *adev = entry->adev;
1265 int ret;
1266
1267 ret = kfd_mem_dmamap_attachment(mem, entry);
1268 if (ret)
1269 return ret;
1270
1271 /* Update the page tables */
1272 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1273 if (ret) {
1274 pr_err("amdgpu_vm_bo_update failed\n");
1275 return ret;
1276 }
1277
1278 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1279}
1280
1281static int map_bo_to_gpuvm(struct kgd_mem *mem,
1282 struct kfd_mem_attachment *entry,
1283 struct amdgpu_sync *sync,
1284 bool no_update_pte)
1285{
1286 int ret;
1287
1288 /* Set virtual address for the allocation */
1289 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1290 amdgpu_bo_size(entry->bo_va->base.bo),
1291 entry->pte_flags);
1292 if (ret) {
1293 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1294 entry->va, ret);
1295 return ret;
1296 }
1297
1298 if (no_update_pte)
1299 return 0;
1300
1301 ret = update_gpuvm_pte(mem, entry, sync);
1302 if (ret) {
1303 pr_err("update_gpuvm_pte() failed\n");
1304 goto update_gpuvm_pte_failed;
1305 }
1306
1307 return 0;
1308
1309update_gpuvm_pte_failed:
1310 unmap_bo_from_gpuvm(mem, entry, sync);
1311 kfd_mem_dmaunmap_attachment(mem, entry);
1312 return ret;
1313}
1314
1315static int process_validate_vms(struct amdkfd_process_info *process_info,
1316 struct ww_acquire_ctx *ticket)
1317{
1318 struct amdgpu_vm *peer_vm;
1319 int ret;
1320
1321 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1322 vm_list_node) {
1323 ret = vm_validate_pt_pd_bos(peer_vm, ticket);
1324 if (ret)
1325 return ret;
1326 }
1327
1328 return 0;
1329}
1330
1331static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1332 struct amdgpu_sync *sync)
1333{
1334 struct amdgpu_vm *peer_vm;
1335 int ret;
1336
1337 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1338 vm_list_node) {
1339 struct amdgpu_bo *pd = peer_vm->root.bo;
1340
1341 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1342 AMDGPU_SYNC_NE_OWNER,
1343 AMDGPU_FENCE_OWNER_KFD);
1344 if (ret)
1345 return ret;
1346 }
1347
1348 return 0;
1349}
1350
1351static int process_update_pds(struct amdkfd_process_info *process_info,
1352 struct amdgpu_sync *sync)
1353{
1354 struct amdgpu_vm *peer_vm;
1355 int ret;
1356
1357 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1358 vm_list_node) {
1359 ret = vm_update_pds(peer_vm, sync);
1360 if (ret)
1361 return ret;
1362 }
1363
1364 return 0;
1365}
1366
1367static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1368 struct dma_fence **ef)
1369{
1370 struct amdkfd_process_info *info = NULL;
1371 int ret;
1372
1373 if (!*process_info) {
1374 info = kzalloc(sizeof(*info), GFP_KERNEL);
1375 if (!info)
1376 return -ENOMEM;
1377
1378 mutex_init(&info->lock);
1379 mutex_init(&info->notifier_lock);
1380 INIT_LIST_HEAD(&info->vm_list_head);
1381 INIT_LIST_HEAD(&info->kfd_bo_list);
1382 INIT_LIST_HEAD(&info->userptr_valid_list);
1383 INIT_LIST_HEAD(&info->userptr_inval_list);
1384
1385 info->eviction_fence =
1386 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1387 current->mm,
1388 NULL);
1389 if (!info->eviction_fence) {
1390 pr_err("Failed to create eviction fence\n");
1391 ret = -ENOMEM;
1392 goto create_evict_fence_fail;
1393 }
1394
1395 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1396 INIT_DELAYED_WORK(&info->restore_userptr_work,
1397 amdgpu_amdkfd_restore_userptr_worker);
1398
1399 *process_info = info;
1400 }
1401
1402 vm->process_info = *process_info;
1403
1404 /* Validate page directory and attach eviction fence */
1405 ret = amdgpu_bo_reserve(vm->root.bo, true);
1406 if (ret)
1407 goto reserve_pd_fail;
1408 ret = vm_validate_pt_pd_bos(vm, NULL);
1409 if (ret) {
1410 pr_err("validate_pt_pd_bos() failed\n");
1411 goto validate_pd_fail;
1412 }
1413 ret = amdgpu_bo_sync_wait(vm->root.bo,
1414 AMDGPU_FENCE_OWNER_KFD, false);
1415 if (ret)
1416 goto wait_pd_fail;
1417 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1418 if (ret)
1419 goto reserve_shared_fail;
1420 dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1421 &vm->process_info->eviction_fence->base,
1422 DMA_RESV_USAGE_BOOKKEEP);
1423 amdgpu_bo_unreserve(vm->root.bo);
1424
1425 /* Update process info */
1426 mutex_lock(&vm->process_info->lock);
1427 list_add_tail(&vm->vm_list_node,
1428 &(vm->process_info->vm_list_head));
1429 vm->process_info->n_vms++;
1430
1431 *ef = dma_fence_get(&vm->process_info->eviction_fence->base);
1432 mutex_unlock(&vm->process_info->lock);
1433
1434 return 0;
1435
1436reserve_shared_fail:
1437wait_pd_fail:
1438validate_pd_fail:
1439 amdgpu_bo_unreserve(vm->root.bo);
1440reserve_pd_fail:
1441 vm->process_info = NULL;
1442 if (info) {
1443 dma_fence_put(&info->eviction_fence->base);
1444 *process_info = NULL;
1445 put_pid(info->pid);
1446create_evict_fence_fail:
1447 mutex_destroy(&info->lock);
1448 mutex_destroy(&info->notifier_lock);
1449 kfree(info);
1450 }
1451 return ret;
1452}
1453
1454/**
1455 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1456 * @bo: Handle of buffer object being pinned
1457 * @domain: Domain into which BO should be pinned
1458 *
1459 * - USERPTR BOs are UNPINNABLE and will return error
1460 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1461 * PIN count incremented. It is valid to PIN a BO multiple times
1462 *
1463 * Return: ZERO if successful in pinning, Non-Zero in case of error.
1464 */
1465static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1466{
1467 int ret = 0;
1468
1469 ret = amdgpu_bo_reserve(bo, false);
1470 if (unlikely(ret))
1471 return ret;
1472
1473 ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1474 if (ret)
1475 pr_err("Error in Pinning BO to domain: %d\n", domain);
1476
1477 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1478 amdgpu_bo_unreserve(bo);
1479
1480 return ret;
1481}
1482
1483/**
1484 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1485 * @bo: Handle of buffer object being unpinned
1486 *
1487 * - Is a illegal request for USERPTR BOs and is ignored
1488 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1489 * PIN count decremented. Calls to UNPIN must balance calls to PIN
1490 */
1491static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1492{
1493 int ret = 0;
1494
1495 ret = amdgpu_bo_reserve(bo, false);
1496 if (unlikely(ret))
1497 return;
1498
1499 amdgpu_bo_unpin(bo);
1500 amdgpu_bo_unreserve(bo);
1501}
1502
1503int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1504 struct amdgpu_vm *avm, u32 pasid)
1505
1506{
1507 int ret;
1508
1509 /* Free the original amdgpu allocated pasid,
1510 * will be replaced with kfd allocated pasid.
1511 */
1512 if (avm->pasid) {
1513 amdgpu_pasid_free(avm->pasid);
1514 amdgpu_vm_set_pasid(adev, avm, 0);
1515 }
1516
1517 ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1518 if (ret)
1519 return ret;
1520
1521 return 0;
1522}
1523
1524int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1525 struct amdgpu_vm *avm,
1526 void **process_info,
1527 struct dma_fence **ef)
1528{
1529 int ret;
1530
1531 /* Already a compute VM? */
1532 if (avm->process_info)
1533 return -EINVAL;
1534
1535 /* Convert VM into a compute VM */
1536 ret = amdgpu_vm_make_compute(adev, avm);
1537 if (ret)
1538 return ret;
1539
1540 /* Initialize KFD part of the VM and process info */
1541 ret = init_kfd_vm(avm, process_info, ef);
1542 if (ret)
1543 return ret;
1544
1545 amdgpu_vm_set_task_info(avm);
1546
1547 return 0;
1548}
1549
1550void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1551 struct amdgpu_vm *vm)
1552{
1553 struct amdkfd_process_info *process_info = vm->process_info;
1554
1555 if (!process_info)
1556 return;
1557
1558 /* Update process info */
1559 mutex_lock(&process_info->lock);
1560 process_info->n_vms--;
1561 list_del(&vm->vm_list_node);
1562 mutex_unlock(&process_info->lock);
1563
1564 vm->process_info = NULL;
1565
1566 /* Release per-process resources when last compute VM is destroyed */
1567 if (!process_info->n_vms) {
1568 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1569 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1570 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1571
1572 dma_fence_put(&process_info->eviction_fence->base);
1573 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1574 put_pid(process_info->pid);
1575 mutex_destroy(&process_info->lock);
1576 mutex_destroy(&process_info->notifier_lock);
1577 kfree(process_info);
1578 }
1579}
1580
1581void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1582 void *drm_priv)
1583{
1584 struct amdgpu_vm *avm;
1585
1586 if (WARN_ON(!adev || !drm_priv))
1587 return;
1588
1589 avm = drm_priv_to_vm(drm_priv);
1590
1591 pr_debug("Releasing process vm %p\n", avm);
1592
1593 /* The original pasid of amdgpu vm has already been
1594 * released during making a amdgpu vm to a compute vm
1595 * The current pasid is managed by kfd and will be
1596 * released on kfd process destroy. Set amdgpu pasid
1597 * to 0 to avoid duplicate release.
1598 */
1599 amdgpu_vm_release_compute(adev, avm);
1600}
1601
1602uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1603{
1604 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1605 struct amdgpu_bo *pd = avm->root.bo;
1606 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1607
1608 if (adev->asic_type < CHIP_VEGA10)
1609 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1610 return avm->pd_phys_addr;
1611}
1612
1613void amdgpu_amdkfd_block_mmu_notifications(void *p)
1614{
1615 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1616
1617 mutex_lock(&pinfo->lock);
1618 WRITE_ONCE(pinfo->block_mmu_notifications, true);
1619 mutex_unlock(&pinfo->lock);
1620}
1621
1622int amdgpu_amdkfd_criu_resume(void *p)
1623{
1624 int ret = 0;
1625 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1626
1627 mutex_lock(&pinfo->lock);
1628 pr_debug("scheduling work\n");
1629 mutex_lock(&pinfo->notifier_lock);
1630 pinfo->evicted_bos++;
1631 mutex_unlock(&pinfo->notifier_lock);
1632 if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1633 ret = -EINVAL;
1634 goto out_unlock;
1635 }
1636 WRITE_ONCE(pinfo->block_mmu_notifications, false);
1637 queue_delayed_work(system_freezable_wq,
1638 &pinfo->restore_userptr_work, 0);
1639
1640out_unlock:
1641 mutex_unlock(&pinfo->lock);
1642 return ret;
1643}
1644
1645size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1646 uint8_t xcp_id)
1647{
1648 uint64_t reserved_for_pt =
1649 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1650 ssize_t available;
1651 uint64_t vram_available, system_mem_available, ttm_mem_available;
1652
1653 spin_lock(&kfd_mem_limit.mem_limit_lock);
1654 vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1655 - adev->kfd.vram_used_aligned[xcp_id]
1656 - atomic64_read(&adev->vram_pin_size)
1657 - reserved_for_pt;
1658
1659 if (adev->gmc.is_app_apu) {
1660 system_mem_available = no_system_mem_limit ?
1661 kfd_mem_limit.max_system_mem_limit :
1662 kfd_mem_limit.max_system_mem_limit -
1663 kfd_mem_limit.system_mem_used;
1664
1665 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1666 kfd_mem_limit.ttm_mem_used;
1667
1668 available = min3(system_mem_available, ttm_mem_available,
1669 vram_available);
1670 available = ALIGN_DOWN(available, PAGE_SIZE);
1671 } else {
1672 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1673 }
1674
1675 spin_unlock(&kfd_mem_limit.mem_limit_lock);
1676
1677 if (available < 0)
1678 available = 0;
1679
1680 return available;
1681}
1682
1683int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1684 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1685 void *drm_priv, struct kgd_mem **mem,
1686 uint64_t *offset, uint32_t flags, bool criu_resume)
1687{
1688 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1689 struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1690 enum ttm_bo_type bo_type = ttm_bo_type_device;
1691 struct sg_table *sg = NULL;
1692 uint64_t user_addr = 0;
1693 struct amdgpu_bo *bo;
1694 struct drm_gem_object *gobj = NULL;
1695 u32 domain, alloc_domain;
1696 uint64_t aligned_size;
1697 int8_t xcp_id = -1;
1698 u64 alloc_flags;
1699 int ret;
1700
1701 /*
1702 * Check on which domain to allocate BO
1703 */
1704 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1705 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1706
1707 if (adev->gmc.is_app_apu) {
1708 domain = AMDGPU_GEM_DOMAIN_GTT;
1709 alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1710 alloc_flags = 0;
1711 } else {
1712 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1713 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1714 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1715 }
1716 xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1717 0 : fpriv->xcp_id;
1718 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1719 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1720 alloc_flags = 0;
1721 } else {
1722 domain = AMDGPU_GEM_DOMAIN_GTT;
1723 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1724 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1725
1726 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1727 if (!offset || !*offset)
1728 return -EINVAL;
1729 user_addr = untagged_addr(*offset);
1730 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1731 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1732 bo_type = ttm_bo_type_sg;
1733 if (size > UINT_MAX)
1734 return -EINVAL;
1735 sg = create_sg_table(*offset, size);
1736 if (!sg)
1737 return -ENOMEM;
1738 } else {
1739 return -EINVAL;
1740 }
1741 }
1742
1743 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1744 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1745 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT)
1746 alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT;
1747 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1748 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1749
1750 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1751 if (!*mem) {
1752 ret = -ENOMEM;
1753 goto err;
1754 }
1755 INIT_LIST_HEAD(&(*mem)->attachments);
1756 mutex_init(&(*mem)->lock);
1757 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1758
1759 /* Workaround for AQL queue wraparound bug. Map the same
1760 * memory twice. That means we only actually allocate half
1761 * the memory.
1762 */
1763 if ((*mem)->aql_queue)
1764 size >>= 1;
1765 aligned_size = PAGE_ALIGN(size);
1766
1767 (*mem)->alloc_flags = flags;
1768
1769 amdgpu_sync_create(&(*mem)->sync);
1770
1771 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1772 xcp_id);
1773 if (ret) {
1774 pr_debug("Insufficient memory\n");
1775 goto err_reserve_limit;
1776 }
1777
1778 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1779 va, (*mem)->aql_queue ? size << 1 : size,
1780 domain_string(alloc_domain), xcp_id);
1781
1782 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1783 bo_type, NULL, &gobj, xcp_id + 1);
1784 if (ret) {
1785 pr_debug("Failed to create BO on domain %s. ret %d\n",
1786 domain_string(alloc_domain), ret);
1787 goto err_bo_create;
1788 }
1789 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1790 if (ret) {
1791 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1792 goto err_node_allow;
1793 }
1794 ret = drm_gem_handle_create(adev->kfd.client.file, gobj, &(*mem)->gem_handle);
1795 if (ret)
1796 goto err_gem_handle_create;
1797 bo = gem_to_amdgpu_bo(gobj);
1798 if (bo_type == ttm_bo_type_sg) {
1799 bo->tbo.sg = sg;
1800 bo->tbo.ttm->sg = sg;
1801 }
1802 bo->kfd_bo = *mem;
1803 (*mem)->bo = bo;
1804 if (user_addr)
1805 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1806
1807 (*mem)->va = va;
1808 (*mem)->domain = domain;
1809 (*mem)->mapped_to_gpu_memory = 0;
1810 (*mem)->process_info = avm->process_info;
1811
1812 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1813
1814 if (user_addr) {
1815 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1816 ret = init_user_pages(*mem, user_addr, criu_resume);
1817 if (ret)
1818 goto allocate_init_user_pages_failed;
1819 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1820 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1821 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1822 if (ret) {
1823 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1824 goto err_pin_bo;
1825 }
1826 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1827 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1828 } else {
1829 mutex_lock(&avm->process_info->lock);
1830 if (avm->process_info->eviction_fence &&
1831 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
1832 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain,
1833 &avm->process_info->eviction_fence->base);
1834 mutex_unlock(&avm->process_info->lock);
1835 if (ret)
1836 goto err_validate_bo;
1837 }
1838
1839 if (offset)
1840 *offset = amdgpu_bo_mmap_offset(bo);
1841
1842 return 0;
1843
1844allocate_init_user_pages_failed:
1845err_pin_bo:
1846err_validate_bo:
1847 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1848 drm_gem_handle_delete(adev->kfd.client.file, (*mem)->gem_handle);
1849err_gem_handle_create:
1850 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1851err_node_allow:
1852 /* Don't unreserve system mem limit twice */
1853 goto err_reserve_limit;
1854err_bo_create:
1855 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1856err_reserve_limit:
1857 amdgpu_sync_free(&(*mem)->sync);
1858 mutex_destroy(&(*mem)->lock);
1859 if (gobj)
1860 drm_gem_object_put(gobj);
1861 else
1862 kfree(*mem);
1863err:
1864 if (sg) {
1865 sg_free_table(sg);
1866 kfree(sg);
1867 }
1868 return ret;
1869}
1870
1871int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1872 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1873 uint64_t *size)
1874{
1875 struct amdkfd_process_info *process_info = mem->process_info;
1876 unsigned long bo_size = mem->bo->tbo.base.size;
1877 bool use_release_notifier = (mem->bo->kfd_bo == mem);
1878 struct kfd_mem_attachment *entry, *tmp;
1879 struct bo_vm_reservation_context ctx;
1880 unsigned int mapped_to_gpu_memory;
1881 int ret;
1882 bool is_imported = false;
1883
1884 mutex_lock(&mem->lock);
1885
1886 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1887 if (mem->alloc_flags &
1888 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1889 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1890 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1891 }
1892
1893 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1894 is_imported = mem->is_imported;
1895 mutex_unlock(&mem->lock);
1896 /* lock is not needed after this, since mem is unused and will
1897 * be freed anyway
1898 */
1899
1900 if (mapped_to_gpu_memory > 0) {
1901 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1902 mem->va, bo_size);
1903 return -EBUSY;
1904 }
1905
1906 /* Make sure restore workers don't access the BO any more */
1907 mutex_lock(&process_info->lock);
1908 list_del(&mem->validate_list);
1909 mutex_unlock(&process_info->lock);
1910
1911 /* Cleanup user pages and MMU notifiers */
1912 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1913 amdgpu_hmm_unregister(mem->bo);
1914 mutex_lock(&process_info->notifier_lock);
1915 amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1916 mutex_unlock(&process_info->notifier_lock);
1917 }
1918
1919 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1920 if (unlikely(ret))
1921 return ret;
1922
1923 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1924 process_info->eviction_fence);
1925 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1926 mem->va + bo_size * (1 + mem->aql_queue));
1927
1928 /* Remove from VM internal data structures */
1929 list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
1930 kfd_mem_dmaunmap_attachment(mem, entry);
1931 kfd_mem_detach(entry);
1932 }
1933
1934 ret = unreserve_bo_and_vms(&ctx, false, false);
1935
1936 /* Free the sync object */
1937 amdgpu_sync_free(&mem->sync);
1938
1939 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1940 * remap BO. We need to free it.
1941 */
1942 if (mem->bo->tbo.sg) {
1943 sg_free_table(mem->bo->tbo.sg);
1944 kfree(mem->bo->tbo.sg);
1945 }
1946
1947 /* Update the size of the BO being freed if it was allocated from
1948 * VRAM and is not imported. For APP APU VRAM allocations are done
1949 * in GTT domain
1950 */
1951 if (size) {
1952 if (!is_imported &&
1953 (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1954 (adev->gmc.is_app_apu &&
1955 mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1956 *size = bo_size;
1957 else
1958 *size = 0;
1959 }
1960
1961 /* Free the BO*/
1962 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1963 drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle);
1964 if (mem->dmabuf) {
1965 dma_buf_put(mem->dmabuf);
1966 mem->dmabuf = NULL;
1967 }
1968 mutex_destroy(&mem->lock);
1969
1970 /* If this releases the last reference, it will end up calling
1971 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1972 * this needs to be the last call here.
1973 */
1974 drm_gem_object_put(&mem->bo->tbo.base);
1975
1976 /*
1977 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
1978 * explicitly free it here.
1979 */
1980 if (!use_release_notifier)
1981 kfree(mem);
1982
1983 return ret;
1984}
1985
1986int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1987 struct amdgpu_device *adev, struct kgd_mem *mem,
1988 void *drm_priv)
1989{
1990 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1991 int ret;
1992 struct amdgpu_bo *bo;
1993 uint32_t domain;
1994 struct kfd_mem_attachment *entry;
1995 struct bo_vm_reservation_context ctx;
1996 unsigned long bo_size;
1997 bool is_invalid_userptr = false;
1998
1999 bo = mem->bo;
2000 if (!bo) {
2001 pr_err("Invalid BO when mapping memory to GPU\n");
2002 return -EINVAL;
2003 }
2004
2005 /* Make sure restore is not running concurrently. Since we
2006 * don't map invalid userptr BOs, we rely on the next restore
2007 * worker to do the mapping
2008 */
2009 mutex_lock(&mem->process_info->lock);
2010
2011 /* Lock notifier lock. If we find an invalid userptr BO, we can be
2012 * sure that the MMU notifier is no longer running
2013 * concurrently and the queues are actually stopped
2014 */
2015 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2016 mutex_lock(&mem->process_info->notifier_lock);
2017 is_invalid_userptr = !!mem->invalid;
2018 mutex_unlock(&mem->process_info->notifier_lock);
2019 }
2020
2021 mutex_lock(&mem->lock);
2022
2023 domain = mem->domain;
2024 bo_size = bo->tbo.base.size;
2025
2026 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
2027 mem->va,
2028 mem->va + bo_size * (1 + mem->aql_queue),
2029 avm, domain_string(domain));
2030
2031 if (!kfd_mem_is_attached(avm, mem)) {
2032 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
2033 if (ret)
2034 goto out;
2035 }
2036
2037 ret = reserve_bo_and_vm(mem, avm, &ctx);
2038 if (unlikely(ret))
2039 goto out;
2040
2041 /* Userptr can be marked as "not invalid", but not actually be
2042 * validated yet (still in the system domain). In that case
2043 * the queues are still stopped and we can leave mapping for
2044 * the next restore worker
2045 */
2046 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
2047 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
2048 is_invalid_userptr = true;
2049
2050 ret = vm_validate_pt_pd_bos(avm, NULL);
2051 if (unlikely(ret))
2052 goto out_unreserve;
2053
2054 list_for_each_entry(entry, &mem->attachments, list) {
2055 if (entry->bo_va->base.vm != avm || entry->is_mapped)
2056 continue;
2057
2058 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2059 entry->va, entry->va + bo_size, entry);
2060
2061 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2062 is_invalid_userptr);
2063 if (ret) {
2064 pr_err("Failed to map bo to gpuvm\n");
2065 goto out_unreserve;
2066 }
2067
2068 ret = vm_update_pds(avm, ctx.sync);
2069 if (ret) {
2070 pr_err("Failed to update page directories\n");
2071 goto out_unreserve;
2072 }
2073
2074 entry->is_mapped = true;
2075 mem->mapped_to_gpu_memory++;
2076 pr_debug("\t INC mapping count %d\n",
2077 mem->mapped_to_gpu_memory);
2078 }
2079
2080 ret = unreserve_bo_and_vms(&ctx, false, false);
2081
2082 goto out;
2083
2084out_unreserve:
2085 unreserve_bo_and_vms(&ctx, false, false);
2086out:
2087 mutex_unlock(&mem->process_info->lock);
2088 mutex_unlock(&mem->lock);
2089 return ret;
2090}
2091
2092int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv)
2093{
2094 struct kfd_mem_attachment *entry;
2095 struct amdgpu_vm *vm;
2096 int ret;
2097
2098 vm = drm_priv_to_vm(drm_priv);
2099
2100 mutex_lock(&mem->lock);
2101
2102 ret = amdgpu_bo_reserve(mem->bo, true);
2103 if (ret)
2104 goto out;
2105
2106 list_for_each_entry(entry, &mem->attachments, list) {
2107 if (entry->bo_va->base.vm != vm)
2108 continue;
2109 if (entry->bo_va->base.bo->tbo.ttm &&
2110 !entry->bo_va->base.bo->tbo.ttm->sg)
2111 continue;
2112
2113 kfd_mem_dmaunmap_attachment(mem, entry);
2114 }
2115
2116 amdgpu_bo_unreserve(mem->bo);
2117out:
2118 mutex_unlock(&mem->lock);
2119
2120 return ret;
2121}
2122
2123int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2124 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2125{
2126 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2127 unsigned long bo_size = mem->bo->tbo.base.size;
2128 struct kfd_mem_attachment *entry;
2129 struct bo_vm_reservation_context ctx;
2130 int ret;
2131
2132 mutex_lock(&mem->lock);
2133
2134 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2135 if (unlikely(ret))
2136 goto out;
2137 /* If no VMs were reserved, it means the BO wasn't actually mapped */
2138 if (ctx.n_vms == 0) {
2139 ret = -EINVAL;
2140 goto unreserve_out;
2141 }
2142
2143 ret = vm_validate_pt_pd_bos(avm, NULL);
2144 if (unlikely(ret))
2145 goto unreserve_out;
2146
2147 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2148 mem->va,
2149 mem->va + bo_size * (1 + mem->aql_queue),
2150 avm);
2151
2152 list_for_each_entry(entry, &mem->attachments, list) {
2153 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2154 continue;
2155
2156 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2157 entry->va, entry->va + bo_size, entry);
2158
2159 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2160 entry->is_mapped = false;
2161
2162 mem->mapped_to_gpu_memory--;
2163 pr_debug("\t DEC mapping count %d\n",
2164 mem->mapped_to_gpu_memory);
2165 }
2166
2167unreserve_out:
2168 unreserve_bo_and_vms(&ctx, false, false);
2169out:
2170 mutex_unlock(&mem->lock);
2171 return ret;
2172}
2173
2174int amdgpu_amdkfd_gpuvm_sync_memory(
2175 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2176{
2177 struct amdgpu_sync sync;
2178 int ret;
2179
2180 amdgpu_sync_create(&sync);
2181
2182 mutex_lock(&mem->lock);
2183 amdgpu_sync_clone(&mem->sync, &sync);
2184 mutex_unlock(&mem->lock);
2185
2186 ret = amdgpu_sync_wait(&sync, intr);
2187 amdgpu_sync_free(&sync);
2188 return ret;
2189}
2190
2191/**
2192 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2193 * @bo: Buffer object to be mapped
2194 *
2195 * Before return, bo reference count is incremented. To release the reference and unpin/
2196 * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2197 */
2198int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
2199{
2200 int ret;
2201
2202 ret = amdgpu_bo_reserve(bo, true);
2203 if (ret) {
2204 pr_err("Failed to reserve bo. ret %d\n", ret);
2205 goto err_reserve_bo_failed;
2206 }
2207
2208 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2209 if (ret) {
2210 pr_err("Failed to pin bo. ret %d\n", ret);
2211 goto err_pin_bo_failed;
2212 }
2213
2214 ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2215 if (ret) {
2216 pr_err("Failed to bind bo to GART. ret %d\n", ret);
2217 goto err_map_bo_gart_failed;
2218 }
2219
2220 amdgpu_amdkfd_remove_eviction_fence(
2221 bo, bo->vm_bo->vm->process_info->eviction_fence);
2222
2223 amdgpu_bo_unreserve(bo);
2224
2225 bo = amdgpu_bo_ref(bo);
2226
2227 return 0;
2228
2229err_map_bo_gart_failed:
2230 amdgpu_bo_unpin(bo);
2231err_pin_bo_failed:
2232 amdgpu_bo_unreserve(bo);
2233err_reserve_bo_failed:
2234
2235 return ret;
2236}
2237
2238/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2239 *
2240 * @mem: Buffer object to be mapped for CPU access
2241 * @kptr[out]: pointer in kernel CPU address space
2242 * @size[out]: size of the buffer
2243 *
2244 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2245 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2246 * validate_list, so the GPU mapping can be restored after a page table was
2247 * evicted.
2248 *
2249 * Return: 0 on success, error code on failure
2250 */
2251int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2252 void **kptr, uint64_t *size)
2253{
2254 int ret;
2255 struct amdgpu_bo *bo = mem->bo;
2256
2257 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2258 pr_err("userptr can't be mapped to kernel\n");
2259 return -EINVAL;
2260 }
2261
2262 mutex_lock(&mem->process_info->lock);
2263
2264 ret = amdgpu_bo_reserve(bo, true);
2265 if (ret) {
2266 pr_err("Failed to reserve bo. ret %d\n", ret);
2267 goto bo_reserve_failed;
2268 }
2269
2270 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2271 if (ret) {
2272 pr_err("Failed to pin bo. ret %d\n", ret);
2273 goto pin_failed;
2274 }
2275
2276 ret = amdgpu_bo_kmap(bo, kptr);
2277 if (ret) {
2278 pr_err("Failed to map bo to kernel. ret %d\n", ret);
2279 goto kmap_failed;
2280 }
2281
2282 amdgpu_amdkfd_remove_eviction_fence(
2283 bo, mem->process_info->eviction_fence);
2284
2285 if (size)
2286 *size = amdgpu_bo_size(bo);
2287
2288 amdgpu_bo_unreserve(bo);
2289
2290 mutex_unlock(&mem->process_info->lock);
2291 return 0;
2292
2293kmap_failed:
2294 amdgpu_bo_unpin(bo);
2295pin_failed:
2296 amdgpu_bo_unreserve(bo);
2297bo_reserve_failed:
2298 mutex_unlock(&mem->process_info->lock);
2299
2300 return ret;
2301}
2302
2303/** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2304 *
2305 * @mem: Buffer object to be unmapped for CPU access
2306 *
2307 * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2308 * eviction fence, so this function should only be used for cleanup before the
2309 * BO is destroyed.
2310 */
2311void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2312{
2313 struct amdgpu_bo *bo = mem->bo;
2314
2315 amdgpu_bo_reserve(bo, true);
2316 amdgpu_bo_kunmap(bo);
2317 amdgpu_bo_unpin(bo);
2318 amdgpu_bo_unreserve(bo);
2319}
2320
2321int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2322 struct kfd_vm_fault_info *mem)
2323{
2324 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2325 *mem = *adev->gmc.vm_fault_info;
2326 mb(); /* make sure read happened */
2327 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2328 }
2329 return 0;
2330}
2331
2332static int import_obj_create(struct amdgpu_device *adev,
2333 struct dma_buf *dma_buf,
2334 struct drm_gem_object *obj,
2335 uint64_t va, void *drm_priv,
2336 struct kgd_mem **mem, uint64_t *size,
2337 uint64_t *mmap_offset)
2338{
2339 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2340 struct amdgpu_bo *bo;
2341 int ret;
2342
2343 bo = gem_to_amdgpu_bo(obj);
2344 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2345 AMDGPU_GEM_DOMAIN_GTT)))
2346 /* Only VRAM and GTT BOs are supported */
2347 return -EINVAL;
2348
2349 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2350 if (!*mem)
2351 return -ENOMEM;
2352
2353 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2354 if (ret)
2355 goto err_free_mem;
2356
2357 if (size)
2358 *size = amdgpu_bo_size(bo);
2359
2360 if (mmap_offset)
2361 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2362
2363 INIT_LIST_HEAD(&(*mem)->attachments);
2364 mutex_init(&(*mem)->lock);
2365
2366 (*mem)->alloc_flags =
2367 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2368 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2369 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2370 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2371
2372 get_dma_buf(dma_buf);
2373 (*mem)->dmabuf = dma_buf;
2374 (*mem)->bo = bo;
2375 (*mem)->va = va;
2376 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->gmc.is_app_apu ?
2377 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2378
2379 (*mem)->mapped_to_gpu_memory = 0;
2380 (*mem)->process_info = avm->process_info;
2381 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2382 amdgpu_sync_create(&(*mem)->sync);
2383 (*mem)->is_imported = true;
2384
2385 mutex_lock(&avm->process_info->lock);
2386 if (avm->process_info->eviction_fence &&
2387 !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
2388 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, (*mem)->domain,
2389 &avm->process_info->eviction_fence->base);
2390 mutex_unlock(&avm->process_info->lock);
2391 if (ret)
2392 goto err_remove_mem;
2393
2394 return 0;
2395
2396err_remove_mem:
2397 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
2398 drm_vma_node_revoke(&obj->vma_node, drm_priv);
2399err_free_mem:
2400 kfree(*mem);
2401 return ret;
2402}
2403
2404int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
2405 uint64_t va, void *drm_priv,
2406 struct kgd_mem **mem, uint64_t *size,
2407 uint64_t *mmap_offset)
2408{
2409 struct drm_gem_object *obj;
2410 uint32_t handle;
2411 int ret;
2412
2413 ret = drm_gem_prime_fd_to_handle(&adev->ddev, adev->kfd.client.file, fd,
2414 &handle);
2415 if (ret)
2416 return ret;
2417 obj = drm_gem_object_lookup(adev->kfd.client.file, handle);
2418 if (!obj) {
2419 ret = -EINVAL;
2420 goto err_release_handle;
2421 }
2422
2423 ret = import_obj_create(adev, obj->dma_buf, obj, va, drm_priv, mem, size,
2424 mmap_offset);
2425 if (ret)
2426 goto err_put_obj;
2427
2428 (*mem)->gem_handle = handle;
2429
2430 return 0;
2431
2432err_put_obj:
2433 drm_gem_object_put(obj);
2434err_release_handle:
2435 drm_gem_handle_delete(adev->kfd.client.file, handle);
2436 return ret;
2437}
2438
2439int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2440 struct dma_buf **dma_buf)
2441{
2442 int ret;
2443
2444 mutex_lock(&mem->lock);
2445 ret = kfd_mem_export_dmabuf(mem);
2446 if (ret)
2447 goto out;
2448
2449 get_dma_buf(mem->dmabuf);
2450 *dma_buf = mem->dmabuf;
2451out:
2452 mutex_unlock(&mem->lock);
2453 return ret;
2454}
2455
2456/* Evict a userptr BO by stopping the queues if necessary
2457 *
2458 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2459 * cannot do any memory allocations, and cannot take any locks that
2460 * are held elsewhere while allocating memory.
2461 *
2462 * It doesn't do anything to the BO itself. The real work happens in
2463 * restore, where we get updated page addresses. This function only
2464 * ensures that GPU access to the BO is stopped.
2465 */
2466int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2467 unsigned long cur_seq, struct kgd_mem *mem)
2468{
2469 struct amdkfd_process_info *process_info = mem->process_info;
2470 int r = 0;
2471
2472 /* Do not process MMU notifications during CRIU restore until
2473 * KFD_CRIU_OP_RESUME IOCTL is received
2474 */
2475 if (READ_ONCE(process_info->block_mmu_notifications))
2476 return 0;
2477
2478 mutex_lock(&process_info->notifier_lock);
2479 mmu_interval_set_seq(mni, cur_seq);
2480
2481 mem->invalid++;
2482 if (++process_info->evicted_bos == 1) {
2483 /* First eviction, stop the queues */
2484 r = kgd2kfd_quiesce_mm(mni->mm,
2485 KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2486 if (r)
2487 pr_err("Failed to quiesce KFD\n");
2488 queue_delayed_work(system_freezable_wq,
2489 &process_info->restore_userptr_work,
2490 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2491 }
2492 mutex_unlock(&process_info->notifier_lock);
2493
2494 return r;
2495}
2496
2497/* Update invalid userptr BOs
2498 *
2499 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2500 * userptr_inval_list and updates user pages for all BOs that have
2501 * been invalidated since their last update.
2502 */
2503static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2504 struct mm_struct *mm)
2505{
2506 struct kgd_mem *mem, *tmp_mem;
2507 struct amdgpu_bo *bo;
2508 struct ttm_operation_ctx ctx = { false, false };
2509 uint32_t invalid;
2510 int ret = 0;
2511
2512 mutex_lock(&process_info->notifier_lock);
2513
2514 /* Move all invalidated BOs to the userptr_inval_list */
2515 list_for_each_entry_safe(mem, tmp_mem,
2516 &process_info->userptr_valid_list,
2517 validate_list)
2518 if (mem->invalid)
2519 list_move_tail(&mem->validate_list,
2520 &process_info->userptr_inval_list);
2521
2522 /* Go through userptr_inval_list and update any invalid user_pages */
2523 list_for_each_entry(mem, &process_info->userptr_inval_list,
2524 validate_list) {
2525 invalid = mem->invalid;
2526 if (!invalid)
2527 /* BO hasn't been invalidated since the last
2528 * revalidation attempt. Keep its page list.
2529 */
2530 continue;
2531
2532 bo = mem->bo;
2533
2534 amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2535 mem->range = NULL;
2536
2537 /* BO reservations and getting user pages (hmm_range_fault)
2538 * must happen outside the notifier lock
2539 */
2540 mutex_unlock(&process_info->notifier_lock);
2541
2542 /* Move the BO to system (CPU) domain if necessary to unmap
2543 * and free the SG table
2544 */
2545 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2546 if (amdgpu_bo_reserve(bo, true))
2547 return -EAGAIN;
2548 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2549 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2550 amdgpu_bo_unreserve(bo);
2551 if (ret) {
2552 pr_err("%s: Failed to invalidate userptr BO\n",
2553 __func__);
2554 return -EAGAIN;
2555 }
2556 }
2557
2558 /* Get updated user pages */
2559 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2560 &mem->range);
2561 if (ret) {
2562 pr_debug("Failed %d to get user pages\n", ret);
2563
2564 /* Return -EFAULT bad address error as success. It will
2565 * fail later with a VM fault if the GPU tries to access
2566 * it. Better than hanging indefinitely with stalled
2567 * user mode queues.
2568 *
2569 * Return other error -EBUSY or -ENOMEM to retry restore
2570 */
2571 if (ret != -EFAULT)
2572 return ret;
2573
2574 ret = 0;
2575 }
2576
2577 mutex_lock(&process_info->notifier_lock);
2578
2579 /* Mark the BO as valid unless it was invalidated
2580 * again concurrently.
2581 */
2582 if (mem->invalid != invalid) {
2583 ret = -EAGAIN;
2584 goto unlock_out;
2585 }
2586 /* set mem valid if mem has hmm range associated */
2587 if (mem->range)
2588 mem->invalid = 0;
2589 }
2590
2591unlock_out:
2592 mutex_unlock(&process_info->notifier_lock);
2593
2594 return ret;
2595}
2596
2597/* Validate invalid userptr BOs
2598 *
2599 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2600 * with new page addresses and waits for the page table updates to complete.
2601 */
2602static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2603{
2604 struct ttm_operation_ctx ctx = { false, false };
2605 struct amdgpu_sync sync;
2606 struct drm_exec exec;
2607
2608 struct amdgpu_vm *peer_vm;
2609 struct kgd_mem *mem, *tmp_mem;
2610 struct amdgpu_bo *bo;
2611 int ret;
2612
2613 amdgpu_sync_create(&sync);
2614
2615 drm_exec_init(&exec, 0, 0);
2616 /* Reserve all BOs and page tables for validation */
2617 drm_exec_until_all_locked(&exec) {
2618 /* Reserve all the page directories */
2619 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2620 vm_list_node) {
2621 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2622 drm_exec_retry_on_contention(&exec);
2623 if (unlikely(ret))
2624 goto unreserve_out;
2625 }
2626
2627 /* Reserve the userptr_inval_list entries to resv_list */
2628 list_for_each_entry(mem, &process_info->userptr_inval_list,
2629 validate_list) {
2630 struct drm_gem_object *gobj;
2631
2632 gobj = &mem->bo->tbo.base;
2633 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2634 drm_exec_retry_on_contention(&exec);
2635 if (unlikely(ret))
2636 goto unreserve_out;
2637 }
2638 }
2639
2640 ret = process_validate_vms(process_info, NULL);
2641 if (ret)
2642 goto unreserve_out;
2643
2644 /* Validate BOs and update GPUVM page tables */
2645 list_for_each_entry_safe(mem, tmp_mem,
2646 &process_info->userptr_inval_list,
2647 validate_list) {
2648 struct kfd_mem_attachment *attachment;
2649
2650 bo = mem->bo;
2651
2652 /* Validate the BO if we got user pages */
2653 if (bo->tbo.ttm->pages[0]) {
2654 amdgpu_bo_placement_from_domain(bo, mem->domain);
2655 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2656 if (ret) {
2657 pr_err("%s: failed to validate BO\n", __func__);
2658 goto unreserve_out;
2659 }
2660 }
2661
2662 /* Update mapping. If the BO was not validated
2663 * (because we couldn't get user pages), this will
2664 * clear the page table entries, which will result in
2665 * VM faults if the GPU tries to access the invalid
2666 * memory.
2667 */
2668 list_for_each_entry(attachment, &mem->attachments, list) {
2669 if (!attachment->is_mapped)
2670 continue;
2671
2672 kfd_mem_dmaunmap_attachment(mem, attachment);
2673 ret = update_gpuvm_pte(mem, attachment, &sync);
2674 if (ret) {
2675 pr_err("%s: update PTE failed\n", __func__);
2676 /* make sure this gets validated again */
2677 mutex_lock(&process_info->notifier_lock);
2678 mem->invalid++;
2679 mutex_unlock(&process_info->notifier_lock);
2680 goto unreserve_out;
2681 }
2682 }
2683 }
2684
2685 /* Update page directories */
2686 ret = process_update_pds(process_info, &sync);
2687
2688unreserve_out:
2689 drm_exec_fini(&exec);
2690 amdgpu_sync_wait(&sync, false);
2691 amdgpu_sync_free(&sync);
2692
2693 return ret;
2694}
2695
2696/* Confirm that all user pages are valid while holding the notifier lock
2697 *
2698 * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2699 */
2700static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2701{
2702 struct kgd_mem *mem, *tmp_mem;
2703 int ret = 0;
2704
2705 list_for_each_entry_safe(mem, tmp_mem,
2706 &process_info->userptr_inval_list,
2707 validate_list) {
2708 bool valid;
2709
2710 /* keep mem without hmm range at userptr_inval_list */
2711 if (!mem->range)
2712 continue;
2713
2714 /* Only check mem with hmm range associated */
2715 valid = amdgpu_ttm_tt_get_user_pages_done(
2716 mem->bo->tbo.ttm, mem->range);
2717
2718 mem->range = NULL;
2719 if (!valid) {
2720 WARN(!mem->invalid, "Invalid BO not marked invalid");
2721 ret = -EAGAIN;
2722 continue;
2723 }
2724
2725 if (mem->invalid) {
2726 WARN(1, "Valid BO is marked invalid");
2727 ret = -EAGAIN;
2728 continue;
2729 }
2730
2731 list_move_tail(&mem->validate_list,
2732 &process_info->userptr_valid_list);
2733 }
2734
2735 return ret;
2736}
2737
2738/* Worker callback to restore evicted userptr BOs
2739 *
2740 * Tries to update and validate all userptr BOs. If successful and no
2741 * concurrent evictions happened, the queues are restarted. Otherwise,
2742 * reschedule for another attempt later.
2743 */
2744static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2745{
2746 struct delayed_work *dwork = to_delayed_work(work);
2747 struct amdkfd_process_info *process_info =
2748 container_of(dwork, struct amdkfd_process_info,
2749 restore_userptr_work);
2750 struct task_struct *usertask;
2751 struct mm_struct *mm;
2752 uint32_t evicted_bos;
2753
2754 mutex_lock(&process_info->notifier_lock);
2755 evicted_bos = process_info->evicted_bos;
2756 mutex_unlock(&process_info->notifier_lock);
2757 if (!evicted_bos)
2758 return;
2759
2760 /* Reference task and mm in case of concurrent process termination */
2761 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2762 if (!usertask)
2763 return;
2764 mm = get_task_mm(usertask);
2765 if (!mm) {
2766 put_task_struct(usertask);
2767 return;
2768 }
2769
2770 mutex_lock(&process_info->lock);
2771
2772 if (update_invalid_user_pages(process_info, mm))
2773 goto unlock_out;
2774 /* userptr_inval_list can be empty if all evicted userptr BOs
2775 * have been freed. In that case there is nothing to validate
2776 * and we can just restart the queues.
2777 */
2778 if (!list_empty(&process_info->userptr_inval_list)) {
2779 if (validate_invalid_user_pages(process_info))
2780 goto unlock_out;
2781 }
2782 /* Final check for concurrent evicton and atomic update. If
2783 * another eviction happens after successful update, it will
2784 * be a first eviction that calls quiesce_mm. The eviction
2785 * reference counting inside KFD will handle this case.
2786 */
2787 mutex_lock(&process_info->notifier_lock);
2788 if (process_info->evicted_bos != evicted_bos)
2789 goto unlock_notifier_out;
2790
2791 if (confirm_valid_user_pages_locked(process_info)) {
2792 WARN(1, "User pages unexpectedly invalid");
2793 goto unlock_notifier_out;
2794 }
2795
2796 process_info->evicted_bos = evicted_bos = 0;
2797
2798 if (kgd2kfd_resume_mm(mm)) {
2799 pr_err("%s: Failed to resume KFD\n", __func__);
2800 /* No recovery from this failure. Probably the CP is
2801 * hanging. No point trying again.
2802 */
2803 }
2804
2805unlock_notifier_out:
2806 mutex_unlock(&process_info->notifier_lock);
2807unlock_out:
2808 mutex_unlock(&process_info->lock);
2809
2810 /* If validation failed, reschedule another attempt */
2811 if (evicted_bos) {
2812 queue_delayed_work(system_freezable_wq,
2813 &process_info->restore_userptr_work,
2814 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2815
2816 kfd_smi_event_queue_restore_rescheduled(mm);
2817 }
2818 mmput(mm);
2819 put_task_struct(usertask);
2820}
2821
2822static void replace_eviction_fence(struct dma_fence __rcu **ef,
2823 struct dma_fence *new_ef)
2824{
2825 struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true
2826 /* protected by process_info->lock */);
2827
2828 /* If we're replacing an unsignaled eviction fence, that fence will
2829 * never be signaled, and if anyone is still waiting on that fence,
2830 * they will hang forever. This should never happen. We should only
2831 * replace the fence in restore_work that only gets scheduled after
2832 * eviction work signaled the fence.
2833 */
2834 WARN_ONCE(!dma_fence_is_signaled(old_ef),
2835 "Replacing unsignaled eviction fence");
2836 dma_fence_put(old_ef);
2837}
2838
2839/** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2840 * KFD process identified by process_info
2841 *
2842 * @process_info: amdkfd_process_info of the KFD process
2843 *
2844 * After memory eviction, restore thread calls this function. The function
2845 * should be called when the Process is still valid. BO restore involves -
2846 *
2847 * 1. Release old eviction fence and create new one
2848 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2849 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2850 * BOs that need to be reserved.
2851 * 4. Reserve all the BOs
2852 * 5. Validate of PD and PT BOs.
2853 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2854 * 7. Add fence to all PD and PT BOs.
2855 * 8. Unreserve all BOs
2856 */
2857int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu **ef)
2858{
2859 struct amdkfd_process_info *process_info = info;
2860 struct amdgpu_vm *peer_vm;
2861 struct kgd_mem *mem;
2862 struct list_head duplicate_save;
2863 struct amdgpu_sync sync_obj;
2864 unsigned long failed_size = 0;
2865 unsigned long total_size = 0;
2866 struct drm_exec exec;
2867 int ret;
2868
2869 INIT_LIST_HEAD(&duplicate_save);
2870
2871 mutex_lock(&process_info->lock);
2872
2873 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
2874 drm_exec_until_all_locked(&exec) {
2875 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2876 vm_list_node) {
2877 ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2878 drm_exec_retry_on_contention(&exec);
2879 if (unlikely(ret)) {
2880 pr_err("Locking VM PD failed, ret: %d\n", ret);
2881 goto ttm_reserve_fail;
2882 }
2883 }
2884
2885 /* Reserve all BOs and page tables/directory. Add all BOs from
2886 * kfd_bo_list to ctx.list
2887 */
2888 list_for_each_entry(mem, &process_info->kfd_bo_list,
2889 validate_list) {
2890 struct drm_gem_object *gobj;
2891
2892 gobj = &mem->bo->tbo.base;
2893 ret = drm_exec_prepare_obj(&exec, gobj, 1);
2894 drm_exec_retry_on_contention(&exec);
2895 if (unlikely(ret)) {
2896 pr_err("drm_exec_prepare_obj failed, ret: %d\n", ret);
2897 goto ttm_reserve_fail;
2898 }
2899 }
2900 }
2901
2902 amdgpu_sync_create(&sync_obj);
2903
2904 /* Validate BOs managed by KFD */
2905 list_for_each_entry(mem, &process_info->kfd_bo_list,
2906 validate_list) {
2907
2908 struct amdgpu_bo *bo = mem->bo;
2909 uint32_t domain = mem->domain;
2910 struct dma_resv_iter cursor;
2911 struct dma_fence *fence;
2912
2913 total_size += amdgpu_bo_size(bo);
2914
2915 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2916 if (ret) {
2917 pr_debug("Memory eviction: Validate BOs failed\n");
2918 failed_size += amdgpu_bo_size(bo);
2919 ret = amdgpu_amdkfd_bo_validate(bo,
2920 AMDGPU_GEM_DOMAIN_GTT, false);
2921 if (ret) {
2922 pr_debug("Memory eviction: Try again\n");
2923 goto validate_map_fail;
2924 }
2925 }
2926 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2927 DMA_RESV_USAGE_KERNEL, fence) {
2928 ret = amdgpu_sync_fence(&sync_obj, fence);
2929 if (ret) {
2930 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2931 goto validate_map_fail;
2932 }
2933 }
2934 }
2935
2936 if (failed_size)
2937 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2938
2939 /* Validate PDs, PTs and evicted DMABuf imports last. Otherwise BO
2940 * validations above would invalidate DMABuf imports again.
2941 */
2942 ret = process_validate_vms(process_info, &exec.ticket);
2943 if (ret) {
2944 pr_debug("Validating VMs failed, ret: %d\n", ret);
2945 goto validate_map_fail;
2946 }
2947
2948 /* Update mappings managed by KFD. */
2949 list_for_each_entry(mem, &process_info->kfd_bo_list,
2950 validate_list) {
2951 struct kfd_mem_attachment *attachment;
2952
2953 list_for_each_entry(attachment, &mem->attachments, list) {
2954 if (!attachment->is_mapped)
2955 continue;
2956
2957 if (attachment->bo_va->base.bo->tbo.pin_count)
2958 continue;
2959
2960 kfd_mem_dmaunmap_attachment(mem, attachment);
2961 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2962 if (ret) {
2963 pr_debug("Memory eviction: update PTE failed. Try again\n");
2964 goto validate_map_fail;
2965 }
2966 }
2967 }
2968
2969 /* Update mappings not managed by KFD */
2970 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2971 vm_list_node) {
2972 struct amdgpu_device *adev = amdgpu_ttm_adev(
2973 peer_vm->root.bo->tbo.bdev);
2974
2975 ret = amdgpu_vm_handle_moved(adev, peer_vm, &exec.ticket);
2976 if (ret) {
2977 pr_debug("Memory eviction: handle moved failed. Try again\n");
2978 goto validate_map_fail;
2979 }
2980 }
2981
2982 /* Update page directories */
2983 ret = process_update_pds(process_info, &sync_obj);
2984 if (ret) {
2985 pr_debug("Memory eviction: update PDs failed. Try again\n");
2986 goto validate_map_fail;
2987 }
2988
2989 /* Sync with fences on all the page tables. They implicitly depend on any
2990 * move fences from amdgpu_vm_handle_moved above.
2991 */
2992 ret = process_sync_pds_resv(process_info, &sync_obj);
2993 if (ret) {
2994 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2995 goto validate_map_fail;
2996 }
2997
2998 /* Wait for validate and PT updates to finish */
2999 amdgpu_sync_wait(&sync_obj, false);
3000
3001 /* The old eviction fence may be unsignaled if restore happens
3002 * after a GPU reset or suspend/resume. Keep the old fence in that
3003 * case. Otherwise release the old eviction fence and create new
3004 * one, because fence only goes from unsignaled to signaled once
3005 * and cannot be reused. Use context and mm from the old fence.
3006 *
3007 * If an old eviction fence signals after this check, that's OK.
3008 * Anyone signaling an eviction fence must stop the queues first
3009 * and schedule another restore worker.
3010 */
3011 if (dma_fence_is_signaled(&process_info->eviction_fence->base)) {
3012 struct amdgpu_amdkfd_fence *new_fence =
3013 amdgpu_amdkfd_fence_create(
3014 process_info->eviction_fence->base.context,
3015 process_info->eviction_fence->mm,
3016 NULL);
3017
3018 if (!new_fence) {
3019 pr_err("Failed to create eviction fence\n");
3020 ret = -ENOMEM;
3021 goto validate_map_fail;
3022 }
3023 dma_fence_put(&process_info->eviction_fence->base);
3024 process_info->eviction_fence = new_fence;
3025 replace_eviction_fence(ef, dma_fence_get(&new_fence->base));
3026 } else {
3027 WARN_ONCE(*ef != &process_info->eviction_fence->base,
3028 "KFD eviction fence doesn't match KGD process_info");
3029 }
3030
3031 /* Attach new eviction fence to all BOs except pinned ones */
3032 list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
3033 if (mem->bo->tbo.pin_count)
3034 continue;
3035
3036 dma_resv_add_fence(mem->bo->tbo.base.resv,
3037 &process_info->eviction_fence->base,
3038 DMA_RESV_USAGE_BOOKKEEP);
3039 }
3040 /* Attach eviction fence to PD / PT BOs and DMABuf imports */
3041 list_for_each_entry(peer_vm, &process_info->vm_list_head,
3042 vm_list_node) {
3043 struct amdgpu_bo *bo = peer_vm->root.bo;
3044
3045 dma_resv_add_fence(bo->tbo.base.resv,
3046 &process_info->eviction_fence->base,
3047 DMA_RESV_USAGE_BOOKKEEP);
3048 }
3049
3050validate_map_fail:
3051 amdgpu_sync_free(&sync_obj);
3052ttm_reserve_fail:
3053 drm_exec_fini(&exec);
3054 mutex_unlock(&process_info->lock);
3055 return ret;
3056}
3057
3058int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
3059{
3060 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3061 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
3062 int ret;
3063
3064 if (!info || !gws)
3065 return -EINVAL;
3066
3067 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
3068 if (!*mem)
3069 return -ENOMEM;
3070
3071 mutex_init(&(*mem)->lock);
3072 INIT_LIST_HEAD(&(*mem)->attachments);
3073 (*mem)->bo = amdgpu_bo_ref(gws_bo);
3074 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
3075 (*mem)->process_info = process_info;
3076 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
3077 amdgpu_sync_create(&(*mem)->sync);
3078
3079
3080 /* Validate gws bo the first time it is added to process */
3081 mutex_lock(&(*mem)->process_info->lock);
3082 ret = amdgpu_bo_reserve(gws_bo, false);
3083 if (unlikely(ret)) {
3084 pr_err("Reserve gws bo failed %d\n", ret);
3085 goto bo_reservation_failure;
3086 }
3087
3088 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
3089 if (ret) {
3090 pr_err("GWS BO validate failed %d\n", ret);
3091 goto bo_validation_failure;
3092 }
3093 /* GWS resource is shared b/t amdgpu and amdkfd
3094 * Add process eviction fence to bo so they can
3095 * evict each other.
3096 */
3097 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
3098 if (ret)
3099 goto reserve_shared_fail;
3100 dma_resv_add_fence(gws_bo->tbo.base.resv,
3101 &process_info->eviction_fence->base,
3102 DMA_RESV_USAGE_BOOKKEEP);
3103 amdgpu_bo_unreserve(gws_bo);
3104 mutex_unlock(&(*mem)->process_info->lock);
3105
3106 return ret;
3107
3108reserve_shared_fail:
3109bo_validation_failure:
3110 amdgpu_bo_unreserve(gws_bo);
3111bo_reservation_failure:
3112 mutex_unlock(&(*mem)->process_info->lock);
3113 amdgpu_sync_free(&(*mem)->sync);
3114 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
3115 amdgpu_bo_unref(&gws_bo);
3116 mutex_destroy(&(*mem)->lock);
3117 kfree(*mem);
3118 *mem = NULL;
3119 return ret;
3120}
3121
3122int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
3123{
3124 int ret;
3125 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3126 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
3127 struct amdgpu_bo *gws_bo = kgd_mem->bo;
3128
3129 /* Remove BO from process's validate list so restore worker won't touch
3130 * it anymore
3131 */
3132 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
3133
3134 ret = amdgpu_bo_reserve(gws_bo, false);
3135 if (unlikely(ret)) {
3136 pr_err("Reserve gws bo failed %d\n", ret);
3137 //TODO add BO back to validate_list?
3138 return ret;
3139 }
3140 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
3141 process_info->eviction_fence);
3142 amdgpu_bo_unreserve(gws_bo);
3143 amdgpu_sync_free(&kgd_mem->sync);
3144 amdgpu_bo_unref(&gws_bo);
3145 mutex_destroy(&kgd_mem->lock);
3146 kfree(mem);
3147 return 0;
3148}
3149
3150/* Returns GPU-specific tiling mode information */
3151int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
3152 struct tile_config *config)
3153{
3154 config->gb_addr_config = adev->gfx.config.gb_addr_config;
3155 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
3156 config->num_tile_configs =
3157 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
3158 config->macro_tile_config_ptr =
3159 adev->gfx.config.macrotile_mode_array;
3160 config->num_macro_tile_configs =
3161 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
3162
3163 /* Those values are not set from GFX9 onwards */
3164 config->num_banks = adev->gfx.config.num_banks;
3165 config->num_ranks = adev->gfx.config.num_ranks;
3166
3167 return 0;
3168}
3169
3170bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
3171{
3172 struct kfd_mem_attachment *entry;
3173
3174 list_for_each_entry(entry, &mem->attachments, list) {
3175 if (entry->is_mapped && entry->adev == adev)
3176 return true;
3177 }
3178 return false;
3179}
3180
3181#if defined(CONFIG_DEBUG_FS)
3182
3183int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3184{
3185
3186 spin_lock(&kfd_mem_limit.mem_limit_lock);
3187 seq_printf(m, "System mem used %lldM out of %lluM\n",
3188 (kfd_mem_limit.system_mem_used >> 20),
3189 (kfd_mem_limit.max_system_mem_limit >> 20));
3190 seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3191 (kfd_mem_limit.ttm_mem_used >> 20),
3192 (kfd_mem_limit.max_ttm_mem_limit >> 20));
3193 spin_unlock(&kfd_mem_limit.mem_limit_lock);
3194
3195 return 0;
3196}
3197
3198#endif
1/*
2 * Copyright 2014-2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include <linux/dma-buf.h>
23#include <linux/list.h>
24#include <linux/pagemap.h>
25#include <linux/sched/mm.h>
26#include <linux/sched/task.h>
27
28#include "amdgpu_object.h"
29#include "amdgpu_gem.h"
30#include "amdgpu_vm.h"
31#include "amdgpu_amdkfd.h"
32#include "amdgpu_dma_buf.h"
33#include <uapi/linux/kfd_ioctl.h>
34#include "amdgpu_xgmi.h"
35
36/* Userptr restore delay, just long enough to allow consecutive VM
37 * changes to accumulate
38 */
39#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
40
41/* Impose limit on how much memory KFD can use */
42static struct {
43 uint64_t max_system_mem_limit;
44 uint64_t max_ttm_mem_limit;
45 int64_t system_mem_used;
46 int64_t ttm_mem_used;
47 spinlock_t mem_limit_lock;
48} kfd_mem_limit;
49
50static const char * const domain_bit_to_string[] = {
51 "CPU",
52 "GTT",
53 "VRAM",
54 "GDS",
55 "GWS",
56 "OA"
57};
58
59#define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
60
61static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
62
63
64static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
65{
66 return (struct amdgpu_device *)kgd;
67}
68
69static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
70 struct kgd_mem *mem)
71{
72 struct kfd_mem_attachment *entry;
73
74 list_for_each_entry(entry, &mem->attachments, list)
75 if (entry->bo_va->base.vm == avm)
76 return true;
77
78 return false;
79}
80
81/* Set memory usage limits. Current, limits are
82 * System (TTM + userptr) memory - 15/16th System RAM
83 * TTM memory - 3/8th System RAM
84 */
85void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
86{
87 struct sysinfo si;
88 uint64_t mem;
89
90 si_meminfo(&si);
91 mem = si.freeram - si.freehigh;
92 mem *= si.mem_unit;
93
94 spin_lock_init(&kfd_mem_limit.mem_limit_lock);
95 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
96 kfd_mem_limit.max_ttm_mem_limit = (mem >> 1) - (mem >> 3);
97 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
98 (kfd_mem_limit.max_system_mem_limit >> 20),
99 (kfd_mem_limit.max_ttm_mem_limit >> 20));
100}
101
102void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
103{
104 kfd_mem_limit.system_mem_used += size;
105}
106
107/* Estimate page table size needed to represent a given memory size
108 *
109 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
110 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
111 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
112 * for 2MB pages for TLB efficiency. However, small allocations and
113 * fragmented system memory still need some 4KB pages. We choose a
114 * compromise that should work in most cases without reserving too
115 * much memory for page tables unnecessarily (factor 16K, >> 14).
116 */
117#define ESTIMATE_PT_SIZE(mem_size) ((mem_size) >> 14)
118
119static size_t amdgpu_amdkfd_acc_size(uint64_t size)
120{
121 size >>= PAGE_SHIFT;
122 size *= sizeof(dma_addr_t) + sizeof(void *);
123
124 return __roundup_pow_of_two(sizeof(struct amdgpu_bo)) +
125 __roundup_pow_of_two(sizeof(struct ttm_tt)) +
126 PAGE_ALIGN(size);
127}
128
129static int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
130 uint64_t size, u32 domain, bool sg)
131{
132 uint64_t reserved_for_pt =
133 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
134 size_t acc_size, system_mem_needed, ttm_mem_needed, vram_needed;
135 int ret = 0;
136
137 acc_size = amdgpu_amdkfd_acc_size(size);
138
139 vram_needed = 0;
140 if (domain == AMDGPU_GEM_DOMAIN_GTT) {
141 /* TTM GTT memory */
142 system_mem_needed = acc_size + size;
143 ttm_mem_needed = acc_size + size;
144 } else if (domain == AMDGPU_GEM_DOMAIN_CPU && !sg) {
145 /* Userptr */
146 system_mem_needed = acc_size + size;
147 ttm_mem_needed = acc_size;
148 } else {
149 /* VRAM and SG */
150 system_mem_needed = acc_size;
151 ttm_mem_needed = acc_size;
152 if (domain == AMDGPU_GEM_DOMAIN_VRAM)
153 vram_needed = size;
154 }
155
156 spin_lock(&kfd_mem_limit.mem_limit_lock);
157
158 if (kfd_mem_limit.system_mem_used + system_mem_needed >
159 kfd_mem_limit.max_system_mem_limit)
160 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
161
162 if ((kfd_mem_limit.system_mem_used + system_mem_needed >
163 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
164 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
165 kfd_mem_limit.max_ttm_mem_limit) ||
166 (adev->kfd.vram_used + vram_needed >
167 adev->gmc.real_vram_size - reserved_for_pt)) {
168 ret = -ENOMEM;
169 } else {
170 kfd_mem_limit.system_mem_used += system_mem_needed;
171 kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
172 adev->kfd.vram_used += vram_needed;
173 }
174
175 spin_unlock(&kfd_mem_limit.mem_limit_lock);
176 return ret;
177}
178
179static void unreserve_mem_limit(struct amdgpu_device *adev,
180 uint64_t size, u32 domain, bool sg)
181{
182 size_t acc_size;
183
184 acc_size = amdgpu_amdkfd_acc_size(size);
185
186 spin_lock(&kfd_mem_limit.mem_limit_lock);
187 if (domain == AMDGPU_GEM_DOMAIN_GTT) {
188 kfd_mem_limit.system_mem_used -= (acc_size + size);
189 kfd_mem_limit.ttm_mem_used -= (acc_size + size);
190 } else if (domain == AMDGPU_GEM_DOMAIN_CPU && !sg) {
191 kfd_mem_limit.system_mem_used -= (acc_size + size);
192 kfd_mem_limit.ttm_mem_used -= acc_size;
193 } else {
194 kfd_mem_limit.system_mem_used -= acc_size;
195 kfd_mem_limit.ttm_mem_used -= acc_size;
196 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
197 adev->kfd.vram_used -= size;
198 WARN_ONCE(adev->kfd.vram_used < 0,
199 "kfd VRAM memory accounting unbalanced");
200 }
201 }
202 WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
203 "kfd system memory accounting unbalanced");
204 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
205 "kfd TTM memory accounting unbalanced");
206
207 spin_unlock(&kfd_mem_limit.mem_limit_lock);
208}
209
210void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
211{
212 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
213 u32 domain = bo->preferred_domains;
214 bool sg = (bo->preferred_domains == AMDGPU_GEM_DOMAIN_CPU);
215
216 if (bo->flags & AMDGPU_AMDKFD_CREATE_USERPTR_BO) {
217 domain = AMDGPU_GEM_DOMAIN_CPU;
218 sg = false;
219 }
220
221 unreserve_mem_limit(adev, amdgpu_bo_size(bo), domain, sg);
222}
223
224
225/* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
226 * reservation object.
227 *
228 * @bo: [IN] Remove eviction fence(s) from this BO
229 * @ef: [IN] This eviction fence is removed if it
230 * is present in the shared list.
231 *
232 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
233 */
234static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
235 struct amdgpu_amdkfd_fence *ef)
236{
237 struct dma_resv *resv = bo->tbo.base.resv;
238 struct dma_resv_list *old, *new;
239 unsigned int i, j, k;
240
241 if (!ef)
242 return -EINVAL;
243
244 old = dma_resv_shared_list(resv);
245 if (!old)
246 return 0;
247
248 new = kmalloc(struct_size(new, shared, old->shared_max), GFP_KERNEL);
249 if (!new)
250 return -ENOMEM;
251
252 /* Go through all the shared fences in the resevation object and sort
253 * the interesting ones to the end of the list.
254 */
255 for (i = 0, j = old->shared_count, k = 0; i < old->shared_count; ++i) {
256 struct dma_fence *f;
257
258 f = rcu_dereference_protected(old->shared[i],
259 dma_resv_held(resv));
260
261 if (f->context == ef->base.context)
262 RCU_INIT_POINTER(new->shared[--j], f);
263 else
264 RCU_INIT_POINTER(new->shared[k++], f);
265 }
266 new->shared_max = old->shared_max;
267 new->shared_count = k;
268
269 /* Install the new fence list, seqcount provides the barriers */
270 write_seqcount_begin(&resv->seq);
271 RCU_INIT_POINTER(resv->fence, new);
272 write_seqcount_end(&resv->seq);
273
274 /* Drop the references to the removed fences or move them to ef_list */
275 for (i = j; i < old->shared_count; ++i) {
276 struct dma_fence *f;
277
278 f = rcu_dereference_protected(new->shared[i],
279 dma_resv_held(resv));
280 dma_fence_put(f);
281 }
282 kfree_rcu(old, rcu);
283
284 return 0;
285}
286
287int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
288{
289 struct amdgpu_bo *root = bo;
290 struct amdgpu_vm_bo_base *vm_bo;
291 struct amdgpu_vm *vm;
292 struct amdkfd_process_info *info;
293 struct amdgpu_amdkfd_fence *ef;
294 int ret;
295
296 /* we can always get vm_bo from root PD bo.*/
297 while (root->parent)
298 root = root->parent;
299
300 vm_bo = root->vm_bo;
301 if (!vm_bo)
302 return 0;
303
304 vm = vm_bo->vm;
305 if (!vm)
306 return 0;
307
308 info = vm->process_info;
309 if (!info || !info->eviction_fence)
310 return 0;
311
312 ef = container_of(dma_fence_get(&info->eviction_fence->base),
313 struct amdgpu_amdkfd_fence, base);
314
315 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
316 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
317 dma_resv_unlock(bo->tbo.base.resv);
318
319 dma_fence_put(&ef->base);
320 return ret;
321}
322
323static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
324 bool wait)
325{
326 struct ttm_operation_ctx ctx = { false, false };
327 int ret;
328
329 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
330 "Called with userptr BO"))
331 return -EINVAL;
332
333 amdgpu_bo_placement_from_domain(bo, domain);
334
335 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
336 if (ret)
337 goto validate_fail;
338 if (wait)
339 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
340
341validate_fail:
342 return ret;
343}
344
345static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
346{
347 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
348}
349
350/* vm_validate_pt_pd_bos - Validate page table and directory BOs
351 *
352 * Page directories are not updated here because huge page handling
353 * during page table updates can invalidate page directory entries
354 * again. Page directories are only updated after updating page
355 * tables.
356 */
357static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
358{
359 struct amdgpu_bo *pd = vm->root.bo;
360 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
361 int ret;
362
363 ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
364 if (ret) {
365 pr_err("failed to validate PT BOs\n");
366 return ret;
367 }
368
369 ret = amdgpu_amdkfd_validate_vm_bo(NULL, pd);
370 if (ret) {
371 pr_err("failed to validate PD\n");
372 return ret;
373 }
374
375 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
376
377 if (vm->use_cpu_for_update) {
378 ret = amdgpu_bo_kmap(pd, NULL);
379 if (ret) {
380 pr_err("failed to kmap PD, ret=%d\n", ret);
381 return ret;
382 }
383 }
384
385 return 0;
386}
387
388static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
389{
390 struct amdgpu_bo *pd = vm->root.bo;
391 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
392 int ret;
393
394 ret = amdgpu_vm_update_pdes(adev, vm, false);
395 if (ret)
396 return ret;
397
398 return amdgpu_sync_fence(sync, vm->last_update);
399}
400
401static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
402{
403 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
404 bool coherent = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT;
405 bool uncached = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED;
406 uint32_t mapping_flags;
407 uint64_t pte_flags;
408 bool snoop = false;
409
410 mapping_flags = AMDGPU_VM_PAGE_READABLE;
411 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
412 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
413 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
414 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
415
416 switch (adev->asic_type) {
417 case CHIP_ARCTURUS:
418 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
419 if (bo_adev == adev)
420 mapping_flags |= coherent ?
421 AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
422 else
423 mapping_flags |= coherent ?
424 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
425 } else {
426 mapping_flags |= coherent ?
427 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
428 }
429 break;
430 case CHIP_ALDEBARAN:
431 if (coherent && uncached) {
432 if (adev->gmc.xgmi.connected_to_cpu ||
433 !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM))
434 snoop = true;
435 mapping_flags |= AMDGPU_VM_MTYPE_UC;
436 } else if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
437 if (bo_adev == adev) {
438 mapping_flags |= coherent ?
439 AMDGPU_VM_MTYPE_CC : AMDGPU_VM_MTYPE_RW;
440 if (adev->gmc.xgmi.connected_to_cpu)
441 snoop = true;
442 } else {
443 mapping_flags |= coherent ?
444 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
445 if (amdgpu_xgmi_same_hive(adev, bo_adev))
446 snoop = true;
447 }
448 } else {
449 snoop = true;
450 mapping_flags |= coherent ?
451 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
452 }
453 break;
454 default:
455 mapping_flags |= coherent ?
456 AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
457 }
458
459 pte_flags = amdgpu_gem_va_map_flags(adev, mapping_flags);
460 pte_flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
461
462 return pte_flags;
463}
464
465static int
466kfd_mem_dmamap_userptr(struct kgd_mem *mem,
467 struct kfd_mem_attachment *attachment)
468{
469 enum dma_data_direction direction =
470 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
471 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
472 struct ttm_operation_ctx ctx = {.interruptible = true};
473 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
474 struct amdgpu_device *adev = attachment->adev;
475 struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
476 struct ttm_tt *ttm = bo->tbo.ttm;
477 int ret;
478
479 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
480 if (unlikely(!ttm->sg))
481 return -ENOMEM;
482
483 if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
484 return -EINVAL;
485
486 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
487 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
488 ttm->num_pages, 0,
489 (u64)ttm->num_pages << PAGE_SHIFT,
490 GFP_KERNEL);
491 if (unlikely(ret))
492 goto free_sg;
493
494 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
495 if (unlikely(ret))
496 goto release_sg;
497
498 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm->dma_address,
499 ttm->num_pages);
500
501 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
502 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
503 if (ret)
504 goto unmap_sg;
505
506 return 0;
507
508unmap_sg:
509 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
510release_sg:
511 pr_err("DMA map userptr failed: %d\n", ret);
512 sg_free_table(ttm->sg);
513free_sg:
514 kfree(ttm->sg);
515 ttm->sg = NULL;
516 return ret;
517}
518
519static int
520kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
521{
522 struct ttm_operation_ctx ctx = {.interruptible = true};
523 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
524
525 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
526 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
527}
528
529static int
530kfd_mem_dmamap_attachment(struct kgd_mem *mem,
531 struct kfd_mem_attachment *attachment)
532{
533 switch (attachment->type) {
534 case KFD_MEM_ATT_SHARED:
535 return 0;
536 case KFD_MEM_ATT_USERPTR:
537 return kfd_mem_dmamap_userptr(mem, attachment);
538 case KFD_MEM_ATT_DMABUF:
539 return kfd_mem_dmamap_dmabuf(attachment);
540 default:
541 WARN_ON_ONCE(1);
542 }
543 return -EINVAL;
544}
545
546static void
547kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
548 struct kfd_mem_attachment *attachment)
549{
550 enum dma_data_direction direction =
551 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
552 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
553 struct ttm_operation_ctx ctx = {.interruptible = false};
554 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
555 struct amdgpu_device *adev = attachment->adev;
556 struct ttm_tt *ttm = bo->tbo.ttm;
557
558 if (unlikely(!ttm->sg))
559 return;
560
561 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
562 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
563
564 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
565 sg_free_table(ttm->sg);
566 kfree(ttm->sg);
567 ttm->sg = NULL;
568}
569
570static void
571kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
572{
573 struct ttm_operation_ctx ctx = {.interruptible = true};
574 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
575
576 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
577 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
578}
579
580static void
581kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
582 struct kfd_mem_attachment *attachment)
583{
584 switch (attachment->type) {
585 case KFD_MEM_ATT_SHARED:
586 break;
587 case KFD_MEM_ATT_USERPTR:
588 kfd_mem_dmaunmap_userptr(mem, attachment);
589 break;
590 case KFD_MEM_ATT_DMABUF:
591 kfd_mem_dmaunmap_dmabuf(attachment);
592 break;
593 default:
594 WARN_ON_ONCE(1);
595 }
596}
597
598static int
599kfd_mem_attach_userptr(struct amdgpu_device *adev, struct kgd_mem *mem,
600 struct amdgpu_bo **bo)
601{
602 unsigned long bo_size = mem->bo->tbo.base.size;
603 struct drm_gem_object *gobj;
604 int ret;
605
606 ret = amdgpu_bo_reserve(mem->bo, false);
607 if (ret)
608 return ret;
609
610 ret = amdgpu_gem_object_create(adev, bo_size, 1,
611 AMDGPU_GEM_DOMAIN_CPU,
612 AMDGPU_GEM_CREATE_PREEMPTIBLE,
613 ttm_bo_type_sg, mem->bo->tbo.base.resv,
614 &gobj);
615 amdgpu_bo_unreserve(mem->bo);
616 if (ret)
617 return ret;
618
619 *bo = gem_to_amdgpu_bo(gobj);
620 (*bo)->parent = amdgpu_bo_ref(mem->bo);
621
622 return 0;
623}
624
625static int
626kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
627 struct amdgpu_bo **bo)
628{
629 struct drm_gem_object *gobj;
630 int ret;
631
632 if (!mem->dmabuf) {
633 mem->dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base,
634 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
635 DRM_RDWR : 0);
636 if (IS_ERR(mem->dmabuf)) {
637 ret = PTR_ERR(mem->dmabuf);
638 mem->dmabuf = NULL;
639 return ret;
640 }
641 }
642
643 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
644 if (IS_ERR(gobj))
645 return PTR_ERR(gobj);
646
647 /* Import takes an extra reference on the dmabuf. Drop it now to
648 * avoid leaking it. We only need the one reference in
649 * kgd_mem->dmabuf.
650 */
651 dma_buf_put(mem->dmabuf);
652
653 *bo = gem_to_amdgpu_bo(gobj);
654 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
655 (*bo)->parent = amdgpu_bo_ref(mem->bo);
656
657 return 0;
658}
659
660/* kfd_mem_attach - Add a BO to a VM
661 *
662 * Everything that needs to bo done only once when a BO is first added
663 * to a VM. It can later be mapped and unmapped many times without
664 * repeating these steps.
665 *
666 * 0. Create BO for DMA mapping, if needed
667 * 1. Allocate and initialize BO VA entry data structure
668 * 2. Add BO to the VM
669 * 3. Determine ASIC-specific PTE flags
670 * 4. Alloc page tables and directories if needed
671 * 4a. Validate new page tables and directories
672 */
673static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
674 struct amdgpu_vm *vm, bool is_aql)
675{
676 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
677 unsigned long bo_size = mem->bo->tbo.base.size;
678 uint64_t va = mem->va;
679 struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
680 struct amdgpu_bo *bo[2] = {NULL, NULL};
681 int i, ret;
682
683 if (!va) {
684 pr_err("Invalid VA when adding BO to VM\n");
685 return -EINVAL;
686 }
687
688 for (i = 0; i <= is_aql; i++) {
689 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
690 if (unlikely(!attachment[i])) {
691 ret = -ENOMEM;
692 goto unwind;
693 }
694
695 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
696 va + bo_size, vm);
697
698 if (adev == bo_adev || (mem->domain == AMDGPU_GEM_DOMAIN_VRAM &&
699 amdgpu_xgmi_same_hive(adev, bo_adev))) {
700 /* Mappings on the local GPU and VRAM mappings in the
701 * local hive share the original BO
702 */
703 attachment[i]->type = KFD_MEM_ATT_SHARED;
704 bo[i] = mem->bo;
705 drm_gem_object_get(&bo[i]->tbo.base);
706 } else if (i > 0) {
707 /* Multiple mappings on the same GPU share the BO */
708 attachment[i]->type = KFD_MEM_ATT_SHARED;
709 bo[i] = bo[0];
710 drm_gem_object_get(&bo[i]->tbo.base);
711 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
712 /* Create an SG BO to DMA-map userptrs on other GPUs */
713 attachment[i]->type = KFD_MEM_ATT_USERPTR;
714 ret = kfd_mem_attach_userptr(adev, mem, &bo[i]);
715 if (ret)
716 goto unwind;
717 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT &&
718 mem->bo->tbo.type != ttm_bo_type_sg) {
719 /* GTT BOs use DMA-mapping ability of dynamic-attach
720 * DMA bufs. TODO: The same should work for VRAM on
721 * large-BAR GPUs.
722 */
723 attachment[i]->type = KFD_MEM_ATT_DMABUF;
724 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
725 if (ret)
726 goto unwind;
727 } else {
728 /* FIXME: Need to DMA-map other BO types:
729 * large-BAR VRAM, doorbells, MMIO remap
730 */
731 attachment[i]->type = KFD_MEM_ATT_SHARED;
732 bo[i] = mem->bo;
733 drm_gem_object_get(&bo[i]->tbo.base);
734 }
735
736 /* Add BO to VM internal data structures */
737 attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
738 if (unlikely(!attachment[i]->bo_va)) {
739 ret = -ENOMEM;
740 pr_err("Failed to add BO object to VM. ret == %d\n",
741 ret);
742 goto unwind;
743 }
744
745 attachment[i]->va = va;
746 attachment[i]->pte_flags = get_pte_flags(adev, mem);
747 attachment[i]->adev = adev;
748 list_add(&attachment[i]->list, &mem->attachments);
749
750 va += bo_size;
751 }
752
753 return 0;
754
755unwind:
756 for (; i >= 0; i--) {
757 if (!attachment[i])
758 continue;
759 if (attachment[i]->bo_va) {
760 amdgpu_vm_bo_rmv(adev, attachment[i]->bo_va);
761 list_del(&attachment[i]->list);
762 }
763 if (bo[i])
764 drm_gem_object_put(&bo[i]->tbo.base);
765 kfree(attachment[i]);
766 }
767 return ret;
768}
769
770static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
771{
772 struct amdgpu_bo *bo = attachment->bo_va->base.bo;
773
774 pr_debug("\t remove VA 0x%llx in entry %p\n",
775 attachment->va, attachment);
776 amdgpu_vm_bo_rmv(attachment->adev, attachment->bo_va);
777 drm_gem_object_put(&bo->tbo.base);
778 list_del(&attachment->list);
779 kfree(attachment);
780}
781
782static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
783 struct amdkfd_process_info *process_info,
784 bool userptr)
785{
786 struct ttm_validate_buffer *entry = &mem->validate_list;
787 struct amdgpu_bo *bo = mem->bo;
788
789 INIT_LIST_HEAD(&entry->head);
790 entry->num_shared = 1;
791 entry->bo = &bo->tbo;
792 mutex_lock(&process_info->lock);
793 if (userptr)
794 list_add_tail(&entry->head, &process_info->userptr_valid_list);
795 else
796 list_add_tail(&entry->head, &process_info->kfd_bo_list);
797 mutex_unlock(&process_info->lock);
798}
799
800static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
801 struct amdkfd_process_info *process_info)
802{
803 struct ttm_validate_buffer *bo_list_entry;
804
805 bo_list_entry = &mem->validate_list;
806 mutex_lock(&process_info->lock);
807 list_del(&bo_list_entry->head);
808 mutex_unlock(&process_info->lock);
809}
810
811/* Initializes user pages. It registers the MMU notifier and validates
812 * the userptr BO in the GTT domain.
813 *
814 * The BO must already be on the userptr_valid_list. Otherwise an
815 * eviction and restore may happen that leaves the new BO unmapped
816 * with the user mode queues running.
817 *
818 * Takes the process_info->lock to protect against concurrent restore
819 * workers.
820 *
821 * Returns 0 for success, negative errno for errors.
822 */
823static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr)
824{
825 struct amdkfd_process_info *process_info = mem->process_info;
826 struct amdgpu_bo *bo = mem->bo;
827 struct ttm_operation_ctx ctx = { true, false };
828 int ret = 0;
829
830 mutex_lock(&process_info->lock);
831
832 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
833 if (ret) {
834 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
835 goto out;
836 }
837
838 ret = amdgpu_mn_register(bo, user_addr);
839 if (ret) {
840 pr_err("%s: Failed to register MMU notifier: %d\n",
841 __func__, ret);
842 goto out;
843 }
844
845 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
846 if (ret) {
847 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
848 goto unregister_out;
849 }
850
851 ret = amdgpu_bo_reserve(bo, true);
852 if (ret) {
853 pr_err("%s: Failed to reserve BO\n", __func__);
854 goto release_out;
855 }
856 amdgpu_bo_placement_from_domain(bo, mem->domain);
857 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
858 if (ret)
859 pr_err("%s: failed to validate BO\n", __func__);
860 amdgpu_bo_unreserve(bo);
861
862release_out:
863 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
864unregister_out:
865 if (ret)
866 amdgpu_mn_unregister(bo);
867out:
868 mutex_unlock(&process_info->lock);
869 return ret;
870}
871
872/* Reserving a BO and its page table BOs must happen atomically to
873 * avoid deadlocks. Some operations update multiple VMs at once. Track
874 * all the reservation info in a context structure. Optionally a sync
875 * object can track VM updates.
876 */
877struct bo_vm_reservation_context {
878 struct amdgpu_bo_list_entry kfd_bo; /* BO list entry for the KFD BO */
879 unsigned int n_vms; /* Number of VMs reserved */
880 struct amdgpu_bo_list_entry *vm_pd; /* Array of VM BO list entries */
881 struct ww_acquire_ctx ticket; /* Reservation ticket */
882 struct list_head list, duplicates; /* BO lists */
883 struct amdgpu_sync *sync; /* Pointer to sync object */
884 bool reserved; /* Whether BOs are reserved */
885};
886
887enum bo_vm_match {
888 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */
889 BO_VM_MAPPED, /* Match VMs where a BO is mapped */
890 BO_VM_ALL, /* Match all VMs a BO was added to */
891};
892
893/**
894 * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
895 * @mem: KFD BO structure.
896 * @vm: the VM to reserve.
897 * @ctx: the struct that will be used in unreserve_bo_and_vms().
898 */
899static int reserve_bo_and_vm(struct kgd_mem *mem,
900 struct amdgpu_vm *vm,
901 struct bo_vm_reservation_context *ctx)
902{
903 struct amdgpu_bo *bo = mem->bo;
904 int ret;
905
906 WARN_ON(!vm);
907
908 ctx->reserved = false;
909 ctx->n_vms = 1;
910 ctx->sync = &mem->sync;
911
912 INIT_LIST_HEAD(&ctx->list);
913 INIT_LIST_HEAD(&ctx->duplicates);
914
915 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd), GFP_KERNEL);
916 if (!ctx->vm_pd)
917 return -ENOMEM;
918
919 ctx->kfd_bo.priority = 0;
920 ctx->kfd_bo.tv.bo = &bo->tbo;
921 ctx->kfd_bo.tv.num_shared = 1;
922 list_add(&ctx->kfd_bo.tv.head, &ctx->list);
923
924 amdgpu_vm_get_pd_bo(vm, &ctx->list, &ctx->vm_pd[0]);
925
926 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
927 false, &ctx->duplicates);
928 if (ret) {
929 pr_err("Failed to reserve buffers in ttm.\n");
930 kfree(ctx->vm_pd);
931 ctx->vm_pd = NULL;
932 return ret;
933 }
934
935 ctx->reserved = true;
936 return 0;
937}
938
939/**
940 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
941 * @mem: KFD BO structure.
942 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
943 * is used. Otherwise, a single VM associated with the BO.
944 * @map_type: the mapping status that will be used to filter the VMs.
945 * @ctx: the struct that will be used in unreserve_bo_and_vms().
946 *
947 * Returns 0 for success, negative for failure.
948 */
949static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
950 struct amdgpu_vm *vm, enum bo_vm_match map_type,
951 struct bo_vm_reservation_context *ctx)
952{
953 struct amdgpu_bo *bo = mem->bo;
954 struct kfd_mem_attachment *entry;
955 unsigned int i;
956 int ret;
957
958 ctx->reserved = false;
959 ctx->n_vms = 0;
960 ctx->vm_pd = NULL;
961 ctx->sync = &mem->sync;
962
963 INIT_LIST_HEAD(&ctx->list);
964 INIT_LIST_HEAD(&ctx->duplicates);
965
966 list_for_each_entry(entry, &mem->attachments, list) {
967 if ((vm && vm != entry->bo_va->base.vm) ||
968 (entry->is_mapped != map_type
969 && map_type != BO_VM_ALL))
970 continue;
971
972 ctx->n_vms++;
973 }
974
975 if (ctx->n_vms != 0) {
976 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd),
977 GFP_KERNEL);
978 if (!ctx->vm_pd)
979 return -ENOMEM;
980 }
981
982 ctx->kfd_bo.priority = 0;
983 ctx->kfd_bo.tv.bo = &bo->tbo;
984 ctx->kfd_bo.tv.num_shared = 1;
985 list_add(&ctx->kfd_bo.tv.head, &ctx->list);
986
987 i = 0;
988 list_for_each_entry(entry, &mem->attachments, list) {
989 if ((vm && vm != entry->bo_va->base.vm) ||
990 (entry->is_mapped != map_type
991 && map_type != BO_VM_ALL))
992 continue;
993
994 amdgpu_vm_get_pd_bo(entry->bo_va->base.vm, &ctx->list,
995 &ctx->vm_pd[i]);
996 i++;
997 }
998
999 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,
1000 false, &ctx->duplicates);
1001 if (ret) {
1002 pr_err("Failed to reserve buffers in ttm.\n");
1003 kfree(ctx->vm_pd);
1004 ctx->vm_pd = NULL;
1005 return ret;
1006 }
1007
1008 ctx->reserved = true;
1009 return 0;
1010}
1011
1012/**
1013 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1014 * @ctx: Reservation context to unreserve
1015 * @wait: Optionally wait for a sync object representing pending VM updates
1016 * @intr: Whether the wait is interruptible
1017 *
1018 * Also frees any resources allocated in
1019 * reserve_bo_and_(cond_)vm(s). Returns the status from
1020 * amdgpu_sync_wait.
1021 */
1022static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1023 bool wait, bool intr)
1024{
1025 int ret = 0;
1026
1027 if (wait)
1028 ret = amdgpu_sync_wait(ctx->sync, intr);
1029
1030 if (ctx->reserved)
1031 ttm_eu_backoff_reservation(&ctx->ticket, &ctx->list);
1032 kfree(ctx->vm_pd);
1033
1034 ctx->sync = NULL;
1035
1036 ctx->reserved = false;
1037 ctx->vm_pd = NULL;
1038
1039 return ret;
1040}
1041
1042static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1043 struct kfd_mem_attachment *entry,
1044 struct amdgpu_sync *sync)
1045{
1046 struct amdgpu_bo_va *bo_va = entry->bo_va;
1047 struct amdgpu_device *adev = entry->adev;
1048 struct amdgpu_vm *vm = bo_va->base.vm;
1049
1050 amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1051
1052 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1053
1054 amdgpu_sync_fence(sync, bo_va->last_pt_update);
1055
1056 kfd_mem_dmaunmap_attachment(mem, entry);
1057}
1058
1059static int update_gpuvm_pte(struct kgd_mem *mem,
1060 struct kfd_mem_attachment *entry,
1061 struct amdgpu_sync *sync)
1062{
1063 struct amdgpu_bo_va *bo_va = entry->bo_va;
1064 struct amdgpu_device *adev = entry->adev;
1065 int ret;
1066
1067 ret = kfd_mem_dmamap_attachment(mem, entry);
1068 if (ret)
1069 return ret;
1070
1071 /* Update the page tables */
1072 ret = amdgpu_vm_bo_update(adev, bo_va, false);
1073 if (ret) {
1074 pr_err("amdgpu_vm_bo_update failed\n");
1075 return ret;
1076 }
1077
1078 return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1079}
1080
1081static int map_bo_to_gpuvm(struct kgd_mem *mem,
1082 struct kfd_mem_attachment *entry,
1083 struct amdgpu_sync *sync,
1084 bool no_update_pte)
1085{
1086 int ret;
1087
1088 /* Set virtual address for the allocation */
1089 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1090 amdgpu_bo_size(entry->bo_va->base.bo),
1091 entry->pte_flags);
1092 if (ret) {
1093 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1094 entry->va, ret);
1095 return ret;
1096 }
1097
1098 if (no_update_pte)
1099 return 0;
1100
1101 ret = update_gpuvm_pte(mem, entry, sync);
1102 if (ret) {
1103 pr_err("update_gpuvm_pte() failed\n");
1104 goto update_gpuvm_pte_failed;
1105 }
1106
1107 return 0;
1108
1109update_gpuvm_pte_failed:
1110 unmap_bo_from_gpuvm(mem, entry, sync);
1111 return ret;
1112}
1113
1114static struct sg_table *create_doorbell_sg(uint64_t addr, uint32_t size)
1115{
1116 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
1117
1118 if (!sg)
1119 return NULL;
1120 if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
1121 kfree(sg);
1122 return NULL;
1123 }
1124 sg->sgl->dma_address = addr;
1125 sg->sgl->length = size;
1126#ifdef CONFIG_NEED_SG_DMA_LENGTH
1127 sg->sgl->dma_length = size;
1128#endif
1129 return sg;
1130}
1131
1132static int process_validate_vms(struct amdkfd_process_info *process_info)
1133{
1134 struct amdgpu_vm *peer_vm;
1135 int ret;
1136
1137 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1138 vm_list_node) {
1139 ret = vm_validate_pt_pd_bos(peer_vm);
1140 if (ret)
1141 return ret;
1142 }
1143
1144 return 0;
1145}
1146
1147static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1148 struct amdgpu_sync *sync)
1149{
1150 struct amdgpu_vm *peer_vm;
1151 int ret;
1152
1153 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1154 vm_list_node) {
1155 struct amdgpu_bo *pd = peer_vm->root.bo;
1156
1157 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1158 AMDGPU_SYNC_NE_OWNER,
1159 AMDGPU_FENCE_OWNER_KFD);
1160 if (ret)
1161 return ret;
1162 }
1163
1164 return 0;
1165}
1166
1167static int process_update_pds(struct amdkfd_process_info *process_info,
1168 struct amdgpu_sync *sync)
1169{
1170 struct amdgpu_vm *peer_vm;
1171 int ret;
1172
1173 list_for_each_entry(peer_vm, &process_info->vm_list_head,
1174 vm_list_node) {
1175 ret = vm_update_pds(peer_vm, sync);
1176 if (ret)
1177 return ret;
1178 }
1179
1180 return 0;
1181}
1182
1183static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1184 struct dma_fence **ef)
1185{
1186 struct amdkfd_process_info *info = NULL;
1187 int ret;
1188
1189 if (!*process_info) {
1190 info = kzalloc(sizeof(*info), GFP_KERNEL);
1191 if (!info)
1192 return -ENOMEM;
1193
1194 mutex_init(&info->lock);
1195 INIT_LIST_HEAD(&info->vm_list_head);
1196 INIT_LIST_HEAD(&info->kfd_bo_list);
1197 INIT_LIST_HEAD(&info->userptr_valid_list);
1198 INIT_LIST_HEAD(&info->userptr_inval_list);
1199
1200 info->eviction_fence =
1201 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1202 current->mm,
1203 NULL);
1204 if (!info->eviction_fence) {
1205 pr_err("Failed to create eviction fence\n");
1206 ret = -ENOMEM;
1207 goto create_evict_fence_fail;
1208 }
1209
1210 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1211 atomic_set(&info->evicted_bos, 0);
1212 INIT_DELAYED_WORK(&info->restore_userptr_work,
1213 amdgpu_amdkfd_restore_userptr_worker);
1214
1215 *process_info = info;
1216 *ef = dma_fence_get(&info->eviction_fence->base);
1217 }
1218
1219 vm->process_info = *process_info;
1220
1221 /* Validate page directory and attach eviction fence */
1222 ret = amdgpu_bo_reserve(vm->root.bo, true);
1223 if (ret)
1224 goto reserve_pd_fail;
1225 ret = vm_validate_pt_pd_bos(vm);
1226 if (ret) {
1227 pr_err("validate_pt_pd_bos() failed\n");
1228 goto validate_pd_fail;
1229 }
1230 ret = amdgpu_bo_sync_wait(vm->root.bo,
1231 AMDGPU_FENCE_OWNER_KFD, false);
1232 if (ret)
1233 goto wait_pd_fail;
1234 ret = dma_resv_reserve_shared(vm->root.bo->tbo.base.resv, 1);
1235 if (ret)
1236 goto reserve_shared_fail;
1237 amdgpu_bo_fence(vm->root.bo,
1238 &vm->process_info->eviction_fence->base, true);
1239 amdgpu_bo_unreserve(vm->root.bo);
1240
1241 /* Update process info */
1242 mutex_lock(&vm->process_info->lock);
1243 list_add_tail(&vm->vm_list_node,
1244 &(vm->process_info->vm_list_head));
1245 vm->process_info->n_vms++;
1246 mutex_unlock(&vm->process_info->lock);
1247
1248 return 0;
1249
1250reserve_shared_fail:
1251wait_pd_fail:
1252validate_pd_fail:
1253 amdgpu_bo_unreserve(vm->root.bo);
1254reserve_pd_fail:
1255 vm->process_info = NULL;
1256 if (info) {
1257 /* Two fence references: one in info and one in *ef */
1258 dma_fence_put(&info->eviction_fence->base);
1259 dma_fence_put(*ef);
1260 *ef = NULL;
1261 *process_info = NULL;
1262 put_pid(info->pid);
1263create_evict_fence_fail:
1264 mutex_destroy(&info->lock);
1265 kfree(info);
1266 }
1267 return ret;
1268}
1269
1270int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
1271 struct file *filp, u32 pasid,
1272 void **process_info,
1273 struct dma_fence **ef)
1274{
1275 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1276 struct amdgpu_fpriv *drv_priv;
1277 struct amdgpu_vm *avm;
1278 int ret;
1279
1280 ret = amdgpu_file_to_fpriv(filp, &drv_priv);
1281 if (ret)
1282 return ret;
1283 avm = &drv_priv->vm;
1284
1285 /* Already a compute VM? */
1286 if (avm->process_info)
1287 return -EINVAL;
1288
1289 /* Convert VM into a compute VM */
1290 ret = amdgpu_vm_make_compute(adev, avm, pasid);
1291 if (ret)
1292 return ret;
1293
1294 /* Initialize KFD part of the VM and process info */
1295 ret = init_kfd_vm(avm, process_info, ef);
1296 if (ret)
1297 return ret;
1298
1299 amdgpu_vm_set_task_info(avm);
1300
1301 return 0;
1302}
1303
1304void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1305 struct amdgpu_vm *vm)
1306{
1307 struct amdkfd_process_info *process_info = vm->process_info;
1308 struct amdgpu_bo *pd = vm->root.bo;
1309
1310 if (!process_info)
1311 return;
1312
1313 /* Release eviction fence from PD */
1314 amdgpu_bo_reserve(pd, false);
1315 amdgpu_bo_fence(pd, NULL, false);
1316 amdgpu_bo_unreserve(pd);
1317
1318 /* Update process info */
1319 mutex_lock(&process_info->lock);
1320 process_info->n_vms--;
1321 list_del(&vm->vm_list_node);
1322 mutex_unlock(&process_info->lock);
1323
1324 vm->process_info = NULL;
1325
1326 /* Release per-process resources when last compute VM is destroyed */
1327 if (!process_info->n_vms) {
1328 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1329 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1330 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1331
1332 dma_fence_put(&process_info->eviction_fence->base);
1333 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1334 put_pid(process_info->pid);
1335 mutex_destroy(&process_info->lock);
1336 kfree(process_info);
1337 }
1338}
1339
1340void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv)
1341{
1342 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1343 struct amdgpu_vm *avm;
1344
1345 if (WARN_ON(!kgd || !drm_priv))
1346 return;
1347
1348 avm = drm_priv_to_vm(drm_priv);
1349
1350 pr_debug("Releasing process vm %p\n", avm);
1351
1352 /* The original pasid of amdgpu vm has already been
1353 * released during making a amdgpu vm to a compute vm
1354 * The current pasid is managed by kfd and will be
1355 * released on kfd process destroy. Set amdgpu pasid
1356 * to 0 to avoid duplicate release.
1357 */
1358 amdgpu_vm_release_compute(adev, avm);
1359}
1360
1361uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1362{
1363 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1364 struct amdgpu_bo *pd = avm->root.bo;
1365 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1366
1367 if (adev->asic_type < CHIP_VEGA10)
1368 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1369 return avm->pd_phys_addr;
1370}
1371
1372int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1373 struct kgd_dev *kgd, uint64_t va, uint64_t size,
1374 void *drm_priv, struct kgd_mem **mem,
1375 uint64_t *offset, uint32_t flags)
1376{
1377 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1378 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1379 enum ttm_bo_type bo_type = ttm_bo_type_device;
1380 struct sg_table *sg = NULL;
1381 uint64_t user_addr = 0;
1382 struct amdgpu_bo *bo;
1383 struct drm_gem_object *gobj;
1384 u32 domain, alloc_domain;
1385 u64 alloc_flags;
1386 int ret;
1387
1388 /*
1389 * Check on which domain to allocate BO
1390 */
1391 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1392 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1393 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1394 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1395 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1396 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1397 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1398 alloc_flags = 0;
1399 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1400 domain = AMDGPU_GEM_DOMAIN_GTT;
1401 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1402 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1403 if (!offset || !*offset)
1404 return -EINVAL;
1405 user_addr = untagged_addr(*offset);
1406 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1407 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1408 domain = AMDGPU_GEM_DOMAIN_GTT;
1409 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1410 bo_type = ttm_bo_type_sg;
1411 alloc_flags = 0;
1412 if (size > UINT_MAX)
1413 return -EINVAL;
1414 sg = create_doorbell_sg(*offset, size);
1415 if (!sg)
1416 return -ENOMEM;
1417 } else {
1418 return -EINVAL;
1419 }
1420
1421 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1422 if (!*mem) {
1423 ret = -ENOMEM;
1424 goto err;
1425 }
1426 INIT_LIST_HEAD(&(*mem)->attachments);
1427 mutex_init(&(*mem)->lock);
1428 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1429
1430 /* Workaround for AQL queue wraparound bug. Map the same
1431 * memory twice. That means we only actually allocate half
1432 * the memory.
1433 */
1434 if ((*mem)->aql_queue)
1435 size = size >> 1;
1436
1437 (*mem)->alloc_flags = flags;
1438
1439 amdgpu_sync_create(&(*mem)->sync);
1440
1441 ret = amdgpu_amdkfd_reserve_mem_limit(adev, size, alloc_domain, !!sg);
1442 if (ret) {
1443 pr_debug("Insufficient memory\n");
1444 goto err_reserve_limit;
1445 }
1446
1447 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
1448 va, size, domain_string(alloc_domain));
1449
1450 ret = amdgpu_gem_object_create(adev, size, 1, alloc_domain, alloc_flags,
1451 bo_type, NULL, &gobj);
1452 if (ret) {
1453 pr_debug("Failed to create BO on domain %s. ret %d\n",
1454 domain_string(alloc_domain), ret);
1455 goto err_bo_create;
1456 }
1457 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1458 if (ret) {
1459 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1460 goto err_node_allow;
1461 }
1462 bo = gem_to_amdgpu_bo(gobj);
1463 if (bo_type == ttm_bo_type_sg) {
1464 bo->tbo.sg = sg;
1465 bo->tbo.ttm->sg = sg;
1466 }
1467 bo->kfd_bo = *mem;
1468 (*mem)->bo = bo;
1469 if (user_addr)
1470 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1471
1472 (*mem)->va = va;
1473 (*mem)->domain = domain;
1474 (*mem)->mapped_to_gpu_memory = 0;
1475 (*mem)->process_info = avm->process_info;
1476 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1477
1478 if (user_addr) {
1479 ret = init_user_pages(*mem, user_addr);
1480 if (ret)
1481 goto allocate_init_user_pages_failed;
1482 }
1483
1484 if (offset)
1485 *offset = amdgpu_bo_mmap_offset(bo);
1486
1487 return 0;
1488
1489allocate_init_user_pages_failed:
1490 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1491 drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1492err_node_allow:
1493 amdgpu_bo_unref(&bo);
1494 /* Don't unreserve system mem limit twice */
1495 goto err_reserve_limit;
1496err_bo_create:
1497 unreserve_mem_limit(adev, size, alloc_domain, !!sg);
1498err_reserve_limit:
1499 mutex_destroy(&(*mem)->lock);
1500 kfree(*mem);
1501err:
1502 if (sg) {
1503 sg_free_table(sg);
1504 kfree(sg);
1505 }
1506 return ret;
1507}
1508
1509int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1510 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
1511 uint64_t *size)
1512{
1513 struct amdkfd_process_info *process_info = mem->process_info;
1514 unsigned long bo_size = mem->bo->tbo.base.size;
1515 struct kfd_mem_attachment *entry, *tmp;
1516 struct bo_vm_reservation_context ctx;
1517 struct ttm_validate_buffer *bo_list_entry;
1518 unsigned int mapped_to_gpu_memory;
1519 int ret;
1520 bool is_imported = false;
1521
1522 mutex_lock(&mem->lock);
1523 mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1524 is_imported = mem->is_imported;
1525 mutex_unlock(&mem->lock);
1526 /* lock is not needed after this, since mem is unused and will
1527 * be freed anyway
1528 */
1529
1530 if (mapped_to_gpu_memory > 0) {
1531 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1532 mem->va, bo_size);
1533 return -EBUSY;
1534 }
1535
1536 /* Make sure restore workers don't access the BO any more */
1537 bo_list_entry = &mem->validate_list;
1538 mutex_lock(&process_info->lock);
1539 list_del(&bo_list_entry->head);
1540 mutex_unlock(&process_info->lock);
1541
1542 /* No more MMU notifiers */
1543 amdgpu_mn_unregister(mem->bo);
1544
1545 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1546 if (unlikely(ret))
1547 return ret;
1548
1549 /* The eviction fence should be removed by the last unmap.
1550 * TODO: Log an error condition if the bo still has the eviction fence
1551 * attached
1552 */
1553 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1554 process_info->eviction_fence);
1555 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1556 mem->va + bo_size * (1 + mem->aql_queue));
1557
1558 ret = unreserve_bo_and_vms(&ctx, false, false);
1559
1560 /* Remove from VM internal data structures */
1561 list_for_each_entry_safe(entry, tmp, &mem->attachments, list)
1562 kfd_mem_detach(entry);
1563
1564 /* Free the sync object */
1565 amdgpu_sync_free(&mem->sync);
1566
1567 /* If the SG is not NULL, it's one we created for a doorbell or mmio
1568 * remap BO. We need to free it.
1569 */
1570 if (mem->bo->tbo.sg) {
1571 sg_free_table(mem->bo->tbo.sg);
1572 kfree(mem->bo->tbo.sg);
1573 }
1574
1575 /* Update the size of the BO being freed if it was allocated from
1576 * VRAM and is not imported.
1577 */
1578 if (size) {
1579 if ((mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) &&
1580 (!is_imported))
1581 *size = bo_size;
1582 else
1583 *size = 0;
1584 }
1585
1586 /* Free the BO*/
1587 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1588 if (mem->dmabuf)
1589 dma_buf_put(mem->dmabuf);
1590 drm_gem_object_put(&mem->bo->tbo.base);
1591 mutex_destroy(&mem->lock);
1592 kfree(mem);
1593
1594 return ret;
1595}
1596
1597int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1598 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
1599{
1600 struct amdgpu_device *adev = get_amdgpu_device(kgd);
1601 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1602 int ret;
1603 struct amdgpu_bo *bo;
1604 uint32_t domain;
1605 struct kfd_mem_attachment *entry;
1606 struct bo_vm_reservation_context ctx;
1607 unsigned long bo_size;
1608 bool is_invalid_userptr = false;
1609
1610 bo = mem->bo;
1611 if (!bo) {
1612 pr_err("Invalid BO when mapping memory to GPU\n");
1613 return -EINVAL;
1614 }
1615
1616 /* Make sure restore is not running concurrently. Since we
1617 * don't map invalid userptr BOs, we rely on the next restore
1618 * worker to do the mapping
1619 */
1620 mutex_lock(&mem->process_info->lock);
1621
1622 /* Lock mmap-sem. If we find an invalid userptr BO, we can be
1623 * sure that the MMU notifier is no longer running
1624 * concurrently and the queues are actually stopped
1625 */
1626 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1627 mmap_write_lock(current->mm);
1628 is_invalid_userptr = atomic_read(&mem->invalid);
1629 mmap_write_unlock(current->mm);
1630 }
1631
1632 mutex_lock(&mem->lock);
1633
1634 domain = mem->domain;
1635 bo_size = bo->tbo.base.size;
1636
1637 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
1638 mem->va,
1639 mem->va + bo_size * (1 + mem->aql_queue),
1640 avm, domain_string(domain));
1641
1642 if (!kfd_mem_is_attached(avm, mem)) {
1643 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
1644 if (ret)
1645 goto out;
1646 }
1647
1648 ret = reserve_bo_and_vm(mem, avm, &ctx);
1649 if (unlikely(ret))
1650 goto out;
1651
1652 /* Userptr can be marked as "not invalid", but not actually be
1653 * validated yet (still in the system domain). In that case
1654 * the queues are still stopped and we can leave mapping for
1655 * the next restore worker
1656 */
1657 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
1658 bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
1659 is_invalid_userptr = true;
1660
1661 ret = vm_validate_pt_pd_bos(avm);
1662 if (unlikely(ret))
1663 goto out_unreserve;
1664
1665 if (mem->mapped_to_gpu_memory == 0 &&
1666 !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1667 /* Validate BO only once. The eviction fence gets added to BO
1668 * the first time it is mapped. Validate will wait for all
1669 * background evictions to complete.
1670 */
1671 ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
1672 if (ret) {
1673 pr_debug("Validate failed\n");
1674 goto out_unreserve;
1675 }
1676 }
1677
1678 list_for_each_entry(entry, &mem->attachments, list) {
1679 if (entry->bo_va->base.vm != avm || entry->is_mapped)
1680 continue;
1681
1682 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
1683 entry->va, entry->va + bo_size, entry);
1684
1685 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
1686 is_invalid_userptr);
1687 if (ret) {
1688 pr_err("Failed to map bo to gpuvm\n");
1689 goto out_unreserve;
1690 }
1691
1692 ret = vm_update_pds(avm, ctx.sync);
1693 if (ret) {
1694 pr_err("Failed to update page directories\n");
1695 goto out_unreserve;
1696 }
1697
1698 entry->is_mapped = true;
1699 mem->mapped_to_gpu_memory++;
1700 pr_debug("\t INC mapping count %d\n",
1701 mem->mapped_to_gpu_memory);
1702 }
1703
1704 if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
1705 amdgpu_bo_fence(bo,
1706 &avm->process_info->eviction_fence->base,
1707 true);
1708 ret = unreserve_bo_and_vms(&ctx, false, false);
1709
1710 goto out;
1711
1712out_unreserve:
1713 unreserve_bo_and_vms(&ctx, false, false);
1714out:
1715 mutex_unlock(&mem->process_info->lock);
1716 mutex_unlock(&mem->lock);
1717 return ret;
1718}
1719
1720int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1721 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
1722{
1723 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1724 struct amdkfd_process_info *process_info = avm->process_info;
1725 unsigned long bo_size = mem->bo->tbo.base.size;
1726 struct kfd_mem_attachment *entry;
1727 struct bo_vm_reservation_context ctx;
1728 int ret;
1729
1730 mutex_lock(&mem->lock);
1731
1732 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
1733 if (unlikely(ret))
1734 goto out;
1735 /* If no VMs were reserved, it means the BO wasn't actually mapped */
1736 if (ctx.n_vms == 0) {
1737 ret = -EINVAL;
1738 goto unreserve_out;
1739 }
1740
1741 ret = vm_validate_pt_pd_bos(avm);
1742 if (unlikely(ret))
1743 goto unreserve_out;
1744
1745 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
1746 mem->va,
1747 mem->va + bo_size * (1 + mem->aql_queue),
1748 avm);
1749
1750 list_for_each_entry(entry, &mem->attachments, list) {
1751 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
1752 continue;
1753
1754 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
1755 entry->va, entry->va + bo_size, entry);
1756
1757 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
1758 entry->is_mapped = false;
1759
1760 mem->mapped_to_gpu_memory--;
1761 pr_debug("\t DEC mapping count %d\n",
1762 mem->mapped_to_gpu_memory);
1763 }
1764
1765 /* If BO is unmapped from all VMs, unfence it. It can be evicted if
1766 * required.
1767 */
1768 if (mem->mapped_to_gpu_memory == 0 &&
1769 !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
1770 !mem->bo->tbo.pin_count)
1771 amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1772 process_info->eviction_fence);
1773
1774unreserve_out:
1775 unreserve_bo_and_vms(&ctx, false, false);
1776out:
1777 mutex_unlock(&mem->lock);
1778 return ret;
1779}
1780
1781int amdgpu_amdkfd_gpuvm_sync_memory(
1782 struct kgd_dev *kgd, struct kgd_mem *mem, bool intr)
1783{
1784 struct amdgpu_sync sync;
1785 int ret;
1786
1787 amdgpu_sync_create(&sync);
1788
1789 mutex_lock(&mem->lock);
1790 amdgpu_sync_clone(&mem->sync, &sync);
1791 mutex_unlock(&mem->lock);
1792
1793 ret = amdgpu_sync_wait(&sync, intr);
1794 amdgpu_sync_free(&sync);
1795 return ret;
1796}
1797
1798int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
1799 struct kgd_mem *mem, void **kptr, uint64_t *size)
1800{
1801 int ret;
1802 struct amdgpu_bo *bo = mem->bo;
1803
1804 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
1805 pr_err("userptr can't be mapped to kernel\n");
1806 return -EINVAL;
1807 }
1808
1809 /* delete kgd_mem from kfd_bo_list to avoid re-validating
1810 * this BO in BO's restoring after eviction.
1811 */
1812 mutex_lock(&mem->process_info->lock);
1813
1814 ret = amdgpu_bo_reserve(bo, true);
1815 if (ret) {
1816 pr_err("Failed to reserve bo. ret %d\n", ret);
1817 goto bo_reserve_failed;
1818 }
1819
1820 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
1821 if (ret) {
1822 pr_err("Failed to pin bo. ret %d\n", ret);
1823 goto pin_failed;
1824 }
1825
1826 ret = amdgpu_bo_kmap(bo, kptr);
1827 if (ret) {
1828 pr_err("Failed to map bo to kernel. ret %d\n", ret);
1829 goto kmap_failed;
1830 }
1831
1832 amdgpu_amdkfd_remove_eviction_fence(
1833 bo, mem->process_info->eviction_fence);
1834 list_del_init(&mem->validate_list.head);
1835
1836 if (size)
1837 *size = amdgpu_bo_size(bo);
1838
1839 amdgpu_bo_unreserve(bo);
1840
1841 mutex_unlock(&mem->process_info->lock);
1842 return 0;
1843
1844kmap_failed:
1845 amdgpu_bo_unpin(bo);
1846pin_failed:
1847 amdgpu_bo_unreserve(bo);
1848bo_reserve_failed:
1849 mutex_unlock(&mem->process_info->lock);
1850
1851 return ret;
1852}
1853
1854int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
1855 struct kfd_vm_fault_info *mem)
1856{
1857 struct amdgpu_device *adev;
1858
1859 adev = (struct amdgpu_device *)kgd;
1860 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
1861 *mem = *adev->gmc.vm_fault_info;
1862 mb();
1863 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1864 }
1865 return 0;
1866}
1867
1868int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
1869 struct dma_buf *dma_buf,
1870 uint64_t va, void *drm_priv,
1871 struct kgd_mem **mem, uint64_t *size,
1872 uint64_t *mmap_offset)
1873{
1874 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
1875 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1876 struct drm_gem_object *obj;
1877 struct amdgpu_bo *bo;
1878 int ret;
1879
1880 if (dma_buf->ops != &amdgpu_dmabuf_ops)
1881 /* Can't handle non-graphics buffers */
1882 return -EINVAL;
1883
1884 obj = dma_buf->priv;
1885 if (drm_to_adev(obj->dev) != adev)
1886 /* Can't handle buffers from other devices */
1887 return -EINVAL;
1888
1889 bo = gem_to_amdgpu_bo(obj);
1890 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
1891 AMDGPU_GEM_DOMAIN_GTT)))
1892 /* Only VRAM and GTT BOs are supported */
1893 return -EINVAL;
1894
1895 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1896 if (!*mem)
1897 return -ENOMEM;
1898
1899 ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
1900 if (ret) {
1901 kfree(mem);
1902 return ret;
1903 }
1904
1905 if (size)
1906 *size = amdgpu_bo_size(bo);
1907
1908 if (mmap_offset)
1909 *mmap_offset = amdgpu_bo_mmap_offset(bo);
1910
1911 INIT_LIST_HEAD(&(*mem)->attachments);
1912 mutex_init(&(*mem)->lock);
1913
1914 (*mem)->alloc_flags =
1915 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
1916 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
1917 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
1918 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
1919
1920 drm_gem_object_get(&bo->tbo.base);
1921 (*mem)->bo = bo;
1922 (*mem)->va = va;
1923 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
1924 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
1925 (*mem)->mapped_to_gpu_memory = 0;
1926 (*mem)->process_info = avm->process_info;
1927 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
1928 amdgpu_sync_create(&(*mem)->sync);
1929 (*mem)->is_imported = true;
1930
1931 return 0;
1932}
1933
1934/* Evict a userptr BO by stopping the queues if necessary
1935 *
1936 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
1937 * cannot do any memory allocations, and cannot take any locks that
1938 * are held elsewhere while allocating memory. Therefore this is as
1939 * simple as possible, using atomic counters.
1940 *
1941 * It doesn't do anything to the BO itself. The real work happens in
1942 * restore, where we get updated page addresses. This function only
1943 * ensures that GPU access to the BO is stopped.
1944 */
1945int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
1946 struct mm_struct *mm)
1947{
1948 struct amdkfd_process_info *process_info = mem->process_info;
1949 int evicted_bos;
1950 int r = 0;
1951
1952 atomic_inc(&mem->invalid);
1953 evicted_bos = atomic_inc_return(&process_info->evicted_bos);
1954 if (evicted_bos == 1) {
1955 /* First eviction, stop the queues */
1956 r = kgd2kfd_quiesce_mm(mm);
1957 if (r)
1958 pr_err("Failed to quiesce KFD\n");
1959 schedule_delayed_work(&process_info->restore_userptr_work,
1960 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
1961 }
1962
1963 return r;
1964}
1965
1966/* Update invalid userptr BOs
1967 *
1968 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
1969 * userptr_inval_list and updates user pages for all BOs that have
1970 * been invalidated since their last update.
1971 */
1972static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
1973 struct mm_struct *mm)
1974{
1975 struct kgd_mem *mem, *tmp_mem;
1976 struct amdgpu_bo *bo;
1977 struct ttm_operation_ctx ctx = { false, false };
1978 int invalid, ret;
1979
1980 /* Move all invalidated BOs to the userptr_inval_list and
1981 * release their user pages by migration to the CPU domain
1982 */
1983 list_for_each_entry_safe(mem, tmp_mem,
1984 &process_info->userptr_valid_list,
1985 validate_list.head) {
1986 if (!atomic_read(&mem->invalid))
1987 continue; /* BO is still valid */
1988
1989 bo = mem->bo;
1990
1991 if (amdgpu_bo_reserve(bo, true))
1992 return -EAGAIN;
1993 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
1994 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1995 amdgpu_bo_unreserve(bo);
1996 if (ret) {
1997 pr_err("%s: Failed to invalidate userptr BO\n",
1998 __func__);
1999 return -EAGAIN;
2000 }
2001
2002 list_move_tail(&mem->validate_list.head,
2003 &process_info->userptr_inval_list);
2004 }
2005
2006 if (list_empty(&process_info->userptr_inval_list))
2007 return 0; /* All evicted userptr BOs were freed */
2008
2009 /* Go through userptr_inval_list and update any invalid user_pages */
2010 list_for_each_entry(mem, &process_info->userptr_inval_list,
2011 validate_list.head) {
2012 invalid = atomic_read(&mem->invalid);
2013 if (!invalid)
2014 /* BO hasn't been invalidated since the last
2015 * revalidation attempt. Keep its BO list.
2016 */
2017 continue;
2018
2019 bo = mem->bo;
2020
2021 /* Get updated user pages */
2022 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
2023 if (ret) {
2024 pr_debug("%s: Failed to get user pages: %d\n",
2025 __func__, ret);
2026
2027 /* Return error -EBUSY or -ENOMEM, retry restore */
2028 return ret;
2029 }
2030
2031 /*
2032 * FIXME: Cannot ignore the return code, must hold
2033 * notifier_lock
2034 */
2035 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
2036
2037 /* Mark the BO as valid unless it was invalidated
2038 * again concurrently.
2039 */
2040 if (atomic_cmpxchg(&mem->invalid, invalid, 0) != invalid)
2041 return -EAGAIN;
2042 }
2043
2044 return 0;
2045}
2046
2047/* Validate invalid userptr BOs
2048 *
2049 * Validates BOs on the userptr_inval_list, and moves them back to the
2050 * userptr_valid_list. Also updates GPUVM page tables with new page
2051 * addresses and waits for the page table updates to complete.
2052 */
2053static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2054{
2055 struct amdgpu_bo_list_entry *pd_bo_list_entries;
2056 struct list_head resv_list, duplicates;
2057 struct ww_acquire_ctx ticket;
2058 struct amdgpu_sync sync;
2059
2060 struct amdgpu_vm *peer_vm;
2061 struct kgd_mem *mem, *tmp_mem;
2062 struct amdgpu_bo *bo;
2063 struct ttm_operation_ctx ctx = { false, false };
2064 int i, ret;
2065
2066 pd_bo_list_entries = kcalloc(process_info->n_vms,
2067 sizeof(struct amdgpu_bo_list_entry),
2068 GFP_KERNEL);
2069 if (!pd_bo_list_entries) {
2070 pr_err("%s: Failed to allocate PD BO list entries\n", __func__);
2071 ret = -ENOMEM;
2072 goto out_no_mem;
2073 }
2074
2075 INIT_LIST_HEAD(&resv_list);
2076 INIT_LIST_HEAD(&duplicates);
2077
2078 /* Get all the page directory BOs that need to be reserved */
2079 i = 0;
2080 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2081 vm_list_node)
2082 amdgpu_vm_get_pd_bo(peer_vm, &resv_list,
2083 &pd_bo_list_entries[i++]);
2084 /* Add the userptr_inval_list entries to resv_list */
2085 list_for_each_entry(mem, &process_info->userptr_inval_list,
2086 validate_list.head) {
2087 list_add_tail(&mem->resv_list.head, &resv_list);
2088 mem->resv_list.bo = mem->validate_list.bo;
2089 mem->resv_list.num_shared = mem->validate_list.num_shared;
2090 }
2091
2092 /* Reserve all BOs and page tables for validation */
2093 ret = ttm_eu_reserve_buffers(&ticket, &resv_list, false, &duplicates);
2094 WARN(!list_empty(&duplicates), "Duplicates should be empty");
2095 if (ret)
2096 goto out_free;
2097
2098 amdgpu_sync_create(&sync);
2099
2100 ret = process_validate_vms(process_info);
2101 if (ret)
2102 goto unreserve_out;
2103
2104 /* Validate BOs and update GPUVM page tables */
2105 list_for_each_entry_safe(mem, tmp_mem,
2106 &process_info->userptr_inval_list,
2107 validate_list.head) {
2108 struct kfd_mem_attachment *attachment;
2109
2110 bo = mem->bo;
2111
2112 /* Validate the BO if we got user pages */
2113 if (bo->tbo.ttm->pages[0]) {
2114 amdgpu_bo_placement_from_domain(bo, mem->domain);
2115 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2116 if (ret) {
2117 pr_err("%s: failed to validate BO\n", __func__);
2118 goto unreserve_out;
2119 }
2120 }
2121
2122 list_move_tail(&mem->validate_list.head,
2123 &process_info->userptr_valid_list);
2124
2125 /* Update mapping. If the BO was not validated
2126 * (because we couldn't get user pages), this will
2127 * clear the page table entries, which will result in
2128 * VM faults if the GPU tries to access the invalid
2129 * memory.
2130 */
2131 list_for_each_entry(attachment, &mem->attachments, list) {
2132 if (!attachment->is_mapped)
2133 continue;
2134
2135 kfd_mem_dmaunmap_attachment(mem, attachment);
2136 ret = update_gpuvm_pte(mem, attachment, &sync);
2137 if (ret) {
2138 pr_err("%s: update PTE failed\n", __func__);
2139 /* make sure this gets validated again */
2140 atomic_inc(&mem->invalid);
2141 goto unreserve_out;
2142 }
2143 }
2144 }
2145
2146 /* Update page directories */
2147 ret = process_update_pds(process_info, &sync);
2148
2149unreserve_out:
2150 ttm_eu_backoff_reservation(&ticket, &resv_list);
2151 amdgpu_sync_wait(&sync, false);
2152 amdgpu_sync_free(&sync);
2153out_free:
2154 kfree(pd_bo_list_entries);
2155out_no_mem:
2156
2157 return ret;
2158}
2159
2160/* Worker callback to restore evicted userptr BOs
2161 *
2162 * Tries to update and validate all userptr BOs. If successful and no
2163 * concurrent evictions happened, the queues are restarted. Otherwise,
2164 * reschedule for another attempt later.
2165 */
2166static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2167{
2168 struct delayed_work *dwork = to_delayed_work(work);
2169 struct amdkfd_process_info *process_info =
2170 container_of(dwork, struct amdkfd_process_info,
2171 restore_userptr_work);
2172 struct task_struct *usertask;
2173 struct mm_struct *mm;
2174 int evicted_bos;
2175
2176 evicted_bos = atomic_read(&process_info->evicted_bos);
2177 if (!evicted_bos)
2178 return;
2179
2180 /* Reference task and mm in case of concurrent process termination */
2181 usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2182 if (!usertask)
2183 return;
2184 mm = get_task_mm(usertask);
2185 if (!mm) {
2186 put_task_struct(usertask);
2187 return;
2188 }
2189
2190 mutex_lock(&process_info->lock);
2191
2192 if (update_invalid_user_pages(process_info, mm))
2193 goto unlock_out;
2194 /* userptr_inval_list can be empty if all evicted userptr BOs
2195 * have been freed. In that case there is nothing to validate
2196 * and we can just restart the queues.
2197 */
2198 if (!list_empty(&process_info->userptr_inval_list)) {
2199 if (atomic_read(&process_info->evicted_bos) != evicted_bos)
2200 goto unlock_out; /* Concurrent eviction, try again */
2201
2202 if (validate_invalid_user_pages(process_info))
2203 goto unlock_out;
2204 }
2205 /* Final check for concurrent evicton and atomic update. If
2206 * another eviction happens after successful update, it will
2207 * be a first eviction that calls quiesce_mm. The eviction
2208 * reference counting inside KFD will handle this case.
2209 */
2210 if (atomic_cmpxchg(&process_info->evicted_bos, evicted_bos, 0) !=
2211 evicted_bos)
2212 goto unlock_out;
2213 evicted_bos = 0;
2214 if (kgd2kfd_resume_mm(mm)) {
2215 pr_err("%s: Failed to resume KFD\n", __func__);
2216 /* No recovery from this failure. Probably the CP is
2217 * hanging. No point trying again.
2218 */
2219 }
2220
2221unlock_out:
2222 mutex_unlock(&process_info->lock);
2223 mmput(mm);
2224 put_task_struct(usertask);
2225
2226 /* If validation failed, reschedule another attempt */
2227 if (evicted_bos)
2228 schedule_delayed_work(&process_info->restore_userptr_work,
2229 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2230}
2231
2232/** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2233 * KFD process identified by process_info
2234 *
2235 * @process_info: amdkfd_process_info of the KFD process
2236 *
2237 * After memory eviction, restore thread calls this function. The function
2238 * should be called when the Process is still valid. BO restore involves -
2239 *
2240 * 1. Release old eviction fence and create new one
2241 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2242 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2243 * BOs that need to be reserved.
2244 * 4. Reserve all the BOs
2245 * 5. Validate of PD and PT BOs.
2246 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2247 * 7. Add fence to all PD and PT BOs.
2248 * 8. Unreserve all BOs
2249 */
2250int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
2251{
2252 struct amdgpu_bo_list_entry *pd_bo_list;
2253 struct amdkfd_process_info *process_info = info;
2254 struct amdgpu_vm *peer_vm;
2255 struct kgd_mem *mem;
2256 struct bo_vm_reservation_context ctx;
2257 struct amdgpu_amdkfd_fence *new_fence;
2258 int ret = 0, i;
2259 struct list_head duplicate_save;
2260 struct amdgpu_sync sync_obj;
2261 unsigned long failed_size = 0;
2262 unsigned long total_size = 0;
2263
2264 INIT_LIST_HEAD(&duplicate_save);
2265 INIT_LIST_HEAD(&ctx.list);
2266 INIT_LIST_HEAD(&ctx.duplicates);
2267
2268 pd_bo_list = kcalloc(process_info->n_vms,
2269 sizeof(struct amdgpu_bo_list_entry),
2270 GFP_KERNEL);
2271 if (!pd_bo_list)
2272 return -ENOMEM;
2273
2274 i = 0;
2275 mutex_lock(&process_info->lock);
2276 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2277 vm_list_node)
2278 amdgpu_vm_get_pd_bo(peer_vm, &ctx.list, &pd_bo_list[i++]);
2279
2280 /* Reserve all BOs and page tables/directory. Add all BOs from
2281 * kfd_bo_list to ctx.list
2282 */
2283 list_for_each_entry(mem, &process_info->kfd_bo_list,
2284 validate_list.head) {
2285
2286 list_add_tail(&mem->resv_list.head, &ctx.list);
2287 mem->resv_list.bo = mem->validate_list.bo;
2288 mem->resv_list.num_shared = mem->validate_list.num_shared;
2289 }
2290
2291 ret = ttm_eu_reserve_buffers(&ctx.ticket, &ctx.list,
2292 false, &duplicate_save);
2293 if (ret) {
2294 pr_debug("Memory eviction: TTM Reserve Failed. Try again\n");
2295 goto ttm_reserve_fail;
2296 }
2297
2298 amdgpu_sync_create(&sync_obj);
2299
2300 /* Validate PDs and PTs */
2301 ret = process_validate_vms(process_info);
2302 if (ret)
2303 goto validate_map_fail;
2304
2305 ret = process_sync_pds_resv(process_info, &sync_obj);
2306 if (ret) {
2307 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2308 goto validate_map_fail;
2309 }
2310
2311 /* Validate BOs and map them to GPUVM (update VM page tables). */
2312 list_for_each_entry(mem, &process_info->kfd_bo_list,
2313 validate_list.head) {
2314
2315 struct amdgpu_bo *bo = mem->bo;
2316 uint32_t domain = mem->domain;
2317 struct kfd_mem_attachment *attachment;
2318
2319 total_size += amdgpu_bo_size(bo);
2320
2321 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2322 if (ret) {
2323 pr_debug("Memory eviction: Validate BOs failed\n");
2324 failed_size += amdgpu_bo_size(bo);
2325 ret = amdgpu_amdkfd_bo_validate(bo,
2326 AMDGPU_GEM_DOMAIN_GTT, false);
2327 if (ret) {
2328 pr_debug("Memory eviction: Try again\n");
2329 goto validate_map_fail;
2330 }
2331 }
2332 ret = amdgpu_sync_fence(&sync_obj, bo->tbo.moving);
2333 if (ret) {
2334 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2335 goto validate_map_fail;
2336 }
2337 list_for_each_entry(attachment, &mem->attachments, list) {
2338 if (!attachment->is_mapped)
2339 continue;
2340
2341 kfd_mem_dmaunmap_attachment(mem, attachment);
2342 ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2343 if (ret) {
2344 pr_debug("Memory eviction: update PTE failed. Try again\n");
2345 goto validate_map_fail;
2346 }
2347 }
2348 }
2349
2350 if (failed_size)
2351 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2352
2353 /* Update page directories */
2354 ret = process_update_pds(process_info, &sync_obj);
2355 if (ret) {
2356 pr_debug("Memory eviction: update PDs failed. Try again\n");
2357 goto validate_map_fail;
2358 }
2359
2360 /* Wait for validate and PT updates to finish */
2361 amdgpu_sync_wait(&sync_obj, false);
2362
2363 /* Release old eviction fence and create new one, because fence only
2364 * goes from unsignaled to signaled, fence cannot be reused.
2365 * Use context and mm from the old fence.
2366 */
2367 new_fence = amdgpu_amdkfd_fence_create(
2368 process_info->eviction_fence->base.context,
2369 process_info->eviction_fence->mm,
2370 NULL);
2371 if (!new_fence) {
2372 pr_err("Failed to create eviction fence\n");
2373 ret = -ENOMEM;
2374 goto validate_map_fail;
2375 }
2376 dma_fence_put(&process_info->eviction_fence->base);
2377 process_info->eviction_fence = new_fence;
2378 *ef = dma_fence_get(&new_fence->base);
2379
2380 /* Attach new eviction fence to all BOs */
2381 list_for_each_entry(mem, &process_info->kfd_bo_list,
2382 validate_list.head)
2383 amdgpu_bo_fence(mem->bo,
2384 &process_info->eviction_fence->base, true);
2385
2386 /* Attach eviction fence to PD / PT BOs */
2387 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2388 vm_list_node) {
2389 struct amdgpu_bo *bo = peer_vm->root.bo;
2390
2391 amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true);
2392 }
2393
2394validate_map_fail:
2395 ttm_eu_backoff_reservation(&ctx.ticket, &ctx.list);
2396 amdgpu_sync_free(&sync_obj);
2397ttm_reserve_fail:
2398 mutex_unlock(&process_info->lock);
2399 kfree(pd_bo_list);
2400 return ret;
2401}
2402
2403int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
2404{
2405 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2406 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
2407 int ret;
2408
2409 if (!info || !gws)
2410 return -EINVAL;
2411
2412 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2413 if (!*mem)
2414 return -ENOMEM;
2415
2416 mutex_init(&(*mem)->lock);
2417 INIT_LIST_HEAD(&(*mem)->attachments);
2418 (*mem)->bo = amdgpu_bo_ref(gws_bo);
2419 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
2420 (*mem)->process_info = process_info;
2421 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
2422 amdgpu_sync_create(&(*mem)->sync);
2423
2424
2425 /* Validate gws bo the first time it is added to process */
2426 mutex_lock(&(*mem)->process_info->lock);
2427 ret = amdgpu_bo_reserve(gws_bo, false);
2428 if (unlikely(ret)) {
2429 pr_err("Reserve gws bo failed %d\n", ret);
2430 goto bo_reservation_failure;
2431 }
2432
2433 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
2434 if (ret) {
2435 pr_err("GWS BO validate failed %d\n", ret);
2436 goto bo_validation_failure;
2437 }
2438 /* GWS resource is shared b/t amdgpu and amdkfd
2439 * Add process eviction fence to bo so they can
2440 * evict each other.
2441 */
2442 ret = dma_resv_reserve_shared(gws_bo->tbo.base.resv, 1);
2443 if (ret)
2444 goto reserve_shared_fail;
2445 amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true);
2446 amdgpu_bo_unreserve(gws_bo);
2447 mutex_unlock(&(*mem)->process_info->lock);
2448
2449 return ret;
2450
2451reserve_shared_fail:
2452bo_validation_failure:
2453 amdgpu_bo_unreserve(gws_bo);
2454bo_reservation_failure:
2455 mutex_unlock(&(*mem)->process_info->lock);
2456 amdgpu_sync_free(&(*mem)->sync);
2457 remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
2458 amdgpu_bo_unref(&gws_bo);
2459 mutex_destroy(&(*mem)->lock);
2460 kfree(*mem);
2461 *mem = NULL;
2462 return ret;
2463}
2464
2465int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
2466{
2467 int ret;
2468 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
2469 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
2470 struct amdgpu_bo *gws_bo = kgd_mem->bo;
2471
2472 /* Remove BO from process's validate list so restore worker won't touch
2473 * it anymore
2474 */
2475 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
2476
2477 ret = amdgpu_bo_reserve(gws_bo, false);
2478 if (unlikely(ret)) {
2479 pr_err("Reserve gws bo failed %d\n", ret);
2480 //TODO add BO back to validate_list?
2481 return ret;
2482 }
2483 amdgpu_amdkfd_remove_eviction_fence(gws_bo,
2484 process_info->eviction_fence);
2485 amdgpu_bo_unreserve(gws_bo);
2486 amdgpu_sync_free(&kgd_mem->sync);
2487 amdgpu_bo_unref(&gws_bo);
2488 mutex_destroy(&kgd_mem->lock);
2489 kfree(mem);
2490 return 0;
2491}
2492
2493/* Returns GPU-specific tiling mode information */
2494int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
2495 struct tile_config *config)
2496{
2497 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
2498
2499 config->gb_addr_config = adev->gfx.config.gb_addr_config;
2500 config->tile_config_ptr = adev->gfx.config.tile_mode_array;
2501 config->num_tile_configs =
2502 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2503 config->macro_tile_config_ptr =
2504 adev->gfx.config.macrotile_mode_array;
2505 config->num_macro_tile_configs =
2506 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2507
2508 /* Those values are not set from GFX9 onwards */
2509 config->num_banks = adev->gfx.config.num_banks;
2510 config->num_ranks = adev->gfx.config.num_ranks;
2511
2512 return 0;
2513}