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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * USB4 specific functionality
4 *
5 * Copyright (C) 2019, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rajmohan Mani <rajmohan.mani@intel.com>
8 */
9
10#include <linux/delay.h>
11#include <linux/ktime.h>
12#include <linux/units.h>
13
14#include "sb_regs.h"
15#include "tb.h"
16
17#define USB4_DATA_RETRIES 3
18#define USB4_DATA_DWORDS 16
19
20enum usb4_sb_target {
21 USB4_SB_TARGET_ROUTER,
22 USB4_SB_TARGET_PARTNER,
23 USB4_SB_TARGET_RETIMER,
24};
25
26#define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
27#define USB4_NVM_READ_OFFSET_SHIFT 2
28#define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
29#define USB4_NVM_READ_LENGTH_SHIFT 24
30
31#define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
32#define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
33
34#define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
35#define USB4_DROM_ADDRESS_SHIFT 2
36#define USB4_DROM_SIZE_MASK GENMASK(19, 15)
37#define USB4_DROM_SIZE_SHIFT 15
38
39#define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
40
41#define USB4_BA_LENGTH_MASK GENMASK(7, 0)
42#define USB4_BA_INDEX_MASK GENMASK(15, 0)
43
44enum usb4_ba_index {
45 USB4_BA_MAX_USB3 = 0x1,
46 USB4_BA_MIN_DP_AUX = 0x2,
47 USB4_BA_MIN_DP_MAIN = 0x3,
48 USB4_BA_MAX_PCIE = 0x4,
49 USB4_BA_MAX_HI = 0x5,
50};
51
52#define USB4_BA_VALUE_MASK GENMASK(31, 16)
53#define USB4_BA_VALUE_SHIFT 16
54
55static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode,
56 u32 *metadata, u8 *status,
57 const void *tx_data, size_t tx_dwords,
58 void *rx_data, size_t rx_dwords)
59{
60 u32 val;
61 int ret;
62
63 if (metadata) {
64 ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
65 if (ret)
66 return ret;
67 }
68 if (tx_dwords) {
69 ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9,
70 tx_dwords);
71 if (ret)
72 return ret;
73 }
74
75 val = opcode | ROUTER_CS_26_OV;
76 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
77 if (ret)
78 return ret;
79
80 ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
81 if (ret)
82 return ret;
83
84 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
85 if (ret)
86 return ret;
87
88 if (val & ROUTER_CS_26_ONS)
89 return -EOPNOTSUPP;
90
91 if (status)
92 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
93 ROUTER_CS_26_STATUS_SHIFT;
94
95 if (metadata) {
96 ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
97 if (ret)
98 return ret;
99 }
100 if (rx_dwords) {
101 ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9,
102 rx_dwords);
103 if (ret)
104 return ret;
105 }
106
107 return 0;
108}
109
110static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata,
111 u8 *status, const void *tx_data, size_t tx_dwords,
112 void *rx_data, size_t rx_dwords)
113{
114 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
115
116 if (tx_dwords > USB4_DATA_DWORDS || rx_dwords > USB4_DATA_DWORDS)
117 return -EINVAL;
118
119 /*
120 * If the connection manager implementation provides USB4 router
121 * operation proxy callback, call it here instead of running the
122 * operation natively.
123 */
124 if (cm_ops->usb4_switch_op) {
125 int ret;
126
127 ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status,
128 tx_data, tx_dwords, rx_data,
129 rx_dwords);
130 if (ret != -EOPNOTSUPP)
131 return ret;
132
133 /*
134 * If the proxy was not supported then run the native
135 * router operation instead.
136 */
137 }
138
139 return usb4_native_switch_op(sw, opcode, metadata, status, tx_data,
140 tx_dwords, rx_data, rx_dwords);
141}
142
143static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode,
144 u32 *metadata, u8 *status)
145{
146 return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0);
147}
148
149static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode,
150 u32 *metadata, u8 *status,
151 const void *tx_data, size_t tx_dwords,
152 void *rx_data, size_t rx_dwords)
153{
154 return __usb4_switch_op(sw, opcode, metadata, status, tx_data,
155 tx_dwords, rx_data, rx_dwords);
156}
157
158static void usb4_switch_check_wakes(struct tb_switch *sw)
159{
160 bool wakeup_usb4 = false;
161 struct usb4_port *usb4;
162 struct tb_port *port;
163 bool wakeup = false;
164 u32 val;
165
166 if (!device_may_wakeup(&sw->dev))
167 return;
168
169 if (tb_route(sw)) {
170 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
171 return;
172
173 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
174 (val & ROUTER_CS_6_WOPS) ? "yes" : "no",
175 (val & ROUTER_CS_6_WOUS) ? "yes" : "no");
176
177 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
178 }
179
180 /*
181 * Check for any downstream ports for USB4 wake,
182 * connection wake and disconnection wake.
183 */
184 tb_switch_for_each_port(sw, port) {
185 if (!port->cap_usb4)
186 continue;
187
188 if (tb_port_read(port, &val, TB_CFG_PORT,
189 port->cap_usb4 + PORT_CS_18, 1))
190 break;
191
192 tb_port_dbg(port, "USB4 wake: %s, connection wake: %s, disconnection wake: %s\n",
193 (val & PORT_CS_18_WOU4S) ? "yes" : "no",
194 (val & PORT_CS_18_WOCS) ? "yes" : "no",
195 (val & PORT_CS_18_WODS) ? "yes" : "no");
196
197 wakeup_usb4 = val & (PORT_CS_18_WOU4S | PORT_CS_18_WOCS |
198 PORT_CS_18_WODS);
199
200 usb4 = port->usb4;
201 if (device_may_wakeup(&usb4->dev) && wakeup_usb4)
202 pm_wakeup_event(&usb4->dev, 0);
203
204 wakeup |= wakeup_usb4;
205 }
206
207 if (wakeup)
208 pm_wakeup_event(&sw->dev, 0);
209}
210
211static bool link_is_usb4(struct tb_port *port)
212{
213 u32 val;
214
215 if (!port->cap_usb4)
216 return false;
217
218 if (tb_port_read(port, &val, TB_CFG_PORT,
219 port->cap_usb4 + PORT_CS_18, 1))
220 return false;
221
222 return !(val & PORT_CS_18_TCM);
223}
224
225/**
226 * usb4_switch_setup() - Additional setup for USB4 device
227 * @sw: USB4 router to setup
228 *
229 * USB4 routers need additional settings in order to enable all the
230 * tunneling. This function enables USB and PCIe tunneling if it can be
231 * enabled (e.g the parent switch also supports them). If USB tunneling
232 * is not available for some reason (like that there is Thunderbolt 3
233 * switch upstream) then the internal xHCI controller is enabled
234 * instead.
235 *
236 * This does not set the configuration valid bit of the router. To do
237 * that call usb4_switch_configuration_valid().
238 */
239int usb4_switch_setup(struct tb_switch *sw)
240{
241 struct tb_switch *parent = tb_switch_parent(sw);
242 struct tb_port *down;
243 bool tbt3, xhci;
244 u32 val = 0;
245 int ret;
246
247 usb4_switch_check_wakes(sw);
248
249 if (!tb_route(sw))
250 return 0;
251
252 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
253 if (ret)
254 return ret;
255
256 down = tb_switch_downstream_port(sw);
257 sw->link_usb4 = link_is_usb4(down);
258 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT");
259
260 xhci = val & ROUTER_CS_6_HCI;
261 tbt3 = !(val & ROUTER_CS_6_TNS);
262
263 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
264 tbt3 ? "yes" : "no", xhci ? "yes" : "no");
265
266 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
267 if (ret)
268 return ret;
269
270 if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 &&
271 tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
272 val |= ROUTER_CS_5_UTO;
273 xhci = false;
274 }
275
276 /*
277 * Only enable PCIe tunneling if the parent router supports it
278 * and it is not disabled.
279 */
280 if (tb_acpi_may_tunnel_pcie() &&
281 tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
282 val |= ROUTER_CS_5_PTO;
283 /*
284 * xHCI can be enabled if PCIe tunneling is supported
285 * and the parent does not have any USB3 dowstream
286 * adapters (so we cannot do USB 3.x tunneling).
287 */
288 if (xhci)
289 val |= ROUTER_CS_5_HCO;
290 }
291
292 /* TBT3 supported by the CM */
293 val &= ~ROUTER_CS_5_CNS;
294
295 return tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
296}
297
298/**
299 * usb4_switch_configuration_valid() - Set tunneling configuration to be valid
300 * @sw: USB4 router
301 *
302 * Sets configuration valid bit for the router. Must be called before
303 * any tunnels can be set through the router and after
304 * usb4_switch_setup() has been called. Can be called to host and device
305 * routers (does nothing for the latter).
306 *
307 * Returns %0 in success and negative errno otherwise.
308 */
309int usb4_switch_configuration_valid(struct tb_switch *sw)
310{
311 u32 val;
312 int ret;
313
314 if (!tb_route(sw))
315 return 0;
316
317 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
318 if (ret)
319 return ret;
320
321 val |= ROUTER_CS_5_CV;
322
323 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
324 if (ret)
325 return ret;
326
327 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
328 ROUTER_CS_6_CR, 50);
329}
330
331/**
332 * usb4_switch_read_uid() - Read UID from USB4 router
333 * @sw: USB4 router
334 * @uid: UID is stored here
335 *
336 * Reads 64-bit UID from USB4 router config space.
337 */
338int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
339{
340 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
341}
342
343static int usb4_switch_drom_read_block(void *data,
344 unsigned int dwaddress, void *buf,
345 size_t dwords)
346{
347 struct tb_switch *sw = data;
348 u8 status = 0;
349 u32 metadata;
350 int ret;
351
352 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
353 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
354 USB4_DROM_ADDRESS_MASK;
355
356 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata,
357 &status, NULL, 0, buf, dwords);
358 if (ret)
359 return ret;
360
361 return status ? -EIO : 0;
362}
363
364/**
365 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
366 * @sw: USB4 router
367 * @address: Byte address inside DROM to start reading
368 * @buf: Buffer where the DROM content is stored
369 * @size: Number of bytes to read from DROM
370 *
371 * Uses USB4 router operations to read router DROM. For devices this
372 * should always work but for hosts it may return %-EOPNOTSUPP in which
373 * case the host router does not have DROM.
374 */
375int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
376 size_t size)
377{
378 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
379 usb4_switch_drom_read_block, sw);
380}
381
382/**
383 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
384 * @sw: USB4 router
385 *
386 * Checks whether conditions are met so that lane bonding can be
387 * established with the upstream router. Call only for device routers.
388 */
389bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
390{
391 struct tb_port *up;
392 int ret;
393 u32 val;
394
395 up = tb_upstream_port(sw);
396 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
397 if (ret)
398 return false;
399
400 return !!(val & PORT_CS_18_BE);
401}
402
403/**
404 * usb4_switch_set_wake() - Enabled/disable wake
405 * @sw: USB4 router
406 * @flags: Wakeup flags (%0 to disable)
407 *
408 * Enables/disables router to wake up from sleep.
409 */
410int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags)
411{
412 struct usb4_port *usb4;
413 struct tb_port *port;
414 u64 route = tb_route(sw);
415 u32 val;
416 int ret;
417
418 /*
419 * Enable wakes coming from all USB4 downstream ports (from
420 * child routers). For device routers do this also for the
421 * upstream USB4 port.
422 */
423 tb_switch_for_each_port(sw, port) {
424 if (!tb_port_is_null(port))
425 continue;
426 if (!route && tb_is_upstream_port(port))
427 continue;
428 if (!port->cap_usb4)
429 continue;
430
431 ret = tb_port_read(port, &val, TB_CFG_PORT,
432 port->cap_usb4 + PORT_CS_19, 1);
433 if (ret)
434 return ret;
435
436 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
437
438 if (tb_is_upstream_port(port)) {
439 val |= PORT_CS_19_WOU4;
440 } else {
441 bool configured = val & PORT_CS_19_PC;
442 usb4 = port->usb4;
443
444 if (((flags & TB_WAKE_ON_CONNECT) |
445 device_may_wakeup(&usb4->dev)) && !configured)
446 val |= PORT_CS_19_WOC;
447 if (((flags & TB_WAKE_ON_DISCONNECT) |
448 device_may_wakeup(&usb4->dev)) && configured)
449 val |= PORT_CS_19_WOD;
450 if ((flags & TB_WAKE_ON_USB4) && configured)
451 val |= PORT_CS_19_WOU4;
452 }
453
454 ret = tb_port_write(port, &val, TB_CFG_PORT,
455 port->cap_usb4 + PORT_CS_19, 1);
456 if (ret)
457 return ret;
458 }
459
460 /*
461 * Enable wakes from PCIe, USB 3.x and DP on this router. Only
462 * needed for device routers.
463 */
464 if (route) {
465 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
466 if (ret)
467 return ret;
468
469 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD);
470 if (flags & TB_WAKE_ON_USB3)
471 val |= ROUTER_CS_5_WOU;
472 if (flags & TB_WAKE_ON_PCIE)
473 val |= ROUTER_CS_5_WOP;
474 if (flags & TB_WAKE_ON_DP)
475 val |= ROUTER_CS_5_WOD;
476
477 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
478 if (ret)
479 return ret;
480 }
481
482 return 0;
483}
484
485/**
486 * usb4_switch_set_sleep() - Prepare the router to enter sleep
487 * @sw: USB4 router
488 *
489 * Sets sleep bit for the router. Returns when the router sleep ready
490 * bit has been asserted.
491 */
492int usb4_switch_set_sleep(struct tb_switch *sw)
493{
494 int ret;
495 u32 val;
496
497 /* Set sleep bit and wait for sleep ready to be asserted */
498 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
499 if (ret)
500 return ret;
501
502 val |= ROUTER_CS_5_SLP;
503
504 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
505 if (ret)
506 return ret;
507
508 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
509 ROUTER_CS_6_SLPR, 500);
510}
511
512/**
513 * usb4_switch_nvm_sector_size() - Return router NVM sector size
514 * @sw: USB4 router
515 *
516 * If the router supports NVM operations this function returns the NVM
517 * sector size in bytes. If NVM operations are not supported returns
518 * %-EOPNOTSUPP.
519 */
520int usb4_switch_nvm_sector_size(struct tb_switch *sw)
521{
522 u32 metadata;
523 u8 status;
524 int ret;
525
526 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata,
527 &status);
528 if (ret)
529 return ret;
530
531 if (status)
532 return status == 0x2 ? -EOPNOTSUPP : -EIO;
533
534 return metadata & USB4_NVM_SECTOR_SIZE_MASK;
535}
536
537static int usb4_switch_nvm_read_block(void *data,
538 unsigned int dwaddress, void *buf, size_t dwords)
539{
540 struct tb_switch *sw = data;
541 u8 status = 0;
542 u32 metadata;
543 int ret;
544
545 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
546 USB4_NVM_READ_LENGTH_MASK;
547 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
548 USB4_NVM_READ_OFFSET_MASK;
549
550 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata,
551 &status, NULL, 0, buf, dwords);
552 if (ret)
553 return ret;
554
555 return status ? -EIO : 0;
556}
557
558/**
559 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
560 * @sw: USB4 router
561 * @address: Starting address in bytes
562 * @buf: Read data is placed here
563 * @size: How many bytes to read
564 *
565 * Reads NVM contents of the router. If NVM is not supported returns
566 * %-EOPNOTSUPP.
567 */
568int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
569 size_t size)
570{
571 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
572 usb4_switch_nvm_read_block, sw);
573}
574
575/**
576 * usb4_switch_nvm_set_offset() - Set NVM write offset
577 * @sw: USB4 router
578 * @address: Start offset
579 *
580 * Explicitly sets NVM write offset. Normally when writing to NVM this
581 * is done automatically by usb4_switch_nvm_write().
582 *
583 * Returns %0 in success and negative errno if there was a failure.
584 */
585int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address)
586{
587 u32 metadata, dwaddress;
588 u8 status = 0;
589 int ret;
590
591 dwaddress = address / 4;
592 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
593 USB4_NVM_SET_OFFSET_MASK;
594
595 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata,
596 &status);
597 if (ret)
598 return ret;
599
600 return status ? -EIO : 0;
601}
602
603static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress,
604 const void *buf, size_t dwords)
605{
606 struct tb_switch *sw = data;
607 u8 status;
608 int ret;
609
610 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status,
611 buf, dwords, NULL, 0);
612 if (ret)
613 return ret;
614
615 return status ? -EIO : 0;
616}
617
618/**
619 * usb4_switch_nvm_write() - Write to the router NVM
620 * @sw: USB4 router
621 * @address: Start address where to write in bytes
622 * @buf: Pointer to the data to write
623 * @size: Size of @buf in bytes
624 *
625 * Writes @buf to the router NVM using USB4 router operations. If NVM
626 * write is not supported returns %-EOPNOTSUPP.
627 */
628int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
629 const void *buf, size_t size)
630{
631 int ret;
632
633 ret = usb4_switch_nvm_set_offset(sw, address);
634 if (ret)
635 return ret;
636
637 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
638 usb4_switch_nvm_write_next_block, sw);
639}
640
641/**
642 * usb4_switch_nvm_authenticate() - Authenticate new NVM
643 * @sw: USB4 router
644 *
645 * After the new NVM has been written via usb4_switch_nvm_write(), this
646 * function triggers NVM authentication process. The router gets power
647 * cycled and if the authentication is successful the new NVM starts
648 * running. In case of failure returns negative errno.
649 *
650 * The caller should call usb4_switch_nvm_authenticate_status() to read
651 * the status of the authentication after power cycle. It should be the
652 * first router operation to avoid the status being lost.
653 */
654int usb4_switch_nvm_authenticate(struct tb_switch *sw)
655{
656 int ret;
657
658 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL);
659 switch (ret) {
660 /*
661 * The router is power cycled once NVM_AUTH is started so it is
662 * expected to get any of the following errors back.
663 */
664 case -EACCES:
665 case -ENOTCONN:
666 case -ETIMEDOUT:
667 return 0;
668
669 default:
670 return ret;
671 }
672}
673
674/**
675 * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate
676 * @sw: USB4 router
677 * @status: Status code of the operation
678 *
679 * The function checks if there is status available from the last NVM
680 * authenticate router operation. If there is status then %0 is returned
681 * and the status code is placed in @status. Returns negative errno in case
682 * of failure.
683 *
684 * Must be called before any other router operation.
685 */
686int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status)
687{
688 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
689 u16 opcode;
690 u32 val;
691 int ret;
692
693 if (cm_ops->usb4_switch_nvm_authenticate_status) {
694 ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status);
695 if (ret != -EOPNOTSUPP)
696 return ret;
697 }
698
699 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
700 if (ret)
701 return ret;
702
703 /* Check that the opcode is correct */
704 opcode = val & ROUTER_CS_26_OPCODE_MASK;
705 if (opcode == USB4_SWITCH_OP_NVM_AUTH) {
706 if (val & ROUTER_CS_26_OV)
707 return -EBUSY;
708 if (val & ROUTER_CS_26_ONS)
709 return -EOPNOTSUPP;
710
711 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
712 ROUTER_CS_26_STATUS_SHIFT;
713 } else {
714 *status = 0;
715 }
716
717 return 0;
718}
719
720/**
721 * usb4_switch_credits_init() - Read buffer allocation parameters
722 * @sw: USB4 router
723 *
724 * Reads @sw buffer allocation parameters and initializes @sw buffer
725 * allocation fields accordingly. Specifically @sw->credits_allocation
726 * is set to %true if these parameters can be used in tunneling.
727 *
728 * Returns %0 on success and negative errno otherwise.
729 */
730int usb4_switch_credits_init(struct tb_switch *sw)
731{
732 int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma;
733 int ret, length, i, nports;
734 const struct tb_port *port;
735 u32 data[USB4_DATA_DWORDS];
736 u32 metadata = 0;
737 u8 status = 0;
738
739 memset(data, 0, sizeof(data));
740 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_BUFFER_ALLOC, &metadata,
741 &status, NULL, 0, data, ARRAY_SIZE(data));
742 if (ret)
743 return ret;
744 if (status)
745 return -EIO;
746
747 length = metadata & USB4_BA_LENGTH_MASK;
748 if (WARN_ON(length > ARRAY_SIZE(data)))
749 return -EMSGSIZE;
750
751 max_usb3 = -1;
752 min_dp_aux = -1;
753 min_dp_main = -1;
754 max_pcie = -1;
755 max_dma = -1;
756
757 tb_sw_dbg(sw, "credit allocation parameters:\n");
758
759 for (i = 0; i < length; i++) {
760 u16 index, value;
761
762 index = data[i] & USB4_BA_INDEX_MASK;
763 value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT;
764
765 switch (index) {
766 case USB4_BA_MAX_USB3:
767 tb_sw_dbg(sw, " USB3: %u\n", value);
768 max_usb3 = value;
769 break;
770 case USB4_BA_MIN_DP_AUX:
771 tb_sw_dbg(sw, " DP AUX: %u\n", value);
772 min_dp_aux = value;
773 break;
774 case USB4_BA_MIN_DP_MAIN:
775 tb_sw_dbg(sw, " DP main: %u\n", value);
776 min_dp_main = value;
777 break;
778 case USB4_BA_MAX_PCIE:
779 tb_sw_dbg(sw, " PCIe: %u\n", value);
780 max_pcie = value;
781 break;
782 case USB4_BA_MAX_HI:
783 tb_sw_dbg(sw, " DMA: %u\n", value);
784 max_dma = value;
785 break;
786 default:
787 tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n",
788 index);
789 break;
790 }
791 }
792
793 /*
794 * Validate the buffer allocation preferences. If we find
795 * issues, log a warning and fall back using the hard-coded
796 * values.
797 */
798
799 /* Host router must report baMaxHI */
800 if (!tb_route(sw) && max_dma < 0) {
801 tb_sw_warn(sw, "host router is missing baMaxHI\n");
802 goto err_invalid;
803 }
804
805 nports = 0;
806 tb_switch_for_each_port(sw, port) {
807 if (tb_port_is_null(port))
808 nports++;
809 }
810
811 /* Must have DP buffer allocation (multiple USB4 ports) */
812 if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) {
813 tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n");
814 goto err_invalid;
815 }
816
817 tb_switch_for_each_port(sw, port) {
818 if (tb_port_is_dpout(port) && min_dp_main < 0) {
819 tb_sw_warn(sw, "missing baMinDPmain");
820 goto err_invalid;
821 }
822 if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) &&
823 min_dp_aux < 0) {
824 tb_sw_warn(sw, "missing baMinDPaux");
825 goto err_invalid;
826 }
827 if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) &&
828 max_usb3 < 0) {
829 tb_sw_warn(sw, "missing baMaxUSB3");
830 goto err_invalid;
831 }
832 if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) &&
833 max_pcie < 0) {
834 tb_sw_warn(sw, "missing baMaxPCIe");
835 goto err_invalid;
836 }
837 }
838
839 /*
840 * Buffer allocation passed the validation so we can use it in
841 * path creation.
842 */
843 sw->credit_allocation = true;
844 if (max_usb3 > 0)
845 sw->max_usb3_credits = max_usb3;
846 if (min_dp_aux > 0)
847 sw->min_dp_aux_credits = min_dp_aux;
848 if (min_dp_main > 0)
849 sw->min_dp_main_credits = min_dp_main;
850 if (max_pcie > 0)
851 sw->max_pcie_credits = max_pcie;
852 if (max_dma > 0)
853 sw->max_dma_credits = max_dma;
854
855 return 0;
856
857err_invalid:
858 return -EINVAL;
859}
860
861/**
862 * usb4_switch_query_dp_resource() - Query availability of DP IN resource
863 * @sw: USB4 router
864 * @in: DP IN adapter
865 *
866 * For DP tunneling this function can be used to query availability of
867 * DP IN resource. Returns true if the resource is available for DP
868 * tunneling, false otherwise.
869 */
870bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
871{
872 u32 metadata = in->port;
873 u8 status;
874 int ret;
875
876 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata,
877 &status);
878 /*
879 * If DP resource allocation is not supported assume it is
880 * always available.
881 */
882 if (ret == -EOPNOTSUPP)
883 return true;
884 if (ret)
885 return false;
886
887 return !status;
888}
889
890/**
891 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
892 * @sw: USB4 router
893 * @in: DP IN adapter
894 *
895 * Allocates DP IN resource for DP tunneling using USB4 router
896 * operations. If the resource was allocated returns %0. Otherwise
897 * returns negative errno, in particular %-EBUSY if the resource is
898 * already allocated.
899 */
900int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
901{
902 u32 metadata = in->port;
903 u8 status;
904 int ret;
905
906 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata,
907 &status);
908 if (ret == -EOPNOTSUPP)
909 return 0;
910 if (ret)
911 return ret;
912
913 return status ? -EBUSY : 0;
914}
915
916/**
917 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
918 * @sw: USB4 router
919 * @in: DP IN adapter
920 *
921 * Releases the previously allocated DP IN resource.
922 */
923int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
924{
925 u32 metadata = in->port;
926 u8 status;
927 int ret;
928
929 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata,
930 &status);
931 if (ret == -EOPNOTSUPP)
932 return 0;
933 if (ret)
934 return ret;
935
936 return status ? -EIO : 0;
937}
938
939static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
940{
941 struct tb_port *p;
942 int usb4_idx = 0;
943
944 /* Assume port is primary */
945 tb_switch_for_each_port(sw, p) {
946 if (!tb_port_is_null(p))
947 continue;
948 if (tb_is_upstream_port(p))
949 continue;
950 if (!p->link_nr) {
951 if (p == port)
952 break;
953 usb4_idx++;
954 }
955 }
956
957 return usb4_idx;
958}
959
960/**
961 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
962 * @sw: USB4 router
963 * @port: USB4 port
964 *
965 * USB4 routers have direct mapping between USB4 ports and PCIe
966 * downstream adapters where the PCIe topology is extended. This
967 * function returns the corresponding downstream PCIe adapter or %NULL
968 * if no such mapping was possible.
969 */
970struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
971 const struct tb_port *port)
972{
973 int usb4_idx = usb4_port_idx(sw, port);
974 struct tb_port *p;
975 int pcie_idx = 0;
976
977 /* Find PCIe down port matching usb4_port */
978 tb_switch_for_each_port(sw, p) {
979 if (!tb_port_is_pcie_down(p))
980 continue;
981
982 if (pcie_idx == usb4_idx)
983 return p;
984
985 pcie_idx++;
986 }
987
988 return NULL;
989}
990
991/**
992 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
993 * @sw: USB4 router
994 * @port: USB4 port
995 *
996 * USB4 routers have direct mapping between USB4 ports and USB 3.x
997 * downstream adapters where the USB 3.x topology is extended. This
998 * function returns the corresponding downstream USB 3.x adapter or
999 * %NULL if no such mapping was possible.
1000 */
1001struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
1002 const struct tb_port *port)
1003{
1004 int usb4_idx = usb4_port_idx(sw, port);
1005 struct tb_port *p;
1006 int usb_idx = 0;
1007
1008 /* Find USB3 down port matching usb4_port */
1009 tb_switch_for_each_port(sw, p) {
1010 if (!tb_port_is_usb3_down(p))
1011 continue;
1012
1013 if (usb_idx == usb4_idx)
1014 return p;
1015
1016 usb_idx++;
1017 }
1018
1019 return NULL;
1020}
1021
1022/**
1023 * usb4_switch_add_ports() - Add USB4 ports for this router
1024 * @sw: USB4 router
1025 *
1026 * For USB4 router finds all USB4 ports and registers devices for each.
1027 * Can be called to any router.
1028 *
1029 * Return %0 in case of success and negative errno in case of failure.
1030 */
1031int usb4_switch_add_ports(struct tb_switch *sw)
1032{
1033 struct tb_port *port;
1034
1035 if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw))
1036 return 0;
1037
1038 tb_switch_for_each_port(sw, port) {
1039 struct usb4_port *usb4;
1040
1041 if (!tb_port_is_null(port))
1042 continue;
1043 if (!port->cap_usb4)
1044 continue;
1045
1046 usb4 = usb4_port_device_add(port);
1047 if (IS_ERR(usb4)) {
1048 usb4_switch_remove_ports(sw);
1049 return PTR_ERR(usb4);
1050 }
1051
1052 port->usb4 = usb4;
1053 }
1054
1055 return 0;
1056}
1057
1058/**
1059 * usb4_switch_remove_ports() - Removes USB4 ports from this router
1060 * @sw: USB4 router
1061 *
1062 * Unregisters previously registered USB4 ports.
1063 */
1064void usb4_switch_remove_ports(struct tb_switch *sw)
1065{
1066 struct tb_port *port;
1067
1068 tb_switch_for_each_port(sw, port) {
1069 if (port->usb4) {
1070 usb4_port_device_remove(port->usb4);
1071 port->usb4 = NULL;
1072 }
1073 }
1074}
1075
1076/**
1077 * usb4_port_unlock() - Unlock USB4 downstream port
1078 * @port: USB4 port to unlock
1079 *
1080 * Unlocks USB4 downstream port so that the connection manager can
1081 * access the router below this port.
1082 */
1083int usb4_port_unlock(struct tb_port *port)
1084{
1085 int ret;
1086 u32 val;
1087
1088 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1089 if (ret)
1090 return ret;
1091
1092 val &= ~ADP_CS_4_LCK;
1093 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1094}
1095
1096/**
1097 * usb4_port_hotplug_enable() - Enables hotplug for a port
1098 * @port: USB4 port to operate on
1099 *
1100 * Enables hot plug events on a given port. This is only intended
1101 * to be used on lane, DP-IN, and DP-OUT adapters.
1102 */
1103int usb4_port_hotplug_enable(struct tb_port *port)
1104{
1105 int ret;
1106 u32 val;
1107
1108 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1109 if (ret)
1110 return ret;
1111
1112 val &= ~ADP_CS_5_DHP;
1113 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1114}
1115
1116static int usb4_port_set_configured(struct tb_port *port, bool configured)
1117{
1118 int ret;
1119 u32 val;
1120
1121 if (!port->cap_usb4)
1122 return -EINVAL;
1123
1124 ret = tb_port_read(port, &val, TB_CFG_PORT,
1125 port->cap_usb4 + PORT_CS_19, 1);
1126 if (ret)
1127 return ret;
1128
1129 if (configured)
1130 val |= PORT_CS_19_PC;
1131 else
1132 val &= ~PORT_CS_19_PC;
1133
1134 return tb_port_write(port, &val, TB_CFG_PORT,
1135 port->cap_usb4 + PORT_CS_19, 1);
1136}
1137
1138/**
1139 * usb4_port_configure() - Set USB4 port configured
1140 * @port: USB4 router
1141 *
1142 * Sets the USB4 link to be configured for power management purposes.
1143 */
1144int usb4_port_configure(struct tb_port *port)
1145{
1146 return usb4_port_set_configured(port, true);
1147}
1148
1149/**
1150 * usb4_port_unconfigure() - Set USB4 port unconfigured
1151 * @port: USB4 router
1152 *
1153 * Sets the USB4 link to be unconfigured for power management purposes.
1154 */
1155void usb4_port_unconfigure(struct tb_port *port)
1156{
1157 usb4_port_set_configured(port, false);
1158}
1159
1160static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
1161{
1162 int ret;
1163 u32 val;
1164
1165 if (!port->cap_usb4)
1166 return -EINVAL;
1167
1168 ret = tb_port_read(port, &val, TB_CFG_PORT,
1169 port->cap_usb4 + PORT_CS_19, 1);
1170 if (ret)
1171 return ret;
1172
1173 if (configured)
1174 val |= PORT_CS_19_PID;
1175 else
1176 val &= ~PORT_CS_19_PID;
1177
1178 return tb_port_write(port, &val, TB_CFG_PORT,
1179 port->cap_usb4 + PORT_CS_19, 1);
1180}
1181
1182/**
1183 * usb4_port_configure_xdomain() - Configure port for XDomain
1184 * @port: USB4 port connected to another host
1185 * @xd: XDomain that is connected to the port
1186 *
1187 * Marks the USB4 port as being connected to another host and updates
1188 * the link type. Returns %0 in success and negative errno in failure.
1189 */
1190int usb4_port_configure_xdomain(struct tb_port *port, struct tb_xdomain *xd)
1191{
1192 xd->link_usb4 = link_is_usb4(port);
1193 return usb4_set_xdomain_configured(port, true);
1194}
1195
1196/**
1197 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
1198 * @port: USB4 port that was connected to another host
1199 *
1200 * Clears USB4 port from being marked as XDomain.
1201 */
1202void usb4_port_unconfigure_xdomain(struct tb_port *port)
1203{
1204 usb4_set_xdomain_configured(port, false);
1205}
1206
1207static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
1208 u32 value, int timeout_msec)
1209{
1210 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
1211
1212 do {
1213 u32 val;
1214 int ret;
1215
1216 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1);
1217 if (ret)
1218 return ret;
1219
1220 if ((val & bit) == value)
1221 return 0;
1222
1223 usleep_range(50, 100);
1224 } while (ktime_before(ktime_get(), timeout));
1225
1226 return -ETIMEDOUT;
1227}
1228
1229static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
1230{
1231 if (dwords > USB4_DATA_DWORDS)
1232 return -EINVAL;
1233
1234 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1235 dwords);
1236}
1237
1238static int usb4_port_write_data(struct tb_port *port, const void *data,
1239 size_t dwords)
1240{
1241 if (dwords > USB4_DATA_DWORDS)
1242 return -EINVAL;
1243
1244 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1245 dwords);
1246}
1247
1248static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target,
1249 u8 index, u8 reg, void *buf, u8 size)
1250{
1251 size_t dwords = DIV_ROUND_UP(size, 4);
1252 int ret;
1253 u32 val;
1254
1255 if (!port->cap_usb4)
1256 return -EINVAL;
1257
1258 val = reg;
1259 val |= size << PORT_CS_1_LENGTH_SHIFT;
1260 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1261 if (target == USB4_SB_TARGET_RETIMER)
1262 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1263 val |= PORT_CS_1_PND;
1264
1265 ret = tb_port_write(port, &val, TB_CFG_PORT,
1266 port->cap_usb4 + PORT_CS_1, 1);
1267 if (ret)
1268 return ret;
1269
1270 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1271 PORT_CS_1_PND, 0, 500);
1272 if (ret)
1273 return ret;
1274
1275 ret = tb_port_read(port, &val, TB_CFG_PORT,
1276 port->cap_usb4 + PORT_CS_1, 1);
1277 if (ret)
1278 return ret;
1279
1280 if (val & PORT_CS_1_NR)
1281 return -ENODEV;
1282 if (val & PORT_CS_1_RC)
1283 return -EIO;
1284
1285 return buf ? usb4_port_read_data(port, buf, dwords) : 0;
1286}
1287
1288static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1289 u8 index, u8 reg, const void *buf, u8 size)
1290{
1291 size_t dwords = DIV_ROUND_UP(size, 4);
1292 int ret;
1293 u32 val;
1294
1295 if (!port->cap_usb4)
1296 return -EINVAL;
1297
1298 if (buf) {
1299 ret = usb4_port_write_data(port, buf, dwords);
1300 if (ret)
1301 return ret;
1302 }
1303
1304 val = reg;
1305 val |= size << PORT_CS_1_LENGTH_SHIFT;
1306 val |= PORT_CS_1_WNR_WRITE;
1307 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1308 if (target == USB4_SB_TARGET_RETIMER)
1309 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1310 val |= PORT_CS_1_PND;
1311
1312 ret = tb_port_write(port, &val, TB_CFG_PORT,
1313 port->cap_usb4 + PORT_CS_1, 1);
1314 if (ret)
1315 return ret;
1316
1317 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1318 PORT_CS_1_PND, 0, 500);
1319 if (ret)
1320 return ret;
1321
1322 ret = tb_port_read(port, &val, TB_CFG_PORT,
1323 port->cap_usb4 + PORT_CS_1, 1);
1324 if (ret)
1325 return ret;
1326
1327 if (val & PORT_CS_1_NR)
1328 return -ENODEV;
1329 if (val & PORT_CS_1_RC)
1330 return -EIO;
1331
1332 return 0;
1333}
1334
1335static int usb4_port_sb_opcode_err_to_errno(u32 val)
1336{
1337 switch (val) {
1338 case 0:
1339 return 0;
1340 case USB4_SB_OPCODE_ERR:
1341 return -EAGAIN;
1342 case USB4_SB_OPCODE_ONS:
1343 return -EOPNOTSUPP;
1344 default:
1345 return -EIO;
1346 }
1347}
1348
1349static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1350 u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1351{
1352 ktime_t timeout;
1353 u32 val;
1354 int ret;
1355
1356 val = opcode;
1357 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val,
1358 sizeof(val));
1359 if (ret)
1360 return ret;
1361
1362 timeout = ktime_add_ms(ktime_get(), timeout_msec);
1363
1364 do {
1365 /* Check results */
1366 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1367 &val, sizeof(val));
1368 if (ret)
1369 return ret;
1370
1371 if (val != opcode)
1372 return usb4_port_sb_opcode_err_to_errno(val);
1373 } while (ktime_before(ktime_get(), timeout));
1374
1375 return -ETIMEDOUT;
1376}
1377
1378static int usb4_port_set_router_offline(struct tb_port *port, bool offline)
1379{
1380 u32 val = !offline;
1381 int ret;
1382
1383 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1384 USB4_SB_METADATA, &val, sizeof(val));
1385 if (ret)
1386 return ret;
1387
1388 val = USB4_SB_OPCODE_ROUTER_OFFLINE;
1389 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1390 USB4_SB_OPCODE, &val, sizeof(val));
1391}
1392
1393/**
1394 * usb4_port_router_offline() - Put the USB4 port to offline mode
1395 * @port: USB4 port
1396 *
1397 * This function puts the USB4 port into offline mode. In this mode the
1398 * port does not react on hotplug events anymore. This needs to be
1399 * called before retimer access is done when the USB4 links is not up.
1400 *
1401 * Returns %0 in case of success and negative errno if there was an
1402 * error.
1403 */
1404int usb4_port_router_offline(struct tb_port *port)
1405{
1406 return usb4_port_set_router_offline(port, true);
1407}
1408
1409/**
1410 * usb4_port_router_online() - Put the USB4 port back to online
1411 * @port: USB4 port
1412 *
1413 * Makes the USB4 port functional again.
1414 */
1415int usb4_port_router_online(struct tb_port *port)
1416{
1417 return usb4_port_set_router_offline(port, false);
1418}
1419
1420/**
1421 * usb4_port_enumerate_retimers() - Send RT broadcast transaction
1422 * @port: USB4 port
1423 *
1424 * This forces the USB4 port to send broadcast RT transaction which
1425 * makes the retimers on the link to assign index to themselves. Returns
1426 * %0 in case of success and negative errno if there was an error.
1427 */
1428int usb4_port_enumerate_retimers(struct tb_port *port)
1429{
1430 u32 val;
1431
1432 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1433 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1434 USB4_SB_OPCODE, &val, sizeof(val));
1435}
1436
1437/**
1438 * usb4_port_clx_supported() - Check if CLx is supported by the link
1439 * @port: Port to check for CLx support for
1440 *
1441 * PORT_CS_18_CPS bit reflects if the link supports CLx including
1442 * active cables (if connected on the link).
1443 */
1444bool usb4_port_clx_supported(struct tb_port *port)
1445{
1446 int ret;
1447 u32 val;
1448
1449 ret = tb_port_read(port, &val, TB_CFG_PORT,
1450 port->cap_usb4 + PORT_CS_18, 1);
1451 if (ret)
1452 return false;
1453
1454 return !!(val & PORT_CS_18_CPS);
1455}
1456
1457/**
1458 * usb4_port_asym_supported() - If the port supports asymmetric link
1459 * @port: USB4 port
1460 *
1461 * Checks if the port and the cable supports asymmetric link and returns
1462 * %true in that case.
1463 */
1464bool usb4_port_asym_supported(struct tb_port *port)
1465{
1466 u32 val;
1467
1468 if (!port->cap_usb4)
1469 return false;
1470
1471 if (tb_port_read(port, &val, TB_CFG_PORT, port->cap_usb4 + PORT_CS_18, 1))
1472 return false;
1473
1474 return !!(val & PORT_CS_18_CSA);
1475}
1476
1477/**
1478 * usb4_port_asym_set_link_width() - Set link width to asymmetric or symmetric
1479 * @port: USB4 port
1480 * @width: Asymmetric width to configure
1481 *
1482 * Sets USB4 port link width to @width. Can be called for widths where
1483 * usb4_port_asym_width_supported() returned @true.
1484 */
1485int usb4_port_asym_set_link_width(struct tb_port *port, enum tb_link_width width)
1486{
1487 u32 val;
1488 int ret;
1489
1490 if (!port->cap_phy)
1491 return -EINVAL;
1492
1493 ret = tb_port_read(port, &val, TB_CFG_PORT,
1494 port->cap_phy + LANE_ADP_CS_1, 1);
1495 if (ret)
1496 return ret;
1497
1498 val &= ~LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK;
1499 switch (width) {
1500 case TB_LINK_WIDTH_DUAL:
1501 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1502 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL);
1503 break;
1504 case TB_LINK_WIDTH_ASYM_TX:
1505 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1506 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX);
1507 break;
1508 case TB_LINK_WIDTH_ASYM_RX:
1509 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1510 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX);
1511 break;
1512 default:
1513 return -EINVAL;
1514 }
1515
1516 return tb_port_write(port, &val, TB_CFG_PORT,
1517 port->cap_phy + LANE_ADP_CS_1, 1);
1518}
1519
1520/**
1521 * usb4_port_asym_start() - Start symmetry change and wait for completion
1522 * @port: USB4 port
1523 *
1524 * Start symmetry change of the link to asymmetric or symmetric
1525 * (according to what was previously set in tb_port_set_link_width().
1526 * Wait for completion of the change.
1527 *
1528 * Returns %0 in case of success, %-ETIMEDOUT if case of timeout or
1529 * a negative errno in case of a failure.
1530 */
1531int usb4_port_asym_start(struct tb_port *port)
1532{
1533 int ret;
1534 u32 val;
1535
1536 ret = tb_port_read(port, &val, TB_CFG_PORT,
1537 port->cap_usb4 + PORT_CS_19, 1);
1538 if (ret)
1539 return ret;
1540
1541 val &= ~PORT_CS_19_START_ASYM;
1542 val |= FIELD_PREP(PORT_CS_19_START_ASYM, 1);
1543
1544 ret = tb_port_write(port, &val, TB_CFG_PORT,
1545 port->cap_usb4 + PORT_CS_19, 1);
1546 if (ret)
1547 return ret;
1548
1549 /*
1550 * Wait for PORT_CS_19_START_ASYM to be 0. This means the USB4
1551 * port started the symmetry transition.
1552 */
1553 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_19,
1554 PORT_CS_19_START_ASYM, 0, 1000);
1555 if (ret)
1556 return ret;
1557
1558 /* Then wait for the transtion to be completed */
1559 return usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_18,
1560 PORT_CS_18_TIP, 0, 5000);
1561}
1562
1563/**
1564 * usb4_port_margining_caps() - Read USB4 port marginig capabilities
1565 * @port: USB4 port
1566 * @caps: Array with at least two elements to hold the results
1567 *
1568 * Reads the USB4 port lane margining capabilities into @caps.
1569 */
1570int usb4_port_margining_caps(struct tb_port *port, u32 *caps)
1571{
1572 int ret;
1573
1574 ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1575 USB4_SB_OPCODE_READ_LANE_MARGINING_CAP, 500);
1576 if (ret)
1577 return ret;
1578
1579 return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1580 USB4_SB_DATA, caps, sizeof(*caps) * 2);
1581}
1582
1583/**
1584 * usb4_port_hw_margin() - Run hardware lane margining on port
1585 * @port: USB4 port
1586 * @lanes: Which lanes to run (must match the port capabilities). Can be
1587 * %0, %1 or %7.
1588 * @ber_level: BER level contour value
1589 * @timing: Perform timing margining instead of voltage
1590 * @right_high: Use Right/high margin instead of left/low
1591 * @results: Array with at least two elements to hold the results
1592 *
1593 * Runs hardware lane margining on USB4 port and returns the result in
1594 * @results.
1595 */
1596int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes,
1597 unsigned int ber_level, bool timing, bool right_high,
1598 u32 *results)
1599{
1600 u32 val;
1601 int ret;
1602
1603 val = lanes;
1604 if (timing)
1605 val |= USB4_MARGIN_HW_TIME;
1606 if (right_high)
1607 val |= USB4_MARGIN_HW_RH;
1608 if (ber_level)
1609 val |= (ber_level << USB4_MARGIN_HW_BER_SHIFT) &
1610 USB4_MARGIN_HW_BER_MASK;
1611
1612 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1613 USB4_SB_METADATA, &val, sizeof(val));
1614 if (ret)
1615 return ret;
1616
1617 ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1618 USB4_SB_OPCODE_RUN_HW_LANE_MARGINING, 2500);
1619 if (ret)
1620 return ret;
1621
1622 return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1623 USB4_SB_DATA, results, sizeof(*results) * 2);
1624}
1625
1626/**
1627 * usb4_port_sw_margin() - Run software lane margining on port
1628 * @port: USB4 port
1629 * @lanes: Which lanes to run (must match the port capabilities). Can be
1630 * %0, %1 or %7.
1631 * @timing: Perform timing margining instead of voltage
1632 * @right_high: Use Right/high margin instead of left/low
1633 * @counter: What to do with the error counter
1634 *
1635 * Runs software lane margining on USB4 port. Read back the error
1636 * counters by calling usb4_port_sw_margin_errors(). Returns %0 in
1637 * success and negative errno otherwise.
1638 */
1639int usb4_port_sw_margin(struct tb_port *port, unsigned int lanes, bool timing,
1640 bool right_high, u32 counter)
1641{
1642 u32 val;
1643 int ret;
1644
1645 val = lanes;
1646 if (timing)
1647 val |= USB4_MARGIN_SW_TIME;
1648 if (right_high)
1649 val |= USB4_MARGIN_SW_RH;
1650 val |= (counter << USB4_MARGIN_SW_COUNTER_SHIFT) &
1651 USB4_MARGIN_SW_COUNTER_MASK;
1652
1653 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1654 USB4_SB_METADATA, &val, sizeof(val));
1655 if (ret)
1656 return ret;
1657
1658 return usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1659 USB4_SB_OPCODE_RUN_SW_LANE_MARGINING, 2500);
1660}
1661
1662/**
1663 * usb4_port_sw_margin_errors() - Read the software margining error counters
1664 * @port: USB4 port
1665 * @errors: Error metadata is copied here.
1666 *
1667 * This reads back the software margining error counters from the port.
1668 * Returns %0 in success and negative errno otherwise.
1669 */
1670int usb4_port_sw_margin_errors(struct tb_port *port, u32 *errors)
1671{
1672 int ret;
1673
1674 ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1675 USB4_SB_OPCODE_READ_SW_MARGIN_ERR, 150);
1676 if (ret)
1677 return ret;
1678
1679 return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1680 USB4_SB_METADATA, errors, sizeof(*errors));
1681}
1682
1683static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1684 enum usb4_sb_opcode opcode,
1685 int timeout_msec)
1686{
1687 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode,
1688 timeout_msec);
1689}
1690
1691/**
1692 * usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions
1693 * @port: USB4 port
1694 * @index: Retimer index
1695 *
1696 * Enables sideband channel transations on SBTX. Can be used when USB4
1697 * link does not go up, for example if there is no device connected.
1698 */
1699int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index)
1700{
1701 int ret;
1702
1703 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1704 500);
1705
1706 if (ret != -ENODEV)
1707 return ret;
1708
1709 /*
1710 * Per the USB4 retimer spec, the retimer is not required to
1711 * send an RT (Retimer Transaction) response for the first
1712 * SET_INBOUND_SBTX command
1713 */
1714 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1715 500);
1716}
1717
1718/**
1719 * usb4_port_retimer_unset_inbound_sbtx() - Disable sideband channel transactions
1720 * @port: USB4 port
1721 * @index: Retimer index
1722 *
1723 * Disables sideband channel transations on SBTX. The reverse of
1724 * usb4_port_retimer_set_inbound_sbtx().
1725 */
1726int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index)
1727{
1728 return usb4_port_retimer_op(port, index,
1729 USB4_SB_OPCODE_UNSET_INBOUND_SBTX, 500);
1730}
1731
1732/**
1733 * usb4_port_retimer_read() - Read from retimer sideband registers
1734 * @port: USB4 port
1735 * @index: Retimer index
1736 * @reg: Sideband register to read
1737 * @buf: Data from @reg is stored here
1738 * @size: Number of bytes to read
1739 *
1740 * Function reads retimer sideband registers starting from @reg. The
1741 * retimer is connected to @port at @index. Returns %0 in case of
1742 * success, and read data is copied to @buf. If there is no retimer
1743 * present at given @index returns %-ENODEV. In any other failure
1744 * returns negative errno.
1745 */
1746int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf,
1747 u8 size)
1748{
1749 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1750 size);
1751}
1752
1753/**
1754 * usb4_port_retimer_write() - Write to retimer sideband registers
1755 * @port: USB4 port
1756 * @index: Retimer index
1757 * @reg: Sideband register to write
1758 * @buf: Data that is written starting from @reg
1759 * @size: Number of bytes to write
1760 *
1761 * Writes retimer sideband registers starting from @reg. The retimer is
1762 * connected to @port at @index. Returns %0 in case of success. If there
1763 * is no retimer present at given @index returns %-ENODEV. In any other
1764 * failure returns negative errno.
1765 */
1766int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg,
1767 const void *buf, u8 size)
1768{
1769 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1770 size);
1771}
1772
1773/**
1774 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1775 * @port: USB4 port
1776 * @index: Retimer index
1777 *
1778 * If the retimer at @index is last one (connected directly to the
1779 * Type-C port) this function returns %1. If it is not returns %0. If
1780 * the retimer is not present returns %-ENODEV. Otherwise returns
1781 * negative errno.
1782 */
1783int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1784{
1785 u32 metadata;
1786 int ret;
1787
1788 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1789 500);
1790 if (ret)
1791 return ret;
1792
1793 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1794 sizeof(metadata));
1795 return ret ? ret : metadata & 1;
1796}
1797
1798/**
1799 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1800 * @port: USB4 port
1801 * @index: Retimer index
1802 *
1803 * Reads NVM sector size (in bytes) of a retimer at @index. This
1804 * operation can be used to determine whether the retimer supports NVM
1805 * upgrade for example. Returns sector size in bytes or negative errno
1806 * in case of error. Specifically returns %-ENODEV if there is no
1807 * retimer at @index.
1808 */
1809int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1810{
1811 u32 metadata;
1812 int ret;
1813
1814 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1815 500);
1816 if (ret)
1817 return ret;
1818
1819 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1820 sizeof(metadata));
1821 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1822}
1823
1824/**
1825 * usb4_port_retimer_nvm_set_offset() - Set NVM write offset
1826 * @port: USB4 port
1827 * @index: Retimer index
1828 * @address: Start offset
1829 *
1830 * Exlicitly sets NVM write offset. Normally when writing to NVM this is
1831 * done automatically by usb4_port_retimer_nvm_write().
1832 *
1833 * Returns %0 in success and negative errno if there was a failure.
1834 */
1835int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1836 unsigned int address)
1837{
1838 u32 metadata, dwaddress;
1839 int ret;
1840
1841 dwaddress = address / 4;
1842 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
1843 USB4_NVM_SET_OFFSET_MASK;
1844
1845 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1846 sizeof(metadata));
1847 if (ret)
1848 return ret;
1849
1850 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET,
1851 500);
1852}
1853
1854struct retimer_info {
1855 struct tb_port *port;
1856 u8 index;
1857};
1858
1859static int usb4_port_retimer_nvm_write_next_block(void *data,
1860 unsigned int dwaddress, const void *buf, size_t dwords)
1861
1862{
1863 const struct retimer_info *info = data;
1864 struct tb_port *port = info->port;
1865 u8 index = info->index;
1866 int ret;
1867
1868 ret = usb4_port_retimer_write(port, index, USB4_SB_DATA,
1869 buf, dwords * 4);
1870 if (ret)
1871 return ret;
1872
1873 return usb4_port_retimer_op(port, index,
1874 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000);
1875}
1876
1877/**
1878 * usb4_port_retimer_nvm_write() - Write to retimer NVM
1879 * @port: USB4 port
1880 * @index: Retimer index
1881 * @address: Byte address where to start the write
1882 * @buf: Data to write
1883 * @size: Size in bytes how much to write
1884 *
1885 * Writes @size bytes from @buf to the retimer NVM. Used for NVM
1886 * upgrade. Returns %0 if the data was written successfully and negative
1887 * errno in case of failure. Specifically returns %-ENODEV if there is
1888 * no retimer at @index.
1889 */
1890int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
1891 const void *buf, size_t size)
1892{
1893 struct retimer_info info = { .port = port, .index = index };
1894 int ret;
1895
1896 ret = usb4_port_retimer_nvm_set_offset(port, index, address);
1897 if (ret)
1898 return ret;
1899
1900 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
1901 usb4_port_retimer_nvm_write_next_block, &info);
1902}
1903
1904/**
1905 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
1906 * @port: USB4 port
1907 * @index: Retimer index
1908 *
1909 * After the new NVM image has been written via usb4_port_retimer_nvm_write()
1910 * this function can be used to trigger the NVM upgrade process. If
1911 * successful the retimer restarts with the new NVM and may not have the
1912 * index set so one needs to call usb4_port_enumerate_retimers() to
1913 * force index to be assigned.
1914 */
1915int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
1916{
1917 u32 val;
1918
1919 /*
1920 * We need to use the raw operation here because once the
1921 * authentication completes the retimer index is not set anymore
1922 * so we do not get back the status now.
1923 */
1924 val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
1925 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1926 USB4_SB_OPCODE, &val, sizeof(val));
1927}
1928
1929/**
1930 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
1931 * @port: USB4 port
1932 * @index: Retimer index
1933 * @status: Raw status code read from metadata
1934 *
1935 * This can be called after usb4_port_retimer_nvm_authenticate() and
1936 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
1937 *
1938 * Returns %0 if the authentication status was successfully read. The
1939 * completion metadata (the result) is then stored into @status. If
1940 * reading the status fails, returns negative errno.
1941 */
1942int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
1943 u32 *status)
1944{
1945 u32 metadata, val;
1946 int ret;
1947
1948 ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val,
1949 sizeof(val));
1950 if (ret)
1951 return ret;
1952
1953 ret = usb4_port_sb_opcode_err_to_errno(val);
1954 switch (ret) {
1955 case 0:
1956 *status = 0;
1957 return 0;
1958
1959 case -EAGAIN:
1960 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA,
1961 &metadata, sizeof(metadata));
1962 if (ret)
1963 return ret;
1964
1965 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
1966 return 0;
1967
1968 default:
1969 return ret;
1970 }
1971}
1972
1973static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
1974 void *buf, size_t dwords)
1975{
1976 const struct retimer_info *info = data;
1977 struct tb_port *port = info->port;
1978 u8 index = info->index;
1979 u32 metadata;
1980 int ret;
1981
1982 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
1983 if (dwords < USB4_DATA_DWORDS)
1984 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
1985
1986 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1987 sizeof(metadata));
1988 if (ret)
1989 return ret;
1990
1991 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500);
1992 if (ret)
1993 return ret;
1994
1995 return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf,
1996 dwords * 4);
1997}
1998
1999/**
2000 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM
2001 * @port: USB4 port
2002 * @index: Retimer index
2003 * @address: NVM address (in bytes) to start reading
2004 * @buf: Data read from NVM is stored here
2005 * @size: Number of bytes to read
2006 *
2007 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the
2008 * read was successful and negative errno in case of failure.
2009 * Specifically returns %-ENODEV if there is no retimer at @index.
2010 */
2011int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
2012 unsigned int address, void *buf, size_t size)
2013{
2014 struct retimer_info info = { .port = port, .index = index };
2015
2016 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
2017 usb4_port_retimer_nvm_read_block, &info);
2018}
2019
2020static inline unsigned int
2021usb4_usb3_port_max_bandwidth(const struct tb_port *port, unsigned int bw)
2022{
2023 /* Take the possible bandwidth limitation into account */
2024 if (port->max_bw)
2025 return min(bw, port->max_bw);
2026 return bw;
2027}
2028
2029/**
2030 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate
2031 * @port: USB3 adapter port
2032 *
2033 * Return maximum supported link rate of a USB3 adapter in Mb/s.
2034 * Negative errno in case of error.
2035 */
2036int usb4_usb3_port_max_link_rate(struct tb_port *port)
2037{
2038 int ret, lr;
2039 u32 val;
2040
2041 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
2042 return -EINVAL;
2043
2044 ret = tb_port_read(port, &val, TB_CFG_PORT,
2045 port->cap_adap + ADP_USB3_CS_4, 1);
2046 if (ret)
2047 return ret;
2048
2049 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
2050 ret = lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
2051
2052 return usb4_usb3_port_max_bandwidth(port, ret);
2053}
2054
2055static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
2056{
2057 int ret;
2058 u32 val;
2059
2060 if (!tb_port_is_usb3_down(port))
2061 return -EINVAL;
2062 if (tb_route(port->sw))
2063 return -EINVAL;
2064
2065 ret = tb_port_read(port, &val, TB_CFG_PORT,
2066 port->cap_adap + ADP_USB3_CS_2, 1);
2067 if (ret)
2068 return ret;
2069
2070 if (request)
2071 val |= ADP_USB3_CS_2_CMR;
2072 else
2073 val &= ~ADP_USB3_CS_2_CMR;
2074
2075 ret = tb_port_write(port, &val, TB_CFG_PORT,
2076 port->cap_adap + ADP_USB3_CS_2, 1);
2077 if (ret)
2078 return ret;
2079
2080 /*
2081 * We can use val here directly as the CMR bit is in the same place
2082 * as HCA. Just mask out others.
2083 */
2084 val &= ADP_USB3_CS_2_CMR;
2085 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1,
2086 ADP_USB3_CS_1_HCA, val, 1500);
2087}
2088
2089static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
2090{
2091 return usb4_usb3_port_cm_request(port, true);
2092}
2093
2094static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
2095{
2096 return usb4_usb3_port_cm_request(port, false);
2097}
2098
2099static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
2100{
2101 unsigned long uframes;
2102
2103 uframes = bw * 512UL << scale;
2104 return DIV_ROUND_CLOSEST(uframes * 8000, MEGA);
2105}
2106
2107static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
2108{
2109 unsigned long uframes;
2110
2111 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
2112 uframes = ((unsigned long)mbps * MEGA) / 8000;
2113 return DIV_ROUND_UP(uframes, 512UL << scale);
2114}
2115
2116static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
2117 int *upstream_bw,
2118 int *downstream_bw)
2119{
2120 u32 val, bw, scale;
2121 int ret;
2122
2123 ret = tb_port_read(port, &val, TB_CFG_PORT,
2124 port->cap_adap + ADP_USB3_CS_2, 1);
2125 if (ret)
2126 return ret;
2127
2128 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2129 port->cap_adap + ADP_USB3_CS_3, 1);
2130 if (ret)
2131 return ret;
2132
2133 scale &= ADP_USB3_CS_3_SCALE_MASK;
2134
2135 bw = val & ADP_USB3_CS_2_AUBW_MASK;
2136 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2137
2138 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
2139 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2140
2141 return 0;
2142}
2143
2144/**
2145 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
2146 * @port: USB3 adapter port
2147 * @upstream_bw: Allocated upstream bandwidth is stored here
2148 * @downstream_bw: Allocated downstream bandwidth is stored here
2149 *
2150 * Stores currently allocated USB3 bandwidth into @upstream_bw and
2151 * @downstream_bw in Mb/s. Returns %0 in case of success and negative
2152 * errno in failure.
2153 */
2154int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
2155 int *downstream_bw)
2156{
2157 int ret;
2158
2159 ret = usb4_usb3_port_set_cm_request(port);
2160 if (ret)
2161 return ret;
2162
2163 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
2164 downstream_bw);
2165 usb4_usb3_port_clear_cm_request(port);
2166
2167 return ret;
2168}
2169
2170static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
2171 int *upstream_bw,
2172 int *downstream_bw)
2173{
2174 u32 val, bw, scale;
2175 int ret;
2176
2177 ret = tb_port_read(port, &val, TB_CFG_PORT,
2178 port->cap_adap + ADP_USB3_CS_1, 1);
2179 if (ret)
2180 return ret;
2181
2182 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2183 port->cap_adap + ADP_USB3_CS_3, 1);
2184 if (ret)
2185 return ret;
2186
2187 scale &= ADP_USB3_CS_3_SCALE_MASK;
2188
2189 bw = val & ADP_USB3_CS_1_CUBW_MASK;
2190 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2191
2192 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
2193 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2194
2195 return 0;
2196}
2197
2198static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
2199 int upstream_bw,
2200 int downstream_bw)
2201{
2202 u32 val, ubw, dbw, scale;
2203 int ret, max_bw;
2204
2205 /* Figure out suitable scale */
2206 scale = 0;
2207 max_bw = max(upstream_bw, downstream_bw);
2208 while (scale < 64) {
2209 if (mbps_to_usb3_bw(max_bw, scale) < 4096)
2210 break;
2211 scale++;
2212 }
2213
2214 if (WARN_ON(scale >= 64))
2215 return -EINVAL;
2216
2217 ret = tb_port_write(port, &scale, TB_CFG_PORT,
2218 port->cap_adap + ADP_USB3_CS_3, 1);
2219 if (ret)
2220 return ret;
2221
2222 ubw = mbps_to_usb3_bw(upstream_bw, scale);
2223 dbw = mbps_to_usb3_bw(downstream_bw, scale);
2224
2225 tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale);
2226
2227 ret = tb_port_read(port, &val, TB_CFG_PORT,
2228 port->cap_adap + ADP_USB3_CS_2, 1);
2229 if (ret)
2230 return ret;
2231
2232 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
2233 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
2234 val |= ubw;
2235
2236 return tb_port_write(port, &val, TB_CFG_PORT,
2237 port->cap_adap + ADP_USB3_CS_2, 1);
2238}
2239
2240/**
2241 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
2242 * @port: USB3 adapter port
2243 * @upstream_bw: New upstream bandwidth
2244 * @downstream_bw: New downstream bandwidth
2245 *
2246 * This can be used to set how much bandwidth is allocated for the USB3
2247 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
2248 * new values programmed to the USB3 adapter allocation registers. If
2249 * the values are lower than what is currently consumed the allocation
2250 * is set to what is currently consumed instead (consumed bandwidth
2251 * cannot be taken away by CM). The actual new values are returned in
2252 * @upstream_bw and @downstream_bw.
2253 *
2254 * Returns %0 in case of success and negative errno if there was a
2255 * failure.
2256 */
2257int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
2258 int *downstream_bw)
2259{
2260 int ret, consumed_up, consumed_down, allocate_up, allocate_down;
2261
2262 ret = usb4_usb3_port_set_cm_request(port);
2263 if (ret)
2264 return ret;
2265
2266 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2267 &consumed_down);
2268 if (ret)
2269 goto err_request;
2270
2271 /* Don't allow it go lower than what is consumed */
2272 allocate_up = max(*upstream_bw, consumed_up);
2273 allocate_down = max(*downstream_bw, consumed_down);
2274
2275 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up,
2276 allocate_down);
2277 if (ret)
2278 goto err_request;
2279
2280 *upstream_bw = allocate_up;
2281 *downstream_bw = allocate_down;
2282
2283err_request:
2284 usb4_usb3_port_clear_cm_request(port);
2285 return ret;
2286}
2287
2288/**
2289 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
2290 * @port: USB3 adapter port
2291 * @upstream_bw: New allocated upstream bandwidth
2292 * @downstream_bw: New allocated downstream bandwidth
2293 *
2294 * Releases USB3 allocated bandwidth down to what is actually consumed.
2295 * The new bandwidth is returned in @upstream_bw and @downstream_bw.
2296 *
2297 * Returns 0% in success and negative errno in case of failure.
2298 */
2299int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
2300 int *downstream_bw)
2301{
2302 int ret, consumed_up, consumed_down;
2303
2304 ret = usb4_usb3_port_set_cm_request(port);
2305 if (ret)
2306 return ret;
2307
2308 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2309 &consumed_down);
2310 if (ret)
2311 goto err_request;
2312
2313 /*
2314 * Always keep 900 Mb/s to make sure xHCI has at least some
2315 * bandwidth available for isochronous traffic.
2316 */
2317 if (consumed_up < 900)
2318 consumed_up = 900;
2319 if (consumed_down < 900)
2320 consumed_down = 900;
2321
2322 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up,
2323 consumed_down);
2324 if (ret)
2325 goto err_request;
2326
2327 *upstream_bw = consumed_up;
2328 *downstream_bw = consumed_down;
2329
2330err_request:
2331 usb4_usb3_port_clear_cm_request(port);
2332 return ret;
2333}
2334
2335static bool is_usb4_dpin(const struct tb_port *port)
2336{
2337 if (!tb_port_is_dpin(port))
2338 return false;
2339 if (!tb_switch_is_usb4(port->sw))
2340 return false;
2341 return true;
2342}
2343
2344/**
2345 * usb4_dp_port_set_cm_id() - Assign CM ID to the DP IN adapter
2346 * @port: DP IN adapter
2347 * @cm_id: CM ID to assign
2348 *
2349 * Sets CM ID for the @port. Returns %0 on success and negative errno
2350 * otherwise. Speficially returns %-EOPNOTSUPP if the @port does not
2351 * support this.
2352 */
2353int usb4_dp_port_set_cm_id(struct tb_port *port, int cm_id)
2354{
2355 u32 val;
2356 int ret;
2357
2358 if (!is_usb4_dpin(port))
2359 return -EOPNOTSUPP;
2360
2361 ret = tb_port_read(port, &val, TB_CFG_PORT,
2362 port->cap_adap + ADP_DP_CS_2, 1);
2363 if (ret)
2364 return ret;
2365
2366 val &= ~ADP_DP_CS_2_CM_ID_MASK;
2367 val |= cm_id << ADP_DP_CS_2_CM_ID_SHIFT;
2368
2369 return tb_port_write(port, &val, TB_CFG_PORT,
2370 port->cap_adap + ADP_DP_CS_2, 1);
2371}
2372
2373/**
2374 * usb4_dp_port_bandwidth_mode_supported() - Is the bandwidth allocation mode
2375 * supported
2376 * @port: DP IN adapter to check
2377 *
2378 * Can be called to any DP IN adapter. Returns true if the adapter
2379 * supports USB4 bandwidth allocation mode, false otherwise.
2380 */
2381bool usb4_dp_port_bandwidth_mode_supported(struct tb_port *port)
2382{
2383 int ret;
2384 u32 val;
2385
2386 if (!is_usb4_dpin(port))
2387 return false;
2388
2389 ret = tb_port_read(port, &val, TB_CFG_PORT,
2390 port->cap_adap + DP_LOCAL_CAP, 1);
2391 if (ret)
2392 return false;
2393
2394 return !!(val & DP_COMMON_CAP_BW_MODE);
2395}
2396
2397/**
2398 * usb4_dp_port_bandwidth_mode_enabled() - Is the bandwidth allocation mode
2399 * enabled
2400 * @port: DP IN adapter to check
2401 *
2402 * Can be called to any DP IN adapter. Returns true if the bandwidth
2403 * allocation mode has been enabled, false otherwise.
2404 */
2405bool usb4_dp_port_bandwidth_mode_enabled(struct tb_port *port)
2406{
2407 int ret;
2408 u32 val;
2409
2410 if (!is_usb4_dpin(port))
2411 return false;
2412
2413 ret = tb_port_read(port, &val, TB_CFG_PORT,
2414 port->cap_adap + ADP_DP_CS_8, 1);
2415 if (ret)
2416 return false;
2417
2418 return !!(val & ADP_DP_CS_8_DPME);
2419}
2420
2421/**
2422 * usb4_dp_port_set_cm_bandwidth_mode_supported() - Set/clear CM support for
2423 * bandwidth allocation mode
2424 * @port: DP IN adapter
2425 * @supported: Does the CM support bandwidth allocation mode
2426 *
2427 * Can be called to any DP IN adapter. Sets or clears the CM support bit
2428 * of the DP IN adapter. Returns %0 in success and negative errno
2429 * otherwise. Specifically returns %-OPNOTSUPP if the passed in adapter
2430 * does not support this.
2431 */
2432int usb4_dp_port_set_cm_bandwidth_mode_supported(struct tb_port *port,
2433 bool supported)
2434{
2435 u32 val;
2436 int ret;
2437
2438 if (!is_usb4_dpin(port))
2439 return -EOPNOTSUPP;
2440
2441 ret = tb_port_read(port, &val, TB_CFG_PORT,
2442 port->cap_adap + ADP_DP_CS_2, 1);
2443 if (ret)
2444 return ret;
2445
2446 if (supported)
2447 val |= ADP_DP_CS_2_CMMS;
2448 else
2449 val &= ~ADP_DP_CS_2_CMMS;
2450
2451 return tb_port_write(port, &val, TB_CFG_PORT,
2452 port->cap_adap + ADP_DP_CS_2, 1);
2453}
2454
2455/**
2456 * usb4_dp_port_group_id() - Return Group ID assigned for the adapter
2457 * @port: DP IN adapter
2458 *
2459 * Reads bandwidth allocation Group ID from the DP IN adapter and
2460 * returns it. If the adapter does not support setting Group_ID
2461 * %-EOPNOTSUPP is returned.
2462 */
2463int usb4_dp_port_group_id(struct tb_port *port)
2464{
2465 u32 val;
2466 int ret;
2467
2468 if (!is_usb4_dpin(port))
2469 return -EOPNOTSUPP;
2470
2471 ret = tb_port_read(port, &val, TB_CFG_PORT,
2472 port->cap_adap + ADP_DP_CS_2, 1);
2473 if (ret)
2474 return ret;
2475
2476 return (val & ADP_DP_CS_2_GROUP_ID_MASK) >> ADP_DP_CS_2_GROUP_ID_SHIFT;
2477}
2478
2479/**
2480 * usb4_dp_port_set_group_id() - Set adapter Group ID
2481 * @port: DP IN adapter
2482 * @group_id: Group ID for the adapter
2483 *
2484 * Sets bandwidth allocation mode Group ID for the DP IN adapter.
2485 * Returns %0 in case of success and negative errno otherwise.
2486 * Specifically returns %-EOPNOTSUPP if the adapter does not support
2487 * this.
2488 */
2489int usb4_dp_port_set_group_id(struct tb_port *port, int group_id)
2490{
2491 u32 val;
2492 int ret;
2493
2494 if (!is_usb4_dpin(port))
2495 return -EOPNOTSUPP;
2496
2497 ret = tb_port_read(port, &val, TB_CFG_PORT,
2498 port->cap_adap + ADP_DP_CS_2, 1);
2499 if (ret)
2500 return ret;
2501
2502 val &= ~ADP_DP_CS_2_GROUP_ID_MASK;
2503 val |= group_id << ADP_DP_CS_2_GROUP_ID_SHIFT;
2504
2505 return tb_port_write(port, &val, TB_CFG_PORT,
2506 port->cap_adap + ADP_DP_CS_2, 1);
2507}
2508
2509/**
2510 * usb4_dp_port_nrd() - Read non-reduced rate and lanes
2511 * @port: DP IN adapter
2512 * @rate: Non-reduced rate in Mb/s is placed here
2513 * @lanes: Non-reduced lanes are placed here
2514 *
2515 * Reads the non-reduced rate and lanes from the DP IN adapter. Returns
2516 * %0 in success and negative errno otherwise. Specifically returns
2517 * %-EOPNOTSUPP if the adapter does not support this.
2518 */
2519int usb4_dp_port_nrd(struct tb_port *port, int *rate, int *lanes)
2520{
2521 u32 val, tmp;
2522 int ret;
2523
2524 if (!is_usb4_dpin(port))
2525 return -EOPNOTSUPP;
2526
2527 ret = tb_port_read(port, &val, TB_CFG_PORT,
2528 port->cap_adap + ADP_DP_CS_2, 1);
2529 if (ret)
2530 return ret;
2531
2532 tmp = (val & ADP_DP_CS_2_NRD_MLR_MASK) >> ADP_DP_CS_2_NRD_MLR_SHIFT;
2533 switch (tmp) {
2534 case DP_COMMON_CAP_RATE_RBR:
2535 *rate = 1620;
2536 break;
2537 case DP_COMMON_CAP_RATE_HBR:
2538 *rate = 2700;
2539 break;
2540 case DP_COMMON_CAP_RATE_HBR2:
2541 *rate = 5400;
2542 break;
2543 case DP_COMMON_CAP_RATE_HBR3:
2544 *rate = 8100;
2545 break;
2546 }
2547
2548 tmp = val & ADP_DP_CS_2_NRD_MLC_MASK;
2549 switch (tmp) {
2550 case DP_COMMON_CAP_1_LANE:
2551 *lanes = 1;
2552 break;
2553 case DP_COMMON_CAP_2_LANES:
2554 *lanes = 2;
2555 break;
2556 case DP_COMMON_CAP_4_LANES:
2557 *lanes = 4;
2558 break;
2559 }
2560
2561 return 0;
2562}
2563
2564/**
2565 * usb4_dp_port_set_nrd() - Set non-reduced rate and lanes
2566 * @port: DP IN adapter
2567 * @rate: Non-reduced rate in Mb/s
2568 * @lanes: Non-reduced lanes
2569 *
2570 * Before the capabilities reduction this function can be used to set
2571 * the non-reduced values for the DP IN adapter. Returns %0 in success
2572 * and negative errno otherwise. If the adapter does not support this
2573 * %-EOPNOTSUPP is returned.
2574 */
2575int usb4_dp_port_set_nrd(struct tb_port *port, int rate, int lanes)
2576{
2577 u32 val;
2578 int ret;
2579
2580 if (!is_usb4_dpin(port))
2581 return -EOPNOTSUPP;
2582
2583 ret = tb_port_read(port, &val, TB_CFG_PORT,
2584 port->cap_adap + ADP_DP_CS_2, 1);
2585 if (ret)
2586 return ret;
2587
2588 val &= ~ADP_DP_CS_2_NRD_MLR_MASK;
2589
2590 switch (rate) {
2591 case 1620:
2592 break;
2593 case 2700:
2594 val |= (DP_COMMON_CAP_RATE_HBR << ADP_DP_CS_2_NRD_MLR_SHIFT)
2595 & ADP_DP_CS_2_NRD_MLR_MASK;
2596 break;
2597 case 5400:
2598 val |= (DP_COMMON_CAP_RATE_HBR2 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2599 & ADP_DP_CS_2_NRD_MLR_MASK;
2600 break;
2601 case 8100:
2602 val |= (DP_COMMON_CAP_RATE_HBR3 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2603 & ADP_DP_CS_2_NRD_MLR_MASK;
2604 break;
2605 default:
2606 return -EINVAL;
2607 }
2608
2609 val &= ~ADP_DP_CS_2_NRD_MLC_MASK;
2610
2611 switch (lanes) {
2612 case 1:
2613 break;
2614 case 2:
2615 val |= DP_COMMON_CAP_2_LANES;
2616 break;
2617 case 4:
2618 val |= DP_COMMON_CAP_4_LANES;
2619 break;
2620 default:
2621 return -EINVAL;
2622 }
2623
2624 return tb_port_write(port, &val, TB_CFG_PORT,
2625 port->cap_adap + ADP_DP_CS_2, 1);
2626}
2627
2628/**
2629 * usb4_dp_port_granularity() - Return granularity for the bandwidth values
2630 * @port: DP IN adapter
2631 *
2632 * Reads the programmed granularity from @port. If the DP IN adapter does
2633 * not support bandwidth allocation mode returns %-EOPNOTSUPP and negative
2634 * errno in other error cases.
2635 */
2636int usb4_dp_port_granularity(struct tb_port *port)
2637{
2638 u32 val;
2639 int ret;
2640
2641 if (!is_usb4_dpin(port))
2642 return -EOPNOTSUPP;
2643
2644 ret = tb_port_read(port, &val, TB_CFG_PORT,
2645 port->cap_adap + ADP_DP_CS_2, 1);
2646 if (ret)
2647 return ret;
2648
2649 val &= ADP_DP_CS_2_GR_MASK;
2650 val >>= ADP_DP_CS_2_GR_SHIFT;
2651
2652 switch (val) {
2653 case ADP_DP_CS_2_GR_0_25G:
2654 return 250;
2655 case ADP_DP_CS_2_GR_0_5G:
2656 return 500;
2657 case ADP_DP_CS_2_GR_1G:
2658 return 1000;
2659 }
2660
2661 return -EINVAL;
2662}
2663
2664/**
2665 * usb4_dp_port_set_granularity() - Set granularity for the bandwidth values
2666 * @port: DP IN adapter
2667 * @granularity: Granularity in Mb/s. Supported values: 1000, 500 and 250.
2668 *
2669 * Sets the granularity used with the estimated, allocated and requested
2670 * bandwidth. Returns %0 in success and negative errno otherwise. If the
2671 * adapter does not support this %-EOPNOTSUPP is returned.
2672 */
2673int usb4_dp_port_set_granularity(struct tb_port *port, int granularity)
2674{
2675 u32 val;
2676 int ret;
2677
2678 if (!is_usb4_dpin(port))
2679 return -EOPNOTSUPP;
2680
2681 ret = tb_port_read(port, &val, TB_CFG_PORT,
2682 port->cap_adap + ADP_DP_CS_2, 1);
2683 if (ret)
2684 return ret;
2685
2686 val &= ~ADP_DP_CS_2_GR_MASK;
2687
2688 switch (granularity) {
2689 case 250:
2690 val |= ADP_DP_CS_2_GR_0_25G << ADP_DP_CS_2_GR_SHIFT;
2691 break;
2692 case 500:
2693 val |= ADP_DP_CS_2_GR_0_5G << ADP_DP_CS_2_GR_SHIFT;
2694 break;
2695 case 1000:
2696 val |= ADP_DP_CS_2_GR_1G << ADP_DP_CS_2_GR_SHIFT;
2697 break;
2698 default:
2699 return -EINVAL;
2700 }
2701
2702 return tb_port_write(port, &val, TB_CFG_PORT,
2703 port->cap_adap + ADP_DP_CS_2, 1);
2704}
2705
2706/**
2707 * usb4_dp_port_set_estimated_bandwidth() - Set estimated bandwidth
2708 * @port: DP IN adapter
2709 * @bw: Estimated bandwidth in Mb/s.
2710 *
2711 * Sets the estimated bandwidth to @bw. Set the granularity by calling
2712 * usb4_dp_port_set_granularity() before calling this. The @bw is round
2713 * down to the closest granularity multiplier. Returns %0 in success
2714 * and negative errno otherwise. Specifically returns %-EOPNOTSUPP if
2715 * the adapter does not support this.
2716 */
2717int usb4_dp_port_set_estimated_bandwidth(struct tb_port *port, int bw)
2718{
2719 u32 val, granularity;
2720 int ret;
2721
2722 if (!is_usb4_dpin(port))
2723 return -EOPNOTSUPP;
2724
2725 ret = usb4_dp_port_granularity(port);
2726 if (ret < 0)
2727 return ret;
2728 granularity = ret;
2729
2730 ret = tb_port_read(port, &val, TB_CFG_PORT,
2731 port->cap_adap + ADP_DP_CS_2, 1);
2732 if (ret)
2733 return ret;
2734
2735 val &= ~ADP_DP_CS_2_ESTIMATED_BW_MASK;
2736 val |= (bw / granularity) << ADP_DP_CS_2_ESTIMATED_BW_SHIFT;
2737
2738 return tb_port_write(port, &val, TB_CFG_PORT,
2739 port->cap_adap + ADP_DP_CS_2, 1);
2740}
2741
2742/**
2743 * usb4_dp_port_allocated_bandwidth() - Return allocated bandwidth
2744 * @port: DP IN adapter
2745 *
2746 * Reads and returns allocated bandwidth for @port in Mb/s (taking into
2747 * account the programmed granularity). Returns negative errno in case
2748 * of error.
2749 */
2750int usb4_dp_port_allocated_bandwidth(struct tb_port *port)
2751{
2752 u32 val, granularity;
2753 int ret;
2754
2755 if (!is_usb4_dpin(port))
2756 return -EOPNOTSUPP;
2757
2758 ret = usb4_dp_port_granularity(port);
2759 if (ret < 0)
2760 return ret;
2761 granularity = ret;
2762
2763 ret = tb_port_read(port, &val, TB_CFG_PORT,
2764 port->cap_adap + DP_STATUS, 1);
2765 if (ret)
2766 return ret;
2767
2768 val &= DP_STATUS_ALLOCATED_BW_MASK;
2769 val >>= DP_STATUS_ALLOCATED_BW_SHIFT;
2770
2771 return val * granularity;
2772}
2773
2774static int __usb4_dp_port_set_cm_ack(struct tb_port *port, bool ack)
2775{
2776 u32 val;
2777 int ret;
2778
2779 ret = tb_port_read(port, &val, TB_CFG_PORT,
2780 port->cap_adap + ADP_DP_CS_2, 1);
2781 if (ret)
2782 return ret;
2783
2784 if (ack)
2785 val |= ADP_DP_CS_2_CA;
2786 else
2787 val &= ~ADP_DP_CS_2_CA;
2788
2789 return tb_port_write(port, &val, TB_CFG_PORT,
2790 port->cap_adap + ADP_DP_CS_2, 1);
2791}
2792
2793static inline int usb4_dp_port_set_cm_ack(struct tb_port *port)
2794{
2795 return __usb4_dp_port_set_cm_ack(port, true);
2796}
2797
2798static int usb4_dp_port_wait_and_clear_cm_ack(struct tb_port *port,
2799 int timeout_msec)
2800{
2801 ktime_t end;
2802 u32 val;
2803 int ret;
2804
2805 ret = __usb4_dp_port_set_cm_ack(port, false);
2806 if (ret)
2807 return ret;
2808
2809 end = ktime_add_ms(ktime_get(), timeout_msec);
2810 do {
2811 ret = tb_port_read(port, &val, TB_CFG_PORT,
2812 port->cap_adap + ADP_DP_CS_8, 1);
2813 if (ret)
2814 return ret;
2815
2816 if (!(val & ADP_DP_CS_8_DR))
2817 break;
2818
2819 usleep_range(50, 100);
2820 } while (ktime_before(ktime_get(), end));
2821
2822 if (val & ADP_DP_CS_8_DR)
2823 return -ETIMEDOUT;
2824
2825 ret = tb_port_read(port, &val, TB_CFG_PORT,
2826 port->cap_adap + ADP_DP_CS_2, 1);
2827 if (ret)
2828 return ret;
2829
2830 val &= ~ADP_DP_CS_2_CA;
2831 return tb_port_write(port, &val, TB_CFG_PORT,
2832 port->cap_adap + ADP_DP_CS_2, 1);
2833}
2834
2835/**
2836 * usb4_dp_port_allocate_bandwidth() - Set allocated bandwidth
2837 * @port: DP IN adapter
2838 * @bw: New allocated bandwidth in Mb/s
2839 *
2840 * Communicates the new allocated bandwidth with the DPCD (graphics
2841 * driver). Takes into account the programmed granularity. Returns %0 in
2842 * success and negative errno in case of error.
2843 */
2844int usb4_dp_port_allocate_bandwidth(struct tb_port *port, int bw)
2845{
2846 u32 val, granularity;
2847 int ret;
2848
2849 if (!is_usb4_dpin(port))
2850 return -EOPNOTSUPP;
2851
2852 ret = usb4_dp_port_granularity(port);
2853 if (ret < 0)
2854 return ret;
2855 granularity = ret;
2856
2857 ret = tb_port_read(port, &val, TB_CFG_PORT,
2858 port->cap_adap + DP_STATUS, 1);
2859 if (ret)
2860 return ret;
2861
2862 val &= ~DP_STATUS_ALLOCATED_BW_MASK;
2863 val |= (bw / granularity) << DP_STATUS_ALLOCATED_BW_SHIFT;
2864
2865 ret = tb_port_write(port, &val, TB_CFG_PORT,
2866 port->cap_adap + DP_STATUS, 1);
2867 if (ret)
2868 return ret;
2869
2870 ret = usb4_dp_port_set_cm_ack(port);
2871 if (ret)
2872 return ret;
2873
2874 return usb4_dp_port_wait_and_clear_cm_ack(port, 500);
2875}
2876
2877/**
2878 * usb4_dp_port_requested_bandwidth() - Read requested bandwidth
2879 * @port: DP IN adapter
2880 *
2881 * Reads the DPCD (graphics driver) requested bandwidth and returns it
2882 * in Mb/s. Takes the programmed granularity into account. In case of
2883 * error returns negative errno. Specifically returns %-EOPNOTSUPP if
2884 * the adapter does not support bandwidth allocation mode, and %ENODATA
2885 * if there is no active bandwidth request from the graphics driver.
2886 */
2887int usb4_dp_port_requested_bandwidth(struct tb_port *port)
2888{
2889 u32 val, granularity;
2890 int ret;
2891
2892 if (!is_usb4_dpin(port))
2893 return -EOPNOTSUPP;
2894
2895 ret = usb4_dp_port_granularity(port);
2896 if (ret < 0)
2897 return ret;
2898 granularity = ret;
2899
2900 ret = tb_port_read(port, &val, TB_CFG_PORT,
2901 port->cap_adap + ADP_DP_CS_8, 1);
2902 if (ret)
2903 return ret;
2904
2905 if (!(val & ADP_DP_CS_8_DR))
2906 return -ENODATA;
2907
2908 return (val & ADP_DP_CS_8_REQUESTED_BW_MASK) * granularity;
2909}
2910
2911/**
2912 * usb4_pci_port_set_ext_encapsulation() - Enable/disable extended encapsulation
2913 * @port: PCIe adapter
2914 * @enable: Enable/disable extended encapsulation
2915 *
2916 * Enables or disables extended encapsulation used in PCIe tunneling. Caller
2917 * needs to make sure both adapters support this before enabling. Returns %0 on
2918 * success and negative errno otherwise.
2919 */
2920int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable)
2921{
2922 u32 val;
2923 int ret;
2924
2925 if (!tb_port_is_pcie_up(port) && !tb_port_is_pcie_down(port))
2926 return -EINVAL;
2927
2928 ret = tb_port_read(port, &val, TB_CFG_PORT,
2929 port->cap_adap + ADP_PCIE_CS_1, 1);
2930 if (ret)
2931 return ret;
2932
2933 if (enable)
2934 val |= ADP_PCIE_CS_1_EE;
2935 else
2936 val &= ~ADP_PCIE_CS_1_EE;
2937
2938 return tb_port_write(port, &val, TB_CFG_PORT,
2939 port->cap_adap + ADP_PCIE_CS_1, 1);
2940}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * USB4 specific functionality
4 *
5 * Copyright (C) 2019, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rajmohan Mani <rajmohan.mani@intel.com>
8 */
9
10#include <linux/delay.h>
11#include <linux/ktime.h>
12#include <linux/units.h>
13
14#include "sb_regs.h"
15#include "tb.h"
16
17#define USB4_DATA_RETRIES 3
18#define USB4_DATA_DWORDS 16
19
20enum usb4_sb_target {
21 USB4_SB_TARGET_ROUTER,
22 USB4_SB_TARGET_PARTNER,
23 USB4_SB_TARGET_RETIMER,
24};
25
26#define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
27#define USB4_NVM_READ_OFFSET_SHIFT 2
28#define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
29#define USB4_NVM_READ_LENGTH_SHIFT 24
30
31#define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
32#define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
33
34#define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
35#define USB4_DROM_ADDRESS_SHIFT 2
36#define USB4_DROM_SIZE_MASK GENMASK(19, 15)
37#define USB4_DROM_SIZE_SHIFT 15
38
39#define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
40
41#define USB4_BA_LENGTH_MASK GENMASK(7, 0)
42#define USB4_BA_INDEX_MASK GENMASK(15, 0)
43
44enum usb4_ba_index {
45 USB4_BA_MAX_USB3 = 0x1,
46 USB4_BA_MIN_DP_AUX = 0x2,
47 USB4_BA_MIN_DP_MAIN = 0x3,
48 USB4_BA_MAX_PCIE = 0x4,
49 USB4_BA_MAX_HI = 0x5,
50};
51
52#define USB4_BA_VALUE_MASK GENMASK(31, 16)
53#define USB4_BA_VALUE_SHIFT 16
54
55static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode,
56 u32 *metadata, u8 *status,
57 const void *tx_data, size_t tx_dwords,
58 void *rx_data, size_t rx_dwords)
59{
60 u32 val;
61 int ret;
62
63 if (metadata) {
64 ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
65 if (ret)
66 return ret;
67 }
68 if (tx_dwords) {
69 ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9,
70 tx_dwords);
71 if (ret)
72 return ret;
73 }
74
75 val = opcode | ROUTER_CS_26_OV;
76 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
77 if (ret)
78 return ret;
79
80 ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
81 if (ret)
82 return ret;
83
84 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
85 if (ret)
86 return ret;
87
88 if (val & ROUTER_CS_26_ONS)
89 return -EOPNOTSUPP;
90
91 if (status)
92 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
93 ROUTER_CS_26_STATUS_SHIFT;
94
95 if (metadata) {
96 ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
97 if (ret)
98 return ret;
99 }
100 if (rx_dwords) {
101 ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9,
102 rx_dwords);
103 if (ret)
104 return ret;
105 }
106
107 return 0;
108}
109
110static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata,
111 u8 *status, const void *tx_data, size_t tx_dwords,
112 void *rx_data, size_t rx_dwords)
113{
114 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
115
116 if (tx_dwords > USB4_DATA_DWORDS || rx_dwords > USB4_DATA_DWORDS)
117 return -EINVAL;
118
119 /*
120 * If the connection manager implementation provides USB4 router
121 * operation proxy callback, call it here instead of running the
122 * operation natively.
123 */
124 if (cm_ops->usb4_switch_op) {
125 int ret;
126
127 ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status,
128 tx_data, tx_dwords, rx_data,
129 rx_dwords);
130 if (ret != -EOPNOTSUPP)
131 return ret;
132
133 /*
134 * If the proxy was not supported then run the native
135 * router operation instead.
136 */
137 }
138
139 return usb4_native_switch_op(sw, opcode, metadata, status, tx_data,
140 tx_dwords, rx_data, rx_dwords);
141}
142
143static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode,
144 u32 *metadata, u8 *status)
145{
146 return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0);
147}
148
149static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode,
150 u32 *metadata, u8 *status,
151 const void *tx_data, size_t tx_dwords,
152 void *rx_data, size_t rx_dwords)
153{
154 return __usb4_switch_op(sw, opcode, metadata, status, tx_data,
155 tx_dwords, rx_data, rx_dwords);
156}
157
158/**
159 * usb4_switch_check_wakes() - Check for wakes and notify PM core about them
160 * @sw: Router whose wakes to check
161 *
162 * Checks wakes occurred during suspend and notify the PM core about them.
163 */
164void usb4_switch_check_wakes(struct tb_switch *sw)
165{
166 bool wakeup_usb4 = false;
167 struct usb4_port *usb4;
168 struct tb_port *port;
169 bool wakeup = false;
170 u32 val;
171
172 if (tb_route(sw)) {
173 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
174 return;
175
176 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
177 (val & ROUTER_CS_6_WOPS) ? "yes" : "no",
178 (val & ROUTER_CS_6_WOUS) ? "yes" : "no");
179
180 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
181 }
182
183 /*
184 * Check for any downstream ports for USB4 wake,
185 * connection wake and disconnection wake.
186 */
187 tb_switch_for_each_port(sw, port) {
188 if (!port->cap_usb4)
189 continue;
190
191 if (tb_port_read(port, &val, TB_CFG_PORT,
192 port->cap_usb4 + PORT_CS_18, 1))
193 break;
194
195 tb_port_dbg(port, "USB4 wake: %s, connection wake: %s, disconnection wake: %s\n",
196 (val & PORT_CS_18_WOU4S) ? "yes" : "no",
197 (val & PORT_CS_18_WOCS) ? "yes" : "no",
198 (val & PORT_CS_18_WODS) ? "yes" : "no");
199
200 wakeup_usb4 = val & (PORT_CS_18_WOU4S | PORT_CS_18_WOCS |
201 PORT_CS_18_WODS);
202
203 usb4 = port->usb4;
204 if (device_may_wakeup(&usb4->dev) && wakeup_usb4)
205 pm_wakeup_event(&usb4->dev, 0);
206
207 wakeup |= wakeup_usb4;
208 }
209
210 if (wakeup)
211 pm_wakeup_event(&sw->dev, 0);
212}
213
214static bool link_is_usb4(struct tb_port *port)
215{
216 u32 val;
217
218 if (!port->cap_usb4)
219 return false;
220
221 if (tb_port_read(port, &val, TB_CFG_PORT,
222 port->cap_usb4 + PORT_CS_18, 1))
223 return false;
224
225 return !(val & PORT_CS_18_TCM);
226}
227
228/**
229 * usb4_switch_setup() - Additional setup for USB4 device
230 * @sw: USB4 router to setup
231 *
232 * USB4 routers need additional settings in order to enable all the
233 * tunneling. This function enables USB and PCIe tunneling if it can be
234 * enabled (e.g the parent switch also supports them). If USB tunneling
235 * is not available for some reason (like that there is Thunderbolt 3
236 * switch upstream) then the internal xHCI controller is enabled
237 * instead.
238 *
239 * This does not set the configuration valid bit of the router. To do
240 * that call usb4_switch_configuration_valid().
241 */
242int usb4_switch_setup(struct tb_switch *sw)
243{
244 struct tb_switch *parent = tb_switch_parent(sw);
245 struct tb_port *down;
246 bool tbt3, xhci;
247 u32 val = 0;
248 int ret;
249
250 if (!tb_route(sw))
251 return 0;
252
253 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
254 if (ret)
255 return ret;
256
257 down = tb_switch_downstream_port(sw);
258 sw->link_usb4 = link_is_usb4(down);
259 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT");
260
261 xhci = val & ROUTER_CS_6_HCI;
262 tbt3 = !(val & ROUTER_CS_6_TNS);
263
264 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
265 tbt3 ? "yes" : "no", xhci ? "yes" : "no");
266
267 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
268 if (ret)
269 return ret;
270
271 if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 &&
272 tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
273 val |= ROUTER_CS_5_UTO;
274 xhci = false;
275 }
276
277 /*
278 * Only enable PCIe tunneling if the parent router supports it
279 * and it is not disabled.
280 */
281 if (tb_acpi_may_tunnel_pcie() &&
282 tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
283 val |= ROUTER_CS_5_PTO;
284 /*
285 * xHCI can be enabled if PCIe tunneling is supported
286 * and the parent does not have any USB3 dowstream
287 * adapters (so we cannot do USB 3.x tunneling).
288 */
289 if (xhci)
290 val |= ROUTER_CS_5_HCO;
291 }
292
293 /* TBT3 supported by the CM */
294 val &= ~ROUTER_CS_5_CNS;
295
296 return tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
297}
298
299/**
300 * usb4_switch_configuration_valid() - Set tunneling configuration to be valid
301 * @sw: USB4 router
302 *
303 * Sets configuration valid bit for the router. Must be called before
304 * any tunnels can be set through the router and after
305 * usb4_switch_setup() has been called. Can be called to host and device
306 * routers (does nothing for the latter).
307 *
308 * Returns %0 in success and negative errno otherwise.
309 */
310int usb4_switch_configuration_valid(struct tb_switch *sw)
311{
312 u32 val;
313 int ret;
314
315 if (!tb_route(sw))
316 return 0;
317
318 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
319 if (ret)
320 return ret;
321
322 val |= ROUTER_CS_5_CV;
323
324 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
325 if (ret)
326 return ret;
327
328 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
329 ROUTER_CS_6_CR, 50);
330}
331
332/**
333 * usb4_switch_read_uid() - Read UID from USB4 router
334 * @sw: USB4 router
335 * @uid: UID is stored here
336 *
337 * Reads 64-bit UID from USB4 router config space.
338 */
339int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
340{
341 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
342}
343
344static int usb4_switch_drom_read_block(void *data,
345 unsigned int dwaddress, void *buf,
346 size_t dwords)
347{
348 struct tb_switch *sw = data;
349 u8 status = 0;
350 u32 metadata;
351 int ret;
352
353 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
354 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
355 USB4_DROM_ADDRESS_MASK;
356
357 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata,
358 &status, NULL, 0, buf, dwords);
359 if (ret)
360 return ret;
361
362 return status ? -EIO : 0;
363}
364
365/**
366 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
367 * @sw: USB4 router
368 * @address: Byte address inside DROM to start reading
369 * @buf: Buffer where the DROM content is stored
370 * @size: Number of bytes to read from DROM
371 *
372 * Uses USB4 router operations to read router DROM. For devices this
373 * should always work but for hosts it may return %-EOPNOTSUPP in which
374 * case the host router does not have DROM.
375 */
376int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
377 size_t size)
378{
379 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
380 usb4_switch_drom_read_block, sw);
381}
382
383/**
384 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
385 * @sw: USB4 router
386 *
387 * Checks whether conditions are met so that lane bonding can be
388 * established with the upstream router. Call only for device routers.
389 */
390bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
391{
392 struct tb_port *up;
393 int ret;
394 u32 val;
395
396 up = tb_upstream_port(sw);
397 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
398 if (ret)
399 return false;
400
401 return !!(val & PORT_CS_18_BE);
402}
403
404/**
405 * usb4_switch_set_wake() - Enabled/disable wake
406 * @sw: USB4 router
407 * @flags: Wakeup flags (%0 to disable)
408 *
409 * Enables/disables router to wake up from sleep.
410 */
411int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags)
412{
413 struct usb4_port *usb4;
414 struct tb_port *port;
415 u64 route = tb_route(sw);
416 u32 val;
417 int ret;
418
419 /*
420 * Enable wakes coming from all USB4 downstream ports (from
421 * child routers). For device routers do this also for the
422 * upstream USB4 port.
423 */
424 tb_switch_for_each_port(sw, port) {
425 if (!tb_port_is_null(port))
426 continue;
427 if (!route && tb_is_upstream_port(port))
428 continue;
429 if (!port->cap_usb4)
430 continue;
431
432 ret = tb_port_read(port, &val, TB_CFG_PORT,
433 port->cap_usb4 + PORT_CS_19, 1);
434 if (ret)
435 return ret;
436
437 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
438
439 if (tb_is_upstream_port(port)) {
440 val |= PORT_CS_19_WOU4;
441 } else {
442 bool configured = val & PORT_CS_19_PC;
443 usb4 = port->usb4;
444
445 if (((flags & TB_WAKE_ON_CONNECT) |
446 device_may_wakeup(&usb4->dev)) && !configured)
447 val |= PORT_CS_19_WOC;
448 if (((flags & TB_WAKE_ON_DISCONNECT) |
449 device_may_wakeup(&usb4->dev)) && configured)
450 val |= PORT_CS_19_WOD;
451 if ((flags & TB_WAKE_ON_USB4) && configured)
452 val |= PORT_CS_19_WOU4;
453 }
454
455 ret = tb_port_write(port, &val, TB_CFG_PORT,
456 port->cap_usb4 + PORT_CS_19, 1);
457 if (ret)
458 return ret;
459 }
460
461 /*
462 * Enable wakes from PCIe, USB 3.x and DP on this router. Only
463 * needed for device routers.
464 */
465 if (route) {
466 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
467 if (ret)
468 return ret;
469
470 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD);
471 if (flags & TB_WAKE_ON_USB3)
472 val |= ROUTER_CS_5_WOU;
473 if (flags & TB_WAKE_ON_PCIE)
474 val |= ROUTER_CS_5_WOP;
475 if (flags & TB_WAKE_ON_DP)
476 val |= ROUTER_CS_5_WOD;
477
478 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
479 if (ret)
480 return ret;
481 }
482
483 return 0;
484}
485
486/**
487 * usb4_switch_set_sleep() - Prepare the router to enter sleep
488 * @sw: USB4 router
489 *
490 * Sets sleep bit for the router. Returns when the router sleep ready
491 * bit has been asserted.
492 */
493int usb4_switch_set_sleep(struct tb_switch *sw)
494{
495 int ret;
496 u32 val;
497
498 /* Set sleep bit and wait for sleep ready to be asserted */
499 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
500 if (ret)
501 return ret;
502
503 val |= ROUTER_CS_5_SLP;
504
505 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
506 if (ret)
507 return ret;
508
509 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
510 ROUTER_CS_6_SLPR, 500);
511}
512
513/**
514 * usb4_switch_nvm_sector_size() - Return router NVM sector size
515 * @sw: USB4 router
516 *
517 * If the router supports NVM operations this function returns the NVM
518 * sector size in bytes. If NVM operations are not supported returns
519 * %-EOPNOTSUPP.
520 */
521int usb4_switch_nvm_sector_size(struct tb_switch *sw)
522{
523 u32 metadata;
524 u8 status;
525 int ret;
526
527 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata,
528 &status);
529 if (ret)
530 return ret;
531
532 if (status)
533 return status == 0x2 ? -EOPNOTSUPP : -EIO;
534
535 return metadata & USB4_NVM_SECTOR_SIZE_MASK;
536}
537
538static int usb4_switch_nvm_read_block(void *data,
539 unsigned int dwaddress, void *buf, size_t dwords)
540{
541 struct tb_switch *sw = data;
542 u8 status = 0;
543 u32 metadata;
544 int ret;
545
546 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
547 USB4_NVM_READ_LENGTH_MASK;
548 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
549 USB4_NVM_READ_OFFSET_MASK;
550
551 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata,
552 &status, NULL, 0, buf, dwords);
553 if (ret)
554 return ret;
555
556 return status ? -EIO : 0;
557}
558
559/**
560 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
561 * @sw: USB4 router
562 * @address: Starting address in bytes
563 * @buf: Read data is placed here
564 * @size: How many bytes to read
565 *
566 * Reads NVM contents of the router. If NVM is not supported returns
567 * %-EOPNOTSUPP.
568 */
569int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
570 size_t size)
571{
572 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
573 usb4_switch_nvm_read_block, sw);
574}
575
576/**
577 * usb4_switch_nvm_set_offset() - Set NVM write offset
578 * @sw: USB4 router
579 * @address: Start offset
580 *
581 * Explicitly sets NVM write offset. Normally when writing to NVM this
582 * is done automatically by usb4_switch_nvm_write().
583 *
584 * Returns %0 in success and negative errno if there was a failure.
585 */
586int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address)
587{
588 u32 metadata, dwaddress;
589 u8 status = 0;
590 int ret;
591
592 dwaddress = address / 4;
593 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
594 USB4_NVM_SET_OFFSET_MASK;
595
596 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata,
597 &status);
598 if (ret)
599 return ret;
600
601 return status ? -EIO : 0;
602}
603
604static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress,
605 const void *buf, size_t dwords)
606{
607 struct tb_switch *sw = data;
608 u8 status;
609 int ret;
610
611 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status,
612 buf, dwords, NULL, 0);
613 if (ret)
614 return ret;
615
616 return status ? -EIO : 0;
617}
618
619/**
620 * usb4_switch_nvm_write() - Write to the router NVM
621 * @sw: USB4 router
622 * @address: Start address where to write in bytes
623 * @buf: Pointer to the data to write
624 * @size: Size of @buf in bytes
625 *
626 * Writes @buf to the router NVM using USB4 router operations. If NVM
627 * write is not supported returns %-EOPNOTSUPP.
628 */
629int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
630 const void *buf, size_t size)
631{
632 int ret;
633
634 ret = usb4_switch_nvm_set_offset(sw, address);
635 if (ret)
636 return ret;
637
638 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
639 usb4_switch_nvm_write_next_block, sw);
640}
641
642/**
643 * usb4_switch_nvm_authenticate() - Authenticate new NVM
644 * @sw: USB4 router
645 *
646 * After the new NVM has been written via usb4_switch_nvm_write(), this
647 * function triggers NVM authentication process. The router gets power
648 * cycled and if the authentication is successful the new NVM starts
649 * running. In case of failure returns negative errno.
650 *
651 * The caller should call usb4_switch_nvm_authenticate_status() to read
652 * the status of the authentication after power cycle. It should be the
653 * first router operation to avoid the status being lost.
654 */
655int usb4_switch_nvm_authenticate(struct tb_switch *sw)
656{
657 int ret;
658
659 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL);
660 switch (ret) {
661 /*
662 * The router is power cycled once NVM_AUTH is started so it is
663 * expected to get any of the following errors back.
664 */
665 case -EACCES:
666 case -ENOTCONN:
667 case -ETIMEDOUT:
668 return 0;
669
670 default:
671 return ret;
672 }
673}
674
675/**
676 * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate
677 * @sw: USB4 router
678 * @status: Status code of the operation
679 *
680 * The function checks if there is status available from the last NVM
681 * authenticate router operation. If there is status then %0 is returned
682 * and the status code is placed in @status. Returns negative errno in case
683 * of failure.
684 *
685 * Must be called before any other router operation.
686 */
687int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status)
688{
689 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
690 u16 opcode;
691 u32 val;
692 int ret;
693
694 if (cm_ops->usb4_switch_nvm_authenticate_status) {
695 ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status);
696 if (ret != -EOPNOTSUPP)
697 return ret;
698 }
699
700 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
701 if (ret)
702 return ret;
703
704 /* Check that the opcode is correct */
705 opcode = val & ROUTER_CS_26_OPCODE_MASK;
706 if (opcode == USB4_SWITCH_OP_NVM_AUTH) {
707 if (val & ROUTER_CS_26_OV)
708 return -EBUSY;
709 if (val & ROUTER_CS_26_ONS)
710 return -EOPNOTSUPP;
711
712 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
713 ROUTER_CS_26_STATUS_SHIFT;
714 } else {
715 *status = 0;
716 }
717
718 return 0;
719}
720
721/**
722 * usb4_switch_credits_init() - Read buffer allocation parameters
723 * @sw: USB4 router
724 *
725 * Reads @sw buffer allocation parameters and initializes @sw buffer
726 * allocation fields accordingly. Specifically @sw->credits_allocation
727 * is set to %true if these parameters can be used in tunneling.
728 *
729 * Returns %0 on success and negative errno otherwise.
730 */
731int usb4_switch_credits_init(struct tb_switch *sw)
732{
733 int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma;
734 int ret, length, i, nports;
735 const struct tb_port *port;
736 u32 data[USB4_DATA_DWORDS];
737 u32 metadata = 0;
738 u8 status = 0;
739
740 memset(data, 0, sizeof(data));
741 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_BUFFER_ALLOC, &metadata,
742 &status, NULL, 0, data, ARRAY_SIZE(data));
743 if (ret)
744 return ret;
745 if (status)
746 return -EIO;
747
748 length = metadata & USB4_BA_LENGTH_MASK;
749 if (WARN_ON(length > ARRAY_SIZE(data)))
750 return -EMSGSIZE;
751
752 max_usb3 = -1;
753 min_dp_aux = -1;
754 min_dp_main = -1;
755 max_pcie = -1;
756 max_dma = -1;
757
758 tb_sw_dbg(sw, "credit allocation parameters:\n");
759
760 for (i = 0; i < length; i++) {
761 u16 index, value;
762
763 index = data[i] & USB4_BA_INDEX_MASK;
764 value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT;
765
766 switch (index) {
767 case USB4_BA_MAX_USB3:
768 tb_sw_dbg(sw, " USB3: %u\n", value);
769 max_usb3 = value;
770 break;
771 case USB4_BA_MIN_DP_AUX:
772 tb_sw_dbg(sw, " DP AUX: %u\n", value);
773 min_dp_aux = value;
774 break;
775 case USB4_BA_MIN_DP_MAIN:
776 tb_sw_dbg(sw, " DP main: %u\n", value);
777 min_dp_main = value;
778 break;
779 case USB4_BA_MAX_PCIE:
780 tb_sw_dbg(sw, " PCIe: %u\n", value);
781 max_pcie = value;
782 break;
783 case USB4_BA_MAX_HI:
784 tb_sw_dbg(sw, " DMA: %u\n", value);
785 max_dma = value;
786 break;
787 default:
788 tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n",
789 index);
790 break;
791 }
792 }
793
794 /*
795 * Validate the buffer allocation preferences. If we find
796 * issues, log a warning and fall back using the hard-coded
797 * values.
798 */
799
800 /* Host router must report baMaxHI */
801 if (!tb_route(sw) && max_dma < 0) {
802 tb_sw_warn(sw, "host router is missing baMaxHI\n");
803 goto err_invalid;
804 }
805
806 nports = 0;
807 tb_switch_for_each_port(sw, port) {
808 if (tb_port_is_null(port))
809 nports++;
810 }
811
812 /* Must have DP buffer allocation (multiple USB4 ports) */
813 if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) {
814 tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n");
815 goto err_invalid;
816 }
817
818 tb_switch_for_each_port(sw, port) {
819 if (tb_port_is_dpout(port) && min_dp_main < 0) {
820 tb_sw_warn(sw, "missing baMinDPmain");
821 goto err_invalid;
822 }
823 if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) &&
824 min_dp_aux < 0) {
825 tb_sw_warn(sw, "missing baMinDPaux");
826 goto err_invalid;
827 }
828 if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) &&
829 max_usb3 < 0) {
830 tb_sw_warn(sw, "missing baMaxUSB3");
831 goto err_invalid;
832 }
833 if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) &&
834 max_pcie < 0) {
835 tb_sw_warn(sw, "missing baMaxPCIe");
836 goto err_invalid;
837 }
838 }
839
840 /*
841 * Buffer allocation passed the validation so we can use it in
842 * path creation.
843 */
844 sw->credit_allocation = true;
845 if (max_usb3 > 0)
846 sw->max_usb3_credits = max_usb3;
847 if (min_dp_aux > 0)
848 sw->min_dp_aux_credits = min_dp_aux;
849 if (min_dp_main > 0)
850 sw->min_dp_main_credits = min_dp_main;
851 if (max_pcie > 0)
852 sw->max_pcie_credits = max_pcie;
853 if (max_dma > 0)
854 sw->max_dma_credits = max_dma;
855
856 return 0;
857
858err_invalid:
859 return -EINVAL;
860}
861
862/**
863 * usb4_switch_query_dp_resource() - Query availability of DP IN resource
864 * @sw: USB4 router
865 * @in: DP IN adapter
866 *
867 * For DP tunneling this function can be used to query availability of
868 * DP IN resource. Returns true if the resource is available for DP
869 * tunneling, false otherwise.
870 */
871bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
872{
873 u32 metadata = in->port;
874 u8 status;
875 int ret;
876
877 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata,
878 &status);
879 /*
880 * If DP resource allocation is not supported assume it is
881 * always available.
882 */
883 if (ret == -EOPNOTSUPP)
884 return true;
885 if (ret)
886 return false;
887
888 return !status;
889}
890
891/**
892 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
893 * @sw: USB4 router
894 * @in: DP IN adapter
895 *
896 * Allocates DP IN resource for DP tunneling using USB4 router
897 * operations. If the resource was allocated returns %0. Otherwise
898 * returns negative errno, in particular %-EBUSY if the resource is
899 * already allocated.
900 */
901int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
902{
903 u32 metadata = in->port;
904 u8 status;
905 int ret;
906
907 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata,
908 &status);
909 if (ret == -EOPNOTSUPP)
910 return 0;
911 if (ret)
912 return ret;
913
914 return status ? -EBUSY : 0;
915}
916
917/**
918 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
919 * @sw: USB4 router
920 * @in: DP IN adapter
921 *
922 * Releases the previously allocated DP IN resource.
923 */
924int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
925{
926 u32 metadata = in->port;
927 u8 status;
928 int ret;
929
930 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata,
931 &status);
932 if (ret == -EOPNOTSUPP)
933 return 0;
934 if (ret)
935 return ret;
936
937 return status ? -EIO : 0;
938}
939
940static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
941{
942 struct tb_port *p;
943 int usb4_idx = 0;
944
945 /* Assume port is primary */
946 tb_switch_for_each_port(sw, p) {
947 if (!tb_port_is_null(p))
948 continue;
949 if (tb_is_upstream_port(p))
950 continue;
951 if (!p->link_nr) {
952 if (p == port)
953 break;
954 usb4_idx++;
955 }
956 }
957
958 return usb4_idx;
959}
960
961/**
962 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
963 * @sw: USB4 router
964 * @port: USB4 port
965 *
966 * USB4 routers have direct mapping between USB4 ports and PCIe
967 * downstream adapters where the PCIe topology is extended. This
968 * function returns the corresponding downstream PCIe adapter or %NULL
969 * if no such mapping was possible.
970 */
971struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
972 const struct tb_port *port)
973{
974 int usb4_idx = usb4_port_idx(sw, port);
975 struct tb_port *p;
976 int pcie_idx = 0;
977
978 /* Find PCIe down port matching usb4_port */
979 tb_switch_for_each_port(sw, p) {
980 if (!tb_port_is_pcie_down(p))
981 continue;
982
983 if (pcie_idx == usb4_idx)
984 return p;
985
986 pcie_idx++;
987 }
988
989 return NULL;
990}
991
992/**
993 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
994 * @sw: USB4 router
995 * @port: USB4 port
996 *
997 * USB4 routers have direct mapping between USB4 ports and USB 3.x
998 * downstream adapters where the USB 3.x topology is extended. This
999 * function returns the corresponding downstream USB 3.x adapter or
1000 * %NULL if no such mapping was possible.
1001 */
1002struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
1003 const struct tb_port *port)
1004{
1005 int usb4_idx = usb4_port_idx(sw, port);
1006 struct tb_port *p;
1007 int usb_idx = 0;
1008
1009 /* Find USB3 down port matching usb4_port */
1010 tb_switch_for_each_port(sw, p) {
1011 if (!tb_port_is_usb3_down(p))
1012 continue;
1013
1014 if (usb_idx == usb4_idx)
1015 return p;
1016
1017 usb_idx++;
1018 }
1019
1020 return NULL;
1021}
1022
1023/**
1024 * usb4_switch_add_ports() - Add USB4 ports for this router
1025 * @sw: USB4 router
1026 *
1027 * For USB4 router finds all USB4 ports and registers devices for each.
1028 * Can be called to any router.
1029 *
1030 * Return %0 in case of success and negative errno in case of failure.
1031 */
1032int usb4_switch_add_ports(struct tb_switch *sw)
1033{
1034 struct tb_port *port;
1035
1036 if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw))
1037 return 0;
1038
1039 tb_switch_for_each_port(sw, port) {
1040 struct usb4_port *usb4;
1041
1042 if (!tb_port_is_null(port))
1043 continue;
1044 if (!port->cap_usb4)
1045 continue;
1046
1047 usb4 = usb4_port_device_add(port);
1048 if (IS_ERR(usb4)) {
1049 usb4_switch_remove_ports(sw);
1050 return PTR_ERR(usb4);
1051 }
1052
1053 port->usb4 = usb4;
1054 }
1055
1056 return 0;
1057}
1058
1059/**
1060 * usb4_switch_remove_ports() - Removes USB4 ports from this router
1061 * @sw: USB4 router
1062 *
1063 * Unregisters previously registered USB4 ports.
1064 */
1065void usb4_switch_remove_ports(struct tb_switch *sw)
1066{
1067 struct tb_port *port;
1068
1069 tb_switch_for_each_port(sw, port) {
1070 if (port->usb4) {
1071 usb4_port_device_remove(port->usb4);
1072 port->usb4 = NULL;
1073 }
1074 }
1075}
1076
1077/**
1078 * usb4_port_unlock() - Unlock USB4 downstream port
1079 * @port: USB4 port to unlock
1080 *
1081 * Unlocks USB4 downstream port so that the connection manager can
1082 * access the router below this port.
1083 */
1084int usb4_port_unlock(struct tb_port *port)
1085{
1086 int ret;
1087 u32 val;
1088
1089 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1090 if (ret)
1091 return ret;
1092
1093 val &= ~ADP_CS_4_LCK;
1094 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1095}
1096
1097/**
1098 * usb4_port_hotplug_enable() - Enables hotplug for a port
1099 * @port: USB4 port to operate on
1100 *
1101 * Enables hot plug events on a given port. This is only intended
1102 * to be used on lane, DP-IN, and DP-OUT adapters.
1103 */
1104int usb4_port_hotplug_enable(struct tb_port *port)
1105{
1106 int ret;
1107 u32 val;
1108
1109 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1110 if (ret)
1111 return ret;
1112
1113 val &= ~ADP_CS_5_DHP;
1114 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1115}
1116
1117/**
1118 * usb4_port_reset() - Issue downstream port reset
1119 * @port: USB4 port to reset
1120 *
1121 * Issues downstream port reset to @port.
1122 */
1123int usb4_port_reset(struct tb_port *port)
1124{
1125 int ret;
1126 u32 val;
1127
1128 if (!port->cap_usb4)
1129 return -EINVAL;
1130
1131 ret = tb_port_read(port, &val, TB_CFG_PORT,
1132 port->cap_usb4 + PORT_CS_19, 1);
1133 if (ret)
1134 return ret;
1135
1136 val |= PORT_CS_19_DPR;
1137
1138 ret = tb_port_write(port, &val, TB_CFG_PORT,
1139 port->cap_usb4 + PORT_CS_19, 1);
1140 if (ret)
1141 return ret;
1142
1143 fsleep(10000);
1144
1145 ret = tb_port_read(port, &val, TB_CFG_PORT,
1146 port->cap_usb4 + PORT_CS_19, 1);
1147 if (ret)
1148 return ret;
1149
1150 val &= ~PORT_CS_19_DPR;
1151
1152 return tb_port_write(port, &val, TB_CFG_PORT,
1153 port->cap_usb4 + PORT_CS_19, 1);
1154}
1155
1156static int usb4_port_set_configured(struct tb_port *port, bool configured)
1157{
1158 int ret;
1159 u32 val;
1160
1161 if (!port->cap_usb4)
1162 return -EINVAL;
1163
1164 ret = tb_port_read(port, &val, TB_CFG_PORT,
1165 port->cap_usb4 + PORT_CS_19, 1);
1166 if (ret)
1167 return ret;
1168
1169 if (configured)
1170 val |= PORT_CS_19_PC;
1171 else
1172 val &= ~PORT_CS_19_PC;
1173
1174 return tb_port_write(port, &val, TB_CFG_PORT,
1175 port->cap_usb4 + PORT_CS_19, 1);
1176}
1177
1178/**
1179 * usb4_port_configure() - Set USB4 port configured
1180 * @port: USB4 router
1181 *
1182 * Sets the USB4 link to be configured for power management purposes.
1183 */
1184int usb4_port_configure(struct tb_port *port)
1185{
1186 return usb4_port_set_configured(port, true);
1187}
1188
1189/**
1190 * usb4_port_unconfigure() - Set USB4 port unconfigured
1191 * @port: USB4 router
1192 *
1193 * Sets the USB4 link to be unconfigured for power management purposes.
1194 */
1195void usb4_port_unconfigure(struct tb_port *port)
1196{
1197 usb4_port_set_configured(port, false);
1198}
1199
1200static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
1201{
1202 int ret;
1203 u32 val;
1204
1205 if (!port->cap_usb4)
1206 return -EINVAL;
1207
1208 ret = tb_port_read(port, &val, TB_CFG_PORT,
1209 port->cap_usb4 + PORT_CS_19, 1);
1210 if (ret)
1211 return ret;
1212
1213 if (configured)
1214 val |= PORT_CS_19_PID;
1215 else
1216 val &= ~PORT_CS_19_PID;
1217
1218 return tb_port_write(port, &val, TB_CFG_PORT,
1219 port->cap_usb4 + PORT_CS_19, 1);
1220}
1221
1222/**
1223 * usb4_port_configure_xdomain() - Configure port for XDomain
1224 * @port: USB4 port connected to another host
1225 * @xd: XDomain that is connected to the port
1226 *
1227 * Marks the USB4 port as being connected to another host and updates
1228 * the link type. Returns %0 in success and negative errno in failure.
1229 */
1230int usb4_port_configure_xdomain(struct tb_port *port, struct tb_xdomain *xd)
1231{
1232 xd->link_usb4 = link_is_usb4(port);
1233 return usb4_set_xdomain_configured(port, true);
1234}
1235
1236/**
1237 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
1238 * @port: USB4 port that was connected to another host
1239 *
1240 * Clears USB4 port from being marked as XDomain.
1241 */
1242void usb4_port_unconfigure_xdomain(struct tb_port *port)
1243{
1244 usb4_set_xdomain_configured(port, false);
1245}
1246
1247static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
1248 u32 value, int timeout_msec)
1249{
1250 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
1251
1252 do {
1253 u32 val;
1254 int ret;
1255
1256 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1);
1257 if (ret)
1258 return ret;
1259
1260 if ((val & bit) == value)
1261 return 0;
1262
1263 usleep_range(50, 100);
1264 } while (ktime_before(ktime_get(), timeout));
1265
1266 return -ETIMEDOUT;
1267}
1268
1269static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
1270{
1271 if (dwords > USB4_DATA_DWORDS)
1272 return -EINVAL;
1273
1274 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1275 dwords);
1276}
1277
1278static int usb4_port_write_data(struct tb_port *port, const void *data,
1279 size_t dwords)
1280{
1281 if (dwords > USB4_DATA_DWORDS)
1282 return -EINVAL;
1283
1284 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1285 dwords);
1286}
1287
1288static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target,
1289 u8 index, u8 reg, void *buf, u8 size)
1290{
1291 size_t dwords = DIV_ROUND_UP(size, 4);
1292 int ret;
1293 u32 val;
1294
1295 if (!port->cap_usb4)
1296 return -EINVAL;
1297
1298 val = reg;
1299 val |= size << PORT_CS_1_LENGTH_SHIFT;
1300 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1301 if (target == USB4_SB_TARGET_RETIMER)
1302 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1303 val |= PORT_CS_1_PND;
1304
1305 ret = tb_port_write(port, &val, TB_CFG_PORT,
1306 port->cap_usb4 + PORT_CS_1, 1);
1307 if (ret)
1308 return ret;
1309
1310 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1311 PORT_CS_1_PND, 0, 500);
1312 if (ret)
1313 return ret;
1314
1315 ret = tb_port_read(port, &val, TB_CFG_PORT,
1316 port->cap_usb4 + PORT_CS_1, 1);
1317 if (ret)
1318 return ret;
1319
1320 if (val & PORT_CS_1_NR)
1321 return -ENODEV;
1322 if (val & PORT_CS_1_RC)
1323 return -EIO;
1324
1325 return buf ? usb4_port_read_data(port, buf, dwords) : 0;
1326}
1327
1328static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1329 u8 index, u8 reg, const void *buf, u8 size)
1330{
1331 size_t dwords = DIV_ROUND_UP(size, 4);
1332 int ret;
1333 u32 val;
1334
1335 if (!port->cap_usb4)
1336 return -EINVAL;
1337
1338 if (buf) {
1339 ret = usb4_port_write_data(port, buf, dwords);
1340 if (ret)
1341 return ret;
1342 }
1343
1344 val = reg;
1345 val |= size << PORT_CS_1_LENGTH_SHIFT;
1346 val |= PORT_CS_1_WNR_WRITE;
1347 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1348 if (target == USB4_SB_TARGET_RETIMER)
1349 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1350 val |= PORT_CS_1_PND;
1351
1352 ret = tb_port_write(port, &val, TB_CFG_PORT,
1353 port->cap_usb4 + PORT_CS_1, 1);
1354 if (ret)
1355 return ret;
1356
1357 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1358 PORT_CS_1_PND, 0, 500);
1359 if (ret)
1360 return ret;
1361
1362 ret = tb_port_read(port, &val, TB_CFG_PORT,
1363 port->cap_usb4 + PORT_CS_1, 1);
1364 if (ret)
1365 return ret;
1366
1367 if (val & PORT_CS_1_NR)
1368 return -ENODEV;
1369 if (val & PORT_CS_1_RC)
1370 return -EIO;
1371
1372 return 0;
1373}
1374
1375static int usb4_port_sb_opcode_err_to_errno(u32 val)
1376{
1377 switch (val) {
1378 case 0:
1379 return 0;
1380 case USB4_SB_OPCODE_ERR:
1381 return -EAGAIN;
1382 case USB4_SB_OPCODE_ONS:
1383 return -EOPNOTSUPP;
1384 default:
1385 return -EIO;
1386 }
1387}
1388
1389static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1390 u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1391{
1392 ktime_t timeout;
1393 u32 val;
1394 int ret;
1395
1396 val = opcode;
1397 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val,
1398 sizeof(val));
1399 if (ret)
1400 return ret;
1401
1402 timeout = ktime_add_ms(ktime_get(), timeout_msec);
1403
1404 do {
1405 /* Check results */
1406 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1407 &val, sizeof(val));
1408 if (ret)
1409 return ret;
1410
1411 if (val != opcode)
1412 return usb4_port_sb_opcode_err_to_errno(val);
1413 } while (ktime_before(ktime_get(), timeout));
1414
1415 return -ETIMEDOUT;
1416}
1417
1418static int usb4_port_set_router_offline(struct tb_port *port, bool offline)
1419{
1420 u32 val = !offline;
1421 int ret;
1422
1423 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1424 USB4_SB_METADATA, &val, sizeof(val));
1425 if (ret)
1426 return ret;
1427
1428 val = USB4_SB_OPCODE_ROUTER_OFFLINE;
1429 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1430 USB4_SB_OPCODE, &val, sizeof(val));
1431}
1432
1433/**
1434 * usb4_port_router_offline() - Put the USB4 port to offline mode
1435 * @port: USB4 port
1436 *
1437 * This function puts the USB4 port into offline mode. In this mode the
1438 * port does not react on hotplug events anymore. This needs to be
1439 * called before retimer access is done when the USB4 links is not up.
1440 *
1441 * Returns %0 in case of success and negative errno if there was an
1442 * error.
1443 */
1444int usb4_port_router_offline(struct tb_port *port)
1445{
1446 return usb4_port_set_router_offline(port, true);
1447}
1448
1449/**
1450 * usb4_port_router_online() - Put the USB4 port back to online
1451 * @port: USB4 port
1452 *
1453 * Makes the USB4 port functional again.
1454 */
1455int usb4_port_router_online(struct tb_port *port)
1456{
1457 return usb4_port_set_router_offline(port, false);
1458}
1459
1460/**
1461 * usb4_port_enumerate_retimers() - Send RT broadcast transaction
1462 * @port: USB4 port
1463 *
1464 * This forces the USB4 port to send broadcast RT transaction which
1465 * makes the retimers on the link to assign index to themselves. Returns
1466 * %0 in case of success and negative errno if there was an error.
1467 */
1468int usb4_port_enumerate_retimers(struct tb_port *port)
1469{
1470 u32 val;
1471
1472 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1473 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1474 USB4_SB_OPCODE, &val, sizeof(val));
1475}
1476
1477/**
1478 * usb4_port_clx_supported() - Check if CLx is supported by the link
1479 * @port: Port to check for CLx support for
1480 *
1481 * PORT_CS_18_CPS bit reflects if the link supports CLx including
1482 * active cables (if connected on the link).
1483 */
1484bool usb4_port_clx_supported(struct tb_port *port)
1485{
1486 int ret;
1487 u32 val;
1488
1489 ret = tb_port_read(port, &val, TB_CFG_PORT,
1490 port->cap_usb4 + PORT_CS_18, 1);
1491 if (ret)
1492 return false;
1493
1494 return !!(val & PORT_CS_18_CPS);
1495}
1496
1497/**
1498 * usb4_port_asym_supported() - If the port supports asymmetric link
1499 * @port: USB4 port
1500 *
1501 * Checks if the port and the cable supports asymmetric link and returns
1502 * %true in that case.
1503 */
1504bool usb4_port_asym_supported(struct tb_port *port)
1505{
1506 u32 val;
1507
1508 if (!port->cap_usb4)
1509 return false;
1510
1511 if (tb_port_read(port, &val, TB_CFG_PORT, port->cap_usb4 + PORT_CS_18, 1))
1512 return false;
1513
1514 return !!(val & PORT_CS_18_CSA);
1515}
1516
1517/**
1518 * usb4_port_asym_set_link_width() - Set link width to asymmetric or symmetric
1519 * @port: USB4 port
1520 * @width: Asymmetric width to configure
1521 *
1522 * Sets USB4 port link width to @width. Can be called for widths where
1523 * usb4_port_asym_width_supported() returned @true.
1524 */
1525int usb4_port_asym_set_link_width(struct tb_port *port, enum tb_link_width width)
1526{
1527 u32 val;
1528 int ret;
1529
1530 if (!port->cap_phy)
1531 return -EINVAL;
1532
1533 ret = tb_port_read(port, &val, TB_CFG_PORT,
1534 port->cap_phy + LANE_ADP_CS_1, 1);
1535 if (ret)
1536 return ret;
1537
1538 val &= ~LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK;
1539 switch (width) {
1540 case TB_LINK_WIDTH_DUAL:
1541 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1542 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL);
1543 break;
1544 case TB_LINK_WIDTH_ASYM_TX:
1545 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1546 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX);
1547 break;
1548 case TB_LINK_WIDTH_ASYM_RX:
1549 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1550 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX);
1551 break;
1552 default:
1553 return -EINVAL;
1554 }
1555
1556 return tb_port_write(port, &val, TB_CFG_PORT,
1557 port->cap_phy + LANE_ADP_CS_1, 1);
1558}
1559
1560/**
1561 * usb4_port_asym_start() - Start symmetry change and wait for completion
1562 * @port: USB4 port
1563 *
1564 * Start symmetry change of the link to asymmetric or symmetric
1565 * (according to what was previously set in tb_port_set_link_width().
1566 * Wait for completion of the change.
1567 *
1568 * Returns %0 in case of success, %-ETIMEDOUT if case of timeout or
1569 * a negative errno in case of a failure.
1570 */
1571int usb4_port_asym_start(struct tb_port *port)
1572{
1573 int ret;
1574 u32 val;
1575
1576 ret = tb_port_read(port, &val, TB_CFG_PORT,
1577 port->cap_usb4 + PORT_CS_19, 1);
1578 if (ret)
1579 return ret;
1580
1581 val &= ~PORT_CS_19_START_ASYM;
1582 val |= FIELD_PREP(PORT_CS_19_START_ASYM, 1);
1583
1584 ret = tb_port_write(port, &val, TB_CFG_PORT,
1585 port->cap_usb4 + PORT_CS_19, 1);
1586 if (ret)
1587 return ret;
1588
1589 /*
1590 * Wait for PORT_CS_19_START_ASYM to be 0. This means the USB4
1591 * port started the symmetry transition.
1592 */
1593 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_19,
1594 PORT_CS_19_START_ASYM, 0, 1000);
1595 if (ret)
1596 return ret;
1597
1598 /* Then wait for the transtion to be completed */
1599 return usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_18,
1600 PORT_CS_18_TIP, 0, 5000);
1601}
1602
1603/**
1604 * usb4_port_margining_caps() - Read USB4 port marginig capabilities
1605 * @port: USB4 port
1606 * @caps: Array with at least two elements to hold the results
1607 *
1608 * Reads the USB4 port lane margining capabilities into @caps.
1609 */
1610int usb4_port_margining_caps(struct tb_port *port, u32 *caps)
1611{
1612 int ret;
1613
1614 ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1615 USB4_SB_OPCODE_READ_LANE_MARGINING_CAP, 500);
1616 if (ret)
1617 return ret;
1618
1619 return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1620 USB4_SB_DATA, caps, sizeof(*caps) * 2);
1621}
1622
1623/**
1624 * usb4_port_hw_margin() - Run hardware lane margining on port
1625 * @port: USB4 port
1626 * @lanes: Which lanes to run (must match the port capabilities). Can be
1627 * %0, %1 or %7.
1628 * @ber_level: BER level contour value
1629 * @timing: Perform timing margining instead of voltage
1630 * @right_high: Use Right/high margin instead of left/low
1631 * @results: Array with at least two elements to hold the results
1632 *
1633 * Runs hardware lane margining on USB4 port and returns the result in
1634 * @results.
1635 */
1636int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes,
1637 unsigned int ber_level, bool timing, bool right_high,
1638 u32 *results)
1639{
1640 u32 val;
1641 int ret;
1642
1643 val = lanes;
1644 if (timing)
1645 val |= USB4_MARGIN_HW_TIME;
1646 if (right_high)
1647 val |= USB4_MARGIN_HW_RH;
1648 if (ber_level)
1649 val |= (ber_level << USB4_MARGIN_HW_BER_SHIFT) &
1650 USB4_MARGIN_HW_BER_MASK;
1651
1652 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1653 USB4_SB_METADATA, &val, sizeof(val));
1654 if (ret)
1655 return ret;
1656
1657 ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1658 USB4_SB_OPCODE_RUN_HW_LANE_MARGINING, 2500);
1659 if (ret)
1660 return ret;
1661
1662 return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1663 USB4_SB_DATA, results, sizeof(*results) * 2);
1664}
1665
1666/**
1667 * usb4_port_sw_margin() - Run software lane margining on port
1668 * @port: USB4 port
1669 * @lanes: Which lanes to run (must match the port capabilities). Can be
1670 * %0, %1 or %7.
1671 * @timing: Perform timing margining instead of voltage
1672 * @right_high: Use Right/high margin instead of left/low
1673 * @counter: What to do with the error counter
1674 *
1675 * Runs software lane margining on USB4 port. Read back the error
1676 * counters by calling usb4_port_sw_margin_errors(). Returns %0 in
1677 * success and negative errno otherwise.
1678 */
1679int usb4_port_sw_margin(struct tb_port *port, unsigned int lanes, bool timing,
1680 bool right_high, u32 counter)
1681{
1682 u32 val;
1683 int ret;
1684
1685 val = lanes;
1686 if (timing)
1687 val |= USB4_MARGIN_SW_TIME;
1688 if (right_high)
1689 val |= USB4_MARGIN_SW_RH;
1690 val |= (counter << USB4_MARGIN_SW_COUNTER_SHIFT) &
1691 USB4_MARGIN_SW_COUNTER_MASK;
1692
1693 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1694 USB4_SB_METADATA, &val, sizeof(val));
1695 if (ret)
1696 return ret;
1697
1698 return usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1699 USB4_SB_OPCODE_RUN_SW_LANE_MARGINING, 2500);
1700}
1701
1702/**
1703 * usb4_port_sw_margin_errors() - Read the software margining error counters
1704 * @port: USB4 port
1705 * @errors: Error metadata is copied here.
1706 *
1707 * This reads back the software margining error counters from the port.
1708 * Returns %0 in success and negative errno otherwise.
1709 */
1710int usb4_port_sw_margin_errors(struct tb_port *port, u32 *errors)
1711{
1712 int ret;
1713
1714 ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1715 USB4_SB_OPCODE_READ_SW_MARGIN_ERR, 150);
1716 if (ret)
1717 return ret;
1718
1719 return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1720 USB4_SB_METADATA, errors, sizeof(*errors));
1721}
1722
1723static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1724 enum usb4_sb_opcode opcode,
1725 int timeout_msec)
1726{
1727 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode,
1728 timeout_msec);
1729}
1730
1731/**
1732 * usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions
1733 * @port: USB4 port
1734 * @index: Retimer index
1735 *
1736 * Enables sideband channel transations on SBTX. Can be used when USB4
1737 * link does not go up, for example if there is no device connected.
1738 */
1739int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index)
1740{
1741 int ret;
1742
1743 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1744 500);
1745
1746 if (ret != -ENODEV)
1747 return ret;
1748
1749 /*
1750 * Per the USB4 retimer spec, the retimer is not required to
1751 * send an RT (Retimer Transaction) response for the first
1752 * SET_INBOUND_SBTX command
1753 */
1754 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1755 500);
1756}
1757
1758/**
1759 * usb4_port_retimer_unset_inbound_sbtx() - Disable sideband channel transactions
1760 * @port: USB4 port
1761 * @index: Retimer index
1762 *
1763 * Disables sideband channel transations on SBTX. The reverse of
1764 * usb4_port_retimer_set_inbound_sbtx().
1765 */
1766int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index)
1767{
1768 return usb4_port_retimer_op(port, index,
1769 USB4_SB_OPCODE_UNSET_INBOUND_SBTX, 500);
1770}
1771
1772/**
1773 * usb4_port_retimer_read() - Read from retimer sideband registers
1774 * @port: USB4 port
1775 * @index: Retimer index
1776 * @reg: Sideband register to read
1777 * @buf: Data from @reg is stored here
1778 * @size: Number of bytes to read
1779 *
1780 * Function reads retimer sideband registers starting from @reg. The
1781 * retimer is connected to @port at @index. Returns %0 in case of
1782 * success, and read data is copied to @buf. If there is no retimer
1783 * present at given @index returns %-ENODEV. In any other failure
1784 * returns negative errno.
1785 */
1786int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf,
1787 u8 size)
1788{
1789 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1790 size);
1791}
1792
1793/**
1794 * usb4_port_retimer_write() - Write to retimer sideband registers
1795 * @port: USB4 port
1796 * @index: Retimer index
1797 * @reg: Sideband register to write
1798 * @buf: Data that is written starting from @reg
1799 * @size: Number of bytes to write
1800 *
1801 * Writes retimer sideband registers starting from @reg. The retimer is
1802 * connected to @port at @index. Returns %0 in case of success. If there
1803 * is no retimer present at given @index returns %-ENODEV. In any other
1804 * failure returns negative errno.
1805 */
1806int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg,
1807 const void *buf, u8 size)
1808{
1809 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1810 size);
1811}
1812
1813/**
1814 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1815 * @port: USB4 port
1816 * @index: Retimer index
1817 *
1818 * If the retimer at @index is last one (connected directly to the
1819 * Type-C port) this function returns %1. If it is not returns %0. If
1820 * the retimer is not present returns %-ENODEV. Otherwise returns
1821 * negative errno.
1822 */
1823int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1824{
1825 u32 metadata;
1826 int ret;
1827
1828 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1829 500);
1830 if (ret)
1831 return ret;
1832
1833 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1834 sizeof(metadata));
1835 return ret ? ret : metadata & 1;
1836}
1837
1838/**
1839 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1840 * @port: USB4 port
1841 * @index: Retimer index
1842 *
1843 * Reads NVM sector size (in bytes) of a retimer at @index. This
1844 * operation can be used to determine whether the retimer supports NVM
1845 * upgrade for example. Returns sector size in bytes or negative errno
1846 * in case of error. Specifically returns %-ENODEV if there is no
1847 * retimer at @index.
1848 */
1849int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1850{
1851 u32 metadata;
1852 int ret;
1853
1854 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1855 500);
1856 if (ret)
1857 return ret;
1858
1859 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1860 sizeof(metadata));
1861 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1862}
1863
1864/**
1865 * usb4_port_retimer_nvm_set_offset() - Set NVM write offset
1866 * @port: USB4 port
1867 * @index: Retimer index
1868 * @address: Start offset
1869 *
1870 * Exlicitly sets NVM write offset. Normally when writing to NVM this is
1871 * done automatically by usb4_port_retimer_nvm_write().
1872 *
1873 * Returns %0 in success and negative errno if there was a failure.
1874 */
1875int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1876 unsigned int address)
1877{
1878 u32 metadata, dwaddress;
1879 int ret;
1880
1881 dwaddress = address / 4;
1882 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
1883 USB4_NVM_SET_OFFSET_MASK;
1884
1885 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1886 sizeof(metadata));
1887 if (ret)
1888 return ret;
1889
1890 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET,
1891 500);
1892}
1893
1894struct retimer_info {
1895 struct tb_port *port;
1896 u8 index;
1897};
1898
1899static int usb4_port_retimer_nvm_write_next_block(void *data,
1900 unsigned int dwaddress, const void *buf, size_t dwords)
1901
1902{
1903 const struct retimer_info *info = data;
1904 struct tb_port *port = info->port;
1905 u8 index = info->index;
1906 int ret;
1907
1908 ret = usb4_port_retimer_write(port, index, USB4_SB_DATA,
1909 buf, dwords * 4);
1910 if (ret)
1911 return ret;
1912
1913 return usb4_port_retimer_op(port, index,
1914 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000);
1915}
1916
1917/**
1918 * usb4_port_retimer_nvm_write() - Write to retimer NVM
1919 * @port: USB4 port
1920 * @index: Retimer index
1921 * @address: Byte address where to start the write
1922 * @buf: Data to write
1923 * @size: Size in bytes how much to write
1924 *
1925 * Writes @size bytes from @buf to the retimer NVM. Used for NVM
1926 * upgrade. Returns %0 if the data was written successfully and negative
1927 * errno in case of failure. Specifically returns %-ENODEV if there is
1928 * no retimer at @index.
1929 */
1930int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
1931 const void *buf, size_t size)
1932{
1933 struct retimer_info info = { .port = port, .index = index };
1934 int ret;
1935
1936 ret = usb4_port_retimer_nvm_set_offset(port, index, address);
1937 if (ret)
1938 return ret;
1939
1940 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
1941 usb4_port_retimer_nvm_write_next_block, &info);
1942}
1943
1944/**
1945 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
1946 * @port: USB4 port
1947 * @index: Retimer index
1948 *
1949 * After the new NVM image has been written via usb4_port_retimer_nvm_write()
1950 * this function can be used to trigger the NVM upgrade process. If
1951 * successful the retimer restarts with the new NVM and may not have the
1952 * index set so one needs to call usb4_port_enumerate_retimers() to
1953 * force index to be assigned.
1954 */
1955int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
1956{
1957 u32 val;
1958
1959 /*
1960 * We need to use the raw operation here because once the
1961 * authentication completes the retimer index is not set anymore
1962 * so we do not get back the status now.
1963 */
1964 val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
1965 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1966 USB4_SB_OPCODE, &val, sizeof(val));
1967}
1968
1969/**
1970 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
1971 * @port: USB4 port
1972 * @index: Retimer index
1973 * @status: Raw status code read from metadata
1974 *
1975 * This can be called after usb4_port_retimer_nvm_authenticate() and
1976 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
1977 *
1978 * Returns %0 if the authentication status was successfully read. The
1979 * completion metadata (the result) is then stored into @status. If
1980 * reading the status fails, returns negative errno.
1981 */
1982int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
1983 u32 *status)
1984{
1985 u32 metadata, val;
1986 int ret;
1987
1988 ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val,
1989 sizeof(val));
1990 if (ret)
1991 return ret;
1992
1993 ret = usb4_port_sb_opcode_err_to_errno(val);
1994 switch (ret) {
1995 case 0:
1996 *status = 0;
1997 return 0;
1998
1999 case -EAGAIN:
2000 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA,
2001 &metadata, sizeof(metadata));
2002 if (ret)
2003 return ret;
2004
2005 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
2006 return 0;
2007
2008 default:
2009 return ret;
2010 }
2011}
2012
2013static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
2014 void *buf, size_t dwords)
2015{
2016 const struct retimer_info *info = data;
2017 struct tb_port *port = info->port;
2018 u8 index = info->index;
2019 u32 metadata;
2020 int ret;
2021
2022 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
2023 if (dwords < USB4_DATA_DWORDS)
2024 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
2025
2026 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
2027 sizeof(metadata));
2028 if (ret)
2029 return ret;
2030
2031 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500);
2032 if (ret)
2033 return ret;
2034
2035 return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf,
2036 dwords * 4);
2037}
2038
2039/**
2040 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM
2041 * @port: USB4 port
2042 * @index: Retimer index
2043 * @address: NVM address (in bytes) to start reading
2044 * @buf: Data read from NVM is stored here
2045 * @size: Number of bytes to read
2046 *
2047 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the
2048 * read was successful and negative errno in case of failure.
2049 * Specifically returns %-ENODEV if there is no retimer at @index.
2050 */
2051int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
2052 unsigned int address, void *buf, size_t size)
2053{
2054 struct retimer_info info = { .port = port, .index = index };
2055
2056 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
2057 usb4_port_retimer_nvm_read_block, &info);
2058}
2059
2060static inline unsigned int
2061usb4_usb3_port_max_bandwidth(const struct tb_port *port, unsigned int bw)
2062{
2063 /* Take the possible bandwidth limitation into account */
2064 if (port->max_bw)
2065 return min(bw, port->max_bw);
2066 return bw;
2067}
2068
2069/**
2070 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate
2071 * @port: USB3 adapter port
2072 *
2073 * Return maximum supported link rate of a USB3 adapter in Mb/s.
2074 * Negative errno in case of error.
2075 */
2076int usb4_usb3_port_max_link_rate(struct tb_port *port)
2077{
2078 int ret, lr;
2079 u32 val;
2080
2081 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
2082 return -EINVAL;
2083
2084 ret = tb_port_read(port, &val, TB_CFG_PORT,
2085 port->cap_adap + ADP_USB3_CS_4, 1);
2086 if (ret)
2087 return ret;
2088
2089 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
2090 ret = lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
2091
2092 return usb4_usb3_port_max_bandwidth(port, ret);
2093}
2094
2095static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
2096{
2097 int ret;
2098 u32 val;
2099
2100 if (!tb_port_is_usb3_down(port))
2101 return -EINVAL;
2102 if (tb_route(port->sw))
2103 return -EINVAL;
2104
2105 ret = tb_port_read(port, &val, TB_CFG_PORT,
2106 port->cap_adap + ADP_USB3_CS_2, 1);
2107 if (ret)
2108 return ret;
2109
2110 if (request)
2111 val |= ADP_USB3_CS_2_CMR;
2112 else
2113 val &= ~ADP_USB3_CS_2_CMR;
2114
2115 ret = tb_port_write(port, &val, TB_CFG_PORT,
2116 port->cap_adap + ADP_USB3_CS_2, 1);
2117 if (ret)
2118 return ret;
2119
2120 /*
2121 * We can use val here directly as the CMR bit is in the same place
2122 * as HCA. Just mask out others.
2123 */
2124 val &= ADP_USB3_CS_2_CMR;
2125 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1,
2126 ADP_USB3_CS_1_HCA, val, 1500);
2127}
2128
2129static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
2130{
2131 return usb4_usb3_port_cm_request(port, true);
2132}
2133
2134static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
2135{
2136 return usb4_usb3_port_cm_request(port, false);
2137}
2138
2139static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
2140{
2141 unsigned long uframes;
2142
2143 uframes = bw * 512UL << scale;
2144 return DIV_ROUND_CLOSEST(uframes * 8000, MEGA);
2145}
2146
2147static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
2148{
2149 unsigned long uframes;
2150
2151 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
2152 uframes = ((unsigned long)mbps * MEGA) / 8000;
2153 return DIV_ROUND_UP(uframes, 512UL << scale);
2154}
2155
2156static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
2157 int *upstream_bw,
2158 int *downstream_bw)
2159{
2160 u32 val, bw, scale;
2161 int ret;
2162
2163 ret = tb_port_read(port, &val, TB_CFG_PORT,
2164 port->cap_adap + ADP_USB3_CS_2, 1);
2165 if (ret)
2166 return ret;
2167
2168 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2169 port->cap_adap + ADP_USB3_CS_3, 1);
2170 if (ret)
2171 return ret;
2172
2173 scale &= ADP_USB3_CS_3_SCALE_MASK;
2174
2175 bw = val & ADP_USB3_CS_2_AUBW_MASK;
2176 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2177
2178 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
2179 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2180
2181 return 0;
2182}
2183
2184/**
2185 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
2186 * @port: USB3 adapter port
2187 * @upstream_bw: Allocated upstream bandwidth is stored here
2188 * @downstream_bw: Allocated downstream bandwidth is stored here
2189 *
2190 * Stores currently allocated USB3 bandwidth into @upstream_bw and
2191 * @downstream_bw in Mb/s. Returns %0 in case of success and negative
2192 * errno in failure.
2193 */
2194int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
2195 int *downstream_bw)
2196{
2197 int ret;
2198
2199 ret = usb4_usb3_port_set_cm_request(port);
2200 if (ret)
2201 return ret;
2202
2203 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
2204 downstream_bw);
2205 usb4_usb3_port_clear_cm_request(port);
2206
2207 return ret;
2208}
2209
2210static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
2211 int *upstream_bw,
2212 int *downstream_bw)
2213{
2214 u32 val, bw, scale;
2215 int ret;
2216
2217 ret = tb_port_read(port, &val, TB_CFG_PORT,
2218 port->cap_adap + ADP_USB3_CS_1, 1);
2219 if (ret)
2220 return ret;
2221
2222 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2223 port->cap_adap + ADP_USB3_CS_3, 1);
2224 if (ret)
2225 return ret;
2226
2227 scale &= ADP_USB3_CS_3_SCALE_MASK;
2228
2229 bw = val & ADP_USB3_CS_1_CUBW_MASK;
2230 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2231
2232 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
2233 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2234
2235 return 0;
2236}
2237
2238static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
2239 int upstream_bw,
2240 int downstream_bw)
2241{
2242 u32 val, ubw, dbw, scale;
2243 int ret, max_bw;
2244
2245 /* Figure out suitable scale */
2246 scale = 0;
2247 max_bw = max(upstream_bw, downstream_bw);
2248 while (scale < 64) {
2249 if (mbps_to_usb3_bw(max_bw, scale) < 4096)
2250 break;
2251 scale++;
2252 }
2253
2254 if (WARN_ON(scale >= 64))
2255 return -EINVAL;
2256
2257 ret = tb_port_write(port, &scale, TB_CFG_PORT,
2258 port->cap_adap + ADP_USB3_CS_3, 1);
2259 if (ret)
2260 return ret;
2261
2262 ubw = mbps_to_usb3_bw(upstream_bw, scale);
2263 dbw = mbps_to_usb3_bw(downstream_bw, scale);
2264
2265 tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale);
2266
2267 ret = tb_port_read(port, &val, TB_CFG_PORT,
2268 port->cap_adap + ADP_USB3_CS_2, 1);
2269 if (ret)
2270 return ret;
2271
2272 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
2273 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
2274 val |= ubw;
2275
2276 return tb_port_write(port, &val, TB_CFG_PORT,
2277 port->cap_adap + ADP_USB3_CS_2, 1);
2278}
2279
2280/**
2281 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
2282 * @port: USB3 adapter port
2283 * @upstream_bw: New upstream bandwidth
2284 * @downstream_bw: New downstream bandwidth
2285 *
2286 * This can be used to set how much bandwidth is allocated for the USB3
2287 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
2288 * new values programmed to the USB3 adapter allocation registers. If
2289 * the values are lower than what is currently consumed the allocation
2290 * is set to what is currently consumed instead (consumed bandwidth
2291 * cannot be taken away by CM). The actual new values are returned in
2292 * @upstream_bw and @downstream_bw.
2293 *
2294 * Returns %0 in case of success and negative errno if there was a
2295 * failure.
2296 */
2297int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
2298 int *downstream_bw)
2299{
2300 int ret, consumed_up, consumed_down, allocate_up, allocate_down;
2301
2302 ret = usb4_usb3_port_set_cm_request(port);
2303 if (ret)
2304 return ret;
2305
2306 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2307 &consumed_down);
2308 if (ret)
2309 goto err_request;
2310
2311 /* Don't allow it go lower than what is consumed */
2312 allocate_up = max(*upstream_bw, consumed_up);
2313 allocate_down = max(*downstream_bw, consumed_down);
2314
2315 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up,
2316 allocate_down);
2317 if (ret)
2318 goto err_request;
2319
2320 *upstream_bw = allocate_up;
2321 *downstream_bw = allocate_down;
2322
2323err_request:
2324 usb4_usb3_port_clear_cm_request(port);
2325 return ret;
2326}
2327
2328/**
2329 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
2330 * @port: USB3 adapter port
2331 * @upstream_bw: New allocated upstream bandwidth
2332 * @downstream_bw: New allocated downstream bandwidth
2333 *
2334 * Releases USB3 allocated bandwidth down to what is actually consumed.
2335 * The new bandwidth is returned in @upstream_bw and @downstream_bw.
2336 *
2337 * Returns 0% in success and negative errno in case of failure.
2338 */
2339int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
2340 int *downstream_bw)
2341{
2342 int ret, consumed_up, consumed_down;
2343
2344 ret = usb4_usb3_port_set_cm_request(port);
2345 if (ret)
2346 return ret;
2347
2348 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2349 &consumed_down);
2350 if (ret)
2351 goto err_request;
2352
2353 /*
2354 * Always keep 900 Mb/s to make sure xHCI has at least some
2355 * bandwidth available for isochronous traffic.
2356 */
2357 if (consumed_up < 900)
2358 consumed_up = 900;
2359 if (consumed_down < 900)
2360 consumed_down = 900;
2361
2362 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up,
2363 consumed_down);
2364 if (ret)
2365 goto err_request;
2366
2367 *upstream_bw = consumed_up;
2368 *downstream_bw = consumed_down;
2369
2370err_request:
2371 usb4_usb3_port_clear_cm_request(port);
2372 return ret;
2373}
2374
2375static bool is_usb4_dpin(const struct tb_port *port)
2376{
2377 if (!tb_port_is_dpin(port))
2378 return false;
2379 if (!tb_switch_is_usb4(port->sw))
2380 return false;
2381 return true;
2382}
2383
2384/**
2385 * usb4_dp_port_set_cm_id() - Assign CM ID to the DP IN adapter
2386 * @port: DP IN adapter
2387 * @cm_id: CM ID to assign
2388 *
2389 * Sets CM ID for the @port. Returns %0 on success and negative errno
2390 * otherwise. Speficially returns %-EOPNOTSUPP if the @port does not
2391 * support this.
2392 */
2393int usb4_dp_port_set_cm_id(struct tb_port *port, int cm_id)
2394{
2395 u32 val;
2396 int ret;
2397
2398 if (!is_usb4_dpin(port))
2399 return -EOPNOTSUPP;
2400
2401 ret = tb_port_read(port, &val, TB_CFG_PORT,
2402 port->cap_adap + ADP_DP_CS_2, 1);
2403 if (ret)
2404 return ret;
2405
2406 val &= ~ADP_DP_CS_2_CM_ID_MASK;
2407 val |= cm_id << ADP_DP_CS_2_CM_ID_SHIFT;
2408
2409 return tb_port_write(port, &val, TB_CFG_PORT,
2410 port->cap_adap + ADP_DP_CS_2, 1);
2411}
2412
2413/**
2414 * usb4_dp_port_bandwidth_mode_supported() - Is the bandwidth allocation mode
2415 * supported
2416 * @port: DP IN adapter to check
2417 *
2418 * Can be called to any DP IN adapter. Returns true if the adapter
2419 * supports USB4 bandwidth allocation mode, false otherwise.
2420 */
2421bool usb4_dp_port_bandwidth_mode_supported(struct tb_port *port)
2422{
2423 int ret;
2424 u32 val;
2425
2426 if (!is_usb4_dpin(port))
2427 return false;
2428
2429 ret = tb_port_read(port, &val, TB_CFG_PORT,
2430 port->cap_adap + DP_LOCAL_CAP, 1);
2431 if (ret)
2432 return false;
2433
2434 return !!(val & DP_COMMON_CAP_BW_MODE);
2435}
2436
2437/**
2438 * usb4_dp_port_bandwidth_mode_enabled() - Is the bandwidth allocation mode
2439 * enabled
2440 * @port: DP IN adapter to check
2441 *
2442 * Can be called to any DP IN adapter. Returns true if the bandwidth
2443 * allocation mode has been enabled, false otherwise.
2444 */
2445bool usb4_dp_port_bandwidth_mode_enabled(struct tb_port *port)
2446{
2447 int ret;
2448 u32 val;
2449
2450 if (!is_usb4_dpin(port))
2451 return false;
2452
2453 ret = tb_port_read(port, &val, TB_CFG_PORT,
2454 port->cap_adap + ADP_DP_CS_8, 1);
2455 if (ret)
2456 return false;
2457
2458 return !!(val & ADP_DP_CS_8_DPME);
2459}
2460
2461/**
2462 * usb4_dp_port_set_cm_bandwidth_mode_supported() - Set/clear CM support for
2463 * bandwidth allocation mode
2464 * @port: DP IN adapter
2465 * @supported: Does the CM support bandwidth allocation mode
2466 *
2467 * Can be called to any DP IN adapter. Sets or clears the CM support bit
2468 * of the DP IN adapter. Returns %0 in success and negative errno
2469 * otherwise. Specifically returns %-OPNOTSUPP if the passed in adapter
2470 * does not support this.
2471 */
2472int usb4_dp_port_set_cm_bandwidth_mode_supported(struct tb_port *port,
2473 bool supported)
2474{
2475 u32 val;
2476 int ret;
2477
2478 if (!is_usb4_dpin(port))
2479 return -EOPNOTSUPP;
2480
2481 ret = tb_port_read(port, &val, TB_CFG_PORT,
2482 port->cap_adap + ADP_DP_CS_2, 1);
2483 if (ret)
2484 return ret;
2485
2486 if (supported)
2487 val |= ADP_DP_CS_2_CMMS;
2488 else
2489 val &= ~ADP_DP_CS_2_CMMS;
2490
2491 return tb_port_write(port, &val, TB_CFG_PORT,
2492 port->cap_adap + ADP_DP_CS_2, 1);
2493}
2494
2495/**
2496 * usb4_dp_port_group_id() - Return Group ID assigned for the adapter
2497 * @port: DP IN adapter
2498 *
2499 * Reads bandwidth allocation Group ID from the DP IN adapter and
2500 * returns it. If the adapter does not support setting Group_ID
2501 * %-EOPNOTSUPP is returned.
2502 */
2503int usb4_dp_port_group_id(struct tb_port *port)
2504{
2505 u32 val;
2506 int ret;
2507
2508 if (!is_usb4_dpin(port))
2509 return -EOPNOTSUPP;
2510
2511 ret = tb_port_read(port, &val, TB_CFG_PORT,
2512 port->cap_adap + ADP_DP_CS_2, 1);
2513 if (ret)
2514 return ret;
2515
2516 return (val & ADP_DP_CS_2_GROUP_ID_MASK) >> ADP_DP_CS_2_GROUP_ID_SHIFT;
2517}
2518
2519/**
2520 * usb4_dp_port_set_group_id() - Set adapter Group ID
2521 * @port: DP IN adapter
2522 * @group_id: Group ID for the adapter
2523 *
2524 * Sets bandwidth allocation mode Group ID for the DP IN adapter.
2525 * Returns %0 in case of success and negative errno otherwise.
2526 * Specifically returns %-EOPNOTSUPP if the adapter does not support
2527 * this.
2528 */
2529int usb4_dp_port_set_group_id(struct tb_port *port, int group_id)
2530{
2531 u32 val;
2532 int ret;
2533
2534 if (!is_usb4_dpin(port))
2535 return -EOPNOTSUPP;
2536
2537 ret = tb_port_read(port, &val, TB_CFG_PORT,
2538 port->cap_adap + ADP_DP_CS_2, 1);
2539 if (ret)
2540 return ret;
2541
2542 val &= ~ADP_DP_CS_2_GROUP_ID_MASK;
2543 val |= group_id << ADP_DP_CS_2_GROUP_ID_SHIFT;
2544
2545 return tb_port_write(port, &val, TB_CFG_PORT,
2546 port->cap_adap + ADP_DP_CS_2, 1);
2547}
2548
2549/**
2550 * usb4_dp_port_nrd() - Read non-reduced rate and lanes
2551 * @port: DP IN adapter
2552 * @rate: Non-reduced rate in Mb/s is placed here
2553 * @lanes: Non-reduced lanes are placed here
2554 *
2555 * Reads the non-reduced rate and lanes from the DP IN adapter. Returns
2556 * %0 in success and negative errno otherwise. Specifically returns
2557 * %-EOPNOTSUPP if the adapter does not support this.
2558 */
2559int usb4_dp_port_nrd(struct tb_port *port, int *rate, int *lanes)
2560{
2561 u32 val, tmp;
2562 int ret;
2563
2564 if (!is_usb4_dpin(port))
2565 return -EOPNOTSUPP;
2566
2567 ret = tb_port_read(port, &val, TB_CFG_PORT,
2568 port->cap_adap + ADP_DP_CS_2, 1);
2569 if (ret)
2570 return ret;
2571
2572 tmp = (val & ADP_DP_CS_2_NRD_MLR_MASK) >> ADP_DP_CS_2_NRD_MLR_SHIFT;
2573 switch (tmp) {
2574 case DP_COMMON_CAP_RATE_RBR:
2575 *rate = 1620;
2576 break;
2577 case DP_COMMON_CAP_RATE_HBR:
2578 *rate = 2700;
2579 break;
2580 case DP_COMMON_CAP_RATE_HBR2:
2581 *rate = 5400;
2582 break;
2583 case DP_COMMON_CAP_RATE_HBR3:
2584 *rate = 8100;
2585 break;
2586 }
2587
2588 tmp = val & ADP_DP_CS_2_NRD_MLC_MASK;
2589 switch (tmp) {
2590 case DP_COMMON_CAP_1_LANE:
2591 *lanes = 1;
2592 break;
2593 case DP_COMMON_CAP_2_LANES:
2594 *lanes = 2;
2595 break;
2596 case DP_COMMON_CAP_4_LANES:
2597 *lanes = 4;
2598 break;
2599 }
2600
2601 return 0;
2602}
2603
2604/**
2605 * usb4_dp_port_set_nrd() - Set non-reduced rate and lanes
2606 * @port: DP IN adapter
2607 * @rate: Non-reduced rate in Mb/s
2608 * @lanes: Non-reduced lanes
2609 *
2610 * Before the capabilities reduction this function can be used to set
2611 * the non-reduced values for the DP IN adapter. Returns %0 in success
2612 * and negative errno otherwise. If the adapter does not support this
2613 * %-EOPNOTSUPP is returned.
2614 */
2615int usb4_dp_port_set_nrd(struct tb_port *port, int rate, int lanes)
2616{
2617 u32 val;
2618 int ret;
2619
2620 if (!is_usb4_dpin(port))
2621 return -EOPNOTSUPP;
2622
2623 ret = tb_port_read(port, &val, TB_CFG_PORT,
2624 port->cap_adap + ADP_DP_CS_2, 1);
2625 if (ret)
2626 return ret;
2627
2628 val &= ~ADP_DP_CS_2_NRD_MLR_MASK;
2629
2630 switch (rate) {
2631 case 1620:
2632 break;
2633 case 2700:
2634 val |= (DP_COMMON_CAP_RATE_HBR << ADP_DP_CS_2_NRD_MLR_SHIFT)
2635 & ADP_DP_CS_2_NRD_MLR_MASK;
2636 break;
2637 case 5400:
2638 val |= (DP_COMMON_CAP_RATE_HBR2 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2639 & ADP_DP_CS_2_NRD_MLR_MASK;
2640 break;
2641 case 8100:
2642 val |= (DP_COMMON_CAP_RATE_HBR3 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2643 & ADP_DP_CS_2_NRD_MLR_MASK;
2644 break;
2645 default:
2646 return -EINVAL;
2647 }
2648
2649 val &= ~ADP_DP_CS_2_NRD_MLC_MASK;
2650
2651 switch (lanes) {
2652 case 1:
2653 break;
2654 case 2:
2655 val |= DP_COMMON_CAP_2_LANES;
2656 break;
2657 case 4:
2658 val |= DP_COMMON_CAP_4_LANES;
2659 break;
2660 default:
2661 return -EINVAL;
2662 }
2663
2664 return tb_port_write(port, &val, TB_CFG_PORT,
2665 port->cap_adap + ADP_DP_CS_2, 1);
2666}
2667
2668/**
2669 * usb4_dp_port_granularity() - Return granularity for the bandwidth values
2670 * @port: DP IN adapter
2671 *
2672 * Reads the programmed granularity from @port. If the DP IN adapter does
2673 * not support bandwidth allocation mode returns %-EOPNOTSUPP and negative
2674 * errno in other error cases.
2675 */
2676int usb4_dp_port_granularity(struct tb_port *port)
2677{
2678 u32 val;
2679 int ret;
2680
2681 if (!is_usb4_dpin(port))
2682 return -EOPNOTSUPP;
2683
2684 ret = tb_port_read(port, &val, TB_CFG_PORT,
2685 port->cap_adap + ADP_DP_CS_2, 1);
2686 if (ret)
2687 return ret;
2688
2689 val &= ADP_DP_CS_2_GR_MASK;
2690 val >>= ADP_DP_CS_2_GR_SHIFT;
2691
2692 switch (val) {
2693 case ADP_DP_CS_2_GR_0_25G:
2694 return 250;
2695 case ADP_DP_CS_2_GR_0_5G:
2696 return 500;
2697 case ADP_DP_CS_2_GR_1G:
2698 return 1000;
2699 }
2700
2701 return -EINVAL;
2702}
2703
2704/**
2705 * usb4_dp_port_set_granularity() - Set granularity for the bandwidth values
2706 * @port: DP IN adapter
2707 * @granularity: Granularity in Mb/s. Supported values: 1000, 500 and 250.
2708 *
2709 * Sets the granularity used with the estimated, allocated and requested
2710 * bandwidth. Returns %0 in success and negative errno otherwise. If the
2711 * adapter does not support this %-EOPNOTSUPP is returned.
2712 */
2713int usb4_dp_port_set_granularity(struct tb_port *port, int granularity)
2714{
2715 u32 val;
2716 int ret;
2717
2718 if (!is_usb4_dpin(port))
2719 return -EOPNOTSUPP;
2720
2721 ret = tb_port_read(port, &val, TB_CFG_PORT,
2722 port->cap_adap + ADP_DP_CS_2, 1);
2723 if (ret)
2724 return ret;
2725
2726 val &= ~ADP_DP_CS_2_GR_MASK;
2727
2728 switch (granularity) {
2729 case 250:
2730 val |= ADP_DP_CS_2_GR_0_25G << ADP_DP_CS_2_GR_SHIFT;
2731 break;
2732 case 500:
2733 val |= ADP_DP_CS_2_GR_0_5G << ADP_DP_CS_2_GR_SHIFT;
2734 break;
2735 case 1000:
2736 val |= ADP_DP_CS_2_GR_1G << ADP_DP_CS_2_GR_SHIFT;
2737 break;
2738 default:
2739 return -EINVAL;
2740 }
2741
2742 return tb_port_write(port, &val, TB_CFG_PORT,
2743 port->cap_adap + ADP_DP_CS_2, 1);
2744}
2745
2746/**
2747 * usb4_dp_port_set_estimated_bandwidth() - Set estimated bandwidth
2748 * @port: DP IN adapter
2749 * @bw: Estimated bandwidth in Mb/s.
2750 *
2751 * Sets the estimated bandwidth to @bw. Set the granularity by calling
2752 * usb4_dp_port_set_granularity() before calling this. The @bw is round
2753 * down to the closest granularity multiplier. Returns %0 in success
2754 * and negative errno otherwise. Specifically returns %-EOPNOTSUPP if
2755 * the adapter does not support this.
2756 */
2757int usb4_dp_port_set_estimated_bandwidth(struct tb_port *port, int bw)
2758{
2759 u32 val, granularity;
2760 int ret;
2761
2762 if (!is_usb4_dpin(port))
2763 return -EOPNOTSUPP;
2764
2765 ret = usb4_dp_port_granularity(port);
2766 if (ret < 0)
2767 return ret;
2768 granularity = ret;
2769
2770 ret = tb_port_read(port, &val, TB_CFG_PORT,
2771 port->cap_adap + ADP_DP_CS_2, 1);
2772 if (ret)
2773 return ret;
2774
2775 val &= ~ADP_DP_CS_2_ESTIMATED_BW_MASK;
2776 val |= (bw / granularity) << ADP_DP_CS_2_ESTIMATED_BW_SHIFT;
2777
2778 return tb_port_write(port, &val, TB_CFG_PORT,
2779 port->cap_adap + ADP_DP_CS_2, 1);
2780}
2781
2782/**
2783 * usb4_dp_port_allocated_bandwidth() - Return allocated bandwidth
2784 * @port: DP IN adapter
2785 *
2786 * Reads and returns allocated bandwidth for @port in Mb/s (taking into
2787 * account the programmed granularity). Returns negative errno in case
2788 * of error.
2789 */
2790int usb4_dp_port_allocated_bandwidth(struct tb_port *port)
2791{
2792 u32 val, granularity;
2793 int ret;
2794
2795 if (!is_usb4_dpin(port))
2796 return -EOPNOTSUPP;
2797
2798 ret = usb4_dp_port_granularity(port);
2799 if (ret < 0)
2800 return ret;
2801 granularity = ret;
2802
2803 ret = tb_port_read(port, &val, TB_CFG_PORT,
2804 port->cap_adap + DP_STATUS, 1);
2805 if (ret)
2806 return ret;
2807
2808 val &= DP_STATUS_ALLOCATED_BW_MASK;
2809 val >>= DP_STATUS_ALLOCATED_BW_SHIFT;
2810
2811 return val * granularity;
2812}
2813
2814static int __usb4_dp_port_set_cm_ack(struct tb_port *port, bool ack)
2815{
2816 u32 val;
2817 int ret;
2818
2819 ret = tb_port_read(port, &val, TB_CFG_PORT,
2820 port->cap_adap + ADP_DP_CS_2, 1);
2821 if (ret)
2822 return ret;
2823
2824 if (ack)
2825 val |= ADP_DP_CS_2_CA;
2826 else
2827 val &= ~ADP_DP_CS_2_CA;
2828
2829 return tb_port_write(port, &val, TB_CFG_PORT,
2830 port->cap_adap + ADP_DP_CS_2, 1);
2831}
2832
2833static inline int usb4_dp_port_set_cm_ack(struct tb_port *port)
2834{
2835 return __usb4_dp_port_set_cm_ack(port, true);
2836}
2837
2838static int usb4_dp_port_wait_and_clear_cm_ack(struct tb_port *port,
2839 int timeout_msec)
2840{
2841 ktime_t end;
2842 u32 val;
2843 int ret;
2844
2845 ret = __usb4_dp_port_set_cm_ack(port, false);
2846 if (ret)
2847 return ret;
2848
2849 end = ktime_add_ms(ktime_get(), timeout_msec);
2850 do {
2851 ret = tb_port_read(port, &val, TB_CFG_PORT,
2852 port->cap_adap + ADP_DP_CS_8, 1);
2853 if (ret)
2854 return ret;
2855
2856 if (!(val & ADP_DP_CS_8_DR))
2857 break;
2858
2859 usleep_range(50, 100);
2860 } while (ktime_before(ktime_get(), end));
2861
2862 if (val & ADP_DP_CS_8_DR) {
2863 tb_port_warn(port, "timeout waiting for DPTX request to clear\n");
2864 return -ETIMEDOUT;
2865 }
2866
2867 ret = tb_port_read(port, &val, TB_CFG_PORT,
2868 port->cap_adap + ADP_DP_CS_2, 1);
2869 if (ret)
2870 return ret;
2871
2872 val &= ~ADP_DP_CS_2_CA;
2873 return tb_port_write(port, &val, TB_CFG_PORT,
2874 port->cap_adap + ADP_DP_CS_2, 1);
2875}
2876
2877/**
2878 * usb4_dp_port_allocate_bandwidth() - Set allocated bandwidth
2879 * @port: DP IN adapter
2880 * @bw: New allocated bandwidth in Mb/s
2881 *
2882 * Communicates the new allocated bandwidth with the DPCD (graphics
2883 * driver). Takes into account the programmed granularity. Returns %0 in
2884 * success and negative errno in case of error.
2885 */
2886int usb4_dp_port_allocate_bandwidth(struct tb_port *port, int bw)
2887{
2888 u32 val, granularity;
2889 int ret;
2890
2891 if (!is_usb4_dpin(port))
2892 return -EOPNOTSUPP;
2893
2894 ret = usb4_dp_port_granularity(port);
2895 if (ret < 0)
2896 return ret;
2897 granularity = ret;
2898
2899 ret = tb_port_read(port, &val, TB_CFG_PORT,
2900 port->cap_adap + DP_STATUS, 1);
2901 if (ret)
2902 return ret;
2903
2904 val &= ~DP_STATUS_ALLOCATED_BW_MASK;
2905 val |= (bw / granularity) << DP_STATUS_ALLOCATED_BW_SHIFT;
2906
2907 ret = tb_port_write(port, &val, TB_CFG_PORT,
2908 port->cap_adap + DP_STATUS, 1);
2909 if (ret)
2910 return ret;
2911
2912 ret = usb4_dp_port_set_cm_ack(port);
2913 if (ret)
2914 return ret;
2915
2916 return usb4_dp_port_wait_and_clear_cm_ack(port, 500);
2917}
2918
2919/**
2920 * usb4_dp_port_requested_bandwidth() - Read requested bandwidth
2921 * @port: DP IN adapter
2922 *
2923 * Reads the DPCD (graphics driver) requested bandwidth and returns it
2924 * in Mb/s. Takes the programmed granularity into account. In case of
2925 * error returns negative errno. Specifically returns %-EOPNOTSUPP if
2926 * the adapter does not support bandwidth allocation mode, and %ENODATA
2927 * if there is no active bandwidth request from the graphics driver.
2928 */
2929int usb4_dp_port_requested_bandwidth(struct tb_port *port)
2930{
2931 u32 val, granularity;
2932 int ret;
2933
2934 if (!is_usb4_dpin(port))
2935 return -EOPNOTSUPP;
2936
2937 ret = usb4_dp_port_granularity(port);
2938 if (ret < 0)
2939 return ret;
2940 granularity = ret;
2941
2942 ret = tb_port_read(port, &val, TB_CFG_PORT,
2943 port->cap_adap + ADP_DP_CS_8, 1);
2944 if (ret)
2945 return ret;
2946
2947 if (!(val & ADP_DP_CS_8_DR))
2948 return -ENODATA;
2949
2950 return (val & ADP_DP_CS_8_REQUESTED_BW_MASK) * granularity;
2951}
2952
2953/**
2954 * usb4_pci_port_set_ext_encapsulation() - Enable/disable extended encapsulation
2955 * @port: PCIe adapter
2956 * @enable: Enable/disable extended encapsulation
2957 *
2958 * Enables or disables extended encapsulation used in PCIe tunneling. Caller
2959 * needs to make sure both adapters support this before enabling. Returns %0 on
2960 * success and negative errno otherwise.
2961 */
2962int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable)
2963{
2964 u32 val;
2965 int ret;
2966
2967 if (!tb_port_is_pcie_up(port) && !tb_port_is_pcie_down(port))
2968 return -EINVAL;
2969
2970 ret = tb_port_read(port, &val, TB_CFG_PORT,
2971 port->cap_adap + ADP_PCIE_CS_1, 1);
2972 if (ret)
2973 return ret;
2974
2975 if (enable)
2976 val |= ADP_PCIE_CS_1_EE;
2977 else
2978 val &= ~ADP_PCIE_CS_1_EE;
2979
2980 return tb_port_write(port, &val, TB_CFG_PORT,
2981 port->cap_adap + ADP_PCIE_CS_1, 1);
2982}