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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PIC32 Integrated Serial Driver.
4 *
5 * Copyright (C) 2015 Microchip Technology, Inc.
6 *
7 * Authors:
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/of.h>
14#include <linux/of_irq.h>
15#include <linux/of_gpio.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/slab.h>
19#include <linux/console.h>
20#include <linux/clk.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24#include <linux/delay.h>
25
26#include <asm/mach-pic32/pic32.h>
27
28/* UART name and device definitions */
29#define PIC32_DEV_NAME "pic32-uart"
30#define PIC32_MAX_UARTS 6
31#define PIC32_SDEV_NAME "ttyPIC"
32
33#define PIC32_UART_DFLT_BRATE 9600
34#define PIC32_UART_TX_FIFO_DEPTH 8
35#define PIC32_UART_RX_FIFO_DEPTH 8
36
37#define PIC32_UART_MODE 0x00
38#define PIC32_UART_STA 0x10
39#define PIC32_UART_TX 0x20
40#define PIC32_UART_RX 0x30
41#define PIC32_UART_BRG 0x40
42
43/* struct pic32_sport - pic32 serial port descriptor
44 * @port: uart port descriptor
45 * @idx: port index
46 * @irq_fault: virtual fault interrupt number
47 * @irq_fault_name: irq fault name
48 * @irq_rx: virtual rx interrupt number
49 * @irq_rx_name: irq rx name
50 * @irq_tx: virtual tx interrupt number
51 * @irq_tx_name: irq tx name
52 * @cts_gpiod: clear to send GPIO
53 * @dev: device descriptor
54 **/
55struct pic32_sport {
56 struct uart_port port;
57 int idx;
58
59 int irq_fault;
60 const char *irq_fault_name;
61 int irq_rx;
62 const char *irq_rx_name;
63 int irq_tx;
64 const char *irq_tx_name;
65 bool enable_tx_irq;
66
67 struct gpio_desc *cts_gpiod;
68
69 struct clk *clk;
70
71 struct device *dev;
72};
73
74static inline struct pic32_sport *to_pic32_sport(struct uart_port *port)
75{
76 return container_of(port, struct pic32_sport, port);
77}
78
79static inline void pic32_uart_writel(struct pic32_sport *sport,
80 u32 reg, u32 val)
81{
82 __raw_writel(val, sport->port.membase + reg);
83}
84
85static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
86{
87 return __raw_readl(sport->port.membase + reg);
88}
89
90/* pic32 uart mode register bits */
91#define PIC32_UART_MODE_ON BIT(15)
92#define PIC32_UART_MODE_FRZ BIT(14)
93#define PIC32_UART_MODE_SIDL BIT(13)
94#define PIC32_UART_MODE_IREN BIT(12)
95#define PIC32_UART_MODE_RTSMD BIT(11)
96#define PIC32_UART_MODE_RESV1 BIT(10)
97#define PIC32_UART_MODE_UEN1 BIT(9)
98#define PIC32_UART_MODE_UEN0 BIT(8)
99#define PIC32_UART_MODE_WAKE BIT(7)
100#define PIC32_UART_MODE_LPBK BIT(6)
101#define PIC32_UART_MODE_ABAUD BIT(5)
102#define PIC32_UART_MODE_RXINV BIT(4)
103#define PIC32_UART_MODE_BRGH BIT(3)
104#define PIC32_UART_MODE_PDSEL1 BIT(2)
105#define PIC32_UART_MODE_PDSEL0 BIT(1)
106#define PIC32_UART_MODE_STSEL BIT(0)
107
108/* pic32 uart status register bits */
109#define PIC32_UART_STA_UTXISEL1 BIT(15)
110#define PIC32_UART_STA_UTXISEL0 BIT(14)
111#define PIC32_UART_STA_UTXINV BIT(13)
112#define PIC32_UART_STA_URXEN BIT(12)
113#define PIC32_UART_STA_UTXBRK BIT(11)
114#define PIC32_UART_STA_UTXEN BIT(10)
115#define PIC32_UART_STA_UTXBF BIT(9)
116#define PIC32_UART_STA_TRMT BIT(8)
117#define PIC32_UART_STA_URXISEL1 BIT(7)
118#define PIC32_UART_STA_URXISEL0 BIT(6)
119#define PIC32_UART_STA_ADDEN BIT(5)
120#define PIC32_UART_STA_RIDLE BIT(4)
121#define PIC32_UART_STA_PERR BIT(3)
122#define PIC32_UART_STA_FERR BIT(2)
123#define PIC32_UART_STA_OERR BIT(1)
124#define PIC32_UART_STA_URXDA BIT(0)
125
126/* pic32_sport pointer for console use */
127static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
128
129static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
130{
131 /* wait for tx empty, otherwise chars will be lost or corrupted */
132 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
133 udelay(1);
134}
135
136/* serial core request to check if uart tx buffer is empty */
137static unsigned int pic32_uart_tx_empty(struct uart_port *port)
138{
139 struct pic32_sport *sport = to_pic32_sport(port);
140 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
141
142 return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
143}
144
145/* serial core request to set UART outputs */
146static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
147{
148 struct pic32_sport *sport = to_pic32_sport(port);
149
150 /* set loopback mode */
151 if (mctrl & TIOCM_LOOP)
152 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
153 PIC32_UART_MODE_LPBK);
154 else
155 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
156 PIC32_UART_MODE_LPBK);
157}
158
159/* serial core request to return the state of misc UART input pins */
160static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
161{
162 struct pic32_sport *sport = to_pic32_sport(port);
163 unsigned int mctrl = 0;
164
165 /* get the state of CTS input pin for this port */
166 if (!sport->cts_gpiod)
167 mctrl |= TIOCM_CTS;
168 else if (gpiod_get_value(sport->cts_gpiod))
169 mctrl |= TIOCM_CTS;
170
171 /* DSR and CD are not supported in PIC32, so return 1
172 * RI is not supported in PIC32, so return 0
173 */
174 mctrl |= TIOCM_CD;
175 mctrl |= TIOCM_DSR;
176
177 return mctrl;
178}
179
180/* stop tx and start tx are not called in pairs, therefore a flag indicates
181 * the status of irq to control the irq-depth.
182 */
183static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
184{
185 if (en && !sport->enable_tx_irq) {
186 enable_irq(sport->irq_tx);
187 sport->enable_tx_irq = true;
188 } else if (!en && sport->enable_tx_irq) {
189 /* use disable_irq_nosync() and not disable_irq() to avoid self
190 * imposed deadlock by not waiting for irq handler to end,
191 * since this callback is called from interrupt context.
192 */
193 disable_irq_nosync(sport->irq_tx);
194 sport->enable_tx_irq = false;
195 }
196}
197
198/* serial core request to disable tx ASAP (used for flow control) */
199static void pic32_uart_stop_tx(struct uart_port *port)
200{
201 struct pic32_sport *sport = to_pic32_sport(port);
202
203 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
204 return;
205
206 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
207 return;
208
209 /* wait for tx empty */
210 pic32_wait_deplete_txbuf(sport);
211
212 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
213 PIC32_UART_STA_UTXEN);
214 pic32_uart_irqtxen(sport, 0);
215}
216
217/* serial core request to (re)enable tx */
218static void pic32_uart_start_tx(struct uart_port *port)
219{
220 struct pic32_sport *sport = to_pic32_sport(port);
221
222 pic32_uart_irqtxen(sport, 1);
223 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
224 PIC32_UART_STA_UTXEN);
225}
226
227/* serial core request to stop rx, called before port shutdown */
228static void pic32_uart_stop_rx(struct uart_port *port)
229{
230 struct pic32_sport *sport = to_pic32_sport(port);
231
232 /* disable rx interrupts */
233 disable_irq(sport->irq_rx);
234
235 /* receiver Enable bit OFF */
236 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
237 PIC32_UART_STA_URXEN);
238}
239
240/* serial core request to start/stop emitting break char */
241static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
242{
243 struct pic32_sport *sport = to_pic32_sport(port);
244 unsigned long flags;
245
246 uart_port_lock_irqsave(port, &flags);
247
248 if (ctl)
249 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
250 PIC32_UART_STA_UTXBRK);
251 else
252 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
253 PIC32_UART_STA_UTXBRK);
254
255 uart_port_unlock_irqrestore(port, flags);
256}
257
258/* get port type in string format */
259static const char *pic32_uart_type(struct uart_port *port)
260{
261 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
262}
263
264/* read all chars in rx fifo and send them to core */
265static void pic32_uart_do_rx(struct uart_port *port)
266{
267 struct pic32_sport *sport = to_pic32_sport(port);
268 struct tty_port *tty;
269 unsigned int max_count;
270
271 /* limit number of char read in interrupt, should not be
272 * higher than fifo size anyway since we're much faster than
273 * serial port
274 */
275 max_count = PIC32_UART_RX_FIFO_DEPTH;
276
277 uart_port_lock(port);
278
279 tty = &port->state->port;
280
281 do {
282 u32 sta_reg, c;
283 char flag;
284
285 /* get overrun/fifo empty information from status register */
286 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
287 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
288
289 /* fifo reset is required to clear interrupt */
290 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
291 PIC32_UART_STA_OERR);
292
293 port->icount.overrun++;
294 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
295 }
296
297 /* Can at least one more character can be read? */
298 if (!(sta_reg & PIC32_UART_STA_URXDA))
299 break;
300
301 /* read the character and increment the rx counter */
302 c = pic32_uart_readl(sport, PIC32_UART_RX);
303
304 port->icount.rx++;
305 flag = TTY_NORMAL;
306 c &= 0xff;
307
308 if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
309 (sta_reg & PIC32_UART_STA_FERR))) {
310
311 /* do stats first */
312 if (sta_reg & PIC32_UART_STA_PERR)
313 port->icount.parity++;
314 if (sta_reg & PIC32_UART_STA_FERR)
315 port->icount.frame++;
316
317 /* update flag wrt read_status_mask */
318 sta_reg &= port->read_status_mask;
319
320 if (sta_reg & PIC32_UART_STA_FERR)
321 flag = TTY_FRAME;
322 if (sta_reg & PIC32_UART_STA_PERR)
323 flag = TTY_PARITY;
324 }
325
326 if (uart_handle_sysrq_char(port, c))
327 continue;
328
329 if ((sta_reg & port->ignore_status_mask) == 0)
330 tty_insert_flip_char(tty, c, flag);
331
332 } while (--max_count);
333
334 uart_port_unlock(port);
335
336 tty_flip_buffer_push(tty);
337}
338
339/* fill tx fifo with chars to send, stop when fifo is about to be full
340 * or when all chars have been sent.
341 */
342static void pic32_uart_do_tx(struct uart_port *port)
343{
344 struct pic32_sport *sport = to_pic32_sport(port);
345 struct circ_buf *xmit = &port->state->xmit;
346 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
347
348 if (port->x_char) {
349 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
350 port->icount.tx++;
351 port->x_char = 0;
352 return;
353 }
354
355 if (uart_tx_stopped(port)) {
356 pic32_uart_stop_tx(port);
357 return;
358 }
359
360 if (uart_circ_empty(xmit))
361 goto txq_empty;
362
363 /* keep stuffing chars into uart tx buffer
364 * 1) until uart fifo is full
365 * or
366 * 2) until the circ buffer is empty
367 * (all chars have been sent)
368 * or
369 * 3) until the max count is reached
370 * (prevents lingering here for too long in certain cases)
371 */
372 while (!(PIC32_UART_STA_UTXBF &
373 pic32_uart_readl(sport, PIC32_UART_STA))) {
374 unsigned int c = xmit->buf[xmit->tail];
375
376 pic32_uart_writel(sport, PIC32_UART_TX, c);
377
378 uart_xmit_advance(port, 1);
379 if (uart_circ_empty(xmit))
380 break;
381 if (--max_count == 0)
382 break;
383 }
384
385 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
386 uart_write_wakeup(port);
387
388 if (uart_circ_empty(xmit))
389 goto txq_empty;
390
391 return;
392
393txq_empty:
394 pic32_uart_irqtxen(sport, 0);
395}
396
397/* RX interrupt handler */
398static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
399{
400 struct uart_port *port = dev_id;
401
402 pic32_uart_do_rx(port);
403
404 return IRQ_HANDLED;
405}
406
407/* TX interrupt handler */
408static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
409{
410 struct uart_port *port = dev_id;
411 unsigned long flags;
412
413 uart_port_lock_irqsave(port, &flags);
414 pic32_uart_do_tx(port);
415 uart_port_unlock_irqrestore(port, flags);
416
417 return IRQ_HANDLED;
418}
419
420/* FAULT interrupt handler */
421static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
422{
423 /* do nothing: pic32_uart_do_rx() handles faults. */
424 return IRQ_HANDLED;
425}
426
427/* enable rx & tx operation on uart */
428static void pic32_uart_en_and_unmask(struct uart_port *port)
429{
430 struct pic32_sport *sport = to_pic32_sport(port);
431
432 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
433 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
434 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
435 PIC32_UART_MODE_ON);
436}
437
438/* disable rx & tx operation on uart */
439static void pic32_uart_dsbl_and_mask(struct uart_port *port)
440{
441 struct pic32_sport *sport = to_pic32_sport(port);
442
443 /* wait for tx empty, otherwise chars will be lost or corrupted */
444 pic32_wait_deplete_txbuf(sport);
445
446 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
447 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
448 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
449 PIC32_UART_MODE_ON);
450}
451
452/* serial core request to initialize uart and start rx operation */
453static int pic32_uart_startup(struct uart_port *port)
454{
455 struct pic32_sport *sport = to_pic32_sport(port);
456 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
457 unsigned long flags;
458 int ret;
459
460 local_irq_save(flags);
461
462 ret = clk_prepare_enable(sport->clk);
463 if (ret) {
464 local_irq_restore(flags);
465 goto out_done;
466 }
467
468 /* clear status and mode registers */
469 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
470 pic32_uart_writel(sport, PIC32_UART_STA, 0);
471
472 /* disable uart and mask all interrupts */
473 pic32_uart_dsbl_and_mask(port);
474
475 /* set default baud */
476 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
477
478 local_irq_restore(flags);
479
480 /* Each UART of a PIC32 has three interrupts therefore,
481 * we setup driver to register the 3 irqs for the device.
482 *
483 * For each irq request_irq() is called with interrupt disabled.
484 * And the irq is enabled as soon as we are ready to handle them.
485 */
486 sport->enable_tx_irq = false;
487
488 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
489 pic32_uart_type(port),
490 sport->idx);
491 if (!sport->irq_fault_name) {
492 dev_err(port->dev, "%s: kasprintf err!", __func__);
493 ret = -ENOMEM;
494 goto out_disable_clk;
495 }
496 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
497 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
498 IRQF_NO_THREAD, sport->irq_fault_name, port);
499 if (ret) {
500 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
501 __func__, sport->irq_fault, ret,
502 pic32_uart_type(port));
503 goto out_f;
504 }
505
506 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
507 pic32_uart_type(port),
508 sport->idx);
509 if (!sport->irq_rx_name) {
510 dev_err(port->dev, "%s: kasprintf err!", __func__);
511 ret = -ENOMEM;
512 goto out_f;
513 }
514 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
515 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
516 IRQF_NO_THREAD, sport->irq_rx_name, port);
517 if (ret) {
518 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
519 __func__, sport->irq_rx, ret,
520 pic32_uart_type(port));
521 goto out_r;
522 }
523
524 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
525 pic32_uart_type(port),
526 sport->idx);
527 if (!sport->irq_tx_name) {
528 dev_err(port->dev, "%s: kasprintf err!", __func__);
529 ret = -ENOMEM;
530 goto out_r;
531 }
532 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
533 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
534 IRQF_NO_THREAD, sport->irq_tx_name, port);
535 if (ret) {
536 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
537 __func__, sport->irq_tx, ret,
538 pic32_uart_type(port));
539 goto out_t;
540 }
541
542 local_irq_save(flags);
543
544 /* set rx interrupt on first receive */
545 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
546 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
547
548 /* set interrupt on empty */
549 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
550 PIC32_UART_STA_UTXISEL1);
551
552 /* enable all interrupts and eanable uart */
553 pic32_uart_en_and_unmask(port);
554
555 local_irq_restore(flags);
556
557 enable_irq(sport->irq_rx);
558
559 return 0;
560
561out_t:
562 free_irq(sport->irq_tx, port);
563 kfree(sport->irq_tx_name);
564out_r:
565 free_irq(sport->irq_rx, port);
566 kfree(sport->irq_rx_name);
567out_f:
568 free_irq(sport->irq_fault, port);
569 kfree(sport->irq_fault_name);
570out_disable_clk:
571 clk_disable_unprepare(sport->clk);
572out_done:
573 return ret;
574}
575
576/* serial core request to flush & disable uart */
577static void pic32_uart_shutdown(struct uart_port *port)
578{
579 struct pic32_sport *sport = to_pic32_sport(port);
580 unsigned long flags;
581
582 /* disable uart */
583 uart_port_lock_irqsave(port, &flags);
584 pic32_uart_dsbl_and_mask(port);
585 uart_port_unlock_irqrestore(port, flags);
586 clk_disable_unprepare(sport->clk);
587
588 /* free all 3 interrupts for this UART */
589 free_irq(sport->irq_fault, port);
590 kfree(sport->irq_fault_name);
591 free_irq(sport->irq_tx, port);
592 kfree(sport->irq_tx_name);
593 free_irq(sport->irq_rx, port);
594 kfree(sport->irq_rx_name);
595}
596
597/* serial core request to change current uart setting */
598static void pic32_uart_set_termios(struct uart_port *port,
599 struct ktermios *new,
600 const struct ktermios *old)
601{
602 struct pic32_sport *sport = to_pic32_sport(port);
603 unsigned int baud;
604 unsigned int quot;
605 unsigned long flags;
606
607 uart_port_lock_irqsave(port, &flags);
608
609 /* disable uart and mask all interrupts while changing speed */
610 pic32_uart_dsbl_and_mask(port);
611
612 /* stop bit options */
613 if (new->c_cflag & CSTOPB)
614 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
615 PIC32_UART_MODE_STSEL);
616 else
617 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
618 PIC32_UART_MODE_STSEL);
619
620 /* parity options */
621 if (new->c_cflag & PARENB) {
622 if (new->c_cflag & PARODD) {
623 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
624 PIC32_UART_MODE_PDSEL1);
625 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
626 PIC32_UART_MODE_PDSEL0);
627 } else {
628 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
629 PIC32_UART_MODE_PDSEL0);
630 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
631 PIC32_UART_MODE_PDSEL1);
632 }
633 } else {
634 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
635 PIC32_UART_MODE_PDSEL1 |
636 PIC32_UART_MODE_PDSEL0);
637 }
638 /* if hw flow ctrl, then the pins must be specified in device tree */
639 if ((new->c_cflag & CRTSCTS) && sport->cts_gpiod) {
640 /* enable hardware flow control */
641 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
642 PIC32_UART_MODE_UEN1);
643 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
644 PIC32_UART_MODE_UEN0);
645 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
646 PIC32_UART_MODE_RTSMD);
647 } else {
648 /* disable hardware flow control */
649 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
650 PIC32_UART_MODE_UEN1);
651 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
652 PIC32_UART_MODE_UEN0);
653 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
654 PIC32_UART_MODE_RTSMD);
655 }
656
657 /* Always 8-bit */
658 new->c_cflag |= CS8;
659
660 /* Mark/Space parity is not supported */
661 new->c_cflag &= ~CMSPAR;
662
663 /* update baud */
664 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
665 quot = uart_get_divisor(port, baud) - 1;
666 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
667 uart_update_timeout(port, new->c_cflag, baud);
668
669 if (tty_termios_baud_rate(new))
670 tty_termios_encode_baud_rate(new, baud, baud);
671
672 /* enable uart */
673 pic32_uart_en_and_unmask(port);
674
675 uart_port_unlock_irqrestore(port, flags);
676}
677
678/* serial core request to claim uart iomem */
679static int pic32_uart_request_port(struct uart_port *port)
680{
681 struct platform_device *pdev = to_platform_device(port->dev);
682 struct resource *res_mem;
683
684 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
685 if (unlikely(!res_mem))
686 return -EINVAL;
687
688 if (!request_mem_region(port->mapbase, resource_size(res_mem),
689 "pic32_uart_mem"))
690 return -EBUSY;
691
692 port->membase = devm_ioremap(port->dev, port->mapbase,
693 resource_size(res_mem));
694 if (!port->membase) {
695 dev_err(port->dev, "Unable to map registers\n");
696 release_mem_region(port->mapbase, resource_size(res_mem));
697 return -ENOMEM;
698 }
699
700 return 0;
701}
702
703/* serial core request to release uart iomem */
704static void pic32_uart_release_port(struct uart_port *port)
705{
706 struct platform_device *pdev = to_platform_device(port->dev);
707 struct resource *res_mem;
708 unsigned int res_size;
709
710 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
711 if (unlikely(!res_mem))
712 return;
713 res_size = resource_size(res_mem);
714
715 release_mem_region(port->mapbase, res_size);
716}
717
718/* serial core request to do any port required auto-configuration */
719static void pic32_uart_config_port(struct uart_port *port, int flags)
720{
721 if (flags & UART_CONFIG_TYPE) {
722 if (pic32_uart_request_port(port))
723 return;
724 port->type = PORT_PIC32;
725 }
726}
727
728/* serial core request to check that port information in serinfo are suitable */
729static int pic32_uart_verify_port(struct uart_port *port,
730 struct serial_struct *serinfo)
731{
732 if (port->type != PORT_PIC32)
733 return -EINVAL;
734 if (port->irq != serinfo->irq)
735 return -EINVAL;
736 if (port->iotype != serinfo->io_type)
737 return -EINVAL;
738 if (port->mapbase != (unsigned long)serinfo->iomem_base)
739 return -EINVAL;
740
741 return 0;
742}
743
744/* serial core callbacks */
745static const struct uart_ops pic32_uart_ops = {
746 .tx_empty = pic32_uart_tx_empty,
747 .get_mctrl = pic32_uart_get_mctrl,
748 .set_mctrl = pic32_uart_set_mctrl,
749 .start_tx = pic32_uart_start_tx,
750 .stop_tx = pic32_uart_stop_tx,
751 .stop_rx = pic32_uart_stop_rx,
752 .break_ctl = pic32_uart_break_ctl,
753 .startup = pic32_uart_startup,
754 .shutdown = pic32_uart_shutdown,
755 .set_termios = pic32_uart_set_termios,
756 .type = pic32_uart_type,
757 .release_port = pic32_uart_release_port,
758 .request_port = pic32_uart_request_port,
759 .config_port = pic32_uart_config_port,
760 .verify_port = pic32_uart_verify_port,
761};
762
763#ifdef CONFIG_SERIAL_PIC32_CONSOLE
764/* output given char */
765static void pic32_console_putchar(struct uart_port *port, unsigned char ch)
766{
767 struct pic32_sport *sport = to_pic32_sport(port);
768
769 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
770 return;
771
772 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
773 return;
774
775 /* wait for tx empty */
776 pic32_wait_deplete_txbuf(sport);
777
778 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
779}
780
781/* console core request to output given string */
782static void pic32_console_write(struct console *co, const char *s,
783 unsigned int count)
784{
785 struct pic32_sport *sport = pic32_sports[co->index];
786
787 /* call uart helper to deal with \r\n */
788 uart_console_write(&sport->port, s, count, pic32_console_putchar);
789}
790
791/* console core request to setup given console, find matching uart
792 * port and setup it.
793 */
794static int pic32_console_setup(struct console *co, char *options)
795{
796 struct pic32_sport *sport;
797 int baud = 115200;
798 int bits = 8;
799 int parity = 'n';
800 int flow = 'n';
801 int ret = 0;
802
803 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
804 return -ENODEV;
805
806 sport = pic32_sports[co->index];
807 if (!sport)
808 return -ENODEV;
809
810 ret = clk_prepare_enable(sport->clk);
811 if (ret)
812 return ret;
813
814 if (options)
815 uart_parse_options(options, &baud, &parity, &bits, &flow);
816
817 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
818}
819
820static struct uart_driver pic32_uart_driver;
821static struct console pic32_console = {
822 .name = PIC32_SDEV_NAME,
823 .write = pic32_console_write,
824 .device = uart_console_device,
825 .setup = pic32_console_setup,
826 .flags = CON_PRINTBUFFER,
827 .index = -1,
828 .data = &pic32_uart_driver,
829};
830#define PIC32_SCONSOLE (&pic32_console)
831
832static int __init pic32_console_init(void)
833{
834 register_console(&pic32_console);
835 return 0;
836}
837console_initcall(pic32_console_init);
838
839/*
840 * Late console initialization.
841 */
842static int __init pic32_late_console_init(void)
843{
844 if (!console_is_registered(&pic32_console))
845 register_console(&pic32_console);
846
847 return 0;
848}
849
850core_initcall(pic32_late_console_init);
851
852#else
853#define PIC32_SCONSOLE NULL
854#endif
855
856static struct uart_driver pic32_uart_driver = {
857 .owner = THIS_MODULE,
858 .driver_name = PIC32_DEV_NAME,
859 .dev_name = PIC32_SDEV_NAME,
860 .nr = PIC32_MAX_UARTS,
861 .cons = PIC32_SCONSOLE,
862};
863
864static int pic32_uart_probe(struct platform_device *pdev)
865{
866 struct device *dev = &pdev->dev;
867 struct device_node *np = dev->of_node;
868 struct pic32_sport *sport;
869 int uart_idx = 0;
870 struct resource *res_mem;
871 struct uart_port *port;
872 int ret;
873
874 uart_idx = of_alias_get_id(np, "serial");
875 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
876 return -EINVAL;
877
878 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
879 if (!res_mem)
880 return -EINVAL;
881
882 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
883 if (!sport)
884 return -ENOMEM;
885
886 sport->idx = uart_idx;
887 sport->irq_fault = irq_of_parse_and_map(np, 0);
888 sport->irq_rx = irq_of_parse_and_map(np, 1);
889 sport->irq_tx = irq_of_parse_and_map(np, 2);
890 sport->clk = devm_clk_get(&pdev->dev, NULL);
891 if (IS_ERR(sport->clk))
892 return PTR_ERR(sport->clk);
893 sport->dev = &pdev->dev;
894
895 /* Hardware flow control: gpios
896 * !Note: Basically, CTS is needed for reading the status.
897 */
898 sport->cts_gpiod = devm_gpiod_get_optional(dev, "cts", GPIOD_IN);
899 if (IS_ERR(sport->cts_gpiod))
900 return dev_err_probe(dev, PTR_ERR(sport->cts_gpiod), "error requesting CTS GPIO\n");
901 gpiod_set_consumer_name(sport->cts_gpiod, "CTS");
902
903 pic32_sports[uart_idx] = sport;
904 port = &sport->port;
905 port->iotype = UPIO_MEM;
906 port->mapbase = res_mem->start;
907 port->ops = &pic32_uart_ops;
908 port->flags = UPF_BOOT_AUTOCONF;
909 port->dev = &pdev->dev;
910 port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
911 port->uartclk = clk_get_rate(sport->clk);
912 port->line = uart_idx;
913
914 ret = uart_add_one_port(&pic32_uart_driver, port);
915 if (ret) {
916 port->membase = NULL;
917 dev_err(port->dev, "%s: uart add port error!\n", __func__);
918 goto err;
919 }
920
921#ifdef CONFIG_SERIAL_PIC32_CONSOLE
922 if (uart_console_registered(port)) {
923 /* The peripheral clock has been enabled by console_setup,
924 * so disable it till the port is used.
925 */
926 clk_disable_unprepare(sport->clk);
927 }
928#endif
929
930 platform_set_drvdata(pdev, port);
931
932 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
933 __func__, uart_idx);
934
935 return 0;
936err:
937 /* automatic unroll of sport and gpios */
938 return ret;
939}
940
941static void pic32_uart_remove(struct platform_device *pdev)
942{
943 struct uart_port *port = platform_get_drvdata(pdev);
944 struct pic32_sport *sport = to_pic32_sport(port);
945
946 uart_remove_one_port(&pic32_uart_driver, port);
947 clk_disable_unprepare(sport->clk);
948 platform_set_drvdata(pdev, NULL);
949 pic32_sports[sport->idx] = NULL;
950}
951
952static const struct of_device_id pic32_serial_dt_ids[] = {
953 { .compatible = "microchip,pic32mzda-uart" },
954 { /* sentinel */ }
955};
956MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
957
958static struct platform_driver pic32_uart_platform_driver = {
959 .probe = pic32_uart_probe,
960 .remove_new = pic32_uart_remove,
961 .driver = {
962 .name = PIC32_DEV_NAME,
963 .of_match_table = of_match_ptr(pic32_serial_dt_ids),
964 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32),
965 },
966};
967
968static int __init pic32_uart_init(void)
969{
970 int ret;
971
972 ret = uart_register_driver(&pic32_uart_driver);
973 if (ret) {
974 pr_err("failed to register %s:%d\n",
975 pic32_uart_driver.driver_name, ret);
976 return ret;
977 }
978
979 ret = platform_driver_register(&pic32_uart_platform_driver);
980 if (ret) {
981 pr_err("fail to register pic32 uart\n");
982 uart_unregister_driver(&pic32_uart_driver);
983 }
984
985 return ret;
986}
987arch_initcall(pic32_uart_init);
988
989static void __exit pic32_uart_exit(void)
990{
991#ifdef CONFIG_SERIAL_PIC32_CONSOLE
992 unregister_console(&pic32_console);
993#endif
994 platform_driver_unregister(&pic32_uart_platform_driver);
995 uart_unregister_driver(&pic32_uart_driver);
996}
997module_exit(pic32_uart_exit);
998
999MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
1000MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
1001MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PIC32 Integrated Serial Driver.
4 *
5 * Copyright (C) 2015 Microchip Technology, Inc.
6 *
7 * Authors:
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_irq.h>
16#include <linux/of_gpio.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/console.h>
21#include <linux/clk.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
24#include <linux/serial_core.h>
25#include <linux/delay.h>
26
27#include <asm/mach-pic32/pic32.h>
28
29/* UART name and device definitions */
30#define PIC32_DEV_NAME "pic32-uart"
31#define PIC32_MAX_UARTS 6
32#define PIC32_SDEV_NAME "ttyPIC"
33
34#define PIC32_UART_DFLT_BRATE 9600
35#define PIC32_UART_TX_FIFO_DEPTH 8
36#define PIC32_UART_RX_FIFO_DEPTH 8
37
38#define PIC32_UART_MODE 0x00
39#define PIC32_UART_STA 0x10
40#define PIC32_UART_TX 0x20
41#define PIC32_UART_RX 0x30
42#define PIC32_UART_BRG 0x40
43
44/* struct pic32_sport - pic32 serial port descriptor
45 * @port: uart port descriptor
46 * @idx: port index
47 * @irq_fault: virtual fault interrupt number
48 * @irq_fault_name: irq fault name
49 * @irq_rx: virtual rx interrupt number
50 * @irq_rx_name: irq rx name
51 * @irq_tx: virtual tx interrupt number
52 * @irq_tx_name: irq tx name
53 * @cts_gpiod: clear to send GPIO
54 * @dev: device descriptor
55 **/
56struct pic32_sport {
57 struct uart_port port;
58 int idx;
59
60 int irq_fault;
61 const char *irq_fault_name;
62 int irq_rx;
63 const char *irq_rx_name;
64 int irq_tx;
65 const char *irq_tx_name;
66 bool enable_tx_irq;
67
68 struct gpio_desc *cts_gpiod;
69
70 struct clk *clk;
71
72 struct device *dev;
73};
74
75static inline struct pic32_sport *to_pic32_sport(struct uart_port *port)
76{
77 return container_of(port, struct pic32_sport, port);
78}
79
80static inline void pic32_uart_writel(struct pic32_sport *sport,
81 u32 reg, u32 val)
82{
83 __raw_writel(val, sport->port.membase + reg);
84}
85
86static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
87{
88 return __raw_readl(sport->port.membase + reg);
89}
90
91/* pic32 uart mode register bits */
92#define PIC32_UART_MODE_ON BIT(15)
93#define PIC32_UART_MODE_FRZ BIT(14)
94#define PIC32_UART_MODE_SIDL BIT(13)
95#define PIC32_UART_MODE_IREN BIT(12)
96#define PIC32_UART_MODE_RTSMD BIT(11)
97#define PIC32_UART_MODE_RESV1 BIT(10)
98#define PIC32_UART_MODE_UEN1 BIT(9)
99#define PIC32_UART_MODE_UEN0 BIT(8)
100#define PIC32_UART_MODE_WAKE BIT(7)
101#define PIC32_UART_MODE_LPBK BIT(6)
102#define PIC32_UART_MODE_ABAUD BIT(5)
103#define PIC32_UART_MODE_RXINV BIT(4)
104#define PIC32_UART_MODE_BRGH BIT(3)
105#define PIC32_UART_MODE_PDSEL1 BIT(2)
106#define PIC32_UART_MODE_PDSEL0 BIT(1)
107#define PIC32_UART_MODE_STSEL BIT(0)
108
109/* pic32 uart status register bits */
110#define PIC32_UART_STA_UTXISEL1 BIT(15)
111#define PIC32_UART_STA_UTXISEL0 BIT(14)
112#define PIC32_UART_STA_UTXINV BIT(13)
113#define PIC32_UART_STA_URXEN BIT(12)
114#define PIC32_UART_STA_UTXBRK BIT(11)
115#define PIC32_UART_STA_UTXEN BIT(10)
116#define PIC32_UART_STA_UTXBF BIT(9)
117#define PIC32_UART_STA_TRMT BIT(8)
118#define PIC32_UART_STA_URXISEL1 BIT(7)
119#define PIC32_UART_STA_URXISEL0 BIT(6)
120#define PIC32_UART_STA_ADDEN BIT(5)
121#define PIC32_UART_STA_RIDLE BIT(4)
122#define PIC32_UART_STA_PERR BIT(3)
123#define PIC32_UART_STA_FERR BIT(2)
124#define PIC32_UART_STA_OERR BIT(1)
125#define PIC32_UART_STA_URXDA BIT(0)
126
127/* pic32_sport pointer for console use */
128static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
129
130static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
131{
132 /* wait for tx empty, otherwise chars will be lost or corrupted */
133 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
134 udelay(1);
135}
136
137/* serial core request to check if uart tx buffer is empty */
138static unsigned int pic32_uart_tx_empty(struct uart_port *port)
139{
140 struct pic32_sport *sport = to_pic32_sport(port);
141 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
142
143 return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
144}
145
146/* serial core request to set UART outputs */
147static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
148{
149 struct pic32_sport *sport = to_pic32_sport(port);
150
151 /* set loopback mode */
152 if (mctrl & TIOCM_LOOP)
153 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
154 PIC32_UART_MODE_LPBK);
155 else
156 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
157 PIC32_UART_MODE_LPBK);
158}
159
160/* serial core request to return the state of misc UART input pins */
161static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
162{
163 struct pic32_sport *sport = to_pic32_sport(port);
164 unsigned int mctrl = 0;
165
166 /* get the state of CTS input pin for this port */
167 if (!sport->cts_gpiod)
168 mctrl |= TIOCM_CTS;
169 else if (gpiod_get_value(sport->cts_gpiod))
170 mctrl |= TIOCM_CTS;
171
172 /* DSR and CD are not supported in PIC32, so return 1
173 * RI is not supported in PIC32, so return 0
174 */
175 mctrl |= TIOCM_CD;
176 mctrl |= TIOCM_DSR;
177
178 return mctrl;
179}
180
181/* stop tx and start tx are not called in pairs, therefore a flag indicates
182 * the status of irq to control the irq-depth.
183 */
184static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
185{
186 if (en && !sport->enable_tx_irq) {
187 enable_irq(sport->irq_tx);
188 sport->enable_tx_irq = true;
189 } else if (!en && sport->enable_tx_irq) {
190 /* use disable_irq_nosync() and not disable_irq() to avoid self
191 * imposed deadlock by not waiting for irq handler to end,
192 * since this callback is called from interrupt context.
193 */
194 disable_irq_nosync(sport->irq_tx);
195 sport->enable_tx_irq = false;
196 }
197}
198
199/* serial core request to disable tx ASAP (used for flow control) */
200static void pic32_uart_stop_tx(struct uart_port *port)
201{
202 struct pic32_sport *sport = to_pic32_sport(port);
203
204 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
205 return;
206
207 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
208 return;
209
210 /* wait for tx empty */
211 pic32_wait_deplete_txbuf(sport);
212
213 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
214 PIC32_UART_STA_UTXEN);
215 pic32_uart_irqtxen(sport, 0);
216}
217
218/* serial core request to (re)enable tx */
219static void pic32_uart_start_tx(struct uart_port *port)
220{
221 struct pic32_sport *sport = to_pic32_sport(port);
222
223 pic32_uart_irqtxen(sport, 1);
224 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
225 PIC32_UART_STA_UTXEN);
226}
227
228/* serial core request to stop rx, called before port shutdown */
229static void pic32_uart_stop_rx(struct uart_port *port)
230{
231 struct pic32_sport *sport = to_pic32_sport(port);
232
233 /* disable rx interrupts */
234 disable_irq(sport->irq_rx);
235
236 /* receiver Enable bit OFF */
237 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
238 PIC32_UART_STA_URXEN);
239}
240
241/* serial core request to start/stop emitting break char */
242static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
243{
244 struct pic32_sport *sport = to_pic32_sport(port);
245 unsigned long flags;
246
247 spin_lock_irqsave(&port->lock, flags);
248
249 if (ctl)
250 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
251 PIC32_UART_STA_UTXBRK);
252 else
253 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
254 PIC32_UART_STA_UTXBRK);
255
256 spin_unlock_irqrestore(&port->lock, flags);
257}
258
259/* get port type in string format */
260static const char *pic32_uart_type(struct uart_port *port)
261{
262 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
263}
264
265/* read all chars in rx fifo and send them to core */
266static void pic32_uart_do_rx(struct uart_port *port)
267{
268 struct pic32_sport *sport = to_pic32_sport(port);
269 struct tty_port *tty;
270 unsigned int max_count;
271
272 /* limit number of char read in interrupt, should not be
273 * higher than fifo size anyway since we're much faster than
274 * serial port
275 */
276 max_count = PIC32_UART_RX_FIFO_DEPTH;
277
278 spin_lock(&port->lock);
279
280 tty = &port->state->port;
281
282 do {
283 u32 sta_reg, c;
284 char flag;
285
286 /* get overrun/fifo empty information from status register */
287 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
288 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
289
290 /* fifo reset is required to clear interrupt */
291 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
292 PIC32_UART_STA_OERR);
293
294 port->icount.overrun++;
295 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
296 }
297
298 /* Can at least one more character can be read? */
299 if (!(sta_reg & PIC32_UART_STA_URXDA))
300 break;
301
302 /* read the character and increment the rx counter */
303 c = pic32_uart_readl(sport, PIC32_UART_RX);
304
305 port->icount.rx++;
306 flag = TTY_NORMAL;
307 c &= 0xff;
308
309 if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
310 (sta_reg & PIC32_UART_STA_FERR))) {
311
312 /* do stats first */
313 if (sta_reg & PIC32_UART_STA_PERR)
314 port->icount.parity++;
315 if (sta_reg & PIC32_UART_STA_FERR)
316 port->icount.frame++;
317
318 /* update flag wrt read_status_mask */
319 sta_reg &= port->read_status_mask;
320
321 if (sta_reg & PIC32_UART_STA_FERR)
322 flag = TTY_FRAME;
323 if (sta_reg & PIC32_UART_STA_PERR)
324 flag = TTY_PARITY;
325 }
326
327 if (uart_handle_sysrq_char(port, c))
328 continue;
329
330 if ((sta_reg & port->ignore_status_mask) == 0)
331 tty_insert_flip_char(tty, c, flag);
332
333 } while (--max_count);
334
335 spin_unlock(&port->lock);
336
337 tty_flip_buffer_push(tty);
338}
339
340/* fill tx fifo with chars to send, stop when fifo is about to be full
341 * or when all chars have been sent.
342 */
343static void pic32_uart_do_tx(struct uart_port *port)
344{
345 struct pic32_sport *sport = to_pic32_sport(port);
346 struct circ_buf *xmit = &port->state->xmit;
347 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
348
349 if (port->x_char) {
350 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
351 port->icount.tx++;
352 port->x_char = 0;
353 return;
354 }
355
356 if (uart_tx_stopped(port)) {
357 pic32_uart_stop_tx(port);
358 return;
359 }
360
361 if (uart_circ_empty(xmit))
362 goto txq_empty;
363
364 /* keep stuffing chars into uart tx buffer
365 * 1) until uart fifo is full
366 * or
367 * 2) until the circ buffer is empty
368 * (all chars have been sent)
369 * or
370 * 3) until the max count is reached
371 * (prevents lingering here for too long in certain cases)
372 */
373 while (!(PIC32_UART_STA_UTXBF &
374 pic32_uart_readl(sport, PIC32_UART_STA))) {
375 unsigned int c = xmit->buf[xmit->tail];
376
377 pic32_uart_writel(sport, PIC32_UART_TX, c);
378
379 uart_xmit_advance(port, 1);
380 if (uart_circ_empty(xmit))
381 break;
382 if (--max_count == 0)
383 break;
384 }
385
386 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
387 uart_write_wakeup(port);
388
389 if (uart_circ_empty(xmit))
390 goto txq_empty;
391
392 return;
393
394txq_empty:
395 pic32_uart_irqtxen(sport, 0);
396}
397
398/* RX interrupt handler */
399static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
400{
401 struct uart_port *port = dev_id;
402
403 pic32_uart_do_rx(port);
404
405 return IRQ_HANDLED;
406}
407
408/* TX interrupt handler */
409static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
410{
411 struct uart_port *port = dev_id;
412 unsigned long flags;
413
414 spin_lock_irqsave(&port->lock, flags);
415 pic32_uart_do_tx(port);
416 spin_unlock_irqrestore(&port->lock, flags);
417
418 return IRQ_HANDLED;
419}
420
421/* FAULT interrupt handler */
422static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
423{
424 /* do nothing: pic32_uart_do_rx() handles faults. */
425 return IRQ_HANDLED;
426}
427
428/* enable rx & tx operation on uart */
429static void pic32_uart_en_and_unmask(struct uart_port *port)
430{
431 struct pic32_sport *sport = to_pic32_sport(port);
432
433 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
434 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
435 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
436 PIC32_UART_MODE_ON);
437}
438
439/* disable rx & tx operation on uart */
440static void pic32_uart_dsbl_and_mask(struct uart_port *port)
441{
442 struct pic32_sport *sport = to_pic32_sport(port);
443
444 /* wait for tx empty, otherwise chars will be lost or corrupted */
445 pic32_wait_deplete_txbuf(sport);
446
447 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
448 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
449 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
450 PIC32_UART_MODE_ON);
451}
452
453/* serial core request to initialize uart and start rx operation */
454static int pic32_uart_startup(struct uart_port *port)
455{
456 struct pic32_sport *sport = to_pic32_sport(port);
457 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
458 unsigned long flags;
459 int ret;
460
461 local_irq_save(flags);
462
463 ret = clk_prepare_enable(sport->clk);
464 if (ret) {
465 local_irq_restore(flags);
466 goto out_done;
467 }
468
469 /* clear status and mode registers */
470 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
471 pic32_uart_writel(sport, PIC32_UART_STA, 0);
472
473 /* disable uart and mask all interrupts */
474 pic32_uart_dsbl_and_mask(port);
475
476 /* set default baud */
477 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
478
479 local_irq_restore(flags);
480
481 /* Each UART of a PIC32 has three interrupts therefore,
482 * we setup driver to register the 3 irqs for the device.
483 *
484 * For each irq request_irq() is called with interrupt disabled.
485 * And the irq is enabled as soon as we are ready to handle them.
486 */
487 sport->enable_tx_irq = false;
488
489 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
490 pic32_uart_type(port),
491 sport->idx);
492 if (!sport->irq_fault_name) {
493 dev_err(port->dev, "%s: kasprintf err!", __func__);
494 ret = -ENOMEM;
495 goto out_disable_clk;
496 }
497 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
498 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
499 IRQF_NO_THREAD, sport->irq_fault_name, port);
500 if (ret) {
501 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
502 __func__, sport->irq_fault, ret,
503 pic32_uart_type(port));
504 goto out_f;
505 }
506
507 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
508 pic32_uart_type(port),
509 sport->idx);
510 if (!sport->irq_rx_name) {
511 dev_err(port->dev, "%s: kasprintf err!", __func__);
512 ret = -ENOMEM;
513 goto out_f;
514 }
515 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
516 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
517 IRQF_NO_THREAD, sport->irq_rx_name, port);
518 if (ret) {
519 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
520 __func__, sport->irq_rx, ret,
521 pic32_uart_type(port));
522 goto out_r;
523 }
524
525 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
526 pic32_uart_type(port),
527 sport->idx);
528 if (!sport->irq_tx_name) {
529 dev_err(port->dev, "%s: kasprintf err!", __func__);
530 ret = -ENOMEM;
531 goto out_r;
532 }
533 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
534 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
535 IRQF_NO_THREAD, sport->irq_tx_name, port);
536 if (ret) {
537 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
538 __func__, sport->irq_tx, ret,
539 pic32_uart_type(port));
540 goto out_t;
541 }
542
543 local_irq_save(flags);
544
545 /* set rx interrupt on first receive */
546 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
547 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
548
549 /* set interrupt on empty */
550 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
551 PIC32_UART_STA_UTXISEL1);
552
553 /* enable all interrupts and eanable uart */
554 pic32_uart_en_and_unmask(port);
555
556 local_irq_restore(flags);
557
558 enable_irq(sport->irq_rx);
559
560 return 0;
561
562out_t:
563 free_irq(sport->irq_tx, port);
564 kfree(sport->irq_tx_name);
565out_r:
566 free_irq(sport->irq_rx, port);
567 kfree(sport->irq_rx_name);
568out_f:
569 free_irq(sport->irq_fault, port);
570 kfree(sport->irq_fault_name);
571out_disable_clk:
572 clk_disable_unprepare(sport->clk);
573out_done:
574 return ret;
575}
576
577/* serial core request to flush & disable uart */
578static void pic32_uart_shutdown(struct uart_port *port)
579{
580 struct pic32_sport *sport = to_pic32_sport(port);
581 unsigned long flags;
582
583 /* disable uart */
584 spin_lock_irqsave(&port->lock, flags);
585 pic32_uart_dsbl_and_mask(port);
586 spin_unlock_irqrestore(&port->lock, flags);
587 clk_disable_unprepare(sport->clk);
588
589 /* free all 3 interrupts for this UART */
590 free_irq(sport->irq_fault, port);
591 kfree(sport->irq_fault_name);
592 free_irq(sport->irq_tx, port);
593 kfree(sport->irq_tx_name);
594 free_irq(sport->irq_rx, port);
595 kfree(sport->irq_rx_name);
596}
597
598/* serial core request to change current uart setting */
599static void pic32_uart_set_termios(struct uart_port *port,
600 struct ktermios *new,
601 const struct ktermios *old)
602{
603 struct pic32_sport *sport = to_pic32_sport(port);
604 unsigned int baud;
605 unsigned int quot;
606 unsigned long flags;
607
608 spin_lock_irqsave(&port->lock, flags);
609
610 /* disable uart and mask all interrupts while changing speed */
611 pic32_uart_dsbl_and_mask(port);
612
613 /* stop bit options */
614 if (new->c_cflag & CSTOPB)
615 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
616 PIC32_UART_MODE_STSEL);
617 else
618 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
619 PIC32_UART_MODE_STSEL);
620
621 /* parity options */
622 if (new->c_cflag & PARENB) {
623 if (new->c_cflag & PARODD) {
624 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
625 PIC32_UART_MODE_PDSEL1);
626 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
627 PIC32_UART_MODE_PDSEL0);
628 } else {
629 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
630 PIC32_UART_MODE_PDSEL0);
631 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
632 PIC32_UART_MODE_PDSEL1);
633 }
634 } else {
635 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
636 PIC32_UART_MODE_PDSEL1 |
637 PIC32_UART_MODE_PDSEL0);
638 }
639 /* if hw flow ctrl, then the pins must be specified in device tree */
640 if ((new->c_cflag & CRTSCTS) && sport->cts_gpiod) {
641 /* enable hardware flow control */
642 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
643 PIC32_UART_MODE_UEN1);
644 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
645 PIC32_UART_MODE_UEN0);
646 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
647 PIC32_UART_MODE_RTSMD);
648 } else {
649 /* disable hardware flow control */
650 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
651 PIC32_UART_MODE_UEN1);
652 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
653 PIC32_UART_MODE_UEN0);
654 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
655 PIC32_UART_MODE_RTSMD);
656 }
657
658 /* Always 8-bit */
659 new->c_cflag |= CS8;
660
661 /* Mark/Space parity is not supported */
662 new->c_cflag &= ~CMSPAR;
663
664 /* update baud */
665 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
666 quot = uart_get_divisor(port, baud) - 1;
667 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
668 uart_update_timeout(port, new->c_cflag, baud);
669
670 if (tty_termios_baud_rate(new))
671 tty_termios_encode_baud_rate(new, baud, baud);
672
673 /* enable uart */
674 pic32_uart_en_and_unmask(port);
675
676 spin_unlock_irqrestore(&port->lock, flags);
677}
678
679/* serial core request to claim uart iomem */
680static int pic32_uart_request_port(struct uart_port *port)
681{
682 struct platform_device *pdev = to_platform_device(port->dev);
683 struct resource *res_mem;
684
685 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
686 if (unlikely(!res_mem))
687 return -EINVAL;
688
689 if (!request_mem_region(port->mapbase, resource_size(res_mem),
690 "pic32_uart_mem"))
691 return -EBUSY;
692
693 port->membase = devm_ioremap(port->dev, port->mapbase,
694 resource_size(res_mem));
695 if (!port->membase) {
696 dev_err(port->dev, "Unable to map registers\n");
697 release_mem_region(port->mapbase, resource_size(res_mem));
698 return -ENOMEM;
699 }
700
701 return 0;
702}
703
704/* serial core request to release uart iomem */
705static void pic32_uart_release_port(struct uart_port *port)
706{
707 struct platform_device *pdev = to_platform_device(port->dev);
708 struct resource *res_mem;
709 unsigned int res_size;
710
711 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
712 if (unlikely(!res_mem))
713 return;
714 res_size = resource_size(res_mem);
715
716 release_mem_region(port->mapbase, res_size);
717}
718
719/* serial core request to do any port required auto-configuration */
720static void pic32_uart_config_port(struct uart_port *port, int flags)
721{
722 if (flags & UART_CONFIG_TYPE) {
723 if (pic32_uart_request_port(port))
724 return;
725 port->type = PORT_PIC32;
726 }
727}
728
729/* serial core request to check that port information in serinfo are suitable */
730static int pic32_uart_verify_port(struct uart_port *port,
731 struct serial_struct *serinfo)
732{
733 if (port->type != PORT_PIC32)
734 return -EINVAL;
735 if (port->irq != serinfo->irq)
736 return -EINVAL;
737 if (port->iotype != serinfo->io_type)
738 return -EINVAL;
739 if (port->mapbase != (unsigned long)serinfo->iomem_base)
740 return -EINVAL;
741
742 return 0;
743}
744
745/* serial core callbacks */
746static const struct uart_ops pic32_uart_ops = {
747 .tx_empty = pic32_uart_tx_empty,
748 .get_mctrl = pic32_uart_get_mctrl,
749 .set_mctrl = pic32_uart_set_mctrl,
750 .start_tx = pic32_uart_start_tx,
751 .stop_tx = pic32_uart_stop_tx,
752 .stop_rx = pic32_uart_stop_rx,
753 .break_ctl = pic32_uart_break_ctl,
754 .startup = pic32_uart_startup,
755 .shutdown = pic32_uart_shutdown,
756 .set_termios = pic32_uart_set_termios,
757 .type = pic32_uart_type,
758 .release_port = pic32_uart_release_port,
759 .request_port = pic32_uart_request_port,
760 .config_port = pic32_uart_config_port,
761 .verify_port = pic32_uart_verify_port,
762};
763
764#ifdef CONFIG_SERIAL_PIC32_CONSOLE
765/* output given char */
766static void pic32_console_putchar(struct uart_port *port, unsigned char ch)
767{
768 struct pic32_sport *sport = to_pic32_sport(port);
769
770 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
771 return;
772
773 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
774 return;
775
776 /* wait for tx empty */
777 pic32_wait_deplete_txbuf(sport);
778
779 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
780}
781
782/* console core request to output given string */
783static void pic32_console_write(struct console *co, const char *s,
784 unsigned int count)
785{
786 struct pic32_sport *sport = pic32_sports[co->index];
787
788 /* call uart helper to deal with \r\n */
789 uart_console_write(&sport->port, s, count, pic32_console_putchar);
790}
791
792/* console core request to setup given console, find matching uart
793 * port and setup it.
794 */
795static int pic32_console_setup(struct console *co, char *options)
796{
797 struct pic32_sport *sport;
798 int baud = 115200;
799 int bits = 8;
800 int parity = 'n';
801 int flow = 'n';
802 int ret = 0;
803
804 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
805 return -ENODEV;
806
807 sport = pic32_sports[co->index];
808 if (!sport)
809 return -ENODEV;
810
811 ret = clk_prepare_enable(sport->clk);
812 if (ret)
813 return ret;
814
815 if (options)
816 uart_parse_options(options, &baud, &parity, &bits, &flow);
817
818 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
819}
820
821static struct uart_driver pic32_uart_driver;
822static struct console pic32_console = {
823 .name = PIC32_SDEV_NAME,
824 .write = pic32_console_write,
825 .device = uart_console_device,
826 .setup = pic32_console_setup,
827 .flags = CON_PRINTBUFFER,
828 .index = -1,
829 .data = &pic32_uart_driver,
830};
831#define PIC32_SCONSOLE (&pic32_console)
832
833static int __init pic32_console_init(void)
834{
835 register_console(&pic32_console);
836 return 0;
837}
838console_initcall(pic32_console_init);
839
840/*
841 * Late console initialization.
842 */
843static int __init pic32_late_console_init(void)
844{
845 if (!console_is_registered(&pic32_console))
846 register_console(&pic32_console);
847
848 return 0;
849}
850
851core_initcall(pic32_late_console_init);
852
853#else
854#define PIC32_SCONSOLE NULL
855#endif
856
857static struct uart_driver pic32_uart_driver = {
858 .owner = THIS_MODULE,
859 .driver_name = PIC32_DEV_NAME,
860 .dev_name = PIC32_SDEV_NAME,
861 .nr = PIC32_MAX_UARTS,
862 .cons = PIC32_SCONSOLE,
863};
864
865static int pic32_uart_probe(struct platform_device *pdev)
866{
867 struct device *dev = &pdev->dev;
868 struct device_node *np = dev->of_node;
869 struct pic32_sport *sport;
870 int uart_idx = 0;
871 struct resource *res_mem;
872 struct uart_port *port;
873 int ret;
874
875 uart_idx = of_alias_get_id(np, "serial");
876 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
877 return -EINVAL;
878
879 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
880 if (!res_mem)
881 return -EINVAL;
882
883 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
884 if (!sport)
885 return -ENOMEM;
886
887 sport->idx = uart_idx;
888 sport->irq_fault = irq_of_parse_and_map(np, 0);
889 sport->irq_rx = irq_of_parse_and_map(np, 1);
890 sport->irq_tx = irq_of_parse_and_map(np, 2);
891 sport->clk = devm_clk_get(&pdev->dev, NULL);
892 sport->dev = &pdev->dev;
893
894 /* Hardware flow control: gpios
895 * !Note: Basically, CTS is needed for reading the status.
896 */
897 sport->cts_gpiod = devm_gpiod_get_optional(dev, "cts", GPIOD_IN);
898 if (IS_ERR(sport->cts_gpiod))
899 return dev_err_probe(dev, PTR_ERR(sport->cts_gpiod), "error requesting CTS GPIO\n");
900 gpiod_set_consumer_name(sport->cts_gpiod, "CTS");
901
902 pic32_sports[uart_idx] = sport;
903 port = &sport->port;
904 port->iotype = UPIO_MEM;
905 port->mapbase = res_mem->start;
906 port->ops = &pic32_uart_ops;
907 port->flags = UPF_BOOT_AUTOCONF;
908 port->dev = &pdev->dev;
909 port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
910 port->uartclk = clk_get_rate(sport->clk);
911 port->line = uart_idx;
912
913 ret = uart_add_one_port(&pic32_uart_driver, port);
914 if (ret) {
915 port->membase = NULL;
916 dev_err(port->dev, "%s: uart add port error!\n", __func__);
917 goto err;
918 }
919
920#ifdef CONFIG_SERIAL_PIC32_CONSOLE
921 if (uart_console_registered(port)) {
922 /* The peripheral clock has been enabled by console_setup,
923 * so disable it till the port is used.
924 */
925 clk_disable_unprepare(sport->clk);
926 }
927#endif
928
929 platform_set_drvdata(pdev, port);
930
931 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
932 __func__, uart_idx);
933
934 return 0;
935err:
936 /* automatic unroll of sport and gpios */
937 return ret;
938}
939
940static int pic32_uart_remove(struct platform_device *pdev)
941{
942 struct uart_port *port = platform_get_drvdata(pdev);
943 struct pic32_sport *sport = to_pic32_sport(port);
944
945 uart_remove_one_port(&pic32_uart_driver, port);
946 clk_disable_unprepare(sport->clk);
947 platform_set_drvdata(pdev, NULL);
948 pic32_sports[sport->idx] = NULL;
949
950 /* automatic unroll of sport and gpios */
951 return 0;
952}
953
954static const struct of_device_id pic32_serial_dt_ids[] = {
955 { .compatible = "microchip,pic32mzda-uart" },
956 { /* sentinel */ }
957};
958MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
959
960static struct platform_driver pic32_uart_platform_driver = {
961 .probe = pic32_uart_probe,
962 .remove = pic32_uart_remove,
963 .driver = {
964 .name = PIC32_DEV_NAME,
965 .of_match_table = of_match_ptr(pic32_serial_dt_ids),
966 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_PIC32),
967 },
968};
969
970static int __init pic32_uart_init(void)
971{
972 int ret;
973
974 ret = uart_register_driver(&pic32_uart_driver);
975 if (ret) {
976 pr_err("failed to register %s:%d\n",
977 pic32_uart_driver.driver_name, ret);
978 return ret;
979 }
980
981 ret = platform_driver_register(&pic32_uart_platform_driver);
982 if (ret) {
983 pr_err("fail to register pic32 uart\n");
984 uart_unregister_driver(&pic32_uart_driver);
985 }
986
987 return ret;
988}
989arch_initcall(pic32_uart_init);
990
991static void __exit pic32_uart_exit(void)
992{
993#ifdef CONFIG_SERIAL_PIC32_CONSOLE
994 unregister_console(&pic32_console);
995#endif
996 platform_driver_unregister(&pic32_uart_platform_driver);
997 uart_unregister_driver(&pic32_uart_driver);
998}
999module_exit(pic32_uart_exit);
1000
1001MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
1002MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
1003MODULE_LICENSE("GPL v2");