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1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
6 */
7
8#ifndef _PCI_H_
9#define _PCI_H_
10
11#include <linux/interrupt.h>
12#include <linux/mutex.h>
13
14#include "hw.h"
15#include "ce.h"
16#include "ahb.h"
17
18/*
19 * maximum number of bytes that can be
20 * handled atomically by DiagRead/DiagWrite
21 */
22#define DIAG_TRANSFER_LIMIT 2048
23
24struct bmi_xfer {
25 bool tx_done;
26 bool rx_done;
27 bool wait_for_resp;
28 u32 resp_len;
29};
30
31/*
32 * PCI-specific Target state
33 *
34 * NOTE: Structure is shared between Host software and Target firmware!
35 *
36 * Much of this may be of interest to the Host so
37 * HOST_INTEREST->hi_interconnect_state points here
38 * (and all members are 32-bit quantities in order to
39 * facilitate Host access). In particular, Host software is
40 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
41 */
42struct pcie_state {
43 /* Pipe configuration Target address */
44 /* NB: ce_pipe_config[CE_COUNT] */
45 u32 pipe_cfg_addr;
46
47 /* Service to pipe map Target address */
48 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
49 u32 svc_to_pipe_map;
50
51 /* number of MSI interrupts requested */
52 u32 msi_requested;
53
54 /* number of MSI interrupts granted */
55 u32 msi_granted;
56
57 /* Message Signalled Interrupt address */
58 u32 msi_addr;
59
60 /* Base data */
61 u32 msi_data;
62
63 /*
64 * Data for firmware interrupt;
65 * MSI data for other interrupts are
66 * in various SoC registers
67 */
68 u32 msi_fw_intr_data;
69
70 /* PCIE_PWR_METHOD_* */
71 u32 power_mgmt_method;
72
73 /* PCIE_CONFIG_FLAG_* */
74 u32 config_flags;
75};
76
77/* PCIE_CONFIG_FLAG definitions */
78#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
79
80/* Per-pipe state. */
81struct ath10k_pci_pipe {
82 /* Handle of underlying Copy Engine */
83 struct ath10k_ce_pipe *ce_hdl;
84
85 /* Our pipe number; facilitates use of pipe_info ptrs. */
86 u8 pipe_num;
87
88 /* Convenience back pointer to hif_ce_state. */
89 struct ath10k *hif_ce_state;
90
91 size_t buf_sz;
92
93 /* protects compl_free and num_send_allowed */
94 spinlock_t pipe_lock;
95};
96
97struct ath10k_pci_supp_chip {
98 u32 dev_id;
99 u32 rev_id;
100};
101
102enum ath10k_pci_irq_mode {
103 ATH10K_PCI_IRQ_AUTO = 0,
104 ATH10K_PCI_IRQ_LEGACY = 1,
105 ATH10K_PCI_IRQ_MSI = 2,
106};
107
108struct ath10k_pci {
109 struct pci_dev *pdev;
110 struct device *dev;
111 struct ath10k *ar;
112 void __iomem *mem;
113 size_t mem_len;
114
115 /* Operating interrupt mode */
116 enum ath10k_pci_irq_mode oper_irq_mode;
117
118 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
119
120 /* Copy Engine used for Diagnostic Accesses */
121 struct ath10k_ce_pipe *ce_diag;
122 /* For protecting ce_diag */
123 struct mutex ce_diag_mutex;
124
125 struct work_struct dump_work;
126
127 struct ath10k_ce ce;
128 struct timer_list rx_post_retry;
129
130 /* Due to HW quirks it is recommended to disable ASPM during device
131 * bootup. To do that the original PCI-E Link Control is stored before
132 * device bootup is executed and re-programmed later.
133 */
134 u16 link_ctl;
135
136 /* Protects ps_awake and ps_wake_refcount */
137 spinlock_t ps_lock;
138
139 /* The device has a special powersave-oriented register. When device is
140 * considered asleep it drains less power and driver is forbidden from
141 * accessing most MMIO registers. If host were to access them without
142 * waking up the device might scribble over host memory or return
143 * 0xdeadbeef readouts.
144 */
145 unsigned long ps_wake_refcount;
146
147 /* Waking up takes some time (up to 2ms in some cases) so it can be bad
148 * for latency. To mitigate this the device isn't immediately allowed
149 * to sleep after all references are undone - instead there's a grace
150 * period after which the powersave register is updated unless some
151 * activity to/from device happened in the meantime.
152 *
153 * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
154 */
155 struct timer_list ps_timer;
156
157 /* MMIO registers are used to communicate with the device. With
158 * intensive traffic accessing powersave register would be a bit
159 * wasteful overhead and would needlessly stall CPU. It is far more
160 * efficient to rely on a variable in RAM and update it only upon
161 * powersave register state changes.
162 */
163 bool ps_awake;
164
165 /* pci power save, disable for QCA988X and QCA99X0.
166 * Writing 'false' to this variable avoids frequent locking
167 * on MMIO read/write.
168 */
169 bool pci_ps;
170
171 /* Chip specific pci reset routine used to do a safe reset */
172 int (*pci_soft_reset)(struct ath10k *ar);
173
174 /* Chip specific pci full reset function */
175 int (*pci_hard_reset)(struct ath10k *ar);
176
177 /* chip specific methods for converting target CPU virtual address
178 * space to CE address space
179 */
180 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
181
182 struct ce_attr *attr;
183 struct ce_pipe_config *pipe_config;
184 struct ce_service_to_pipe *serv_to_pipe;
185
186 /* Keep this entry in the last, memory for struct ath10k_ahb is
187 * allocated (ahb support enabled case) in the continuation of
188 * this struct.
189 */
190 struct ath10k_ahb ahb[];
191
192};
193
194static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
195{
196 return (struct ath10k_pci *)ar->drv_priv;
197}
198
199#define ATH10K_PCI_RX_POST_RETRY_MS 50
200#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
201#define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
202#define PCIE_WAKE_LATE_US 10000 /* 10ms */
203
204#define BAR_NUM 0
205
206#define CDC_WAR_MAGIC_STR 0xceef0000
207#define CDC_WAR_DATA_CE 4
208
209/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
210#define DIAG_ACCESS_CE_TIMEOUT_US 10000 /* 10 ms */
211#define DIAG_ACCESS_CE_WAIT_US 50
212
213void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
214void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
215void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
216
217u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
218u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
219u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
220
221int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
222 struct ath10k_hif_sg_item *items, int n_items);
223int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
224 size_t buf_len);
225int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
226 const void *data, int nbytes);
227int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
228 void *resp, u32 *resp_len);
229int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
230 u8 *ul_pipe, u8 *dl_pipe);
231void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
232 u8 *dl_pipe);
233void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
234 int force);
235u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
236void ath10k_pci_hif_power_down(struct ath10k *ar);
237int ath10k_pci_alloc_pipes(struct ath10k *ar);
238void ath10k_pci_free_pipes(struct ath10k *ar);
239void ath10k_pci_rx_replenish_retry(struct timer_list *t);
240void ath10k_pci_ce_deinit(struct ath10k *ar);
241void ath10k_pci_init_napi(struct ath10k *ar);
242int ath10k_pci_init_pipes(struct ath10k *ar);
243int ath10k_pci_init_config(struct ath10k *ar);
244void ath10k_pci_rx_post(struct ath10k *ar);
245void ath10k_pci_flush(struct ath10k *ar);
246void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
247bool ath10k_pci_irq_pending(struct ath10k *ar);
248void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
249void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
250int ath10k_pci_wait_for_target_init(struct ath10k *ar);
251int ath10k_pci_setup_resource(struct ath10k *ar);
252void ath10k_pci_release_resource(struct ath10k *ar);
253
254/* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
255 * frequently. To avoid this put SoC to sleep after a very conservative grace
256 * period. Adjust with great care.
257 */
258#define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
259
260#endif /* _PCI_H_ */
1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 */
6
7#ifndef _PCI_H_
8#define _PCI_H_
9
10#include <linux/interrupt.h>
11#include <linux/mutex.h>
12
13#include "hw.h"
14#include "ce.h"
15#include "ahb.h"
16
17/*
18 * maximum number of bytes that can be
19 * handled atomically by DiagRead/DiagWrite
20 */
21#define DIAG_TRANSFER_LIMIT 2048
22
23struct bmi_xfer {
24 bool tx_done;
25 bool rx_done;
26 bool wait_for_resp;
27 u32 resp_len;
28};
29
30/*
31 * PCI-specific Target state
32 *
33 * NOTE: Structure is shared between Host software and Target firmware!
34 *
35 * Much of this may be of interest to the Host so
36 * HOST_INTEREST->hi_interconnect_state points here
37 * (and all members are 32-bit quantities in order to
38 * facilitate Host access). In particular, Host software is
39 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
40 */
41struct pcie_state {
42 /* Pipe configuration Target address */
43 /* NB: ce_pipe_config[CE_COUNT] */
44 u32 pipe_cfg_addr;
45
46 /* Service to pipe map Target address */
47 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
48 u32 svc_to_pipe_map;
49
50 /* number of MSI interrupts requested */
51 u32 msi_requested;
52
53 /* number of MSI interrupts granted */
54 u32 msi_granted;
55
56 /* Message Signalled Interrupt address */
57 u32 msi_addr;
58
59 /* Base data */
60 u32 msi_data;
61
62 /*
63 * Data for firmware interrupt;
64 * MSI data for other interrupts are
65 * in various SoC registers
66 */
67 u32 msi_fw_intr_data;
68
69 /* PCIE_PWR_METHOD_* */
70 u32 power_mgmt_method;
71
72 /* PCIE_CONFIG_FLAG_* */
73 u32 config_flags;
74};
75
76/* PCIE_CONFIG_FLAG definitions */
77#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
78
79/* Per-pipe state. */
80struct ath10k_pci_pipe {
81 /* Handle of underlying Copy Engine */
82 struct ath10k_ce_pipe *ce_hdl;
83
84 /* Our pipe number; facilitiates use of pipe_info ptrs. */
85 u8 pipe_num;
86
87 /* Convenience back pointer to hif_ce_state. */
88 struct ath10k *hif_ce_state;
89
90 size_t buf_sz;
91
92 /* protects compl_free and num_send_allowed */
93 spinlock_t pipe_lock;
94};
95
96struct ath10k_pci_supp_chip {
97 u32 dev_id;
98 u32 rev_id;
99};
100
101enum ath10k_pci_irq_mode {
102 ATH10K_PCI_IRQ_AUTO = 0,
103 ATH10K_PCI_IRQ_LEGACY = 1,
104 ATH10K_PCI_IRQ_MSI = 2,
105};
106
107struct ath10k_pci {
108 struct pci_dev *pdev;
109 struct device *dev;
110 struct ath10k *ar;
111 void __iomem *mem;
112 size_t mem_len;
113
114 /* Operating interrupt mode */
115 enum ath10k_pci_irq_mode oper_irq_mode;
116
117 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
118
119 /* Copy Engine used for Diagnostic Accesses */
120 struct ath10k_ce_pipe *ce_diag;
121 /* For protecting ce_diag */
122 struct mutex ce_diag_mutex;
123
124 struct work_struct dump_work;
125
126 struct ath10k_ce ce;
127 struct timer_list rx_post_retry;
128
129 /* Due to HW quirks it is recommended to disable ASPM during device
130 * bootup. To do that the original PCI-E Link Control is stored before
131 * device bootup is executed and re-programmed later.
132 */
133 u16 link_ctl;
134
135 /* Protects ps_awake and ps_wake_refcount */
136 spinlock_t ps_lock;
137
138 /* The device has a special powersave-oriented register. When device is
139 * considered asleep it drains less power and driver is forbidden from
140 * accessing most MMIO registers. If host were to access them without
141 * waking up the device might scribble over host memory or return
142 * 0xdeadbeef readouts.
143 */
144 unsigned long ps_wake_refcount;
145
146 /* Waking up takes some time (up to 2ms in some cases) so it can be bad
147 * for latency. To mitigate this the device isn't immediately allowed
148 * to sleep after all references are undone - instead there's a grace
149 * period after which the powersave register is updated unless some
150 * activity to/from device happened in the meantime.
151 *
152 * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
153 */
154 struct timer_list ps_timer;
155
156 /* MMIO registers are used to communicate with the device. With
157 * intensive traffic accessing powersave register would be a bit
158 * wasteful overhead and would needlessly stall CPU. It is far more
159 * efficient to rely on a variable in RAM and update it only upon
160 * powersave register state changes.
161 */
162 bool ps_awake;
163
164 /* pci power save, disable for QCA988X and QCA99X0.
165 * Writing 'false' to this variable avoids frequent locking
166 * on MMIO read/write.
167 */
168 bool pci_ps;
169
170 /* Chip specific pci reset routine used to do a safe reset */
171 int (*pci_soft_reset)(struct ath10k *ar);
172
173 /* Chip specific pci full reset function */
174 int (*pci_hard_reset)(struct ath10k *ar);
175
176 /* chip specific methods for converting target CPU virtual address
177 * space to CE address space
178 */
179 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
180
181 struct ce_attr *attr;
182 struct ce_pipe_config *pipe_config;
183 struct ce_service_to_pipe *serv_to_pipe;
184
185 /* Keep this entry in the last, memory for struct ath10k_ahb is
186 * allocated (ahb support enabled case) in the continuation of
187 * this struct.
188 */
189 struct ath10k_ahb ahb[];
190
191};
192
193static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
194{
195 return (struct ath10k_pci *)ar->drv_priv;
196}
197
198#define ATH10K_PCI_RX_POST_RETRY_MS 50
199#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
200#define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
201#define PCIE_WAKE_LATE_US 10000 /* 10ms */
202
203#define BAR_NUM 0
204
205#define CDC_WAR_MAGIC_STR 0xceef0000
206#define CDC_WAR_DATA_CE 4
207
208/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
209#define DIAG_ACCESS_CE_TIMEOUT_US 10000 /* 10 ms */
210#define DIAG_ACCESS_CE_WAIT_US 50
211
212void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
213void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
214void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
215
216u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
217u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
218u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
219
220int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
221 struct ath10k_hif_sg_item *items, int n_items);
222int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
223 size_t buf_len);
224int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
225 const void *data, int nbytes);
226int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
227 void *resp, u32 *resp_len);
228int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
229 u8 *ul_pipe, u8 *dl_pipe);
230void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
231 u8 *dl_pipe);
232void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
233 int force);
234u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
235void ath10k_pci_hif_power_down(struct ath10k *ar);
236int ath10k_pci_alloc_pipes(struct ath10k *ar);
237void ath10k_pci_free_pipes(struct ath10k *ar);
238void ath10k_pci_free_pipes(struct ath10k *ar);
239void ath10k_pci_rx_replenish_retry(struct timer_list *t);
240void ath10k_pci_ce_deinit(struct ath10k *ar);
241void ath10k_pci_init_napi(struct ath10k *ar);
242int ath10k_pci_init_pipes(struct ath10k *ar);
243int ath10k_pci_init_config(struct ath10k *ar);
244void ath10k_pci_rx_post(struct ath10k *ar);
245void ath10k_pci_flush(struct ath10k *ar);
246void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
247bool ath10k_pci_irq_pending(struct ath10k *ar);
248void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
249void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
250int ath10k_pci_wait_for_target_init(struct ath10k *ar);
251int ath10k_pci_setup_resource(struct ath10k *ar);
252void ath10k_pci_release_resource(struct ath10k *ar);
253
254/* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
255 * frequently. To avoid this put SoC to sleep after a very conservative grace
256 * period. Adjust with great care.
257 */
258#define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
259
260#endif /* _PCI_H_ */