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1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
6 */
7
8#ifndef _PCI_H_
9#define _PCI_H_
10
11#include <linux/interrupt.h>
12#include <linux/mutex.h>
13
14#include "hw.h"
15#include "ce.h"
16#include "ahb.h"
17
18/*
19 * maximum number of bytes that can be
20 * handled atomically by DiagRead/DiagWrite
21 */
22#define DIAG_TRANSFER_LIMIT 2048
23
24struct bmi_xfer {
25 bool tx_done;
26 bool rx_done;
27 bool wait_for_resp;
28 u32 resp_len;
29};
30
31/*
32 * PCI-specific Target state
33 *
34 * NOTE: Structure is shared between Host software and Target firmware!
35 *
36 * Much of this may be of interest to the Host so
37 * HOST_INTEREST->hi_interconnect_state points here
38 * (and all members are 32-bit quantities in order to
39 * facilitate Host access). In particular, Host software is
40 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
41 */
42struct pcie_state {
43 /* Pipe configuration Target address */
44 /* NB: ce_pipe_config[CE_COUNT] */
45 u32 pipe_cfg_addr;
46
47 /* Service to pipe map Target address */
48 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
49 u32 svc_to_pipe_map;
50
51 /* number of MSI interrupts requested */
52 u32 msi_requested;
53
54 /* number of MSI interrupts granted */
55 u32 msi_granted;
56
57 /* Message Signalled Interrupt address */
58 u32 msi_addr;
59
60 /* Base data */
61 u32 msi_data;
62
63 /*
64 * Data for firmware interrupt;
65 * MSI data for other interrupts are
66 * in various SoC registers
67 */
68 u32 msi_fw_intr_data;
69
70 /* PCIE_PWR_METHOD_* */
71 u32 power_mgmt_method;
72
73 /* PCIE_CONFIG_FLAG_* */
74 u32 config_flags;
75};
76
77/* PCIE_CONFIG_FLAG definitions */
78#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
79
80/* Per-pipe state. */
81struct ath10k_pci_pipe {
82 /* Handle of underlying Copy Engine */
83 struct ath10k_ce_pipe *ce_hdl;
84
85 /* Our pipe number; facilitates use of pipe_info ptrs. */
86 u8 pipe_num;
87
88 /* Convenience back pointer to hif_ce_state. */
89 struct ath10k *hif_ce_state;
90
91 size_t buf_sz;
92
93 /* protects compl_free and num_send_allowed */
94 spinlock_t pipe_lock;
95};
96
97struct ath10k_pci_supp_chip {
98 u32 dev_id;
99 u32 rev_id;
100};
101
102enum ath10k_pci_irq_mode {
103 ATH10K_PCI_IRQ_AUTO = 0,
104 ATH10K_PCI_IRQ_LEGACY = 1,
105 ATH10K_PCI_IRQ_MSI = 2,
106};
107
108struct ath10k_pci {
109 struct pci_dev *pdev;
110 struct device *dev;
111 struct ath10k *ar;
112 void __iomem *mem;
113 size_t mem_len;
114
115 /* Operating interrupt mode */
116 enum ath10k_pci_irq_mode oper_irq_mode;
117
118 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
119
120 /* Copy Engine used for Diagnostic Accesses */
121 struct ath10k_ce_pipe *ce_diag;
122 /* For protecting ce_diag */
123 struct mutex ce_diag_mutex;
124
125 struct work_struct dump_work;
126
127 struct ath10k_ce ce;
128 struct timer_list rx_post_retry;
129
130 /* Due to HW quirks it is recommended to disable ASPM during device
131 * bootup. To do that the original PCI-E Link Control is stored before
132 * device bootup is executed and re-programmed later.
133 */
134 u16 link_ctl;
135
136 /* Protects ps_awake and ps_wake_refcount */
137 spinlock_t ps_lock;
138
139 /* The device has a special powersave-oriented register. When device is
140 * considered asleep it drains less power and driver is forbidden from
141 * accessing most MMIO registers. If host were to access them without
142 * waking up the device might scribble over host memory or return
143 * 0xdeadbeef readouts.
144 */
145 unsigned long ps_wake_refcount;
146
147 /* Waking up takes some time (up to 2ms in some cases) so it can be bad
148 * for latency. To mitigate this the device isn't immediately allowed
149 * to sleep after all references are undone - instead there's a grace
150 * period after which the powersave register is updated unless some
151 * activity to/from device happened in the meantime.
152 *
153 * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
154 */
155 struct timer_list ps_timer;
156
157 /* MMIO registers are used to communicate with the device. With
158 * intensive traffic accessing powersave register would be a bit
159 * wasteful overhead and would needlessly stall CPU. It is far more
160 * efficient to rely on a variable in RAM and update it only upon
161 * powersave register state changes.
162 */
163 bool ps_awake;
164
165 /* pci power save, disable for QCA988X and QCA99X0.
166 * Writing 'false' to this variable avoids frequent locking
167 * on MMIO read/write.
168 */
169 bool pci_ps;
170
171 /* Chip specific pci reset routine used to do a safe reset */
172 int (*pci_soft_reset)(struct ath10k *ar);
173
174 /* Chip specific pci full reset function */
175 int (*pci_hard_reset)(struct ath10k *ar);
176
177 /* chip specific methods for converting target CPU virtual address
178 * space to CE address space
179 */
180 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
181
182 struct ce_attr *attr;
183 struct ce_pipe_config *pipe_config;
184 struct ce_service_to_pipe *serv_to_pipe;
185
186 /* Keep this entry in the last, memory for struct ath10k_ahb is
187 * allocated (ahb support enabled case) in the continuation of
188 * this struct.
189 */
190 struct ath10k_ahb ahb[];
191
192};
193
194static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
195{
196 return (struct ath10k_pci *)ar->drv_priv;
197}
198
199#define ATH10K_PCI_RX_POST_RETRY_MS 50
200#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
201#define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
202#define PCIE_WAKE_LATE_US 10000 /* 10ms */
203
204#define BAR_NUM 0
205
206#define CDC_WAR_MAGIC_STR 0xceef0000
207#define CDC_WAR_DATA_CE 4
208
209/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
210#define DIAG_ACCESS_CE_TIMEOUT_US 10000 /* 10 ms */
211#define DIAG_ACCESS_CE_WAIT_US 50
212
213void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
214void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
215void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
216
217u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
218u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
219u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
220
221int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
222 struct ath10k_hif_sg_item *items, int n_items);
223int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
224 size_t buf_len);
225int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
226 const void *data, int nbytes);
227int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
228 void *resp, u32 *resp_len);
229int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
230 u8 *ul_pipe, u8 *dl_pipe);
231void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
232 u8 *dl_pipe);
233void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
234 int force);
235u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
236void ath10k_pci_hif_power_down(struct ath10k *ar);
237int ath10k_pci_alloc_pipes(struct ath10k *ar);
238void ath10k_pci_free_pipes(struct ath10k *ar);
239void ath10k_pci_rx_replenish_retry(struct timer_list *t);
240void ath10k_pci_ce_deinit(struct ath10k *ar);
241void ath10k_pci_init_napi(struct ath10k *ar);
242int ath10k_pci_init_pipes(struct ath10k *ar);
243int ath10k_pci_init_config(struct ath10k *ar);
244void ath10k_pci_rx_post(struct ath10k *ar);
245void ath10k_pci_flush(struct ath10k *ar);
246void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
247bool ath10k_pci_irq_pending(struct ath10k *ar);
248void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
249void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
250int ath10k_pci_wait_for_target_init(struct ath10k *ar);
251int ath10k_pci_setup_resource(struct ath10k *ar);
252void ath10k_pci_release_resource(struct ath10k *ar);
253
254/* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
255 * frequently. To avoid this put SoC to sleep after a very conservative grace
256 * period. Adjust with great care.
257 */
258#define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
259
260#endif /* _PCI_H_ */
1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _PCI_H_
19#define _PCI_H_
20
21#include <linux/interrupt.h>
22
23#include "hw.h"
24#include "ce.h"
25#include "ahb.h"
26
27/*
28 * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
29 */
30#define DIAG_TRANSFER_LIMIT 2048
31
32/*
33 * maximum number of bytes that can be
34 * handled atomically by DiagRead/DiagWrite
35 */
36#define DIAG_TRANSFER_LIMIT 2048
37
38struct bmi_xfer {
39 bool tx_done;
40 bool rx_done;
41 bool wait_for_resp;
42 u32 resp_len;
43};
44
45/*
46 * PCI-specific Target state
47 *
48 * NOTE: Structure is shared between Host software and Target firmware!
49 *
50 * Much of this may be of interest to the Host so
51 * HOST_INTEREST->hi_interconnect_state points here
52 * (and all members are 32-bit quantities in order to
53 * facilitate Host access). In particular, Host software is
54 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
55 */
56struct pcie_state {
57 /* Pipe configuration Target address */
58 /* NB: ce_pipe_config[CE_COUNT] */
59 u32 pipe_cfg_addr;
60
61 /* Service to pipe map Target address */
62 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
63 u32 svc_to_pipe_map;
64
65 /* number of MSI interrupts requested */
66 u32 msi_requested;
67
68 /* number of MSI interrupts granted */
69 u32 msi_granted;
70
71 /* Message Signalled Interrupt address */
72 u32 msi_addr;
73
74 /* Base data */
75 u32 msi_data;
76
77 /*
78 * Data for firmware interrupt;
79 * MSI data for other interrupts are
80 * in various SoC registers
81 */
82 u32 msi_fw_intr_data;
83
84 /* PCIE_PWR_METHOD_* */
85 u32 power_mgmt_method;
86
87 /* PCIE_CONFIG_FLAG_* */
88 u32 config_flags;
89};
90
91/* PCIE_CONFIG_FLAG definitions */
92#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
93
94/* Host software's Copy Engine configuration. */
95#define CE_ATTR_FLAGS 0
96
97/*
98 * Configuration information for a Copy Engine pipe.
99 * Passed from Host to Target during startup (one per CE).
100 *
101 * NOTE: Structure is shared between Host software and Target firmware!
102 */
103struct ce_pipe_config {
104 __le32 pipenum;
105 __le32 pipedir;
106 __le32 nentries;
107 __le32 nbytes_max;
108 __le32 flags;
109 __le32 reserved;
110};
111
112/*
113 * Directions for interconnect pipe configuration.
114 * These definitions may be used during configuration and are shared
115 * between Host and Target.
116 *
117 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
118 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
119 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
120 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
121 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
122 * over the interconnect.
123 */
124#define PIPEDIR_NONE 0
125#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
126#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
127#define PIPEDIR_INOUT 3 /* bidirectional */
128
129/* Establish a mapping between a service/direction and a pipe. */
130struct service_to_pipe {
131 __le32 service_id;
132 __le32 pipedir;
133 __le32 pipenum;
134};
135
136/* Per-pipe state. */
137struct ath10k_pci_pipe {
138 /* Handle of underlying Copy Engine */
139 struct ath10k_ce_pipe *ce_hdl;
140
141 /* Our pipe number; facilitiates use of pipe_info ptrs. */
142 u8 pipe_num;
143
144 /* Convenience back pointer to hif_ce_state. */
145 struct ath10k *hif_ce_state;
146
147 size_t buf_sz;
148
149 /* protects compl_free and num_send_allowed */
150 spinlock_t pipe_lock;
151};
152
153struct ath10k_pci_supp_chip {
154 u32 dev_id;
155 u32 rev_id;
156};
157
158struct ath10k_bus_ops {
159 u32 (*read32)(struct ath10k *ar, u32 offset);
160 void (*write32)(struct ath10k *ar, u32 offset, u32 value);
161 int (*get_num_banks)(struct ath10k *ar);
162};
163
164enum ath10k_pci_irq_mode {
165 ATH10K_PCI_IRQ_AUTO = 0,
166 ATH10K_PCI_IRQ_LEGACY = 1,
167 ATH10K_PCI_IRQ_MSI = 2,
168};
169
170struct ath10k_pci {
171 struct pci_dev *pdev;
172 struct device *dev;
173 struct ath10k *ar;
174 void __iomem *mem;
175 size_t mem_len;
176
177 /* Operating interrupt mode */
178 enum ath10k_pci_irq_mode oper_irq_mode;
179
180 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
181
182 /* Copy Engine used for Diagnostic Accesses */
183 struct ath10k_ce_pipe *ce_diag;
184
185 /* FIXME: document what this really protects */
186 spinlock_t ce_lock;
187
188 /* Map CE id to ce_state */
189 struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
190 struct timer_list rx_post_retry;
191
192 /* Due to HW quirks it is recommended to disable ASPM during device
193 * bootup. To do that the original PCI-E Link Control is stored before
194 * device bootup is executed and re-programmed later.
195 */
196 u16 link_ctl;
197
198 /* Protects ps_awake and ps_wake_refcount */
199 spinlock_t ps_lock;
200
201 /* The device has a special powersave-oriented register. When device is
202 * considered asleep it drains less power and driver is forbidden from
203 * accessing most MMIO registers. If host were to access them without
204 * waking up the device might scribble over host memory or return
205 * 0xdeadbeef readouts.
206 */
207 unsigned long ps_wake_refcount;
208
209 /* Waking up takes some time (up to 2ms in some cases) so it can be bad
210 * for latency. To mitigate this the device isn't immediately allowed
211 * to sleep after all references are undone - instead there's a grace
212 * period after which the powersave register is updated unless some
213 * activity to/from device happened in the meantime.
214 *
215 * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
216 */
217 struct timer_list ps_timer;
218
219 /* MMIO registers are used to communicate with the device. With
220 * intensive traffic accessing powersave register would be a bit
221 * wasteful overhead and would needlessly stall CPU. It is far more
222 * efficient to rely on a variable in RAM and update it only upon
223 * powersave register state changes.
224 */
225 bool ps_awake;
226
227 /* pci power save, disable for QCA988X and QCA99X0.
228 * Writing 'false' to this variable avoids frequent locking
229 * on MMIO read/write.
230 */
231 bool pci_ps;
232
233 const struct ath10k_bus_ops *bus_ops;
234
235 /* Chip specific pci reset routine used to do a safe reset */
236 int (*pci_soft_reset)(struct ath10k *ar);
237
238 /* Chip specific pci full reset function */
239 int (*pci_hard_reset)(struct ath10k *ar);
240
241 /* Keep this entry in the last, memory for struct ath10k_ahb is
242 * allocated (ahb support enabled case) in the continuation of
243 * this struct.
244 */
245 struct ath10k_ahb ahb[0];
246};
247
248static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
249{
250 return (struct ath10k_pci *)ar->drv_priv;
251}
252
253#define ATH10K_PCI_RX_POST_RETRY_MS 50
254#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
255#define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
256#define PCIE_WAKE_LATE_US 10000 /* 10ms */
257
258#define BAR_NUM 0
259
260#define CDC_WAR_MAGIC_STR 0xceef0000
261#define CDC_WAR_DATA_CE 4
262
263/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
264#define DIAG_ACCESS_CE_TIMEOUT_MS 10
265
266void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
267void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
268void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
269
270u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
271u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
272u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
273
274int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
275 struct ath10k_hif_sg_item *items, int n_items);
276int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
277 size_t buf_len);
278int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
279 const void *data, int nbytes);
280int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
281 void *resp, u32 *resp_len);
282int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
283 u8 *ul_pipe, u8 *dl_pipe);
284void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
285 u8 *dl_pipe);
286void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
287 int force);
288u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
289void ath10k_pci_hif_power_down(struct ath10k *ar);
290int ath10k_pci_alloc_pipes(struct ath10k *ar);
291void ath10k_pci_free_pipes(struct ath10k *ar);
292void ath10k_pci_free_pipes(struct ath10k *ar);
293void ath10k_pci_rx_replenish_retry(unsigned long ptr);
294void ath10k_pci_ce_deinit(struct ath10k *ar);
295void ath10k_pci_init_napi(struct ath10k *ar);
296int ath10k_pci_init_pipes(struct ath10k *ar);
297int ath10k_pci_init_config(struct ath10k *ar);
298void ath10k_pci_rx_post(struct ath10k *ar);
299void ath10k_pci_flush(struct ath10k *ar);
300void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
301bool ath10k_pci_irq_pending(struct ath10k *ar);
302void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
303void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
304int ath10k_pci_wait_for_target_init(struct ath10k *ar);
305int ath10k_pci_setup_resource(struct ath10k *ar);
306void ath10k_pci_release_resource(struct ath10k *ar);
307
308/* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
309 * frequently. To avoid this put SoC to sleep after a very conservative grace
310 * period. Adjust with great care.
311 */
312#define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
313
314#endif /* _PCI_H_ */