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1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
6 */
7
8#ifndef _PCI_H_
9#define _PCI_H_
10
11#include <linux/interrupt.h>
12#include <linux/mutex.h>
13
14#include "hw.h"
15#include "ce.h"
16#include "ahb.h"
17
18/*
19 * maximum number of bytes that can be
20 * handled atomically by DiagRead/DiagWrite
21 */
22#define DIAG_TRANSFER_LIMIT 2048
23
24struct bmi_xfer {
25 bool tx_done;
26 bool rx_done;
27 bool wait_for_resp;
28 u32 resp_len;
29};
30
31/*
32 * PCI-specific Target state
33 *
34 * NOTE: Structure is shared between Host software and Target firmware!
35 *
36 * Much of this may be of interest to the Host so
37 * HOST_INTEREST->hi_interconnect_state points here
38 * (and all members are 32-bit quantities in order to
39 * facilitate Host access). In particular, Host software is
40 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
41 */
42struct pcie_state {
43 /* Pipe configuration Target address */
44 /* NB: ce_pipe_config[CE_COUNT] */
45 u32 pipe_cfg_addr;
46
47 /* Service to pipe map Target address */
48 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
49 u32 svc_to_pipe_map;
50
51 /* number of MSI interrupts requested */
52 u32 msi_requested;
53
54 /* number of MSI interrupts granted */
55 u32 msi_granted;
56
57 /* Message Signalled Interrupt address */
58 u32 msi_addr;
59
60 /* Base data */
61 u32 msi_data;
62
63 /*
64 * Data for firmware interrupt;
65 * MSI data for other interrupts are
66 * in various SoC registers
67 */
68 u32 msi_fw_intr_data;
69
70 /* PCIE_PWR_METHOD_* */
71 u32 power_mgmt_method;
72
73 /* PCIE_CONFIG_FLAG_* */
74 u32 config_flags;
75};
76
77/* PCIE_CONFIG_FLAG definitions */
78#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
79
80/* Per-pipe state. */
81struct ath10k_pci_pipe {
82 /* Handle of underlying Copy Engine */
83 struct ath10k_ce_pipe *ce_hdl;
84
85 /* Our pipe number; facilitates use of pipe_info ptrs. */
86 u8 pipe_num;
87
88 /* Convenience back pointer to hif_ce_state. */
89 struct ath10k *hif_ce_state;
90
91 size_t buf_sz;
92
93 /* protects compl_free and num_send_allowed */
94 spinlock_t pipe_lock;
95};
96
97struct ath10k_pci_supp_chip {
98 u32 dev_id;
99 u32 rev_id;
100};
101
102enum ath10k_pci_irq_mode {
103 ATH10K_PCI_IRQ_AUTO = 0,
104 ATH10K_PCI_IRQ_LEGACY = 1,
105 ATH10K_PCI_IRQ_MSI = 2,
106};
107
108struct ath10k_pci {
109 struct pci_dev *pdev;
110 struct device *dev;
111 struct ath10k *ar;
112 void __iomem *mem;
113 size_t mem_len;
114
115 /* Operating interrupt mode */
116 enum ath10k_pci_irq_mode oper_irq_mode;
117
118 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
119
120 /* Copy Engine used for Diagnostic Accesses */
121 struct ath10k_ce_pipe *ce_diag;
122 /* For protecting ce_diag */
123 struct mutex ce_diag_mutex;
124
125 struct work_struct dump_work;
126
127 struct ath10k_ce ce;
128 struct timer_list rx_post_retry;
129
130 /* Due to HW quirks it is recommended to disable ASPM during device
131 * bootup. To do that the original PCI-E Link Control is stored before
132 * device bootup is executed and re-programmed later.
133 */
134 u16 link_ctl;
135
136 /* Protects ps_awake and ps_wake_refcount */
137 spinlock_t ps_lock;
138
139 /* The device has a special powersave-oriented register. When device is
140 * considered asleep it drains less power and driver is forbidden from
141 * accessing most MMIO registers. If host were to access them without
142 * waking up the device might scribble over host memory or return
143 * 0xdeadbeef readouts.
144 */
145 unsigned long ps_wake_refcount;
146
147 /* Waking up takes some time (up to 2ms in some cases) so it can be bad
148 * for latency. To mitigate this the device isn't immediately allowed
149 * to sleep after all references are undone - instead there's a grace
150 * period after which the powersave register is updated unless some
151 * activity to/from device happened in the meantime.
152 *
153 * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
154 */
155 struct timer_list ps_timer;
156
157 /* MMIO registers are used to communicate with the device. With
158 * intensive traffic accessing powersave register would be a bit
159 * wasteful overhead and would needlessly stall CPU. It is far more
160 * efficient to rely on a variable in RAM and update it only upon
161 * powersave register state changes.
162 */
163 bool ps_awake;
164
165 /* pci power save, disable for QCA988X and QCA99X0.
166 * Writing 'false' to this variable avoids frequent locking
167 * on MMIO read/write.
168 */
169 bool pci_ps;
170
171 /* Chip specific pci reset routine used to do a safe reset */
172 int (*pci_soft_reset)(struct ath10k *ar);
173
174 /* Chip specific pci full reset function */
175 int (*pci_hard_reset)(struct ath10k *ar);
176
177 /* chip specific methods for converting target CPU virtual address
178 * space to CE address space
179 */
180 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
181
182 struct ce_attr *attr;
183 struct ce_pipe_config *pipe_config;
184 struct ce_service_to_pipe *serv_to_pipe;
185
186 /* Keep this entry in the last, memory for struct ath10k_ahb is
187 * allocated (ahb support enabled case) in the continuation of
188 * this struct.
189 */
190 struct ath10k_ahb ahb[];
191
192};
193
194static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
195{
196 return (struct ath10k_pci *)ar->drv_priv;
197}
198
199#define ATH10K_PCI_RX_POST_RETRY_MS 50
200#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
201#define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
202#define PCIE_WAKE_LATE_US 10000 /* 10ms */
203
204#define BAR_NUM 0
205
206#define CDC_WAR_MAGIC_STR 0xceef0000
207#define CDC_WAR_DATA_CE 4
208
209/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
210#define DIAG_ACCESS_CE_TIMEOUT_US 10000 /* 10 ms */
211#define DIAG_ACCESS_CE_WAIT_US 50
212
213void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
214void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
215void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
216
217u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
218u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
219u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
220
221int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
222 struct ath10k_hif_sg_item *items, int n_items);
223int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
224 size_t buf_len);
225int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
226 const void *data, int nbytes);
227int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
228 void *resp, u32 *resp_len);
229int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
230 u8 *ul_pipe, u8 *dl_pipe);
231void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
232 u8 *dl_pipe);
233void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
234 int force);
235u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
236void ath10k_pci_hif_power_down(struct ath10k *ar);
237int ath10k_pci_alloc_pipes(struct ath10k *ar);
238void ath10k_pci_free_pipes(struct ath10k *ar);
239void ath10k_pci_rx_replenish_retry(struct timer_list *t);
240void ath10k_pci_ce_deinit(struct ath10k *ar);
241void ath10k_pci_init_napi(struct ath10k *ar);
242int ath10k_pci_init_pipes(struct ath10k *ar);
243int ath10k_pci_init_config(struct ath10k *ar);
244void ath10k_pci_rx_post(struct ath10k *ar);
245void ath10k_pci_flush(struct ath10k *ar);
246void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
247bool ath10k_pci_irq_pending(struct ath10k *ar);
248void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
249void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
250int ath10k_pci_wait_for_target_init(struct ath10k *ar);
251int ath10k_pci_setup_resource(struct ath10k *ar);
252void ath10k_pci_release_resource(struct ath10k *ar);
253
254/* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
255 * frequently. To avoid this put SoC to sleep after a very conservative grace
256 * period. Adjust with great care.
257 */
258#define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
259
260#endif /* _PCI_H_ */
1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _PCI_H_
19#define _PCI_H_
20
21#include <linux/interrupt.h>
22
23#include "hw.h"
24#include "ce.h"
25
26/* FW dump area */
27#define REG_DUMP_COUNT_QCA988X 60
28
29/*
30 * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
31 */
32#define DIAG_TRANSFER_LIMIT 2048
33
34/*
35 * maximum number of bytes that can be
36 * handled atomically by DiagRead/DiagWrite
37 */
38#define DIAG_TRANSFER_LIMIT 2048
39
40struct bmi_xfer {
41 struct completion done;
42 bool wait_for_resp;
43 u32 resp_len;
44};
45
46/*
47 * PCI-specific Target state
48 *
49 * NOTE: Structure is shared between Host software and Target firmware!
50 *
51 * Much of this may be of interest to the Host so
52 * HOST_INTEREST->hi_interconnect_state points here
53 * (and all members are 32-bit quantities in order to
54 * facilitate Host access). In particular, Host software is
55 * required to initialize pipe_cfg_addr and svc_to_pipe_map.
56 */
57struct pcie_state {
58 /* Pipe configuration Target address */
59 /* NB: ce_pipe_config[CE_COUNT] */
60 u32 pipe_cfg_addr;
61
62 /* Service to pipe map Target address */
63 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
64 u32 svc_to_pipe_map;
65
66 /* number of MSI interrupts requested */
67 u32 msi_requested;
68
69 /* number of MSI interrupts granted */
70 u32 msi_granted;
71
72 /* Message Signalled Interrupt address */
73 u32 msi_addr;
74
75 /* Base data */
76 u32 msi_data;
77
78 /*
79 * Data for firmware interrupt;
80 * MSI data for other interrupts are
81 * in various SoC registers
82 */
83 u32 msi_fw_intr_data;
84
85 /* PCIE_PWR_METHOD_* */
86 u32 power_mgmt_method;
87
88 /* PCIE_CONFIG_FLAG_* */
89 u32 config_flags;
90};
91
92/* PCIE_CONFIG_FLAG definitions */
93#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
94
95/* Host software's Copy Engine configuration. */
96#define CE_ATTR_FLAGS 0
97
98/*
99 * Configuration information for a Copy Engine pipe.
100 * Passed from Host to Target during startup (one per CE).
101 *
102 * NOTE: Structure is shared between Host software and Target firmware!
103 */
104struct ce_pipe_config {
105 u32 pipenum;
106 u32 pipedir;
107 u32 nentries;
108 u32 nbytes_max;
109 u32 flags;
110 u32 reserved;
111};
112
113/*
114 * Directions for interconnect pipe configuration.
115 * These definitions may be used during configuration and are shared
116 * between Host and Target.
117 *
118 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
119 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
120 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
121 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
122 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
123 * over the interconnect.
124 */
125#define PIPEDIR_NONE 0
126#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
127#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
128#define PIPEDIR_INOUT 3 /* bidirectional */
129
130/* Establish a mapping between a service/direction and a pipe. */
131struct service_to_pipe {
132 u32 service_id;
133 u32 pipedir;
134 u32 pipenum;
135};
136
137enum ath10k_pci_features {
138 ATH10K_PCI_FEATURE_MSI_X = 0,
139 ATH10K_PCI_FEATURE_SOC_POWER_SAVE = 1,
140
141 /* keep last */
142 ATH10K_PCI_FEATURE_COUNT
143};
144
145/* Per-pipe state. */
146struct ath10k_pci_pipe {
147 /* Handle of underlying Copy Engine */
148 struct ath10k_ce_pipe *ce_hdl;
149
150 /* Our pipe number; facilitiates use of pipe_info ptrs. */
151 u8 pipe_num;
152
153 /* Convenience back pointer to hif_ce_state. */
154 struct ath10k *hif_ce_state;
155
156 size_t buf_sz;
157
158 /* protects compl_free and num_send_allowed */
159 spinlock_t pipe_lock;
160
161 struct ath10k_pci *ar_pci;
162 struct tasklet_struct intr;
163};
164
165struct ath10k_pci {
166 struct pci_dev *pdev;
167 struct device *dev;
168 struct ath10k *ar;
169 void __iomem *mem;
170
171 DECLARE_BITMAP(features, ATH10K_PCI_FEATURE_COUNT);
172
173 /*
174 * Number of MSI interrupts granted, 0 --> using legacy PCI line
175 * interrupts.
176 */
177 int num_msi_intrs;
178
179 struct tasklet_struct intr_tq;
180 struct tasklet_struct msi_fw_err;
181 struct tasklet_struct early_irq_tasklet;
182
183 int started;
184
185 atomic_t keep_awake_count;
186 bool verified_awake;
187
188 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
189
190 struct ath10k_hif_cb msg_callbacks_current;
191
192 /* Target address used to signal a pending firmware event */
193 u32 fw_indicator_address;
194
195 /* Copy Engine used for Diagnostic Accesses */
196 struct ath10k_ce_pipe *ce_diag;
197
198 /* FIXME: document what this really protects */
199 spinlock_t ce_lock;
200
201 /* Map CE id to ce_state */
202 struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
203};
204
205static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
206{
207 return ar->hif.priv;
208}
209
210static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
211{
212 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
213
214 return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
215}
216
217static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
218{
219 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
220
221 iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
222}
223
224#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
225#define PCIE_WAKE_TIMEOUT 5000 /* 5ms */
226
227#define BAR_NUM 0
228
229#define CDC_WAR_MAGIC_STR 0xceef0000
230#define CDC_WAR_DATA_CE 4
231
232/*
233 * TODO: Should be a function call specific to each Target-type.
234 * This convoluted macro converts from Target CPU Virtual Address Space to CE
235 * Address Space. As part of this process, we conservatively fetch the current
236 * PCIE_BAR. MOST of the time, this should match the upper bits of PCI space
237 * for this device; but that's not guaranteed.
238 */
239#define TARG_CPU_SPACE_TO_CE_SPACE(ar, pci_addr, addr) \
240 (((ioread32((pci_addr)+(SOC_CORE_BASE_ADDRESS| \
241 CORE_CTRL_ADDRESS)) & 0x7ff) << 21) | \
242 0x100000 | ((addr) & 0xfffff))
243
244/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
245#define DIAG_ACCESS_CE_TIMEOUT_MS 10
246
247/*
248 * This API allows the Host to access Target registers directly
249 * and relatively efficiently over PCIe.
250 * This allows the Host to avoid extra overhead associated with
251 * sending a message to firmware and waiting for a response message
252 * from firmware, as is done on other interconnects.
253 *
254 * Yet there is some complexity with direct accesses because the
255 * Target's power state is not known a priori. The Host must issue
256 * special PCIe reads/writes in order to explicitly wake the Target
257 * and to verify that it is awake and will remain awake.
258 *
259 * Usage:
260 *
261 * Use ath10k_pci_read32 and ath10k_pci_write32 to access Target space.
262 * These calls must be bracketed by ath10k_pci_wake and
263 * ath10k_pci_sleep. A single BEGIN/END pair is adequate for
264 * multiple READ/WRITE operations.
265 *
266 * Use ath10k_pci_wake to put the Target in a state in
267 * which it is legal for the Host to directly access it. This
268 * may involve waking the Target from a low power state, which
269 * may take up to 2Ms!
270 *
271 * Use ath10k_pci_sleep to tell the Target that as far as
272 * this code path is concerned, it no longer needs to remain
273 * directly accessible. BEGIN/END is under a reference counter;
274 * multiple code paths may issue BEGIN/END on a single targid.
275 */
276static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset,
277 u32 value)
278{
279 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
280
281 iowrite32(value, ar_pci->mem + offset);
282}
283
284static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
285{
286 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
287
288 return ioread32(ar_pci->mem + offset);
289}
290
291static inline u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
292{
293 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
294}
295
296static inline void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
297{
298 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
299}
300
301int ath10k_do_pci_wake(struct ath10k *ar);
302void ath10k_do_pci_sleep(struct ath10k *ar);
303
304static inline int ath10k_pci_wake(struct ath10k *ar)
305{
306 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
307
308 if (test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
309 return ath10k_do_pci_wake(ar);
310
311 return 0;
312}
313
314static inline void ath10k_pci_sleep(struct ath10k *ar)
315{
316 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
317
318 if (test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
319 ath10k_do_pci_sleep(ar);
320}
321
322#endif /* _PCI_H_ */