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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4#include <linux/bpf_trace.h>
5#include <linux/prefetch.h>
6#include <linux/sctp.h>
7#include <net/mpls.h>
8#include <net/xdp.h>
9#include "i40e_txrx_common.h"
10#include "i40e_trace.h"
11#include "i40e_xsk.h"
12
13#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
14/**
15 * i40e_fdir - Generate a Flow Director descriptor based on fdata
16 * @tx_ring: Tx ring to send buffer on
17 * @fdata: Flow director filter data
18 * @add: Indicate if we are adding a rule or deleting one
19 *
20 **/
21static void i40e_fdir(struct i40e_ring *tx_ring,
22 struct i40e_fdir_filter *fdata, bool add)
23{
24 struct i40e_filter_program_desc *fdir_desc;
25 struct i40e_pf *pf = tx_ring->vsi->back;
26 u32 flex_ptype, dtype_cmd;
27 u16 i;
28
29 /* grab the next descriptor */
30 i = tx_ring->next_to_use;
31 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
32
33 i++;
34 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
35
36 flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK, fdata->q_index);
37
38 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_FLEXOFF_MASK,
39 fdata->flex_off);
40
41 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_PCTYPE_MASK, fdata->pctype);
42
43 /* Use LAN VSI Id if not programmed by user */
44 flex_ptype |= FIELD_PREP(I40E_TXD_FLTR_QW0_DEST_VSI_MASK,
45 fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id);
46
47 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
48
49 dtype_cmd |= add ?
50 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
51 I40E_TXD_FLTR_QW1_PCMD_SHIFT :
52 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
53 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
54
55 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_DEST_MASK, fdata->dest_ctl);
56
57 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_FD_STATUS_MASK,
58 fdata->fd_status);
59
60 if (fdata->cnt_index) {
61 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
62 dtype_cmd |= FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK,
63 fdata->cnt_index);
64 }
65
66 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
67 fdir_desc->rsvd = cpu_to_le32(0);
68 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
69 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
70}
71
72#define I40E_FD_CLEAN_DELAY 10
73/**
74 * i40e_program_fdir_filter - Program a Flow Director filter
75 * @fdir_data: Packet data that will be filter parameters
76 * @raw_packet: the pre-allocated packet buffer for FDir
77 * @pf: The PF pointer
78 * @add: True for add/update, False for remove
79 **/
80static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
81 u8 *raw_packet, struct i40e_pf *pf,
82 bool add)
83{
84 struct i40e_tx_buffer *tx_buf, *first;
85 struct i40e_tx_desc *tx_desc;
86 struct i40e_ring *tx_ring;
87 struct i40e_vsi *vsi;
88 struct device *dev;
89 dma_addr_t dma;
90 u32 td_cmd = 0;
91 u16 i;
92
93 /* find existing FDIR VSI */
94 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
95 if (!vsi)
96 return -ENOENT;
97
98 tx_ring = vsi->tx_rings[0];
99 dev = tx_ring->dev;
100
101 /* we need two descriptors to add/del a filter and we can wait */
102 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
103 if (!i)
104 return -EAGAIN;
105 msleep_interruptible(1);
106 }
107
108 dma = dma_map_single(dev, raw_packet,
109 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
110 if (dma_mapping_error(dev, dma))
111 goto dma_fail;
112
113 /* grab the next descriptor */
114 i = tx_ring->next_to_use;
115 first = &tx_ring->tx_bi[i];
116 i40e_fdir(tx_ring, fdir_data, add);
117
118 /* Now program a dummy descriptor */
119 i = tx_ring->next_to_use;
120 tx_desc = I40E_TX_DESC(tx_ring, i);
121 tx_buf = &tx_ring->tx_bi[i];
122
123 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
124
125 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
126
127 /* record length, and DMA address */
128 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
129 dma_unmap_addr_set(tx_buf, dma, dma);
130
131 tx_desc->buffer_addr = cpu_to_le64(dma);
132 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
133
134 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
135 tx_buf->raw_buf = (void *)raw_packet;
136
137 tx_desc->cmd_type_offset_bsz =
138 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
139
140 /* Force memory writes to complete before letting h/w
141 * know there are new descriptors to fetch.
142 */
143 wmb();
144
145 /* Mark the data descriptor to be watched */
146 first->next_to_watch = tx_desc;
147
148 writel(tx_ring->next_to_use, tx_ring->tail);
149 return 0;
150
151dma_fail:
152 return -1;
153}
154
155/**
156 * i40e_create_dummy_packet - Constructs dummy packet for HW
157 * @dummy_packet: preallocated space for dummy packet
158 * @ipv4: is layer 3 packet of version 4 or 6
159 * @l4proto: next level protocol used in data portion of l3
160 * @data: filter data
161 *
162 * Returns address of layer 4 protocol dummy packet.
163 **/
164static char *i40e_create_dummy_packet(u8 *dummy_packet, bool ipv4, u8 l4proto,
165 struct i40e_fdir_filter *data)
166{
167 bool is_vlan = !!data->vlan_tag;
168 struct vlan_hdr vlan = {};
169 struct ipv6hdr ipv6 = {};
170 struct ethhdr eth = {};
171 struct iphdr ip = {};
172 u8 *tmp;
173
174 if (ipv4) {
175 eth.h_proto = cpu_to_be16(ETH_P_IP);
176 ip.protocol = l4proto;
177 ip.version = 0x4;
178 ip.ihl = 0x5;
179
180 ip.daddr = data->dst_ip;
181 ip.saddr = data->src_ip;
182 } else {
183 eth.h_proto = cpu_to_be16(ETH_P_IPV6);
184 ipv6.nexthdr = l4proto;
185 ipv6.version = 0x6;
186
187 memcpy(&ipv6.saddr.in6_u.u6_addr32, data->src_ip6,
188 sizeof(__be32) * 4);
189 memcpy(&ipv6.daddr.in6_u.u6_addr32, data->dst_ip6,
190 sizeof(__be32) * 4);
191 }
192
193 if (is_vlan) {
194 vlan.h_vlan_TCI = data->vlan_tag;
195 vlan.h_vlan_encapsulated_proto = eth.h_proto;
196 eth.h_proto = data->vlan_etype;
197 }
198
199 tmp = dummy_packet;
200 memcpy(tmp, ð, sizeof(eth));
201 tmp += sizeof(eth);
202
203 if (is_vlan) {
204 memcpy(tmp, &vlan, sizeof(vlan));
205 tmp += sizeof(vlan);
206 }
207
208 if (ipv4) {
209 memcpy(tmp, &ip, sizeof(ip));
210 tmp += sizeof(ip);
211 } else {
212 memcpy(tmp, &ipv6, sizeof(ipv6));
213 tmp += sizeof(ipv6);
214 }
215
216 return tmp;
217}
218
219/**
220 * i40e_create_dummy_udp_packet - helper function to create UDP packet
221 * @raw_packet: preallocated space for dummy packet
222 * @ipv4: is layer 3 packet of version 4 or 6
223 * @l4proto: next level protocol used in data portion of l3
224 * @data: filter data
225 *
226 * Helper function to populate udp fields.
227 **/
228static void i40e_create_dummy_udp_packet(u8 *raw_packet, bool ipv4, u8 l4proto,
229 struct i40e_fdir_filter *data)
230{
231 struct udphdr *udp;
232 u8 *tmp;
233
234 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_UDP, data);
235 udp = (struct udphdr *)(tmp);
236 udp->dest = data->dst_port;
237 udp->source = data->src_port;
238}
239
240/**
241 * i40e_create_dummy_tcp_packet - helper function to create TCP packet
242 * @raw_packet: preallocated space for dummy packet
243 * @ipv4: is layer 3 packet of version 4 or 6
244 * @l4proto: next level protocol used in data portion of l3
245 * @data: filter data
246 *
247 * Helper function to populate tcp fields.
248 **/
249static void i40e_create_dummy_tcp_packet(u8 *raw_packet, bool ipv4, u8 l4proto,
250 struct i40e_fdir_filter *data)
251{
252 struct tcphdr *tcp;
253 u8 *tmp;
254 /* Dummy tcp packet */
255 static const char tcp_packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
256 0x50, 0x11, 0x0, 0x72, 0, 0, 0, 0};
257
258 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_TCP, data);
259
260 tcp = (struct tcphdr *)tmp;
261 memcpy(tcp, tcp_packet, sizeof(tcp_packet));
262 tcp->dest = data->dst_port;
263 tcp->source = data->src_port;
264}
265
266/**
267 * i40e_create_dummy_sctp_packet - helper function to create SCTP packet
268 * @raw_packet: preallocated space for dummy packet
269 * @ipv4: is layer 3 packet of version 4 or 6
270 * @l4proto: next level protocol used in data portion of l3
271 * @data: filter data
272 *
273 * Helper function to populate sctp fields.
274 **/
275static void i40e_create_dummy_sctp_packet(u8 *raw_packet, bool ipv4,
276 u8 l4proto,
277 struct i40e_fdir_filter *data)
278{
279 struct sctphdr *sctp;
280 u8 *tmp;
281
282 tmp = i40e_create_dummy_packet(raw_packet, ipv4, IPPROTO_SCTP, data);
283
284 sctp = (struct sctphdr *)tmp;
285 sctp->dest = data->dst_port;
286 sctp->source = data->src_port;
287}
288
289/**
290 * i40e_prepare_fdir_filter - Prepare and program fdir filter
291 * @pf: physical function to attach filter to
292 * @fd_data: filter data
293 * @add: add or delete filter
294 * @packet_addr: address of dummy packet, used in filtering
295 * @payload_offset: offset from dummy packet address to user defined data
296 * @pctype: Packet type for which filter is used
297 *
298 * Helper function to offset data of dummy packet, program it and
299 * handle errors.
300 **/
301static int i40e_prepare_fdir_filter(struct i40e_pf *pf,
302 struct i40e_fdir_filter *fd_data,
303 bool add, char *packet_addr,
304 int payload_offset, u8 pctype)
305{
306 int ret;
307
308 if (fd_data->flex_filter) {
309 u8 *payload;
310 __be16 pattern = fd_data->flex_word;
311 u16 off = fd_data->flex_offset;
312
313 payload = packet_addr + payload_offset;
314
315 /* If user provided vlan, offset payload by vlan header length */
316 if (!!fd_data->vlan_tag)
317 payload += VLAN_HLEN;
318
319 *((__force __be16 *)(payload + off)) = pattern;
320 }
321
322 fd_data->pctype = pctype;
323 ret = i40e_program_fdir_filter(fd_data, packet_addr, pf, add);
324 if (ret) {
325 dev_info(&pf->pdev->dev,
326 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
327 fd_data->pctype, fd_data->fd_id, ret);
328 /* Free the packet buffer since it wasn't added to the ring */
329 return -EOPNOTSUPP;
330 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
331 if (add)
332 dev_info(&pf->pdev->dev,
333 "Filter OK for PCTYPE %d loc = %d\n",
334 fd_data->pctype, fd_data->fd_id);
335 else
336 dev_info(&pf->pdev->dev,
337 "Filter deleted for PCTYPE %d loc = %d\n",
338 fd_data->pctype, fd_data->fd_id);
339 }
340
341 return ret;
342}
343
344/**
345 * i40e_change_filter_num - Prepare and program fdir filter
346 * @ipv4: is layer 3 packet of version 4 or 6
347 * @add: add or delete filter
348 * @ipv4_filter_num: field to update
349 * @ipv6_filter_num: field to update
350 *
351 * Update filter number field for pf.
352 **/
353static void i40e_change_filter_num(bool ipv4, bool add, u16 *ipv4_filter_num,
354 u16 *ipv6_filter_num)
355{
356 if (add) {
357 if (ipv4)
358 (*ipv4_filter_num)++;
359 else
360 (*ipv6_filter_num)++;
361 } else {
362 if (ipv4)
363 (*ipv4_filter_num)--;
364 else
365 (*ipv6_filter_num)--;
366 }
367}
368
369#define I40E_UDPIP_DUMMY_PACKET_LEN 42
370#define I40E_UDPIP6_DUMMY_PACKET_LEN 62
371/**
372 * i40e_add_del_fdir_udp - Add/Remove UDP filters
373 * @vsi: pointer to the targeted VSI
374 * @fd_data: the flow director data required for the FDir descriptor
375 * @add: true adds a filter, false removes it
376 * @ipv4: true is v4, false is v6
377 *
378 * Returns 0 if the filters were successfully added or removed
379 **/
380static int i40e_add_del_fdir_udp(struct i40e_vsi *vsi,
381 struct i40e_fdir_filter *fd_data,
382 bool add,
383 bool ipv4)
384{
385 struct i40e_pf *pf = vsi->back;
386 u8 *raw_packet;
387 int ret;
388
389 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
390 if (!raw_packet)
391 return -ENOMEM;
392
393 i40e_create_dummy_udp_packet(raw_packet, ipv4, IPPROTO_UDP, fd_data);
394
395 if (ipv4)
396 ret = i40e_prepare_fdir_filter
397 (pf, fd_data, add, raw_packet,
398 I40E_UDPIP_DUMMY_PACKET_LEN,
399 I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
400 else
401 ret = i40e_prepare_fdir_filter
402 (pf, fd_data, add, raw_packet,
403 I40E_UDPIP6_DUMMY_PACKET_LEN,
404 I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
405
406 if (ret) {
407 kfree(raw_packet);
408 return ret;
409 }
410
411 i40e_change_filter_num(ipv4, add, &pf->fd_udp4_filter_cnt,
412 &pf->fd_udp6_filter_cnt);
413
414 return 0;
415}
416
417#define I40E_TCPIP_DUMMY_PACKET_LEN 54
418#define I40E_TCPIP6_DUMMY_PACKET_LEN 74
419/**
420 * i40e_add_del_fdir_tcp - Add/Remove TCPv4 filters
421 * @vsi: pointer to the targeted VSI
422 * @fd_data: the flow director data required for the FDir descriptor
423 * @add: true adds a filter, false removes it
424 * @ipv4: true is v4, false is v6
425 *
426 * Returns 0 if the filters were successfully added or removed
427 **/
428static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi,
429 struct i40e_fdir_filter *fd_data,
430 bool add,
431 bool ipv4)
432{
433 struct i40e_pf *pf = vsi->back;
434 u8 *raw_packet;
435 int ret;
436
437 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
438 if (!raw_packet)
439 return -ENOMEM;
440
441 i40e_create_dummy_tcp_packet(raw_packet, ipv4, IPPROTO_TCP, fd_data);
442 if (ipv4)
443 ret = i40e_prepare_fdir_filter
444 (pf, fd_data, add, raw_packet,
445 I40E_TCPIP_DUMMY_PACKET_LEN,
446 I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
447 else
448 ret = i40e_prepare_fdir_filter
449 (pf, fd_data, add, raw_packet,
450 I40E_TCPIP6_DUMMY_PACKET_LEN,
451 I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
452
453 if (ret) {
454 kfree(raw_packet);
455 return ret;
456 }
457
458 i40e_change_filter_num(ipv4, add, &pf->fd_tcp4_filter_cnt,
459 &pf->fd_tcp6_filter_cnt);
460
461 if (add) {
462 if (test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags) &&
463 I40E_DEBUG_FD & pf->hw.debug_mask)
464 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
465 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
466 }
467 return 0;
468}
469
470#define I40E_SCTPIP_DUMMY_PACKET_LEN 46
471#define I40E_SCTPIP6_DUMMY_PACKET_LEN 66
472/**
473 * i40e_add_del_fdir_sctp - Add/Remove SCTPv4 Flow Director filters for
474 * a specific flow spec
475 * @vsi: pointer to the targeted VSI
476 * @fd_data: the flow director data required for the FDir descriptor
477 * @add: true adds a filter, false removes it
478 * @ipv4: true is v4, false is v6
479 *
480 * Returns 0 if the filters were successfully added or removed
481 **/
482static int i40e_add_del_fdir_sctp(struct i40e_vsi *vsi,
483 struct i40e_fdir_filter *fd_data,
484 bool add,
485 bool ipv4)
486{
487 struct i40e_pf *pf = vsi->back;
488 u8 *raw_packet;
489 int ret;
490
491 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
492 if (!raw_packet)
493 return -ENOMEM;
494
495 i40e_create_dummy_sctp_packet(raw_packet, ipv4, IPPROTO_SCTP, fd_data);
496
497 if (ipv4)
498 ret = i40e_prepare_fdir_filter
499 (pf, fd_data, add, raw_packet,
500 I40E_SCTPIP_DUMMY_PACKET_LEN,
501 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
502 else
503 ret = i40e_prepare_fdir_filter
504 (pf, fd_data, add, raw_packet,
505 I40E_SCTPIP6_DUMMY_PACKET_LEN,
506 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
507
508 if (ret) {
509 kfree(raw_packet);
510 return ret;
511 }
512
513 i40e_change_filter_num(ipv4, add, &pf->fd_sctp4_filter_cnt,
514 &pf->fd_sctp6_filter_cnt);
515
516 return 0;
517}
518
519#define I40E_IP_DUMMY_PACKET_LEN 34
520#define I40E_IP6_DUMMY_PACKET_LEN 54
521/**
522 * i40e_add_del_fdir_ip - Add/Remove IPv4 Flow Director filters for
523 * a specific flow spec
524 * @vsi: pointer to the targeted VSI
525 * @fd_data: the flow director data required for the FDir descriptor
526 * @add: true adds a filter, false removes it
527 * @ipv4: true is v4, false is v6
528 *
529 * Returns 0 if the filters were successfully added or removed
530 **/
531static int i40e_add_del_fdir_ip(struct i40e_vsi *vsi,
532 struct i40e_fdir_filter *fd_data,
533 bool add,
534 bool ipv4)
535{
536 struct i40e_pf *pf = vsi->back;
537 int payload_offset;
538 u8 *raw_packet;
539 int iter_start;
540 int iter_end;
541 int ret;
542 int i;
543
544 if (ipv4) {
545 iter_start = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
546 iter_end = I40E_FILTER_PCTYPE_FRAG_IPV4;
547 } else {
548 iter_start = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
549 iter_end = I40E_FILTER_PCTYPE_FRAG_IPV6;
550 }
551
552 for (i = iter_start; i <= iter_end; i++) {
553 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
554 if (!raw_packet)
555 return -ENOMEM;
556
557 /* IPv6 no header option differs from IPv4 */
558 (void)i40e_create_dummy_packet
559 (raw_packet, ipv4, (ipv4) ? IPPROTO_IP : IPPROTO_NONE,
560 fd_data);
561
562 payload_offset = (ipv4) ? I40E_IP_DUMMY_PACKET_LEN :
563 I40E_IP6_DUMMY_PACKET_LEN;
564 ret = i40e_prepare_fdir_filter(pf, fd_data, add, raw_packet,
565 payload_offset, i);
566 if (ret)
567 goto err;
568 }
569
570 i40e_change_filter_num(ipv4, add, &pf->fd_ip4_filter_cnt,
571 &pf->fd_ip6_filter_cnt);
572
573 return 0;
574err:
575 kfree(raw_packet);
576 return ret;
577}
578
579/**
580 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
581 * @vsi: pointer to the targeted VSI
582 * @input: filter to add or delete
583 * @add: true adds a filter, false removes it
584 *
585 **/
586int i40e_add_del_fdir(struct i40e_vsi *vsi,
587 struct i40e_fdir_filter *input, bool add)
588{
589 enum ip_ver { ipv6 = 0, ipv4 = 1 };
590 struct i40e_pf *pf = vsi->back;
591 int ret;
592
593 switch (input->flow_type & ~FLOW_EXT) {
594 case TCP_V4_FLOW:
595 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4);
596 break;
597 case UDP_V4_FLOW:
598 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4);
599 break;
600 case SCTP_V4_FLOW:
601 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4);
602 break;
603 case TCP_V6_FLOW:
604 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6);
605 break;
606 case UDP_V6_FLOW:
607 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6);
608 break;
609 case SCTP_V6_FLOW:
610 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6);
611 break;
612 case IP_USER_FLOW:
613 switch (input->ipl4_proto) {
614 case IPPROTO_TCP:
615 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4);
616 break;
617 case IPPROTO_UDP:
618 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4);
619 break;
620 case IPPROTO_SCTP:
621 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4);
622 break;
623 case IPPROTO_IP:
624 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv4);
625 break;
626 default:
627 /* We cannot support masking based on protocol */
628 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n",
629 input->ipl4_proto);
630 return -EINVAL;
631 }
632 break;
633 case IPV6_USER_FLOW:
634 switch (input->ipl4_proto) {
635 case IPPROTO_TCP:
636 ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6);
637 break;
638 case IPPROTO_UDP:
639 ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6);
640 break;
641 case IPPROTO_SCTP:
642 ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6);
643 break;
644 case IPPROTO_IP:
645 ret = i40e_add_del_fdir_ip(vsi, input, add, ipv6);
646 break;
647 default:
648 /* We cannot support masking based on protocol */
649 dev_info(&pf->pdev->dev, "Unsupported IPv6 protocol 0x%02x\n",
650 input->ipl4_proto);
651 return -EINVAL;
652 }
653 break;
654 default:
655 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n",
656 input->flow_type);
657 return -EINVAL;
658 }
659
660 /* The buffer allocated here will be normally be freed by
661 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit
662 * completion. In the event of an error adding the buffer to the FDIR
663 * ring, it will immediately be freed. It may also be freed by
664 * i40e_clean_tx_ring() when closing the VSI.
665 */
666 return ret;
667}
668
669/**
670 * i40e_fd_handle_status - check the Programming Status for FD
671 * @rx_ring: the Rx ring for this descriptor
672 * @qword0_raw: qword0
673 * @qword1: qword1 after le_to_cpu
674 * @prog_id: the id originally used for programming
675 *
676 * This is used to verify if the FD programming or invalidation
677 * requested by SW to the HW is successful or not and take actions accordingly.
678 **/
679static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw,
680 u64 qword1, u8 prog_id)
681{
682 struct i40e_pf *pf = rx_ring->vsi->back;
683 struct pci_dev *pdev = pf->pdev;
684 struct i40e_16b_rx_wb_qw0 *qw0;
685 u32 fcnt_prog, fcnt_avail;
686 u32 error;
687
688 qw0 = (struct i40e_16b_rx_wb_qw0 *)&qword0_raw;
689 error = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK, qword1);
690
691 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
692 pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id);
693 if (qw0->hi_dword.fd_id != 0 ||
694 (I40E_DEBUG_FD & pf->hw.debug_mask))
695 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
696 pf->fd_inv);
697
698 /* Check if the programming error is for ATR.
699 * If so, auto disable ATR and set a state for
700 * flush in progress. Next time we come here if flush is in
701 * progress do nothing, once flush is complete the state will
702 * be cleared.
703 */
704 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
705 return;
706
707 pf->fd_add_err++;
708 /* store the current atr filter count */
709 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
710
711 if (qw0->hi_dword.fd_id == 0 &&
712 test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) {
713 /* These set_bit() calls aren't atomic with the
714 * test_bit() here, but worse case we potentially
715 * disable ATR and queue a flush right after SB
716 * support is re-enabled. That shouldn't cause an
717 * issue in practice
718 */
719 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
720 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
721 }
722
723 /* filter programming failed most likely due to table full */
724 fcnt_prog = i40e_get_global_fd_count(pf);
725 fcnt_avail = pf->fdir_pf_filter_count;
726 /* If ATR is running fcnt_prog can quickly change,
727 * if we are very close to full, it makes sense to disable
728 * FD ATR/SB and then re-enable it when there is room.
729 */
730 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
731 if (test_bit(I40E_FLAG_FD_SB_ENA, pf->flags) &&
732 !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED,
733 pf->state))
734 if (I40E_DEBUG_FD & pf->hw.debug_mask)
735 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
736 }
737 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
738 if (I40E_DEBUG_FD & pf->hw.debug_mask)
739 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
740 qw0->hi_dword.fd_id);
741 }
742}
743
744/**
745 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
746 * @ring: the ring that owns the buffer
747 * @tx_buffer: the buffer to free
748 **/
749static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
750 struct i40e_tx_buffer *tx_buffer)
751{
752 if (tx_buffer->skb) {
753 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
754 kfree(tx_buffer->raw_buf);
755 else if (ring_is_xdp(ring))
756 xdp_return_frame(tx_buffer->xdpf);
757 else
758 dev_kfree_skb_any(tx_buffer->skb);
759 if (dma_unmap_len(tx_buffer, len))
760 dma_unmap_single(ring->dev,
761 dma_unmap_addr(tx_buffer, dma),
762 dma_unmap_len(tx_buffer, len),
763 DMA_TO_DEVICE);
764 } else if (dma_unmap_len(tx_buffer, len)) {
765 dma_unmap_page(ring->dev,
766 dma_unmap_addr(tx_buffer, dma),
767 dma_unmap_len(tx_buffer, len),
768 DMA_TO_DEVICE);
769 }
770
771 tx_buffer->next_to_watch = NULL;
772 tx_buffer->skb = NULL;
773 dma_unmap_len_set(tx_buffer, len, 0);
774 /* tx_buffer must be completely set up in the transmit path */
775}
776
777/**
778 * i40e_clean_tx_ring - Free any empty Tx buffers
779 * @tx_ring: ring to be cleaned
780 **/
781void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
782{
783 unsigned long bi_size;
784 u16 i;
785
786 if (ring_is_xdp(tx_ring) && tx_ring->xsk_pool) {
787 i40e_xsk_clean_tx_ring(tx_ring);
788 } else {
789 /* ring already cleared, nothing to do */
790 if (!tx_ring->tx_bi)
791 return;
792
793 /* Free all the Tx ring sk_buffs */
794 for (i = 0; i < tx_ring->count; i++)
795 i40e_unmap_and_free_tx_resource(tx_ring,
796 &tx_ring->tx_bi[i]);
797 }
798
799 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
800 memset(tx_ring->tx_bi, 0, bi_size);
801
802 /* Zero out the descriptor ring */
803 memset(tx_ring->desc, 0, tx_ring->size);
804
805 tx_ring->next_to_use = 0;
806 tx_ring->next_to_clean = 0;
807
808 if (!tx_ring->netdev)
809 return;
810
811 /* cleanup Tx queue statistics */
812 netdev_tx_reset_queue(txring_txq(tx_ring));
813}
814
815/**
816 * i40e_free_tx_resources - Free Tx resources per queue
817 * @tx_ring: Tx descriptor ring for a specific queue
818 *
819 * Free all transmit software resources
820 **/
821void i40e_free_tx_resources(struct i40e_ring *tx_ring)
822{
823 i40e_clean_tx_ring(tx_ring);
824 kfree(tx_ring->tx_bi);
825 tx_ring->tx_bi = NULL;
826
827 if (tx_ring->desc) {
828 dma_free_coherent(tx_ring->dev, tx_ring->size,
829 tx_ring->desc, tx_ring->dma);
830 tx_ring->desc = NULL;
831 }
832}
833
834/**
835 * i40e_get_tx_pending - how many tx descriptors not processed
836 * @ring: the ring of descriptors
837 * @in_sw: use SW variables
838 *
839 * Since there is no access to the ring head register
840 * in XL710, we need to use our local copies
841 **/
842u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
843{
844 u32 head, tail;
845
846 if (!in_sw) {
847 head = i40e_get_head(ring);
848 tail = readl(ring->tail);
849 } else {
850 head = ring->next_to_clean;
851 tail = ring->next_to_use;
852 }
853
854 if (head != tail)
855 return (head < tail) ?
856 tail - head : (tail + ring->count - head);
857
858 return 0;
859}
860
861/**
862 * i40e_detect_recover_hung - Function to detect and recover hung_queues
863 * @vsi: pointer to vsi struct with tx queues
864 *
865 * VSI has netdev and netdev has TX queues. This function is to check each of
866 * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
867 **/
868void i40e_detect_recover_hung(struct i40e_vsi *vsi)
869{
870 struct i40e_ring *tx_ring = NULL;
871 struct net_device *netdev;
872 unsigned int i;
873 int packets;
874
875 if (!vsi)
876 return;
877
878 if (test_bit(__I40E_VSI_DOWN, vsi->state))
879 return;
880
881 netdev = vsi->netdev;
882 if (!netdev)
883 return;
884
885 if (!netif_carrier_ok(netdev))
886 return;
887
888 for (i = 0; i < vsi->num_queue_pairs; i++) {
889 tx_ring = vsi->tx_rings[i];
890 if (tx_ring && tx_ring->desc) {
891 /* If packet counter has not changed the queue is
892 * likely stalled, so force an interrupt for this
893 * queue.
894 *
895 * prev_pkt_ctr would be negative if there was no
896 * pending work.
897 */
898 packets = tx_ring->stats.packets & INT_MAX;
899 if (tx_ring->tx_stats.prev_pkt_ctr == packets) {
900 i40e_force_wb(vsi, tx_ring->q_vector);
901 continue;
902 }
903
904 /* Memory barrier between read of packet count and call
905 * to i40e_get_tx_pending()
906 */
907 smp_rmb();
908 tx_ring->tx_stats.prev_pkt_ctr =
909 i40e_get_tx_pending(tx_ring, true) ? packets : -1;
910 }
911 }
912}
913
914/**
915 * i40e_clean_tx_irq - Reclaim resources after transmit completes
916 * @vsi: the VSI we care about
917 * @tx_ring: Tx ring to clean
918 * @napi_budget: Used to determine if we are in netpoll
919 * @tx_cleaned: Out parameter set to the number of TXes cleaned
920 *
921 * Returns true if there's any budget left (e.g. the clean is finished)
922 **/
923static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
924 struct i40e_ring *tx_ring, int napi_budget,
925 unsigned int *tx_cleaned)
926{
927 int i = tx_ring->next_to_clean;
928 struct i40e_tx_buffer *tx_buf;
929 struct i40e_tx_desc *tx_head;
930 struct i40e_tx_desc *tx_desc;
931 unsigned int total_bytes = 0, total_packets = 0;
932 unsigned int budget = vsi->work_limit;
933
934 tx_buf = &tx_ring->tx_bi[i];
935 tx_desc = I40E_TX_DESC(tx_ring, i);
936 i -= tx_ring->count;
937
938 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
939
940 do {
941 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
942
943 /* if next_to_watch is not set then there is no work pending */
944 if (!eop_desc)
945 break;
946
947 /* prevent any other reads prior to eop_desc */
948 smp_rmb();
949
950 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
951 /* we have caught up to head, no work left to do */
952 if (tx_head == tx_desc)
953 break;
954
955 /* clear next_to_watch to prevent false hangs */
956 tx_buf->next_to_watch = NULL;
957
958 /* update the statistics for this packet */
959 total_bytes += tx_buf->bytecount;
960 total_packets += tx_buf->gso_segs;
961
962 /* free the skb/XDP data */
963 if (ring_is_xdp(tx_ring))
964 xdp_return_frame(tx_buf->xdpf);
965 else
966 napi_consume_skb(tx_buf->skb, napi_budget);
967
968 /* unmap skb header data */
969 dma_unmap_single(tx_ring->dev,
970 dma_unmap_addr(tx_buf, dma),
971 dma_unmap_len(tx_buf, len),
972 DMA_TO_DEVICE);
973
974 /* clear tx_buffer data */
975 tx_buf->skb = NULL;
976 dma_unmap_len_set(tx_buf, len, 0);
977
978 /* unmap remaining buffers */
979 while (tx_desc != eop_desc) {
980 i40e_trace(clean_tx_irq_unmap,
981 tx_ring, tx_desc, tx_buf);
982
983 tx_buf++;
984 tx_desc++;
985 i++;
986 if (unlikely(!i)) {
987 i -= tx_ring->count;
988 tx_buf = tx_ring->tx_bi;
989 tx_desc = I40E_TX_DESC(tx_ring, 0);
990 }
991
992 /* unmap any remaining paged data */
993 if (dma_unmap_len(tx_buf, len)) {
994 dma_unmap_page(tx_ring->dev,
995 dma_unmap_addr(tx_buf, dma),
996 dma_unmap_len(tx_buf, len),
997 DMA_TO_DEVICE);
998 dma_unmap_len_set(tx_buf, len, 0);
999 }
1000 }
1001
1002 /* move us one more past the eop_desc for start of next pkt */
1003 tx_buf++;
1004 tx_desc++;
1005 i++;
1006 if (unlikely(!i)) {
1007 i -= tx_ring->count;
1008 tx_buf = tx_ring->tx_bi;
1009 tx_desc = I40E_TX_DESC(tx_ring, 0);
1010 }
1011
1012 prefetch(tx_desc);
1013
1014 /* update budget accounting */
1015 budget--;
1016 } while (likely(budget));
1017
1018 i += tx_ring->count;
1019 tx_ring->next_to_clean = i;
1020 i40e_update_tx_stats(tx_ring, total_packets, total_bytes);
1021 i40e_arm_wb(tx_ring, vsi, budget);
1022
1023 if (ring_is_xdp(tx_ring))
1024 return !!budget;
1025
1026 /* notify netdev of completed buffers */
1027 netdev_tx_completed_queue(txring_txq(tx_ring),
1028 total_packets, total_bytes);
1029
1030#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
1031 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1032 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
1033 /* Make sure that anybody stopping the queue after this
1034 * sees the new next_to_clean.
1035 */
1036 smp_mb();
1037 if (__netif_subqueue_stopped(tx_ring->netdev,
1038 tx_ring->queue_index) &&
1039 !test_bit(__I40E_VSI_DOWN, vsi->state)) {
1040 netif_wake_subqueue(tx_ring->netdev,
1041 tx_ring->queue_index);
1042 ++tx_ring->tx_stats.restart_queue;
1043 }
1044 }
1045
1046 *tx_cleaned = total_packets;
1047 return !!budget;
1048}
1049
1050/**
1051 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
1052 * @vsi: the VSI we care about
1053 * @q_vector: the vector on which to enable writeback
1054 *
1055 **/
1056static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
1057 struct i40e_q_vector *q_vector)
1058{
1059 u16 flags = q_vector->tx.ring[0].flags;
1060 u32 val;
1061
1062 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
1063 return;
1064
1065 if (q_vector->arm_wb_state)
1066 return;
1067
1068 if (test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) {
1069 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
1070 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
1071
1072 wr32(&vsi->back->hw,
1073 I40E_PFINT_DYN_CTLN(q_vector->reg_idx),
1074 val);
1075 } else {
1076 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
1077 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
1078
1079 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
1080 }
1081 q_vector->arm_wb_state = true;
1082}
1083
1084/**
1085 * i40e_force_wb - Issue SW Interrupt so HW does a wb
1086 * @vsi: the VSI we care about
1087 * @q_vector: the vector on which to force writeback
1088 *
1089 **/
1090void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
1091{
1092 if (test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) {
1093 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1094 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
1095 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
1096 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
1097 /* allow 00 to be written to the index */
1098
1099 wr32(&vsi->back->hw,
1100 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val);
1101 } else {
1102 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
1103 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
1104 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
1105 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
1106 /* allow 00 to be written to the index */
1107
1108 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
1109 }
1110}
1111
1112static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector,
1113 struct i40e_ring_container *rc)
1114{
1115 return &q_vector->rx == rc;
1116}
1117
1118static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector)
1119{
1120 unsigned int divisor;
1121
1122 switch (q_vector->vsi->back->hw.phy.link_info.link_speed) {
1123 case I40E_LINK_SPEED_40GB:
1124 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024;
1125 break;
1126 case I40E_LINK_SPEED_25GB:
1127 case I40E_LINK_SPEED_20GB:
1128 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512;
1129 break;
1130 default:
1131 case I40E_LINK_SPEED_10GB:
1132 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256;
1133 break;
1134 case I40E_LINK_SPEED_1GB:
1135 case I40E_LINK_SPEED_100MB:
1136 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32;
1137 break;
1138 }
1139
1140 return divisor;
1141}
1142
1143/**
1144 * i40e_update_itr - update the dynamic ITR value based on statistics
1145 * @q_vector: structure containing interrupt and ring information
1146 * @rc: structure containing ring performance data
1147 *
1148 * Stores a new ITR value based on packets and byte
1149 * counts during the last interrupt. The advantage of per interrupt
1150 * computation is faster updates and more accurate ITR for the current
1151 * traffic pattern. Constants in this function were computed
1152 * based on theoretical maximum wire speed and thresholds were set based
1153 * on testing data as well as attempting to minimize response time
1154 * while increasing bulk throughput.
1155 **/
1156static void i40e_update_itr(struct i40e_q_vector *q_vector,
1157 struct i40e_ring_container *rc)
1158{
1159 unsigned int avg_wire_size, packets, bytes, itr;
1160 unsigned long next_update = jiffies;
1161
1162 /* If we don't have any rings just leave ourselves set for maximum
1163 * possible latency so we take ourselves out of the equation.
1164 */
1165 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
1166 return;
1167
1168 /* For Rx we want to push the delay up and default to low latency.
1169 * for Tx we want to pull the delay down and default to high latency.
1170 */
1171 itr = i40e_container_is_rx(q_vector, rc) ?
1172 I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY :
1173 I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY;
1174
1175 /* If we didn't update within up to 1 - 2 jiffies we can assume
1176 * that either packets are coming in so slow there hasn't been
1177 * any work, or that there is so much work that NAPI is dealing
1178 * with interrupt moderation and we don't need to do anything.
1179 */
1180 if (time_after(next_update, rc->next_update))
1181 goto clear_counts;
1182
1183 /* If itr_countdown is set it means we programmed an ITR within
1184 * the last 4 interrupt cycles. This has a side effect of us
1185 * potentially firing an early interrupt. In order to work around
1186 * this we need to throw out any data received for a few
1187 * interrupts following the update.
1188 */
1189 if (q_vector->itr_countdown) {
1190 itr = rc->target_itr;
1191 goto clear_counts;
1192 }
1193
1194 packets = rc->total_packets;
1195 bytes = rc->total_bytes;
1196
1197 if (i40e_container_is_rx(q_vector, rc)) {
1198 /* If Rx there are 1 to 4 packets and bytes are less than
1199 * 9000 assume insufficient data to use bulk rate limiting
1200 * approach unless Tx is already in bulk rate limiting. We
1201 * are likely latency driven.
1202 */
1203 if (packets && packets < 4 && bytes < 9000 &&
1204 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) {
1205 itr = I40E_ITR_ADAPTIVE_LATENCY;
1206 goto adjust_by_size;
1207 }
1208 } else if (packets < 4) {
1209 /* If we have Tx and Rx ITR maxed and Tx ITR is running in
1210 * bulk mode and we are receiving 4 or fewer packets just
1211 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
1212 * that the Rx can relax.
1213 */
1214 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS &&
1215 (q_vector->rx.target_itr & I40E_ITR_MASK) ==
1216 I40E_ITR_ADAPTIVE_MAX_USECS)
1217 goto clear_counts;
1218 } else if (packets > 32) {
1219 /* If we have processed over 32 packets in a single interrupt
1220 * for Tx assume we need to switch over to "bulk" mode.
1221 */
1222 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY;
1223 }
1224
1225 /* We have no packets to actually measure against. This means
1226 * either one of the other queues on this vector is active or
1227 * we are a Tx queue doing TSO with too high of an interrupt rate.
1228 *
1229 * Between 4 and 56 we can assume that our current interrupt delay
1230 * is only slightly too low. As such we should increase it by a small
1231 * fixed amount.
1232 */
1233 if (packets < 56) {
1234 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC;
1235 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1236 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1237 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1238 }
1239 goto clear_counts;
1240 }
1241
1242 if (packets <= 256) {
1243 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
1244 itr &= I40E_ITR_MASK;
1245
1246 /* Between 56 and 112 is our "goldilocks" zone where we are
1247 * working out "just right". Just report that our current
1248 * ITR is good for us.
1249 */
1250 if (packets <= 112)
1251 goto clear_counts;
1252
1253 /* If packet count is 128 or greater we are likely looking
1254 * at a slight overrun of the delay we want. Try halving
1255 * our delay to see if that will cut the number of packets
1256 * in half per interrupt.
1257 */
1258 itr /= 2;
1259 itr &= I40E_ITR_MASK;
1260 if (itr < I40E_ITR_ADAPTIVE_MIN_USECS)
1261 itr = I40E_ITR_ADAPTIVE_MIN_USECS;
1262
1263 goto clear_counts;
1264 }
1265
1266 /* The paths below assume we are dealing with a bulk ITR since
1267 * number of packets is greater than 256. We are just going to have
1268 * to compute a value and try to bring the count under control,
1269 * though for smaller packet sizes there isn't much we can do as
1270 * NAPI polling will likely be kicking in sooner rather than later.
1271 */
1272 itr = I40E_ITR_ADAPTIVE_BULK;
1273
1274adjust_by_size:
1275 /* If packet counts are 256 or greater we can assume we have a gross
1276 * overestimation of what the rate should be. Instead of trying to fine
1277 * tune it just use the formula below to try and dial in an exact value
1278 * give the current packet size of the frame.
1279 */
1280 avg_wire_size = bytes / packets;
1281
1282 /* The following is a crude approximation of:
1283 * wmem_default / (size + overhead) = desired_pkts_per_int
1284 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
1285 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1286 *
1287 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1288 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1289 * formula down to
1290 *
1291 * (170 * (size + 24)) / (size + 640) = ITR
1292 *
1293 * We first do some math on the packet size and then finally bitshift
1294 * by 8 after rounding up. We also have to account for PCIe link speed
1295 * difference as ITR scales based on this.
1296 */
1297 if (avg_wire_size <= 60) {
1298 /* Start at 250k ints/sec */
1299 avg_wire_size = 4096;
1300 } else if (avg_wire_size <= 380) {
1301 /* 250K ints/sec to 60K ints/sec */
1302 avg_wire_size *= 40;
1303 avg_wire_size += 1696;
1304 } else if (avg_wire_size <= 1084) {
1305 /* 60K ints/sec to 36K ints/sec */
1306 avg_wire_size *= 15;
1307 avg_wire_size += 11452;
1308 } else if (avg_wire_size <= 1980) {
1309 /* 36K ints/sec to 30K ints/sec */
1310 avg_wire_size *= 5;
1311 avg_wire_size += 22420;
1312 } else {
1313 /* plateau at a limit of 30K ints/sec */
1314 avg_wire_size = 32256;
1315 }
1316
1317 /* If we are in low latency mode halve our delay which doubles the
1318 * rate to somewhere between 100K to 16K ints/sec
1319 */
1320 if (itr & I40E_ITR_ADAPTIVE_LATENCY)
1321 avg_wire_size /= 2;
1322
1323 /* Resultant value is 256 times larger than it needs to be. This
1324 * gives us room to adjust the value as needed to either increase
1325 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
1326 *
1327 * Use addition as we have already recorded the new latency flag
1328 * for the ITR value.
1329 */
1330 itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) *
1331 I40E_ITR_ADAPTIVE_MIN_INC;
1332
1333 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1334 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1335 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1336 }
1337
1338clear_counts:
1339 /* write back value */
1340 rc->target_itr = itr;
1341
1342 /* next update should occur within next jiffy */
1343 rc->next_update = next_update + 1;
1344
1345 rc->total_bytes = 0;
1346 rc->total_packets = 0;
1347}
1348
1349static struct i40e_rx_buffer *i40e_rx_bi(struct i40e_ring *rx_ring, u32 idx)
1350{
1351 return &rx_ring->rx_bi[idx];
1352}
1353
1354/**
1355 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
1356 * @rx_ring: rx descriptor ring to store buffers on
1357 * @old_buff: donor buffer to have page reused
1358 *
1359 * Synchronizes page for reuse by the adapter
1360 **/
1361static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
1362 struct i40e_rx_buffer *old_buff)
1363{
1364 struct i40e_rx_buffer *new_buff;
1365 u16 nta = rx_ring->next_to_alloc;
1366
1367 new_buff = i40e_rx_bi(rx_ring, nta);
1368
1369 /* update, and store next to alloc */
1370 nta++;
1371 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1372
1373 /* transfer page from old buffer to new buffer */
1374 new_buff->dma = old_buff->dma;
1375 new_buff->page = old_buff->page;
1376 new_buff->page_offset = old_buff->page_offset;
1377 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1378
1379 /* clear contents of buffer_info */
1380 old_buff->page = NULL;
1381}
1382
1383/**
1384 * i40e_clean_programming_status - clean the programming status descriptor
1385 * @rx_ring: the rx ring that has this descriptor
1386 * @qword0_raw: qword0
1387 * @qword1: qword1 representing status_error_len in CPU ordering
1388 *
1389 * Flow director should handle FD_FILTER_STATUS to check its filter programming
1390 * status being successful or not and take actions accordingly. FCoE should
1391 * handle its context/filter programming/invalidation status and take actions.
1392 *
1393 * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL.
1394 **/
1395void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw,
1396 u64 qword1)
1397{
1398 u8 id;
1399
1400 id = FIELD_GET(I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK, qword1);
1401
1402 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
1403 i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id);
1404}
1405
1406/**
1407 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
1408 * @tx_ring: the tx ring to set up
1409 *
1410 * Return 0 on success, negative on error
1411 **/
1412int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
1413{
1414 struct device *dev = tx_ring->dev;
1415 int bi_size;
1416
1417 if (!dev)
1418 return -ENOMEM;
1419
1420 /* warn if we are about to overwrite the pointer */
1421 WARN_ON(tx_ring->tx_bi);
1422 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1423 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1424 if (!tx_ring->tx_bi)
1425 goto err;
1426
1427 u64_stats_init(&tx_ring->syncp);
1428
1429 /* round up to nearest 4K */
1430 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1431 /* add u32 for head writeback, align after this takes care of
1432 * guaranteeing this is at least one cache line in size
1433 */
1434 tx_ring->size += sizeof(u32);
1435 tx_ring->size = ALIGN(tx_ring->size, 4096);
1436 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1437 &tx_ring->dma, GFP_KERNEL);
1438 if (!tx_ring->desc) {
1439 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1440 tx_ring->size);
1441 goto err;
1442 }
1443
1444 tx_ring->next_to_use = 0;
1445 tx_ring->next_to_clean = 0;
1446 tx_ring->tx_stats.prev_pkt_ctr = -1;
1447 return 0;
1448
1449err:
1450 kfree(tx_ring->tx_bi);
1451 tx_ring->tx_bi = NULL;
1452 return -ENOMEM;
1453}
1454
1455static void i40e_clear_rx_bi(struct i40e_ring *rx_ring)
1456{
1457 memset(rx_ring->rx_bi, 0, sizeof(*rx_ring->rx_bi) * rx_ring->count);
1458}
1459
1460/**
1461 * i40e_clean_rx_ring - Free Rx buffers
1462 * @rx_ring: ring to be cleaned
1463 **/
1464void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1465{
1466 u16 i;
1467
1468 /* ring already cleared, nothing to do */
1469 if (!rx_ring->rx_bi)
1470 return;
1471
1472 if (rx_ring->xsk_pool) {
1473 i40e_xsk_clean_rx_ring(rx_ring);
1474 goto skip_free;
1475 }
1476
1477 /* Free all the Rx ring sk_buffs */
1478 for (i = 0; i < rx_ring->count; i++) {
1479 struct i40e_rx_buffer *rx_bi = i40e_rx_bi(rx_ring, i);
1480
1481 if (!rx_bi->page)
1482 continue;
1483
1484 /* Invalidate cache lines that may have been written to by
1485 * device so that we avoid corrupting memory.
1486 */
1487 dma_sync_single_range_for_cpu(rx_ring->dev,
1488 rx_bi->dma,
1489 rx_bi->page_offset,
1490 rx_ring->rx_buf_len,
1491 DMA_FROM_DEVICE);
1492
1493 /* free resources associated with mapping */
1494 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
1495 i40e_rx_pg_size(rx_ring),
1496 DMA_FROM_DEVICE,
1497 I40E_RX_DMA_ATTR);
1498
1499 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
1500
1501 rx_bi->page = NULL;
1502 rx_bi->page_offset = 0;
1503 }
1504
1505skip_free:
1506 if (rx_ring->xsk_pool)
1507 i40e_clear_rx_bi_zc(rx_ring);
1508 else
1509 i40e_clear_rx_bi(rx_ring);
1510
1511 /* Zero out the descriptor ring */
1512 memset(rx_ring->desc, 0, rx_ring->size);
1513
1514 rx_ring->next_to_alloc = 0;
1515 rx_ring->next_to_clean = 0;
1516 rx_ring->next_to_process = 0;
1517 rx_ring->next_to_use = 0;
1518}
1519
1520/**
1521 * i40e_free_rx_resources - Free Rx resources
1522 * @rx_ring: ring to clean the resources from
1523 *
1524 * Free all receive software resources
1525 **/
1526void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1527{
1528 i40e_clean_rx_ring(rx_ring);
1529 if (rx_ring->vsi->type == I40E_VSI_MAIN)
1530 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
1531 rx_ring->xdp_prog = NULL;
1532 kfree(rx_ring->rx_bi);
1533 rx_ring->rx_bi = NULL;
1534
1535 if (rx_ring->desc) {
1536 dma_free_coherent(rx_ring->dev, rx_ring->size,
1537 rx_ring->desc, rx_ring->dma);
1538 rx_ring->desc = NULL;
1539 }
1540}
1541
1542/**
1543 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1544 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1545 *
1546 * Returns 0 on success, negative on failure
1547 **/
1548int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1549{
1550 struct device *dev = rx_ring->dev;
1551
1552 u64_stats_init(&rx_ring->syncp);
1553
1554 /* Round up to nearest 4K */
1555 rx_ring->size = rx_ring->count * sizeof(union i40e_rx_desc);
1556 rx_ring->size = ALIGN(rx_ring->size, 4096);
1557 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1558 &rx_ring->dma, GFP_KERNEL);
1559
1560 if (!rx_ring->desc) {
1561 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1562 rx_ring->size);
1563 return -ENOMEM;
1564 }
1565
1566 rx_ring->next_to_alloc = 0;
1567 rx_ring->next_to_clean = 0;
1568 rx_ring->next_to_process = 0;
1569 rx_ring->next_to_use = 0;
1570
1571 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog;
1572
1573 rx_ring->rx_bi =
1574 kcalloc(rx_ring->count, sizeof(*rx_ring->rx_bi), GFP_KERNEL);
1575 if (!rx_ring->rx_bi)
1576 return -ENOMEM;
1577
1578 return 0;
1579}
1580
1581/**
1582 * i40e_release_rx_desc - Store the new tail and head values
1583 * @rx_ring: ring to bump
1584 * @val: new head index
1585 **/
1586void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1587{
1588 rx_ring->next_to_use = val;
1589
1590 /* update next to alloc since we have filled the ring */
1591 rx_ring->next_to_alloc = val;
1592
1593 /* Force memory writes to complete before letting h/w
1594 * know there are new descriptors to fetch. (Only
1595 * applicable for weak-ordered memory model archs,
1596 * such as IA-64).
1597 */
1598 wmb();
1599 writel(val, rx_ring->tail);
1600}
1601
1602#if (PAGE_SIZE >= 8192)
1603static unsigned int i40e_rx_frame_truesize(struct i40e_ring *rx_ring,
1604 unsigned int size)
1605{
1606 unsigned int truesize;
1607
1608 truesize = rx_ring->rx_offset ?
1609 SKB_DATA_ALIGN(size + rx_ring->rx_offset) +
1610 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
1611 SKB_DATA_ALIGN(size);
1612 return truesize;
1613}
1614#endif
1615
1616/**
1617 * i40e_alloc_mapped_page - recycle or make a new page
1618 * @rx_ring: ring to use
1619 * @bi: rx_buffer struct to modify
1620 *
1621 * Returns true if the page was successfully allocated or
1622 * reused.
1623 **/
1624static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
1625 struct i40e_rx_buffer *bi)
1626{
1627 struct page *page = bi->page;
1628 dma_addr_t dma;
1629
1630 /* since we are recycling buffers we should seldom need to alloc */
1631 if (likely(page)) {
1632 rx_ring->rx_stats.page_reuse_count++;
1633 return true;
1634 }
1635
1636 /* alloc new page for storage */
1637 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
1638 if (unlikely(!page)) {
1639 rx_ring->rx_stats.alloc_page_failed++;
1640 return false;
1641 }
1642
1643 rx_ring->rx_stats.page_alloc_count++;
1644
1645 /* map page for use */
1646 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1647 i40e_rx_pg_size(rx_ring),
1648 DMA_FROM_DEVICE,
1649 I40E_RX_DMA_ATTR);
1650
1651 /* if mapping failed free memory back to system since
1652 * there isn't much point in holding memory we can't use
1653 */
1654 if (dma_mapping_error(rx_ring->dev, dma)) {
1655 __free_pages(page, i40e_rx_pg_order(rx_ring));
1656 rx_ring->rx_stats.alloc_page_failed++;
1657 return false;
1658 }
1659
1660 bi->dma = dma;
1661 bi->page = page;
1662 bi->page_offset = rx_ring->rx_offset;
1663 page_ref_add(page, USHRT_MAX - 1);
1664 bi->pagecnt_bias = USHRT_MAX;
1665
1666 return true;
1667}
1668
1669/**
1670 * i40e_alloc_rx_buffers - Replace used receive buffers
1671 * @rx_ring: ring to place buffers on
1672 * @cleaned_count: number of buffers to replace
1673 *
1674 * Returns false if all allocations were successful, true if any fail
1675 **/
1676bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1677{
1678 u16 ntu = rx_ring->next_to_use;
1679 union i40e_rx_desc *rx_desc;
1680 struct i40e_rx_buffer *bi;
1681
1682 /* do nothing if no valid netdev defined */
1683 if (!rx_ring->netdev || !cleaned_count)
1684 return false;
1685
1686 rx_desc = I40E_RX_DESC(rx_ring, ntu);
1687 bi = i40e_rx_bi(rx_ring, ntu);
1688
1689 do {
1690 if (!i40e_alloc_mapped_page(rx_ring, bi))
1691 goto no_buffers;
1692
1693 /* sync the buffer for use by the device */
1694 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1695 bi->page_offset,
1696 rx_ring->rx_buf_len,
1697 DMA_FROM_DEVICE);
1698
1699 /* Refresh the desc even if buffer_addrs didn't change
1700 * because each write-back erases this info.
1701 */
1702 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1703
1704 rx_desc++;
1705 bi++;
1706 ntu++;
1707 if (unlikely(ntu == rx_ring->count)) {
1708 rx_desc = I40E_RX_DESC(rx_ring, 0);
1709 bi = i40e_rx_bi(rx_ring, 0);
1710 ntu = 0;
1711 }
1712
1713 /* clear the status bits for the next_to_use descriptor */
1714 rx_desc->wb.qword1.status_error_len = 0;
1715
1716 cleaned_count--;
1717 } while (cleaned_count);
1718
1719 if (rx_ring->next_to_use != ntu)
1720 i40e_release_rx_desc(rx_ring, ntu);
1721
1722 return false;
1723
1724no_buffers:
1725 if (rx_ring->next_to_use != ntu)
1726 i40e_release_rx_desc(rx_ring, ntu);
1727
1728 /* make sure to come back via polling to try again after
1729 * allocation failure
1730 */
1731 return true;
1732}
1733
1734/**
1735 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1736 * @vsi: the VSI we care about
1737 * @skb: skb currently being received and modified
1738 * @rx_desc: the receive descriptor
1739 **/
1740static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1741 struct sk_buff *skb,
1742 union i40e_rx_desc *rx_desc)
1743{
1744 struct i40e_rx_ptype_decoded decoded;
1745 u32 rx_error, rx_status;
1746 bool ipv4, ipv6;
1747 u8 ptype;
1748 u64 qword;
1749
1750 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1751 ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword);
1752 rx_error = FIELD_GET(I40E_RXD_QW1_ERROR_MASK, qword);
1753 rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword);
1754 decoded = decode_rx_desc_ptype(ptype);
1755
1756 skb->ip_summed = CHECKSUM_NONE;
1757
1758 skb_checksum_none_assert(skb);
1759
1760 /* Rx csum enabled and ip headers found? */
1761 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1762 return;
1763
1764 /* did the hardware decode the packet and checksum? */
1765 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1766 return;
1767
1768 /* both known and outer_ip must be set for the below code to work */
1769 if (!(decoded.known && decoded.outer_ip))
1770 return;
1771
1772 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1773 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
1774 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1775 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1776
1777 if (ipv4 &&
1778 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1779 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1780 goto checksum_fail;
1781
1782 /* likely incorrect csum if alternate IP extension headers found */
1783 if (ipv6 &&
1784 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1785 /* don't increment checksum err here, non-fatal err */
1786 return;
1787
1788 /* there was some L4 error, count error and punt packet to the stack */
1789 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1790 goto checksum_fail;
1791
1792 /* handle packets that were not able to be checksummed due
1793 * to arrival speed, in this case the stack can compute
1794 * the csum.
1795 */
1796 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1797 return;
1798
1799 /* If there is an outer header present that might contain a checksum
1800 * we need to bump the checksum level by 1 to reflect the fact that
1801 * we are indicating we validated the inner checksum.
1802 */
1803 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
1804 skb->csum_level = 1;
1805
1806 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
1807 switch (decoded.inner_prot) {
1808 case I40E_RX_PTYPE_INNER_PROT_TCP:
1809 case I40E_RX_PTYPE_INNER_PROT_UDP:
1810 case I40E_RX_PTYPE_INNER_PROT_SCTP:
1811 skb->ip_summed = CHECKSUM_UNNECESSARY;
1812 fallthrough;
1813 default:
1814 break;
1815 }
1816
1817 return;
1818
1819checksum_fail:
1820 vsi->back->hw_csum_rx_error++;
1821}
1822
1823/**
1824 * i40e_ptype_to_htype - get a hash type
1825 * @ptype: the ptype value from the descriptor
1826 *
1827 * Returns a hash type to be used by skb_set_hash
1828 **/
1829static inline int i40e_ptype_to_htype(u8 ptype)
1830{
1831 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1832
1833 if (!decoded.known)
1834 return PKT_HASH_TYPE_NONE;
1835
1836 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1837 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1838 return PKT_HASH_TYPE_L4;
1839 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1840 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1841 return PKT_HASH_TYPE_L3;
1842 else
1843 return PKT_HASH_TYPE_L2;
1844}
1845
1846/**
1847 * i40e_rx_hash - set the hash value in the skb
1848 * @ring: descriptor ring
1849 * @rx_desc: specific descriptor
1850 * @skb: skb currently being received and modified
1851 * @rx_ptype: Rx packet type
1852 **/
1853static inline void i40e_rx_hash(struct i40e_ring *ring,
1854 union i40e_rx_desc *rx_desc,
1855 struct sk_buff *skb,
1856 u8 rx_ptype)
1857{
1858 u32 hash;
1859 const __le64 rss_mask =
1860 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1861 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1862
1863 if (!(ring->netdev->features & NETIF_F_RXHASH))
1864 return;
1865
1866 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1867 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1868 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1869 }
1870}
1871
1872/**
1873 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
1874 * @rx_ring: rx descriptor ring packet is being transacted on
1875 * @rx_desc: pointer to the EOP Rx descriptor
1876 * @skb: pointer to current skb being populated
1877 *
1878 * This function checks the ring, descriptor, and packet information in
1879 * order to populate the hash, checksum, VLAN, protocol, and
1880 * other fields within the skb.
1881 **/
1882void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1883 union i40e_rx_desc *rx_desc, struct sk_buff *skb)
1884{
1885 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1886 u32 rx_status = FIELD_GET(I40E_RXD_QW1_STATUS_MASK, qword);
1887 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
1888 u32 tsyn = FIELD_GET(I40E_RXD_QW1_STATUS_TSYNINDX_MASK, rx_status);
1889 u8 rx_ptype = FIELD_GET(I40E_RXD_QW1_PTYPE_MASK, qword);
1890
1891 if (unlikely(tsynvalid))
1892 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1893
1894 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1895
1896 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
1897
1898 skb_record_rx_queue(skb, rx_ring->queue_index);
1899
1900 if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1901 __le16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;
1902
1903 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1904 le16_to_cpu(vlan_tag));
1905 }
1906
1907 /* modifies the skb - consumes the enet header */
1908 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1909}
1910
1911/**
1912 * i40e_cleanup_headers - Correct empty headers
1913 * @rx_ring: rx descriptor ring packet is being transacted on
1914 * @skb: pointer to current skb being fixed
1915 * @rx_desc: pointer to the EOP Rx descriptor
1916 *
1917 * In addition if skb is not at least 60 bytes we need to pad it so that
1918 * it is large enough to qualify as a valid Ethernet frame.
1919 *
1920 * Returns true if an error was encountered and skb was freed.
1921 **/
1922static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb,
1923 union i40e_rx_desc *rx_desc)
1924
1925{
1926 /* ERR_MASK will only have valid bits if EOP set, and
1927 * what we are doing here is actually checking
1928 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1929 * the error field
1930 */
1931 if (unlikely(i40e_test_staterr(rx_desc,
1932 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1933 dev_kfree_skb_any(skb);
1934 return true;
1935 }
1936
1937 /* if eth_skb_pad returns an error the skb was freed */
1938 if (eth_skb_pad(skb))
1939 return true;
1940
1941 return false;
1942}
1943
1944/**
1945 * i40e_can_reuse_rx_page - Determine if page can be reused for another Rx
1946 * @rx_buffer: buffer containing the page
1947 * @rx_stats: rx stats structure for the rx ring
1948 *
1949 * If page is reusable, we have a green light for calling i40e_reuse_rx_page,
1950 * which will assign the current buffer to the buffer that next_to_alloc is
1951 * pointing to; otherwise, the DMA mapping needs to be destroyed and
1952 * page freed.
1953 *
1954 * rx_stats will be updated to indicate whether the page was waived
1955 * or busy if it could not be reused.
1956 */
1957static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer,
1958 struct i40e_rx_queue_stats *rx_stats)
1959{
1960 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1961 struct page *page = rx_buffer->page;
1962
1963 /* Is any reuse possible? */
1964 if (!dev_page_is_reusable(page)) {
1965 rx_stats->page_waive_count++;
1966 return false;
1967 }
1968
1969#if (PAGE_SIZE < 8192)
1970 /* if we are only owner of page we can reuse it */
1971 if (unlikely((rx_buffer->page_count - pagecnt_bias) > 1)) {
1972 rx_stats->page_busy_count++;
1973 return false;
1974 }
1975#else
1976#define I40E_LAST_OFFSET \
1977 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
1978 if (rx_buffer->page_offset > I40E_LAST_OFFSET) {
1979 rx_stats->page_busy_count++;
1980 return false;
1981 }
1982#endif
1983
1984 /* If we have drained the page fragment pool we need to update
1985 * the pagecnt_bias and page count so that we fully restock the
1986 * number of references the driver holds.
1987 */
1988 if (unlikely(pagecnt_bias == 1)) {
1989 page_ref_add(page, USHRT_MAX - 1);
1990 rx_buffer->pagecnt_bias = USHRT_MAX;
1991 }
1992
1993 return true;
1994}
1995
1996/**
1997 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region
1998 * @rx_buffer: Rx buffer to adjust
1999 * @truesize: Size of adjustment
2000 **/
2001static void i40e_rx_buffer_flip(struct i40e_rx_buffer *rx_buffer,
2002 unsigned int truesize)
2003{
2004#if (PAGE_SIZE < 8192)
2005 rx_buffer->page_offset ^= truesize;
2006#else
2007 rx_buffer->page_offset += truesize;
2008#endif
2009}
2010
2011/**
2012 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
2013 * @rx_ring: rx descriptor ring to transact packets on
2014 * @size: size of buffer to add to skb
2015 *
2016 * This function will pull an Rx buffer from the ring and synchronize it
2017 * for use by the CPU.
2018 */
2019static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
2020 const unsigned int size)
2021{
2022 struct i40e_rx_buffer *rx_buffer;
2023
2024 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_process);
2025 rx_buffer->page_count =
2026#if (PAGE_SIZE < 8192)
2027 page_count(rx_buffer->page);
2028#else
2029 0;
2030#endif
2031 prefetch_page_address(rx_buffer->page);
2032
2033 /* we are reusing so sync this buffer for CPU use */
2034 dma_sync_single_range_for_cpu(rx_ring->dev,
2035 rx_buffer->dma,
2036 rx_buffer->page_offset,
2037 size,
2038 DMA_FROM_DEVICE);
2039
2040 /* We have pulled a buffer for use, so decrement pagecnt_bias */
2041 rx_buffer->pagecnt_bias--;
2042
2043 return rx_buffer;
2044}
2045
2046/**
2047 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
2048 * @rx_ring: rx descriptor ring to transact packets on
2049 * @rx_buffer: rx buffer to pull data from
2050 *
2051 * This function will clean up the contents of the rx_buffer. It will
2052 * either recycle the buffer or unmap it and free the associated resources.
2053 */
2054static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
2055 struct i40e_rx_buffer *rx_buffer)
2056{
2057 if (i40e_can_reuse_rx_page(rx_buffer, &rx_ring->rx_stats)) {
2058 /* hand second half of page back to the ring */
2059 i40e_reuse_rx_page(rx_ring, rx_buffer);
2060 } else {
2061 /* we are not reusing the buffer so unmap it */
2062 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2063 i40e_rx_pg_size(rx_ring),
2064 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
2065 __page_frag_cache_drain(rx_buffer->page,
2066 rx_buffer->pagecnt_bias);
2067 /* clear contents of buffer_info */
2068 rx_buffer->page = NULL;
2069 }
2070}
2071
2072/**
2073 * i40e_process_rx_buffs- Processing of buffers post XDP prog or on error
2074 * @rx_ring: Rx descriptor ring to transact packets on
2075 * @xdp_res: Result of the XDP program
2076 * @xdp: xdp_buff pointing to the data
2077 **/
2078static void i40e_process_rx_buffs(struct i40e_ring *rx_ring, int xdp_res,
2079 struct xdp_buff *xdp)
2080{
2081 u32 nr_frags = xdp_get_shared_info_from_buff(xdp)->nr_frags;
2082 u32 next = rx_ring->next_to_clean, i = 0;
2083 struct i40e_rx_buffer *rx_buffer;
2084
2085 xdp->flags = 0;
2086
2087 while (1) {
2088 rx_buffer = i40e_rx_bi(rx_ring, next);
2089 if (++next == rx_ring->count)
2090 next = 0;
2091
2092 if (!rx_buffer->page)
2093 continue;
2094
2095 if (xdp_res != I40E_XDP_CONSUMED)
2096 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz);
2097 else if (i++ <= nr_frags)
2098 rx_buffer->pagecnt_bias++;
2099
2100 /* EOP buffer will be put in i40e_clean_rx_irq() */
2101 if (next == rx_ring->next_to_process)
2102 return;
2103
2104 i40e_put_rx_buffer(rx_ring, rx_buffer);
2105 }
2106}
2107
2108/**
2109 * i40e_construct_skb - Allocate skb and populate it
2110 * @rx_ring: rx descriptor ring to transact packets on
2111 * @xdp: xdp_buff pointing to the data
2112 *
2113 * This function allocates an skb. It then populates it with the page
2114 * data from the current receive descriptor, taking care to set up the
2115 * skb correctly.
2116 */
2117static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
2118 struct xdp_buff *xdp)
2119{
2120 unsigned int size = xdp->data_end - xdp->data;
2121 struct i40e_rx_buffer *rx_buffer;
2122 struct skb_shared_info *sinfo;
2123 unsigned int headlen;
2124 struct sk_buff *skb;
2125 u32 nr_frags = 0;
2126
2127 /* prefetch first cache line of first page */
2128 net_prefetch(xdp->data);
2129
2130 /* Note, we get here by enabling legacy-rx via:
2131 *
2132 * ethtool --set-priv-flags <dev> legacy-rx on
2133 *
2134 * In this mode, we currently get 0 extra XDP headroom as
2135 * opposed to having legacy-rx off, where we process XDP
2136 * packets going to stack via i40e_build_skb(). The latter
2137 * provides us currently with 192 bytes of headroom.
2138 *
2139 * For i40e_construct_skb() mode it means that the
2140 * xdp->data_meta will always point to xdp->data, since
2141 * the helper cannot expand the head. Should this ever
2142 * change in future for legacy-rx mode on, then lets also
2143 * add xdp->data_meta handling here.
2144 */
2145
2146 /* allocate a skb to store the frags */
2147 skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
2148 I40E_RX_HDR_SIZE,
2149 GFP_ATOMIC | __GFP_NOWARN);
2150 if (unlikely(!skb))
2151 return NULL;
2152
2153 /* Determine available headroom for copy */
2154 headlen = size;
2155 if (headlen > I40E_RX_HDR_SIZE)
2156 headlen = eth_get_headlen(skb->dev, xdp->data,
2157 I40E_RX_HDR_SIZE);
2158
2159 /* align pull length to size of long to optimize memcpy performance */
2160 memcpy(__skb_put(skb, headlen), xdp->data,
2161 ALIGN(headlen, sizeof(long)));
2162
2163 if (unlikely(xdp_buff_has_frags(xdp))) {
2164 sinfo = xdp_get_shared_info_from_buff(xdp);
2165 nr_frags = sinfo->nr_frags;
2166 }
2167 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2168 /* update all of the pointers */
2169 size -= headlen;
2170 if (size) {
2171 if (unlikely(nr_frags >= MAX_SKB_FRAGS)) {
2172 dev_kfree_skb(skb);
2173 return NULL;
2174 }
2175 skb_add_rx_frag(skb, 0, rx_buffer->page,
2176 rx_buffer->page_offset + headlen,
2177 size, xdp->frame_sz);
2178 /* buffer is used by skb, update page_offset */
2179 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz);
2180 } else {
2181 /* buffer is unused, reset bias back to rx_buffer */
2182 rx_buffer->pagecnt_bias++;
2183 }
2184
2185 if (unlikely(xdp_buff_has_frags(xdp))) {
2186 struct skb_shared_info *skinfo = skb_shinfo(skb);
2187
2188 memcpy(&skinfo->frags[skinfo->nr_frags], &sinfo->frags[0],
2189 sizeof(skb_frag_t) * nr_frags);
2190
2191 xdp_update_skb_shared_info(skb, skinfo->nr_frags + nr_frags,
2192 sinfo->xdp_frags_size,
2193 nr_frags * xdp->frame_sz,
2194 xdp_buff_is_frag_pfmemalloc(xdp));
2195
2196 /* First buffer has already been processed, so bump ntc */
2197 if (++rx_ring->next_to_clean == rx_ring->count)
2198 rx_ring->next_to_clean = 0;
2199
2200 i40e_process_rx_buffs(rx_ring, I40E_XDP_PASS, xdp);
2201 }
2202
2203 return skb;
2204}
2205
2206/**
2207 * i40e_build_skb - Build skb around an existing buffer
2208 * @rx_ring: Rx descriptor ring to transact packets on
2209 * @xdp: xdp_buff pointing to the data
2210 *
2211 * This function builds an skb around an existing Rx buffer, taking care
2212 * to set up the skb correctly and avoid any memcpy overhead.
2213 */
2214static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
2215 struct xdp_buff *xdp)
2216{
2217 unsigned int metasize = xdp->data - xdp->data_meta;
2218 struct skb_shared_info *sinfo;
2219 struct sk_buff *skb;
2220 u32 nr_frags;
2221
2222 /* Prefetch first cache line of first page. If xdp->data_meta
2223 * is unused, this points exactly as xdp->data, otherwise we
2224 * likely have a consumer accessing first few bytes of meta
2225 * data, and then actual data.
2226 */
2227 net_prefetch(xdp->data_meta);
2228
2229 if (unlikely(xdp_buff_has_frags(xdp))) {
2230 sinfo = xdp_get_shared_info_from_buff(xdp);
2231 nr_frags = sinfo->nr_frags;
2232 }
2233
2234 /* build an skb around the page buffer */
2235 skb = napi_build_skb(xdp->data_hard_start, xdp->frame_sz);
2236 if (unlikely(!skb))
2237 return NULL;
2238
2239 /* update pointers within the skb to store the data */
2240 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2241 __skb_put(skb, xdp->data_end - xdp->data);
2242 if (metasize)
2243 skb_metadata_set(skb, metasize);
2244
2245 if (unlikely(xdp_buff_has_frags(xdp))) {
2246 xdp_update_skb_shared_info(skb, nr_frags,
2247 sinfo->xdp_frags_size,
2248 nr_frags * xdp->frame_sz,
2249 xdp_buff_is_frag_pfmemalloc(xdp));
2250
2251 i40e_process_rx_buffs(rx_ring, I40E_XDP_PASS, xdp);
2252 } else {
2253 struct i40e_rx_buffer *rx_buffer;
2254
2255 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2256 /* buffer is used by skb, update page_offset */
2257 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz);
2258 }
2259
2260 return skb;
2261}
2262
2263/**
2264 * i40e_is_non_eop - process handling of non-EOP buffers
2265 * @rx_ring: Rx ring being processed
2266 * @rx_desc: Rx descriptor for current buffer
2267 *
2268 * If the buffer is an EOP buffer, this function exits returning false,
2269 * otherwise return true indicating that this is in fact a non-EOP buffer.
2270 */
2271bool i40e_is_non_eop(struct i40e_ring *rx_ring,
2272 union i40e_rx_desc *rx_desc)
2273{
2274 /* if we are the last buffer then there is nothing else to do */
2275#define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
2276 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
2277 return false;
2278
2279 rx_ring->rx_stats.non_eop_descs++;
2280
2281 return true;
2282}
2283
2284static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
2285 struct i40e_ring *xdp_ring);
2286
2287int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring)
2288{
2289 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2290
2291 if (unlikely(!xdpf))
2292 return I40E_XDP_CONSUMED;
2293
2294 return i40e_xmit_xdp_ring(xdpf, xdp_ring);
2295}
2296
2297/**
2298 * i40e_run_xdp - run an XDP program
2299 * @rx_ring: Rx ring being processed
2300 * @xdp: XDP buffer containing the frame
2301 * @xdp_prog: XDP program to run
2302 **/
2303static int i40e_run_xdp(struct i40e_ring *rx_ring, struct xdp_buff *xdp, struct bpf_prog *xdp_prog)
2304{
2305 int err, result = I40E_XDP_PASS;
2306 struct i40e_ring *xdp_ring;
2307 u32 act;
2308
2309 if (!xdp_prog)
2310 goto xdp_out;
2311
2312 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2313
2314 act = bpf_prog_run_xdp(xdp_prog, xdp);
2315 switch (act) {
2316 case XDP_PASS:
2317 break;
2318 case XDP_TX:
2319 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2320 result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring);
2321 if (result == I40E_XDP_CONSUMED)
2322 goto out_failure;
2323 break;
2324 case XDP_REDIRECT:
2325 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog);
2326 if (err)
2327 goto out_failure;
2328 result = I40E_XDP_REDIR;
2329 break;
2330 default:
2331 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act);
2332 fallthrough;
2333 case XDP_ABORTED:
2334out_failure:
2335 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2336 fallthrough; /* handle aborts by dropping packet */
2337 case XDP_DROP:
2338 result = I40E_XDP_CONSUMED;
2339 break;
2340 }
2341xdp_out:
2342 return result;
2343}
2344
2345/**
2346 * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register
2347 * @xdp_ring: XDP Tx ring
2348 *
2349 * This function updates the XDP Tx ring tail register.
2350 **/
2351void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring)
2352{
2353 /* Force memory writes to complete before letting h/w
2354 * know there are new descriptors to fetch.
2355 */
2356 wmb();
2357 writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
2358}
2359
2360/**
2361 * i40e_update_rx_stats - Update Rx ring statistics
2362 * @rx_ring: rx descriptor ring
2363 * @total_rx_bytes: number of bytes received
2364 * @total_rx_packets: number of packets received
2365 *
2366 * This function updates the Rx ring statistics.
2367 **/
2368void i40e_update_rx_stats(struct i40e_ring *rx_ring,
2369 unsigned int total_rx_bytes,
2370 unsigned int total_rx_packets)
2371{
2372 u64_stats_update_begin(&rx_ring->syncp);
2373 rx_ring->stats.packets += total_rx_packets;
2374 rx_ring->stats.bytes += total_rx_bytes;
2375 u64_stats_update_end(&rx_ring->syncp);
2376 rx_ring->q_vector->rx.total_packets += total_rx_packets;
2377 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
2378}
2379
2380/**
2381 * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map
2382 * @rx_ring: Rx ring
2383 * @xdp_res: Result of the receive batch
2384 *
2385 * This function bumps XDP Tx tail and/or flush redirect map, and
2386 * should be called when a batch of packets has been processed in the
2387 * napi loop.
2388 **/
2389void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res)
2390{
2391 if (xdp_res & I40E_XDP_REDIR)
2392 xdp_do_flush();
2393
2394 if (xdp_res & I40E_XDP_TX) {
2395 struct i40e_ring *xdp_ring =
2396 rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2397
2398 i40e_xdp_ring_update_tail(xdp_ring);
2399 }
2400}
2401
2402/**
2403 * i40e_inc_ntp: Advance the next_to_process index
2404 * @rx_ring: Rx ring
2405 **/
2406static void i40e_inc_ntp(struct i40e_ring *rx_ring)
2407{
2408 u32 ntp = rx_ring->next_to_process + 1;
2409
2410 ntp = (ntp < rx_ring->count) ? ntp : 0;
2411 rx_ring->next_to_process = ntp;
2412 prefetch(I40E_RX_DESC(rx_ring, ntp));
2413}
2414
2415/**
2416 * i40e_add_xdp_frag: Add a frag to xdp_buff
2417 * @xdp: xdp_buff pointing to the data
2418 * @nr_frags: return number of buffers for the packet
2419 * @rx_buffer: rx_buffer holding data of the current frag
2420 * @size: size of data of current frag
2421 */
2422static int i40e_add_xdp_frag(struct xdp_buff *xdp, u32 *nr_frags,
2423 struct i40e_rx_buffer *rx_buffer, u32 size)
2424{
2425 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp);
2426
2427 if (!xdp_buff_has_frags(xdp)) {
2428 sinfo->nr_frags = 0;
2429 sinfo->xdp_frags_size = 0;
2430 xdp_buff_set_frags_flag(xdp);
2431 } else if (unlikely(sinfo->nr_frags >= MAX_SKB_FRAGS)) {
2432 /* Overflowing packet: All frags need to be dropped */
2433 return -ENOMEM;
2434 }
2435
2436 __skb_fill_page_desc_noacc(sinfo, sinfo->nr_frags++, rx_buffer->page,
2437 rx_buffer->page_offset, size);
2438
2439 sinfo->xdp_frags_size += size;
2440
2441 if (page_is_pfmemalloc(rx_buffer->page))
2442 xdp_buff_set_frag_pfmemalloc(xdp);
2443 *nr_frags = sinfo->nr_frags;
2444
2445 return 0;
2446}
2447
2448/**
2449 * i40e_consume_xdp_buff - Consume all the buffers of the packet and update ntc
2450 * @rx_ring: rx descriptor ring to transact packets on
2451 * @xdp: xdp_buff pointing to the data
2452 * @rx_buffer: rx_buffer of eop desc
2453 */
2454static void i40e_consume_xdp_buff(struct i40e_ring *rx_ring,
2455 struct xdp_buff *xdp,
2456 struct i40e_rx_buffer *rx_buffer)
2457{
2458 i40e_process_rx_buffs(rx_ring, I40E_XDP_CONSUMED, xdp);
2459 i40e_put_rx_buffer(rx_ring, rx_buffer);
2460 rx_ring->next_to_clean = rx_ring->next_to_process;
2461 xdp->data = NULL;
2462}
2463
2464/**
2465 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2466 * @rx_ring: rx descriptor ring to transact packets on
2467 * @budget: Total limit on number of packets to process
2468 * @rx_cleaned: Out parameter of the number of packets processed
2469 *
2470 * This function provides a "bounce buffer" approach to Rx interrupt
2471 * processing. The advantage to this is that on systems that have
2472 * expensive overhead for IOMMU access this provides a means of avoiding
2473 * it by maintaining the mapping of the page to the system.
2474 *
2475 * Returns amount of work completed
2476 **/
2477static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget,
2478 unsigned int *rx_cleaned)
2479{
2480 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2481 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
2482 u16 clean_threshold = rx_ring->count / 2;
2483 unsigned int offset = rx_ring->rx_offset;
2484 struct xdp_buff *xdp = &rx_ring->xdp;
2485 unsigned int xdp_xmit = 0;
2486 struct bpf_prog *xdp_prog;
2487 bool failure = false;
2488 int xdp_res = 0;
2489
2490 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2491
2492 while (likely(total_rx_packets < (unsigned int)budget)) {
2493 u16 ntp = rx_ring->next_to_process;
2494 struct i40e_rx_buffer *rx_buffer;
2495 union i40e_rx_desc *rx_desc;
2496 struct sk_buff *skb;
2497 unsigned int size;
2498 u32 nfrags = 0;
2499 bool neop;
2500 u64 qword;
2501
2502 /* return some buffers to hardware, one at a time is too slow */
2503 if (cleaned_count >= clean_threshold) {
2504 failure = failure ||
2505 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
2506 cleaned_count = 0;
2507 }
2508
2509 rx_desc = I40E_RX_DESC(rx_ring, ntp);
2510
2511 /* status_error_len will always be zero for unused descriptors
2512 * because it's cleared in cleanup, and overlaps with hdr_addr
2513 * which is always zero because packet split isn't used, if the
2514 * hardware wrote DD then the length will be non-zero
2515 */
2516 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2517
2518 /* This memory barrier is needed to keep us from reading
2519 * any other fields out of the rx_desc until we have
2520 * verified the descriptor has been written back.
2521 */
2522 dma_rmb();
2523
2524 if (i40e_rx_is_programming_status(qword)) {
2525 i40e_clean_programming_status(rx_ring,
2526 rx_desc->raw.qword[0],
2527 qword);
2528 rx_buffer = i40e_rx_bi(rx_ring, ntp);
2529 i40e_inc_ntp(rx_ring);
2530 i40e_reuse_rx_page(rx_ring, rx_buffer);
2531 /* Update ntc and bump cleaned count if not in the
2532 * middle of mb packet.
2533 */
2534 if (rx_ring->next_to_clean == ntp) {
2535 rx_ring->next_to_clean =
2536 rx_ring->next_to_process;
2537 cleaned_count++;
2538 }
2539 continue;
2540 }
2541
2542 size = FIELD_GET(I40E_RXD_QW1_LENGTH_PBUF_MASK, qword);
2543 if (!size)
2544 break;
2545
2546 i40e_trace(clean_rx_irq, rx_ring, rx_desc, xdp);
2547 /* retrieve a buffer from the ring */
2548 rx_buffer = i40e_get_rx_buffer(rx_ring, size);
2549
2550 neop = i40e_is_non_eop(rx_ring, rx_desc);
2551 i40e_inc_ntp(rx_ring);
2552
2553 if (!xdp->data) {
2554 unsigned char *hard_start;
2555
2556 hard_start = page_address(rx_buffer->page) +
2557 rx_buffer->page_offset - offset;
2558 xdp_prepare_buff(xdp, hard_start, offset, size, true);
2559#if (PAGE_SIZE > 4096)
2560 /* At larger PAGE_SIZE, frame_sz depend on len size */
2561 xdp->frame_sz = i40e_rx_frame_truesize(rx_ring, size);
2562#endif
2563 } else if (i40e_add_xdp_frag(xdp, &nfrags, rx_buffer, size) &&
2564 !neop) {
2565 /* Overflowing packet: Drop all frags on EOP */
2566 i40e_consume_xdp_buff(rx_ring, xdp, rx_buffer);
2567 break;
2568 }
2569
2570 if (neop)
2571 continue;
2572
2573 xdp_res = i40e_run_xdp(rx_ring, xdp, xdp_prog);
2574
2575 if (xdp_res) {
2576 xdp_xmit |= xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR);
2577
2578 if (unlikely(xdp_buff_has_frags(xdp))) {
2579 i40e_process_rx_buffs(rx_ring, xdp_res, xdp);
2580 size = xdp_get_buff_len(xdp);
2581 } else if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) {
2582 i40e_rx_buffer_flip(rx_buffer, xdp->frame_sz);
2583 } else {
2584 rx_buffer->pagecnt_bias++;
2585 }
2586 total_rx_bytes += size;
2587 } else {
2588 if (ring_uses_build_skb(rx_ring))
2589 skb = i40e_build_skb(rx_ring, xdp);
2590 else
2591 skb = i40e_construct_skb(rx_ring, xdp);
2592
2593 /* drop if we failed to retrieve a buffer */
2594 if (!skb) {
2595 rx_ring->rx_stats.alloc_buff_failed++;
2596 i40e_consume_xdp_buff(rx_ring, xdp, rx_buffer);
2597 break;
2598 }
2599
2600 if (i40e_cleanup_headers(rx_ring, skb, rx_desc))
2601 goto process_next;
2602
2603 /* probably a little skewed due to removing CRC */
2604 total_rx_bytes += skb->len;
2605
2606 /* populate checksum, VLAN, and protocol */
2607 i40e_process_skb_fields(rx_ring, rx_desc, skb);
2608
2609 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, xdp);
2610 napi_gro_receive(&rx_ring->q_vector->napi, skb);
2611 }
2612
2613 /* update budget accounting */
2614 total_rx_packets++;
2615process_next:
2616 cleaned_count += nfrags + 1;
2617 i40e_put_rx_buffer(rx_ring, rx_buffer);
2618 rx_ring->next_to_clean = rx_ring->next_to_process;
2619
2620 xdp->data = NULL;
2621 }
2622
2623 i40e_finalize_xdp_rx(rx_ring, xdp_xmit);
2624
2625 i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets);
2626
2627 *rx_cleaned = total_rx_packets;
2628
2629 /* guarantee a trip back through this routine if there was a failure */
2630 return failure ? budget : (int)total_rx_packets;
2631}
2632
2633static inline u32 i40e_buildreg_itr(const int type, u16 itr)
2634{
2635 u32 val;
2636
2637 /* We don't bother with setting the CLEARPBA bit as the data sheet
2638 * points out doing so is "meaningless since it was already
2639 * auto-cleared". The auto-clearing happens when the interrupt is
2640 * asserted.
2641 *
2642 * Hardware errata 28 for also indicates that writing to a
2643 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
2644 * an event in the PBA anyway so we need to rely on the automask
2645 * to hold pending events for us until the interrupt is re-enabled
2646 *
2647 * The itr value is reported in microseconds, and the register
2648 * value is recorded in 2 microsecond units. For this reason we
2649 * only need to shift by the interval shift - 1 instead of the
2650 * full value.
2651 */
2652 itr &= I40E_ITR_MASK;
2653
2654 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2655 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
2656 (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1));
2657
2658 return val;
2659}
2660
2661/* a small macro to shorten up some long lines */
2662#define INTREG I40E_PFINT_DYN_CTLN
2663
2664/* The act of updating the ITR will cause it to immediately trigger. In order
2665 * to prevent this from throwing off adaptive update statistics we defer the
2666 * update so that it can only happen so often. So after either Tx or Rx are
2667 * updated we make the adaptive scheme wait until either the ITR completely
2668 * expires via the next_update expiration or we have been through at least
2669 * 3 interrupts.
2670 */
2671#define ITR_COUNTDOWN_START 3
2672
2673/**
2674 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
2675 * @vsi: the VSI we care about
2676 * @q_vector: q_vector for which itr is being updated and interrupt enabled
2677 *
2678 **/
2679static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
2680 struct i40e_q_vector *q_vector)
2681{
2682 struct i40e_hw *hw = &vsi->back->hw;
2683 u32 intval;
2684
2685 /* If we don't have MSIX, then we only need to re-enable icr0 */
2686 if (!test_bit(I40E_FLAG_MSIX_ENA, vsi->back->flags)) {
2687 i40e_irq_dynamic_enable_icr0(vsi->back);
2688 return;
2689 }
2690
2691 /* These will do nothing if dynamic updates are not enabled */
2692 i40e_update_itr(q_vector, &q_vector->tx);
2693 i40e_update_itr(q_vector, &q_vector->rx);
2694
2695 /* This block of logic allows us to get away with only updating
2696 * one ITR value with each interrupt. The idea is to perform a
2697 * pseudo-lazy update with the following criteria.
2698 *
2699 * 1. Rx is given higher priority than Tx if both are in same state
2700 * 2. If we must reduce an ITR that is given highest priority.
2701 * 3. We then give priority to increasing ITR based on amount.
2702 */
2703 if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
2704 /* Rx ITR needs to be reduced, this is highest priority */
2705 intval = i40e_buildreg_itr(I40E_RX_ITR,
2706 q_vector->rx.target_itr);
2707 q_vector->rx.current_itr = q_vector->rx.target_itr;
2708 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2709 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
2710 ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
2711 (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
2712 /* Tx ITR needs to be reduced, this is second priority
2713 * Tx ITR needs to be increased more than Rx, fourth priority
2714 */
2715 intval = i40e_buildreg_itr(I40E_TX_ITR,
2716 q_vector->tx.target_itr);
2717 q_vector->tx.current_itr = q_vector->tx.target_itr;
2718 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2719 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
2720 /* Rx ITR needs to be increased, third priority */
2721 intval = i40e_buildreg_itr(I40E_RX_ITR,
2722 q_vector->rx.target_itr);
2723 q_vector->rx.current_itr = q_vector->rx.target_itr;
2724 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2725 } else {
2726 /* No ITR update, lowest priority */
2727 intval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
2728 if (q_vector->itr_countdown)
2729 q_vector->itr_countdown--;
2730 }
2731
2732 if (!test_bit(__I40E_VSI_DOWN, vsi->state))
2733 wr32(hw, INTREG(q_vector->reg_idx), intval);
2734}
2735
2736/**
2737 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
2738 * @napi: napi struct with our devices info in it
2739 * @budget: amount of work driver is allowed to do this pass, in packets
2740 *
2741 * This function will clean all queues associated with a q_vector.
2742 *
2743 * Returns the amount of work done
2744 **/
2745int i40e_napi_poll(struct napi_struct *napi, int budget)
2746{
2747 struct i40e_q_vector *q_vector =
2748 container_of(napi, struct i40e_q_vector, napi);
2749 struct i40e_vsi *vsi = q_vector->vsi;
2750 struct i40e_ring *ring;
2751 bool tx_clean_complete = true;
2752 bool rx_clean_complete = true;
2753 unsigned int tx_cleaned = 0;
2754 unsigned int rx_cleaned = 0;
2755 bool clean_complete = true;
2756 bool arm_wb = false;
2757 int budget_per_ring;
2758 int work_done = 0;
2759
2760 if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
2761 napi_complete(napi);
2762 return 0;
2763 }
2764
2765 /* Since the actual Tx work is minimal, we can give the Tx a larger
2766 * budget and be more aggressive about cleaning up the Tx descriptors.
2767 */
2768 i40e_for_each_ring(ring, q_vector->tx) {
2769 bool wd = ring->xsk_pool ?
2770 i40e_clean_xdp_tx_irq(vsi, ring) :
2771 i40e_clean_tx_irq(vsi, ring, budget, &tx_cleaned);
2772
2773 if (!wd) {
2774 clean_complete = tx_clean_complete = false;
2775 continue;
2776 }
2777 arm_wb |= ring->arm_wb;
2778 ring->arm_wb = false;
2779 }
2780
2781 /* Handle case where we are called by netpoll with a budget of 0 */
2782 if (budget <= 0)
2783 goto tx_only;
2784
2785 /* normally we have 1 Rx ring per q_vector */
2786 if (unlikely(q_vector->num_ringpairs > 1))
2787 /* We attempt to distribute budget to each Rx queue fairly, but
2788 * don't allow the budget to go below 1 because that would exit
2789 * polling early.
2790 */
2791 budget_per_ring = max_t(int, budget / q_vector->num_ringpairs, 1);
2792 else
2793 /* Max of 1 Rx ring in this q_vector so give it the budget */
2794 budget_per_ring = budget;
2795
2796 i40e_for_each_ring(ring, q_vector->rx) {
2797 int cleaned = ring->xsk_pool ?
2798 i40e_clean_rx_irq_zc(ring, budget_per_ring) :
2799 i40e_clean_rx_irq(ring, budget_per_ring, &rx_cleaned);
2800
2801 work_done += cleaned;
2802 /* if we clean as many as budgeted, we must not be done */
2803 if (cleaned >= budget_per_ring)
2804 clean_complete = rx_clean_complete = false;
2805 }
2806
2807 if (!i40e_enabled_xdp_vsi(vsi))
2808 trace_i40e_napi_poll(napi, q_vector, budget, budget_per_ring, rx_cleaned,
2809 tx_cleaned, rx_clean_complete, tx_clean_complete);
2810
2811 /* If work not completed, return budget and polling will return */
2812 if (!clean_complete) {
2813 int cpu_id = smp_processor_id();
2814
2815 /* It is possible that the interrupt affinity has changed but,
2816 * if the cpu is pegged at 100%, polling will never exit while
2817 * traffic continues and the interrupt will be stuck on this
2818 * cpu. We check to make sure affinity is correct before we
2819 * continue to poll, otherwise we must stop polling so the
2820 * interrupt can move to the correct cpu.
2821 */
2822 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
2823 /* Tell napi that we are done polling */
2824 napi_complete_done(napi, work_done);
2825
2826 /* Force an interrupt */
2827 i40e_force_wb(vsi, q_vector);
2828
2829 /* Return budget-1 so that polling stops */
2830 return budget - 1;
2831 }
2832tx_only:
2833 if (arm_wb) {
2834 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2835 i40e_enable_wb_on_itr(vsi, q_vector);
2836 }
2837 return budget;
2838 }
2839
2840 if (q_vector->tx.ring[0].flags & I40E_TXR_FLAGS_WB_ON_ITR)
2841 q_vector->arm_wb_state = false;
2842
2843 /* Exit the polling mode, but don't re-enable interrupts if stack might
2844 * poll us due to busy-polling
2845 */
2846 if (likely(napi_complete_done(napi, work_done)))
2847 i40e_update_enable_itr(vsi, q_vector);
2848
2849 return min(work_done, budget - 1);
2850}
2851
2852/**
2853 * i40e_atr - Add a Flow Director ATR filter
2854 * @tx_ring: ring to add programming descriptor to
2855 * @skb: send buffer
2856 * @tx_flags: send tx flags
2857 **/
2858static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2859 u32 tx_flags)
2860{
2861 struct i40e_filter_program_desc *fdir_desc;
2862 struct i40e_pf *pf = tx_ring->vsi->back;
2863 union {
2864 unsigned char *network;
2865 struct iphdr *ipv4;
2866 struct ipv6hdr *ipv6;
2867 } hdr;
2868 struct tcphdr *th;
2869 unsigned int hlen;
2870 u32 flex_ptype, dtype_cmd;
2871 int l4_proto;
2872 u16 i;
2873
2874 /* make sure ATR is enabled */
2875 if (!test_bit(I40E_FLAG_FD_ATR_ENA, pf->flags))
2876 return;
2877
2878 if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2879 return;
2880
2881 /* if sampling is disabled do nothing */
2882 if (!tx_ring->atr_sample_rate)
2883 return;
2884
2885 /* Currently only IPv4/IPv6 with TCP is supported */
2886 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2887 return;
2888
2889 /* snag network header to get L4 type and address */
2890 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2891 skb_inner_network_header(skb) : skb_network_header(skb);
2892
2893 /* Note: tx_flags gets modified to reflect inner protocols in
2894 * tx_enable_csum function if encap is enabled.
2895 */
2896 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2897 /* access ihl as u8 to avoid unaligned access on ia64 */
2898 hlen = (hdr.network[0] & 0x0F) << 2;
2899 l4_proto = hdr.ipv4->protocol;
2900 } else {
2901 /* find the start of the innermost ipv6 header */
2902 unsigned int inner_hlen = hdr.network - skb->data;
2903 unsigned int h_offset = inner_hlen;
2904
2905 /* this function updates h_offset to the end of the header */
2906 l4_proto =
2907 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL);
2908 /* hlen will contain our best estimate of the tcp header */
2909 hlen = h_offset - inner_hlen;
2910 }
2911
2912 if (l4_proto != IPPROTO_TCP)
2913 return;
2914
2915 th = (struct tcphdr *)(hdr.network + hlen);
2916
2917 /* Due to lack of space, no more new filters can be programmed */
2918 if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2919 return;
2920 if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags)) {
2921 /* HW ATR eviction will take care of removing filters on FIN
2922 * and RST packets.
2923 */
2924 if (th->fin || th->rst)
2925 return;
2926 }
2927
2928 tx_ring->atr_count++;
2929
2930 /* sample on all syn/fin/rst packets or once every atr sample rate */
2931 if (!th->fin &&
2932 !th->syn &&
2933 !th->rst &&
2934 (tx_ring->atr_count < tx_ring->atr_sample_rate))
2935 return;
2936
2937 tx_ring->atr_count = 0;
2938
2939 /* grab the next descriptor */
2940 i = tx_ring->next_to_use;
2941 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2942
2943 i++;
2944 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2945
2946 flex_ptype = FIELD_PREP(I40E_TXD_FLTR_QW0_QINDEX_MASK,
2947 tx_ring->queue_index);
2948 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2949 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2950 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2951 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2952 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2953
2954 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2955
2956 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2957
2958 dtype_cmd |= (th->fin || th->rst) ?
2959 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2960 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2961 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2962 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2963
2964 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2965 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2966
2967 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2968 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2969
2970 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2971 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2972 dtype_cmd |=
2973 FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK,
2974 I40E_FD_ATR_STAT_IDX(pf->hw.pf_id));
2975 else
2976 dtype_cmd |=
2977 FIELD_PREP(I40E_TXD_FLTR_QW1_CNTINDEX_MASK,
2978 I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id));
2979
2980 if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags))
2981 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2982
2983 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2984 fdir_desc->rsvd = cpu_to_le32(0);
2985 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2986 fdir_desc->fd_id = cpu_to_le32(0);
2987}
2988
2989/**
2990 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2991 * @skb: send buffer
2992 * @tx_ring: ring to send buffer on
2993 * @flags: the tx flags to be set
2994 *
2995 * Checks the skb and set up correspondingly several generic transmit flags
2996 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2997 *
2998 * Returns error code indicate the frame should be dropped upon error and the
2999 * otherwise returns 0 to indicate the flags has been set properly.
3000 **/
3001static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
3002 struct i40e_ring *tx_ring,
3003 u32 *flags)
3004{
3005 __be16 protocol = skb->protocol;
3006 u32 tx_flags = 0;
3007
3008 if (protocol == htons(ETH_P_8021Q) &&
3009 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
3010 /* When HW VLAN acceleration is turned off by the user the
3011 * stack sets the protocol to 8021q so that the driver
3012 * can take any steps required to support the SW only
3013 * VLAN handling. In our case the driver doesn't need
3014 * to take any further steps so just set the protocol
3015 * to the encapsulated ethertype.
3016 */
3017 skb->protocol = vlan_get_protocol(skb);
3018 goto out;
3019 }
3020
3021 /* if we have a HW VLAN tag being added, default to the HW one */
3022 if (skb_vlan_tag_present(skb)) {
3023 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
3024 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
3025 /* else if it is a SW VLAN, check the next protocol and store the tag */
3026 } else if (protocol == htons(ETH_P_8021Q)) {
3027 struct vlan_hdr *vhdr, _vhdr;
3028
3029 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
3030 if (!vhdr)
3031 return -EINVAL;
3032
3033 protocol = vhdr->h_vlan_encapsulated_proto;
3034 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
3035 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
3036 }
3037
3038 if (!test_bit(I40E_FLAG_DCB_ENA, tx_ring->vsi->back->flags))
3039 goto out;
3040
3041 /* Insert 802.1p priority into VLAN header */
3042 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
3043 (skb->priority != TC_PRIO_CONTROL)) {
3044 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
3045 tx_flags |= (skb->priority & 0x7) <<
3046 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
3047 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
3048 struct vlan_ethhdr *vhdr;
3049 int rc;
3050
3051 rc = skb_cow_head(skb, 0);
3052 if (rc < 0)
3053 return rc;
3054 vhdr = skb_vlan_eth_hdr(skb);
3055 vhdr->h_vlan_TCI = htons(tx_flags >>
3056 I40E_TX_FLAGS_VLAN_SHIFT);
3057 } else {
3058 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
3059 }
3060 }
3061
3062out:
3063 *flags = tx_flags;
3064 return 0;
3065}
3066
3067/**
3068 * i40e_tso - set up the tso context descriptor
3069 * @first: pointer to first Tx buffer for xmit
3070 * @hdr_len: ptr to the size of the packet header
3071 * @cd_type_cmd_tso_mss: Quad Word 1
3072 *
3073 * Returns 0 if no TSO can happen, 1 if tso is going, or error
3074 **/
3075static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
3076 u64 *cd_type_cmd_tso_mss)
3077{
3078 struct sk_buff *skb = first->skb;
3079 u64 cd_cmd, cd_tso_len, cd_mss;
3080 __be16 protocol;
3081 union {
3082 struct iphdr *v4;
3083 struct ipv6hdr *v6;
3084 unsigned char *hdr;
3085 } ip;
3086 union {
3087 struct tcphdr *tcp;
3088 struct udphdr *udp;
3089 unsigned char *hdr;
3090 } l4;
3091 u32 paylen, l4_offset;
3092 u16 gso_size;
3093 int err;
3094
3095 if (skb->ip_summed != CHECKSUM_PARTIAL)
3096 return 0;
3097
3098 if (!skb_is_gso(skb))
3099 return 0;
3100
3101 err = skb_cow_head(skb, 0);
3102 if (err < 0)
3103 return err;
3104
3105 protocol = vlan_get_protocol(skb);
3106
3107 if (eth_p_mpls(protocol))
3108 ip.hdr = skb_inner_network_header(skb);
3109 else
3110 ip.hdr = skb_network_header(skb);
3111 l4.hdr = skb_checksum_start(skb);
3112
3113 /* initialize outer IP header fields */
3114 if (ip.v4->version == 4) {
3115 ip.v4->tot_len = 0;
3116 ip.v4->check = 0;
3117
3118 first->tx_flags |= I40E_TX_FLAGS_TSO;
3119 } else {
3120 ip.v6->payload_len = 0;
3121 first->tx_flags |= I40E_TX_FLAGS_TSO;
3122 }
3123
3124 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
3125 SKB_GSO_GRE_CSUM |
3126 SKB_GSO_IPXIP4 |
3127 SKB_GSO_IPXIP6 |
3128 SKB_GSO_UDP_TUNNEL |
3129 SKB_GSO_UDP_TUNNEL_CSUM)) {
3130 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3131 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
3132 l4.udp->len = 0;
3133
3134 /* determine offset of outer transport header */
3135 l4_offset = l4.hdr - skb->data;
3136
3137 /* remove payload length from outer checksum */
3138 paylen = skb->len - l4_offset;
3139 csum_replace_by_diff(&l4.udp->check,
3140 (__force __wsum)htonl(paylen));
3141 }
3142
3143 /* reset pointers to inner headers */
3144 ip.hdr = skb_inner_network_header(skb);
3145 l4.hdr = skb_inner_transport_header(skb);
3146
3147 /* initialize inner IP header fields */
3148 if (ip.v4->version == 4) {
3149 ip.v4->tot_len = 0;
3150 ip.v4->check = 0;
3151 } else {
3152 ip.v6->payload_len = 0;
3153 }
3154 }
3155
3156 /* determine offset of inner transport header */
3157 l4_offset = l4.hdr - skb->data;
3158
3159 /* remove payload length from inner checksum */
3160 paylen = skb->len - l4_offset;
3161
3162 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3163 csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen));
3164 /* compute length of segmentation header */
3165 *hdr_len = sizeof(*l4.udp) + l4_offset;
3166 } else {
3167 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
3168 /* compute length of segmentation header */
3169 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
3170 }
3171
3172 /* pull values out of skb_shinfo */
3173 gso_size = skb_shinfo(skb)->gso_size;
3174
3175 /* update GSO size and bytecount with header size */
3176 first->gso_segs = skb_shinfo(skb)->gso_segs;
3177 first->bytecount += (first->gso_segs - 1) * *hdr_len;
3178
3179 /* find the field values */
3180 cd_cmd = I40E_TX_CTX_DESC_TSO;
3181 cd_tso_len = skb->len - *hdr_len;
3182 cd_mss = gso_size;
3183 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
3184 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
3185 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
3186 return 1;
3187}
3188
3189/**
3190 * i40e_tsyn - set up the tsyn context descriptor
3191 * @tx_ring: ptr to the ring to send
3192 * @skb: ptr to the skb we're sending
3193 * @tx_flags: the collected send information
3194 * @cd_type_cmd_tso_mss: Quad Word 1
3195 *
3196 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
3197 **/
3198static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
3199 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
3200{
3201 struct i40e_pf *pf;
3202
3203 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
3204 return 0;
3205
3206 /* Tx timestamps cannot be sampled when doing TSO */
3207 if (tx_flags & I40E_TX_FLAGS_TSO)
3208 return 0;
3209
3210 /* only timestamp the outbound packet if the user has requested it and
3211 * we are not already transmitting a packet to be timestamped
3212 */
3213 pf = i40e_netdev_to_pf(tx_ring->netdev);
3214 if (!test_bit(I40E_FLAG_PTP_ENA, pf->flags))
3215 return 0;
3216
3217 if (pf->ptp_tx &&
3218 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) {
3219 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3220 pf->ptp_tx_start = jiffies;
3221 pf->ptp_tx_skb = skb_get(skb);
3222 } else {
3223 pf->tx_hwtstamp_skipped++;
3224 return 0;
3225 }
3226
3227 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
3228 I40E_TXD_CTX_QW1_CMD_SHIFT;
3229
3230 return 1;
3231}
3232
3233/**
3234 * i40e_tx_enable_csum - Enable Tx checksum offloads
3235 * @skb: send buffer
3236 * @tx_flags: pointer to Tx flags currently set
3237 * @td_cmd: Tx descriptor command bits to set
3238 * @td_offset: Tx descriptor header offsets to set
3239 * @tx_ring: Tx descriptor ring
3240 * @cd_tunneling: ptr to context desc bits
3241 **/
3242static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
3243 u32 *td_cmd, u32 *td_offset,
3244 struct i40e_ring *tx_ring,
3245 u32 *cd_tunneling)
3246{
3247 union {
3248 struct iphdr *v4;
3249 struct ipv6hdr *v6;
3250 unsigned char *hdr;
3251 } ip;
3252 union {
3253 struct tcphdr *tcp;
3254 struct udphdr *udp;
3255 unsigned char *hdr;
3256 } l4;
3257 unsigned char *exthdr;
3258 u32 offset, cmd = 0;
3259 __be16 frag_off;
3260 __be16 protocol;
3261 u8 l4_proto = 0;
3262
3263 if (skb->ip_summed != CHECKSUM_PARTIAL)
3264 return 0;
3265
3266 protocol = vlan_get_protocol(skb);
3267
3268 if (eth_p_mpls(protocol)) {
3269 ip.hdr = skb_inner_network_header(skb);
3270 l4.hdr = skb_checksum_start(skb);
3271 } else {
3272 ip.hdr = skb_network_header(skb);
3273 l4.hdr = skb_transport_header(skb);
3274 }
3275
3276 /* set the tx_flags to indicate the IP protocol type. this is
3277 * required so that checksum header computation below is accurate.
3278 */
3279 if (ip.v4->version == 4)
3280 *tx_flags |= I40E_TX_FLAGS_IPV4;
3281 else
3282 *tx_flags |= I40E_TX_FLAGS_IPV6;
3283
3284 /* compute outer L2 header size */
3285 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
3286
3287 if (skb->encapsulation) {
3288 u32 tunnel = 0;
3289 /* define outer network header type */
3290 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3291 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3292 I40E_TX_CTX_EXT_IP_IPV4 :
3293 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
3294
3295 l4_proto = ip.v4->protocol;
3296 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3297 int ret;
3298
3299 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
3300
3301 exthdr = ip.hdr + sizeof(*ip.v6);
3302 l4_proto = ip.v6->nexthdr;
3303 ret = ipv6_skip_exthdr(skb, exthdr - skb->data,
3304 &l4_proto, &frag_off);
3305 if (ret < 0)
3306 return -1;
3307 }
3308
3309 /* define outer transport */
3310 switch (l4_proto) {
3311 case IPPROTO_UDP:
3312 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
3313 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3314 break;
3315 case IPPROTO_GRE:
3316 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
3317 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3318 break;
3319 case IPPROTO_IPIP:
3320 case IPPROTO_IPV6:
3321 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3322 l4.hdr = skb_inner_network_header(skb);
3323 break;
3324 default:
3325 if (*tx_flags & I40E_TX_FLAGS_TSO)
3326 return -1;
3327
3328 skb_checksum_help(skb);
3329 return 0;
3330 }
3331
3332 /* compute outer L3 header size */
3333 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
3334 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
3335
3336 /* switch IP header pointer from outer to inner header */
3337 ip.hdr = skb_inner_network_header(skb);
3338
3339 /* compute tunnel header size */
3340 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
3341 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
3342
3343 /* indicate if we need to offload outer UDP header */
3344 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
3345 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3346 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
3347 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
3348
3349 /* record tunnel offload values */
3350 *cd_tunneling |= tunnel;
3351
3352 /* switch L4 header pointer from outer to inner */
3353 l4.hdr = skb_inner_transport_header(skb);
3354 l4_proto = 0;
3355
3356 /* reset type as we transition from outer to inner headers */
3357 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
3358 if (ip.v4->version == 4)
3359 *tx_flags |= I40E_TX_FLAGS_IPV4;
3360 if (ip.v6->version == 6)
3361 *tx_flags |= I40E_TX_FLAGS_IPV6;
3362 }
3363
3364 /* Enable IP checksum offloads */
3365 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3366 l4_proto = ip.v4->protocol;
3367 /* the stack computes the IP header already, the only time we
3368 * need the hardware to recompute it is in the case of TSO.
3369 */
3370 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3371 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
3372 I40E_TX_DESC_CMD_IIPT_IPV4;
3373 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3374 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
3375
3376 exthdr = ip.hdr + sizeof(*ip.v6);
3377 l4_proto = ip.v6->nexthdr;
3378 if (l4.hdr != exthdr)
3379 ipv6_skip_exthdr(skb, exthdr - skb->data,
3380 &l4_proto, &frag_off);
3381 }
3382
3383 /* compute inner L3 header size */
3384 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
3385
3386 /* Enable L4 checksum offloads */
3387 switch (l4_proto) {
3388 case IPPROTO_TCP:
3389 /* enable checksum offloads */
3390 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
3391 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3392 break;
3393 case IPPROTO_SCTP:
3394 /* enable SCTP checksum offload */
3395 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
3396 offset |= (sizeof(struct sctphdr) >> 2) <<
3397 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3398 break;
3399 case IPPROTO_UDP:
3400 /* enable UDP checksum offload */
3401 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
3402 offset |= (sizeof(struct udphdr) >> 2) <<
3403 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3404 break;
3405 default:
3406 if (*tx_flags & I40E_TX_FLAGS_TSO)
3407 return -1;
3408 skb_checksum_help(skb);
3409 return 0;
3410 }
3411
3412 *td_cmd |= cmd;
3413 *td_offset |= offset;
3414
3415 return 1;
3416}
3417
3418/**
3419 * i40e_create_tx_ctx - Build the Tx context descriptor
3420 * @tx_ring: ring to create the descriptor on
3421 * @cd_type_cmd_tso_mss: Quad Word 1
3422 * @cd_tunneling: Quad Word 0 - bits 0-31
3423 * @cd_l2tag2: Quad Word 0 - bits 32-63
3424 **/
3425static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
3426 const u64 cd_type_cmd_tso_mss,
3427 const u32 cd_tunneling, const u32 cd_l2tag2)
3428{
3429 struct i40e_tx_context_desc *context_desc;
3430 int i = tx_ring->next_to_use;
3431
3432 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
3433 !cd_tunneling && !cd_l2tag2)
3434 return;
3435
3436 /* grab the next descriptor */
3437 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
3438
3439 i++;
3440 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3441
3442 /* cpu_to_le32 and assign to struct fields */
3443 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
3444 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3445 context_desc->rsvd = cpu_to_le16(0);
3446 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
3447}
3448
3449/**
3450 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
3451 * @tx_ring: the ring to be checked
3452 * @size: the size buffer we want to assure is available
3453 *
3454 * Returns -EBUSY if a stop is needed, else 0
3455 **/
3456int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
3457{
3458 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
3459 /* Memory barrier before checking head and tail */
3460 smp_mb();
3461
3462 ++tx_ring->tx_stats.tx_stopped;
3463
3464 /* Check again in a case another CPU has just made room available. */
3465 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
3466 return -EBUSY;
3467
3468 /* A reprieve! - use start_queue because it doesn't call schedule */
3469 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
3470 ++tx_ring->tx_stats.restart_queue;
3471 return 0;
3472}
3473
3474/**
3475 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
3476 * @skb: send buffer
3477 *
3478 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
3479 * and so we need to figure out the cases where we need to linearize the skb.
3480 *
3481 * For TSO we need to count the TSO header and segment payload separately.
3482 * As such we need to check cases where we have 7 fragments or more as we
3483 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
3484 * the segment payload in the first descriptor, and another 7 for the
3485 * fragments.
3486 **/
3487bool __i40e_chk_linearize(struct sk_buff *skb)
3488{
3489 const skb_frag_t *frag, *stale;
3490 int nr_frags, sum;
3491
3492 /* no need to check if number of frags is less than 7 */
3493 nr_frags = skb_shinfo(skb)->nr_frags;
3494 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
3495 return false;
3496
3497 /* We need to walk through the list and validate that each group
3498 * of 6 fragments totals at least gso_size.
3499 */
3500 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
3501 frag = &skb_shinfo(skb)->frags[0];
3502
3503 /* Initialize size to the negative value of gso_size minus 1. We
3504 * use this as the worst case scenerio in which the frag ahead
3505 * of us only provides one byte which is why we are limited to 6
3506 * descriptors for a single transmit as the header and previous
3507 * fragment are already consuming 2 descriptors.
3508 */
3509 sum = 1 - skb_shinfo(skb)->gso_size;
3510
3511 /* Add size of frags 0 through 4 to create our initial sum */
3512 sum += skb_frag_size(frag++);
3513 sum += skb_frag_size(frag++);
3514 sum += skb_frag_size(frag++);
3515 sum += skb_frag_size(frag++);
3516 sum += skb_frag_size(frag++);
3517
3518 /* Walk through fragments adding latest fragment, testing it, and
3519 * then removing stale fragments from the sum.
3520 */
3521 for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
3522 int stale_size = skb_frag_size(stale);
3523
3524 sum += skb_frag_size(frag++);
3525
3526 /* The stale fragment may present us with a smaller
3527 * descriptor than the actual fragment size. To account
3528 * for that we need to remove all the data on the front and
3529 * figure out what the remainder would be in the last
3530 * descriptor associated with the fragment.
3531 */
3532 if (stale_size > I40E_MAX_DATA_PER_TXD) {
3533 int align_pad = -(skb_frag_off(stale)) &
3534 (I40E_MAX_READ_REQ_SIZE - 1);
3535
3536 sum -= align_pad;
3537 stale_size -= align_pad;
3538
3539 do {
3540 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3541 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3542 } while (stale_size > I40E_MAX_DATA_PER_TXD);
3543 }
3544
3545 /* if sum is negative we failed to make sufficient progress */
3546 if (sum < 0)
3547 return true;
3548
3549 if (!nr_frags--)
3550 break;
3551
3552 sum -= stale_size;
3553 }
3554
3555 return false;
3556}
3557
3558/**
3559 * i40e_tx_map - Build the Tx descriptor
3560 * @tx_ring: ring to send buffer on
3561 * @skb: send buffer
3562 * @first: first buffer info buffer to use
3563 * @tx_flags: collected send information
3564 * @hdr_len: size of the packet header
3565 * @td_cmd: the command field in the descriptor
3566 * @td_offset: offset for checksum or crc
3567 *
3568 * Returns 0 on success, -1 on failure to DMA
3569 **/
3570static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
3571 struct i40e_tx_buffer *first, u32 tx_flags,
3572 const u8 hdr_len, u32 td_cmd, u32 td_offset)
3573{
3574 unsigned int data_len = skb->data_len;
3575 unsigned int size = skb_headlen(skb);
3576 skb_frag_t *frag;
3577 struct i40e_tx_buffer *tx_bi;
3578 struct i40e_tx_desc *tx_desc;
3579 u16 i = tx_ring->next_to_use;
3580 u32 td_tag = 0;
3581 dma_addr_t dma;
3582 u16 desc_count = 1;
3583
3584 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
3585 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
3586 td_tag = FIELD_GET(I40E_TX_FLAGS_VLAN_MASK, tx_flags);
3587 }
3588
3589 first->tx_flags = tx_flags;
3590
3591 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
3592
3593 tx_desc = I40E_TX_DESC(tx_ring, i);
3594 tx_bi = first;
3595
3596 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
3597 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3598
3599 if (dma_mapping_error(tx_ring->dev, dma))
3600 goto dma_error;
3601
3602 /* record length, and DMA address */
3603 dma_unmap_len_set(tx_bi, len, size);
3604 dma_unmap_addr_set(tx_bi, dma, dma);
3605
3606 /* align size to end of page */
3607 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
3608 tx_desc->buffer_addr = cpu_to_le64(dma);
3609
3610 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
3611 tx_desc->cmd_type_offset_bsz =
3612 build_ctob(td_cmd, td_offset,
3613 max_data, td_tag);
3614
3615 tx_desc++;
3616 i++;
3617 desc_count++;
3618
3619 if (i == tx_ring->count) {
3620 tx_desc = I40E_TX_DESC(tx_ring, 0);
3621 i = 0;
3622 }
3623
3624 dma += max_data;
3625 size -= max_data;
3626
3627 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3628 tx_desc->buffer_addr = cpu_to_le64(dma);
3629 }
3630
3631 if (likely(!data_len))
3632 break;
3633
3634 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
3635 size, td_tag);
3636
3637 tx_desc++;
3638 i++;
3639 desc_count++;
3640
3641 if (i == tx_ring->count) {
3642 tx_desc = I40E_TX_DESC(tx_ring, 0);
3643 i = 0;
3644 }
3645
3646 size = skb_frag_size(frag);
3647 data_len -= size;
3648
3649 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
3650 DMA_TO_DEVICE);
3651
3652 tx_bi = &tx_ring->tx_bi[i];
3653 }
3654
3655 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
3656
3657 i++;
3658 if (i == tx_ring->count)
3659 i = 0;
3660
3661 tx_ring->next_to_use = i;
3662
3663 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
3664
3665 /* write last descriptor with EOP bit */
3666 td_cmd |= I40E_TX_DESC_CMD_EOP;
3667
3668 /* We OR these values together to check both against 4 (WB_STRIDE)
3669 * below. This is safe since we don't re-use desc_count afterwards.
3670 */
3671 desc_count |= ++tx_ring->packet_stride;
3672
3673 if (desc_count >= WB_STRIDE) {
3674 /* write last descriptor with RS bit set */
3675 td_cmd |= I40E_TX_DESC_CMD_RS;
3676 tx_ring->packet_stride = 0;
3677 }
3678
3679 tx_desc->cmd_type_offset_bsz =
3680 build_ctob(td_cmd, td_offset, size, td_tag);
3681
3682 skb_tx_timestamp(skb);
3683
3684 /* Force memory writes to complete before letting h/w know there
3685 * are new descriptors to fetch.
3686 *
3687 * We also use this memory barrier to make certain all of the
3688 * status bits have been updated before next_to_watch is written.
3689 */
3690 wmb();
3691
3692 /* set next_to_watch value indicating a packet is present */
3693 first->next_to_watch = tx_desc;
3694
3695 /* notify HW of packet */
3696 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
3697 writel(i, tx_ring->tail);
3698 }
3699
3700 return 0;
3701
3702dma_error:
3703 dev_info(tx_ring->dev, "TX DMA map failed\n");
3704
3705 /* clear dma mappings for failed tx_bi map */
3706 for (;;) {
3707 tx_bi = &tx_ring->tx_bi[i];
3708 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
3709 if (tx_bi == first)
3710 break;
3711 if (i == 0)
3712 i = tx_ring->count;
3713 i--;
3714 }
3715
3716 tx_ring->next_to_use = i;
3717
3718 return -1;
3719}
3720
3721static u16 i40e_swdcb_skb_tx_hash(struct net_device *dev,
3722 const struct sk_buff *skb,
3723 u16 num_tx_queues)
3724{
3725 u32 jhash_initval_salt = 0xd631614b;
3726 u32 hash;
3727
3728 if (skb->sk && skb->sk->sk_hash)
3729 hash = skb->sk->sk_hash;
3730 else
3731 hash = (__force u16)skb->protocol ^ skb->hash;
3732
3733 hash = jhash_1word(hash, jhash_initval_salt);
3734
3735 return (u16)(((u64)hash * num_tx_queues) >> 32);
3736}
3737
3738u16 i40e_lan_select_queue(struct net_device *netdev,
3739 struct sk_buff *skb,
3740 struct net_device __always_unused *sb_dev)
3741{
3742 struct i40e_netdev_priv *np = netdev_priv(netdev);
3743 struct i40e_vsi *vsi = np->vsi;
3744 struct i40e_hw *hw;
3745 u16 qoffset;
3746 u16 qcount;
3747 u8 tclass;
3748 u16 hash;
3749 u8 prio;
3750
3751 /* is DCB enabled at all? */
3752 if (vsi->tc_config.numtc == 1 ||
3753 i40e_is_tc_mqprio_enabled(vsi->back))
3754 return netdev_pick_tx(netdev, skb, sb_dev);
3755
3756 prio = skb->priority;
3757 hw = &vsi->back->hw;
3758 tclass = hw->local_dcbx_config.etscfg.prioritytable[prio];
3759 /* sanity check */
3760 if (unlikely(!(vsi->tc_config.enabled_tc & BIT(tclass))))
3761 tclass = 0;
3762
3763 /* select a queue assigned for the given TC */
3764 qcount = vsi->tc_config.tc_info[tclass].qcount;
3765 hash = i40e_swdcb_skb_tx_hash(netdev, skb, qcount);
3766
3767 qoffset = vsi->tc_config.tc_info[tclass].qoffset;
3768 return qoffset + hash;
3769}
3770
3771/**
3772 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
3773 * @xdpf: data to transmit
3774 * @xdp_ring: XDP Tx ring
3775 **/
3776static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
3777 struct i40e_ring *xdp_ring)
3778{
3779 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
3780 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
3781 u16 i = 0, index = xdp_ring->next_to_use;
3782 struct i40e_tx_buffer *tx_head = &xdp_ring->tx_bi[index];
3783 struct i40e_tx_buffer *tx_bi = tx_head;
3784 struct i40e_tx_desc *tx_desc = I40E_TX_DESC(xdp_ring, index);
3785 void *data = xdpf->data;
3786 u32 size = xdpf->len;
3787
3788 if (unlikely(I40E_DESC_UNUSED(xdp_ring) < 1 + nr_frags)) {
3789 xdp_ring->tx_stats.tx_busy++;
3790 return I40E_XDP_CONSUMED;
3791 }
3792
3793 tx_head->bytecount = xdp_get_frame_len(xdpf);
3794 tx_head->gso_segs = 1;
3795 tx_head->xdpf = xdpf;
3796
3797 for (;;) {
3798 dma_addr_t dma;
3799
3800 dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE);
3801 if (dma_mapping_error(xdp_ring->dev, dma))
3802 goto unmap;
3803
3804 /* record length, and DMA address */
3805 dma_unmap_len_set(tx_bi, len, size);
3806 dma_unmap_addr_set(tx_bi, dma, dma);
3807
3808 tx_desc->buffer_addr = cpu_to_le64(dma);
3809 tx_desc->cmd_type_offset_bsz =
3810 build_ctob(I40E_TX_DESC_CMD_ICRC, 0, size, 0);
3811
3812 if (++index == xdp_ring->count)
3813 index = 0;
3814
3815 if (i == nr_frags)
3816 break;
3817
3818 tx_bi = &xdp_ring->tx_bi[index];
3819 tx_desc = I40E_TX_DESC(xdp_ring, index);
3820
3821 data = skb_frag_address(&sinfo->frags[i]);
3822 size = skb_frag_size(&sinfo->frags[i]);
3823 i++;
3824 }
3825
3826 tx_desc->cmd_type_offset_bsz |=
3827 cpu_to_le64(I40E_TXD_CMD << I40E_TXD_QW1_CMD_SHIFT);
3828
3829 /* Make certain all of the status bits have been updated
3830 * before next_to_watch is written.
3831 */
3832 smp_wmb();
3833
3834 xdp_ring->xdp_tx_active++;
3835
3836 tx_head->next_to_watch = tx_desc;
3837 xdp_ring->next_to_use = index;
3838
3839 return I40E_XDP_TX;
3840
3841unmap:
3842 for (;;) {
3843 tx_bi = &xdp_ring->tx_bi[index];
3844 if (dma_unmap_len(tx_bi, len))
3845 dma_unmap_page(xdp_ring->dev,
3846 dma_unmap_addr(tx_bi, dma),
3847 dma_unmap_len(tx_bi, len),
3848 DMA_TO_DEVICE);
3849 dma_unmap_len_set(tx_bi, len, 0);
3850 if (tx_bi == tx_head)
3851 break;
3852
3853 if (!index)
3854 index += xdp_ring->count;
3855 index--;
3856 }
3857
3858 return I40E_XDP_CONSUMED;
3859}
3860
3861/**
3862 * i40e_xmit_frame_ring - Sends buffer on Tx ring
3863 * @skb: send buffer
3864 * @tx_ring: ring to send buffer on
3865 *
3866 * Returns NETDEV_TX_OK if sent, else an error code
3867 **/
3868static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
3869 struct i40e_ring *tx_ring)
3870{
3871 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
3872 u32 cd_tunneling = 0, cd_l2tag2 = 0;
3873 struct i40e_tx_buffer *first;
3874 u32 td_offset = 0;
3875 u32 tx_flags = 0;
3876 u32 td_cmd = 0;
3877 u8 hdr_len = 0;
3878 int tso, count;
3879 int tsyn;
3880
3881 /* prefetch the data, we'll need it later */
3882 prefetch(skb->data);
3883
3884 i40e_trace(xmit_frame_ring, skb, tx_ring);
3885
3886 count = i40e_xmit_descriptor_count(skb);
3887 if (i40e_chk_linearize(skb, count)) {
3888 if (__skb_linearize(skb)) {
3889 dev_kfree_skb_any(skb);
3890 return NETDEV_TX_OK;
3891 }
3892 count = i40e_txd_use_count(skb->len);
3893 tx_ring->tx_stats.tx_linearize++;
3894 }
3895
3896 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
3897 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
3898 * + 4 desc gap to avoid the cache line where head is,
3899 * + 1 desc for context descriptor,
3900 * otherwise try next time
3901 */
3902 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
3903 tx_ring->tx_stats.tx_busy++;
3904 return NETDEV_TX_BUSY;
3905 }
3906
3907 /* record the location of the first descriptor for this packet */
3908 first = &tx_ring->tx_bi[tx_ring->next_to_use];
3909 first->skb = skb;
3910 first->bytecount = skb->len;
3911 first->gso_segs = 1;
3912
3913 /* prepare the xmit flags */
3914 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
3915 goto out_drop;
3916
3917 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
3918
3919 if (tso < 0)
3920 goto out_drop;
3921 else if (tso)
3922 tx_flags |= I40E_TX_FLAGS_TSO;
3923
3924 /* Always offload the checksum, since it's in the data descriptor */
3925 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
3926 tx_ring, &cd_tunneling);
3927 if (tso < 0)
3928 goto out_drop;
3929
3930 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
3931
3932 if (tsyn)
3933 tx_flags |= I40E_TX_FLAGS_TSYN;
3934
3935 /* always enable CRC insertion offload */
3936 td_cmd |= I40E_TX_DESC_CMD_ICRC;
3937
3938 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
3939 cd_tunneling, cd_l2tag2);
3940
3941 /* Add Flow Director ATR if it's enabled.
3942 *
3943 * NOTE: this must always be directly before the data descriptor.
3944 */
3945 i40e_atr(tx_ring, skb, tx_flags);
3946
3947 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
3948 td_cmd, td_offset))
3949 goto cleanup_tx_tstamp;
3950
3951 return NETDEV_TX_OK;
3952
3953out_drop:
3954 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
3955 dev_kfree_skb_any(first->skb);
3956 first->skb = NULL;
3957cleanup_tx_tstamp:
3958 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) {
3959 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev);
3960
3961 dev_kfree_skb_any(pf->ptp_tx_skb);
3962 pf->ptp_tx_skb = NULL;
3963 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
3964 }
3965
3966 return NETDEV_TX_OK;
3967}
3968
3969/**
3970 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
3971 * @skb: send buffer
3972 * @netdev: network interface device structure
3973 *
3974 * Returns NETDEV_TX_OK if sent, else an error code
3975 **/
3976netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3977{
3978 struct i40e_netdev_priv *np = netdev_priv(netdev);
3979 struct i40e_vsi *vsi = np->vsi;
3980 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
3981
3982 /* hardware can't handle really short frames, hardware padding works
3983 * beyond this point
3984 */
3985 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
3986 return NETDEV_TX_OK;
3987
3988 return i40e_xmit_frame_ring(skb, tx_ring);
3989}
3990
3991/**
3992 * i40e_xdp_xmit - Implements ndo_xdp_xmit
3993 * @dev: netdev
3994 * @n: number of frames
3995 * @frames: array of XDP buffer pointers
3996 * @flags: XDP extra info
3997 *
3998 * Returns number of frames successfully sent. Failed frames
3999 * will be free'ed by XDP core.
4000 *
4001 * For error cases, a negative errno code is returned and no-frames
4002 * are transmitted (caller must handle freeing frames).
4003 **/
4004int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
4005 u32 flags)
4006{
4007 struct i40e_netdev_priv *np = netdev_priv(dev);
4008 unsigned int queue_index = smp_processor_id();
4009 struct i40e_vsi *vsi = np->vsi;
4010 struct i40e_pf *pf = vsi->back;
4011 struct i40e_ring *xdp_ring;
4012 int nxmit = 0;
4013 int i;
4014
4015 if (test_bit(__I40E_VSI_DOWN, vsi->state))
4016 return -ENETDOWN;
4017
4018 if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs ||
4019 test_bit(__I40E_CONFIG_BUSY, pf->state))
4020 return -ENXIO;
4021
4022 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
4023 return -EINVAL;
4024
4025 xdp_ring = vsi->xdp_rings[queue_index];
4026
4027 for (i = 0; i < n; i++) {
4028 struct xdp_frame *xdpf = frames[i];
4029 int err;
4030
4031 err = i40e_xmit_xdp_ring(xdpf, xdp_ring);
4032 if (err != I40E_XDP_TX)
4033 break;
4034 nxmit++;
4035 }
4036
4037 if (unlikely(flags & XDP_XMIT_FLUSH))
4038 i40e_xdp_ring_update_tail(xdp_ring);
4039
4040 return nxmit;
4041}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4#include <linux/prefetch.h>
5#include <linux/bpf_trace.h>
6#include <net/xdp.h>
7#include "i40e.h"
8#include "i40e_trace.h"
9#include "i40e_prototype.h"
10#include "i40e_txrx_common.h"
11#include "i40e_xsk.h"
12
13#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
14/**
15 * i40e_fdir - Generate a Flow Director descriptor based on fdata
16 * @tx_ring: Tx ring to send buffer on
17 * @fdata: Flow director filter data
18 * @add: Indicate if we are adding a rule or deleting one
19 *
20 **/
21static void i40e_fdir(struct i40e_ring *tx_ring,
22 struct i40e_fdir_filter *fdata, bool add)
23{
24 struct i40e_filter_program_desc *fdir_desc;
25 struct i40e_pf *pf = tx_ring->vsi->back;
26 u32 flex_ptype, dtype_cmd;
27 u16 i;
28
29 /* grab the next descriptor */
30 i = tx_ring->next_to_use;
31 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
32
33 i++;
34 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
35
36 flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK &
37 (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT);
38
39 flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK &
40 (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
41
42 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
43 (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
44
45 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
46 (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
47
48 /* Use LAN VSI Id if not programmed by user */
49 flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK &
50 ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) <<
51 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);
52
53 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
54
55 dtype_cmd |= add ?
56 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
57 I40E_TXD_FLTR_QW1_PCMD_SHIFT :
58 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
59 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
60
61 dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK &
62 (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT);
63
64 dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK &
65 (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT);
66
67 if (fdata->cnt_index) {
68 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
69 dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK &
70 ((u32)fdata->cnt_index <<
71 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT);
72 }
73
74 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
75 fdir_desc->rsvd = cpu_to_le32(0);
76 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
77 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
78}
79
80#define I40E_FD_CLEAN_DELAY 10
81/**
82 * i40e_program_fdir_filter - Program a Flow Director filter
83 * @fdir_data: Packet data that will be filter parameters
84 * @raw_packet: the pre-allocated packet buffer for FDir
85 * @pf: The PF pointer
86 * @add: True for add/update, False for remove
87 **/
88static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
89 u8 *raw_packet, struct i40e_pf *pf,
90 bool add)
91{
92 struct i40e_tx_buffer *tx_buf, *first;
93 struct i40e_tx_desc *tx_desc;
94 struct i40e_ring *tx_ring;
95 struct i40e_vsi *vsi;
96 struct device *dev;
97 dma_addr_t dma;
98 u32 td_cmd = 0;
99 u16 i;
100
101 /* find existing FDIR VSI */
102 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
103 if (!vsi)
104 return -ENOENT;
105
106 tx_ring = vsi->tx_rings[0];
107 dev = tx_ring->dev;
108
109 /* we need two descriptors to add/del a filter and we can wait */
110 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
111 if (!i)
112 return -EAGAIN;
113 msleep_interruptible(1);
114 }
115
116 dma = dma_map_single(dev, raw_packet,
117 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
118 if (dma_mapping_error(dev, dma))
119 goto dma_fail;
120
121 /* grab the next descriptor */
122 i = tx_ring->next_to_use;
123 first = &tx_ring->tx_bi[i];
124 i40e_fdir(tx_ring, fdir_data, add);
125
126 /* Now program a dummy descriptor */
127 i = tx_ring->next_to_use;
128 tx_desc = I40E_TX_DESC(tx_ring, i);
129 tx_buf = &tx_ring->tx_bi[i];
130
131 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
132
133 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
134
135 /* record length, and DMA address */
136 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
137 dma_unmap_addr_set(tx_buf, dma, dma);
138
139 tx_desc->buffer_addr = cpu_to_le64(dma);
140 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
141
142 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
143 tx_buf->raw_buf = (void *)raw_packet;
144
145 tx_desc->cmd_type_offset_bsz =
146 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
147
148 /* Force memory writes to complete before letting h/w
149 * know there are new descriptors to fetch.
150 */
151 wmb();
152
153 /* Mark the data descriptor to be watched */
154 first->next_to_watch = tx_desc;
155
156 writel(tx_ring->next_to_use, tx_ring->tail);
157 return 0;
158
159dma_fail:
160 return -1;
161}
162
163#define IP_HEADER_OFFSET 14
164#define I40E_UDPIP_DUMMY_PACKET_LEN 42
165/**
166 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
167 * @vsi: pointer to the targeted VSI
168 * @fd_data: the flow director data required for the FDir descriptor
169 * @add: true adds a filter, false removes it
170 *
171 * Returns 0 if the filters were successfully added or removed
172 **/
173static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
174 struct i40e_fdir_filter *fd_data,
175 bool add)
176{
177 struct i40e_pf *pf = vsi->back;
178 struct udphdr *udp;
179 struct iphdr *ip;
180 u8 *raw_packet;
181 int ret;
182 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
183 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
184 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
185
186 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
187 if (!raw_packet)
188 return -ENOMEM;
189 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
190
191 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
192 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
193 + sizeof(struct iphdr));
194
195 ip->daddr = fd_data->dst_ip;
196 udp->dest = fd_data->dst_port;
197 ip->saddr = fd_data->src_ip;
198 udp->source = fd_data->src_port;
199
200 if (fd_data->flex_filter) {
201 u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN;
202 __be16 pattern = fd_data->flex_word;
203 u16 off = fd_data->flex_offset;
204
205 *((__force __be16 *)(payload + off)) = pattern;
206 }
207
208 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
209 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
210 if (ret) {
211 dev_info(&pf->pdev->dev,
212 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
213 fd_data->pctype, fd_data->fd_id, ret);
214 /* Free the packet buffer since it wasn't added to the ring */
215 kfree(raw_packet);
216 return -EOPNOTSUPP;
217 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
218 if (add)
219 dev_info(&pf->pdev->dev,
220 "Filter OK for PCTYPE %d loc = %d\n",
221 fd_data->pctype, fd_data->fd_id);
222 else
223 dev_info(&pf->pdev->dev,
224 "Filter deleted for PCTYPE %d loc = %d\n",
225 fd_data->pctype, fd_data->fd_id);
226 }
227
228 if (add)
229 pf->fd_udp4_filter_cnt++;
230 else
231 pf->fd_udp4_filter_cnt--;
232
233 return 0;
234}
235
236#define I40E_TCPIP_DUMMY_PACKET_LEN 54
237/**
238 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
239 * @vsi: pointer to the targeted VSI
240 * @fd_data: the flow director data required for the FDir descriptor
241 * @add: true adds a filter, false removes it
242 *
243 * Returns 0 if the filters were successfully added or removed
244 **/
245static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
246 struct i40e_fdir_filter *fd_data,
247 bool add)
248{
249 struct i40e_pf *pf = vsi->back;
250 struct tcphdr *tcp;
251 struct iphdr *ip;
252 u8 *raw_packet;
253 int ret;
254 /* Dummy packet */
255 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
256 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
258 0x0, 0x72, 0, 0, 0, 0};
259
260 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
261 if (!raw_packet)
262 return -ENOMEM;
263 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
264
265 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
266 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
267 + sizeof(struct iphdr));
268
269 ip->daddr = fd_data->dst_ip;
270 tcp->dest = fd_data->dst_port;
271 ip->saddr = fd_data->src_ip;
272 tcp->source = fd_data->src_port;
273
274 if (fd_data->flex_filter) {
275 u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN;
276 __be16 pattern = fd_data->flex_word;
277 u16 off = fd_data->flex_offset;
278
279 *((__force __be16 *)(payload + off)) = pattern;
280 }
281
282 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
283 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
284 if (ret) {
285 dev_info(&pf->pdev->dev,
286 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
287 fd_data->pctype, fd_data->fd_id, ret);
288 /* Free the packet buffer since it wasn't added to the ring */
289 kfree(raw_packet);
290 return -EOPNOTSUPP;
291 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
292 if (add)
293 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
294 fd_data->pctype, fd_data->fd_id);
295 else
296 dev_info(&pf->pdev->dev,
297 "Filter deleted for PCTYPE %d loc = %d\n",
298 fd_data->pctype, fd_data->fd_id);
299 }
300
301 if (add) {
302 pf->fd_tcp4_filter_cnt++;
303 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
304 I40E_DEBUG_FD & pf->hw.debug_mask)
305 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
306 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
307 } else {
308 pf->fd_tcp4_filter_cnt--;
309 }
310
311 return 0;
312}
313
314#define I40E_SCTPIP_DUMMY_PACKET_LEN 46
315/**
316 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
317 * a specific flow spec
318 * @vsi: pointer to the targeted VSI
319 * @fd_data: the flow director data required for the FDir descriptor
320 * @add: true adds a filter, false removes it
321 *
322 * Returns 0 if the filters were successfully added or removed
323 **/
324static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
325 struct i40e_fdir_filter *fd_data,
326 bool add)
327{
328 struct i40e_pf *pf = vsi->back;
329 struct sctphdr *sctp;
330 struct iphdr *ip;
331 u8 *raw_packet;
332 int ret;
333 /* Dummy packet */
334 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
335 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0,
336 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
337
338 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
339 if (!raw_packet)
340 return -ENOMEM;
341 memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN);
342
343 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
344 sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET
345 + sizeof(struct iphdr));
346
347 ip->daddr = fd_data->dst_ip;
348 sctp->dest = fd_data->dst_port;
349 ip->saddr = fd_data->src_ip;
350 sctp->source = fd_data->src_port;
351
352 if (fd_data->flex_filter) {
353 u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN;
354 __be16 pattern = fd_data->flex_word;
355 u16 off = fd_data->flex_offset;
356
357 *((__force __be16 *)(payload + off)) = pattern;
358 }
359
360 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
361 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
362 if (ret) {
363 dev_info(&pf->pdev->dev,
364 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
365 fd_data->pctype, fd_data->fd_id, ret);
366 /* Free the packet buffer since it wasn't added to the ring */
367 kfree(raw_packet);
368 return -EOPNOTSUPP;
369 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
370 if (add)
371 dev_info(&pf->pdev->dev,
372 "Filter OK for PCTYPE %d loc = %d\n",
373 fd_data->pctype, fd_data->fd_id);
374 else
375 dev_info(&pf->pdev->dev,
376 "Filter deleted for PCTYPE %d loc = %d\n",
377 fd_data->pctype, fd_data->fd_id);
378 }
379
380 if (add)
381 pf->fd_sctp4_filter_cnt++;
382 else
383 pf->fd_sctp4_filter_cnt--;
384
385 return 0;
386}
387
388#define I40E_IP_DUMMY_PACKET_LEN 34
389/**
390 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
391 * a specific flow spec
392 * @vsi: pointer to the targeted VSI
393 * @fd_data: the flow director data required for the FDir descriptor
394 * @add: true adds a filter, false removes it
395 *
396 * Returns 0 if the filters were successfully added or removed
397 **/
398static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
399 struct i40e_fdir_filter *fd_data,
400 bool add)
401{
402 struct i40e_pf *pf = vsi->back;
403 struct iphdr *ip;
404 u8 *raw_packet;
405 int ret;
406 int i;
407 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
408 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
409 0, 0, 0, 0};
410
411 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
412 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
413 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
414 if (!raw_packet)
415 return -ENOMEM;
416 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
417 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
418
419 ip->saddr = fd_data->src_ip;
420 ip->daddr = fd_data->dst_ip;
421 ip->protocol = 0;
422
423 if (fd_data->flex_filter) {
424 u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN;
425 __be16 pattern = fd_data->flex_word;
426 u16 off = fd_data->flex_offset;
427
428 *((__force __be16 *)(payload + off)) = pattern;
429 }
430
431 fd_data->pctype = i;
432 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
433 if (ret) {
434 dev_info(&pf->pdev->dev,
435 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
436 fd_data->pctype, fd_data->fd_id, ret);
437 /* The packet buffer wasn't added to the ring so we
438 * need to free it now.
439 */
440 kfree(raw_packet);
441 return -EOPNOTSUPP;
442 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
443 if (add)
444 dev_info(&pf->pdev->dev,
445 "Filter OK for PCTYPE %d loc = %d\n",
446 fd_data->pctype, fd_data->fd_id);
447 else
448 dev_info(&pf->pdev->dev,
449 "Filter deleted for PCTYPE %d loc = %d\n",
450 fd_data->pctype, fd_data->fd_id);
451 }
452 }
453
454 if (add)
455 pf->fd_ip4_filter_cnt++;
456 else
457 pf->fd_ip4_filter_cnt--;
458
459 return 0;
460}
461
462/**
463 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
464 * @vsi: pointer to the targeted VSI
465 * @input: filter to add or delete
466 * @add: true adds a filter, false removes it
467 *
468 **/
469int i40e_add_del_fdir(struct i40e_vsi *vsi,
470 struct i40e_fdir_filter *input, bool add)
471{
472 struct i40e_pf *pf = vsi->back;
473 int ret;
474
475 switch (input->flow_type & ~FLOW_EXT) {
476 case TCP_V4_FLOW:
477 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
478 break;
479 case UDP_V4_FLOW:
480 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
481 break;
482 case SCTP_V4_FLOW:
483 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
484 break;
485 case IP_USER_FLOW:
486 switch (input->ip4_proto) {
487 case IPPROTO_TCP:
488 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
489 break;
490 case IPPROTO_UDP:
491 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
492 break;
493 case IPPROTO_SCTP:
494 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
495 break;
496 case IPPROTO_IP:
497 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
498 break;
499 default:
500 /* We cannot support masking based on protocol */
501 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n",
502 input->ip4_proto);
503 return -EINVAL;
504 }
505 break;
506 default:
507 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n",
508 input->flow_type);
509 return -EINVAL;
510 }
511
512 /* The buffer allocated here will be normally be freed by
513 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit
514 * completion. In the event of an error adding the buffer to the FDIR
515 * ring, it will immediately be freed. It may also be freed by
516 * i40e_clean_tx_ring() when closing the VSI.
517 */
518 return ret;
519}
520
521/**
522 * i40e_fd_handle_status - check the Programming Status for FD
523 * @rx_ring: the Rx ring for this descriptor
524 * @qword0_raw: qword0
525 * @qword1: qword1 after le_to_cpu
526 * @prog_id: the id originally used for programming
527 *
528 * This is used to verify if the FD programming or invalidation
529 * requested by SW to the HW is successful or not and take actions accordingly.
530 **/
531static void i40e_fd_handle_status(struct i40e_ring *rx_ring, u64 qword0_raw,
532 u64 qword1, u8 prog_id)
533{
534 struct i40e_pf *pf = rx_ring->vsi->back;
535 struct pci_dev *pdev = pf->pdev;
536 struct i40e_32b_rx_wb_qw0 *qw0;
537 u32 fcnt_prog, fcnt_avail;
538 u32 error;
539
540 qw0 = (struct i40e_32b_rx_wb_qw0 *)&qword0_raw;
541 error = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
542 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
543
544 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
545 pf->fd_inv = le32_to_cpu(qw0->hi_dword.fd_id);
546 if (qw0->hi_dword.fd_id != 0 ||
547 (I40E_DEBUG_FD & pf->hw.debug_mask))
548 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
549 pf->fd_inv);
550
551 /* Check if the programming error is for ATR.
552 * If so, auto disable ATR and set a state for
553 * flush in progress. Next time we come here if flush is in
554 * progress do nothing, once flush is complete the state will
555 * be cleared.
556 */
557 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
558 return;
559
560 pf->fd_add_err++;
561 /* store the current atr filter count */
562 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
563
564 if (qw0->hi_dword.fd_id == 0 &&
565 test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) {
566 /* These set_bit() calls aren't atomic with the
567 * test_bit() here, but worse case we potentially
568 * disable ATR and queue a flush right after SB
569 * support is re-enabled. That shouldn't cause an
570 * issue in practice
571 */
572 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
573 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
574 }
575
576 /* filter programming failed most likely due to table full */
577 fcnt_prog = i40e_get_global_fd_count(pf);
578 fcnt_avail = pf->fdir_pf_filter_count;
579 /* If ATR is running fcnt_prog can quickly change,
580 * if we are very close to full, it makes sense to disable
581 * FD ATR/SB and then re-enable it when there is room.
582 */
583 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
584 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
585 !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED,
586 pf->state))
587 if (I40E_DEBUG_FD & pf->hw.debug_mask)
588 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
589 }
590 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
591 if (I40E_DEBUG_FD & pf->hw.debug_mask)
592 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
593 qw0->hi_dword.fd_id);
594 }
595}
596
597/**
598 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
599 * @ring: the ring that owns the buffer
600 * @tx_buffer: the buffer to free
601 **/
602static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
603 struct i40e_tx_buffer *tx_buffer)
604{
605 if (tx_buffer->skb) {
606 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
607 kfree(tx_buffer->raw_buf);
608 else if (ring_is_xdp(ring))
609 xdp_return_frame(tx_buffer->xdpf);
610 else
611 dev_kfree_skb_any(tx_buffer->skb);
612 if (dma_unmap_len(tx_buffer, len))
613 dma_unmap_single(ring->dev,
614 dma_unmap_addr(tx_buffer, dma),
615 dma_unmap_len(tx_buffer, len),
616 DMA_TO_DEVICE);
617 } else if (dma_unmap_len(tx_buffer, len)) {
618 dma_unmap_page(ring->dev,
619 dma_unmap_addr(tx_buffer, dma),
620 dma_unmap_len(tx_buffer, len),
621 DMA_TO_DEVICE);
622 }
623
624 tx_buffer->next_to_watch = NULL;
625 tx_buffer->skb = NULL;
626 dma_unmap_len_set(tx_buffer, len, 0);
627 /* tx_buffer must be completely set up in the transmit path */
628}
629
630/**
631 * i40e_clean_tx_ring - Free any empty Tx buffers
632 * @tx_ring: ring to be cleaned
633 **/
634void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
635{
636 unsigned long bi_size;
637 u16 i;
638
639 if (ring_is_xdp(tx_ring) && tx_ring->xsk_umem) {
640 i40e_xsk_clean_tx_ring(tx_ring);
641 } else {
642 /* ring already cleared, nothing to do */
643 if (!tx_ring->tx_bi)
644 return;
645
646 /* Free all the Tx ring sk_buffs */
647 for (i = 0; i < tx_ring->count; i++)
648 i40e_unmap_and_free_tx_resource(tx_ring,
649 &tx_ring->tx_bi[i]);
650 }
651
652 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
653 memset(tx_ring->tx_bi, 0, bi_size);
654
655 /* Zero out the descriptor ring */
656 memset(tx_ring->desc, 0, tx_ring->size);
657
658 tx_ring->next_to_use = 0;
659 tx_ring->next_to_clean = 0;
660
661 if (!tx_ring->netdev)
662 return;
663
664 /* cleanup Tx queue statistics */
665 netdev_tx_reset_queue(txring_txq(tx_ring));
666}
667
668/**
669 * i40e_free_tx_resources - Free Tx resources per queue
670 * @tx_ring: Tx descriptor ring for a specific queue
671 *
672 * Free all transmit software resources
673 **/
674void i40e_free_tx_resources(struct i40e_ring *tx_ring)
675{
676 i40e_clean_tx_ring(tx_ring);
677 kfree(tx_ring->tx_bi);
678 tx_ring->tx_bi = NULL;
679
680 if (tx_ring->desc) {
681 dma_free_coherent(tx_ring->dev, tx_ring->size,
682 tx_ring->desc, tx_ring->dma);
683 tx_ring->desc = NULL;
684 }
685}
686
687/**
688 * i40e_get_tx_pending - how many tx descriptors not processed
689 * @ring: the ring of descriptors
690 * @in_sw: use SW variables
691 *
692 * Since there is no access to the ring head register
693 * in XL710, we need to use our local copies
694 **/
695u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
696{
697 u32 head, tail;
698
699 if (!in_sw) {
700 head = i40e_get_head(ring);
701 tail = readl(ring->tail);
702 } else {
703 head = ring->next_to_clean;
704 tail = ring->next_to_use;
705 }
706
707 if (head != tail)
708 return (head < tail) ?
709 tail - head : (tail + ring->count - head);
710
711 return 0;
712}
713
714/**
715 * i40e_detect_recover_hung - Function to detect and recover hung_queues
716 * @vsi: pointer to vsi struct with tx queues
717 *
718 * VSI has netdev and netdev has TX queues. This function is to check each of
719 * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
720 **/
721void i40e_detect_recover_hung(struct i40e_vsi *vsi)
722{
723 struct i40e_ring *tx_ring = NULL;
724 struct net_device *netdev;
725 unsigned int i;
726 int packets;
727
728 if (!vsi)
729 return;
730
731 if (test_bit(__I40E_VSI_DOWN, vsi->state))
732 return;
733
734 netdev = vsi->netdev;
735 if (!netdev)
736 return;
737
738 if (!netif_carrier_ok(netdev))
739 return;
740
741 for (i = 0; i < vsi->num_queue_pairs; i++) {
742 tx_ring = vsi->tx_rings[i];
743 if (tx_ring && tx_ring->desc) {
744 /* If packet counter has not changed the queue is
745 * likely stalled, so force an interrupt for this
746 * queue.
747 *
748 * prev_pkt_ctr would be negative if there was no
749 * pending work.
750 */
751 packets = tx_ring->stats.packets & INT_MAX;
752 if (tx_ring->tx_stats.prev_pkt_ctr == packets) {
753 i40e_force_wb(vsi, tx_ring->q_vector);
754 continue;
755 }
756
757 /* Memory barrier between read of packet count and call
758 * to i40e_get_tx_pending()
759 */
760 smp_rmb();
761 tx_ring->tx_stats.prev_pkt_ctr =
762 i40e_get_tx_pending(tx_ring, true) ? packets : -1;
763 }
764 }
765}
766
767/**
768 * i40e_clean_tx_irq - Reclaim resources after transmit completes
769 * @vsi: the VSI we care about
770 * @tx_ring: Tx ring to clean
771 * @napi_budget: Used to determine if we are in netpoll
772 *
773 * Returns true if there's any budget left (e.g. the clean is finished)
774 **/
775static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
776 struct i40e_ring *tx_ring, int napi_budget)
777{
778 int i = tx_ring->next_to_clean;
779 struct i40e_tx_buffer *tx_buf;
780 struct i40e_tx_desc *tx_head;
781 struct i40e_tx_desc *tx_desc;
782 unsigned int total_bytes = 0, total_packets = 0;
783 unsigned int budget = vsi->work_limit;
784
785 tx_buf = &tx_ring->tx_bi[i];
786 tx_desc = I40E_TX_DESC(tx_ring, i);
787 i -= tx_ring->count;
788
789 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
790
791 do {
792 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
793
794 /* if next_to_watch is not set then there is no work pending */
795 if (!eop_desc)
796 break;
797
798 /* prevent any other reads prior to eop_desc */
799 smp_rmb();
800
801 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
802 /* we have caught up to head, no work left to do */
803 if (tx_head == tx_desc)
804 break;
805
806 /* clear next_to_watch to prevent false hangs */
807 tx_buf->next_to_watch = NULL;
808
809 /* update the statistics for this packet */
810 total_bytes += tx_buf->bytecount;
811 total_packets += tx_buf->gso_segs;
812
813 /* free the skb/XDP data */
814 if (ring_is_xdp(tx_ring))
815 xdp_return_frame(tx_buf->xdpf);
816 else
817 napi_consume_skb(tx_buf->skb, napi_budget);
818
819 /* unmap skb header data */
820 dma_unmap_single(tx_ring->dev,
821 dma_unmap_addr(tx_buf, dma),
822 dma_unmap_len(tx_buf, len),
823 DMA_TO_DEVICE);
824
825 /* clear tx_buffer data */
826 tx_buf->skb = NULL;
827 dma_unmap_len_set(tx_buf, len, 0);
828
829 /* unmap remaining buffers */
830 while (tx_desc != eop_desc) {
831 i40e_trace(clean_tx_irq_unmap,
832 tx_ring, tx_desc, tx_buf);
833
834 tx_buf++;
835 tx_desc++;
836 i++;
837 if (unlikely(!i)) {
838 i -= tx_ring->count;
839 tx_buf = tx_ring->tx_bi;
840 tx_desc = I40E_TX_DESC(tx_ring, 0);
841 }
842
843 /* unmap any remaining paged data */
844 if (dma_unmap_len(tx_buf, len)) {
845 dma_unmap_page(tx_ring->dev,
846 dma_unmap_addr(tx_buf, dma),
847 dma_unmap_len(tx_buf, len),
848 DMA_TO_DEVICE);
849 dma_unmap_len_set(tx_buf, len, 0);
850 }
851 }
852
853 /* move us one more past the eop_desc for start of next pkt */
854 tx_buf++;
855 tx_desc++;
856 i++;
857 if (unlikely(!i)) {
858 i -= tx_ring->count;
859 tx_buf = tx_ring->tx_bi;
860 tx_desc = I40E_TX_DESC(tx_ring, 0);
861 }
862
863 prefetch(tx_desc);
864
865 /* update budget accounting */
866 budget--;
867 } while (likely(budget));
868
869 i += tx_ring->count;
870 tx_ring->next_to_clean = i;
871 i40e_update_tx_stats(tx_ring, total_packets, total_bytes);
872 i40e_arm_wb(tx_ring, vsi, budget);
873
874 if (ring_is_xdp(tx_ring))
875 return !!budget;
876
877 /* notify netdev of completed buffers */
878 netdev_tx_completed_queue(txring_txq(tx_ring),
879 total_packets, total_bytes);
880
881#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
882 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
883 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
884 /* Make sure that anybody stopping the queue after this
885 * sees the new next_to_clean.
886 */
887 smp_mb();
888 if (__netif_subqueue_stopped(tx_ring->netdev,
889 tx_ring->queue_index) &&
890 !test_bit(__I40E_VSI_DOWN, vsi->state)) {
891 netif_wake_subqueue(tx_ring->netdev,
892 tx_ring->queue_index);
893 ++tx_ring->tx_stats.restart_queue;
894 }
895 }
896
897 return !!budget;
898}
899
900/**
901 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
902 * @vsi: the VSI we care about
903 * @q_vector: the vector on which to enable writeback
904 *
905 **/
906static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
907 struct i40e_q_vector *q_vector)
908{
909 u16 flags = q_vector->tx.ring[0].flags;
910 u32 val;
911
912 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
913 return;
914
915 if (q_vector->arm_wb_state)
916 return;
917
918 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
919 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
920 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
921
922 wr32(&vsi->back->hw,
923 I40E_PFINT_DYN_CTLN(q_vector->reg_idx),
924 val);
925 } else {
926 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
927 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
928
929 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
930 }
931 q_vector->arm_wb_state = true;
932}
933
934/**
935 * i40e_force_wb - Issue SW Interrupt so HW does a wb
936 * @vsi: the VSI we care about
937 * @q_vector: the vector on which to force writeback
938 *
939 **/
940void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
941{
942 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
943 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
944 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
945 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
946 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
947 /* allow 00 to be written to the index */
948
949 wr32(&vsi->back->hw,
950 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val);
951 } else {
952 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
953 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
954 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
955 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
956 /* allow 00 to be written to the index */
957
958 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
959 }
960}
961
962static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector,
963 struct i40e_ring_container *rc)
964{
965 return &q_vector->rx == rc;
966}
967
968static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector)
969{
970 unsigned int divisor;
971
972 switch (q_vector->vsi->back->hw.phy.link_info.link_speed) {
973 case I40E_LINK_SPEED_40GB:
974 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024;
975 break;
976 case I40E_LINK_SPEED_25GB:
977 case I40E_LINK_SPEED_20GB:
978 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512;
979 break;
980 default:
981 case I40E_LINK_SPEED_10GB:
982 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256;
983 break;
984 case I40E_LINK_SPEED_1GB:
985 case I40E_LINK_SPEED_100MB:
986 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32;
987 break;
988 }
989
990 return divisor;
991}
992
993/**
994 * i40e_update_itr - update the dynamic ITR value based on statistics
995 * @q_vector: structure containing interrupt and ring information
996 * @rc: structure containing ring performance data
997 *
998 * Stores a new ITR value based on packets and byte
999 * counts during the last interrupt. The advantage of per interrupt
1000 * computation is faster updates and more accurate ITR for the current
1001 * traffic pattern. Constants in this function were computed
1002 * based on theoretical maximum wire speed and thresholds were set based
1003 * on testing data as well as attempting to minimize response time
1004 * while increasing bulk throughput.
1005 **/
1006static void i40e_update_itr(struct i40e_q_vector *q_vector,
1007 struct i40e_ring_container *rc)
1008{
1009 unsigned int avg_wire_size, packets, bytes, itr;
1010 unsigned long next_update = jiffies;
1011
1012 /* If we don't have any rings just leave ourselves set for maximum
1013 * possible latency so we take ourselves out of the equation.
1014 */
1015 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
1016 return;
1017
1018 /* For Rx we want to push the delay up and default to low latency.
1019 * for Tx we want to pull the delay down and default to high latency.
1020 */
1021 itr = i40e_container_is_rx(q_vector, rc) ?
1022 I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY :
1023 I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY;
1024
1025 /* If we didn't update within up to 1 - 2 jiffies we can assume
1026 * that either packets are coming in so slow there hasn't been
1027 * any work, or that there is so much work that NAPI is dealing
1028 * with interrupt moderation and we don't need to do anything.
1029 */
1030 if (time_after(next_update, rc->next_update))
1031 goto clear_counts;
1032
1033 /* If itr_countdown is set it means we programmed an ITR within
1034 * the last 4 interrupt cycles. This has a side effect of us
1035 * potentially firing an early interrupt. In order to work around
1036 * this we need to throw out any data received for a few
1037 * interrupts following the update.
1038 */
1039 if (q_vector->itr_countdown) {
1040 itr = rc->target_itr;
1041 goto clear_counts;
1042 }
1043
1044 packets = rc->total_packets;
1045 bytes = rc->total_bytes;
1046
1047 if (i40e_container_is_rx(q_vector, rc)) {
1048 /* If Rx there are 1 to 4 packets and bytes are less than
1049 * 9000 assume insufficient data to use bulk rate limiting
1050 * approach unless Tx is already in bulk rate limiting. We
1051 * are likely latency driven.
1052 */
1053 if (packets && packets < 4 && bytes < 9000 &&
1054 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) {
1055 itr = I40E_ITR_ADAPTIVE_LATENCY;
1056 goto adjust_by_size;
1057 }
1058 } else if (packets < 4) {
1059 /* If we have Tx and Rx ITR maxed and Tx ITR is running in
1060 * bulk mode and we are receiving 4 or fewer packets just
1061 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
1062 * that the Rx can relax.
1063 */
1064 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS &&
1065 (q_vector->rx.target_itr & I40E_ITR_MASK) ==
1066 I40E_ITR_ADAPTIVE_MAX_USECS)
1067 goto clear_counts;
1068 } else if (packets > 32) {
1069 /* If we have processed over 32 packets in a single interrupt
1070 * for Tx assume we need to switch over to "bulk" mode.
1071 */
1072 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY;
1073 }
1074
1075 /* We have no packets to actually measure against. This means
1076 * either one of the other queues on this vector is active or
1077 * we are a Tx queue doing TSO with too high of an interrupt rate.
1078 *
1079 * Between 4 and 56 we can assume that our current interrupt delay
1080 * is only slightly too low. As such we should increase it by a small
1081 * fixed amount.
1082 */
1083 if (packets < 56) {
1084 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC;
1085 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1086 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1087 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1088 }
1089 goto clear_counts;
1090 }
1091
1092 if (packets <= 256) {
1093 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
1094 itr &= I40E_ITR_MASK;
1095
1096 /* Between 56 and 112 is our "goldilocks" zone where we are
1097 * working out "just right". Just report that our current
1098 * ITR is good for us.
1099 */
1100 if (packets <= 112)
1101 goto clear_counts;
1102
1103 /* If packet count is 128 or greater we are likely looking
1104 * at a slight overrun of the delay we want. Try halving
1105 * our delay to see if that will cut the number of packets
1106 * in half per interrupt.
1107 */
1108 itr /= 2;
1109 itr &= I40E_ITR_MASK;
1110 if (itr < I40E_ITR_ADAPTIVE_MIN_USECS)
1111 itr = I40E_ITR_ADAPTIVE_MIN_USECS;
1112
1113 goto clear_counts;
1114 }
1115
1116 /* The paths below assume we are dealing with a bulk ITR since
1117 * number of packets is greater than 256. We are just going to have
1118 * to compute a value and try to bring the count under control,
1119 * though for smaller packet sizes there isn't much we can do as
1120 * NAPI polling will likely be kicking in sooner rather than later.
1121 */
1122 itr = I40E_ITR_ADAPTIVE_BULK;
1123
1124adjust_by_size:
1125 /* If packet counts are 256 or greater we can assume we have a gross
1126 * overestimation of what the rate should be. Instead of trying to fine
1127 * tune it just use the formula below to try and dial in an exact value
1128 * give the current packet size of the frame.
1129 */
1130 avg_wire_size = bytes / packets;
1131
1132 /* The following is a crude approximation of:
1133 * wmem_default / (size + overhead) = desired_pkts_per_int
1134 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
1135 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1136 *
1137 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1138 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1139 * formula down to
1140 *
1141 * (170 * (size + 24)) / (size + 640) = ITR
1142 *
1143 * We first do some math on the packet size and then finally bitshift
1144 * by 8 after rounding up. We also have to account for PCIe link speed
1145 * difference as ITR scales based on this.
1146 */
1147 if (avg_wire_size <= 60) {
1148 /* Start at 250k ints/sec */
1149 avg_wire_size = 4096;
1150 } else if (avg_wire_size <= 380) {
1151 /* 250K ints/sec to 60K ints/sec */
1152 avg_wire_size *= 40;
1153 avg_wire_size += 1696;
1154 } else if (avg_wire_size <= 1084) {
1155 /* 60K ints/sec to 36K ints/sec */
1156 avg_wire_size *= 15;
1157 avg_wire_size += 11452;
1158 } else if (avg_wire_size <= 1980) {
1159 /* 36K ints/sec to 30K ints/sec */
1160 avg_wire_size *= 5;
1161 avg_wire_size += 22420;
1162 } else {
1163 /* plateau at a limit of 30K ints/sec */
1164 avg_wire_size = 32256;
1165 }
1166
1167 /* If we are in low latency mode halve our delay which doubles the
1168 * rate to somewhere between 100K to 16K ints/sec
1169 */
1170 if (itr & I40E_ITR_ADAPTIVE_LATENCY)
1171 avg_wire_size /= 2;
1172
1173 /* Resultant value is 256 times larger than it needs to be. This
1174 * gives us room to adjust the value as needed to either increase
1175 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
1176 *
1177 * Use addition as we have already recorded the new latency flag
1178 * for the ITR value.
1179 */
1180 itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) *
1181 I40E_ITR_ADAPTIVE_MIN_INC;
1182
1183 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1184 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1185 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1186 }
1187
1188clear_counts:
1189 /* write back value */
1190 rc->target_itr = itr;
1191
1192 /* next update should occur within next jiffy */
1193 rc->next_update = next_update + 1;
1194
1195 rc->total_bytes = 0;
1196 rc->total_packets = 0;
1197}
1198
1199static struct i40e_rx_buffer *i40e_rx_bi(struct i40e_ring *rx_ring, u32 idx)
1200{
1201 return &rx_ring->rx_bi[idx];
1202}
1203
1204/**
1205 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
1206 * @rx_ring: rx descriptor ring to store buffers on
1207 * @old_buff: donor buffer to have page reused
1208 *
1209 * Synchronizes page for reuse by the adapter
1210 **/
1211static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
1212 struct i40e_rx_buffer *old_buff)
1213{
1214 struct i40e_rx_buffer *new_buff;
1215 u16 nta = rx_ring->next_to_alloc;
1216
1217 new_buff = i40e_rx_bi(rx_ring, nta);
1218
1219 /* update, and store next to alloc */
1220 nta++;
1221 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1222
1223 /* transfer page from old buffer to new buffer */
1224 new_buff->dma = old_buff->dma;
1225 new_buff->page = old_buff->page;
1226 new_buff->page_offset = old_buff->page_offset;
1227 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1228
1229 rx_ring->rx_stats.page_reuse_count++;
1230
1231 /* clear contents of buffer_info */
1232 old_buff->page = NULL;
1233}
1234
1235/**
1236 * i40e_clean_programming_status - clean the programming status descriptor
1237 * @rx_ring: the rx ring that has this descriptor
1238 * @qword0_raw: qword0
1239 * @qword1: qword1 representing status_error_len in CPU ordering
1240 *
1241 * Flow director should handle FD_FILTER_STATUS to check its filter programming
1242 * status being successful or not and take actions accordingly. FCoE should
1243 * handle its context/filter programming/invalidation status and take actions.
1244 *
1245 * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL.
1246 **/
1247void i40e_clean_programming_status(struct i40e_ring *rx_ring, u64 qword0_raw,
1248 u64 qword1)
1249{
1250 u8 id;
1251
1252 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1253 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1254
1255 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
1256 i40e_fd_handle_status(rx_ring, qword0_raw, qword1, id);
1257}
1258
1259/**
1260 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
1261 * @tx_ring: the tx ring to set up
1262 *
1263 * Return 0 on success, negative on error
1264 **/
1265int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
1266{
1267 struct device *dev = tx_ring->dev;
1268 int bi_size;
1269
1270 if (!dev)
1271 return -ENOMEM;
1272
1273 /* warn if we are about to overwrite the pointer */
1274 WARN_ON(tx_ring->tx_bi);
1275 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1276 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1277 if (!tx_ring->tx_bi)
1278 goto err;
1279
1280 u64_stats_init(&tx_ring->syncp);
1281
1282 /* round up to nearest 4K */
1283 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1284 /* add u32 for head writeback, align after this takes care of
1285 * guaranteeing this is at least one cache line in size
1286 */
1287 tx_ring->size += sizeof(u32);
1288 tx_ring->size = ALIGN(tx_ring->size, 4096);
1289 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1290 &tx_ring->dma, GFP_KERNEL);
1291 if (!tx_ring->desc) {
1292 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1293 tx_ring->size);
1294 goto err;
1295 }
1296
1297 tx_ring->next_to_use = 0;
1298 tx_ring->next_to_clean = 0;
1299 tx_ring->tx_stats.prev_pkt_ctr = -1;
1300 return 0;
1301
1302err:
1303 kfree(tx_ring->tx_bi);
1304 tx_ring->tx_bi = NULL;
1305 return -ENOMEM;
1306}
1307
1308int i40e_alloc_rx_bi(struct i40e_ring *rx_ring)
1309{
1310 unsigned long sz = sizeof(*rx_ring->rx_bi) * rx_ring->count;
1311
1312 rx_ring->rx_bi = kzalloc(sz, GFP_KERNEL);
1313 return rx_ring->rx_bi ? 0 : -ENOMEM;
1314}
1315
1316static void i40e_clear_rx_bi(struct i40e_ring *rx_ring)
1317{
1318 memset(rx_ring->rx_bi, 0, sizeof(*rx_ring->rx_bi) * rx_ring->count);
1319}
1320
1321/**
1322 * i40e_clean_rx_ring - Free Rx buffers
1323 * @rx_ring: ring to be cleaned
1324 **/
1325void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1326{
1327 u16 i;
1328
1329 /* ring already cleared, nothing to do */
1330 if (!rx_ring->rx_bi)
1331 return;
1332
1333 if (rx_ring->skb) {
1334 dev_kfree_skb(rx_ring->skb);
1335 rx_ring->skb = NULL;
1336 }
1337
1338 if (rx_ring->xsk_umem) {
1339 i40e_xsk_clean_rx_ring(rx_ring);
1340 goto skip_free;
1341 }
1342
1343 /* Free all the Rx ring sk_buffs */
1344 for (i = 0; i < rx_ring->count; i++) {
1345 struct i40e_rx_buffer *rx_bi = i40e_rx_bi(rx_ring, i);
1346
1347 if (!rx_bi->page)
1348 continue;
1349
1350 /* Invalidate cache lines that may have been written to by
1351 * device so that we avoid corrupting memory.
1352 */
1353 dma_sync_single_range_for_cpu(rx_ring->dev,
1354 rx_bi->dma,
1355 rx_bi->page_offset,
1356 rx_ring->rx_buf_len,
1357 DMA_FROM_DEVICE);
1358
1359 /* free resources associated with mapping */
1360 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
1361 i40e_rx_pg_size(rx_ring),
1362 DMA_FROM_DEVICE,
1363 I40E_RX_DMA_ATTR);
1364
1365 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
1366
1367 rx_bi->page = NULL;
1368 rx_bi->page_offset = 0;
1369 }
1370
1371skip_free:
1372 if (rx_ring->xsk_umem)
1373 i40e_clear_rx_bi_zc(rx_ring);
1374 else
1375 i40e_clear_rx_bi(rx_ring);
1376
1377 /* Zero out the descriptor ring */
1378 memset(rx_ring->desc, 0, rx_ring->size);
1379
1380 rx_ring->next_to_alloc = 0;
1381 rx_ring->next_to_clean = 0;
1382 rx_ring->next_to_use = 0;
1383}
1384
1385/**
1386 * i40e_free_rx_resources - Free Rx resources
1387 * @rx_ring: ring to clean the resources from
1388 *
1389 * Free all receive software resources
1390 **/
1391void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1392{
1393 i40e_clean_rx_ring(rx_ring);
1394 if (rx_ring->vsi->type == I40E_VSI_MAIN)
1395 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
1396 rx_ring->xdp_prog = NULL;
1397 kfree(rx_ring->rx_bi);
1398 rx_ring->rx_bi = NULL;
1399
1400 if (rx_ring->desc) {
1401 dma_free_coherent(rx_ring->dev, rx_ring->size,
1402 rx_ring->desc, rx_ring->dma);
1403 rx_ring->desc = NULL;
1404 }
1405}
1406
1407/**
1408 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1409 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1410 *
1411 * Returns 0 on success, negative on failure
1412 **/
1413int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1414{
1415 struct device *dev = rx_ring->dev;
1416 int err;
1417
1418 u64_stats_init(&rx_ring->syncp);
1419
1420 /* Round up to nearest 4K */
1421 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1422 rx_ring->size = ALIGN(rx_ring->size, 4096);
1423 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1424 &rx_ring->dma, GFP_KERNEL);
1425
1426 if (!rx_ring->desc) {
1427 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1428 rx_ring->size);
1429 return -ENOMEM;
1430 }
1431
1432 rx_ring->next_to_alloc = 0;
1433 rx_ring->next_to_clean = 0;
1434 rx_ring->next_to_use = 0;
1435
1436 /* XDP RX-queue info only needed for RX rings exposed to XDP */
1437 if (rx_ring->vsi->type == I40E_VSI_MAIN) {
1438 err = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
1439 rx_ring->queue_index);
1440 if (err < 0)
1441 return err;
1442 }
1443
1444 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog;
1445
1446 return 0;
1447}
1448
1449/**
1450 * i40e_release_rx_desc - Store the new tail and head values
1451 * @rx_ring: ring to bump
1452 * @val: new head index
1453 **/
1454void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1455{
1456 rx_ring->next_to_use = val;
1457
1458 /* update next to alloc since we have filled the ring */
1459 rx_ring->next_to_alloc = val;
1460
1461 /* Force memory writes to complete before letting h/w
1462 * know there are new descriptors to fetch. (Only
1463 * applicable for weak-ordered memory model archs,
1464 * such as IA-64).
1465 */
1466 wmb();
1467 writel(val, rx_ring->tail);
1468}
1469
1470/**
1471 * i40e_rx_offset - Return expected offset into page to access data
1472 * @rx_ring: Ring we are requesting offset of
1473 *
1474 * Returns the offset value for ring into the data buffer.
1475 */
1476static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring)
1477{
1478 return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0;
1479}
1480
1481static unsigned int i40e_rx_frame_truesize(struct i40e_ring *rx_ring,
1482 unsigned int size)
1483{
1484 unsigned int truesize;
1485
1486#if (PAGE_SIZE < 8192)
1487 truesize = i40e_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
1488#else
1489 truesize = i40e_rx_offset(rx_ring) ?
1490 SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring)) +
1491 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
1492 SKB_DATA_ALIGN(size);
1493#endif
1494 return truesize;
1495}
1496
1497/**
1498 * i40e_alloc_mapped_page - recycle or make a new page
1499 * @rx_ring: ring to use
1500 * @bi: rx_buffer struct to modify
1501 *
1502 * Returns true if the page was successfully allocated or
1503 * reused.
1504 **/
1505static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
1506 struct i40e_rx_buffer *bi)
1507{
1508 struct page *page = bi->page;
1509 dma_addr_t dma;
1510
1511 /* since we are recycling buffers we should seldom need to alloc */
1512 if (likely(page)) {
1513 rx_ring->rx_stats.page_reuse_count++;
1514 return true;
1515 }
1516
1517 /* alloc new page for storage */
1518 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
1519 if (unlikely(!page)) {
1520 rx_ring->rx_stats.alloc_page_failed++;
1521 return false;
1522 }
1523
1524 /* map page for use */
1525 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1526 i40e_rx_pg_size(rx_ring),
1527 DMA_FROM_DEVICE,
1528 I40E_RX_DMA_ATTR);
1529
1530 /* if mapping failed free memory back to system since
1531 * there isn't much point in holding memory we can't use
1532 */
1533 if (dma_mapping_error(rx_ring->dev, dma)) {
1534 __free_pages(page, i40e_rx_pg_order(rx_ring));
1535 rx_ring->rx_stats.alloc_page_failed++;
1536 return false;
1537 }
1538
1539 bi->dma = dma;
1540 bi->page = page;
1541 bi->page_offset = i40e_rx_offset(rx_ring);
1542 page_ref_add(page, USHRT_MAX - 1);
1543 bi->pagecnt_bias = USHRT_MAX;
1544
1545 return true;
1546}
1547
1548/**
1549 * i40e_alloc_rx_buffers - Replace used receive buffers
1550 * @rx_ring: ring to place buffers on
1551 * @cleaned_count: number of buffers to replace
1552 *
1553 * Returns false if all allocations were successful, true if any fail
1554 **/
1555bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1556{
1557 u16 ntu = rx_ring->next_to_use;
1558 union i40e_rx_desc *rx_desc;
1559 struct i40e_rx_buffer *bi;
1560
1561 /* do nothing if no valid netdev defined */
1562 if (!rx_ring->netdev || !cleaned_count)
1563 return false;
1564
1565 rx_desc = I40E_RX_DESC(rx_ring, ntu);
1566 bi = i40e_rx_bi(rx_ring, ntu);
1567
1568 do {
1569 if (!i40e_alloc_mapped_page(rx_ring, bi))
1570 goto no_buffers;
1571
1572 /* sync the buffer for use by the device */
1573 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1574 bi->page_offset,
1575 rx_ring->rx_buf_len,
1576 DMA_FROM_DEVICE);
1577
1578 /* Refresh the desc even if buffer_addrs didn't change
1579 * because each write-back erases this info.
1580 */
1581 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1582
1583 rx_desc++;
1584 bi++;
1585 ntu++;
1586 if (unlikely(ntu == rx_ring->count)) {
1587 rx_desc = I40E_RX_DESC(rx_ring, 0);
1588 bi = i40e_rx_bi(rx_ring, 0);
1589 ntu = 0;
1590 }
1591
1592 /* clear the status bits for the next_to_use descriptor */
1593 rx_desc->wb.qword1.status_error_len = 0;
1594
1595 cleaned_count--;
1596 } while (cleaned_count);
1597
1598 if (rx_ring->next_to_use != ntu)
1599 i40e_release_rx_desc(rx_ring, ntu);
1600
1601 return false;
1602
1603no_buffers:
1604 if (rx_ring->next_to_use != ntu)
1605 i40e_release_rx_desc(rx_ring, ntu);
1606
1607 /* make sure to come back via polling to try again after
1608 * allocation failure
1609 */
1610 return true;
1611}
1612
1613/**
1614 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1615 * @vsi: the VSI we care about
1616 * @skb: skb currently being received and modified
1617 * @rx_desc: the receive descriptor
1618 **/
1619static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1620 struct sk_buff *skb,
1621 union i40e_rx_desc *rx_desc)
1622{
1623 struct i40e_rx_ptype_decoded decoded;
1624 u32 rx_error, rx_status;
1625 bool ipv4, ipv6;
1626 u8 ptype;
1627 u64 qword;
1628
1629 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1630 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
1631 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1632 I40E_RXD_QW1_ERROR_SHIFT;
1633 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1634 I40E_RXD_QW1_STATUS_SHIFT;
1635 decoded = decode_rx_desc_ptype(ptype);
1636
1637 skb->ip_summed = CHECKSUM_NONE;
1638
1639 skb_checksum_none_assert(skb);
1640
1641 /* Rx csum enabled and ip headers found? */
1642 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1643 return;
1644
1645 /* did the hardware decode the packet and checksum? */
1646 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1647 return;
1648
1649 /* both known and outer_ip must be set for the below code to work */
1650 if (!(decoded.known && decoded.outer_ip))
1651 return;
1652
1653 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1654 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
1655 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1656 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1657
1658 if (ipv4 &&
1659 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1660 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1661 goto checksum_fail;
1662
1663 /* likely incorrect csum if alternate IP extension headers found */
1664 if (ipv6 &&
1665 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1666 /* don't increment checksum err here, non-fatal err */
1667 return;
1668
1669 /* there was some L4 error, count error and punt packet to the stack */
1670 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1671 goto checksum_fail;
1672
1673 /* handle packets that were not able to be checksummed due
1674 * to arrival speed, in this case the stack can compute
1675 * the csum.
1676 */
1677 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1678 return;
1679
1680 /* If there is an outer header present that might contain a checksum
1681 * we need to bump the checksum level by 1 to reflect the fact that
1682 * we are indicating we validated the inner checksum.
1683 */
1684 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
1685 skb->csum_level = 1;
1686
1687 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
1688 switch (decoded.inner_prot) {
1689 case I40E_RX_PTYPE_INNER_PROT_TCP:
1690 case I40E_RX_PTYPE_INNER_PROT_UDP:
1691 case I40E_RX_PTYPE_INNER_PROT_SCTP:
1692 skb->ip_summed = CHECKSUM_UNNECESSARY;
1693 fallthrough;
1694 default:
1695 break;
1696 }
1697
1698 return;
1699
1700checksum_fail:
1701 vsi->back->hw_csum_rx_error++;
1702}
1703
1704/**
1705 * i40e_ptype_to_htype - get a hash type
1706 * @ptype: the ptype value from the descriptor
1707 *
1708 * Returns a hash type to be used by skb_set_hash
1709 **/
1710static inline int i40e_ptype_to_htype(u8 ptype)
1711{
1712 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1713
1714 if (!decoded.known)
1715 return PKT_HASH_TYPE_NONE;
1716
1717 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1718 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1719 return PKT_HASH_TYPE_L4;
1720 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1721 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1722 return PKT_HASH_TYPE_L3;
1723 else
1724 return PKT_HASH_TYPE_L2;
1725}
1726
1727/**
1728 * i40e_rx_hash - set the hash value in the skb
1729 * @ring: descriptor ring
1730 * @rx_desc: specific descriptor
1731 * @skb: skb currently being received and modified
1732 * @rx_ptype: Rx packet type
1733 **/
1734static inline void i40e_rx_hash(struct i40e_ring *ring,
1735 union i40e_rx_desc *rx_desc,
1736 struct sk_buff *skb,
1737 u8 rx_ptype)
1738{
1739 u32 hash;
1740 const __le64 rss_mask =
1741 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1742 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1743
1744 if (!(ring->netdev->features & NETIF_F_RXHASH))
1745 return;
1746
1747 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1748 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1749 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1750 }
1751}
1752
1753/**
1754 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
1755 * @rx_ring: rx descriptor ring packet is being transacted on
1756 * @rx_desc: pointer to the EOP Rx descriptor
1757 * @skb: pointer to current skb being populated
1758 * @rx_ptype: the packet type decoded by hardware
1759 *
1760 * This function checks the ring, descriptor, and packet information in
1761 * order to populate the hash, checksum, VLAN, protocol, and
1762 * other fields within the skb.
1763 **/
1764void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1765 union i40e_rx_desc *rx_desc, struct sk_buff *skb)
1766{
1767 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1768 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1769 I40E_RXD_QW1_STATUS_SHIFT;
1770 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
1771 u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1772 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;
1773 u8 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1774 I40E_RXD_QW1_PTYPE_SHIFT;
1775
1776 if (unlikely(tsynvalid))
1777 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1778
1779 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1780
1781 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
1782
1783 skb_record_rx_queue(skb, rx_ring->queue_index);
1784
1785 if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1786 u16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;
1787
1788 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1789 le16_to_cpu(vlan_tag));
1790 }
1791
1792 /* modifies the skb - consumes the enet header */
1793 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1794}
1795
1796/**
1797 * i40e_cleanup_headers - Correct empty headers
1798 * @rx_ring: rx descriptor ring packet is being transacted on
1799 * @skb: pointer to current skb being fixed
1800 * @rx_desc: pointer to the EOP Rx descriptor
1801 *
1802 * Also address the case where we are pulling data in on pages only
1803 * and as such no data is present in the skb header.
1804 *
1805 * In addition if skb is not at least 60 bytes we need to pad it so that
1806 * it is large enough to qualify as a valid Ethernet frame.
1807 *
1808 * Returns true if an error was encountered and skb was freed.
1809 **/
1810static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb,
1811 union i40e_rx_desc *rx_desc)
1812
1813{
1814 /* XDP packets use error pointer so abort at this point */
1815 if (IS_ERR(skb))
1816 return true;
1817
1818 /* ERR_MASK will only have valid bits if EOP set, and
1819 * what we are doing here is actually checking
1820 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1821 * the error field
1822 */
1823 if (unlikely(i40e_test_staterr(rx_desc,
1824 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1825 dev_kfree_skb_any(skb);
1826 return true;
1827 }
1828
1829 /* if eth_skb_pad returns an error the skb was freed */
1830 if (eth_skb_pad(skb))
1831 return true;
1832
1833 return false;
1834}
1835
1836/**
1837 * i40e_page_is_reusable - check if any reuse is possible
1838 * @page: page struct to check
1839 *
1840 * A page is not reusable if it was allocated under low memory
1841 * conditions, or it's not in the same NUMA node as this CPU.
1842 */
1843static inline bool i40e_page_is_reusable(struct page *page)
1844{
1845 return (page_to_nid(page) == numa_mem_id()) &&
1846 !page_is_pfmemalloc(page);
1847}
1848
1849/**
1850 * i40e_can_reuse_rx_page - Determine if this page can be reused by
1851 * the adapter for another receive
1852 *
1853 * @rx_buffer: buffer containing the page
1854 *
1855 * If page is reusable, rx_buffer->page_offset is adjusted to point to
1856 * an unused region in the page.
1857 *
1858 * For small pages, @truesize will be a constant value, half the size
1859 * of the memory at page. We'll attempt to alternate between high and
1860 * low halves of the page, with one half ready for use by the hardware
1861 * and the other half being consumed by the stack. We use the page
1862 * ref count to determine whether the stack has finished consuming the
1863 * portion of this page that was passed up with a previous packet. If
1864 * the page ref count is >1, we'll assume the "other" half page is
1865 * still busy, and this page cannot be reused.
1866 *
1867 * For larger pages, @truesize will be the actual space used by the
1868 * received packet (adjusted upward to an even multiple of the cache
1869 * line size). This will advance through the page by the amount
1870 * actually consumed by the received packets while there is still
1871 * space for a buffer. Each region of larger pages will be used at
1872 * most once, after which the page will not be reused.
1873 *
1874 * In either case, if the page is reusable its refcount is increased.
1875 **/
1876static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer)
1877{
1878 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1879 struct page *page = rx_buffer->page;
1880
1881 /* Is any reuse possible? */
1882 if (unlikely(!i40e_page_is_reusable(page)))
1883 return false;
1884
1885#if (PAGE_SIZE < 8192)
1886 /* if we are only owner of page we can reuse it */
1887 if (unlikely((page_count(page) - pagecnt_bias) > 1))
1888 return false;
1889#else
1890#define I40E_LAST_OFFSET \
1891 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
1892 if (rx_buffer->page_offset > I40E_LAST_OFFSET)
1893 return false;
1894#endif
1895
1896 /* If we have drained the page fragment pool we need to update
1897 * the pagecnt_bias and page count so that we fully restock the
1898 * number of references the driver holds.
1899 */
1900 if (unlikely(pagecnt_bias == 1)) {
1901 page_ref_add(page, USHRT_MAX - 1);
1902 rx_buffer->pagecnt_bias = USHRT_MAX;
1903 }
1904
1905 return true;
1906}
1907
1908/**
1909 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
1910 * @rx_ring: rx descriptor ring to transact packets on
1911 * @rx_buffer: buffer containing page to add
1912 * @skb: sk_buff to place the data into
1913 * @size: packet length from rx_desc
1914 *
1915 * This function will add the data contained in rx_buffer->page to the skb.
1916 * It will just attach the page as a frag to the skb.
1917 *
1918 * The function will then update the page offset.
1919 **/
1920static void i40e_add_rx_frag(struct i40e_ring *rx_ring,
1921 struct i40e_rx_buffer *rx_buffer,
1922 struct sk_buff *skb,
1923 unsigned int size)
1924{
1925#if (PAGE_SIZE < 8192)
1926 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1927#else
1928 unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring));
1929#endif
1930
1931 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1932 rx_buffer->page_offset, size, truesize);
1933
1934 /* page is being used so we must update the page offset */
1935#if (PAGE_SIZE < 8192)
1936 rx_buffer->page_offset ^= truesize;
1937#else
1938 rx_buffer->page_offset += truesize;
1939#endif
1940}
1941
1942/**
1943 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
1944 * @rx_ring: rx descriptor ring to transact packets on
1945 * @size: size of buffer to add to skb
1946 *
1947 * This function will pull an Rx buffer from the ring and synchronize it
1948 * for use by the CPU.
1949 */
1950static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
1951 const unsigned int size)
1952{
1953 struct i40e_rx_buffer *rx_buffer;
1954
1955 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
1956 prefetchw(rx_buffer->page);
1957
1958 /* we are reusing so sync this buffer for CPU use */
1959 dma_sync_single_range_for_cpu(rx_ring->dev,
1960 rx_buffer->dma,
1961 rx_buffer->page_offset,
1962 size,
1963 DMA_FROM_DEVICE);
1964
1965 /* We have pulled a buffer for use, so decrement pagecnt_bias */
1966 rx_buffer->pagecnt_bias--;
1967
1968 return rx_buffer;
1969}
1970
1971/**
1972 * i40e_construct_skb - Allocate skb and populate it
1973 * @rx_ring: rx descriptor ring to transact packets on
1974 * @rx_buffer: rx buffer to pull data from
1975 * @xdp: xdp_buff pointing to the data
1976 *
1977 * This function allocates an skb. It then populates it with the page
1978 * data from the current receive descriptor, taking care to set up the
1979 * skb correctly.
1980 */
1981static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
1982 struct i40e_rx_buffer *rx_buffer,
1983 struct xdp_buff *xdp)
1984{
1985 unsigned int size = xdp->data_end - xdp->data;
1986#if (PAGE_SIZE < 8192)
1987 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1988#else
1989 unsigned int truesize = SKB_DATA_ALIGN(size);
1990#endif
1991 unsigned int headlen;
1992 struct sk_buff *skb;
1993
1994 /* prefetch first cache line of first page */
1995 prefetch(xdp->data);
1996#if L1_CACHE_BYTES < 128
1997 prefetch(xdp->data + L1_CACHE_BYTES);
1998#endif
1999 /* Note, we get here by enabling legacy-rx via:
2000 *
2001 * ethtool --set-priv-flags <dev> legacy-rx on
2002 *
2003 * In this mode, we currently get 0 extra XDP headroom as
2004 * opposed to having legacy-rx off, where we process XDP
2005 * packets going to stack via i40e_build_skb(). The latter
2006 * provides us currently with 192 bytes of headroom.
2007 *
2008 * For i40e_construct_skb() mode it means that the
2009 * xdp->data_meta will always point to xdp->data, since
2010 * the helper cannot expand the head. Should this ever
2011 * change in future for legacy-rx mode on, then lets also
2012 * add xdp->data_meta handling here.
2013 */
2014
2015 /* allocate a skb to store the frags */
2016 skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
2017 I40E_RX_HDR_SIZE,
2018 GFP_ATOMIC | __GFP_NOWARN);
2019 if (unlikely(!skb))
2020 return NULL;
2021
2022 /* Determine available headroom for copy */
2023 headlen = size;
2024 if (headlen > I40E_RX_HDR_SIZE)
2025 headlen = eth_get_headlen(skb->dev, xdp->data,
2026 I40E_RX_HDR_SIZE);
2027
2028 /* align pull length to size of long to optimize memcpy performance */
2029 memcpy(__skb_put(skb, headlen), xdp->data,
2030 ALIGN(headlen, sizeof(long)));
2031
2032 /* update all of the pointers */
2033 size -= headlen;
2034 if (size) {
2035 skb_add_rx_frag(skb, 0, rx_buffer->page,
2036 rx_buffer->page_offset + headlen,
2037 size, truesize);
2038
2039 /* buffer is used by skb, update page_offset */
2040#if (PAGE_SIZE < 8192)
2041 rx_buffer->page_offset ^= truesize;
2042#else
2043 rx_buffer->page_offset += truesize;
2044#endif
2045 } else {
2046 /* buffer is unused, reset bias back to rx_buffer */
2047 rx_buffer->pagecnt_bias++;
2048 }
2049
2050 return skb;
2051}
2052
2053/**
2054 * i40e_build_skb - Build skb around an existing buffer
2055 * @rx_ring: Rx descriptor ring to transact packets on
2056 * @rx_buffer: Rx buffer to pull data from
2057 * @xdp: xdp_buff pointing to the data
2058 *
2059 * This function builds an skb around an existing Rx buffer, taking care
2060 * to set up the skb correctly and avoid any memcpy overhead.
2061 */
2062static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
2063 struct i40e_rx_buffer *rx_buffer,
2064 struct xdp_buff *xdp)
2065{
2066 unsigned int metasize = xdp->data - xdp->data_meta;
2067#if (PAGE_SIZE < 8192)
2068 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2069#else
2070 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2071 SKB_DATA_ALIGN(xdp->data_end -
2072 xdp->data_hard_start);
2073#endif
2074 struct sk_buff *skb;
2075
2076 /* Prefetch first cache line of first page. If xdp->data_meta
2077 * is unused, this points exactly as xdp->data, otherwise we
2078 * likely have a consumer accessing first few bytes of meta
2079 * data, and then actual data.
2080 */
2081 prefetch(xdp->data_meta);
2082#if L1_CACHE_BYTES < 128
2083 prefetch(xdp->data_meta + L1_CACHE_BYTES);
2084#endif
2085 /* build an skb around the page buffer */
2086 skb = build_skb(xdp->data_hard_start, truesize);
2087 if (unlikely(!skb))
2088 return NULL;
2089
2090 /* update pointers within the skb to store the data */
2091 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2092 __skb_put(skb, xdp->data_end - xdp->data);
2093 if (metasize)
2094 skb_metadata_set(skb, metasize);
2095
2096 /* buffer is used by skb, update page_offset */
2097#if (PAGE_SIZE < 8192)
2098 rx_buffer->page_offset ^= truesize;
2099#else
2100 rx_buffer->page_offset += truesize;
2101#endif
2102
2103 return skb;
2104}
2105
2106/**
2107 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
2108 * @rx_ring: rx descriptor ring to transact packets on
2109 * @rx_buffer: rx buffer to pull data from
2110 *
2111 * This function will clean up the contents of the rx_buffer. It will
2112 * either recycle the buffer or unmap it and free the associated resources.
2113 */
2114static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
2115 struct i40e_rx_buffer *rx_buffer)
2116{
2117 if (i40e_can_reuse_rx_page(rx_buffer)) {
2118 /* hand second half of page back to the ring */
2119 i40e_reuse_rx_page(rx_ring, rx_buffer);
2120 } else {
2121 /* we are not reusing the buffer so unmap it */
2122 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2123 i40e_rx_pg_size(rx_ring),
2124 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
2125 __page_frag_cache_drain(rx_buffer->page,
2126 rx_buffer->pagecnt_bias);
2127 /* clear contents of buffer_info */
2128 rx_buffer->page = NULL;
2129 }
2130}
2131
2132/**
2133 * i40e_is_non_eop - process handling of non-EOP buffers
2134 * @rx_ring: Rx ring being processed
2135 * @rx_desc: Rx descriptor for current buffer
2136 * @skb: Current socket buffer containing buffer in progress
2137 *
2138 * This function updates next to clean. If the buffer is an EOP buffer
2139 * this function exits returning false, otherwise it will place the
2140 * sk_buff in the next buffer to be chained and return true indicating
2141 * that this is in fact a non-EOP buffer.
2142 **/
2143static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
2144 union i40e_rx_desc *rx_desc,
2145 struct sk_buff *skb)
2146{
2147 u32 ntc = rx_ring->next_to_clean + 1;
2148
2149 /* fetch, update, and store next to clean */
2150 ntc = (ntc < rx_ring->count) ? ntc : 0;
2151 rx_ring->next_to_clean = ntc;
2152
2153 prefetch(I40E_RX_DESC(rx_ring, ntc));
2154
2155 /* if we are the last buffer then there is nothing else to do */
2156#define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
2157 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
2158 return false;
2159
2160 rx_ring->rx_stats.non_eop_descs++;
2161
2162 return true;
2163}
2164
2165static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
2166 struct i40e_ring *xdp_ring);
2167
2168int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring)
2169{
2170 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2171
2172 if (unlikely(!xdpf))
2173 return I40E_XDP_CONSUMED;
2174
2175 return i40e_xmit_xdp_ring(xdpf, xdp_ring);
2176}
2177
2178/**
2179 * i40e_run_xdp - run an XDP program
2180 * @rx_ring: Rx ring being processed
2181 * @xdp: XDP buffer containing the frame
2182 **/
2183static struct sk_buff *i40e_run_xdp(struct i40e_ring *rx_ring,
2184 struct xdp_buff *xdp)
2185{
2186 int err, result = I40E_XDP_PASS;
2187 struct i40e_ring *xdp_ring;
2188 struct bpf_prog *xdp_prog;
2189 u32 act;
2190
2191 rcu_read_lock();
2192 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2193
2194 if (!xdp_prog)
2195 goto xdp_out;
2196
2197 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2198
2199 act = bpf_prog_run_xdp(xdp_prog, xdp);
2200 switch (act) {
2201 case XDP_PASS:
2202 break;
2203 case XDP_TX:
2204 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2205 result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring);
2206 break;
2207 case XDP_REDIRECT:
2208 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog);
2209 result = !err ? I40E_XDP_REDIR : I40E_XDP_CONSUMED;
2210 break;
2211 default:
2212 bpf_warn_invalid_xdp_action(act);
2213 fallthrough;
2214 case XDP_ABORTED:
2215 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2216 fallthrough; /* handle aborts by dropping packet */
2217 case XDP_DROP:
2218 result = I40E_XDP_CONSUMED;
2219 break;
2220 }
2221xdp_out:
2222 rcu_read_unlock();
2223 return ERR_PTR(-result);
2224}
2225
2226/**
2227 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region
2228 * @rx_ring: Rx ring
2229 * @rx_buffer: Rx buffer to adjust
2230 * @size: Size of adjustment
2231 **/
2232static void i40e_rx_buffer_flip(struct i40e_ring *rx_ring,
2233 struct i40e_rx_buffer *rx_buffer,
2234 unsigned int size)
2235{
2236 unsigned int truesize = i40e_rx_frame_truesize(rx_ring, size);
2237
2238#if (PAGE_SIZE < 8192)
2239 rx_buffer->page_offset ^= truesize;
2240#else
2241 rx_buffer->page_offset += truesize;
2242#endif
2243}
2244
2245/**
2246 * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register
2247 * @xdp_ring: XDP Tx ring
2248 *
2249 * This function updates the XDP Tx ring tail register.
2250 **/
2251void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring)
2252{
2253 /* Force memory writes to complete before letting h/w
2254 * know there are new descriptors to fetch.
2255 */
2256 wmb();
2257 writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
2258}
2259
2260/**
2261 * i40e_update_rx_stats - Update Rx ring statistics
2262 * @rx_ring: rx descriptor ring
2263 * @total_rx_bytes: number of bytes received
2264 * @total_rx_packets: number of packets received
2265 *
2266 * This function updates the Rx ring statistics.
2267 **/
2268void i40e_update_rx_stats(struct i40e_ring *rx_ring,
2269 unsigned int total_rx_bytes,
2270 unsigned int total_rx_packets)
2271{
2272 u64_stats_update_begin(&rx_ring->syncp);
2273 rx_ring->stats.packets += total_rx_packets;
2274 rx_ring->stats.bytes += total_rx_bytes;
2275 u64_stats_update_end(&rx_ring->syncp);
2276 rx_ring->q_vector->rx.total_packets += total_rx_packets;
2277 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
2278}
2279
2280/**
2281 * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map
2282 * @rx_ring: Rx ring
2283 * @xdp_res: Result of the receive batch
2284 *
2285 * This function bumps XDP Tx tail and/or flush redirect map, and
2286 * should be called when a batch of packets has been processed in the
2287 * napi loop.
2288 **/
2289void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res)
2290{
2291 if (xdp_res & I40E_XDP_REDIR)
2292 xdp_do_flush_map();
2293
2294 if (xdp_res & I40E_XDP_TX) {
2295 struct i40e_ring *xdp_ring =
2296 rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2297
2298 i40e_xdp_ring_update_tail(xdp_ring);
2299 }
2300}
2301
2302/**
2303 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2304 * @rx_ring: rx descriptor ring to transact packets on
2305 * @budget: Total limit on number of packets to process
2306 *
2307 * This function provides a "bounce buffer" approach to Rx interrupt
2308 * processing. The advantage to this is that on systems that have
2309 * expensive overhead for IOMMU access this provides a means of avoiding
2310 * it by maintaining the mapping of the page to the system.
2311 *
2312 * Returns amount of work completed
2313 **/
2314static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
2315{
2316 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2317 struct sk_buff *skb = rx_ring->skb;
2318 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
2319 unsigned int xdp_xmit = 0;
2320 bool failure = false;
2321 struct xdp_buff xdp;
2322
2323#if (PAGE_SIZE < 8192)
2324 xdp.frame_sz = i40e_rx_frame_truesize(rx_ring, 0);
2325#endif
2326 xdp.rxq = &rx_ring->xdp_rxq;
2327
2328 while (likely(total_rx_packets < (unsigned int)budget)) {
2329 struct i40e_rx_buffer *rx_buffer;
2330 union i40e_rx_desc *rx_desc;
2331 unsigned int size;
2332 u64 qword;
2333
2334 /* return some buffers to hardware, one at a time is too slow */
2335 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
2336 failure = failure ||
2337 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
2338 cleaned_count = 0;
2339 }
2340
2341 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
2342
2343 /* status_error_len will always be zero for unused descriptors
2344 * because it's cleared in cleanup, and overlaps with hdr_addr
2345 * which is always zero because packet split isn't used, if the
2346 * hardware wrote DD then the length will be non-zero
2347 */
2348 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2349
2350 /* This memory barrier is needed to keep us from reading
2351 * any other fields out of the rx_desc until we have
2352 * verified the descriptor has been written back.
2353 */
2354 dma_rmb();
2355
2356 if (i40e_rx_is_programming_status(qword)) {
2357 i40e_clean_programming_status(rx_ring,
2358 rx_desc->raw.qword[0],
2359 qword);
2360 rx_buffer = i40e_rx_bi(rx_ring, rx_ring->next_to_clean);
2361 i40e_inc_ntc(rx_ring);
2362 i40e_reuse_rx_page(rx_ring, rx_buffer);
2363 cleaned_count++;
2364 continue;
2365 }
2366
2367 size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
2368 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
2369 if (!size)
2370 break;
2371
2372 i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb);
2373 rx_buffer = i40e_get_rx_buffer(rx_ring, size);
2374
2375 /* retrieve a buffer from the ring */
2376 if (!skb) {
2377 xdp.data = page_address(rx_buffer->page) +
2378 rx_buffer->page_offset;
2379 xdp.data_meta = xdp.data;
2380 xdp.data_hard_start = xdp.data -
2381 i40e_rx_offset(rx_ring);
2382 xdp.data_end = xdp.data + size;
2383#if (PAGE_SIZE > 4096)
2384 /* At larger PAGE_SIZE, frame_sz depend on len size */
2385 xdp.frame_sz = i40e_rx_frame_truesize(rx_ring, size);
2386#endif
2387 skb = i40e_run_xdp(rx_ring, &xdp);
2388 }
2389
2390 if (IS_ERR(skb)) {
2391 unsigned int xdp_res = -PTR_ERR(skb);
2392
2393 if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) {
2394 xdp_xmit |= xdp_res;
2395 i40e_rx_buffer_flip(rx_ring, rx_buffer, size);
2396 } else {
2397 rx_buffer->pagecnt_bias++;
2398 }
2399 total_rx_bytes += size;
2400 total_rx_packets++;
2401 } else if (skb) {
2402 i40e_add_rx_frag(rx_ring, rx_buffer, skb, size);
2403 } else if (ring_uses_build_skb(rx_ring)) {
2404 skb = i40e_build_skb(rx_ring, rx_buffer, &xdp);
2405 } else {
2406 skb = i40e_construct_skb(rx_ring, rx_buffer, &xdp);
2407 }
2408
2409 /* exit if we failed to retrieve a buffer */
2410 if (!skb) {
2411 rx_ring->rx_stats.alloc_buff_failed++;
2412 rx_buffer->pagecnt_bias++;
2413 break;
2414 }
2415
2416 i40e_put_rx_buffer(rx_ring, rx_buffer);
2417 cleaned_count++;
2418
2419 if (i40e_is_non_eop(rx_ring, rx_desc, skb))
2420 continue;
2421
2422 if (i40e_cleanup_headers(rx_ring, skb, rx_desc)) {
2423 skb = NULL;
2424 continue;
2425 }
2426
2427 /* probably a little skewed due to removing CRC */
2428 total_rx_bytes += skb->len;
2429
2430 /* populate checksum, VLAN, and protocol */
2431 i40e_process_skb_fields(rx_ring, rx_desc, skb);
2432
2433 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
2434 napi_gro_receive(&rx_ring->q_vector->napi, skb);
2435 skb = NULL;
2436
2437 /* update budget accounting */
2438 total_rx_packets++;
2439 }
2440
2441 i40e_finalize_xdp_rx(rx_ring, xdp_xmit);
2442 rx_ring->skb = skb;
2443
2444 i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets);
2445
2446 /* guarantee a trip back through this routine if there was a failure */
2447 return failure ? budget : (int)total_rx_packets;
2448}
2449
2450static inline u32 i40e_buildreg_itr(const int type, u16 itr)
2451{
2452 u32 val;
2453
2454 /* We don't bother with setting the CLEARPBA bit as the data sheet
2455 * points out doing so is "meaningless since it was already
2456 * auto-cleared". The auto-clearing happens when the interrupt is
2457 * asserted.
2458 *
2459 * Hardware errata 28 for also indicates that writing to a
2460 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
2461 * an event in the PBA anyway so we need to rely on the automask
2462 * to hold pending events for us until the interrupt is re-enabled
2463 *
2464 * The itr value is reported in microseconds, and the register
2465 * value is recorded in 2 microsecond units. For this reason we
2466 * only need to shift by the interval shift - 1 instead of the
2467 * full value.
2468 */
2469 itr &= I40E_ITR_MASK;
2470
2471 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2472 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
2473 (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1));
2474
2475 return val;
2476}
2477
2478/* a small macro to shorten up some long lines */
2479#define INTREG I40E_PFINT_DYN_CTLN
2480
2481/* The act of updating the ITR will cause it to immediately trigger. In order
2482 * to prevent this from throwing off adaptive update statistics we defer the
2483 * update so that it can only happen so often. So after either Tx or Rx are
2484 * updated we make the adaptive scheme wait until either the ITR completely
2485 * expires via the next_update expiration or we have been through at least
2486 * 3 interrupts.
2487 */
2488#define ITR_COUNTDOWN_START 3
2489
2490/**
2491 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
2492 * @vsi: the VSI we care about
2493 * @q_vector: q_vector for which itr is being updated and interrupt enabled
2494 *
2495 **/
2496static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
2497 struct i40e_q_vector *q_vector)
2498{
2499 struct i40e_hw *hw = &vsi->back->hw;
2500 u32 intval;
2501
2502 /* If we don't have MSIX, then we only need to re-enable icr0 */
2503 if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {
2504 i40e_irq_dynamic_enable_icr0(vsi->back);
2505 return;
2506 }
2507
2508 /* These will do nothing if dynamic updates are not enabled */
2509 i40e_update_itr(q_vector, &q_vector->tx);
2510 i40e_update_itr(q_vector, &q_vector->rx);
2511
2512 /* This block of logic allows us to get away with only updating
2513 * one ITR value with each interrupt. The idea is to perform a
2514 * pseudo-lazy update with the following criteria.
2515 *
2516 * 1. Rx is given higher priority than Tx if both are in same state
2517 * 2. If we must reduce an ITR that is given highest priority.
2518 * 3. We then give priority to increasing ITR based on amount.
2519 */
2520 if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
2521 /* Rx ITR needs to be reduced, this is highest priority */
2522 intval = i40e_buildreg_itr(I40E_RX_ITR,
2523 q_vector->rx.target_itr);
2524 q_vector->rx.current_itr = q_vector->rx.target_itr;
2525 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2526 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
2527 ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
2528 (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
2529 /* Tx ITR needs to be reduced, this is second priority
2530 * Tx ITR needs to be increased more than Rx, fourth priority
2531 */
2532 intval = i40e_buildreg_itr(I40E_TX_ITR,
2533 q_vector->tx.target_itr);
2534 q_vector->tx.current_itr = q_vector->tx.target_itr;
2535 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2536 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
2537 /* Rx ITR needs to be increased, third priority */
2538 intval = i40e_buildreg_itr(I40E_RX_ITR,
2539 q_vector->rx.target_itr);
2540 q_vector->rx.current_itr = q_vector->rx.target_itr;
2541 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2542 } else {
2543 /* No ITR update, lowest priority */
2544 intval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
2545 if (q_vector->itr_countdown)
2546 q_vector->itr_countdown--;
2547 }
2548
2549 if (!test_bit(__I40E_VSI_DOWN, vsi->state))
2550 wr32(hw, INTREG(q_vector->reg_idx), intval);
2551}
2552
2553/**
2554 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
2555 * @napi: napi struct with our devices info in it
2556 * @budget: amount of work driver is allowed to do this pass, in packets
2557 *
2558 * This function will clean all queues associated with a q_vector.
2559 *
2560 * Returns the amount of work done
2561 **/
2562int i40e_napi_poll(struct napi_struct *napi, int budget)
2563{
2564 struct i40e_q_vector *q_vector =
2565 container_of(napi, struct i40e_q_vector, napi);
2566 struct i40e_vsi *vsi = q_vector->vsi;
2567 struct i40e_ring *ring;
2568 bool clean_complete = true;
2569 bool arm_wb = false;
2570 int budget_per_ring;
2571 int work_done = 0;
2572
2573 if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
2574 napi_complete(napi);
2575 return 0;
2576 }
2577
2578 /* Since the actual Tx work is minimal, we can give the Tx a larger
2579 * budget and be more aggressive about cleaning up the Tx descriptors.
2580 */
2581 i40e_for_each_ring(ring, q_vector->tx) {
2582 bool wd = ring->xsk_umem ?
2583 i40e_clean_xdp_tx_irq(vsi, ring) :
2584 i40e_clean_tx_irq(vsi, ring, budget);
2585
2586 if (!wd) {
2587 clean_complete = false;
2588 continue;
2589 }
2590 arm_wb |= ring->arm_wb;
2591 ring->arm_wb = false;
2592 }
2593
2594 /* Handle case where we are called by netpoll with a budget of 0 */
2595 if (budget <= 0)
2596 goto tx_only;
2597
2598 /* normally we have 1 Rx ring per q_vector */
2599 if (unlikely(q_vector->num_ringpairs > 1))
2600 /* We attempt to distribute budget to each Rx queue fairly, but
2601 * don't allow the budget to go below 1 because that would exit
2602 * polling early.
2603 */
2604 budget_per_ring = max_t(int, budget / q_vector->num_ringpairs, 1);
2605 else
2606 /* Max of 1 Rx ring in this q_vector so give it the budget */
2607 budget_per_ring = budget;
2608
2609 i40e_for_each_ring(ring, q_vector->rx) {
2610 int cleaned = ring->xsk_umem ?
2611 i40e_clean_rx_irq_zc(ring, budget_per_ring) :
2612 i40e_clean_rx_irq(ring, budget_per_ring);
2613
2614 work_done += cleaned;
2615 /* if we clean as many as budgeted, we must not be done */
2616 if (cleaned >= budget_per_ring)
2617 clean_complete = false;
2618 }
2619
2620 /* If work not completed, return budget and polling will return */
2621 if (!clean_complete) {
2622 int cpu_id = smp_processor_id();
2623
2624 /* It is possible that the interrupt affinity has changed but,
2625 * if the cpu is pegged at 100%, polling will never exit while
2626 * traffic continues and the interrupt will be stuck on this
2627 * cpu. We check to make sure affinity is correct before we
2628 * continue to poll, otherwise we must stop polling so the
2629 * interrupt can move to the correct cpu.
2630 */
2631 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
2632 /* Tell napi that we are done polling */
2633 napi_complete_done(napi, work_done);
2634
2635 /* Force an interrupt */
2636 i40e_force_wb(vsi, q_vector);
2637
2638 /* Return budget-1 so that polling stops */
2639 return budget - 1;
2640 }
2641tx_only:
2642 if (arm_wb) {
2643 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2644 i40e_enable_wb_on_itr(vsi, q_vector);
2645 }
2646 return budget;
2647 }
2648
2649 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
2650 q_vector->arm_wb_state = false;
2651
2652 /* Exit the polling mode, but don't re-enable interrupts if stack might
2653 * poll us due to busy-polling
2654 */
2655 if (likely(napi_complete_done(napi, work_done)))
2656 i40e_update_enable_itr(vsi, q_vector);
2657
2658 return min(work_done, budget - 1);
2659}
2660
2661/**
2662 * i40e_atr - Add a Flow Director ATR filter
2663 * @tx_ring: ring to add programming descriptor to
2664 * @skb: send buffer
2665 * @tx_flags: send tx flags
2666 **/
2667static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2668 u32 tx_flags)
2669{
2670 struct i40e_filter_program_desc *fdir_desc;
2671 struct i40e_pf *pf = tx_ring->vsi->back;
2672 union {
2673 unsigned char *network;
2674 struct iphdr *ipv4;
2675 struct ipv6hdr *ipv6;
2676 } hdr;
2677 struct tcphdr *th;
2678 unsigned int hlen;
2679 u32 flex_ptype, dtype_cmd;
2680 int l4_proto;
2681 u16 i;
2682
2683 /* make sure ATR is enabled */
2684 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2685 return;
2686
2687 if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2688 return;
2689
2690 /* if sampling is disabled do nothing */
2691 if (!tx_ring->atr_sample_rate)
2692 return;
2693
2694 /* Currently only IPv4/IPv6 with TCP is supported */
2695 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2696 return;
2697
2698 /* snag network header to get L4 type and address */
2699 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2700 skb_inner_network_header(skb) : skb_network_header(skb);
2701
2702 /* Note: tx_flags gets modified to reflect inner protocols in
2703 * tx_enable_csum function if encap is enabled.
2704 */
2705 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2706 /* access ihl as u8 to avoid unaligned access on ia64 */
2707 hlen = (hdr.network[0] & 0x0F) << 2;
2708 l4_proto = hdr.ipv4->protocol;
2709 } else {
2710 /* find the start of the innermost ipv6 header */
2711 unsigned int inner_hlen = hdr.network - skb->data;
2712 unsigned int h_offset = inner_hlen;
2713
2714 /* this function updates h_offset to the end of the header */
2715 l4_proto =
2716 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL);
2717 /* hlen will contain our best estimate of the tcp header */
2718 hlen = h_offset - inner_hlen;
2719 }
2720
2721 if (l4_proto != IPPROTO_TCP)
2722 return;
2723
2724 th = (struct tcphdr *)(hdr.network + hlen);
2725
2726 /* Due to lack of space, no more new filters can be programmed */
2727 if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2728 return;
2729 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) {
2730 /* HW ATR eviction will take care of removing filters on FIN
2731 * and RST packets.
2732 */
2733 if (th->fin || th->rst)
2734 return;
2735 }
2736
2737 tx_ring->atr_count++;
2738
2739 /* sample on all syn/fin/rst packets or once every atr sample rate */
2740 if (!th->fin &&
2741 !th->syn &&
2742 !th->rst &&
2743 (tx_ring->atr_count < tx_ring->atr_sample_rate))
2744 return;
2745
2746 tx_ring->atr_count = 0;
2747
2748 /* grab the next descriptor */
2749 i = tx_ring->next_to_use;
2750 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2751
2752 i++;
2753 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2754
2755 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2756 I40E_TXD_FLTR_QW0_QINDEX_MASK;
2757 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2758 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2759 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2760 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2761 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2762
2763 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2764
2765 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2766
2767 dtype_cmd |= (th->fin || th->rst) ?
2768 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2769 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2770 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2771 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2772
2773 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2774 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2775
2776 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2777 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2778
2779 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2780 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2781 dtype_cmd |=
2782 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2783 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2784 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2785 else
2786 dtype_cmd |=
2787 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2788 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2789 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2790
2791 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED)
2792 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2793
2794 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2795 fdir_desc->rsvd = cpu_to_le32(0);
2796 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2797 fdir_desc->fd_id = cpu_to_le32(0);
2798}
2799
2800/**
2801 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2802 * @skb: send buffer
2803 * @tx_ring: ring to send buffer on
2804 * @flags: the tx flags to be set
2805 *
2806 * Checks the skb and set up correspondingly several generic transmit flags
2807 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2808 *
2809 * Returns error code indicate the frame should be dropped upon error and the
2810 * otherwise returns 0 to indicate the flags has been set properly.
2811 **/
2812static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2813 struct i40e_ring *tx_ring,
2814 u32 *flags)
2815{
2816 __be16 protocol = skb->protocol;
2817 u32 tx_flags = 0;
2818
2819 if (protocol == htons(ETH_P_8021Q) &&
2820 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2821 /* When HW VLAN acceleration is turned off by the user the
2822 * stack sets the protocol to 8021q so that the driver
2823 * can take any steps required to support the SW only
2824 * VLAN handling. In our case the driver doesn't need
2825 * to take any further steps so just set the protocol
2826 * to the encapsulated ethertype.
2827 */
2828 skb->protocol = vlan_get_protocol(skb);
2829 goto out;
2830 }
2831
2832 /* if we have a HW VLAN tag being added, default to the HW one */
2833 if (skb_vlan_tag_present(skb)) {
2834 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2835 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2836 /* else if it is a SW VLAN, check the next protocol and store the tag */
2837 } else if (protocol == htons(ETH_P_8021Q)) {
2838 struct vlan_hdr *vhdr, _vhdr;
2839
2840 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2841 if (!vhdr)
2842 return -EINVAL;
2843
2844 protocol = vhdr->h_vlan_encapsulated_proto;
2845 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2846 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2847 }
2848
2849 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2850 goto out;
2851
2852 /* Insert 802.1p priority into VLAN header */
2853 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2854 (skb->priority != TC_PRIO_CONTROL)) {
2855 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2856 tx_flags |= (skb->priority & 0x7) <<
2857 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2858 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2859 struct vlan_ethhdr *vhdr;
2860 int rc;
2861
2862 rc = skb_cow_head(skb, 0);
2863 if (rc < 0)
2864 return rc;
2865 vhdr = (struct vlan_ethhdr *)skb->data;
2866 vhdr->h_vlan_TCI = htons(tx_flags >>
2867 I40E_TX_FLAGS_VLAN_SHIFT);
2868 } else {
2869 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2870 }
2871 }
2872
2873out:
2874 *flags = tx_flags;
2875 return 0;
2876}
2877
2878/**
2879 * i40e_tso - set up the tso context descriptor
2880 * @first: pointer to first Tx buffer for xmit
2881 * @hdr_len: ptr to the size of the packet header
2882 * @cd_type_cmd_tso_mss: Quad Word 1
2883 *
2884 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2885 **/
2886static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
2887 u64 *cd_type_cmd_tso_mss)
2888{
2889 struct sk_buff *skb = first->skb;
2890 u64 cd_cmd, cd_tso_len, cd_mss;
2891 union {
2892 struct iphdr *v4;
2893 struct ipv6hdr *v6;
2894 unsigned char *hdr;
2895 } ip;
2896 union {
2897 struct tcphdr *tcp;
2898 struct udphdr *udp;
2899 unsigned char *hdr;
2900 } l4;
2901 u32 paylen, l4_offset;
2902 u16 gso_segs, gso_size;
2903 int err;
2904
2905 if (skb->ip_summed != CHECKSUM_PARTIAL)
2906 return 0;
2907
2908 if (!skb_is_gso(skb))
2909 return 0;
2910
2911 err = skb_cow_head(skb, 0);
2912 if (err < 0)
2913 return err;
2914
2915 ip.hdr = skb_network_header(skb);
2916 l4.hdr = skb_transport_header(skb);
2917
2918 /* initialize outer IP header fields */
2919 if (ip.v4->version == 4) {
2920 ip.v4->tot_len = 0;
2921 ip.v4->check = 0;
2922 } else {
2923 ip.v6->payload_len = 0;
2924 }
2925
2926 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
2927 SKB_GSO_GRE_CSUM |
2928 SKB_GSO_IPXIP4 |
2929 SKB_GSO_IPXIP6 |
2930 SKB_GSO_UDP_TUNNEL |
2931 SKB_GSO_UDP_TUNNEL_CSUM)) {
2932 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
2933 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
2934 l4.udp->len = 0;
2935
2936 /* determine offset of outer transport header */
2937 l4_offset = l4.hdr - skb->data;
2938
2939 /* remove payload length from outer checksum */
2940 paylen = skb->len - l4_offset;
2941 csum_replace_by_diff(&l4.udp->check,
2942 (__force __wsum)htonl(paylen));
2943 }
2944
2945 /* reset pointers to inner headers */
2946 ip.hdr = skb_inner_network_header(skb);
2947 l4.hdr = skb_inner_transport_header(skb);
2948
2949 /* initialize inner IP header fields */
2950 if (ip.v4->version == 4) {
2951 ip.v4->tot_len = 0;
2952 ip.v4->check = 0;
2953 } else {
2954 ip.v6->payload_len = 0;
2955 }
2956 }
2957
2958 /* determine offset of inner transport header */
2959 l4_offset = l4.hdr - skb->data;
2960
2961 /* remove payload length from inner checksum */
2962 paylen = skb->len - l4_offset;
2963
2964 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
2965 csum_replace_by_diff(&l4.udp->check, (__force __wsum)htonl(paylen));
2966 /* compute length of segmentation header */
2967 *hdr_len = sizeof(*l4.udp) + l4_offset;
2968 } else {
2969 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
2970 /* compute length of segmentation header */
2971 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
2972 }
2973
2974 /* pull values out of skb_shinfo */
2975 gso_size = skb_shinfo(skb)->gso_size;
2976 gso_segs = skb_shinfo(skb)->gso_segs;
2977
2978 /* update GSO size and bytecount with header size */
2979 first->gso_segs = gso_segs;
2980 first->bytecount += (first->gso_segs - 1) * *hdr_len;
2981
2982 /* find the field values */
2983 cd_cmd = I40E_TX_CTX_DESC_TSO;
2984 cd_tso_len = skb->len - *hdr_len;
2985 cd_mss = gso_size;
2986 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2987 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2988 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2989 return 1;
2990}
2991
2992/**
2993 * i40e_tsyn - set up the tsyn context descriptor
2994 * @tx_ring: ptr to the ring to send
2995 * @skb: ptr to the skb we're sending
2996 * @tx_flags: the collected send information
2997 * @cd_type_cmd_tso_mss: Quad Word 1
2998 *
2999 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
3000 **/
3001static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
3002 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
3003{
3004 struct i40e_pf *pf;
3005
3006 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
3007 return 0;
3008
3009 /* Tx timestamps cannot be sampled when doing TSO */
3010 if (tx_flags & I40E_TX_FLAGS_TSO)
3011 return 0;
3012
3013 /* only timestamp the outbound packet if the user has requested it and
3014 * we are not already transmitting a packet to be timestamped
3015 */
3016 pf = i40e_netdev_to_pf(tx_ring->netdev);
3017 if (!(pf->flags & I40E_FLAG_PTP))
3018 return 0;
3019
3020 if (pf->ptp_tx &&
3021 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) {
3022 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3023 pf->ptp_tx_start = jiffies;
3024 pf->ptp_tx_skb = skb_get(skb);
3025 } else {
3026 pf->tx_hwtstamp_skipped++;
3027 return 0;
3028 }
3029
3030 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
3031 I40E_TXD_CTX_QW1_CMD_SHIFT;
3032
3033 return 1;
3034}
3035
3036/**
3037 * i40e_tx_enable_csum - Enable Tx checksum offloads
3038 * @skb: send buffer
3039 * @tx_flags: pointer to Tx flags currently set
3040 * @td_cmd: Tx descriptor command bits to set
3041 * @td_offset: Tx descriptor header offsets to set
3042 * @tx_ring: Tx descriptor ring
3043 * @cd_tunneling: ptr to context desc bits
3044 **/
3045static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
3046 u32 *td_cmd, u32 *td_offset,
3047 struct i40e_ring *tx_ring,
3048 u32 *cd_tunneling)
3049{
3050 union {
3051 struct iphdr *v4;
3052 struct ipv6hdr *v6;
3053 unsigned char *hdr;
3054 } ip;
3055 union {
3056 struct tcphdr *tcp;
3057 struct udphdr *udp;
3058 unsigned char *hdr;
3059 } l4;
3060 unsigned char *exthdr;
3061 u32 offset, cmd = 0;
3062 __be16 frag_off;
3063 u8 l4_proto = 0;
3064
3065 if (skb->ip_summed != CHECKSUM_PARTIAL)
3066 return 0;
3067
3068 ip.hdr = skb_network_header(skb);
3069 l4.hdr = skb_transport_header(skb);
3070
3071 /* compute outer L2 header size */
3072 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
3073
3074 if (skb->encapsulation) {
3075 u32 tunnel = 0;
3076 /* define outer network header type */
3077 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3078 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3079 I40E_TX_CTX_EXT_IP_IPV4 :
3080 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
3081
3082 l4_proto = ip.v4->protocol;
3083 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3084 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
3085
3086 exthdr = ip.hdr + sizeof(*ip.v6);
3087 l4_proto = ip.v6->nexthdr;
3088 if (l4.hdr != exthdr)
3089 ipv6_skip_exthdr(skb, exthdr - skb->data,
3090 &l4_proto, &frag_off);
3091 }
3092
3093 /* define outer transport */
3094 switch (l4_proto) {
3095 case IPPROTO_UDP:
3096 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
3097 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3098 break;
3099 case IPPROTO_GRE:
3100 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
3101 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3102 break;
3103 case IPPROTO_IPIP:
3104 case IPPROTO_IPV6:
3105 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3106 l4.hdr = skb_inner_network_header(skb);
3107 break;
3108 default:
3109 if (*tx_flags & I40E_TX_FLAGS_TSO)
3110 return -1;
3111
3112 skb_checksum_help(skb);
3113 return 0;
3114 }
3115
3116 /* compute outer L3 header size */
3117 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
3118 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
3119
3120 /* switch IP header pointer from outer to inner header */
3121 ip.hdr = skb_inner_network_header(skb);
3122
3123 /* compute tunnel header size */
3124 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
3125 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
3126
3127 /* indicate if we need to offload outer UDP header */
3128 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
3129 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3130 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
3131 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
3132
3133 /* record tunnel offload values */
3134 *cd_tunneling |= tunnel;
3135
3136 /* switch L4 header pointer from outer to inner */
3137 l4.hdr = skb_inner_transport_header(skb);
3138 l4_proto = 0;
3139
3140 /* reset type as we transition from outer to inner headers */
3141 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
3142 if (ip.v4->version == 4)
3143 *tx_flags |= I40E_TX_FLAGS_IPV4;
3144 if (ip.v6->version == 6)
3145 *tx_flags |= I40E_TX_FLAGS_IPV6;
3146 }
3147
3148 /* Enable IP checksum offloads */
3149 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3150 l4_proto = ip.v4->protocol;
3151 /* the stack computes the IP header already, the only time we
3152 * need the hardware to recompute it is in the case of TSO.
3153 */
3154 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3155 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
3156 I40E_TX_DESC_CMD_IIPT_IPV4;
3157 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3158 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
3159
3160 exthdr = ip.hdr + sizeof(*ip.v6);
3161 l4_proto = ip.v6->nexthdr;
3162 if (l4.hdr != exthdr)
3163 ipv6_skip_exthdr(skb, exthdr - skb->data,
3164 &l4_proto, &frag_off);
3165 }
3166
3167 /* compute inner L3 header size */
3168 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
3169
3170 /* Enable L4 checksum offloads */
3171 switch (l4_proto) {
3172 case IPPROTO_TCP:
3173 /* enable checksum offloads */
3174 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
3175 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3176 break;
3177 case IPPROTO_SCTP:
3178 /* enable SCTP checksum offload */
3179 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
3180 offset |= (sizeof(struct sctphdr) >> 2) <<
3181 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3182 break;
3183 case IPPROTO_UDP:
3184 /* enable UDP checksum offload */
3185 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
3186 offset |= (sizeof(struct udphdr) >> 2) <<
3187 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3188 break;
3189 default:
3190 if (*tx_flags & I40E_TX_FLAGS_TSO)
3191 return -1;
3192 skb_checksum_help(skb);
3193 return 0;
3194 }
3195
3196 *td_cmd |= cmd;
3197 *td_offset |= offset;
3198
3199 return 1;
3200}
3201
3202/**
3203 * i40e_create_tx_ctx Build the Tx context descriptor
3204 * @tx_ring: ring to create the descriptor on
3205 * @cd_type_cmd_tso_mss: Quad Word 1
3206 * @cd_tunneling: Quad Word 0 - bits 0-31
3207 * @cd_l2tag2: Quad Word 0 - bits 32-63
3208 **/
3209static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
3210 const u64 cd_type_cmd_tso_mss,
3211 const u32 cd_tunneling, const u32 cd_l2tag2)
3212{
3213 struct i40e_tx_context_desc *context_desc;
3214 int i = tx_ring->next_to_use;
3215
3216 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
3217 !cd_tunneling && !cd_l2tag2)
3218 return;
3219
3220 /* grab the next descriptor */
3221 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
3222
3223 i++;
3224 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3225
3226 /* cpu_to_le32 and assign to struct fields */
3227 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
3228 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3229 context_desc->rsvd = cpu_to_le16(0);
3230 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
3231}
3232
3233/**
3234 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
3235 * @tx_ring: the ring to be checked
3236 * @size: the size buffer we want to assure is available
3237 *
3238 * Returns -EBUSY if a stop is needed, else 0
3239 **/
3240int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
3241{
3242 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
3243 /* Memory barrier before checking head and tail */
3244 smp_mb();
3245
3246 /* Check again in a case another CPU has just made room available. */
3247 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
3248 return -EBUSY;
3249
3250 /* A reprieve! - use start_queue because it doesn't call schedule */
3251 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
3252 ++tx_ring->tx_stats.restart_queue;
3253 return 0;
3254}
3255
3256/**
3257 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
3258 * @skb: send buffer
3259 *
3260 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
3261 * and so we need to figure out the cases where we need to linearize the skb.
3262 *
3263 * For TSO we need to count the TSO header and segment payload separately.
3264 * As such we need to check cases where we have 7 fragments or more as we
3265 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
3266 * the segment payload in the first descriptor, and another 7 for the
3267 * fragments.
3268 **/
3269bool __i40e_chk_linearize(struct sk_buff *skb)
3270{
3271 const skb_frag_t *frag, *stale;
3272 int nr_frags, sum;
3273
3274 /* no need to check if number of frags is less than 7 */
3275 nr_frags = skb_shinfo(skb)->nr_frags;
3276 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
3277 return false;
3278
3279 /* We need to walk through the list and validate that each group
3280 * of 6 fragments totals at least gso_size.
3281 */
3282 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
3283 frag = &skb_shinfo(skb)->frags[0];
3284
3285 /* Initialize size to the negative value of gso_size minus 1. We
3286 * use this as the worst case scenerio in which the frag ahead
3287 * of us only provides one byte which is why we are limited to 6
3288 * descriptors for a single transmit as the header and previous
3289 * fragment are already consuming 2 descriptors.
3290 */
3291 sum = 1 - skb_shinfo(skb)->gso_size;
3292
3293 /* Add size of frags 0 through 4 to create our initial sum */
3294 sum += skb_frag_size(frag++);
3295 sum += skb_frag_size(frag++);
3296 sum += skb_frag_size(frag++);
3297 sum += skb_frag_size(frag++);
3298 sum += skb_frag_size(frag++);
3299
3300 /* Walk through fragments adding latest fragment, testing it, and
3301 * then removing stale fragments from the sum.
3302 */
3303 for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
3304 int stale_size = skb_frag_size(stale);
3305
3306 sum += skb_frag_size(frag++);
3307
3308 /* The stale fragment may present us with a smaller
3309 * descriptor than the actual fragment size. To account
3310 * for that we need to remove all the data on the front and
3311 * figure out what the remainder would be in the last
3312 * descriptor associated with the fragment.
3313 */
3314 if (stale_size > I40E_MAX_DATA_PER_TXD) {
3315 int align_pad = -(skb_frag_off(stale)) &
3316 (I40E_MAX_READ_REQ_SIZE - 1);
3317
3318 sum -= align_pad;
3319 stale_size -= align_pad;
3320
3321 do {
3322 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3323 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3324 } while (stale_size > I40E_MAX_DATA_PER_TXD);
3325 }
3326
3327 /* if sum is negative we failed to make sufficient progress */
3328 if (sum < 0)
3329 return true;
3330
3331 if (!nr_frags--)
3332 break;
3333
3334 sum -= stale_size;
3335 }
3336
3337 return false;
3338}
3339
3340/**
3341 * i40e_tx_map - Build the Tx descriptor
3342 * @tx_ring: ring to send buffer on
3343 * @skb: send buffer
3344 * @first: first buffer info buffer to use
3345 * @tx_flags: collected send information
3346 * @hdr_len: size of the packet header
3347 * @td_cmd: the command field in the descriptor
3348 * @td_offset: offset for checksum or crc
3349 *
3350 * Returns 0 on success, -1 on failure to DMA
3351 **/
3352static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
3353 struct i40e_tx_buffer *first, u32 tx_flags,
3354 const u8 hdr_len, u32 td_cmd, u32 td_offset)
3355{
3356 unsigned int data_len = skb->data_len;
3357 unsigned int size = skb_headlen(skb);
3358 skb_frag_t *frag;
3359 struct i40e_tx_buffer *tx_bi;
3360 struct i40e_tx_desc *tx_desc;
3361 u16 i = tx_ring->next_to_use;
3362 u32 td_tag = 0;
3363 dma_addr_t dma;
3364 u16 desc_count = 1;
3365
3366 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
3367 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
3368 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
3369 I40E_TX_FLAGS_VLAN_SHIFT;
3370 }
3371
3372 first->tx_flags = tx_flags;
3373
3374 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
3375
3376 tx_desc = I40E_TX_DESC(tx_ring, i);
3377 tx_bi = first;
3378
3379 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
3380 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3381
3382 if (dma_mapping_error(tx_ring->dev, dma))
3383 goto dma_error;
3384
3385 /* record length, and DMA address */
3386 dma_unmap_len_set(tx_bi, len, size);
3387 dma_unmap_addr_set(tx_bi, dma, dma);
3388
3389 /* align size to end of page */
3390 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
3391 tx_desc->buffer_addr = cpu_to_le64(dma);
3392
3393 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
3394 tx_desc->cmd_type_offset_bsz =
3395 build_ctob(td_cmd, td_offset,
3396 max_data, td_tag);
3397
3398 tx_desc++;
3399 i++;
3400 desc_count++;
3401
3402 if (i == tx_ring->count) {
3403 tx_desc = I40E_TX_DESC(tx_ring, 0);
3404 i = 0;
3405 }
3406
3407 dma += max_data;
3408 size -= max_data;
3409
3410 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3411 tx_desc->buffer_addr = cpu_to_le64(dma);
3412 }
3413
3414 if (likely(!data_len))
3415 break;
3416
3417 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
3418 size, td_tag);
3419
3420 tx_desc++;
3421 i++;
3422 desc_count++;
3423
3424 if (i == tx_ring->count) {
3425 tx_desc = I40E_TX_DESC(tx_ring, 0);
3426 i = 0;
3427 }
3428
3429 size = skb_frag_size(frag);
3430 data_len -= size;
3431
3432 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
3433 DMA_TO_DEVICE);
3434
3435 tx_bi = &tx_ring->tx_bi[i];
3436 }
3437
3438 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
3439
3440 i++;
3441 if (i == tx_ring->count)
3442 i = 0;
3443
3444 tx_ring->next_to_use = i;
3445
3446 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
3447
3448 /* write last descriptor with EOP bit */
3449 td_cmd |= I40E_TX_DESC_CMD_EOP;
3450
3451 /* We OR these values together to check both against 4 (WB_STRIDE)
3452 * below. This is safe since we don't re-use desc_count afterwards.
3453 */
3454 desc_count |= ++tx_ring->packet_stride;
3455
3456 if (desc_count >= WB_STRIDE) {
3457 /* write last descriptor with RS bit set */
3458 td_cmd |= I40E_TX_DESC_CMD_RS;
3459 tx_ring->packet_stride = 0;
3460 }
3461
3462 tx_desc->cmd_type_offset_bsz =
3463 build_ctob(td_cmd, td_offset, size, td_tag);
3464
3465 skb_tx_timestamp(skb);
3466
3467 /* Force memory writes to complete before letting h/w know there
3468 * are new descriptors to fetch.
3469 *
3470 * We also use this memory barrier to make certain all of the
3471 * status bits have been updated before next_to_watch is written.
3472 */
3473 wmb();
3474
3475 /* set next_to_watch value indicating a packet is present */
3476 first->next_to_watch = tx_desc;
3477
3478 /* notify HW of packet */
3479 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
3480 writel(i, tx_ring->tail);
3481 }
3482
3483 return 0;
3484
3485dma_error:
3486 dev_info(tx_ring->dev, "TX DMA map failed\n");
3487
3488 /* clear dma mappings for failed tx_bi map */
3489 for (;;) {
3490 tx_bi = &tx_ring->tx_bi[i];
3491 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
3492 if (tx_bi == first)
3493 break;
3494 if (i == 0)
3495 i = tx_ring->count;
3496 i--;
3497 }
3498
3499 tx_ring->next_to_use = i;
3500
3501 return -1;
3502}
3503
3504/**
3505 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
3506 * @xdp: data to transmit
3507 * @xdp_ring: XDP Tx ring
3508 **/
3509static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
3510 struct i40e_ring *xdp_ring)
3511{
3512 u16 i = xdp_ring->next_to_use;
3513 struct i40e_tx_buffer *tx_bi;
3514 struct i40e_tx_desc *tx_desc;
3515 void *data = xdpf->data;
3516 u32 size = xdpf->len;
3517 dma_addr_t dma;
3518
3519 if (!unlikely(I40E_DESC_UNUSED(xdp_ring))) {
3520 xdp_ring->tx_stats.tx_busy++;
3521 return I40E_XDP_CONSUMED;
3522 }
3523 dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE);
3524 if (dma_mapping_error(xdp_ring->dev, dma))
3525 return I40E_XDP_CONSUMED;
3526
3527 tx_bi = &xdp_ring->tx_bi[i];
3528 tx_bi->bytecount = size;
3529 tx_bi->gso_segs = 1;
3530 tx_bi->xdpf = xdpf;
3531
3532 /* record length, and DMA address */
3533 dma_unmap_len_set(tx_bi, len, size);
3534 dma_unmap_addr_set(tx_bi, dma, dma);
3535
3536 tx_desc = I40E_TX_DESC(xdp_ring, i);
3537 tx_desc->buffer_addr = cpu_to_le64(dma);
3538 tx_desc->cmd_type_offset_bsz = build_ctob(I40E_TX_DESC_CMD_ICRC
3539 | I40E_TXD_CMD,
3540 0, size, 0);
3541
3542 /* Make certain all of the status bits have been updated
3543 * before next_to_watch is written.
3544 */
3545 smp_wmb();
3546
3547 xdp_ring->xdp_tx_active++;
3548 i++;
3549 if (i == xdp_ring->count)
3550 i = 0;
3551
3552 tx_bi->next_to_watch = tx_desc;
3553 xdp_ring->next_to_use = i;
3554
3555 return I40E_XDP_TX;
3556}
3557
3558/**
3559 * i40e_xmit_frame_ring - Sends buffer on Tx ring
3560 * @skb: send buffer
3561 * @tx_ring: ring to send buffer on
3562 *
3563 * Returns NETDEV_TX_OK if sent, else an error code
3564 **/
3565static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
3566 struct i40e_ring *tx_ring)
3567{
3568 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
3569 u32 cd_tunneling = 0, cd_l2tag2 = 0;
3570 struct i40e_tx_buffer *first;
3571 u32 td_offset = 0;
3572 u32 tx_flags = 0;
3573 __be16 protocol;
3574 u32 td_cmd = 0;
3575 u8 hdr_len = 0;
3576 int tso, count;
3577 int tsyn;
3578
3579 /* prefetch the data, we'll need it later */
3580 prefetch(skb->data);
3581
3582 i40e_trace(xmit_frame_ring, skb, tx_ring);
3583
3584 count = i40e_xmit_descriptor_count(skb);
3585 if (i40e_chk_linearize(skb, count)) {
3586 if (__skb_linearize(skb)) {
3587 dev_kfree_skb_any(skb);
3588 return NETDEV_TX_OK;
3589 }
3590 count = i40e_txd_use_count(skb->len);
3591 tx_ring->tx_stats.tx_linearize++;
3592 }
3593
3594 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
3595 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
3596 * + 4 desc gap to avoid the cache line where head is,
3597 * + 1 desc for context descriptor,
3598 * otherwise try next time
3599 */
3600 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
3601 tx_ring->tx_stats.tx_busy++;
3602 return NETDEV_TX_BUSY;
3603 }
3604
3605 /* record the location of the first descriptor for this packet */
3606 first = &tx_ring->tx_bi[tx_ring->next_to_use];
3607 first->skb = skb;
3608 first->bytecount = skb->len;
3609 first->gso_segs = 1;
3610
3611 /* prepare the xmit flags */
3612 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
3613 goto out_drop;
3614
3615 /* obtain protocol of skb */
3616 protocol = vlan_get_protocol(skb);
3617
3618 /* setup IPv4/IPv6 offloads */
3619 if (protocol == htons(ETH_P_IP))
3620 tx_flags |= I40E_TX_FLAGS_IPV4;
3621 else if (protocol == htons(ETH_P_IPV6))
3622 tx_flags |= I40E_TX_FLAGS_IPV6;
3623
3624 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
3625
3626 if (tso < 0)
3627 goto out_drop;
3628 else if (tso)
3629 tx_flags |= I40E_TX_FLAGS_TSO;
3630
3631 /* Always offload the checksum, since it's in the data descriptor */
3632 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
3633 tx_ring, &cd_tunneling);
3634 if (tso < 0)
3635 goto out_drop;
3636
3637 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
3638
3639 if (tsyn)
3640 tx_flags |= I40E_TX_FLAGS_TSYN;
3641
3642 /* always enable CRC insertion offload */
3643 td_cmd |= I40E_TX_DESC_CMD_ICRC;
3644
3645 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
3646 cd_tunneling, cd_l2tag2);
3647
3648 /* Add Flow Director ATR if it's enabled.
3649 *
3650 * NOTE: this must always be directly before the data descriptor.
3651 */
3652 i40e_atr(tx_ring, skb, tx_flags);
3653
3654 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
3655 td_cmd, td_offset))
3656 goto cleanup_tx_tstamp;
3657
3658 return NETDEV_TX_OK;
3659
3660out_drop:
3661 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
3662 dev_kfree_skb_any(first->skb);
3663 first->skb = NULL;
3664cleanup_tx_tstamp:
3665 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) {
3666 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev);
3667
3668 dev_kfree_skb_any(pf->ptp_tx_skb);
3669 pf->ptp_tx_skb = NULL;
3670 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
3671 }
3672
3673 return NETDEV_TX_OK;
3674}
3675
3676/**
3677 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
3678 * @skb: send buffer
3679 * @netdev: network interface device structure
3680 *
3681 * Returns NETDEV_TX_OK if sent, else an error code
3682 **/
3683netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3684{
3685 struct i40e_netdev_priv *np = netdev_priv(netdev);
3686 struct i40e_vsi *vsi = np->vsi;
3687 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
3688
3689 /* hardware can't handle really short frames, hardware padding works
3690 * beyond this point
3691 */
3692 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
3693 return NETDEV_TX_OK;
3694
3695 return i40e_xmit_frame_ring(skb, tx_ring);
3696}
3697
3698/**
3699 * i40e_xdp_xmit - Implements ndo_xdp_xmit
3700 * @dev: netdev
3701 * @xdp: XDP buffer
3702 *
3703 * Returns number of frames successfully sent. Frames that fail are
3704 * free'ed via XDP return API.
3705 *
3706 * For error cases, a negative errno code is returned and no-frames
3707 * are transmitted (caller must handle freeing frames).
3708 **/
3709int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
3710 u32 flags)
3711{
3712 struct i40e_netdev_priv *np = netdev_priv(dev);
3713 unsigned int queue_index = smp_processor_id();
3714 struct i40e_vsi *vsi = np->vsi;
3715 struct i40e_pf *pf = vsi->back;
3716 struct i40e_ring *xdp_ring;
3717 int drops = 0;
3718 int i;
3719
3720 if (test_bit(__I40E_VSI_DOWN, vsi->state))
3721 return -ENETDOWN;
3722
3723 if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs ||
3724 test_bit(__I40E_CONFIG_BUSY, pf->state))
3725 return -ENXIO;
3726
3727 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3728 return -EINVAL;
3729
3730 xdp_ring = vsi->xdp_rings[queue_index];
3731
3732 for (i = 0; i < n; i++) {
3733 struct xdp_frame *xdpf = frames[i];
3734 int err;
3735
3736 err = i40e_xmit_xdp_ring(xdpf, xdp_ring);
3737 if (err != I40E_XDP_TX) {
3738 xdp_return_frame_rx_napi(xdpf);
3739 drops++;
3740 }
3741 }
3742
3743 if (unlikely(flags & XDP_XMIT_FLUSH))
3744 i40e_xdp_ring_update_tail(xdp_ring);
3745
3746 return n - drops;
3747}