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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
11 * small packets.
12 *
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 *
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 *
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
21 *
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23 */
24
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/string.h>
28#include <linux/pm_runtime.h>
29#include <linux/ptrace.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/slab.h>
33#include <linux/interrupt.h>
34#include <linux/delay.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
38#include <linux/in.h>
39#include <linux/ip.h>
40#include <net/ip.h>
41#include <net/page_pool/helpers.h>
42#include <net/selftests.h>
43#include <net/tso.h>
44#include <linux/tcp.h>
45#include <linux/udp.h>
46#include <linux/icmp.h>
47#include <linux/spinlock.h>
48#include <linux/workqueue.h>
49#include <linux/bitops.h>
50#include <linux/io.h>
51#include <linux/irq.h>
52#include <linux/clk.h>
53#include <linux/crc32.h>
54#include <linux/platform_device.h>
55#include <linux/property.h>
56#include <linux/mdio.h>
57#include <linux/phy.h>
58#include <linux/fec.h>
59#include <linux/of.h>
60#include <linux/of_mdio.h>
61#include <linux/of_net.h>
62#include <linux/regulator/consumer.h>
63#include <linux/if_vlan.h>
64#include <linux/pinctrl/consumer.h>
65#include <linux/gpio/consumer.h>
66#include <linux/prefetch.h>
67#include <linux/mfd/syscon.h>
68#include <linux/regmap.h>
69#include <soc/imx/cpuidle.h>
70#include <linux/filter.h>
71#include <linux/bpf.h>
72#include <linux/bpf_trace.h>
73
74#include <asm/cacheflush.h>
75
76#include "fec.h"
77
78static void set_multicast_list(struct net_device *ndev);
79static void fec_enet_itr_coal_set(struct net_device *ndev);
80static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
81 int cpu, struct xdp_buff *xdp,
82 u32 dma_sync_len);
83
84#define DRIVER_NAME "fec"
85
86static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
87
88/* Pause frame feild and FIFO threshold */
89#define FEC_ENET_FCE (1 << 5)
90#define FEC_ENET_RSEM_V 0x84
91#define FEC_ENET_RSFL_V 16
92#define FEC_ENET_RAEM_V 0x8
93#define FEC_ENET_RAFL_V 0x8
94#define FEC_ENET_OPD_V 0xFFF0
95#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
96
97#define FEC_ENET_XDP_PASS 0
98#define FEC_ENET_XDP_CONSUMED BIT(0)
99#define FEC_ENET_XDP_TX BIT(1)
100#define FEC_ENET_XDP_REDIR BIT(2)
101
102struct fec_devinfo {
103 u32 quirks;
104};
105
106static const struct fec_devinfo fec_imx25_info = {
107 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
108 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45,
109};
110
111static const struct fec_devinfo fec_imx27_info = {
112 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG |
113 FEC_QUIRK_HAS_MDIO_C45,
114};
115
116static const struct fec_devinfo fec_imx28_info = {
117 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
118 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
119 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII |
120 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45,
121};
122
123static const struct fec_devinfo fec_imx6q_info = {
124 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
125 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
126 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
127 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII |
128 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45,
129};
130
131static const struct fec_devinfo fec_mvf600_info = {
132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC |
133 FEC_QUIRK_HAS_MDIO_C45,
134};
135
136static const struct fec_devinfo fec_imx6x_info = {
137 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
138 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
139 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
140 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
141 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
142 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
143 FEC_QUIRK_HAS_MDIO_C45,
144};
145
146static const struct fec_devinfo fec_imx6ul_info = {
147 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
148 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
149 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
150 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
151 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII |
152 FEC_QUIRK_HAS_MDIO_C45,
153};
154
155static const struct fec_devinfo fec_imx8mq_info = {
156 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
157 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
158 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
159 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
160 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
161 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
162 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 |
163 FEC_QUIRK_HAS_MDIO_C45,
164};
165
166static const struct fec_devinfo fec_imx8qm_info = {
167 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
168 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
169 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
170 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
171 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
172 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
173 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45,
174};
175
176static const struct fec_devinfo fec_s32v234_info = {
177 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
178 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
179 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
180 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
181 FEC_QUIRK_HAS_MDIO_C45,
182};
183
184static struct platform_device_id fec_devtype[] = {
185 {
186 /* keep it for coldfire */
187 .name = DRIVER_NAME,
188 .driver_data = 0,
189 }, {
190 /* sentinel */
191 }
192};
193MODULE_DEVICE_TABLE(platform, fec_devtype);
194
195static const struct of_device_id fec_dt_ids[] = {
196 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, },
197 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, },
198 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, },
199 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, },
200 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, },
201 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6x_info, },
202 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, },
203 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, },
204 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, },
205 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, },
206 { /* sentinel */ }
207};
208MODULE_DEVICE_TABLE(of, fec_dt_ids);
209
210static unsigned char macaddr[ETH_ALEN];
211module_param_array(macaddr, byte, NULL, 0);
212MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
213
214#if defined(CONFIG_M5272)
215/*
216 * Some hardware gets it MAC address out of local flash memory.
217 * if this is non-zero then assume it is the address to get MAC from.
218 */
219#if defined(CONFIG_NETtel)
220#define FEC_FLASHMAC 0xf0006006
221#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
222#define FEC_FLASHMAC 0xf0006000
223#elif defined(CONFIG_CANCam)
224#define FEC_FLASHMAC 0xf0020000
225#elif defined (CONFIG_M5272C3)
226#define FEC_FLASHMAC (0xffe04000 + 4)
227#elif defined(CONFIG_MOD5272)
228#define FEC_FLASHMAC 0xffc0406b
229#else
230#define FEC_FLASHMAC 0
231#endif
232#endif /* CONFIG_M5272 */
233
234/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
235 *
236 * 2048 byte skbufs are allocated. However, alignment requirements
237 * varies between FEC variants. Worst case is 64, so round down by 64.
238 */
239#define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
240#define PKT_MINBUF_SIZE 64
241
242/* FEC receive acceleration */
243#define FEC_RACC_IPDIS (1 << 1)
244#define FEC_RACC_PRODIS (1 << 2)
245#define FEC_RACC_SHIFT16 BIT(7)
246#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
247
248/* MIB Control Register */
249#define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
250
251/*
252 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
253 * size bits. Other FEC hardware does not, so we need to take that into
254 * account when setting it.
255 */
256#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
257 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
258 defined(CONFIG_ARM64)
259#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
260#else
261#define OPT_FRAME_SIZE 0
262#endif
263
264/* FEC MII MMFR bits definition */
265#define FEC_MMFR_ST (1 << 30)
266#define FEC_MMFR_ST_C45 (0)
267#define FEC_MMFR_OP_READ (2 << 28)
268#define FEC_MMFR_OP_READ_C45 (3 << 28)
269#define FEC_MMFR_OP_WRITE (1 << 28)
270#define FEC_MMFR_OP_ADDR_WRITE (0)
271#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
272#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
273#define FEC_MMFR_TA (2 << 16)
274#define FEC_MMFR_DATA(v) (v & 0xffff)
275/* FEC ECR bits definition */
276#define FEC_ECR_MAGICEN (1 << 2)
277#define FEC_ECR_SLEEP (1 << 3)
278
279#define FEC_MII_TIMEOUT 30000 /* us */
280
281/* Transmitter timeout */
282#define TX_TIMEOUT (2 * HZ)
283
284#define FEC_PAUSE_FLAG_AUTONEG 0x1
285#define FEC_PAUSE_FLAG_ENABLE 0x2
286#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
287#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
288#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
289
290/* Max number of allowed TCP segments for software TSO */
291#define FEC_MAX_TSO_SEGS 100
292#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
293
294#define IS_TSO_HEADER(txq, addr) \
295 ((addr >= txq->tso_hdrs_dma) && \
296 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
297
298static int mii_cnt;
299
300static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
301 struct bufdesc_prop *bd)
302{
303 return (bdp >= bd->last) ? bd->base
304 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
305}
306
307static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
308 struct bufdesc_prop *bd)
309{
310 return (bdp <= bd->base) ? bd->last
311 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
312}
313
314static int fec_enet_get_bd_index(struct bufdesc *bdp,
315 struct bufdesc_prop *bd)
316{
317 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
318}
319
320static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
321{
322 int entries;
323
324 entries = (((const char *)txq->dirty_tx -
325 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
326
327 return entries >= 0 ? entries : entries + txq->bd.ring_size;
328}
329
330static void swap_buffer(void *bufaddr, int len)
331{
332 int i;
333 unsigned int *buf = bufaddr;
334
335 for (i = 0; i < len; i += 4, buf++)
336 swab32s(buf);
337}
338
339static void fec_dump(struct net_device *ndev)
340{
341 struct fec_enet_private *fep = netdev_priv(ndev);
342 struct bufdesc *bdp;
343 struct fec_enet_priv_tx_q *txq;
344 int index = 0;
345
346 netdev_info(ndev, "TX ring dump\n");
347 pr_info("Nr SC addr len SKB\n");
348
349 txq = fep->tx_queue[0];
350 bdp = txq->bd.base;
351
352 do {
353 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
354 index,
355 bdp == txq->bd.cur ? 'S' : ' ',
356 bdp == txq->dirty_tx ? 'H' : ' ',
357 fec16_to_cpu(bdp->cbd_sc),
358 fec32_to_cpu(bdp->cbd_bufaddr),
359 fec16_to_cpu(bdp->cbd_datlen),
360 txq->tx_buf[index].buf_p);
361 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
362 index++;
363 } while (bdp != txq->bd.base);
364}
365
366/*
367 * Coldfire does not support DMA coherent allocations, and has historically used
368 * a band-aid with a manual flush in fec_enet_rx_queue.
369 */
370#if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA)
371static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
372 gfp_t gfp)
373{
374 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp);
375}
376
377static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr,
378 dma_addr_t handle)
379{
380 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL);
381}
382#else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */
383static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
384 gfp_t gfp)
385{
386 return dma_alloc_coherent(dev, size, handle, gfp);
387}
388
389static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr,
390 dma_addr_t handle)
391{
392 dma_free_coherent(dev, size, cpu_addr, handle);
393}
394#endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */
395
396struct fec_dma_devres {
397 size_t size;
398 void *vaddr;
399 dma_addr_t dma_handle;
400};
401
402static void fec_dmam_release(struct device *dev, void *res)
403{
404 struct fec_dma_devres *this = res;
405
406 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle);
407}
408
409static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle,
410 gfp_t gfp)
411{
412 struct fec_dma_devres *dr;
413 void *vaddr;
414
415 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp);
416 if (!dr)
417 return NULL;
418 vaddr = fec_dma_alloc(dev, size, handle, gfp);
419 if (!vaddr) {
420 devres_free(dr);
421 return NULL;
422 }
423 dr->vaddr = vaddr;
424 dr->dma_handle = *handle;
425 dr->size = size;
426 devres_add(dev, dr);
427 return vaddr;
428}
429
430static inline bool is_ipv4_pkt(struct sk_buff *skb)
431{
432 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
433}
434
435static int
436fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
437{
438 /* Only run for packets requiring a checksum. */
439 if (skb->ip_summed != CHECKSUM_PARTIAL)
440 return 0;
441
442 if (unlikely(skb_cow_head(skb, 0)))
443 return -1;
444
445 if (is_ipv4_pkt(skb))
446 ip_hdr(skb)->check = 0;
447 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
448
449 return 0;
450}
451
452static int
453fec_enet_create_page_pool(struct fec_enet_private *fep,
454 struct fec_enet_priv_rx_q *rxq, int size)
455{
456 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
457 struct page_pool_params pp_params = {
458 .order = 0,
459 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
460 .pool_size = size,
461 .nid = dev_to_node(&fep->pdev->dev),
462 .dev = &fep->pdev->dev,
463 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
464 .offset = FEC_ENET_XDP_HEADROOM,
465 .max_len = FEC_ENET_RX_FRSIZE,
466 };
467 int err;
468
469 rxq->page_pool = page_pool_create(&pp_params);
470 if (IS_ERR(rxq->page_pool)) {
471 err = PTR_ERR(rxq->page_pool);
472 rxq->page_pool = NULL;
473 return err;
474 }
475
476 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0);
477 if (err < 0)
478 goto err_free_pp;
479
480 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
481 rxq->page_pool);
482 if (err)
483 goto err_unregister_rxq;
484
485 return 0;
486
487err_unregister_rxq:
488 xdp_rxq_info_unreg(&rxq->xdp_rxq);
489err_free_pp:
490 page_pool_destroy(rxq->page_pool);
491 rxq->page_pool = NULL;
492 return err;
493}
494
495static struct bufdesc *
496fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
497 struct sk_buff *skb,
498 struct net_device *ndev)
499{
500 struct fec_enet_private *fep = netdev_priv(ndev);
501 struct bufdesc *bdp = txq->bd.cur;
502 struct bufdesc_ex *ebdp;
503 int nr_frags = skb_shinfo(skb)->nr_frags;
504 int frag, frag_len;
505 unsigned short status;
506 unsigned int estatus = 0;
507 skb_frag_t *this_frag;
508 unsigned int index;
509 void *bufaddr;
510 dma_addr_t addr;
511 int i;
512
513 for (frag = 0; frag < nr_frags; frag++) {
514 this_frag = &skb_shinfo(skb)->frags[frag];
515 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
516 ebdp = (struct bufdesc_ex *)bdp;
517
518 status = fec16_to_cpu(bdp->cbd_sc);
519 status &= ~BD_ENET_TX_STATS;
520 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
521 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
522
523 /* Handle the last BD specially */
524 if (frag == nr_frags - 1) {
525 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
526 if (fep->bufdesc_ex) {
527 estatus |= BD_ENET_TX_INT;
528 if (unlikely(skb_shinfo(skb)->tx_flags &
529 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
530 estatus |= BD_ENET_TX_TS;
531 }
532 }
533
534 if (fep->bufdesc_ex) {
535 if (fep->quirks & FEC_QUIRK_HAS_AVB)
536 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
537 if (skb->ip_summed == CHECKSUM_PARTIAL)
538 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
539
540 ebdp->cbd_bdu = 0;
541 ebdp->cbd_esc = cpu_to_fec32(estatus);
542 }
543
544 bufaddr = skb_frag_address(this_frag);
545
546 index = fec_enet_get_bd_index(bdp, &txq->bd);
547 if (((unsigned long) bufaddr) & fep->tx_align ||
548 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
549 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
550 bufaddr = txq->tx_bounce[index];
551
552 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
553 swap_buffer(bufaddr, frag_len);
554 }
555
556 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
557 DMA_TO_DEVICE);
558 if (dma_mapping_error(&fep->pdev->dev, addr)) {
559 if (net_ratelimit())
560 netdev_err(ndev, "Tx DMA memory map failed\n");
561 goto dma_mapping_error;
562 }
563
564 bdp->cbd_bufaddr = cpu_to_fec32(addr);
565 bdp->cbd_datlen = cpu_to_fec16(frag_len);
566 /* Make sure the updates to rest of the descriptor are
567 * performed before transferring ownership.
568 */
569 wmb();
570 bdp->cbd_sc = cpu_to_fec16(status);
571 }
572
573 return bdp;
574dma_mapping_error:
575 bdp = txq->bd.cur;
576 for (i = 0; i < frag; i++) {
577 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
578 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
579 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
580 }
581 return ERR_PTR(-ENOMEM);
582}
583
584static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
585 struct sk_buff *skb, struct net_device *ndev)
586{
587 struct fec_enet_private *fep = netdev_priv(ndev);
588 int nr_frags = skb_shinfo(skb)->nr_frags;
589 struct bufdesc *bdp, *last_bdp;
590 void *bufaddr;
591 dma_addr_t addr;
592 unsigned short status;
593 unsigned short buflen;
594 unsigned int estatus = 0;
595 unsigned int index;
596 int entries_free;
597
598 entries_free = fec_enet_get_free_txdesc_num(txq);
599 if (entries_free < MAX_SKB_FRAGS + 1) {
600 dev_kfree_skb_any(skb);
601 if (net_ratelimit())
602 netdev_err(ndev, "NOT enough BD for SG!\n");
603 return NETDEV_TX_OK;
604 }
605
606 /* Protocol checksum off-load for TCP and UDP. */
607 if (fec_enet_clear_csum(skb, ndev)) {
608 dev_kfree_skb_any(skb);
609 return NETDEV_TX_OK;
610 }
611
612 /* Fill in a Tx ring entry */
613 bdp = txq->bd.cur;
614 last_bdp = bdp;
615 status = fec16_to_cpu(bdp->cbd_sc);
616 status &= ~BD_ENET_TX_STATS;
617
618 /* Set buffer length and buffer pointer */
619 bufaddr = skb->data;
620 buflen = skb_headlen(skb);
621
622 index = fec_enet_get_bd_index(bdp, &txq->bd);
623 if (((unsigned long) bufaddr) & fep->tx_align ||
624 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
625 memcpy(txq->tx_bounce[index], skb->data, buflen);
626 bufaddr = txq->tx_bounce[index];
627
628 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
629 swap_buffer(bufaddr, buflen);
630 }
631
632 /* Push the data cache so the CPM does not get stale memory data. */
633 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
634 if (dma_mapping_error(&fep->pdev->dev, addr)) {
635 dev_kfree_skb_any(skb);
636 if (net_ratelimit())
637 netdev_err(ndev, "Tx DMA memory map failed\n");
638 return NETDEV_TX_OK;
639 }
640
641 if (nr_frags) {
642 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
643 if (IS_ERR(last_bdp)) {
644 dma_unmap_single(&fep->pdev->dev, addr,
645 buflen, DMA_TO_DEVICE);
646 dev_kfree_skb_any(skb);
647 return NETDEV_TX_OK;
648 }
649 } else {
650 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
651 if (fep->bufdesc_ex) {
652 estatus = BD_ENET_TX_INT;
653 if (unlikely(skb_shinfo(skb)->tx_flags &
654 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
655 estatus |= BD_ENET_TX_TS;
656 }
657 }
658 bdp->cbd_bufaddr = cpu_to_fec32(addr);
659 bdp->cbd_datlen = cpu_to_fec16(buflen);
660
661 if (fep->bufdesc_ex) {
662
663 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
664
665 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
666 fep->hwts_tx_en))
667 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
668
669 if (fep->quirks & FEC_QUIRK_HAS_AVB)
670 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
671
672 if (skb->ip_summed == CHECKSUM_PARTIAL)
673 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
674
675 ebdp->cbd_bdu = 0;
676 ebdp->cbd_esc = cpu_to_fec32(estatus);
677 }
678
679 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
680 /* Save skb pointer */
681 txq->tx_buf[index].buf_p = skb;
682
683 /* Make sure the updates to rest of the descriptor are performed before
684 * transferring ownership.
685 */
686 wmb();
687
688 /* Send it on its way. Tell FEC it's ready, interrupt when done,
689 * it's the last BD of the frame, and to put the CRC on the end.
690 */
691 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
692 bdp->cbd_sc = cpu_to_fec16(status);
693
694 /* If this was the last BD in the ring, start at the beginning again. */
695 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
696
697 skb_tx_timestamp(skb);
698
699 /* Make sure the update to bdp is performed before txq->bd.cur. */
700 wmb();
701 txq->bd.cur = bdp;
702
703 /* Trigger transmission start */
704 writel(0, txq->bd.reg_desc_active);
705
706 return 0;
707}
708
709static int
710fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
711 struct net_device *ndev,
712 struct bufdesc *bdp, int index, char *data,
713 int size, bool last_tcp, bool is_last)
714{
715 struct fec_enet_private *fep = netdev_priv(ndev);
716 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
717 unsigned short status;
718 unsigned int estatus = 0;
719 dma_addr_t addr;
720
721 status = fec16_to_cpu(bdp->cbd_sc);
722 status &= ~BD_ENET_TX_STATS;
723
724 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
725
726 if (((unsigned long) data) & fep->tx_align ||
727 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
728 memcpy(txq->tx_bounce[index], data, size);
729 data = txq->tx_bounce[index];
730
731 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
732 swap_buffer(data, size);
733 }
734
735 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
736 if (dma_mapping_error(&fep->pdev->dev, addr)) {
737 dev_kfree_skb_any(skb);
738 if (net_ratelimit())
739 netdev_err(ndev, "Tx DMA memory map failed\n");
740 return NETDEV_TX_OK;
741 }
742
743 bdp->cbd_datlen = cpu_to_fec16(size);
744 bdp->cbd_bufaddr = cpu_to_fec32(addr);
745
746 if (fep->bufdesc_ex) {
747 if (fep->quirks & FEC_QUIRK_HAS_AVB)
748 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
749 if (skb->ip_summed == CHECKSUM_PARTIAL)
750 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
751 ebdp->cbd_bdu = 0;
752 ebdp->cbd_esc = cpu_to_fec32(estatus);
753 }
754
755 /* Handle the last BD specially */
756 if (last_tcp)
757 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
758 if (is_last) {
759 status |= BD_ENET_TX_INTR;
760 if (fep->bufdesc_ex)
761 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
762 }
763
764 bdp->cbd_sc = cpu_to_fec16(status);
765
766 return 0;
767}
768
769static int
770fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
771 struct sk_buff *skb, struct net_device *ndev,
772 struct bufdesc *bdp, int index)
773{
774 struct fec_enet_private *fep = netdev_priv(ndev);
775 int hdr_len = skb_tcp_all_headers(skb);
776 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
777 void *bufaddr;
778 unsigned long dmabuf;
779 unsigned short status;
780 unsigned int estatus = 0;
781
782 status = fec16_to_cpu(bdp->cbd_sc);
783 status &= ~BD_ENET_TX_STATS;
784 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
785
786 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
787 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
788 if (((unsigned long)bufaddr) & fep->tx_align ||
789 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
790 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
791 bufaddr = txq->tx_bounce[index];
792
793 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
794 swap_buffer(bufaddr, hdr_len);
795
796 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
797 hdr_len, DMA_TO_DEVICE);
798 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
799 dev_kfree_skb_any(skb);
800 if (net_ratelimit())
801 netdev_err(ndev, "Tx DMA memory map failed\n");
802 return NETDEV_TX_OK;
803 }
804 }
805
806 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
807 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
808
809 if (fep->bufdesc_ex) {
810 if (fep->quirks & FEC_QUIRK_HAS_AVB)
811 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
812 if (skb->ip_summed == CHECKSUM_PARTIAL)
813 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
814 ebdp->cbd_bdu = 0;
815 ebdp->cbd_esc = cpu_to_fec32(estatus);
816 }
817
818 bdp->cbd_sc = cpu_to_fec16(status);
819
820 return 0;
821}
822
823static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
824 struct sk_buff *skb,
825 struct net_device *ndev)
826{
827 struct fec_enet_private *fep = netdev_priv(ndev);
828 int hdr_len, total_len, data_left;
829 struct bufdesc *bdp = txq->bd.cur;
830 struct tso_t tso;
831 unsigned int index = 0;
832 int ret;
833
834 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
835 dev_kfree_skb_any(skb);
836 if (net_ratelimit())
837 netdev_err(ndev, "NOT enough BD for TSO!\n");
838 return NETDEV_TX_OK;
839 }
840
841 /* Protocol checksum off-load for TCP and UDP. */
842 if (fec_enet_clear_csum(skb, ndev)) {
843 dev_kfree_skb_any(skb);
844 return NETDEV_TX_OK;
845 }
846
847 /* Initialize the TSO handler, and prepare the first payload */
848 hdr_len = tso_start(skb, &tso);
849
850 total_len = skb->len - hdr_len;
851 while (total_len > 0) {
852 char *hdr;
853
854 index = fec_enet_get_bd_index(bdp, &txq->bd);
855 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
856 total_len -= data_left;
857
858 /* prepare packet headers: MAC + IP + TCP */
859 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
860 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
861 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
862 if (ret)
863 goto err_release;
864
865 while (data_left > 0) {
866 int size;
867
868 size = min_t(int, tso.size, data_left);
869 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
870 index = fec_enet_get_bd_index(bdp, &txq->bd);
871 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
872 bdp, index,
873 tso.data, size,
874 size == data_left,
875 total_len == 0);
876 if (ret)
877 goto err_release;
878
879 data_left -= size;
880 tso_build_data(skb, &tso, size);
881 }
882
883 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
884 }
885
886 /* Save skb pointer */
887 txq->tx_buf[index].buf_p = skb;
888
889 skb_tx_timestamp(skb);
890 txq->bd.cur = bdp;
891
892 /* Trigger transmission start */
893 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
894 !readl(txq->bd.reg_desc_active) ||
895 !readl(txq->bd.reg_desc_active) ||
896 !readl(txq->bd.reg_desc_active) ||
897 !readl(txq->bd.reg_desc_active))
898 writel(0, txq->bd.reg_desc_active);
899
900 return 0;
901
902err_release:
903 /* TODO: Release all used data descriptors for TSO */
904 return ret;
905}
906
907static netdev_tx_t
908fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
909{
910 struct fec_enet_private *fep = netdev_priv(ndev);
911 int entries_free;
912 unsigned short queue;
913 struct fec_enet_priv_tx_q *txq;
914 struct netdev_queue *nq;
915 int ret;
916
917 queue = skb_get_queue_mapping(skb);
918 txq = fep->tx_queue[queue];
919 nq = netdev_get_tx_queue(ndev, queue);
920
921 if (skb_is_gso(skb))
922 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
923 else
924 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
925 if (ret)
926 return ret;
927
928 entries_free = fec_enet_get_free_txdesc_num(txq);
929 if (entries_free <= txq->tx_stop_threshold)
930 netif_tx_stop_queue(nq);
931
932 return NETDEV_TX_OK;
933}
934
935/* Init RX & TX buffer descriptors
936 */
937static void fec_enet_bd_init(struct net_device *dev)
938{
939 struct fec_enet_private *fep = netdev_priv(dev);
940 struct fec_enet_priv_tx_q *txq;
941 struct fec_enet_priv_rx_q *rxq;
942 struct bufdesc *bdp;
943 unsigned int i;
944 unsigned int q;
945
946 for (q = 0; q < fep->num_rx_queues; q++) {
947 /* Initialize the receive buffer descriptors. */
948 rxq = fep->rx_queue[q];
949 bdp = rxq->bd.base;
950
951 for (i = 0; i < rxq->bd.ring_size; i++) {
952
953 /* Initialize the BD for every fragment in the page. */
954 if (bdp->cbd_bufaddr)
955 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
956 else
957 bdp->cbd_sc = cpu_to_fec16(0);
958 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
959 }
960
961 /* Set the last buffer to wrap */
962 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
963 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
964
965 rxq->bd.cur = rxq->bd.base;
966 }
967
968 for (q = 0; q < fep->num_tx_queues; q++) {
969 /* ...and the same for transmit */
970 txq = fep->tx_queue[q];
971 bdp = txq->bd.base;
972 txq->bd.cur = bdp;
973
974 for (i = 0; i < txq->bd.ring_size; i++) {
975 /* Initialize the BD for every fragment in the page. */
976 bdp->cbd_sc = cpu_to_fec16(0);
977 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
978 if (bdp->cbd_bufaddr &&
979 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
980 dma_unmap_single(&fep->pdev->dev,
981 fec32_to_cpu(bdp->cbd_bufaddr),
982 fec16_to_cpu(bdp->cbd_datlen),
983 DMA_TO_DEVICE);
984 if (txq->tx_buf[i].buf_p)
985 dev_kfree_skb_any(txq->tx_buf[i].buf_p);
986 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) {
987 if (bdp->cbd_bufaddr)
988 dma_unmap_single(&fep->pdev->dev,
989 fec32_to_cpu(bdp->cbd_bufaddr),
990 fec16_to_cpu(bdp->cbd_datlen),
991 DMA_TO_DEVICE);
992
993 if (txq->tx_buf[i].buf_p)
994 xdp_return_frame(txq->tx_buf[i].buf_p);
995 } else {
996 struct page *page = txq->tx_buf[i].buf_p;
997
998 if (page)
999 page_pool_put_page(page->pp, page, 0, false);
1000 }
1001
1002 txq->tx_buf[i].buf_p = NULL;
1003 /* restore default tx buffer type: FEC_TXBUF_T_SKB */
1004 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
1005 bdp->cbd_bufaddr = cpu_to_fec32(0);
1006 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1007 }
1008
1009 /* Set the last buffer to wrap */
1010 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
1011 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
1012 txq->dirty_tx = bdp;
1013 }
1014}
1015
1016static void fec_enet_active_rxring(struct net_device *ndev)
1017{
1018 struct fec_enet_private *fep = netdev_priv(ndev);
1019 int i;
1020
1021 for (i = 0; i < fep->num_rx_queues; i++)
1022 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
1023}
1024
1025static void fec_enet_enable_ring(struct net_device *ndev)
1026{
1027 struct fec_enet_private *fep = netdev_priv(ndev);
1028 struct fec_enet_priv_tx_q *txq;
1029 struct fec_enet_priv_rx_q *rxq;
1030 int i;
1031
1032 for (i = 0; i < fep->num_rx_queues; i++) {
1033 rxq = fep->rx_queue[i];
1034 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
1035 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
1036
1037 /* enable DMA1/2 */
1038 if (i)
1039 writel(RCMR_MATCHEN | RCMR_CMP(i),
1040 fep->hwp + FEC_RCMR(i));
1041 }
1042
1043 for (i = 0; i < fep->num_tx_queues; i++) {
1044 txq = fep->tx_queue[i];
1045 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
1046
1047 /* enable DMA1/2 */
1048 if (i)
1049 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
1050 fep->hwp + FEC_DMA_CFG(i));
1051 }
1052}
1053
1054/*
1055 * This function is called to start or restart the FEC during a link
1056 * change, transmit timeout, or to reconfigure the FEC. The network
1057 * packet processing for this device must be stopped before this call.
1058 */
1059static void
1060fec_restart(struct net_device *ndev)
1061{
1062 struct fec_enet_private *fep = netdev_priv(ndev);
1063 u32 temp_mac[2];
1064 u32 rcntl = OPT_FRAME_SIZE | 0x04;
1065 u32 ecntl = 0x2; /* ETHEREN */
1066
1067 /* Whack a reset. We should wait for this.
1068 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1069 * instead of reset MAC itself.
1070 */
1071 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES ||
1072 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) {
1073 writel(0, fep->hwp + FEC_ECNTRL);
1074 } else {
1075 writel(1, fep->hwp + FEC_ECNTRL);
1076 udelay(10);
1077 }
1078
1079 /*
1080 * enet-mac reset will reset mac address registers too,
1081 * so need to reconfigure it.
1082 */
1083 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
1084 writel((__force u32)cpu_to_be32(temp_mac[0]),
1085 fep->hwp + FEC_ADDR_LOW);
1086 writel((__force u32)cpu_to_be32(temp_mac[1]),
1087 fep->hwp + FEC_ADDR_HIGH);
1088
1089 /* Clear any outstanding interrupt, except MDIO. */
1090 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
1091
1092 fec_enet_bd_init(ndev);
1093
1094 fec_enet_enable_ring(ndev);
1095
1096 /* Enable MII mode */
1097 if (fep->full_duplex == DUPLEX_FULL) {
1098 /* FD enable */
1099 writel(0x04, fep->hwp + FEC_X_CNTRL);
1100 } else {
1101 /* No Rcv on Xmit */
1102 rcntl |= 0x02;
1103 writel(0x0, fep->hwp + FEC_X_CNTRL);
1104 }
1105
1106 /* Set MII speed */
1107 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1108
1109#if !defined(CONFIG_M5272)
1110 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1111 u32 val = readl(fep->hwp + FEC_RACC);
1112
1113 /* align IP header */
1114 val |= FEC_RACC_SHIFT16;
1115 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1116 /* set RX checksum */
1117 val |= FEC_RACC_OPTIONS;
1118 else
1119 val &= ~FEC_RACC_OPTIONS;
1120 writel(val, fep->hwp + FEC_RACC);
1121 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1122 }
1123#endif
1124
1125 /*
1126 * The phy interface and speed need to get configured
1127 * differently on enet-mac.
1128 */
1129 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1130 /* Enable flow control and length check */
1131 rcntl |= 0x40000000 | 0x00000020;
1132
1133 /* RGMII, RMII or MII */
1134 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1135 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1136 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1137 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1138 rcntl |= (1 << 6);
1139 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1140 rcntl |= (1 << 8);
1141 else
1142 rcntl &= ~(1 << 8);
1143
1144 /* 1G, 100M or 10M */
1145 if (ndev->phydev) {
1146 if (ndev->phydev->speed == SPEED_1000)
1147 ecntl |= (1 << 5);
1148 else if (ndev->phydev->speed == SPEED_100)
1149 rcntl &= ~(1 << 9);
1150 else
1151 rcntl |= (1 << 9);
1152 }
1153 } else {
1154#ifdef FEC_MIIGSK_ENR
1155 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1156 u32 cfgr;
1157 /* disable the gasket and wait */
1158 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1159 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1160 udelay(1);
1161
1162 /*
1163 * configure the gasket:
1164 * RMII, 50 MHz, no loopback, no echo
1165 * MII, 25 MHz, no loopback, no echo
1166 */
1167 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1168 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1169 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1170 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1171 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1172
1173 /* re-enable the gasket */
1174 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1175 }
1176#endif
1177 }
1178
1179#if !defined(CONFIG_M5272)
1180 /* enable pause frame*/
1181 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1182 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1183 ndev->phydev && ndev->phydev->pause)) {
1184 rcntl |= FEC_ENET_FCE;
1185
1186 /* set FIFO threshold parameter to reduce overrun */
1187 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1188 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1189 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1190 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1191
1192 /* OPD */
1193 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1194 } else {
1195 rcntl &= ~FEC_ENET_FCE;
1196 }
1197#endif /* !defined(CONFIG_M5272) */
1198
1199 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1200
1201 /* Setup multicast filter. */
1202 set_multicast_list(ndev);
1203#ifndef CONFIG_M5272
1204 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1205 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1206#endif
1207
1208 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1209 /* enable ENET endian swap */
1210 ecntl |= (1 << 8);
1211 /* enable ENET store and forward mode */
1212 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1213 }
1214
1215 if (fep->bufdesc_ex)
1216 ecntl |= (1 << 4);
1217
1218 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1219 fep->rgmii_txc_dly)
1220 ecntl |= FEC_ENET_TXC_DLY;
1221 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1222 fep->rgmii_rxc_dly)
1223 ecntl |= FEC_ENET_RXC_DLY;
1224
1225#ifndef CONFIG_M5272
1226 /* Enable the MIB statistic event counters */
1227 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1228#endif
1229
1230 /* And last, enable the transmit and receive processing */
1231 writel(ecntl, fep->hwp + FEC_ECNTRL);
1232 fec_enet_active_rxring(ndev);
1233
1234 if (fep->bufdesc_ex)
1235 fec_ptp_start_cyclecounter(ndev);
1236
1237 /* Enable interrupts we wish to service */
1238 if (fep->link)
1239 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1240 else
1241 writel(0, fep->hwp + FEC_IMASK);
1242
1243 /* Init the interrupt coalescing */
1244 if (fep->quirks & FEC_QUIRK_HAS_COALESCE)
1245 fec_enet_itr_coal_set(ndev);
1246}
1247
1248static int fec_enet_ipc_handle_init(struct fec_enet_private *fep)
1249{
1250 if (!(of_machine_is_compatible("fsl,imx8qm") ||
1251 of_machine_is_compatible("fsl,imx8qxp") ||
1252 of_machine_is_compatible("fsl,imx8dxl")))
1253 return 0;
1254
1255 return imx_scu_get_handle(&fep->ipc_handle);
1256}
1257
1258static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled)
1259{
1260 struct device_node *np = fep->pdev->dev.of_node;
1261 u32 rsrc_id, val;
1262 int idx;
1263
1264 if (!np || !fep->ipc_handle)
1265 return;
1266
1267 idx = of_alias_get_id(np, "ethernet");
1268 if (idx < 0)
1269 idx = 0;
1270 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0;
1271
1272 val = enabled ? 1 : 0;
1273 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val);
1274}
1275
1276static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1277{
1278 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1279 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1280
1281 if (stop_gpr->gpr) {
1282 if (enabled)
1283 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1284 BIT(stop_gpr->bit),
1285 BIT(stop_gpr->bit));
1286 else
1287 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1288 BIT(stop_gpr->bit), 0);
1289 } else if (pdata && pdata->sleep_mode_enable) {
1290 pdata->sleep_mode_enable(enabled);
1291 } else {
1292 fec_enet_ipg_stop_set(fep, enabled);
1293 }
1294}
1295
1296static void fec_irqs_disable(struct net_device *ndev)
1297{
1298 struct fec_enet_private *fep = netdev_priv(ndev);
1299
1300 writel(0, fep->hwp + FEC_IMASK);
1301}
1302
1303static void fec_irqs_disable_except_wakeup(struct net_device *ndev)
1304{
1305 struct fec_enet_private *fep = netdev_priv(ndev);
1306
1307 writel(0, fep->hwp + FEC_IMASK);
1308 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1309}
1310
1311static void
1312fec_stop(struct net_device *ndev)
1313{
1314 struct fec_enet_private *fep = netdev_priv(ndev);
1315 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1316 u32 val;
1317
1318 /* We cannot expect a graceful transmit stop without link !!! */
1319 if (fep->link) {
1320 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1321 udelay(10);
1322 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1323 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1324 }
1325
1326 /* Whack a reset. We should wait for this.
1327 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1328 * instead of reset MAC itself.
1329 */
1330 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1331 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
1332 writel(0, fep->hwp + FEC_ECNTRL);
1333 } else {
1334 writel(1, fep->hwp + FEC_ECNTRL);
1335 udelay(10);
1336 }
1337 } else {
1338 val = readl(fep->hwp + FEC_ECNTRL);
1339 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1340 writel(val, fep->hwp + FEC_ECNTRL);
1341 }
1342 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1343 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1344
1345 /* We have to keep ENET enabled to have MII interrupt stay working */
1346 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1347 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1348 writel(2, fep->hwp + FEC_ECNTRL);
1349 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1350 }
1351}
1352
1353
1354static void
1355fec_timeout(struct net_device *ndev, unsigned int txqueue)
1356{
1357 struct fec_enet_private *fep = netdev_priv(ndev);
1358
1359 fec_dump(ndev);
1360
1361 ndev->stats.tx_errors++;
1362
1363 schedule_work(&fep->tx_timeout_work);
1364}
1365
1366static void fec_enet_timeout_work(struct work_struct *work)
1367{
1368 struct fec_enet_private *fep =
1369 container_of(work, struct fec_enet_private, tx_timeout_work);
1370 struct net_device *ndev = fep->netdev;
1371
1372 rtnl_lock();
1373 if (netif_device_present(ndev) || netif_running(ndev)) {
1374 napi_disable(&fep->napi);
1375 netif_tx_lock_bh(ndev);
1376 fec_restart(ndev);
1377 netif_tx_wake_all_queues(ndev);
1378 netif_tx_unlock_bh(ndev);
1379 napi_enable(&fep->napi);
1380 }
1381 rtnl_unlock();
1382}
1383
1384static void
1385fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1386 struct skb_shared_hwtstamps *hwtstamps)
1387{
1388 unsigned long flags;
1389 u64 ns;
1390
1391 spin_lock_irqsave(&fep->tmreg_lock, flags);
1392 ns = timecounter_cyc2time(&fep->tc, ts);
1393 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1394
1395 memset(hwtstamps, 0, sizeof(*hwtstamps));
1396 hwtstamps->hwtstamp = ns_to_ktime(ns);
1397}
1398
1399static void
1400fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget)
1401{
1402 struct fec_enet_private *fep;
1403 struct xdp_frame *xdpf;
1404 struct bufdesc *bdp;
1405 unsigned short status;
1406 struct sk_buff *skb;
1407 struct fec_enet_priv_tx_q *txq;
1408 struct netdev_queue *nq;
1409 int index = 0;
1410 int entries_free;
1411 struct page *page;
1412 int frame_len;
1413
1414 fep = netdev_priv(ndev);
1415
1416 txq = fep->tx_queue[queue_id];
1417 /* get next bdp of dirty_tx */
1418 nq = netdev_get_tx_queue(ndev, queue_id);
1419 bdp = txq->dirty_tx;
1420
1421 /* get next bdp of dirty_tx */
1422 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1423
1424 while (bdp != READ_ONCE(txq->bd.cur)) {
1425 /* Order the load of bd.cur and cbd_sc */
1426 rmb();
1427 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1428 if (status & BD_ENET_TX_READY)
1429 break;
1430
1431 index = fec_enet_get_bd_index(bdp, &txq->bd);
1432
1433 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1434 skb = txq->tx_buf[index].buf_p;
1435 if (bdp->cbd_bufaddr &&
1436 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1437 dma_unmap_single(&fep->pdev->dev,
1438 fec32_to_cpu(bdp->cbd_bufaddr),
1439 fec16_to_cpu(bdp->cbd_datlen),
1440 DMA_TO_DEVICE);
1441 bdp->cbd_bufaddr = cpu_to_fec32(0);
1442 if (!skb)
1443 goto tx_buf_done;
1444 } else {
1445 /* Tx processing cannot call any XDP (or page pool) APIs if
1446 * the "budget" is 0. Because NAPI is called with budget of
1447 * 0 (such as netpoll) indicates we may be in an IRQ context,
1448 * however, we can't use the page pool from IRQ context.
1449 */
1450 if (unlikely(!budget))
1451 break;
1452
1453 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) {
1454 xdpf = txq->tx_buf[index].buf_p;
1455 if (bdp->cbd_bufaddr)
1456 dma_unmap_single(&fep->pdev->dev,
1457 fec32_to_cpu(bdp->cbd_bufaddr),
1458 fec16_to_cpu(bdp->cbd_datlen),
1459 DMA_TO_DEVICE);
1460 } else {
1461 page = txq->tx_buf[index].buf_p;
1462 }
1463
1464 bdp->cbd_bufaddr = cpu_to_fec32(0);
1465 if (unlikely(!txq->tx_buf[index].buf_p)) {
1466 txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1467 goto tx_buf_done;
1468 }
1469
1470 frame_len = fec16_to_cpu(bdp->cbd_datlen);
1471 }
1472
1473 /* Check for errors. */
1474 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1475 BD_ENET_TX_RL | BD_ENET_TX_UN |
1476 BD_ENET_TX_CSL)) {
1477 ndev->stats.tx_errors++;
1478 if (status & BD_ENET_TX_HB) /* No heartbeat */
1479 ndev->stats.tx_heartbeat_errors++;
1480 if (status & BD_ENET_TX_LC) /* Late collision */
1481 ndev->stats.tx_window_errors++;
1482 if (status & BD_ENET_TX_RL) /* Retrans limit */
1483 ndev->stats.tx_aborted_errors++;
1484 if (status & BD_ENET_TX_UN) /* Underrun */
1485 ndev->stats.tx_fifo_errors++;
1486 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1487 ndev->stats.tx_carrier_errors++;
1488 } else {
1489 ndev->stats.tx_packets++;
1490
1491 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB)
1492 ndev->stats.tx_bytes += skb->len;
1493 else
1494 ndev->stats.tx_bytes += frame_len;
1495 }
1496
1497 /* Deferred means some collisions occurred during transmit,
1498 * but we eventually sent the packet OK.
1499 */
1500 if (status & BD_ENET_TX_DEF)
1501 ndev->stats.collisions++;
1502
1503 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1504 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who
1505 * are to time stamp the packet, so we still need to check time
1506 * stamping enabled flag.
1507 */
1508 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
1509 fep->hwts_tx_en) && fep->bufdesc_ex) {
1510 struct skb_shared_hwtstamps shhwtstamps;
1511 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1512
1513 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1514 skb_tstamp_tx(skb, &shhwtstamps);
1515 }
1516
1517 /* Free the sk buffer associated with this last transmit */
1518 napi_consume_skb(skb, budget);
1519 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) {
1520 xdp_return_frame_rx_napi(xdpf);
1521 } else { /* recycle pages of XDP_TX frames */
1522 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */
1523 page_pool_put_page(page->pp, page, 0, true);
1524 }
1525
1526 txq->tx_buf[index].buf_p = NULL;
1527 /* restore default tx buffer type: FEC_TXBUF_T_SKB */
1528 txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1529
1530tx_buf_done:
1531 /* Make sure the update to bdp and tx_buf are performed
1532 * before dirty_tx
1533 */
1534 wmb();
1535 txq->dirty_tx = bdp;
1536
1537 /* Update pointer to next buffer descriptor to be transmitted */
1538 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1539
1540 /* Since we have freed up a buffer, the ring is no longer full
1541 */
1542 if (netif_tx_queue_stopped(nq)) {
1543 entries_free = fec_enet_get_free_txdesc_num(txq);
1544 if (entries_free >= txq->tx_wake_threshold)
1545 netif_tx_wake_queue(nq);
1546 }
1547 }
1548
1549 /* ERR006358: Keep the transmitter going */
1550 if (bdp != txq->bd.cur &&
1551 readl(txq->bd.reg_desc_active) == 0)
1552 writel(0, txq->bd.reg_desc_active);
1553}
1554
1555static void fec_enet_tx(struct net_device *ndev, int budget)
1556{
1557 struct fec_enet_private *fep = netdev_priv(ndev);
1558 int i;
1559
1560 /* Make sure that AVB queues are processed first. */
1561 for (i = fep->num_tx_queues - 1; i >= 0; i--)
1562 fec_enet_tx_queue(ndev, i, budget);
1563}
1564
1565static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq,
1566 struct bufdesc *bdp, int index)
1567{
1568 struct page *new_page;
1569 dma_addr_t phys_addr;
1570
1571 new_page = page_pool_dev_alloc_pages(rxq->page_pool);
1572 WARN_ON(!new_page);
1573 rxq->rx_skb_info[index].page = new_page;
1574
1575 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM;
1576 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM;
1577 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
1578}
1579
1580static u32
1581fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog,
1582 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu)
1583{
1584 unsigned int sync, len = xdp->data_end - xdp->data;
1585 u32 ret = FEC_ENET_XDP_PASS;
1586 struct page *page;
1587 int err;
1588 u32 act;
1589
1590 act = bpf_prog_run_xdp(prog, xdp);
1591
1592 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover
1593 * max len CPU touch
1594 */
1595 sync = xdp->data_end - xdp->data;
1596 sync = max(sync, len);
1597
1598 switch (act) {
1599 case XDP_PASS:
1600 rxq->stats[RX_XDP_PASS]++;
1601 ret = FEC_ENET_XDP_PASS;
1602 break;
1603
1604 case XDP_REDIRECT:
1605 rxq->stats[RX_XDP_REDIRECT]++;
1606 err = xdp_do_redirect(fep->netdev, xdp, prog);
1607 if (unlikely(err))
1608 goto xdp_err;
1609
1610 ret = FEC_ENET_XDP_REDIR;
1611 break;
1612
1613 case XDP_TX:
1614 rxq->stats[RX_XDP_TX]++;
1615 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync);
1616 if (unlikely(err)) {
1617 rxq->stats[RX_XDP_TX_ERRORS]++;
1618 goto xdp_err;
1619 }
1620
1621 ret = FEC_ENET_XDP_TX;
1622 break;
1623
1624 default:
1625 bpf_warn_invalid_xdp_action(fep->netdev, prog, act);
1626 fallthrough;
1627
1628 case XDP_ABORTED:
1629 fallthrough; /* handle aborts by dropping packet */
1630
1631 case XDP_DROP:
1632 rxq->stats[RX_XDP_DROP]++;
1633xdp_err:
1634 ret = FEC_ENET_XDP_CONSUMED;
1635 page = virt_to_head_page(xdp->data);
1636 page_pool_put_page(rxq->page_pool, page, sync, true);
1637 if (act != XDP_DROP)
1638 trace_xdp_exception(fep->netdev, prog, act);
1639 break;
1640 }
1641
1642 return ret;
1643}
1644
1645/* During a receive, the bd_rx.cur points to the current incoming buffer.
1646 * When we update through the ring, if the next incoming buffer has
1647 * not been given to the system, we just set the empty indicator,
1648 * effectively tossing the packet.
1649 */
1650static int
1651fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1652{
1653 struct fec_enet_private *fep = netdev_priv(ndev);
1654 struct fec_enet_priv_rx_q *rxq;
1655 struct bufdesc *bdp;
1656 unsigned short status;
1657 struct sk_buff *skb;
1658 ushort pkt_len;
1659 __u8 *data;
1660 int pkt_received = 0;
1661 struct bufdesc_ex *ebdp = NULL;
1662 bool vlan_packet_rcvd = false;
1663 u16 vlan_tag;
1664 int index = 0;
1665 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1666 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
1667 u32 ret, xdp_result = FEC_ENET_XDP_PASS;
1668 u32 data_start = FEC_ENET_XDP_HEADROOM;
1669 int cpu = smp_processor_id();
1670 struct xdp_buff xdp;
1671 struct page *page;
1672 u32 sub_len = 4;
1673
1674#if !defined(CONFIG_M5272)
1675 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of
1676 * FEC_RACC_SHIFT16 is set by default in the probe function.
1677 */
1678 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1679 data_start += 2;
1680 sub_len += 2;
1681 }
1682#endif
1683
1684#if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA)
1685 /*
1686 * Hacky flush of all caches instead of using the DMA API for the TSO
1687 * headers.
1688 */
1689 flush_cache_all();
1690#endif
1691 rxq = fep->rx_queue[queue_id];
1692
1693 /* First, grab all of the stats for the incoming packet.
1694 * These get messed up if we get called due to a busy condition.
1695 */
1696 bdp = rxq->bd.cur;
1697 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq);
1698
1699 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1700
1701 if (pkt_received >= budget)
1702 break;
1703 pkt_received++;
1704
1705 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT);
1706
1707 /* Check for errors. */
1708 status ^= BD_ENET_RX_LAST;
1709 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1710 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1711 BD_ENET_RX_CL)) {
1712 ndev->stats.rx_errors++;
1713 if (status & BD_ENET_RX_OV) {
1714 /* FIFO overrun */
1715 ndev->stats.rx_fifo_errors++;
1716 goto rx_processing_done;
1717 }
1718 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1719 | BD_ENET_RX_LAST)) {
1720 /* Frame too long or too short. */
1721 ndev->stats.rx_length_errors++;
1722 if (status & BD_ENET_RX_LAST)
1723 netdev_err(ndev, "rcv is not +last\n");
1724 }
1725 if (status & BD_ENET_RX_CR) /* CRC Error */
1726 ndev->stats.rx_crc_errors++;
1727 /* Report late collisions as a frame error. */
1728 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1729 ndev->stats.rx_frame_errors++;
1730 goto rx_processing_done;
1731 }
1732
1733 /* Process the incoming frame. */
1734 ndev->stats.rx_packets++;
1735 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1736 ndev->stats.rx_bytes += pkt_len;
1737
1738 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1739 page = rxq->rx_skb_info[index].page;
1740 dma_sync_single_for_cpu(&fep->pdev->dev,
1741 fec32_to_cpu(bdp->cbd_bufaddr),
1742 pkt_len,
1743 DMA_FROM_DEVICE);
1744 prefetch(page_address(page));
1745 fec_enet_update_cbd(rxq, bdp, index);
1746
1747 if (xdp_prog) {
1748 xdp_buff_clear_frags_flag(&xdp);
1749 /* subtract 16bit shift and FCS */
1750 xdp_prepare_buff(&xdp, page_address(page),
1751 data_start, pkt_len - sub_len, false);
1752 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu);
1753 xdp_result |= ret;
1754 if (ret != FEC_ENET_XDP_PASS)
1755 goto rx_processing_done;
1756 }
1757
1758 /* The packet length includes FCS, but we don't want to
1759 * include that when passing upstream as it messes up
1760 * bridging applications.
1761 */
1762 skb = build_skb(page_address(page), PAGE_SIZE);
1763 if (unlikely(!skb)) {
1764 page_pool_recycle_direct(rxq->page_pool, page);
1765 ndev->stats.rx_dropped++;
1766
1767 netdev_err_once(ndev, "build_skb failed!\n");
1768 goto rx_processing_done;
1769 }
1770
1771 skb_reserve(skb, data_start);
1772 skb_put(skb, pkt_len - sub_len);
1773 skb_mark_for_recycle(skb);
1774
1775 if (unlikely(need_swap)) {
1776 data = page_address(page) + FEC_ENET_XDP_HEADROOM;
1777 swap_buffer(data, pkt_len);
1778 }
1779 data = skb->data;
1780
1781 /* Extract the enhanced buffer descriptor */
1782 ebdp = NULL;
1783 if (fep->bufdesc_ex)
1784 ebdp = (struct bufdesc_ex *)bdp;
1785
1786 /* If this is a VLAN packet remove the VLAN Tag */
1787 vlan_packet_rcvd = false;
1788 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1789 fep->bufdesc_ex &&
1790 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1791 /* Push and remove the vlan tag */
1792 struct vlan_hdr *vlan_header =
1793 (struct vlan_hdr *) (data + ETH_HLEN);
1794 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1795
1796 vlan_packet_rcvd = true;
1797
1798 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1799 skb_pull(skb, VLAN_HLEN);
1800 }
1801
1802 skb->protocol = eth_type_trans(skb, ndev);
1803
1804 /* Get receive timestamp from the skb */
1805 if (fep->hwts_rx_en && fep->bufdesc_ex)
1806 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1807 skb_hwtstamps(skb));
1808
1809 if (fep->bufdesc_ex &&
1810 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1811 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1812 /* don't check it */
1813 skb->ip_summed = CHECKSUM_UNNECESSARY;
1814 } else {
1815 skb_checksum_none_assert(skb);
1816 }
1817 }
1818
1819 /* Handle received VLAN packets */
1820 if (vlan_packet_rcvd)
1821 __vlan_hwaccel_put_tag(skb,
1822 htons(ETH_P_8021Q),
1823 vlan_tag);
1824
1825 skb_record_rx_queue(skb, queue_id);
1826 napi_gro_receive(&fep->napi, skb);
1827
1828rx_processing_done:
1829 /* Clear the status flags for this buffer */
1830 status &= ~BD_ENET_RX_STATS;
1831
1832 /* Mark the buffer empty */
1833 status |= BD_ENET_RX_EMPTY;
1834
1835 if (fep->bufdesc_ex) {
1836 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1837
1838 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1839 ebdp->cbd_prot = 0;
1840 ebdp->cbd_bdu = 0;
1841 }
1842 /* Make sure the updates to rest of the descriptor are
1843 * performed before transferring ownership.
1844 */
1845 wmb();
1846 bdp->cbd_sc = cpu_to_fec16(status);
1847
1848 /* Update BD pointer to next entry */
1849 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1850
1851 /* Doing this here will keep the FEC running while we process
1852 * incoming frames. On a heavily loaded network, we should be
1853 * able to keep up at the expense of system resources.
1854 */
1855 writel(0, rxq->bd.reg_desc_active);
1856 }
1857 rxq->bd.cur = bdp;
1858
1859 if (xdp_result & FEC_ENET_XDP_REDIR)
1860 xdp_do_flush();
1861
1862 return pkt_received;
1863}
1864
1865static int fec_enet_rx(struct net_device *ndev, int budget)
1866{
1867 struct fec_enet_private *fep = netdev_priv(ndev);
1868 int i, done = 0;
1869
1870 /* Make sure that AVB queues are processed first. */
1871 for (i = fep->num_rx_queues - 1; i >= 0; i--)
1872 done += fec_enet_rx_queue(ndev, budget - done, i);
1873
1874 return done;
1875}
1876
1877static bool fec_enet_collect_events(struct fec_enet_private *fep)
1878{
1879 uint int_events;
1880
1881 int_events = readl(fep->hwp + FEC_IEVENT);
1882
1883 /* Don't clear MDIO events, we poll for those */
1884 int_events &= ~FEC_ENET_MII;
1885
1886 writel(int_events, fep->hwp + FEC_IEVENT);
1887
1888 return int_events != 0;
1889}
1890
1891static irqreturn_t
1892fec_enet_interrupt(int irq, void *dev_id)
1893{
1894 struct net_device *ndev = dev_id;
1895 struct fec_enet_private *fep = netdev_priv(ndev);
1896 irqreturn_t ret = IRQ_NONE;
1897
1898 if (fec_enet_collect_events(fep) && fep->link) {
1899 ret = IRQ_HANDLED;
1900
1901 if (napi_schedule_prep(&fep->napi)) {
1902 /* Disable interrupts */
1903 writel(0, fep->hwp + FEC_IMASK);
1904 __napi_schedule(&fep->napi);
1905 }
1906 }
1907
1908 return ret;
1909}
1910
1911static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1912{
1913 struct net_device *ndev = napi->dev;
1914 struct fec_enet_private *fep = netdev_priv(ndev);
1915 int done = 0;
1916
1917 do {
1918 done += fec_enet_rx(ndev, budget - done);
1919 fec_enet_tx(ndev, budget);
1920 } while ((done < budget) && fec_enet_collect_events(fep));
1921
1922 if (done < budget) {
1923 napi_complete_done(napi, done);
1924 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1925 }
1926
1927 return done;
1928}
1929
1930/* ------------------------------------------------------------------------- */
1931static int fec_get_mac(struct net_device *ndev)
1932{
1933 struct fec_enet_private *fep = netdev_priv(ndev);
1934 unsigned char *iap, tmpaddr[ETH_ALEN];
1935 int ret;
1936
1937 /*
1938 * try to get mac address in following order:
1939 *
1940 * 1) module parameter via kernel command line in form
1941 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1942 */
1943 iap = macaddr;
1944
1945 /*
1946 * 2) from device tree data
1947 */
1948 if (!is_valid_ether_addr(iap)) {
1949 struct device_node *np = fep->pdev->dev.of_node;
1950 if (np) {
1951 ret = of_get_mac_address(np, tmpaddr);
1952 if (!ret)
1953 iap = tmpaddr;
1954 else if (ret == -EPROBE_DEFER)
1955 return ret;
1956 }
1957 }
1958
1959 /*
1960 * 3) from flash or fuse (via platform data)
1961 */
1962 if (!is_valid_ether_addr(iap)) {
1963#ifdef CONFIG_M5272
1964 if (FEC_FLASHMAC)
1965 iap = (unsigned char *)FEC_FLASHMAC;
1966#else
1967 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1968
1969 if (pdata)
1970 iap = (unsigned char *)&pdata->mac;
1971#endif
1972 }
1973
1974 /*
1975 * 4) FEC mac registers set by bootloader
1976 */
1977 if (!is_valid_ether_addr(iap)) {
1978 *((__be32 *) &tmpaddr[0]) =
1979 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1980 *((__be16 *) &tmpaddr[4]) =
1981 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1982 iap = &tmpaddr[0];
1983 }
1984
1985 /*
1986 * 5) random mac address
1987 */
1988 if (!is_valid_ether_addr(iap)) {
1989 /* Report it and use a random ethernet address instead */
1990 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1991 eth_hw_addr_random(ndev);
1992 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1993 ndev->dev_addr);
1994 return 0;
1995 }
1996
1997 /* Adjust MAC if using macaddr */
1998 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0);
1999
2000 return 0;
2001}
2002
2003/* ------------------------------------------------------------------------- */
2004
2005/*
2006 * Phy section
2007 */
2008static void fec_enet_adjust_link(struct net_device *ndev)
2009{
2010 struct fec_enet_private *fep = netdev_priv(ndev);
2011 struct phy_device *phy_dev = ndev->phydev;
2012 int status_change = 0;
2013
2014 /*
2015 * If the netdev is down, or is going down, we're not interested
2016 * in link state events, so just mark our idea of the link as down
2017 * and ignore the event.
2018 */
2019 if (!netif_running(ndev) || !netif_device_present(ndev)) {
2020 fep->link = 0;
2021 } else if (phy_dev->link) {
2022 if (!fep->link) {
2023 fep->link = phy_dev->link;
2024 status_change = 1;
2025 }
2026
2027 if (fep->full_duplex != phy_dev->duplex) {
2028 fep->full_duplex = phy_dev->duplex;
2029 status_change = 1;
2030 }
2031
2032 if (phy_dev->speed != fep->speed) {
2033 fep->speed = phy_dev->speed;
2034 status_change = 1;
2035 }
2036
2037 /* if any of the above changed restart the FEC */
2038 if (status_change) {
2039 netif_stop_queue(ndev);
2040 napi_disable(&fep->napi);
2041 netif_tx_lock_bh(ndev);
2042 fec_restart(ndev);
2043 netif_tx_wake_all_queues(ndev);
2044 netif_tx_unlock_bh(ndev);
2045 napi_enable(&fep->napi);
2046 }
2047 } else {
2048 if (fep->link) {
2049 netif_stop_queue(ndev);
2050 napi_disable(&fep->napi);
2051 netif_tx_lock_bh(ndev);
2052 fec_stop(ndev);
2053 netif_tx_unlock_bh(ndev);
2054 napi_enable(&fep->napi);
2055 fep->link = phy_dev->link;
2056 status_change = 1;
2057 }
2058 }
2059
2060 if (status_change)
2061 phy_print_status(phy_dev);
2062}
2063
2064static int fec_enet_mdio_wait(struct fec_enet_private *fep)
2065{
2066 uint ievent;
2067 int ret;
2068
2069 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
2070 ievent & FEC_ENET_MII, 2, 30000);
2071
2072 if (!ret)
2073 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2074
2075 return ret;
2076}
2077
2078static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
2079{
2080 struct fec_enet_private *fep = bus->priv;
2081 struct device *dev = &fep->pdev->dev;
2082 int ret = 0, frame_start, frame_addr, frame_op;
2083
2084 ret = pm_runtime_resume_and_get(dev);
2085 if (ret < 0)
2086 return ret;
2087
2088 /* C22 read */
2089 frame_op = FEC_MMFR_OP_READ;
2090 frame_start = FEC_MMFR_ST;
2091 frame_addr = regnum;
2092
2093 /* start a read op */
2094 writel(frame_start | frame_op |
2095 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2096 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2097
2098 /* wait for end of transfer */
2099 ret = fec_enet_mdio_wait(fep);
2100 if (ret) {
2101 netdev_err(fep->netdev, "MDIO read timeout\n");
2102 goto out;
2103 }
2104
2105 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2106
2107out:
2108 pm_runtime_mark_last_busy(dev);
2109 pm_runtime_put_autosuspend(dev);
2110
2111 return ret;
2112}
2113
2114static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id,
2115 int devad, int regnum)
2116{
2117 struct fec_enet_private *fep = bus->priv;
2118 struct device *dev = &fep->pdev->dev;
2119 int ret = 0, frame_start, frame_op;
2120
2121 ret = pm_runtime_resume_and_get(dev);
2122 if (ret < 0)
2123 return ret;
2124
2125 frame_start = FEC_MMFR_ST_C45;
2126
2127 /* write address */
2128 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2129 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2130 FEC_MMFR_TA | (regnum & 0xFFFF),
2131 fep->hwp + FEC_MII_DATA);
2132
2133 /* wait for end of transfer */
2134 ret = fec_enet_mdio_wait(fep);
2135 if (ret) {
2136 netdev_err(fep->netdev, "MDIO address write timeout\n");
2137 goto out;
2138 }
2139
2140 frame_op = FEC_MMFR_OP_READ_C45;
2141
2142 /* start a read op */
2143 writel(frame_start | frame_op |
2144 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2145 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2146
2147 /* wait for end of transfer */
2148 ret = fec_enet_mdio_wait(fep);
2149 if (ret) {
2150 netdev_err(fep->netdev, "MDIO read timeout\n");
2151 goto out;
2152 }
2153
2154 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2155
2156out:
2157 pm_runtime_mark_last_busy(dev);
2158 pm_runtime_put_autosuspend(dev);
2159
2160 return ret;
2161}
2162
2163static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
2164 u16 value)
2165{
2166 struct fec_enet_private *fep = bus->priv;
2167 struct device *dev = &fep->pdev->dev;
2168 int ret, frame_start, frame_addr;
2169
2170 ret = pm_runtime_resume_and_get(dev);
2171 if (ret < 0)
2172 return ret;
2173
2174 /* C22 write */
2175 frame_start = FEC_MMFR_ST;
2176 frame_addr = regnum;
2177
2178 /* start a write op */
2179 writel(frame_start | FEC_MMFR_OP_WRITE |
2180 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2181 FEC_MMFR_TA | FEC_MMFR_DATA(value),
2182 fep->hwp + FEC_MII_DATA);
2183
2184 /* wait for end of transfer */
2185 ret = fec_enet_mdio_wait(fep);
2186 if (ret)
2187 netdev_err(fep->netdev, "MDIO write timeout\n");
2188
2189 pm_runtime_mark_last_busy(dev);
2190 pm_runtime_put_autosuspend(dev);
2191
2192 return ret;
2193}
2194
2195static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id,
2196 int devad, int regnum, u16 value)
2197{
2198 struct fec_enet_private *fep = bus->priv;
2199 struct device *dev = &fep->pdev->dev;
2200 int ret, frame_start;
2201
2202 ret = pm_runtime_resume_and_get(dev);
2203 if (ret < 0)
2204 return ret;
2205
2206 frame_start = FEC_MMFR_ST_C45;
2207
2208 /* write address */
2209 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2210 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2211 FEC_MMFR_TA | (regnum & 0xFFFF),
2212 fep->hwp + FEC_MII_DATA);
2213
2214 /* wait for end of transfer */
2215 ret = fec_enet_mdio_wait(fep);
2216 if (ret) {
2217 netdev_err(fep->netdev, "MDIO address write timeout\n");
2218 goto out;
2219 }
2220
2221 /* start a write op */
2222 writel(frame_start | FEC_MMFR_OP_WRITE |
2223 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2224 FEC_MMFR_TA | FEC_MMFR_DATA(value),
2225 fep->hwp + FEC_MII_DATA);
2226
2227 /* wait for end of transfer */
2228 ret = fec_enet_mdio_wait(fep);
2229 if (ret)
2230 netdev_err(fep->netdev, "MDIO write timeout\n");
2231
2232out:
2233 pm_runtime_mark_last_busy(dev);
2234 pm_runtime_put_autosuspend(dev);
2235
2236 return ret;
2237}
2238
2239static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
2240{
2241 struct fec_enet_private *fep = netdev_priv(ndev);
2242 struct phy_device *phy_dev = ndev->phydev;
2243
2244 if (phy_dev) {
2245 phy_reset_after_clk_enable(phy_dev);
2246 } else if (fep->phy_node) {
2247 /*
2248 * If the PHY still is not bound to the MAC, but there is
2249 * OF PHY node and a matching PHY device instance already,
2250 * use the OF PHY node to obtain the PHY device instance,
2251 * and then use that PHY device instance when triggering
2252 * the PHY reset.
2253 */
2254 phy_dev = of_phy_find_device(fep->phy_node);
2255 phy_reset_after_clk_enable(phy_dev);
2256 put_device(&phy_dev->mdio.dev);
2257 }
2258}
2259
2260static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
2261{
2262 struct fec_enet_private *fep = netdev_priv(ndev);
2263 int ret;
2264
2265 if (enable) {
2266 ret = clk_prepare_enable(fep->clk_enet_out);
2267 if (ret)
2268 return ret;
2269
2270 if (fep->clk_ptp) {
2271 mutex_lock(&fep->ptp_clk_mutex);
2272 ret = clk_prepare_enable(fep->clk_ptp);
2273 if (ret) {
2274 mutex_unlock(&fep->ptp_clk_mutex);
2275 goto failed_clk_ptp;
2276 } else {
2277 fep->ptp_clk_on = true;
2278 }
2279 mutex_unlock(&fep->ptp_clk_mutex);
2280 }
2281
2282 ret = clk_prepare_enable(fep->clk_ref);
2283 if (ret)
2284 goto failed_clk_ref;
2285
2286 ret = clk_prepare_enable(fep->clk_2x_txclk);
2287 if (ret)
2288 goto failed_clk_2x_txclk;
2289
2290 fec_enet_phy_reset_after_clk_enable(ndev);
2291 } else {
2292 clk_disable_unprepare(fep->clk_enet_out);
2293 if (fep->clk_ptp) {
2294 mutex_lock(&fep->ptp_clk_mutex);
2295 clk_disable_unprepare(fep->clk_ptp);
2296 fep->ptp_clk_on = false;
2297 mutex_unlock(&fep->ptp_clk_mutex);
2298 }
2299 clk_disable_unprepare(fep->clk_ref);
2300 clk_disable_unprepare(fep->clk_2x_txclk);
2301 }
2302
2303 return 0;
2304
2305failed_clk_2x_txclk:
2306 if (fep->clk_ref)
2307 clk_disable_unprepare(fep->clk_ref);
2308failed_clk_ref:
2309 if (fep->clk_ptp) {
2310 mutex_lock(&fep->ptp_clk_mutex);
2311 clk_disable_unprepare(fep->clk_ptp);
2312 fep->ptp_clk_on = false;
2313 mutex_unlock(&fep->ptp_clk_mutex);
2314 }
2315failed_clk_ptp:
2316 clk_disable_unprepare(fep->clk_enet_out);
2317
2318 return ret;
2319}
2320
2321static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep,
2322 struct device_node *np)
2323{
2324 u32 rgmii_tx_delay, rgmii_rx_delay;
2325
2326 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */
2327 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) {
2328 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) {
2329 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps");
2330 return -EINVAL;
2331 } else if (rgmii_tx_delay == 2000) {
2332 fep->rgmii_txc_dly = true;
2333 }
2334 }
2335
2336 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */
2337 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) {
2338 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) {
2339 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps");
2340 return -EINVAL;
2341 } else if (rgmii_rx_delay == 2000) {
2342 fep->rgmii_rxc_dly = true;
2343 }
2344 }
2345
2346 return 0;
2347}
2348
2349static int fec_enet_mii_probe(struct net_device *ndev)
2350{
2351 struct fec_enet_private *fep = netdev_priv(ndev);
2352 struct phy_device *phy_dev = NULL;
2353 char mdio_bus_id[MII_BUS_ID_SIZE];
2354 char phy_name[MII_BUS_ID_SIZE + 3];
2355 int phy_id;
2356 int dev_id = fep->dev_id;
2357
2358 if (fep->phy_node) {
2359 phy_dev = of_phy_connect(ndev, fep->phy_node,
2360 &fec_enet_adjust_link, 0,
2361 fep->phy_interface);
2362 if (!phy_dev) {
2363 netdev_err(ndev, "Unable to connect to phy\n");
2364 return -ENODEV;
2365 }
2366 } else {
2367 /* check for attached phy */
2368 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
2369 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
2370 continue;
2371 if (dev_id--)
2372 continue;
2373 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
2374 break;
2375 }
2376
2377 if (phy_id >= PHY_MAX_ADDR) {
2378 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2379 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2380 phy_id = 0;
2381 }
2382
2383 snprintf(phy_name, sizeof(phy_name),
2384 PHY_ID_FMT, mdio_bus_id, phy_id);
2385 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2386 fep->phy_interface);
2387 }
2388
2389 if (IS_ERR(phy_dev)) {
2390 netdev_err(ndev, "could not attach to PHY\n");
2391 return PTR_ERR(phy_dev);
2392 }
2393
2394 /* mask with MAC supported features */
2395 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2396 phy_set_max_speed(phy_dev, 1000);
2397 phy_remove_link_mode(phy_dev,
2398 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
2399#if !defined(CONFIG_M5272)
2400 phy_support_sym_pause(phy_dev);
2401#endif
2402 }
2403 else
2404 phy_set_max_speed(phy_dev, 100);
2405
2406 fep->link = 0;
2407 fep->full_duplex = 0;
2408
2409 phy_dev->mac_managed_pm = true;
2410
2411 phy_attached_info(phy_dev);
2412
2413 return 0;
2414}
2415
2416static int fec_enet_mii_init(struct platform_device *pdev)
2417{
2418 static struct mii_bus *fec0_mii_bus;
2419 struct net_device *ndev = platform_get_drvdata(pdev);
2420 struct fec_enet_private *fep = netdev_priv(ndev);
2421 bool suppress_preamble = false;
2422 struct device_node *node;
2423 int err = -ENXIO;
2424 u32 mii_speed, holdtime;
2425 u32 bus_freq;
2426
2427 /*
2428 * The i.MX28 dual fec interfaces are not equal.
2429 * Here are the differences:
2430 *
2431 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2432 * - fec0 acts as the 1588 time master while fec1 is slave
2433 * - external phys can only be configured by fec0
2434 *
2435 * That is to say fec1 can not work independently. It only works
2436 * when fec0 is working. The reason behind this design is that the
2437 * second interface is added primarily for Switch mode.
2438 *
2439 * Because of the last point above, both phys are attached on fec0
2440 * mdio interface in board design, and need to be configured by
2441 * fec0 mii_bus.
2442 */
2443 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2444 /* fec1 uses fec0 mii_bus */
2445 if (mii_cnt && fec0_mii_bus) {
2446 fep->mii_bus = fec0_mii_bus;
2447 mii_cnt++;
2448 return 0;
2449 }
2450 return -ENOENT;
2451 }
2452
2453 bus_freq = 2500000; /* 2.5MHz by default */
2454 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2455 if (node) {
2456 of_property_read_u32(node, "clock-frequency", &bus_freq);
2457 suppress_preamble = of_property_read_bool(node,
2458 "suppress-preamble");
2459 }
2460
2461 /*
2462 * Set MII speed (= clk_get_rate() / 2 * phy_speed)
2463 *
2464 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2465 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2466 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2467 * document.
2468 */
2469 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2);
2470 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2471 mii_speed--;
2472 if (mii_speed > 63) {
2473 dev_err(&pdev->dev,
2474 "fec clock (%lu) too fast to get right mii speed\n",
2475 clk_get_rate(fep->clk_ipg));
2476 err = -EINVAL;
2477 goto err_out;
2478 }
2479
2480 /*
2481 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2482 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2483 * versions are RAZ there, so just ignore the difference and write the
2484 * register always.
2485 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2486 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2487 * output.
2488 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2489 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2490 * holdtime cannot result in a value greater than 3.
2491 */
2492 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2493
2494 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2495
2496 if (suppress_preamble)
2497 fep->phy_speed |= BIT(7);
2498
2499 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
2500 /* Clear MMFR to avoid to generate MII event by writing MSCR.
2501 * MII event generation condition:
2502 * - writing MSCR:
2503 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
2504 * mscr_reg_data_in[7:0] != 0
2505 * - writing MMFR:
2506 * - mscr[7:0]_not_zero
2507 */
2508 writel(0, fep->hwp + FEC_MII_DATA);
2509 }
2510
2511 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2512
2513 /* Clear any pending transaction complete indication */
2514 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2515
2516 fep->mii_bus = mdiobus_alloc();
2517 if (fep->mii_bus == NULL) {
2518 err = -ENOMEM;
2519 goto err_out;
2520 }
2521
2522 fep->mii_bus->name = "fec_enet_mii_bus";
2523 fep->mii_bus->read = fec_enet_mdio_read_c22;
2524 fep->mii_bus->write = fec_enet_mdio_write_c22;
2525 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) {
2526 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45;
2527 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45;
2528 }
2529 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2530 pdev->name, fep->dev_id + 1);
2531 fep->mii_bus->priv = fep;
2532 fep->mii_bus->parent = &pdev->dev;
2533
2534 err = of_mdiobus_register(fep->mii_bus, node);
2535 if (err)
2536 goto err_out_free_mdiobus;
2537 of_node_put(node);
2538
2539 mii_cnt++;
2540
2541 /* save fec0 mii_bus */
2542 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2543 fec0_mii_bus = fep->mii_bus;
2544
2545 return 0;
2546
2547err_out_free_mdiobus:
2548 mdiobus_free(fep->mii_bus);
2549err_out:
2550 of_node_put(node);
2551 return err;
2552}
2553
2554static void fec_enet_mii_remove(struct fec_enet_private *fep)
2555{
2556 if (--mii_cnt == 0) {
2557 mdiobus_unregister(fep->mii_bus);
2558 mdiobus_free(fep->mii_bus);
2559 }
2560}
2561
2562static void fec_enet_get_drvinfo(struct net_device *ndev,
2563 struct ethtool_drvinfo *info)
2564{
2565 struct fec_enet_private *fep = netdev_priv(ndev);
2566
2567 strscpy(info->driver, fep->pdev->dev.driver->name,
2568 sizeof(info->driver));
2569 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2570}
2571
2572static int fec_enet_get_regs_len(struct net_device *ndev)
2573{
2574 struct fec_enet_private *fep = netdev_priv(ndev);
2575 struct resource *r;
2576 int s = 0;
2577
2578 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2579 if (r)
2580 s = resource_size(r);
2581
2582 return s;
2583}
2584
2585/* List of registers that can be safety be read to dump them with ethtool */
2586#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2587 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2588 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2589static __u32 fec_enet_register_version = 2;
2590static u32 fec_enet_register_offset[] = {
2591 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2592 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2593 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2594 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2595 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2596 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2597 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2598 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2599 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2600 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2601 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2602 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2603 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2604 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2605 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2606 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2607 RMON_T_P_GTE2048, RMON_T_OCTETS,
2608 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2609 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2610 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2611 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2612 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2613 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2614 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2615 RMON_R_P_GTE2048, RMON_R_OCTETS,
2616 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2617 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2618};
2619/* for i.MX6ul */
2620static u32 fec_enet_register_offset_6ul[] = {
2621 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2622 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2623 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0,
2624 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH,
2625 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0,
2626 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2627 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC,
2628 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2629 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2630 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2631 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2632 RMON_T_P_GTE2048, RMON_T_OCTETS,
2633 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2634 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2635 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2636 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2637 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2638 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2639 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2640 RMON_R_P_GTE2048, RMON_R_OCTETS,
2641 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2642 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2643};
2644#else
2645static __u32 fec_enet_register_version = 1;
2646static u32 fec_enet_register_offset[] = {
2647 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2648 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2649 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2650 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2651 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2652 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2653 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2654 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2655 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2656};
2657#endif
2658
2659static void fec_enet_get_regs(struct net_device *ndev,
2660 struct ethtool_regs *regs, void *regbuf)
2661{
2662 struct fec_enet_private *fep = netdev_priv(ndev);
2663 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2664 struct device *dev = &fep->pdev->dev;
2665 u32 *buf = (u32 *)regbuf;
2666 u32 i, off;
2667 int ret;
2668#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2669 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2670 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2671 u32 *reg_list;
2672 u32 reg_cnt;
2673
2674 if (!of_machine_is_compatible("fsl,imx6ul")) {
2675 reg_list = fec_enet_register_offset;
2676 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2677 } else {
2678 reg_list = fec_enet_register_offset_6ul;
2679 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul);
2680 }
2681#else
2682 /* coldfire */
2683 static u32 *reg_list = fec_enet_register_offset;
2684 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2685#endif
2686 ret = pm_runtime_resume_and_get(dev);
2687 if (ret < 0)
2688 return;
2689
2690 regs->version = fec_enet_register_version;
2691
2692 memset(buf, 0, regs->len);
2693
2694 for (i = 0; i < reg_cnt; i++) {
2695 off = reg_list[i];
2696
2697 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2698 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2699 continue;
2700
2701 off >>= 2;
2702 buf[off] = readl(&theregs[off]);
2703 }
2704
2705 pm_runtime_mark_last_busy(dev);
2706 pm_runtime_put_autosuspend(dev);
2707}
2708
2709static int fec_enet_get_ts_info(struct net_device *ndev,
2710 struct ethtool_ts_info *info)
2711{
2712 struct fec_enet_private *fep = netdev_priv(ndev);
2713
2714 if (fep->bufdesc_ex) {
2715
2716 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2717 SOF_TIMESTAMPING_RX_SOFTWARE |
2718 SOF_TIMESTAMPING_SOFTWARE |
2719 SOF_TIMESTAMPING_TX_HARDWARE |
2720 SOF_TIMESTAMPING_RX_HARDWARE |
2721 SOF_TIMESTAMPING_RAW_HARDWARE;
2722 if (fep->ptp_clock)
2723 info->phc_index = ptp_clock_index(fep->ptp_clock);
2724 else
2725 info->phc_index = -1;
2726
2727 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2728 (1 << HWTSTAMP_TX_ON);
2729
2730 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2731 (1 << HWTSTAMP_FILTER_ALL);
2732 return 0;
2733 } else {
2734 return ethtool_op_get_ts_info(ndev, info);
2735 }
2736}
2737
2738#if !defined(CONFIG_M5272)
2739
2740static void fec_enet_get_pauseparam(struct net_device *ndev,
2741 struct ethtool_pauseparam *pause)
2742{
2743 struct fec_enet_private *fep = netdev_priv(ndev);
2744
2745 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2746 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2747 pause->rx_pause = pause->tx_pause;
2748}
2749
2750static int fec_enet_set_pauseparam(struct net_device *ndev,
2751 struct ethtool_pauseparam *pause)
2752{
2753 struct fec_enet_private *fep = netdev_priv(ndev);
2754
2755 if (!ndev->phydev)
2756 return -ENODEV;
2757
2758 if (pause->tx_pause != pause->rx_pause) {
2759 netdev_info(ndev,
2760 "hardware only support enable/disable both tx and rx");
2761 return -EINVAL;
2762 }
2763
2764 fep->pause_flag = 0;
2765
2766 /* tx pause must be same as rx pause */
2767 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2768 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2769
2770 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2771 pause->autoneg);
2772
2773 if (pause->autoneg) {
2774 if (netif_running(ndev))
2775 fec_stop(ndev);
2776 phy_start_aneg(ndev->phydev);
2777 }
2778 if (netif_running(ndev)) {
2779 napi_disable(&fep->napi);
2780 netif_tx_lock_bh(ndev);
2781 fec_restart(ndev);
2782 netif_tx_wake_all_queues(ndev);
2783 netif_tx_unlock_bh(ndev);
2784 napi_enable(&fep->napi);
2785 }
2786
2787 return 0;
2788}
2789
2790static const struct fec_stat {
2791 char name[ETH_GSTRING_LEN];
2792 u16 offset;
2793} fec_stats[] = {
2794 /* RMON TX */
2795 { "tx_dropped", RMON_T_DROP },
2796 { "tx_packets", RMON_T_PACKETS },
2797 { "tx_broadcast", RMON_T_BC_PKT },
2798 { "tx_multicast", RMON_T_MC_PKT },
2799 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2800 { "tx_undersize", RMON_T_UNDERSIZE },
2801 { "tx_oversize", RMON_T_OVERSIZE },
2802 { "tx_fragment", RMON_T_FRAG },
2803 { "tx_jabber", RMON_T_JAB },
2804 { "tx_collision", RMON_T_COL },
2805 { "tx_64byte", RMON_T_P64 },
2806 { "tx_65to127byte", RMON_T_P65TO127 },
2807 { "tx_128to255byte", RMON_T_P128TO255 },
2808 { "tx_256to511byte", RMON_T_P256TO511 },
2809 { "tx_512to1023byte", RMON_T_P512TO1023 },
2810 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2811 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2812 { "tx_octets", RMON_T_OCTETS },
2813
2814 /* IEEE TX */
2815 { "IEEE_tx_drop", IEEE_T_DROP },
2816 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2817 { "IEEE_tx_1col", IEEE_T_1COL },
2818 { "IEEE_tx_mcol", IEEE_T_MCOL },
2819 { "IEEE_tx_def", IEEE_T_DEF },
2820 { "IEEE_tx_lcol", IEEE_T_LCOL },
2821 { "IEEE_tx_excol", IEEE_T_EXCOL },
2822 { "IEEE_tx_macerr", IEEE_T_MACERR },
2823 { "IEEE_tx_cserr", IEEE_T_CSERR },
2824 { "IEEE_tx_sqe", IEEE_T_SQE },
2825 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2826 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2827
2828 /* RMON RX */
2829 { "rx_packets", RMON_R_PACKETS },
2830 { "rx_broadcast", RMON_R_BC_PKT },
2831 { "rx_multicast", RMON_R_MC_PKT },
2832 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2833 { "rx_undersize", RMON_R_UNDERSIZE },
2834 { "rx_oversize", RMON_R_OVERSIZE },
2835 { "rx_fragment", RMON_R_FRAG },
2836 { "rx_jabber", RMON_R_JAB },
2837 { "rx_64byte", RMON_R_P64 },
2838 { "rx_65to127byte", RMON_R_P65TO127 },
2839 { "rx_128to255byte", RMON_R_P128TO255 },
2840 { "rx_256to511byte", RMON_R_P256TO511 },
2841 { "rx_512to1023byte", RMON_R_P512TO1023 },
2842 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2843 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2844 { "rx_octets", RMON_R_OCTETS },
2845
2846 /* IEEE RX */
2847 { "IEEE_rx_drop", IEEE_R_DROP },
2848 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2849 { "IEEE_rx_crc", IEEE_R_CRC },
2850 { "IEEE_rx_align", IEEE_R_ALIGN },
2851 { "IEEE_rx_macerr", IEEE_R_MACERR },
2852 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2853 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2854};
2855
2856#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2857
2858static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = {
2859 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */
2860 "rx_xdp_pass", /* RX_XDP_PASS, */
2861 "rx_xdp_drop", /* RX_XDP_DROP, */
2862 "rx_xdp_tx", /* RX_XDP_TX, */
2863 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */
2864 "tx_xdp_xmit", /* TX_XDP_XMIT, */
2865 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */
2866};
2867
2868static void fec_enet_update_ethtool_stats(struct net_device *dev)
2869{
2870 struct fec_enet_private *fep = netdev_priv(dev);
2871 int i;
2872
2873 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2874 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2875}
2876
2877static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data)
2878{
2879 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 };
2880 struct fec_enet_priv_rx_q *rxq;
2881 int i, j;
2882
2883 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2884 rxq = fep->rx_queue[i];
2885
2886 for (j = 0; j < XDP_STATS_TOTAL; j++)
2887 xdp_stats[j] += rxq->stats[j];
2888 }
2889
2890 memcpy(data, xdp_stats, sizeof(xdp_stats));
2891}
2892
2893static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data)
2894{
2895#ifdef CONFIG_PAGE_POOL_STATS
2896 struct page_pool_stats stats = {};
2897 struct fec_enet_priv_rx_q *rxq;
2898 int i;
2899
2900 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2901 rxq = fep->rx_queue[i];
2902
2903 if (!rxq->page_pool)
2904 continue;
2905
2906 page_pool_get_stats(rxq->page_pool, &stats);
2907 }
2908
2909 page_pool_ethtool_stats_get(data, &stats);
2910#endif
2911}
2912
2913static void fec_enet_get_ethtool_stats(struct net_device *dev,
2914 struct ethtool_stats *stats, u64 *data)
2915{
2916 struct fec_enet_private *fep = netdev_priv(dev);
2917
2918 if (netif_running(dev))
2919 fec_enet_update_ethtool_stats(dev);
2920
2921 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2922 data += FEC_STATS_SIZE / sizeof(u64);
2923
2924 fec_enet_get_xdp_stats(fep, data);
2925 data += XDP_STATS_TOTAL;
2926
2927 fec_enet_page_pool_stats(fep, data);
2928}
2929
2930static void fec_enet_get_strings(struct net_device *netdev,
2931 u32 stringset, u8 *data)
2932{
2933 int i;
2934 switch (stringset) {
2935 case ETH_SS_STATS:
2936 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) {
2937 ethtool_puts(&data, fec_stats[i].name);
2938 }
2939 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) {
2940 ethtool_puts(&data, fec_xdp_stat_strs[i]);
2941 }
2942 page_pool_ethtool_stats_get_strings(data);
2943
2944 break;
2945 case ETH_SS_TEST:
2946 net_selftest_get_strings(data);
2947 break;
2948 }
2949}
2950
2951static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2952{
2953 int count;
2954
2955 switch (sset) {
2956 case ETH_SS_STATS:
2957 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL;
2958 count += page_pool_ethtool_stats_get_count();
2959 return count;
2960
2961 case ETH_SS_TEST:
2962 return net_selftest_get_count();
2963 default:
2964 return -EOPNOTSUPP;
2965 }
2966}
2967
2968static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2969{
2970 struct fec_enet_private *fep = netdev_priv(dev);
2971 struct fec_enet_priv_rx_q *rxq;
2972 int i, j;
2973
2974 /* Disable MIB statistics counters */
2975 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2976
2977 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2978 writel(0, fep->hwp + fec_stats[i].offset);
2979
2980 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2981 rxq = fep->rx_queue[i];
2982 for (j = 0; j < XDP_STATS_TOTAL; j++)
2983 rxq->stats[j] = 0;
2984 }
2985
2986 /* Don't disable MIB statistics counters */
2987 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2988}
2989
2990#else /* !defined(CONFIG_M5272) */
2991#define FEC_STATS_SIZE 0
2992static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2993{
2994}
2995
2996static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2997{
2998}
2999#endif /* !defined(CONFIG_M5272) */
3000
3001/* ITR clock source is enet system clock (clk_ahb).
3002 * TCTT unit is cycle_ns * 64 cycle
3003 * So, the ICTT value = X us / (cycle_ns * 64)
3004 */
3005static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
3006{
3007 struct fec_enet_private *fep = netdev_priv(ndev);
3008
3009 return us * (fep->itr_clk_rate / 64000) / 1000;
3010}
3011
3012/* Set threshold for interrupt coalescing */
3013static void fec_enet_itr_coal_set(struct net_device *ndev)
3014{
3015 struct fec_enet_private *fep = netdev_priv(ndev);
3016 int rx_itr, tx_itr;
3017
3018 /* Must be greater than zero to avoid unpredictable behavior */
3019 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
3020 !fep->tx_time_itr || !fep->tx_pkts_itr)
3021 return;
3022
3023 /* Select enet system clock as Interrupt Coalescing
3024 * timer Clock Source
3025 */
3026 rx_itr = FEC_ITR_CLK_SEL;
3027 tx_itr = FEC_ITR_CLK_SEL;
3028
3029 /* set ICFT and ICTT */
3030 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
3031 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
3032 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
3033 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
3034
3035 rx_itr |= FEC_ITR_EN;
3036 tx_itr |= FEC_ITR_EN;
3037
3038 writel(tx_itr, fep->hwp + FEC_TXIC0);
3039 writel(rx_itr, fep->hwp + FEC_RXIC0);
3040 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
3041 writel(tx_itr, fep->hwp + FEC_TXIC1);
3042 writel(rx_itr, fep->hwp + FEC_RXIC1);
3043 writel(tx_itr, fep->hwp + FEC_TXIC2);
3044 writel(rx_itr, fep->hwp + FEC_RXIC2);
3045 }
3046}
3047
3048static int fec_enet_get_coalesce(struct net_device *ndev,
3049 struct ethtool_coalesce *ec,
3050 struct kernel_ethtool_coalesce *kernel_coal,
3051 struct netlink_ext_ack *extack)
3052{
3053 struct fec_enet_private *fep = netdev_priv(ndev);
3054
3055 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3056 return -EOPNOTSUPP;
3057
3058 ec->rx_coalesce_usecs = fep->rx_time_itr;
3059 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
3060
3061 ec->tx_coalesce_usecs = fep->tx_time_itr;
3062 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
3063
3064 return 0;
3065}
3066
3067static int fec_enet_set_coalesce(struct net_device *ndev,
3068 struct ethtool_coalesce *ec,
3069 struct kernel_ethtool_coalesce *kernel_coal,
3070 struct netlink_ext_ack *extack)
3071{
3072 struct fec_enet_private *fep = netdev_priv(ndev);
3073 struct device *dev = &fep->pdev->dev;
3074 unsigned int cycle;
3075
3076 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3077 return -EOPNOTSUPP;
3078
3079 if (ec->rx_max_coalesced_frames > 255) {
3080 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
3081 return -EINVAL;
3082 }
3083
3084 if (ec->tx_max_coalesced_frames > 255) {
3085 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
3086 return -EINVAL;
3087 }
3088
3089 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
3090 if (cycle > 0xFFFF) {
3091 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
3092 return -EINVAL;
3093 }
3094
3095 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
3096 if (cycle > 0xFFFF) {
3097 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
3098 return -EINVAL;
3099 }
3100
3101 fep->rx_time_itr = ec->rx_coalesce_usecs;
3102 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
3103
3104 fep->tx_time_itr = ec->tx_coalesce_usecs;
3105 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
3106
3107 fec_enet_itr_coal_set(ndev);
3108
3109 return 0;
3110}
3111
3112/* LPI Sleep Ts count base on tx clk (clk_ref).
3113 * The lpi sleep cnt value = X us / (cycle_ns).
3114 */
3115static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us)
3116{
3117 struct fec_enet_private *fep = netdev_priv(ndev);
3118
3119 return us * (fep->clk_ref_rate / 1000) / 1000;
3120}
3121
3122static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable)
3123{
3124 struct fec_enet_private *fep = netdev_priv(ndev);
3125 struct ethtool_eee *p = &fep->eee;
3126 unsigned int sleep_cycle, wake_cycle;
3127 int ret = 0;
3128
3129 if (enable) {
3130 ret = phy_init_eee(ndev->phydev, false);
3131 if (ret)
3132 return ret;
3133
3134 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer);
3135 wake_cycle = sleep_cycle;
3136 } else {
3137 sleep_cycle = 0;
3138 wake_cycle = 0;
3139 }
3140
3141 p->tx_lpi_enabled = enable;
3142 p->eee_enabled = enable;
3143 p->eee_active = enable;
3144
3145 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP);
3146 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE);
3147
3148 return 0;
3149}
3150
3151static int
3152fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
3153{
3154 struct fec_enet_private *fep = netdev_priv(ndev);
3155 struct ethtool_eee *p = &fep->eee;
3156
3157 if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3158 return -EOPNOTSUPP;
3159
3160 if (!netif_running(ndev))
3161 return -ENETDOWN;
3162
3163 edata->eee_enabled = p->eee_enabled;
3164 edata->eee_active = p->eee_active;
3165 edata->tx_lpi_timer = p->tx_lpi_timer;
3166 edata->tx_lpi_enabled = p->tx_lpi_enabled;
3167
3168 return phy_ethtool_get_eee(ndev->phydev, edata);
3169}
3170
3171static int
3172fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
3173{
3174 struct fec_enet_private *fep = netdev_priv(ndev);
3175 struct ethtool_eee *p = &fep->eee;
3176 int ret = 0;
3177
3178 if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3179 return -EOPNOTSUPP;
3180
3181 if (!netif_running(ndev))
3182 return -ENETDOWN;
3183
3184 p->tx_lpi_timer = edata->tx_lpi_timer;
3185
3186 if (!edata->eee_enabled || !edata->tx_lpi_enabled ||
3187 !edata->tx_lpi_timer)
3188 ret = fec_enet_eee_mode_set(ndev, false);
3189 else
3190 ret = fec_enet_eee_mode_set(ndev, true);
3191
3192 if (ret)
3193 return ret;
3194
3195 return phy_ethtool_set_eee(ndev->phydev, edata);
3196}
3197
3198static void
3199fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3200{
3201 struct fec_enet_private *fep = netdev_priv(ndev);
3202
3203 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
3204 wol->supported = WAKE_MAGIC;
3205 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
3206 } else {
3207 wol->supported = wol->wolopts = 0;
3208 }
3209}
3210
3211static int
3212fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3213{
3214 struct fec_enet_private *fep = netdev_priv(ndev);
3215
3216 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
3217 return -EINVAL;
3218
3219 if (wol->wolopts & ~WAKE_MAGIC)
3220 return -EINVAL;
3221
3222 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
3223 if (device_may_wakeup(&ndev->dev))
3224 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
3225 else
3226 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
3227
3228 return 0;
3229}
3230
3231static const struct ethtool_ops fec_enet_ethtool_ops = {
3232 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3233 ETHTOOL_COALESCE_MAX_FRAMES,
3234 .get_drvinfo = fec_enet_get_drvinfo,
3235 .get_regs_len = fec_enet_get_regs_len,
3236 .get_regs = fec_enet_get_regs,
3237 .nway_reset = phy_ethtool_nway_reset,
3238 .get_link = ethtool_op_get_link,
3239 .get_coalesce = fec_enet_get_coalesce,
3240 .set_coalesce = fec_enet_set_coalesce,
3241#ifndef CONFIG_M5272
3242 .get_pauseparam = fec_enet_get_pauseparam,
3243 .set_pauseparam = fec_enet_set_pauseparam,
3244 .get_strings = fec_enet_get_strings,
3245 .get_ethtool_stats = fec_enet_get_ethtool_stats,
3246 .get_sset_count = fec_enet_get_sset_count,
3247#endif
3248 .get_ts_info = fec_enet_get_ts_info,
3249 .get_wol = fec_enet_get_wol,
3250 .set_wol = fec_enet_set_wol,
3251 .get_eee = fec_enet_get_eee,
3252 .set_eee = fec_enet_set_eee,
3253 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3254 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3255 .self_test = net_selftest,
3256};
3257
3258static void fec_enet_free_buffers(struct net_device *ndev)
3259{
3260 struct fec_enet_private *fep = netdev_priv(ndev);
3261 unsigned int i;
3262 struct fec_enet_priv_tx_q *txq;
3263 struct fec_enet_priv_rx_q *rxq;
3264 unsigned int q;
3265
3266 for (q = 0; q < fep->num_rx_queues; q++) {
3267 rxq = fep->rx_queue[q];
3268 for (i = 0; i < rxq->bd.ring_size; i++)
3269 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false);
3270
3271 for (i = 0; i < XDP_STATS_TOTAL; i++)
3272 rxq->stats[i] = 0;
3273
3274 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
3275 xdp_rxq_info_unreg(&rxq->xdp_rxq);
3276 page_pool_destroy(rxq->page_pool);
3277 rxq->page_pool = NULL;
3278 }
3279
3280 for (q = 0; q < fep->num_tx_queues; q++) {
3281 txq = fep->tx_queue[q];
3282 for (i = 0; i < txq->bd.ring_size; i++) {
3283 kfree(txq->tx_bounce[i]);
3284 txq->tx_bounce[i] = NULL;
3285
3286 if (!txq->tx_buf[i].buf_p) {
3287 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3288 continue;
3289 }
3290
3291 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
3292 dev_kfree_skb(txq->tx_buf[i].buf_p);
3293 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) {
3294 xdp_return_frame(txq->tx_buf[i].buf_p);
3295 } else {
3296 struct page *page = txq->tx_buf[i].buf_p;
3297
3298 page_pool_put_page(page->pp, page, 0, false);
3299 }
3300
3301 txq->tx_buf[i].buf_p = NULL;
3302 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3303 }
3304 }
3305}
3306
3307static void fec_enet_free_queue(struct net_device *ndev)
3308{
3309 struct fec_enet_private *fep = netdev_priv(ndev);
3310 int i;
3311 struct fec_enet_priv_tx_q *txq;
3312
3313 for (i = 0; i < fep->num_tx_queues; i++)
3314 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
3315 txq = fep->tx_queue[i];
3316 fec_dma_free(&fep->pdev->dev,
3317 txq->bd.ring_size * TSO_HEADER_SIZE,
3318 txq->tso_hdrs, txq->tso_hdrs_dma);
3319 }
3320
3321 for (i = 0; i < fep->num_rx_queues; i++)
3322 kfree(fep->rx_queue[i]);
3323 for (i = 0; i < fep->num_tx_queues; i++)
3324 kfree(fep->tx_queue[i]);
3325}
3326
3327static int fec_enet_alloc_queue(struct net_device *ndev)
3328{
3329 struct fec_enet_private *fep = netdev_priv(ndev);
3330 int i;
3331 int ret = 0;
3332 struct fec_enet_priv_tx_q *txq;
3333
3334 for (i = 0; i < fep->num_tx_queues; i++) {
3335 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
3336 if (!txq) {
3337 ret = -ENOMEM;
3338 goto alloc_failed;
3339 }
3340
3341 fep->tx_queue[i] = txq;
3342 txq->bd.ring_size = TX_RING_SIZE;
3343 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
3344
3345 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
3346 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS;
3347
3348 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev,
3349 txq->bd.ring_size * TSO_HEADER_SIZE,
3350 &txq->tso_hdrs_dma, GFP_KERNEL);
3351 if (!txq->tso_hdrs) {
3352 ret = -ENOMEM;
3353 goto alloc_failed;
3354 }
3355 }
3356
3357 for (i = 0; i < fep->num_rx_queues; i++) {
3358 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
3359 GFP_KERNEL);
3360 if (!fep->rx_queue[i]) {
3361 ret = -ENOMEM;
3362 goto alloc_failed;
3363 }
3364
3365 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
3366 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
3367 }
3368 return ret;
3369
3370alloc_failed:
3371 fec_enet_free_queue(ndev);
3372 return ret;
3373}
3374
3375static int
3376fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
3377{
3378 struct fec_enet_private *fep = netdev_priv(ndev);
3379 struct fec_enet_priv_rx_q *rxq;
3380 dma_addr_t phys_addr;
3381 struct bufdesc *bdp;
3382 struct page *page;
3383 int i, err;
3384
3385 rxq = fep->rx_queue[queue];
3386 bdp = rxq->bd.base;
3387
3388 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size);
3389 if (err < 0) {
3390 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err);
3391 return err;
3392 }
3393
3394 for (i = 0; i < rxq->bd.ring_size; i++) {
3395 page = page_pool_dev_alloc_pages(rxq->page_pool);
3396 if (!page)
3397 goto err_alloc;
3398
3399 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM;
3400 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
3401
3402 rxq->rx_skb_info[i].page = page;
3403 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM;
3404 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
3405
3406 if (fep->bufdesc_ex) {
3407 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3408 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
3409 }
3410
3411 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
3412 }
3413
3414 /* Set the last buffer to wrap. */
3415 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
3416 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3417 return 0;
3418
3419 err_alloc:
3420 fec_enet_free_buffers(ndev);
3421 return -ENOMEM;
3422}
3423
3424static int
3425fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
3426{
3427 struct fec_enet_private *fep = netdev_priv(ndev);
3428 unsigned int i;
3429 struct bufdesc *bdp;
3430 struct fec_enet_priv_tx_q *txq;
3431
3432 txq = fep->tx_queue[queue];
3433 bdp = txq->bd.base;
3434 for (i = 0; i < txq->bd.ring_size; i++) {
3435 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
3436 if (!txq->tx_bounce[i])
3437 goto err_alloc;
3438
3439 bdp->cbd_sc = cpu_to_fec16(0);
3440 bdp->cbd_bufaddr = cpu_to_fec32(0);
3441
3442 if (fep->bufdesc_ex) {
3443 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3444 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
3445 }
3446
3447 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3448 }
3449
3450 /* Set the last buffer to wrap. */
3451 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
3452 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3453
3454 return 0;
3455
3456 err_alloc:
3457 fec_enet_free_buffers(ndev);
3458 return -ENOMEM;
3459}
3460
3461static int fec_enet_alloc_buffers(struct net_device *ndev)
3462{
3463 struct fec_enet_private *fep = netdev_priv(ndev);
3464 unsigned int i;
3465
3466 for (i = 0; i < fep->num_rx_queues; i++)
3467 if (fec_enet_alloc_rxq_buffers(ndev, i))
3468 return -ENOMEM;
3469
3470 for (i = 0; i < fep->num_tx_queues; i++)
3471 if (fec_enet_alloc_txq_buffers(ndev, i))
3472 return -ENOMEM;
3473 return 0;
3474}
3475
3476static int
3477fec_enet_open(struct net_device *ndev)
3478{
3479 struct fec_enet_private *fep = netdev_priv(ndev);
3480 int ret;
3481 bool reset_again;
3482
3483 ret = pm_runtime_resume_and_get(&fep->pdev->dev);
3484 if (ret < 0)
3485 return ret;
3486
3487 pinctrl_pm_select_default_state(&fep->pdev->dev);
3488 ret = fec_enet_clk_enable(ndev, true);
3489 if (ret)
3490 goto clk_enable;
3491
3492 /* During the first fec_enet_open call the PHY isn't probed at this
3493 * point. Therefore the phy_reset_after_clk_enable() call within
3494 * fec_enet_clk_enable() fails. As we need this reset in order to be
3495 * sure the PHY is working correctly we check if we need to reset again
3496 * later when the PHY is probed
3497 */
3498 if (ndev->phydev && ndev->phydev->drv)
3499 reset_again = false;
3500 else
3501 reset_again = true;
3502
3503 /* I should reset the ring buffers here, but I don't yet know
3504 * a simple way to do that.
3505 */
3506
3507 ret = fec_enet_alloc_buffers(ndev);
3508 if (ret)
3509 goto err_enet_alloc;
3510
3511 /* Init MAC prior to mii bus probe */
3512 fec_restart(ndev);
3513
3514 /* Call phy_reset_after_clk_enable() again if it failed during
3515 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
3516 */
3517 if (reset_again)
3518 fec_enet_phy_reset_after_clk_enable(ndev);
3519
3520 /* Probe and connect to PHY when open the interface */
3521 ret = fec_enet_mii_probe(ndev);
3522 if (ret)
3523 goto err_enet_mii_probe;
3524
3525 if (fep->quirks & FEC_QUIRK_ERR006687)
3526 imx6q_cpuidle_fec_irqs_used();
3527
3528 if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3529 cpu_latency_qos_add_request(&fep->pm_qos_req, 0);
3530
3531 napi_enable(&fep->napi);
3532 phy_start(ndev->phydev);
3533 netif_tx_start_all_queues(ndev);
3534
3535 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
3536 FEC_WOL_FLAG_ENABLE);
3537
3538 return 0;
3539
3540err_enet_mii_probe:
3541 fec_enet_free_buffers(ndev);
3542err_enet_alloc:
3543 fec_enet_clk_enable(ndev, false);
3544clk_enable:
3545 pm_runtime_mark_last_busy(&fep->pdev->dev);
3546 pm_runtime_put_autosuspend(&fep->pdev->dev);
3547 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3548 return ret;
3549}
3550
3551static int
3552fec_enet_close(struct net_device *ndev)
3553{
3554 struct fec_enet_private *fep = netdev_priv(ndev);
3555
3556 phy_stop(ndev->phydev);
3557
3558 if (netif_device_present(ndev)) {
3559 napi_disable(&fep->napi);
3560 netif_tx_disable(ndev);
3561 fec_stop(ndev);
3562 }
3563
3564 phy_disconnect(ndev->phydev);
3565
3566 if (fep->quirks & FEC_QUIRK_ERR006687)
3567 imx6q_cpuidle_fec_irqs_unused();
3568
3569 fec_enet_update_ethtool_stats(ndev);
3570
3571 fec_enet_clk_enable(ndev, false);
3572 if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3573 cpu_latency_qos_remove_request(&fep->pm_qos_req);
3574
3575 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3576 pm_runtime_mark_last_busy(&fep->pdev->dev);
3577 pm_runtime_put_autosuspend(&fep->pdev->dev);
3578
3579 fec_enet_free_buffers(ndev);
3580
3581 return 0;
3582}
3583
3584/* Set or clear the multicast filter for this adaptor.
3585 * Skeleton taken from sunlance driver.
3586 * The CPM Ethernet implementation allows Multicast as well as individual
3587 * MAC address filtering. Some of the drivers check to make sure it is
3588 * a group multicast address, and discard those that are not. I guess I
3589 * will do the same for now, but just remove the test if you want
3590 * individual filtering as well (do the upper net layers want or support
3591 * this kind of feature?).
3592 */
3593
3594#define FEC_HASH_BITS 6 /* #bits in hash */
3595
3596static void set_multicast_list(struct net_device *ndev)
3597{
3598 struct fec_enet_private *fep = netdev_priv(ndev);
3599 struct netdev_hw_addr *ha;
3600 unsigned int crc, tmp;
3601 unsigned char hash;
3602 unsigned int hash_high = 0, hash_low = 0;
3603
3604 if (ndev->flags & IFF_PROMISC) {
3605 tmp = readl(fep->hwp + FEC_R_CNTRL);
3606 tmp |= 0x8;
3607 writel(tmp, fep->hwp + FEC_R_CNTRL);
3608 return;
3609 }
3610
3611 tmp = readl(fep->hwp + FEC_R_CNTRL);
3612 tmp &= ~0x8;
3613 writel(tmp, fep->hwp + FEC_R_CNTRL);
3614
3615 if (ndev->flags & IFF_ALLMULTI) {
3616 /* Catch all multicast addresses, so set the
3617 * filter to all 1's
3618 */
3619 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3620 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3621
3622 return;
3623 }
3624
3625 /* Add the addresses in hash register */
3626 netdev_for_each_mc_addr(ha, ndev) {
3627 /* calculate crc32 value of mac address */
3628 crc = ether_crc_le(ndev->addr_len, ha->addr);
3629
3630 /* only upper 6 bits (FEC_HASH_BITS) are used
3631 * which point to specific bit in the hash registers
3632 */
3633 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3634
3635 if (hash > 31)
3636 hash_high |= 1 << (hash - 32);
3637 else
3638 hash_low |= 1 << hash;
3639 }
3640
3641 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3642 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3643}
3644
3645/* Set a MAC change in hardware. */
3646static int
3647fec_set_mac_address(struct net_device *ndev, void *p)
3648{
3649 struct fec_enet_private *fep = netdev_priv(ndev);
3650 struct sockaddr *addr = p;
3651
3652 if (addr) {
3653 if (!is_valid_ether_addr(addr->sa_data))
3654 return -EADDRNOTAVAIL;
3655 eth_hw_addr_set(ndev, addr->sa_data);
3656 }
3657
3658 /* Add netif status check here to avoid system hang in below case:
3659 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3660 * After ethx down, fec all clocks are gated off and then register
3661 * access causes system hang.
3662 */
3663 if (!netif_running(ndev))
3664 return 0;
3665
3666 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3667 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3668 fep->hwp + FEC_ADDR_LOW);
3669 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3670 fep->hwp + FEC_ADDR_HIGH);
3671 return 0;
3672}
3673
3674#ifdef CONFIG_NET_POLL_CONTROLLER
3675/**
3676 * fec_poll_controller - FEC Poll controller function
3677 * @dev: The FEC network adapter
3678 *
3679 * Polled functionality used by netconsole and others in non interrupt mode
3680 *
3681 */
3682static void fec_poll_controller(struct net_device *dev)
3683{
3684 int i;
3685 struct fec_enet_private *fep = netdev_priv(dev);
3686
3687 for (i = 0; i < FEC_IRQ_NUM; i++) {
3688 if (fep->irq[i] > 0) {
3689 disable_irq(fep->irq[i]);
3690 fec_enet_interrupt(fep->irq[i], dev);
3691 enable_irq(fep->irq[i]);
3692 }
3693 }
3694}
3695#endif
3696
3697static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3698 netdev_features_t features)
3699{
3700 struct fec_enet_private *fep = netdev_priv(netdev);
3701 netdev_features_t changed = features ^ netdev->features;
3702
3703 netdev->features = features;
3704
3705 /* Receive checksum has been changed */
3706 if (changed & NETIF_F_RXCSUM) {
3707 if (features & NETIF_F_RXCSUM)
3708 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3709 else
3710 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3711 }
3712}
3713
3714static int fec_set_features(struct net_device *netdev,
3715 netdev_features_t features)
3716{
3717 struct fec_enet_private *fep = netdev_priv(netdev);
3718 netdev_features_t changed = features ^ netdev->features;
3719
3720 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3721 napi_disable(&fep->napi);
3722 netif_tx_lock_bh(netdev);
3723 fec_stop(netdev);
3724 fec_enet_set_netdev_features(netdev, features);
3725 fec_restart(netdev);
3726 netif_tx_wake_all_queues(netdev);
3727 netif_tx_unlock_bh(netdev);
3728 napi_enable(&fep->napi);
3729 } else {
3730 fec_enet_set_netdev_features(netdev, features);
3731 }
3732
3733 return 0;
3734}
3735
3736static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
3737 struct net_device *sb_dev)
3738{
3739 struct fec_enet_private *fep = netdev_priv(ndev);
3740 u16 vlan_tag = 0;
3741
3742 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
3743 return netdev_pick_tx(ndev, skb, NULL);
3744
3745 /* VLAN is present in the payload.*/
3746 if (eth_type_vlan(skb->protocol)) {
3747 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb);
3748
3749 vlan_tag = ntohs(vhdr->h_vlan_TCI);
3750 /* VLAN is present in the skb but not yet pushed in the payload.*/
3751 } else if (skb_vlan_tag_present(skb)) {
3752 vlan_tag = skb->vlan_tci;
3753 } else {
3754 return vlan_tag;
3755 }
3756
3757 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
3758}
3759
3760static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf)
3761{
3762 struct fec_enet_private *fep = netdev_priv(dev);
3763 bool is_run = netif_running(dev);
3764 struct bpf_prog *old_prog;
3765
3766 switch (bpf->command) {
3767 case XDP_SETUP_PROG:
3768 /* No need to support the SoCs that require to
3769 * do the frame swap because the performance wouldn't be
3770 * better than the skb mode.
3771 */
3772 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
3773 return -EOPNOTSUPP;
3774
3775 if (!bpf->prog)
3776 xdp_features_clear_redirect_target(dev);
3777
3778 if (is_run) {
3779 napi_disable(&fep->napi);
3780 netif_tx_disable(dev);
3781 }
3782
3783 old_prog = xchg(&fep->xdp_prog, bpf->prog);
3784 if (old_prog)
3785 bpf_prog_put(old_prog);
3786
3787 fec_restart(dev);
3788
3789 if (is_run) {
3790 napi_enable(&fep->napi);
3791 netif_tx_start_all_queues(dev);
3792 }
3793
3794 if (bpf->prog)
3795 xdp_features_set_redirect_target(dev, false);
3796
3797 return 0;
3798
3799 case XDP_SETUP_XSK_POOL:
3800 return -EOPNOTSUPP;
3801
3802 default:
3803 return -EOPNOTSUPP;
3804 }
3805}
3806
3807static int
3808fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index)
3809{
3810 if (unlikely(index < 0))
3811 return 0;
3812
3813 return (index % fep->num_tx_queues);
3814}
3815
3816static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep,
3817 struct fec_enet_priv_tx_q *txq,
3818 void *frame, u32 dma_sync_len,
3819 bool ndo_xmit)
3820{
3821 unsigned int index, status, estatus;
3822 struct bufdesc *bdp;
3823 dma_addr_t dma_addr;
3824 int entries_free;
3825 u16 frame_len;
3826
3827 entries_free = fec_enet_get_free_txdesc_num(txq);
3828 if (entries_free < MAX_SKB_FRAGS + 1) {
3829 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n");
3830 return -EBUSY;
3831 }
3832
3833 /* Fill in a Tx ring entry */
3834 bdp = txq->bd.cur;
3835 status = fec16_to_cpu(bdp->cbd_sc);
3836 status &= ~BD_ENET_TX_STATS;
3837
3838 index = fec_enet_get_bd_index(bdp, &txq->bd);
3839
3840 if (ndo_xmit) {
3841 struct xdp_frame *xdpf = frame;
3842
3843 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data,
3844 xdpf->len, DMA_TO_DEVICE);
3845 if (dma_mapping_error(&fep->pdev->dev, dma_addr))
3846 return -ENOMEM;
3847
3848 frame_len = xdpf->len;
3849 txq->tx_buf[index].buf_p = xdpf;
3850 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO;
3851 } else {
3852 struct xdp_buff *xdpb = frame;
3853 struct page *page;
3854
3855 page = virt_to_page(xdpb->data);
3856 dma_addr = page_pool_get_dma_addr(page) +
3857 (xdpb->data - xdpb->data_hard_start);
3858 dma_sync_single_for_device(&fep->pdev->dev, dma_addr,
3859 dma_sync_len, DMA_BIDIRECTIONAL);
3860 frame_len = xdpb->data_end - xdpb->data;
3861 txq->tx_buf[index].buf_p = page;
3862 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX;
3863 }
3864
3865 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
3866 if (fep->bufdesc_ex)
3867 estatus = BD_ENET_TX_INT;
3868
3869 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr);
3870 bdp->cbd_datlen = cpu_to_fec16(frame_len);
3871
3872 if (fep->bufdesc_ex) {
3873 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3874
3875 if (fep->quirks & FEC_QUIRK_HAS_AVB)
3876 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
3877
3878 ebdp->cbd_bdu = 0;
3879 ebdp->cbd_esc = cpu_to_fec32(estatus);
3880 }
3881
3882 /* Make sure the updates to rest of the descriptor are performed before
3883 * transferring ownership.
3884 */
3885 dma_wmb();
3886
3887 /* Send it on its way. Tell FEC it's ready, interrupt when done,
3888 * it's the last BD of the frame, and to put the CRC on the end.
3889 */
3890 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
3891 bdp->cbd_sc = cpu_to_fec16(status);
3892
3893 /* If this was the last BD in the ring, start at the beginning again. */
3894 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3895
3896 /* Make sure the update to bdp are performed before txq->bd.cur. */
3897 dma_wmb();
3898
3899 txq->bd.cur = bdp;
3900
3901 /* Trigger transmission start */
3902 writel(0, txq->bd.reg_desc_active);
3903
3904 return 0;
3905}
3906
3907static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
3908 int cpu, struct xdp_buff *xdp,
3909 u32 dma_sync_len)
3910{
3911 struct fec_enet_priv_tx_q *txq;
3912 struct netdev_queue *nq;
3913 int queue, ret;
3914
3915 queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3916 txq = fep->tx_queue[queue];
3917 nq = netdev_get_tx_queue(fep->netdev, queue);
3918
3919 __netif_tx_lock(nq, cpu);
3920
3921 /* Avoid tx timeout as XDP shares the queue with kernel stack */
3922 txq_trans_cond_update(nq);
3923 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false);
3924
3925 __netif_tx_unlock(nq);
3926
3927 return ret;
3928}
3929
3930static int fec_enet_xdp_xmit(struct net_device *dev,
3931 int num_frames,
3932 struct xdp_frame **frames,
3933 u32 flags)
3934{
3935 struct fec_enet_private *fep = netdev_priv(dev);
3936 struct fec_enet_priv_tx_q *txq;
3937 int cpu = smp_processor_id();
3938 unsigned int sent_frames = 0;
3939 struct netdev_queue *nq;
3940 unsigned int queue;
3941 int i;
3942
3943 queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3944 txq = fep->tx_queue[queue];
3945 nq = netdev_get_tx_queue(fep->netdev, queue);
3946
3947 __netif_tx_lock(nq, cpu);
3948
3949 /* Avoid tx timeout as XDP shares the queue with kernel stack */
3950 txq_trans_cond_update(nq);
3951 for (i = 0; i < num_frames; i++) {
3952 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0)
3953 break;
3954 sent_frames++;
3955 }
3956
3957 __netif_tx_unlock(nq);
3958
3959 return sent_frames;
3960}
3961
3962static int fec_hwtstamp_get(struct net_device *ndev,
3963 struct kernel_hwtstamp_config *config)
3964{
3965 struct fec_enet_private *fep = netdev_priv(ndev);
3966
3967 if (!netif_running(ndev))
3968 return -EINVAL;
3969
3970 if (!fep->bufdesc_ex)
3971 return -EOPNOTSUPP;
3972
3973 fec_ptp_get(ndev, config);
3974
3975 return 0;
3976}
3977
3978static int fec_hwtstamp_set(struct net_device *ndev,
3979 struct kernel_hwtstamp_config *config,
3980 struct netlink_ext_ack *extack)
3981{
3982 struct fec_enet_private *fep = netdev_priv(ndev);
3983
3984 if (!netif_running(ndev))
3985 return -EINVAL;
3986
3987 if (!fep->bufdesc_ex)
3988 return -EOPNOTSUPP;
3989
3990 return fec_ptp_set(ndev, config, extack);
3991}
3992
3993static const struct net_device_ops fec_netdev_ops = {
3994 .ndo_open = fec_enet_open,
3995 .ndo_stop = fec_enet_close,
3996 .ndo_start_xmit = fec_enet_start_xmit,
3997 .ndo_select_queue = fec_enet_select_queue,
3998 .ndo_set_rx_mode = set_multicast_list,
3999 .ndo_validate_addr = eth_validate_addr,
4000 .ndo_tx_timeout = fec_timeout,
4001 .ndo_set_mac_address = fec_set_mac_address,
4002 .ndo_eth_ioctl = phy_do_ioctl_running,
4003#ifdef CONFIG_NET_POLL_CONTROLLER
4004 .ndo_poll_controller = fec_poll_controller,
4005#endif
4006 .ndo_set_features = fec_set_features,
4007 .ndo_bpf = fec_enet_bpf,
4008 .ndo_xdp_xmit = fec_enet_xdp_xmit,
4009 .ndo_hwtstamp_get = fec_hwtstamp_get,
4010 .ndo_hwtstamp_set = fec_hwtstamp_set,
4011};
4012
4013static const unsigned short offset_des_active_rxq[] = {
4014 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
4015};
4016
4017static const unsigned short offset_des_active_txq[] = {
4018 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
4019};
4020
4021 /*
4022 * XXX: We need to clean up on failure exits here.
4023 *
4024 */
4025static int fec_enet_init(struct net_device *ndev)
4026{
4027 struct fec_enet_private *fep = netdev_priv(ndev);
4028 struct bufdesc *cbd_base;
4029 dma_addr_t bd_dma;
4030 int bd_size;
4031 unsigned int i;
4032 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
4033 sizeof(struct bufdesc);
4034 unsigned dsize_log2 = __fls(dsize);
4035 int ret;
4036
4037 WARN_ON(dsize != (1 << dsize_log2));
4038#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
4039 fep->rx_align = 0xf;
4040 fep->tx_align = 0xf;
4041#else
4042 fep->rx_align = 0x3;
4043 fep->tx_align = 0x3;
4044#endif
4045 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
4046 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
4047 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT;
4048 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT;
4049
4050 /* Check mask of the streaming and coherent API */
4051 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
4052 if (ret < 0) {
4053 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
4054 return ret;
4055 }
4056
4057 ret = fec_enet_alloc_queue(ndev);
4058 if (ret)
4059 return ret;
4060
4061 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
4062
4063 /* Allocate memory for buffer descriptors. */
4064 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma,
4065 GFP_KERNEL);
4066 if (!cbd_base) {
4067 ret = -ENOMEM;
4068 goto free_queue_mem;
4069 }
4070
4071 /* Get the Ethernet address */
4072 ret = fec_get_mac(ndev);
4073 if (ret)
4074 goto free_queue_mem;
4075
4076 /* Set receive and transmit descriptor base. */
4077 for (i = 0; i < fep->num_rx_queues; i++) {
4078 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
4079 unsigned size = dsize * rxq->bd.ring_size;
4080
4081 rxq->bd.qid = i;
4082 rxq->bd.base = cbd_base;
4083 rxq->bd.cur = cbd_base;
4084 rxq->bd.dma = bd_dma;
4085 rxq->bd.dsize = dsize;
4086 rxq->bd.dsize_log2 = dsize_log2;
4087 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
4088 bd_dma += size;
4089 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4090 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4091 }
4092
4093 for (i = 0; i < fep->num_tx_queues; i++) {
4094 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
4095 unsigned size = dsize * txq->bd.ring_size;
4096
4097 txq->bd.qid = i;
4098 txq->bd.base = cbd_base;
4099 txq->bd.cur = cbd_base;
4100 txq->bd.dma = bd_dma;
4101 txq->bd.dsize = dsize;
4102 txq->bd.dsize_log2 = dsize_log2;
4103 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
4104 bd_dma += size;
4105 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4106 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4107 }
4108
4109
4110 /* The FEC Ethernet specific entries in the device structure */
4111 ndev->watchdog_timeo = TX_TIMEOUT;
4112 ndev->netdev_ops = &fec_netdev_ops;
4113 ndev->ethtool_ops = &fec_enet_ethtool_ops;
4114
4115 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
4116 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi);
4117
4118 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
4119 /* enable hw VLAN support */
4120 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
4121
4122 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
4123 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS);
4124
4125 /* enable hw accelerator */
4126 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
4127 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
4128 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
4129 }
4130
4131 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
4132 fep->tx_align = 0;
4133 fep->rx_align = 0x3f;
4134 }
4135
4136 ndev->hw_features = ndev->features;
4137
4138 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME))
4139 ndev->xdp_features = NETDEV_XDP_ACT_BASIC |
4140 NETDEV_XDP_ACT_REDIRECT;
4141
4142 fec_restart(ndev);
4143
4144 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
4145 fec_enet_clear_ethtool_stats(ndev);
4146 else
4147 fec_enet_update_ethtool_stats(ndev);
4148
4149 return 0;
4150
4151free_queue_mem:
4152 fec_enet_free_queue(ndev);
4153 return ret;
4154}
4155
4156#ifdef CONFIG_OF
4157static int fec_reset_phy(struct platform_device *pdev)
4158{
4159 struct gpio_desc *phy_reset;
4160 int msec = 1, phy_post_delay = 0;
4161 struct device_node *np = pdev->dev.of_node;
4162 int err;
4163
4164 if (!np)
4165 return 0;
4166
4167 err = of_property_read_u32(np, "phy-reset-duration", &msec);
4168 /* A sane reset duration should not be longer than 1s */
4169 if (!err && msec > 1000)
4170 msec = 1;
4171
4172 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
4173 /* valid reset duration should be less than 1s */
4174 if (!err && phy_post_delay > 1000)
4175 return -EINVAL;
4176
4177 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset",
4178 GPIOD_OUT_HIGH);
4179 if (IS_ERR(phy_reset))
4180 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset),
4181 "failed to get phy-reset-gpios\n");
4182
4183 if (!phy_reset)
4184 return 0;
4185
4186 if (msec > 20)
4187 msleep(msec);
4188 else
4189 usleep_range(msec * 1000, msec * 1000 + 1000);
4190
4191 gpiod_set_value_cansleep(phy_reset, 0);
4192
4193 if (!phy_post_delay)
4194 return 0;
4195
4196 if (phy_post_delay > 20)
4197 msleep(phy_post_delay);
4198 else
4199 usleep_range(phy_post_delay * 1000,
4200 phy_post_delay * 1000 + 1000);
4201
4202 return 0;
4203}
4204#else /* CONFIG_OF */
4205static int fec_reset_phy(struct platform_device *pdev)
4206{
4207 /*
4208 * In case of platform probe, the reset has been done
4209 * by machine code.
4210 */
4211 return 0;
4212}
4213#endif /* CONFIG_OF */
4214
4215static void
4216fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
4217{
4218 struct device_node *np = pdev->dev.of_node;
4219
4220 *num_tx = *num_rx = 1;
4221
4222 if (!np || !of_device_is_available(np))
4223 return;
4224
4225 /* parse the num of tx and rx queues */
4226 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
4227
4228 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
4229
4230 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
4231 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
4232 *num_tx);
4233 *num_tx = 1;
4234 return;
4235 }
4236
4237 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
4238 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
4239 *num_rx);
4240 *num_rx = 1;
4241 return;
4242 }
4243
4244}
4245
4246static int fec_enet_get_irq_cnt(struct platform_device *pdev)
4247{
4248 int irq_cnt = platform_irq_count(pdev);
4249
4250 if (irq_cnt > FEC_IRQ_NUM)
4251 irq_cnt = FEC_IRQ_NUM; /* last for pps */
4252 else if (irq_cnt == 2)
4253 irq_cnt = 1; /* last for pps */
4254 else if (irq_cnt <= 0)
4255 irq_cnt = 1; /* At least 1 irq is needed */
4256 return irq_cnt;
4257}
4258
4259static void fec_enet_get_wakeup_irq(struct platform_device *pdev)
4260{
4261 struct net_device *ndev = platform_get_drvdata(pdev);
4262 struct fec_enet_private *fep = netdev_priv(ndev);
4263
4264 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2)
4265 fep->wake_irq = fep->irq[2];
4266 else
4267 fep->wake_irq = fep->irq[0];
4268}
4269
4270static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
4271 struct device_node *np)
4272{
4273 struct device_node *gpr_np;
4274 u32 out_val[3];
4275 int ret = 0;
4276
4277 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
4278 if (!gpr_np)
4279 return 0;
4280
4281 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
4282 ARRAY_SIZE(out_val));
4283 if (ret) {
4284 dev_dbg(&fep->pdev->dev, "no stop mode property\n");
4285 goto out;
4286 }
4287
4288 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
4289 if (IS_ERR(fep->stop_gpr.gpr)) {
4290 dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
4291 ret = PTR_ERR(fep->stop_gpr.gpr);
4292 fep->stop_gpr.gpr = NULL;
4293 goto out;
4294 }
4295
4296 fep->stop_gpr.reg = out_val[1];
4297 fep->stop_gpr.bit = out_val[2];
4298
4299out:
4300 of_node_put(gpr_np);
4301
4302 return ret;
4303}
4304
4305static int
4306fec_probe(struct platform_device *pdev)
4307{
4308 struct fec_enet_private *fep;
4309 struct fec_platform_data *pdata;
4310 phy_interface_t interface;
4311 struct net_device *ndev;
4312 int i, irq, ret = 0;
4313 static int dev_id;
4314 struct device_node *np = pdev->dev.of_node, *phy_node;
4315 int num_tx_qs;
4316 int num_rx_qs;
4317 char irq_name[8];
4318 int irq_cnt;
4319 const struct fec_devinfo *dev_info;
4320
4321 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
4322
4323 /* Init network device */
4324 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
4325 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
4326 if (!ndev)
4327 return -ENOMEM;
4328
4329 SET_NETDEV_DEV(ndev, &pdev->dev);
4330
4331 /* setup board info structure */
4332 fep = netdev_priv(ndev);
4333
4334 dev_info = device_get_match_data(&pdev->dev);
4335 if (!dev_info)
4336 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data;
4337 if (dev_info)
4338 fep->quirks = dev_info->quirks;
4339
4340 fep->netdev = ndev;
4341 fep->num_rx_queues = num_rx_qs;
4342 fep->num_tx_queues = num_tx_qs;
4343
4344#if !defined(CONFIG_M5272)
4345 /* default enable pause frame auto negotiation */
4346 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
4347 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
4348#endif
4349
4350 /* Select default pin state */
4351 pinctrl_pm_select_default_state(&pdev->dev);
4352
4353 fep->hwp = devm_platform_ioremap_resource(pdev, 0);
4354 if (IS_ERR(fep->hwp)) {
4355 ret = PTR_ERR(fep->hwp);
4356 goto failed_ioremap;
4357 }
4358
4359 fep->pdev = pdev;
4360 fep->dev_id = dev_id++;
4361
4362 platform_set_drvdata(pdev, ndev);
4363
4364 if ((of_machine_is_compatible("fsl,imx6q") ||
4365 of_machine_is_compatible("fsl,imx6dl")) &&
4366 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
4367 fep->quirks |= FEC_QUIRK_ERR006687;
4368
4369 ret = fec_enet_ipc_handle_init(fep);
4370 if (ret)
4371 goto failed_ipc_init;
4372
4373 if (of_property_read_bool(np, "fsl,magic-packet"))
4374 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
4375
4376 ret = fec_enet_init_stop_mode(fep, np);
4377 if (ret)
4378 goto failed_stop_mode;
4379
4380 phy_node = of_parse_phandle(np, "phy-handle", 0);
4381 if (!phy_node && of_phy_is_fixed_link(np)) {
4382 ret = of_phy_register_fixed_link(np);
4383 if (ret < 0) {
4384 dev_err(&pdev->dev,
4385 "broken fixed-link specification\n");
4386 goto failed_phy;
4387 }
4388 phy_node = of_node_get(np);
4389 }
4390 fep->phy_node = phy_node;
4391
4392 ret = of_get_phy_mode(pdev->dev.of_node, &interface);
4393 if (ret) {
4394 pdata = dev_get_platdata(&pdev->dev);
4395 if (pdata)
4396 fep->phy_interface = pdata->phy;
4397 else
4398 fep->phy_interface = PHY_INTERFACE_MODE_MII;
4399 } else {
4400 fep->phy_interface = interface;
4401 }
4402
4403 ret = fec_enet_parse_rgmii_delay(fep, np);
4404 if (ret)
4405 goto failed_rgmii_delay;
4406
4407 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
4408 if (IS_ERR(fep->clk_ipg)) {
4409 ret = PTR_ERR(fep->clk_ipg);
4410 goto failed_clk;
4411 }
4412
4413 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
4414 if (IS_ERR(fep->clk_ahb)) {
4415 ret = PTR_ERR(fep->clk_ahb);
4416 goto failed_clk;
4417 }
4418
4419 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
4420
4421 /* enet_out is optional, depends on board */
4422 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out");
4423 if (IS_ERR(fep->clk_enet_out)) {
4424 ret = PTR_ERR(fep->clk_enet_out);
4425 goto failed_clk;
4426 }
4427
4428 fep->ptp_clk_on = false;
4429 mutex_init(&fep->ptp_clk_mutex);
4430
4431 /* clk_ref is optional, depends on board */
4432 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref");
4433 if (IS_ERR(fep->clk_ref)) {
4434 ret = PTR_ERR(fep->clk_ref);
4435 goto failed_clk;
4436 }
4437 fep->clk_ref_rate = clk_get_rate(fep->clk_ref);
4438
4439 /* clk_2x_txclk is optional, depends on board */
4440 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) {
4441 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk");
4442 if (IS_ERR(fep->clk_2x_txclk))
4443 fep->clk_2x_txclk = NULL;
4444 }
4445
4446 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
4447 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
4448 if (IS_ERR(fep->clk_ptp)) {
4449 fep->clk_ptp = NULL;
4450 fep->bufdesc_ex = false;
4451 }
4452
4453 ret = fec_enet_clk_enable(ndev, true);
4454 if (ret)
4455 goto failed_clk;
4456
4457 ret = clk_prepare_enable(fep->clk_ipg);
4458 if (ret)
4459 goto failed_clk_ipg;
4460 ret = clk_prepare_enable(fep->clk_ahb);
4461 if (ret)
4462 goto failed_clk_ahb;
4463
4464 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
4465 if (!IS_ERR(fep->reg_phy)) {
4466 ret = regulator_enable(fep->reg_phy);
4467 if (ret) {
4468 dev_err(&pdev->dev,
4469 "Failed to enable phy regulator: %d\n", ret);
4470 goto failed_regulator;
4471 }
4472 } else {
4473 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
4474 ret = -EPROBE_DEFER;
4475 goto failed_regulator;
4476 }
4477 fep->reg_phy = NULL;
4478 }
4479
4480 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
4481 pm_runtime_use_autosuspend(&pdev->dev);
4482 pm_runtime_get_noresume(&pdev->dev);
4483 pm_runtime_set_active(&pdev->dev);
4484 pm_runtime_enable(&pdev->dev);
4485
4486 ret = fec_reset_phy(pdev);
4487 if (ret)
4488 goto failed_reset;
4489
4490 irq_cnt = fec_enet_get_irq_cnt(pdev);
4491 if (fep->bufdesc_ex)
4492 fec_ptp_init(pdev, irq_cnt);
4493
4494 ret = fec_enet_init(ndev);
4495 if (ret)
4496 goto failed_init;
4497
4498 for (i = 0; i < irq_cnt; i++) {
4499 snprintf(irq_name, sizeof(irq_name), "int%d", i);
4500 irq = platform_get_irq_byname_optional(pdev, irq_name);
4501 if (irq < 0)
4502 irq = platform_get_irq(pdev, i);
4503 if (irq < 0) {
4504 ret = irq;
4505 goto failed_irq;
4506 }
4507 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
4508 0, pdev->name, ndev);
4509 if (ret)
4510 goto failed_irq;
4511
4512 fep->irq[i] = irq;
4513 }
4514
4515 /* Decide which interrupt line is wakeup capable */
4516 fec_enet_get_wakeup_irq(pdev);
4517
4518 ret = fec_enet_mii_init(pdev);
4519 if (ret)
4520 goto failed_mii_init;
4521
4522 /* Carrier starts down, phylib will bring it up */
4523 netif_carrier_off(ndev);
4524 fec_enet_clk_enable(ndev, false);
4525 pinctrl_pm_select_sleep_state(&pdev->dev);
4526
4527 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN;
4528
4529 ret = register_netdev(ndev);
4530 if (ret)
4531 goto failed_register;
4532
4533 device_init_wakeup(&ndev->dev, fep->wol_flag &
4534 FEC_WOL_HAS_MAGIC_PACKET);
4535
4536 if (fep->bufdesc_ex && fep->ptp_clock)
4537 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
4538
4539 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
4540
4541 pm_runtime_mark_last_busy(&pdev->dev);
4542 pm_runtime_put_autosuspend(&pdev->dev);
4543
4544 return 0;
4545
4546failed_register:
4547 fec_enet_mii_remove(fep);
4548failed_mii_init:
4549failed_irq:
4550failed_init:
4551 fec_ptp_stop(pdev);
4552failed_reset:
4553 pm_runtime_put_noidle(&pdev->dev);
4554 pm_runtime_disable(&pdev->dev);
4555 if (fep->reg_phy)
4556 regulator_disable(fep->reg_phy);
4557failed_regulator:
4558 clk_disable_unprepare(fep->clk_ahb);
4559failed_clk_ahb:
4560 clk_disable_unprepare(fep->clk_ipg);
4561failed_clk_ipg:
4562 fec_enet_clk_enable(ndev, false);
4563failed_clk:
4564failed_rgmii_delay:
4565 if (of_phy_is_fixed_link(np))
4566 of_phy_deregister_fixed_link(np);
4567 of_node_put(phy_node);
4568failed_stop_mode:
4569failed_ipc_init:
4570failed_phy:
4571 dev_id--;
4572failed_ioremap:
4573 free_netdev(ndev);
4574
4575 return ret;
4576}
4577
4578static void
4579fec_drv_remove(struct platform_device *pdev)
4580{
4581 struct net_device *ndev = platform_get_drvdata(pdev);
4582 struct fec_enet_private *fep = netdev_priv(ndev);
4583 struct device_node *np = pdev->dev.of_node;
4584 int ret;
4585
4586 ret = pm_runtime_get_sync(&pdev->dev);
4587 if (ret < 0)
4588 dev_err(&pdev->dev,
4589 "Failed to resume device in remove callback (%pe)\n",
4590 ERR_PTR(ret));
4591
4592 cancel_work_sync(&fep->tx_timeout_work);
4593 fec_ptp_stop(pdev);
4594 unregister_netdev(ndev);
4595 fec_enet_mii_remove(fep);
4596 if (fep->reg_phy)
4597 regulator_disable(fep->reg_phy);
4598
4599 if (of_phy_is_fixed_link(np))
4600 of_phy_deregister_fixed_link(np);
4601 of_node_put(fep->phy_node);
4602
4603 /* After pm_runtime_get_sync() failed, the clks are still off, so skip
4604 * disabling them again.
4605 */
4606 if (ret >= 0) {
4607 clk_disable_unprepare(fep->clk_ahb);
4608 clk_disable_unprepare(fep->clk_ipg);
4609 }
4610 pm_runtime_put_noidle(&pdev->dev);
4611 pm_runtime_disable(&pdev->dev);
4612
4613 free_netdev(ndev);
4614}
4615
4616static int __maybe_unused fec_suspend(struct device *dev)
4617{
4618 struct net_device *ndev = dev_get_drvdata(dev);
4619 struct fec_enet_private *fep = netdev_priv(ndev);
4620 int ret;
4621
4622 rtnl_lock();
4623 if (netif_running(ndev)) {
4624 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
4625 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
4626 phy_stop(ndev->phydev);
4627 napi_disable(&fep->napi);
4628 netif_tx_lock_bh(ndev);
4629 netif_device_detach(ndev);
4630 netif_tx_unlock_bh(ndev);
4631 fec_stop(ndev);
4632 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4633 fec_irqs_disable(ndev);
4634 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
4635 } else {
4636 fec_irqs_disable_except_wakeup(ndev);
4637 if (fep->wake_irq > 0) {
4638 disable_irq(fep->wake_irq);
4639 enable_irq_wake(fep->wake_irq);
4640 }
4641 fec_enet_stop_mode(fep, true);
4642 }
4643 /* It's safe to disable clocks since interrupts are masked */
4644 fec_enet_clk_enable(ndev, false);
4645
4646 fep->rpm_active = !pm_runtime_status_suspended(dev);
4647 if (fep->rpm_active) {
4648 ret = pm_runtime_force_suspend(dev);
4649 if (ret < 0) {
4650 rtnl_unlock();
4651 return ret;
4652 }
4653 }
4654 }
4655 rtnl_unlock();
4656
4657 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
4658 regulator_disable(fep->reg_phy);
4659
4660 /* SOC supply clock to phy, when clock is disabled, phy link down
4661 * SOC control phy regulator, when regulator is disabled, phy link down
4662 */
4663 if (fep->clk_enet_out || fep->reg_phy)
4664 fep->link = 0;
4665
4666 return 0;
4667}
4668
4669static int __maybe_unused fec_resume(struct device *dev)
4670{
4671 struct net_device *ndev = dev_get_drvdata(dev);
4672 struct fec_enet_private *fep = netdev_priv(ndev);
4673 int ret;
4674 int val;
4675
4676 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4677 ret = regulator_enable(fep->reg_phy);
4678 if (ret)
4679 return ret;
4680 }
4681
4682 rtnl_lock();
4683 if (netif_running(ndev)) {
4684 if (fep->rpm_active)
4685 pm_runtime_force_resume(dev);
4686
4687 ret = fec_enet_clk_enable(ndev, true);
4688 if (ret) {
4689 rtnl_unlock();
4690 goto failed_clk;
4691 }
4692 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
4693 fec_enet_stop_mode(fep, false);
4694 if (fep->wake_irq) {
4695 disable_irq_wake(fep->wake_irq);
4696 enable_irq(fep->wake_irq);
4697 }
4698
4699 val = readl(fep->hwp + FEC_ECNTRL);
4700 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
4701 writel(val, fep->hwp + FEC_ECNTRL);
4702 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
4703 } else {
4704 pinctrl_pm_select_default_state(&fep->pdev->dev);
4705 }
4706 fec_restart(ndev);
4707 netif_tx_lock_bh(ndev);
4708 netif_device_attach(ndev);
4709 netif_tx_unlock_bh(ndev);
4710 napi_enable(&fep->napi);
4711 phy_init_hw(ndev->phydev);
4712 phy_start(ndev->phydev);
4713 }
4714 rtnl_unlock();
4715
4716 return 0;
4717
4718failed_clk:
4719 if (fep->reg_phy)
4720 regulator_disable(fep->reg_phy);
4721 return ret;
4722}
4723
4724static int __maybe_unused fec_runtime_suspend(struct device *dev)
4725{
4726 struct net_device *ndev = dev_get_drvdata(dev);
4727 struct fec_enet_private *fep = netdev_priv(ndev);
4728
4729 clk_disable_unprepare(fep->clk_ahb);
4730 clk_disable_unprepare(fep->clk_ipg);
4731
4732 return 0;
4733}
4734
4735static int __maybe_unused fec_runtime_resume(struct device *dev)
4736{
4737 struct net_device *ndev = dev_get_drvdata(dev);
4738 struct fec_enet_private *fep = netdev_priv(ndev);
4739 int ret;
4740
4741 ret = clk_prepare_enable(fep->clk_ahb);
4742 if (ret)
4743 return ret;
4744 ret = clk_prepare_enable(fep->clk_ipg);
4745 if (ret)
4746 goto failed_clk_ipg;
4747
4748 return 0;
4749
4750failed_clk_ipg:
4751 clk_disable_unprepare(fep->clk_ahb);
4752 return ret;
4753}
4754
4755static const struct dev_pm_ops fec_pm_ops = {
4756 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
4757 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
4758};
4759
4760static struct platform_driver fec_driver = {
4761 .driver = {
4762 .name = DRIVER_NAME,
4763 .pm = &fec_pm_ops,
4764 .of_match_table = fec_dt_ids,
4765 .suppress_bind_attrs = true,
4766 },
4767 .id_table = fec_devtype,
4768 .probe = fec_probe,
4769 .remove_new = fec_drv_remove,
4770};
4771
4772module_platform_driver(fec_driver);
4773
4774MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver");
4775MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
11 * small packets.
12 *
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 *
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 *
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
21 *
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23 */
24
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/string.h>
28#include <linux/pm_runtime.h>
29#include <linux/ptrace.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/slab.h>
33#include <linux/interrupt.h>
34#include <linux/delay.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
38#include <linux/in.h>
39#include <linux/ip.h>
40#include <net/ip.h>
41#include <net/tso.h>
42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/icmp.h>
45#include <linux/spinlock.h>
46#include <linux/workqueue.h>
47#include <linux/bitops.h>
48#include <linux/io.h>
49#include <linux/irq.h>
50#include <linux/clk.h>
51#include <linux/crc32.h>
52#include <linux/platform_device.h>
53#include <linux/mdio.h>
54#include <linux/phy.h>
55#include <linux/fec.h>
56#include <linux/of.h>
57#include <linux/of_device.h>
58#include <linux/of_gpio.h>
59#include <linux/of_mdio.h>
60#include <linux/of_net.h>
61#include <linux/regulator/consumer.h>
62#include <linux/if_vlan.h>
63#include <linux/pinctrl/consumer.h>
64#include <linux/prefetch.h>
65#include <soc/imx/cpuidle.h>
66
67#include <asm/cacheflush.h>
68
69#include "fec.h"
70
71static void set_multicast_list(struct net_device *ndev);
72static void fec_enet_itr_coal_init(struct net_device *ndev);
73
74#define DRIVER_NAME "fec"
75
76#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
77
78/* Pause frame feild and FIFO threshold */
79#define FEC_ENET_FCE (1 << 5)
80#define FEC_ENET_RSEM_V 0x84
81#define FEC_ENET_RSFL_V 16
82#define FEC_ENET_RAEM_V 0x8
83#define FEC_ENET_RAFL_V 0x8
84#define FEC_ENET_OPD_V 0xFFF0
85#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
86
87static struct platform_device_id fec_devtype[] = {
88 {
89 /* keep it for coldfire */
90 .name = DRIVER_NAME,
91 .driver_data = 0,
92 }, {
93 .name = "imx25-fec",
94 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
95 FEC_QUIRK_HAS_FRREG,
96 }, {
97 .name = "imx27-fec",
98 .driver_data = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
99 }, {
100 .name = "imx28-fec",
101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
102 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
103 FEC_QUIRK_HAS_FRREG,
104 }, {
105 .name = "imx6q-fec",
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
108 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
109 FEC_QUIRK_HAS_RACC,
110 }, {
111 .name = "mvf600-fec",
112 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
113 }, {
114 .name = "imx6sx-fec",
115 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
116 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
117 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
118 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
119 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
120 }, {
121 .name = "imx6ul-fec",
122 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
125 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
126 FEC_QUIRK_HAS_COALESCE,
127 }, {
128 /* sentinel */
129 }
130};
131MODULE_DEVICE_TABLE(platform, fec_devtype);
132
133enum imx_fec_type {
134 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
135 IMX27_FEC, /* runs on i.mx27/35/51 */
136 IMX28_FEC,
137 IMX6Q_FEC,
138 MVF600_FEC,
139 IMX6SX_FEC,
140 IMX6UL_FEC,
141};
142
143static const struct of_device_id fec_dt_ids[] = {
144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
149 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
150 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
151 { /* sentinel */ }
152};
153MODULE_DEVICE_TABLE(of, fec_dt_ids);
154
155static unsigned char macaddr[ETH_ALEN];
156module_param_array(macaddr, byte, NULL, 0);
157MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
158
159#if defined(CONFIG_M5272)
160/*
161 * Some hardware gets it MAC address out of local flash memory.
162 * if this is non-zero then assume it is the address to get MAC from.
163 */
164#if defined(CONFIG_NETtel)
165#define FEC_FLASHMAC 0xf0006006
166#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
167#define FEC_FLASHMAC 0xf0006000
168#elif defined(CONFIG_CANCam)
169#define FEC_FLASHMAC 0xf0020000
170#elif defined (CONFIG_M5272C3)
171#define FEC_FLASHMAC (0xffe04000 + 4)
172#elif defined(CONFIG_MOD5272)
173#define FEC_FLASHMAC 0xffc0406b
174#else
175#define FEC_FLASHMAC 0
176#endif
177#endif /* CONFIG_M5272 */
178
179/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
180 *
181 * 2048 byte skbufs are allocated. However, alignment requirements
182 * varies between FEC variants. Worst case is 64, so round down by 64.
183 */
184#define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
185#define PKT_MINBUF_SIZE 64
186
187/* FEC receive acceleration */
188#define FEC_RACC_IPDIS (1 << 1)
189#define FEC_RACC_PRODIS (1 << 2)
190#define FEC_RACC_SHIFT16 BIT(7)
191#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
192
193/* MIB Control Register */
194#define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
195
196/*
197 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
198 * size bits. Other FEC hardware does not, so we need to take that into
199 * account when setting it.
200 */
201#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
202 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
203 defined(CONFIG_ARM64)
204#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
205#else
206#define OPT_FRAME_SIZE 0
207#endif
208
209/* FEC MII MMFR bits definition */
210#define FEC_MMFR_ST (1 << 30)
211#define FEC_MMFR_ST_C45 (0)
212#define FEC_MMFR_OP_READ (2 << 28)
213#define FEC_MMFR_OP_READ_C45 (3 << 28)
214#define FEC_MMFR_OP_WRITE (1 << 28)
215#define FEC_MMFR_OP_ADDR_WRITE (0)
216#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
217#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
218#define FEC_MMFR_TA (2 << 16)
219#define FEC_MMFR_DATA(v) (v & 0xffff)
220/* FEC ECR bits definition */
221#define FEC_ECR_MAGICEN (1 << 2)
222#define FEC_ECR_SLEEP (1 << 3)
223
224#define FEC_MII_TIMEOUT 30000 /* us */
225
226/* Transmitter timeout */
227#define TX_TIMEOUT (2 * HZ)
228
229#define FEC_PAUSE_FLAG_AUTONEG 0x1
230#define FEC_PAUSE_FLAG_ENABLE 0x2
231#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
232#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
233#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
234
235#define COPYBREAK_DEFAULT 256
236
237/* Max number of allowed TCP segments for software TSO */
238#define FEC_MAX_TSO_SEGS 100
239#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
240
241#define IS_TSO_HEADER(txq, addr) \
242 ((addr >= txq->tso_hdrs_dma) && \
243 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
244
245static int mii_cnt;
246
247static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
248 struct bufdesc_prop *bd)
249{
250 return (bdp >= bd->last) ? bd->base
251 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
252}
253
254static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
255 struct bufdesc_prop *bd)
256{
257 return (bdp <= bd->base) ? bd->last
258 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
259}
260
261static int fec_enet_get_bd_index(struct bufdesc *bdp,
262 struct bufdesc_prop *bd)
263{
264 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
265}
266
267static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
268{
269 int entries;
270
271 entries = (((const char *)txq->dirty_tx -
272 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
273
274 return entries >= 0 ? entries : entries + txq->bd.ring_size;
275}
276
277static void swap_buffer(void *bufaddr, int len)
278{
279 int i;
280 unsigned int *buf = bufaddr;
281
282 for (i = 0; i < len; i += 4, buf++)
283 swab32s(buf);
284}
285
286static void swap_buffer2(void *dst_buf, void *src_buf, int len)
287{
288 int i;
289 unsigned int *src = src_buf;
290 unsigned int *dst = dst_buf;
291
292 for (i = 0; i < len; i += 4, src++, dst++)
293 *dst = swab32p(src);
294}
295
296static void fec_dump(struct net_device *ndev)
297{
298 struct fec_enet_private *fep = netdev_priv(ndev);
299 struct bufdesc *bdp;
300 struct fec_enet_priv_tx_q *txq;
301 int index = 0;
302
303 netdev_info(ndev, "TX ring dump\n");
304 pr_info("Nr SC addr len SKB\n");
305
306 txq = fep->tx_queue[0];
307 bdp = txq->bd.base;
308
309 do {
310 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
311 index,
312 bdp == txq->bd.cur ? 'S' : ' ',
313 bdp == txq->dirty_tx ? 'H' : ' ',
314 fec16_to_cpu(bdp->cbd_sc),
315 fec32_to_cpu(bdp->cbd_bufaddr),
316 fec16_to_cpu(bdp->cbd_datlen),
317 txq->tx_skbuff[index]);
318 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
319 index++;
320 } while (bdp != txq->bd.base);
321}
322
323static inline bool is_ipv4_pkt(struct sk_buff *skb)
324{
325 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
326}
327
328static int
329fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
330{
331 /* Only run for packets requiring a checksum. */
332 if (skb->ip_summed != CHECKSUM_PARTIAL)
333 return 0;
334
335 if (unlikely(skb_cow_head(skb, 0)))
336 return -1;
337
338 if (is_ipv4_pkt(skb))
339 ip_hdr(skb)->check = 0;
340 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
341
342 return 0;
343}
344
345static struct bufdesc *
346fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
347 struct sk_buff *skb,
348 struct net_device *ndev)
349{
350 struct fec_enet_private *fep = netdev_priv(ndev);
351 struct bufdesc *bdp = txq->bd.cur;
352 struct bufdesc_ex *ebdp;
353 int nr_frags = skb_shinfo(skb)->nr_frags;
354 int frag, frag_len;
355 unsigned short status;
356 unsigned int estatus = 0;
357 skb_frag_t *this_frag;
358 unsigned int index;
359 void *bufaddr;
360 dma_addr_t addr;
361 int i;
362
363 for (frag = 0; frag < nr_frags; frag++) {
364 this_frag = &skb_shinfo(skb)->frags[frag];
365 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
366 ebdp = (struct bufdesc_ex *)bdp;
367
368 status = fec16_to_cpu(bdp->cbd_sc);
369 status &= ~BD_ENET_TX_STATS;
370 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
371 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
372
373 /* Handle the last BD specially */
374 if (frag == nr_frags - 1) {
375 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
376 if (fep->bufdesc_ex) {
377 estatus |= BD_ENET_TX_INT;
378 if (unlikely(skb_shinfo(skb)->tx_flags &
379 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
380 estatus |= BD_ENET_TX_TS;
381 }
382 }
383
384 if (fep->bufdesc_ex) {
385 if (fep->quirks & FEC_QUIRK_HAS_AVB)
386 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
387 if (skb->ip_summed == CHECKSUM_PARTIAL)
388 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
389 ebdp->cbd_bdu = 0;
390 ebdp->cbd_esc = cpu_to_fec32(estatus);
391 }
392
393 bufaddr = skb_frag_address(this_frag);
394
395 index = fec_enet_get_bd_index(bdp, &txq->bd);
396 if (((unsigned long) bufaddr) & fep->tx_align ||
397 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
398 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
399 bufaddr = txq->tx_bounce[index];
400
401 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
402 swap_buffer(bufaddr, frag_len);
403 }
404
405 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
406 DMA_TO_DEVICE);
407 if (dma_mapping_error(&fep->pdev->dev, addr)) {
408 if (net_ratelimit())
409 netdev_err(ndev, "Tx DMA memory map failed\n");
410 goto dma_mapping_error;
411 }
412
413 bdp->cbd_bufaddr = cpu_to_fec32(addr);
414 bdp->cbd_datlen = cpu_to_fec16(frag_len);
415 /* Make sure the updates to rest of the descriptor are
416 * performed before transferring ownership.
417 */
418 wmb();
419 bdp->cbd_sc = cpu_to_fec16(status);
420 }
421
422 return bdp;
423dma_mapping_error:
424 bdp = txq->bd.cur;
425 for (i = 0; i < frag; i++) {
426 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
427 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
428 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
429 }
430 return ERR_PTR(-ENOMEM);
431}
432
433static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
434 struct sk_buff *skb, struct net_device *ndev)
435{
436 struct fec_enet_private *fep = netdev_priv(ndev);
437 int nr_frags = skb_shinfo(skb)->nr_frags;
438 struct bufdesc *bdp, *last_bdp;
439 void *bufaddr;
440 dma_addr_t addr;
441 unsigned short status;
442 unsigned short buflen;
443 unsigned int estatus = 0;
444 unsigned int index;
445 int entries_free;
446
447 entries_free = fec_enet_get_free_txdesc_num(txq);
448 if (entries_free < MAX_SKB_FRAGS + 1) {
449 dev_kfree_skb_any(skb);
450 if (net_ratelimit())
451 netdev_err(ndev, "NOT enough BD for SG!\n");
452 return NETDEV_TX_OK;
453 }
454
455 /* Protocol checksum off-load for TCP and UDP. */
456 if (fec_enet_clear_csum(skb, ndev)) {
457 dev_kfree_skb_any(skb);
458 return NETDEV_TX_OK;
459 }
460
461 /* Fill in a Tx ring entry */
462 bdp = txq->bd.cur;
463 last_bdp = bdp;
464 status = fec16_to_cpu(bdp->cbd_sc);
465 status &= ~BD_ENET_TX_STATS;
466
467 /* Set buffer length and buffer pointer */
468 bufaddr = skb->data;
469 buflen = skb_headlen(skb);
470
471 index = fec_enet_get_bd_index(bdp, &txq->bd);
472 if (((unsigned long) bufaddr) & fep->tx_align ||
473 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
474 memcpy(txq->tx_bounce[index], skb->data, buflen);
475 bufaddr = txq->tx_bounce[index];
476
477 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
478 swap_buffer(bufaddr, buflen);
479 }
480
481 /* Push the data cache so the CPM does not get stale memory data. */
482 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
483 if (dma_mapping_error(&fep->pdev->dev, addr)) {
484 dev_kfree_skb_any(skb);
485 if (net_ratelimit())
486 netdev_err(ndev, "Tx DMA memory map failed\n");
487 return NETDEV_TX_OK;
488 }
489
490 if (nr_frags) {
491 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
492 if (IS_ERR(last_bdp)) {
493 dma_unmap_single(&fep->pdev->dev, addr,
494 buflen, DMA_TO_DEVICE);
495 dev_kfree_skb_any(skb);
496 return NETDEV_TX_OK;
497 }
498 } else {
499 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
500 if (fep->bufdesc_ex) {
501 estatus = BD_ENET_TX_INT;
502 if (unlikely(skb_shinfo(skb)->tx_flags &
503 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
504 estatus |= BD_ENET_TX_TS;
505 }
506 }
507 bdp->cbd_bufaddr = cpu_to_fec32(addr);
508 bdp->cbd_datlen = cpu_to_fec16(buflen);
509
510 if (fep->bufdesc_ex) {
511
512 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
513
514 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
515 fep->hwts_tx_en))
516 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
517
518 if (fep->quirks & FEC_QUIRK_HAS_AVB)
519 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
520
521 if (skb->ip_summed == CHECKSUM_PARTIAL)
522 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
523
524 ebdp->cbd_bdu = 0;
525 ebdp->cbd_esc = cpu_to_fec32(estatus);
526 }
527
528 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
529 /* Save skb pointer */
530 txq->tx_skbuff[index] = skb;
531
532 /* Make sure the updates to rest of the descriptor are performed before
533 * transferring ownership.
534 */
535 wmb();
536
537 /* Send it on its way. Tell FEC it's ready, interrupt when done,
538 * it's the last BD of the frame, and to put the CRC on the end.
539 */
540 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
541 bdp->cbd_sc = cpu_to_fec16(status);
542
543 /* If this was the last BD in the ring, start at the beginning again. */
544 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
545
546 skb_tx_timestamp(skb);
547
548 /* Make sure the update to bdp and tx_skbuff are performed before
549 * txq->bd.cur.
550 */
551 wmb();
552 txq->bd.cur = bdp;
553
554 /* Trigger transmission start */
555 writel(0, txq->bd.reg_desc_active);
556
557 return 0;
558}
559
560static int
561fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
562 struct net_device *ndev,
563 struct bufdesc *bdp, int index, char *data,
564 int size, bool last_tcp, bool is_last)
565{
566 struct fec_enet_private *fep = netdev_priv(ndev);
567 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
568 unsigned short status;
569 unsigned int estatus = 0;
570 dma_addr_t addr;
571
572 status = fec16_to_cpu(bdp->cbd_sc);
573 status &= ~BD_ENET_TX_STATS;
574
575 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
576
577 if (((unsigned long) data) & fep->tx_align ||
578 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
579 memcpy(txq->tx_bounce[index], data, size);
580 data = txq->tx_bounce[index];
581
582 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
583 swap_buffer(data, size);
584 }
585
586 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
587 if (dma_mapping_error(&fep->pdev->dev, addr)) {
588 dev_kfree_skb_any(skb);
589 if (net_ratelimit())
590 netdev_err(ndev, "Tx DMA memory map failed\n");
591 return NETDEV_TX_BUSY;
592 }
593
594 bdp->cbd_datlen = cpu_to_fec16(size);
595 bdp->cbd_bufaddr = cpu_to_fec32(addr);
596
597 if (fep->bufdesc_ex) {
598 if (fep->quirks & FEC_QUIRK_HAS_AVB)
599 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
600 if (skb->ip_summed == CHECKSUM_PARTIAL)
601 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
602 ebdp->cbd_bdu = 0;
603 ebdp->cbd_esc = cpu_to_fec32(estatus);
604 }
605
606 /* Handle the last BD specially */
607 if (last_tcp)
608 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
609 if (is_last) {
610 status |= BD_ENET_TX_INTR;
611 if (fep->bufdesc_ex)
612 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
613 }
614
615 bdp->cbd_sc = cpu_to_fec16(status);
616
617 return 0;
618}
619
620static int
621fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
622 struct sk_buff *skb, struct net_device *ndev,
623 struct bufdesc *bdp, int index)
624{
625 struct fec_enet_private *fep = netdev_priv(ndev);
626 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
627 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
628 void *bufaddr;
629 unsigned long dmabuf;
630 unsigned short status;
631 unsigned int estatus = 0;
632
633 status = fec16_to_cpu(bdp->cbd_sc);
634 status &= ~BD_ENET_TX_STATS;
635 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
636
637 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
638 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
639 if (((unsigned long)bufaddr) & fep->tx_align ||
640 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
641 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
642 bufaddr = txq->tx_bounce[index];
643
644 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
645 swap_buffer(bufaddr, hdr_len);
646
647 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
648 hdr_len, DMA_TO_DEVICE);
649 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
650 dev_kfree_skb_any(skb);
651 if (net_ratelimit())
652 netdev_err(ndev, "Tx DMA memory map failed\n");
653 return NETDEV_TX_BUSY;
654 }
655 }
656
657 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
658 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
659
660 if (fep->bufdesc_ex) {
661 if (fep->quirks & FEC_QUIRK_HAS_AVB)
662 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
663 if (skb->ip_summed == CHECKSUM_PARTIAL)
664 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
665 ebdp->cbd_bdu = 0;
666 ebdp->cbd_esc = cpu_to_fec32(estatus);
667 }
668
669 bdp->cbd_sc = cpu_to_fec16(status);
670
671 return 0;
672}
673
674static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
675 struct sk_buff *skb,
676 struct net_device *ndev)
677{
678 struct fec_enet_private *fep = netdev_priv(ndev);
679 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
680 int total_len, data_left;
681 struct bufdesc *bdp = txq->bd.cur;
682 struct tso_t tso;
683 unsigned int index = 0;
684 int ret;
685
686 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
687 dev_kfree_skb_any(skb);
688 if (net_ratelimit())
689 netdev_err(ndev, "NOT enough BD for TSO!\n");
690 return NETDEV_TX_OK;
691 }
692
693 /* Protocol checksum off-load for TCP and UDP. */
694 if (fec_enet_clear_csum(skb, ndev)) {
695 dev_kfree_skb_any(skb);
696 return NETDEV_TX_OK;
697 }
698
699 /* Initialize the TSO handler, and prepare the first payload */
700 tso_start(skb, &tso);
701
702 total_len = skb->len - hdr_len;
703 while (total_len > 0) {
704 char *hdr;
705
706 index = fec_enet_get_bd_index(bdp, &txq->bd);
707 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
708 total_len -= data_left;
709
710 /* prepare packet headers: MAC + IP + TCP */
711 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
712 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
713 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
714 if (ret)
715 goto err_release;
716
717 while (data_left > 0) {
718 int size;
719
720 size = min_t(int, tso.size, data_left);
721 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
722 index = fec_enet_get_bd_index(bdp, &txq->bd);
723 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
724 bdp, index,
725 tso.data, size,
726 size == data_left,
727 total_len == 0);
728 if (ret)
729 goto err_release;
730
731 data_left -= size;
732 tso_build_data(skb, &tso, size);
733 }
734
735 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
736 }
737
738 /* Save skb pointer */
739 txq->tx_skbuff[index] = skb;
740
741 skb_tx_timestamp(skb);
742 txq->bd.cur = bdp;
743
744 /* Trigger transmission start */
745 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
746 !readl(txq->bd.reg_desc_active) ||
747 !readl(txq->bd.reg_desc_active) ||
748 !readl(txq->bd.reg_desc_active) ||
749 !readl(txq->bd.reg_desc_active))
750 writel(0, txq->bd.reg_desc_active);
751
752 return 0;
753
754err_release:
755 /* TODO: Release all used data descriptors for TSO */
756 return ret;
757}
758
759static netdev_tx_t
760fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
761{
762 struct fec_enet_private *fep = netdev_priv(ndev);
763 int entries_free;
764 unsigned short queue;
765 struct fec_enet_priv_tx_q *txq;
766 struct netdev_queue *nq;
767 int ret;
768
769 queue = skb_get_queue_mapping(skb);
770 txq = fep->tx_queue[queue];
771 nq = netdev_get_tx_queue(ndev, queue);
772
773 if (skb_is_gso(skb))
774 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
775 else
776 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
777 if (ret)
778 return ret;
779
780 entries_free = fec_enet_get_free_txdesc_num(txq);
781 if (entries_free <= txq->tx_stop_threshold)
782 netif_tx_stop_queue(nq);
783
784 return NETDEV_TX_OK;
785}
786
787/* Init RX & TX buffer descriptors
788 */
789static void fec_enet_bd_init(struct net_device *dev)
790{
791 struct fec_enet_private *fep = netdev_priv(dev);
792 struct fec_enet_priv_tx_q *txq;
793 struct fec_enet_priv_rx_q *rxq;
794 struct bufdesc *bdp;
795 unsigned int i;
796 unsigned int q;
797
798 for (q = 0; q < fep->num_rx_queues; q++) {
799 /* Initialize the receive buffer descriptors. */
800 rxq = fep->rx_queue[q];
801 bdp = rxq->bd.base;
802
803 for (i = 0; i < rxq->bd.ring_size; i++) {
804
805 /* Initialize the BD for every fragment in the page. */
806 if (bdp->cbd_bufaddr)
807 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
808 else
809 bdp->cbd_sc = cpu_to_fec16(0);
810 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
811 }
812
813 /* Set the last buffer to wrap */
814 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
815 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
816
817 rxq->bd.cur = rxq->bd.base;
818 }
819
820 for (q = 0; q < fep->num_tx_queues; q++) {
821 /* ...and the same for transmit */
822 txq = fep->tx_queue[q];
823 bdp = txq->bd.base;
824 txq->bd.cur = bdp;
825
826 for (i = 0; i < txq->bd.ring_size; i++) {
827 /* Initialize the BD for every fragment in the page. */
828 bdp->cbd_sc = cpu_to_fec16(0);
829 if (bdp->cbd_bufaddr &&
830 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
831 dma_unmap_single(&fep->pdev->dev,
832 fec32_to_cpu(bdp->cbd_bufaddr),
833 fec16_to_cpu(bdp->cbd_datlen),
834 DMA_TO_DEVICE);
835 if (txq->tx_skbuff[i]) {
836 dev_kfree_skb_any(txq->tx_skbuff[i]);
837 txq->tx_skbuff[i] = NULL;
838 }
839 bdp->cbd_bufaddr = cpu_to_fec32(0);
840 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
841 }
842
843 /* Set the last buffer to wrap */
844 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
845 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
846 txq->dirty_tx = bdp;
847 }
848}
849
850static void fec_enet_active_rxring(struct net_device *ndev)
851{
852 struct fec_enet_private *fep = netdev_priv(ndev);
853 int i;
854
855 for (i = 0; i < fep->num_rx_queues; i++)
856 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
857}
858
859static void fec_enet_enable_ring(struct net_device *ndev)
860{
861 struct fec_enet_private *fep = netdev_priv(ndev);
862 struct fec_enet_priv_tx_q *txq;
863 struct fec_enet_priv_rx_q *rxq;
864 int i;
865
866 for (i = 0; i < fep->num_rx_queues; i++) {
867 rxq = fep->rx_queue[i];
868 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
869 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
870
871 /* enable DMA1/2 */
872 if (i)
873 writel(RCMR_MATCHEN | RCMR_CMP(i),
874 fep->hwp + FEC_RCMR(i));
875 }
876
877 for (i = 0; i < fep->num_tx_queues; i++) {
878 txq = fep->tx_queue[i];
879 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
880
881 /* enable DMA1/2 */
882 if (i)
883 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
884 fep->hwp + FEC_DMA_CFG(i));
885 }
886}
887
888static void fec_enet_reset_skb(struct net_device *ndev)
889{
890 struct fec_enet_private *fep = netdev_priv(ndev);
891 struct fec_enet_priv_tx_q *txq;
892 int i, j;
893
894 for (i = 0; i < fep->num_tx_queues; i++) {
895 txq = fep->tx_queue[i];
896
897 for (j = 0; j < txq->bd.ring_size; j++) {
898 if (txq->tx_skbuff[j]) {
899 dev_kfree_skb_any(txq->tx_skbuff[j]);
900 txq->tx_skbuff[j] = NULL;
901 }
902 }
903 }
904}
905
906/*
907 * This function is called to start or restart the FEC during a link
908 * change, transmit timeout, or to reconfigure the FEC. The network
909 * packet processing for this device must be stopped before this call.
910 */
911static void
912fec_restart(struct net_device *ndev)
913{
914 struct fec_enet_private *fep = netdev_priv(ndev);
915 u32 val;
916 u32 temp_mac[2];
917 u32 rcntl = OPT_FRAME_SIZE | 0x04;
918 u32 ecntl = 0x2; /* ETHEREN */
919
920 /* Whack a reset. We should wait for this.
921 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
922 * instead of reset MAC itself.
923 */
924 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
925 writel(0, fep->hwp + FEC_ECNTRL);
926 } else {
927 writel(1, fep->hwp + FEC_ECNTRL);
928 udelay(10);
929 }
930
931 /*
932 * enet-mac reset will reset mac address registers too,
933 * so need to reconfigure it.
934 */
935 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
936 writel((__force u32)cpu_to_be32(temp_mac[0]),
937 fep->hwp + FEC_ADDR_LOW);
938 writel((__force u32)cpu_to_be32(temp_mac[1]),
939 fep->hwp + FEC_ADDR_HIGH);
940
941 /* Clear any outstanding interrupt. */
942 writel(0xffffffff, fep->hwp + FEC_IEVENT);
943
944 fec_enet_bd_init(ndev);
945
946 fec_enet_enable_ring(ndev);
947
948 /* Reset tx SKB buffers. */
949 fec_enet_reset_skb(ndev);
950
951 /* Enable MII mode */
952 if (fep->full_duplex == DUPLEX_FULL) {
953 /* FD enable */
954 writel(0x04, fep->hwp + FEC_X_CNTRL);
955 } else {
956 /* No Rcv on Xmit */
957 rcntl |= 0x02;
958 writel(0x0, fep->hwp + FEC_X_CNTRL);
959 }
960
961 /* Set MII speed */
962 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
963
964#if !defined(CONFIG_M5272)
965 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
966 val = readl(fep->hwp + FEC_RACC);
967 /* align IP header */
968 val |= FEC_RACC_SHIFT16;
969 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
970 /* set RX checksum */
971 val |= FEC_RACC_OPTIONS;
972 else
973 val &= ~FEC_RACC_OPTIONS;
974 writel(val, fep->hwp + FEC_RACC);
975 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
976 }
977#endif
978
979 /*
980 * The phy interface and speed need to get configured
981 * differently on enet-mac.
982 */
983 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
984 /* Enable flow control and length check */
985 rcntl |= 0x40000000 | 0x00000020;
986
987 /* RGMII, RMII or MII */
988 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
989 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
990 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
991 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
992 rcntl |= (1 << 6);
993 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
994 rcntl |= (1 << 8);
995 else
996 rcntl &= ~(1 << 8);
997
998 /* 1G, 100M or 10M */
999 if (ndev->phydev) {
1000 if (ndev->phydev->speed == SPEED_1000)
1001 ecntl |= (1 << 5);
1002 else if (ndev->phydev->speed == SPEED_100)
1003 rcntl &= ~(1 << 9);
1004 else
1005 rcntl |= (1 << 9);
1006 }
1007 } else {
1008#ifdef FEC_MIIGSK_ENR
1009 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1010 u32 cfgr;
1011 /* disable the gasket and wait */
1012 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1013 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1014 udelay(1);
1015
1016 /*
1017 * configure the gasket:
1018 * RMII, 50 MHz, no loopback, no echo
1019 * MII, 25 MHz, no loopback, no echo
1020 */
1021 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1022 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1023 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1024 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1025 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1026
1027 /* re-enable the gasket */
1028 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1029 }
1030#endif
1031 }
1032
1033#if !defined(CONFIG_M5272)
1034 /* enable pause frame*/
1035 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1036 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1037 ndev->phydev && ndev->phydev->pause)) {
1038 rcntl |= FEC_ENET_FCE;
1039
1040 /* set FIFO threshold parameter to reduce overrun */
1041 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1042 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1043 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1044 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1045
1046 /* OPD */
1047 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1048 } else {
1049 rcntl &= ~FEC_ENET_FCE;
1050 }
1051#endif /* !defined(CONFIG_M5272) */
1052
1053 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1054
1055 /* Setup multicast filter. */
1056 set_multicast_list(ndev);
1057#ifndef CONFIG_M5272
1058 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1059 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1060#endif
1061
1062 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1063 /* enable ENET endian swap */
1064 ecntl |= (1 << 8);
1065 /* enable ENET store and forward mode */
1066 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1067 }
1068
1069 if (fep->bufdesc_ex)
1070 ecntl |= (1 << 4);
1071
1072#ifndef CONFIG_M5272
1073 /* Enable the MIB statistic event counters */
1074 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1075#endif
1076
1077 /* And last, enable the transmit and receive processing */
1078 writel(ecntl, fep->hwp + FEC_ECNTRL);
1079 fec_enet_active_rxring(ndev);
1080
1081 if (fep->bufdesc_ex)
1082 fec_ptp_start_cyclecounter(ndev);
1083
1084 /* Enable interrupts we wish to service */
1085 if (fep->link)
1086 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1087 else
1088 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1089
1090 /* Init the interrupt coalescing */
1091 fec_enet_itr_coal_init(ndev);
1092
1093}
1094
1095static void
1096fec_stop(struct net_device *ndev)
1097{
1098 struct fec_enet_private *fep = netdev_priv(ndev);
1099 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1100 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1101 u32 val;
1102
1103 /* We cannot expect a graceful transmit stop without link !!! */
1104 if (fep->link) {
1105 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1106 udelay(10);
1107 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1108 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1109 }
1110
1111 /* Whack a reset. We should wait for this.
1112 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1113 * instead of reset MAC itself.
1114 */
1115 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1116 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1117 writel(0, fep->hwp + FEC_ECNTRL);
1118 } else {
1119 writel(1, fep->hwp + FEC_ECNTRL);
1120 udelay(10);
1121 }
1122 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1123 } else {
1124 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1125 val = readl(fep->hwp + FEC_ECNTRL);
1126 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1127 writel(val, fep->hwp + FEC_ECNTRL);
1128
1129 if (pdata && pdata->sleep_mode_enable)
1130 pdata->sleep_mode_enable(true);
1131 }
1132 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1133
1134 /* We have to keep ENET enabled to have MII interrupt stay working */
1135 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1136 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1137 writel(2, fep->hwp + FEC_ECNTRL);
1138 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1139 }
1140}
1141
1142
1143static void
1144fec_timeout(struct net_device *ndev)
1145{
1146 struct fec_enet_private *fep = netdev_priv(ndev);
1147
1148 fec_dump(ndev);
1149
1150 ndev->stats.tx_errors++;
1151
1152 schedule_work(&fep->tx_timeout_work);
1153}
1154
1155static void fec_enet_timeout_work(struct work_struct *work)
1156{
1157 struct fec_enet_private *fep =
1158 container_of(work, struct fec_enet_private, tx_timeout_work);
1159 struct net_device *ndev = fep->netdev;
1160
1161 rtnl_lock();
1162 if (netif_device_present(ndev) || netif_running(ndev)) {
1163 napi_disable(&fep->napi);
1164 netif_tx_lock_bh(ndev);
1165 fec_restart(ndev);
1166 netif_tx_wake_all_queues(ndev);
1167 netif_tx_unlock_bh(ndev);
1168 napi_enable(&fep->napi);
1169 }
1170 rtnl_unlock();
1171}
1172
1173static void
1174fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1175 struct skb_shared_hwtstamps *hwtstamps)
1176{
1177 unsigned long flags;
1178 u64 ns;
1179
1180 spin_lock_irqsave(&fep->tmreg_lock, flags);
1181 ns = timecounter_cyc2time(&fep->tc, ts);
1182 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1183
1184 memset(hwtstamps, 0, sizeof(*hwtstamps));
1185 hwtstamps->hwtstamp = ns_to_ktime(ns);
1186}
1187
1188static void
1189fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1190{
1191 struct fec_enet_private *fep;
1192 struct bufdesc *bdp;
1193 unsigned short status;
1194 struct sk_buff *skb;
1195 struct fec_enet_priv_tx_q *txq;
1196 struct netdev_queue *nq;
1197 int index = 0;
1198 int entries_free;
1199
1200 fep = netdev_priv(ndev);
1201
1202 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1203
1204 txq = fep->tx_queue[queue_id];
1205 /* get next bdp of dirty_tx */
1206 nq = netdev_get_tx_queue(ndev, queue_id);
1207 bdp = txq->dirty_tx;
1208
1209 /* get next bdp of dirty_tx */
1210 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1211
1212 while (bdp != READ_ONCE(txq->bd.cur)) {
1213 /* Order the load of bd.cur and cbd_sc */
1214 rmb();
1215 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1216 if (status & BD_ENET_TX_READY)
1217 break;
1218
1219 index = fec_enet_get_bd_index(bdp, &txq->bd);
1220
1221 skb = txq->tx_skbuff[index];
1222 txq->tx_skbuff[index] = NULL;
1223 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1224 dma_unmap_single(&fep->pdev->dev,
1225 fec32_to_cpu(bdp->cbd_bufaddr),
1226 fec16_to_cpu(bdp->cbd_datlen),
1227 DMA_TO_DEVICE);
1228 bdp->cbd_bufaddr = cpu_to_fec32(0);
1229 if (!skb)
1230 goto skb_done;
1231
1232 /* Check for errors. */
1233 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1234 BD_ENET_TX_RL | BD_ENET_TX_UN |
1235 BD_ENET_TX_CSL)) {
1236 ndev->stats.tx_errors++;
1237 if (status & BD_ENET_TX_HB) /* No heartbeat */
1238 ndev->stats.tx_heartbeat_errors++;
1239 if (status & BD_ENET_TX_LC) /* Late collision */
1240 ndev->stats.tx_window_errors++;
1241 if (status & BD_ENET_TX_RL) /* Retrans limit */
1242 ndev->stats.tx_aborted_errors++;
1243 if (status & BD_ENET_TX_UN) /* Underrun */
1244 ndev->stats.tx_fifo_errors++;
1245 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1246 ndev->stats.tx_carrier_errors++;
1247 } else {
1248 ndev->stats.tx_packets++;
1249 ndev->stats.tx_bytes += skb->len;
1250 }
1251
1252 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1253 fep->bufdesc_ex) {
1254 struct skb_shared_hwtstamps shhwtstamps;
1255 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1256
1257 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1258 skb_tstamp_tx(skb, &shhwtstamps);
1259 }
1260
1261 /* Deferred means some collisions occurred during transmit,
1262 * but we eventually sent the packet OK.
1263 */
1264 if (status & BD_ENET_TX_DEF)
1265 ndev->stats.collisions++;
1266
1267 /* Free the sk buffer associated with this last transmit */
1268 dev_kfree_skb_any(skb);
1269skb_done:
1270 /* Make sure the update to bdp and tx_skbuff are performed
1271 * before dirty_tx
1272 */
1273 wmb();
1274 txq->dirty_tx = bdp;
1275
1276 /* Update pointer to next buffer descriptor to be transmitted */
1277 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1278
1279 /* Since we have freed up a buffer, the ring is no longer full
1280 */
1281 if (netif_tx_queue_stopped(nq)) {
1282 entries_free = fec_enet_get_free_txdesc_num(txq);
1283 if (entries_free >= txq->tx_wake_threshold)
1284 netif_tx_wake_queue(nq);
1285 }
1286 }
1287
1288 /* ERR006358: Keep the transmitter going */
1289 if (bdp != txq->bd.cur &&
1290 readl(txq->bd.reg_desc_active) == 0)
1291 writel(0, txq->bd.reg_desc_active);
1292}
1293
1294static void
1295fec_enet_tx(struct net_device *ndev)
1296{
1297 struct fec_enet_private *fep = netdev_priv(ndev);
1298 u16 queue_id;
1299 /* First process class A queue, then Class B and Best Effort queue */
1300 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1301 clear_bit(queue_id, &fep->work_tx);
1302 fec_enet_tx_queue(ndev, queue_id);
1303 }
1304 return;
1305}
1306
1307static int
1308fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1309{
1310 struct fec_enet_private *fep = netdev_priv(ndev);
1311 int off;
1312
1313 off = ((unsigned long)skb->data) & fep->rx_align;
1314 if (off)
1315 skb_reserve(skb, fep->rx_align + 1 - off);
1316
1317 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1318 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1319 if (net_ratelimit())
1320 netdev_err(ndev, "Rx DMA memory map failed\n");
1321 return -ENOMEM;
1322 }
1323
1324 return 0;
1325}
1326
1327static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1328 struct bufdesc *bdp, u32 length, bool swap)
1329{
1330 struct fec_enet_private *fep = netdev_priv(ndev);
1331 struct sk_buff *new_skb;
1332
1333 if (length > fep->rx_copybreak)
1334 return false;
1335
1336 new_skb = netdev_alloc_skb(ndev, length);
1337 if (!new_skb)
1338 return false;
1339
1340 dma_sync_single_for_cpu(&fep->pdev->dev,
1341 fec32_to_cpu(bdp->cbd_bufaddr),
1342 FEC_ENET_RX_FRSIZE - fep->rx_align,
1343 DMA_FROM_DEVICE);
1344 if (!swap)
1345 memcpy(new_skb->data, (*skb)->data, length);
1346 else
1347 swap_buffer2(new_skb->data, (*skb)->data, length);
1348 *skb = new_skb;
1349
1350 return true;
1351}
1352
1353/* During a receive, the bd_rx.cur points to the current incoming buffer.
1354 * When we update through the ring, if the next incoming buffer has
1355 * not been given to the system, we just set the empty indicator,
1356 * effectively tossing the packet.
1357 */
1358static int
1359fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1360{
1361 struct fec_enet_private *fep = netdev_priv(ndev);
1362 struct fec_enet_priv_rx_q *rxq;
1363 struct bufdesc *bdp;
1364 unsigned short status;
1365 struct sk_buff *skb_new = NULL;
1366 struct sk_buff *skb;
1367 ushort pkt_len;
1368 __u8 *data;
1369 int pkt_received = 0;
1370 struct bufdesc_ex *ebdp = NULL;
1371 bool vlan_packet_rcvd = false;
1372 u16 vlan_tag;
1373 int index = 0;
1374 bool is_copybreak;
1375 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1376
1377#ifdef CONFIG_M532x
1378 flush_cache_all();
1379#endif
1380 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1381 rxq = fep->rx_queue[queue_id];
1382
1383 /* First, grab all of the stats for the incoming packet.
1384 * These get messed up if we get called due to a busy condition.
1385 */
1386 bdp = rxq->bd.cur;
1387
1388 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1389
1390 if (pkt_received >= budget)
1391 break;
1392 pkt_received++;
1393
1394 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1395
1396 /* Check for errors. */
1397 status ^= BD_ENET_RX_LAST;
1398 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1399 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1400 BD_ENET_RX_CL)) {
1401 ndev->stats.rx_errors++;
1402 if (status & BD_ENET_RX_OV) {
1403 /* FIFO overrun */
1404 ndev->stats.rx_fifo_errors++;
1405 goto rx_processing_done;
1406 }
1407 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1408 | BD_ENET_RX_LAST)) {
1409 /* Frame too long or too short. */
1410 ndev->stats.rx_length_errors++;
1411 if (status & BD_ENET_RX_LAST)
1412 netdev_err(ndev, "rcv is not +last\n");
1413 }
1414 if (status & BD_ENET_RX_CR) /* CRC Error */
1415 ndev->stats.rx_crc_errors++;
1416 /* Report late collisions as a frame error. */
1417 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1418 ndev->stats.rx_frame_errors++;
1419 goto rx_processing_done;
1420 }
1421
1422 /* Process the incoming frame. */
1423 ndev->stats.rx_packets++;
1424 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1425 ndev->stats.rx_bytes += pkt_len;
1426
1427 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1428 skb = rxq->rx_skbuff[index];
1429
1430 /* The packet length includes FCS, but we don't want to
1431 * include that when passing upstream as it messes up
1432 * bridging applications.
1433 */
1434 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1435 need_swap);
1436 if (!is_copybreak) {
1437 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1438 if (unlikely(!skb_new)) {
1439 ndev->stats.rx_dropped++;
1440 goto rx_processing_done;
1441 }
1442 dma_unmap_single(&fep->pdev->dev,
1443 fec32_to_cpu(bdp->cbd_bufaddr),
1444 FEC_ENET_RX_FRSIZE - fep->rx_align,
1445 DMA_FROM_DEVICE);
1446 }
1447
1448 prefetch(skb->data - NET_IP_ALIGN);
1449 skb_put(skb, pkt_len - 4);
1450 data = skb->data;
1451
1452 if (!is_copybreak && need_swap)
1453 swap_buffer(data, pkt_len);
1454
1455#if !defined(CONFIG_M5272)
1456 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1457 data = skb_pull_inline(skb, 2);
1458#endif
1459
1460 /* Extract the enhanced buffer descriptor */
1461 ebdp = NULL;
1462 if (fep->bufdesc_ex)
1463 ebdp = (struct bufdesc_ex *)bdp;
1464
1465 /* If this is a VLAN packet remove the VLAN Tag */
1466 vlan_packet_rcvd = false;
1467 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1468 fep->bufdesc_ex &&
1469 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1470 /* Push and remove the vlan tag */
1471 struct vlan_hdr *vlan_header =
1472 (struct vlan_hdr *) (data + ETH_HLEN);
1473 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1474
1475 vlan_packet_rcvd = true;
1476
1477 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1478 skb_pull(skb, VLAN_HLEN);
1479 }
1480
1481 skb->protocol = eth_type_trans(skb, ndev);
1482
1483 /* Get receive timestamp from the skb */
1484 if (fep->hwts_rx_en && fep->bufdesc_ex)
1485 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1486 skb_hwtstamps(skb));
1487
1488 if (fep->bufdesc_ex &&
1489 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1490 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1491 /* don't check it */
1492 skb->ip_summed = CHECKSUM_UNNECESSARY;
1493 } else {
1494 skb_checksum_none_assert(skb);
1495 }
1496 }
1497
1498 /* Handle received VLAN packets */
1499 if (vlan_packet_rcvd)
1500 __vlan_hwaccel_put_tag(skb,
1501 htons(ETH_P_8021Q),
1502 vlan_tag);
1503
1504 napi_gro_receive(&fep->napi, skb);
1505
1506 if (is_copybreak) {
1507 dma_sync_single_for_device(&fep->pdev->dev,
1508 fec32_to_cpu(bdp->cbd_bufaddr),
1509 FEC_ENET_RX_FRSIZE - fep->rx_align,
1510 DMA_FROM_DEVICE);
1511 } else {
1512 rxq->rx_skbuff[index] = skb_new;
1513 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1514 }
1515
1516rx_processing_done:
1517 /* Clear the status flags for this buffer */
1518 status &= ~BD_ENET_RX_STATS;
1519
1520 /* Mark the buffer empty */
1521 status |= BD_ENET_RX_EMPTY;
1522
1523 if (fep->bufdesc_ex) {
1524 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1525
1526 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1527 ebdp->cbd_prot = 0;
1528 ebdp->cbd_bdu = 0;
1529 }
1530 /* Make sure the updates to rest of the descriptor are
1531 * performed before transferring ownership.
1532 */
1533 wmb();
1534 bdp->cbd_sc = cpu_to_fec16(status);
1535
1536 /* Update BD pointer to next entry */
1537 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1538
1539 /* Doing this here will keep the FEC running while we process
1540 * incoming frames. On a heavily loaded network, we should be
1541 * able to keep up at the expense of system resources.
1542 */
1543 writel(0, rxq->bd.reg_desc_active);
1544 }
1545 rxq->bd.cur = bdp;
1546 return pkt_received;
1547}
1548
1549static int
1550fec_enet_rx(struct net_device *ndev, int budget)
1551{
1552 int pkt_received = 0;
1553 u16 queue_id;
1554 struct fec_enet_private *fep = netdev_priv(ndev);
1555
1556 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1557 int ret;
1558
1559 ret = fec_enet_rx_queue(ndev,
1560 budget - pkt_received, queue_id);
1561
1562 if (ret < budget - pkt_received)
1563 clear_bit(queue_id, &fep->work_rx);
1564
1565 pkt_received += ret;
1566 }
1567 return pkt_received;
1568}
1569
1570static bool
1571fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1572{
1573 if (int_events == 0)
1574 return false;
1575
1576 if (int_events & FEC_ENET_RXF_0)
1577 fep->work_rx |= (1 << 2);
1578 if (int_events & FEC_ENET_RXF_1)
1579 fep->work_rx |= (1 << 0);
1580 if (int_events & FEC_ENET_RXF_2)
1581 fep->work_rx |= (1 << 1);
1582
1583 if (int_events & FEC_ENET_TXF_0)
1584 fep->work_tx |= (1 << 2);
1585 if (int_events & FEC_ENET_TXF_1)
1586 fep->work_tx |= (1 << 0);
1587 if (int_events & FEC_ENET_TXF_2)
1588 fep->work_tx |= (1 << 1);
1589
1590 return true;
1591}
1592
1593static irqreturn_t
1594fec_enet_interrupt(int irq, void *dev_id)
1595{
1596 struct net_device *ndev = dev_id;
1597 struct fec_enet_private *fep = netdev_priv(ndev);
1598 uint int_events;
1599 irqreturn_t ret = IRQ_NONE;
1600
1601 int_events = readl(fep->hwp + FEC_IEVENT);
1602 writel(int_events, fep->hwp + FEC_IEVENT);
1603 fec_enet_collect_events(fep, int_events);
1604
1605 if ((fep->work_tx || fep->work_rx) && fep->link) {
1606 ret = IRQ_HANDLED;
1607
1608 if (napi_schedule_prep(&fep->napi)) {
1609 /* Disable the NAPI interrupts */
1610 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1611 __napi_schedule(&fep->napi);
1612 }
1613 }
1614
1615 if (int_events & FEC_ENET_MII) {
1616 ret = IRQ_HANDLED;
1617 complete(&fep->mdio_done);
1618 }
1619 return ret;
1620}
1621
1622static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1623{
1624 struct net_device *ndev = napi->dev;
1625 struct fec_enet_private *fep = netdev_priv(ndev);
1626 int pkts;
1627
1628 pkts = fec_enet_rx(ndev, budget);
1629
1630 fec_enet_tx(ndev);
1631
1632 if (pkts < budget) {
1633 napi_complete_done(napi, pkts);
1634 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1635 }
1636 return pkts;
1637}
1638
1639/* ------------------------------------------------------------------------- */
1640static void fec_get_mac(struct net_device *ndev)
1641{
1642 struct fec_enet_private *fep = netdev_priv(ndev);
1643 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1644 unsigned char *iap, tmpaddr[ETH_ALEN];
1645
1646 /*
1647 * try to get mac address in following order:
1648 *
1649 * 1) module parameter via kernel command line in form
1650 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1651 */
1652 iap = macaddr;
1653
1654 /*
1655 * 2) from device tree data
1656 */
1657 if (!is_valid_ether_addr(iap)) {
1658 struct device_node *np = fep->pdev->dev.of_node;
1659 if (np) {
1660 const char *mac = of_get_mac_address(np);
1661 if (!IS_ERR(mac))
1662 iap = (unsigned char *) mac;
1663 }
1664 }
1665
1666 /*
1667 * 3) from flash or fuse (via platform data)
1668 */
1669 if (!is_valid_ether_addr(iap)) {
1670#ifdef CONFIG_M5272
1671 if (FEC_FLASHMAC)
1672 iap = (unsigned char *)FEC_FLASHMAC;
1673#else
1674 if (pdata)
1675 iap = (unsigned char *)&pdata->mac;
1676#endif
1677 }
1678
1679 /*
1680 * 4) FEC mac registers set by bootloader
1681 */
1682 if (!is_valid_ether_addr(iap)) {
1683 *((__be32 *) &tmpaddr[0]) =
1684 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1685 *((__be16 *) &tmpaddr[4]) =
1686 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1687 iap = &tmpaddr[0];
1688 }
1689
1690 /*
1691 * 5) random mac address
1692 */
1693 if (!is_valid_ether_addr(iap)) {
1694 /* Report it and use a random ethernet address instead */
1695 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1696 eth_hw_addr_random(ndev);
1697 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1698 ndev->dev_addr);
1699 return;
1700 }
1701
1702 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1703
1704 /* Adjust MAC if using macaddr */
1705 if (iap == macaddr)
1706 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1707}
1708
1709/* ------------------------------------------------------------------------- */
1710
1711/*
1712 * Phy section
1713 */
1714static void fec_enet_adjust_link(struct net_device *ndev)
1715{
1716 struct fec_enet_private *fep = netdev_priv(ndev);
1717 struct phy_device *phy_dev = ndev->phydev;
1718 int status_change = 0;
1719
1720 /*
1721 * If the netdev is down, or is going down, we're not interested
1722 * in link state events, so just mark our idea of the link as down
1723 * and ignore the event.
1724 */
1725 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1726 fep->link = 0;
1727 } else if (phy_dev->link) {
1728 if (!fep->link) {
1729 fep->link = phy_dev->link;
1730 status_change = 1;
1731 }
1732
1733 if (fep->full_duplex != phy_dev->duplex) {
1734 fep->full_duplex = phy_dev->duplex;
1735 status_change = 1;
1736 }
1737
1738 if (phy_dev->speed != fep->speed) {
1739 fep->speed = phy_dev->speed;
1740 status_change = 1;
1741 }
1742
1743 /* if any of the above changed restart the FEC */
1744 if (status_change) {
1745 napi_disable(&fep->napi);
1746 netif_tx_lock_bh(ndev);
1747 fec_restart(ndev);
1748 netif_tx_wake_all_queues(ndev);
1749 netif_tx_unlock_bh(ndev);
1750 napi_enable(&fep->napi);
1751 }
1752 } else {
1753 if (fep->link) {
1754 napi_disable(&fep->napi);
1755 netif_tx_lock_bh(ndev);
1756 fec_stop(ndev);
1757 netif_tx_unlock_bh(ndev);
1758 napi_enable(&fep->napi);
1759 fep->link = phy_dev->link;
1760 status_change = 1;
1761 }
1762 }
1763
1764 if (status_change)
1765 phy_print_status(phy_dev);
1766}
1767
1768static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1769{
1770 struct fec_enet_private *fep = bus->priv;
1771 struct device *dev = &fep->pdev->dev;
1772 unsigned long time_left;
1773 int ret = 0, frame_start, frame_addr, frame_op;
1774 bool is_c45 = !!(regnum & MII_ADDR_C45);
1775
1776 ret = pm_runtime_get_sync(dev);
1777 if (ret < 0)
1778 return ret;
1779
1780 reinit_completion(&fep->mdio_done);
1781
1782 if (is_c45) {
1783 frame_start = FEC_MMFR_ST_C45;
1784
1785 /* write address */
1786 frame_addr = (regnum >> 16);
1787 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1788 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1789 FEC_MMFR_TA | (regnum & 0xFFFF),
1790 fep->hwp + FEC_MII_DATA);
1791
1792 /* wait for end of transfer */
1793 time_left = wait_for_completion_timeout(&fep->mdio_done,
1794 usecs_to_jiffies(FEC_MII_TIMEOUT));
1795 if (time_left == 0) {
1796 netdev_err(fep->netdev, "MDIO address write timeout\n");
1797 ret = -ETIMEDOUT;
1798 goto out;
1799 }
1800
1801 frame_op = FEC_MMFR_OP_READ_C45;
1802
1803 } else {
1804 /* C22 read */
1805 frame_op = FEC_MMFR_OP_READ;
1806 frame_start = FEC_MMFR_ST;
1807 frame_addr = regnum;
1808 }
1809
1810 /* start a read op */
1811 writel(frame_start | frame_op |
1812 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1813 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1814
1815 /* wait for end of transfer */
1816 time_left = wait_for_completion_timeout(&fep->mdio_done,
1817 usecs_to_jiffies(FEC_MII_TIMEOUT));
1818 if (time_left == 0) {
1819 netdev_err(fep->netdev, "MDIO read timeout\n");
1820 ret = -ETIMEDOUT;
1821 goto out;
1822 }
1823
1824 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1825
1826out:
1827 pm_runtime_mark_last_busy(dev);
1828 pm_runtime_put_autosuspend(dev);
1829
1830 return ret;
1831}
1832
1833static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1834 u16 value)
1835{
1836 struct fec_enet_private *fep = bus->priv;
1837 struct device *dev = &fep->pdev->dev;
1838 unsigned long time_left;
1839 int ret, frame_start, frame_addr;
1840 bool is_c45 = !!(regnum & MII_ADDR_C45);
1841
1842 ret = pm_runtime_get_sync(dev);
1843 if (ret < 0)
1844 return ret;
1845 else
1846 ret = 0;
1847
1848 reinit_completion(&fep->mdio_done);
1849
1850 if (is_c45) {
1851 frame_start = FEC_MMFR_ST_C45;
1852
1853 /* write address */
1854 frame_addr = (regnum >> 16);
1855 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1856 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1857 FEC_MMFR_TA | (regnum & 0xFFFF),
1858 fep->hwp + FEC_MII_DATA);
1859
1860 /* wait for end of transfer */
1861 time_left = wait_for_completion_timeout(&fep->mdio_done,
1862 usecs_to_jiffies(FEC_MII_TIMEOUT));
1863 if (time_left == 0) {
1864 netdev_err(fep->netdev, "MDIO address write timeout\n");
1865 ret = -ETIMEDOUT;
1866 goto out;
1867 }
1868 } else {
1869 /* C22 write */
1870 frame_start = FEC_MMFR_ST;
1871 frame_addr = regnum;
1872 }
1873
1874 /* start a write op */
1875 writel(frame_start | FEC_MMFR_OP_WRITE |
1876 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1877 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1878 fep->hwp + FEC_MII_DATA);
1879
1880 /* wait for end of transfer */
1881 time_left = wait_for_completion_timeout(&fep->mdio_done,
1882 usecs_to_jiffies(FEC_MII_TIMEOUT));
1883 if (time_left == 0) {
1884 netdev_err(fep->netdev, "MDIO write timeout\n");
1885 ret = -ETIMEDOUT;
1886 }
1887
1888out:
1889 pm_runtime_mark_last_busy(dev);
1890 pm_runtime_put_autosuspend(dev);
1891
1892 return ret;
1893}
1894
1895static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1896{
1897 struct fec_enet_private *fep = netdev_priv(ndev);
1898 int ret;
1899
1900 if (enable) {
1901 ret = clk_prepare_enable(fep->clk_enet_out);
1902 if (ret)
1903 return ret;
1904
1905 if (fep->clk_ptp) {
1906 mutex_lock(&fep->ptp_clk_mutex);
1907 ret = clk_prepare_enable(fep->clk_ptp);
1908 if (ret) {
1909 mutex_unlock(&fep->ptp_clk_mutex);
1910 goto failed_clk_ptp;
1911 } else {
1912 fep->ptp_clk_on = true;
1913 }
1914 mutex_unlock(&fep->ptp_clk_mutex);
1915 }
1916
1917 ret = clk_prepare_enable(fep->clk_ref);
1918 if (ret)
1919 goto failed_clk_ref;
1920
1921 phy_reset_after_clk_enable(ndev->phydev);
1922 } else {
1923 clk_disable_unprepare(fep->clk_enet_out);
1924 if (fep->clk_ptp) {
1925 mutex_lock(&fep->ptp_clk_mutex);
1926 clk_disable_unprepare(fep->clk_ptp);
1927 fep->ptp_clk_on = false;
1928 mutex_unlock(&fep->ptp_clk_mutex);
1929 }
1930 clk_disable_unprepare(fep->clk_ref);
1931 }
1932
1933 return 0;
1934
1935failed_clk_ref:
1936 if (fep->clk_ref)
1937 clk_disable_unprepare(fep->clk_ref);
1938failed_clk_ptp:
1939 if (fep->clk_enet_out)
1940 clk_disable_unprepare(fep->clk_enet_out);
1941
1942 return ret;
1943}
1944
1945static int fec_enet_mii_probe(struct net_device *ndev)
1946{
1947 struct fec_enet_private *fep = netdev_priv(ndev);
1948 struct phy_device *phy_dev = NULL;
1949 char mdio_bus_id[MII_BUS_ID_SIZE];
1950 char phy_name[MII_BUS_ID_SIZE + 3];
1951 int phy_id;
1952 int dev_id = fep->dev_id;
1953
1954 if (fep->phy_node) {
1955 phy_dev = of_phy_connect(ndev, fep->phy_node,
1956 &fec_enet_adjust_link, 0,
1957 fep->phy_interface);
1958 if (!phy_dev) {
1959 netdev_err(ndev, "Unable to connect to phy\n");
1960 return -ENODEV;
1961 }
1962 } else {
1963 /* check for attached phy */
1964 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1965 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1966 continue;
1967 if (dev_id--)
1968 continue;
1969 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1970 break;
1971 }
1972
1973 if (phy_id >= PHY_MAX_ADDR) {
1974 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1975 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1976 phy_id = 0;
1977 }
1978
1979 snprintf(phy_name, sizeof(phy_name),
1980 PHY_ID_FMT, mdio_bus_id, phy_id);
1981 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1982 fep->phy_interface);
1983 }
1984
1985 if (IS_ERR(phy_dev)) {
1986 netdev_err(ndev, "could not attach to PHY\n");
1987 return PTR_ERR(phy_dev);
1988 }
1989
1990 /* mask with MAC supported features */
1991 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1992 phy_set_max_speed(phy_dev, 1000);
1993 phy_remove_link_mode(phy_dev,
1994 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1995#if !defined(CONFIG_M5272)
1996 phy_support_sym_pause(phy_dev);
1997#endif
1998 }
1999 else
2000 phy_set_max_speed(phy_dev, 100);
2001
2002 fep->link = 0;
2003 fep->full_duplex = 0;
2004
2005 phy_attached_info(phy_dev);
2006
2007 return 0;
2008}
2009
2010static int fec_enet_mii_init(struct platform_device *pdev)
2011{
2012 static struct mii_bus *fec0_mii_bus;
2013 struct net_device *ndev = platform_get_drvdata(pdev);
2014 struct fec_enet_private *fep = netdev_priv(ndev);
2015 struct device_node *node;
2016 int err = -ENXIO;
2017 u32 mii_speed, holdtime;
2018
2019 /*
2020 * The i.MX28 dual fec interfaces are not equal.
2021 * Here are the differences:
2022 *
2023 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2024 * - fec0 acts as the 1588 time master while fec1 is slave
2025 * - external phys can only be configured by fec0
2026 *
2027 * That is to say fec1 can not work independently. It only works
2028 * when fec0 is working. The reason behind this design is that the
2029 * second interface is added primarily for Switch mode.
2030 *
2031 * Because of the last point above, both phys are attached on fec0
2032 * mdio interface in board design, and need to be configured by
2033 * fec0 mii_bus.
2034 */
2035 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2036 /* fec1 uses fec0 mii_bus */
2037 if (mii_cnt && fec0_mii_bus) {
2038 fep->mii_bus = fec0_mii_bus;
2039 mii_cnt++;
2040 return 0;
2041 }
2042 return -ENOENT;
2043 }
2044
2045 /*
2046 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2047 *
2048 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2049 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2050 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2051 * document.
2052 */
2053 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2054 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2055 mii_speed--;
2056 if (mii_speed > 63) {
2057 dev_err(&pdev->dev,
2058 "fec clock (%lu) too fast to get right mii speed\n",
2059 clk_get_rate(fep->clk_ipg));
2060 err = -EINVAL;
2061 goto err_out;
2062 }
2063
2064 /*
2065 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2066 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2067 * versions are RAZ there, so just ignore the difference and write the
2068 * register always.
2069 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2070 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2071 * output.
2072 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2073 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2074 * holdtime cannot result in a value greater than 3.
2075 */
2076 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2077
2078 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2079
2080 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2081
2082 fep->mii_bus = mdiobus_alloc();
2083 if (fep->mii_bus == NULL) {
2084 err = -ENOMEM;
2085 goto err_out;
2086 }
2087
2088 fep->mii_bus->name = "fec_enet_mii_bus";
2089 fep->mii_bus->read = fec_enet_mdio_read;
2090 fep->mii_bus->write = fec_enet_mdio_write;
2091 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2092 pdev->name, fep->dev_id + 1);
2093 fep->mii_bus->priv = fep;
2094 fep->mii_bus->parent = &pdev->dev;
2095
2096 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2097 err = of_mdiobus_register(fep->mii_bus, node);
2098 of_node_put(node);
2099 if (err)
2100 goto err_out_free_mdiobus;
2101
2102 mii_cnt++;
2103
2104 /* save fec0 mii_bus */
2105 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2106 fec0_mii_bus = fep->mii_bus;
2107
2108 return 0;
2109
2110err_out_free_mdiobus:
2111 mdiobus_free(fep->mii_bus);
2112err_out:
2113 return err;
2114}
2115
2116static void fec_enet_mii_remove(struct fec_enet_private *fep)
2117{
2118 if (--mii_cnt == 0) {
2119 mdiobus_unregister(fep->mii_bus);
2120 mdiobus_free(fep->mii_bus);
2121 }
2122}
2123
2124static void fec_enet_get_drvinfo(struct net_device *ndev,
2125 struct ethtool_drvinfo *info)
2126{
2127 struct fec_enet_private *fep = netdev_priv(ndev);
2128
2129 strlcpy(info->driver, fep->pdev->dev.driver->name,
2130 sizeof(info->driver));
2131 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2132 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2133}
2134
2135static int fec_enet_get_regs_len(struct net_device *ndev)
2136{
2137 struct fec_enet_private *fep = netdev_priv(ndev);
2138 struct resource *r;
2139 int s = 0;
2140
2141 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2142 if (r)
2143 s = resource_size(r);
2144
2145 return s;
2146}
2147
2148/* List of registers that can be safety be read to dump them with ethtool */
2149#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2150 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2151 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2152static __u32 fec_enet_register_version = 2;
2153static u32 fec_enet_register_offset[] = {
2154 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2155 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2156 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2157 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2158 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2159 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2160 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2161 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2162 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2163 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2164 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2165 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2166 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2167 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2168 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2169 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2170 RMON_T_P_GTE2048, RMON_T_OCTETS,
2171 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2172 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2173 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2174 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2175 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2176 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2177 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2178 RMON_R_P_GTE2048, RMON_R_OCTETS,
2179 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2180 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2181};
2182#else
2183static __u32 fec_enet_register_version = 1;
2184static u32 fec_enet_register_offset[] = {
2185 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2186 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2187 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2188 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2189 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2190 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2191 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2192 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2193 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2194};
2195#endif
2196
2197static void fec_enet_get_regs(struct net_device *ndev,
2198 struct ethtool_regs *regs, void *regbuf)
2199{
2200 struct fec_enet_private *fep = netdev_priv(ndev);
2201 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2202 u32 *buf = (u32 *)regbuf;
2203 u32 i, off;
2204
2205 regs->version = fec_enet_register_version;
2206
2207 memset(buf, 0, regs->len);
2208
2209 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2210 off = fec_enet_register_offset[i];
2211
2212 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2213 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2214 continue;
2215
2216 off >>= 2;
2217 buf[off] = readl(&theregs[off]);
2218 }
2219}
2220
2221static int fec_enet_get_ts_info(struct net_device *ndev,
2222 struct ethtool_ts_info *info)
2223{
2224 struct fec_enet_private *fep = netdev_priv(ndev);
2225
2226 if (fep->bufdesc_ex) {
2227
2228 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2229 SOF_TIMESTAMPING_RX_SOFTWARE |
2230 SOF_TIMESTAMPING_SOFTWARE |
2231 SOF_TIMESTAMPING_TX_HARDWARE |
2232 SOF_TIMESTAMPING_RX_HARDWARE |
2233 SOF_TIMESTAMPING_RAW_HARDWARE;
2234 if (fep->ptp_clock)
2235 info->phc_index = ptp_clock_index(fep->ptp_clock);
2236 else
2237 info->phc_index = -1;
2238
2239 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2240 (1 << HWTSTAMP_TX_ON);
2241
2242 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2243 (1 << HWTSTAMP_FILTER_ALL);
2244 return 0;
2245 } else {
2246 return ethtool_op_get_ts_info(ndev, info);
2247 }
2248}
2249
2250#if !defined(CONFIG_M5272)
2251
2252static void fec_enet_get_pauseparam(struct net_device *ndev,
2253 struct ethtool_pauseparam *pause)
2254{
2255 struct fec_enet_private *fep = netdev_priv(ndev);
2256
2257 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2258 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2259 pause->rx_pause = pause->tx_pause;
2260}
2261
2262static int fec_enet_set_pauseparam(struct net_device *ndev,
2263 struct ethtool_pauseparam *pause)
2264{
2265 struct fec_enet_private *fep = netdev_priv(ndev);
2266
2267 if (!ndev->phydev)
2268 return -ENODEV;
2269
2270 if (pause->tx_pause != pause->rx_pause) {
2271 netdev_info(ndev,
2272 "hardware only support enable/disable both tx and rx");
2273 return -EINVAL;
2274 }
2275
2276 fep->pause_flag = 0;
2277
2278 /* tx pause must be same as rx pause */
2279 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2280 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2281
2282 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2283 pause->autoneg);
2284
2285 if (pause->autoneg) {
2286 if (netif_running(ndev))
2287 fec_stop(ndev);
2288 phy_start_aneg(ndev->phydev);
2289 }
2290 if (netif_running(ndev)) {
2291 napi_disable(&fep->napi);
2292 netif_tx_lock_bh(ndev);
2293 fec_restart(ndev);
2294 netif_tx_wake_all_queues(ndev);
2295 netif_tx_unlock_bh(ndev);
2296 napi_enable(&fep->napi);
2297 }
2298
2299 return 0;
2300}
2301
2302static const struct fec_stat {
2303 char name[ETH_GSTRING_LEN];
2304 u16 offset;
2305} fec_stats[] = {
2306 /* RMON TX */
2307 { "tx_dropped", RMON_T_DROP },
2308 { "tx_packets", RMON_T_PACKETS },
2309 { "tx_broadcast", RMON_T_BC_PKT },
2310 { "tx_multicast", RMON_T_MC_PKT },
2311 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2312 { "tx_undersize", RMON_T_UNDERSIZE },
2313 { "tx_oversize", RMON_T_OVERSIZE },
2314 { "tx_fragment", RMON_T_FRAG },
2315 { "tx_jabber", RMON_T_JAB },
2316 { "tx_collision", RMON_T_COL },
2317 { "tx_64byte", RMON_T_P64 },
2318 { "tx_65to127byte", RMON_T_P65TO127 },
2319 { "tx_128to255byte", RMON_T_P128TO255 },
2320 { "tx_256to511byte", RMON_T_P256TO511 },
2321 { "tx_512to1023byte", RMON_T_P512TO1023 },
2322 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2323 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2324 { "tx_octets", RMON_T_OCTETS },
2325
2326 /* IEEE TX */
2327 { "IEEE_tx_drop", IEEE_T_DROP },
2328 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2329 { "IEEE_tx_1col", IEEE_T_1COL },
2330 { "IEEE_tx_mcol", IEEE_T_MCOL },
2331 { "IEEE_tx_def", IEEE_T_DEF },
2332 { "IEEE_tx_lcol", IEEE_T_LCOL },
2333 { "IEEE_tx_excol", IEEE_T_EXCOL },
2334 { "IEEE_tx_macerr", IEEE_T_MACERR },
2335 { "IEEE_tx_cserr", IEEE_T_CSERR },
2336 { "IEEE_tx_sqe", IEEE_T_SQE },
2337 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2338 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2339
2340 /* RMON RX */
2341 { "rx_packets", RMON_R_PACKETS },
2342 { "rx_broadcast", RMON_R_BC_PKT },
2343 { "rx_multicast", RMON_R_MC_PKT },
2344 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2345 { "rx_undersize", RMON_R_UNDERSIZE },
2346 { "rx_oversize", RMON_R_OVERSIZE },
2347 { "rx_fragment", RMON_R_FRAG },
2348 { "rx_jabber", RMON_R_JAB },
2349 { "rx_64byte", RMON_R_P64 },
2350 { "rx_65to127byte", RMON_R_P65TO127 },
2351 { "rx_128to255byte", RMON_R_P128TO255 },
2352 { "rx_256to511byte", RMON_R_P256TO511 },
2353 { "rx_512to1023byte", RMON_R_P512TO1023 },
2354 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2355 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2356 { "rx_octets", RMON_R_OCTETS },
2357
2358 /* IEEE RX */
2359 { "IEEE_rx_drop", IEEE_R_DROP },
2360 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2361 { "IEEE_rx_crc", IEEE_R_CRC },
2362 { "IEEE_rx_align", IEEE_R_ALIGN },
2363 { "IEEE_rx_macerr", IEEE_R_MACERR },
2364 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2365 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2366};
2367
2368#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2369
2370static void fec_enet_update_ethtool_stats(struct net_device *dev)
2371{
2372 struct fec_enet_private *fep = netdev_priv(dev);
2373 int i;
2374
2375 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2376 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2377}
2378
2379static void fec_enet_get_ethtool_stats(struct net_device *dev,
2380 struct ethtool_stats *stats, u64 *data)
2381{
2382 struct fec_enet_private *fep = netdev_priv(dev);
2383
2384 if (netif_running(dev))
2385 fec_enet_update_ethtool_stats(dev);
2386
2387 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2388}
2389
2390static void fec_enet_get_strings(struct net_device *netdev,
2391 u32 stringset, u8 *data)
2392{
2393 int i;
2394 switch (stringset) {
2395 case ETH_SS_STATS:
2396 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2397 memcpy(data + i * ETH_GSTRING_LEN,
2398 fec_stats[i].name, ETH_GSTRING_LEN);
2399 break;
2400 }
2401}
2402
2403static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2404{
2405 switch (sset) {
2406 case ETH_SS_STATS:
2407 return ARRAY_SIZE(fec_stats);
2408 default:
2409 return -EOPNOTSUPP;
2410 }
2411}
2412
2413static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2414{
2415 struct fec_enet_private *fep = netdev_priv(dev);
2416 int i;
2417
2418 /* Disable MIB statistics counters */
2419 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2420
2421 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2422 writel(0, fep->hwp + fec_stats[i].offset);
2423
2424 /* Don't disable MIB statistics counters */
2425 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2426}
2427
2428#else /* !defined(CONFIG_M5272) */
2429#define FEC_STATS_SIZE 0
2430static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2431{
2432}
2433
2434static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2435{
2436}
2437#endif /* !defined(CONFIG_M5272) */
2438
2439/* ITR clock source is enet system clock (clk_ahb).
2440 * TCTT unit is cycle_ns * 64 cycle
2441 * So, the ICTT value = X us / (cycle_ns * 64)
2442 */
2443static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2444{
2445 struct fec_enet_private *fep = netdev_priv(ndev);
2446
2447 return us * (fep->itr_clk_rate / 64000) / 1000;
2448}
2449
2450/* Set threshold for interrupt coalescing */
2451static void fec_enet_itr_coal_set(struct net_device *ndev)
2452{
2453 struct fec_enet_private *fep = netdev_priv(ndev);
2454 int rx_itr, tx_itr;
2455
2456 /* Must be greater than zero to avoid unpredictable behavior */
2457 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2458 !fep->tx_time_itr || !fep->tx_pkts_itr)
2459 return;
2460
2461 /* Select enet system clock as Interrupt Coalescing
2462 * timer Clock Source
2463 */
2464 rx_itr = FEC_ITR_CLK_SEL;
2465 tx_itr = FEC_ITR_CLK_SEL;
2466
2467 /* set ICFT and ICTT */
2468 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2469 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2470 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2471 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2472
2473 rx_itr |= FEC_ITR_EN;
2474 tx_itr |= FEC_ITR_EN;
2475
2476 writel(tx_itr, fep->hwp + FEC_TXIC0);
2477 writel(rx_itr, fep->hwp + FEC_RXIC0);
2478 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2479 writel(tx_itr, fep->hwp + FEC_TXIC1);
2480 writel(rx_itr, fep->hwp + FEC_RXIC1);
2481 writel(tx_itr, fep->hwp + FEC_TXIC2);
2482 writel(rx_itr, fep->hwp + FEC_RXIC2);
2483 }
2484}
2485
2486static int
2487fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2488{
2489 struct fec_enet_private *fep = netdev_priv(ndev);
2490
2491 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2492 return -EOPNOTSUPP;
2493
2494 ec->rx_coalesce_usecs = fep->rx_time_itr;
2495 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2496
2497 ec->tx_coalesce_usecs = fep->tx_time_itr;
2498 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2499
2500 return 0;
2501}
2502
2503static int
2504fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2505{
2506 struct fec_enet_private *fep = netdev_priv(ndev);
2507 struct device *dev = &fep->pdev->dev;
2508 unsigned int cycle;
2509
2510 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2511 return -EOPNOTSUPP;
2512
2513 if (ec->rx_max_coalesced_frames > 255) {
2514 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
2515 return -EINVAL;
2516 }
2517
2518 if (ec->tx_max_coalesced_frames > 255) {
2519 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
2520 return -EINVAL;
2521 }
2522
2523 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2524 if (cycle > 0xFFFF) {
2525 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
2526 return -EINVAL;
2527 }
2528
2529 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2530 if (cycle > 0xFFFF) {
2531 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
2532 return -EINVAL;
2533 }
2534
2535 fep->rx_time_itr = ec->rx_coalesce_usecs;
2536 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2537
2538 fep->tx_time_itr = ec->tx_coalesce_usecs;
2539 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2540
2541 fec_enet_itr_coal_set(ndev);
2542
2543 return 0;
2544}
2545
2546static void fec_enet_itr_coal_init(struct net_device *ndev)
2547{
2548 struct ethtool_coalesce ec;
2549
2550 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2551 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2552
2553 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2554 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2555
2556 fec_enet_set_coalesce(ndev, &ec);
2557}
2558
2559static int fec_enet_get_tunable(struct net_device *netdev,
2560 const struct ethtool_tunable *tuna,
2561 void *data)
2562{
2563 struct fec_enet_private *fep = netdev_priv(netdev);
2564 int ret = 0;
2565
2566 switch (tuna->id) {
2567 case ETHTOOL_RX_COPYBREAK:
2568 *(u32 *)data = fep->rx_copybreak;
2569 break;
2570 default:
2571 ret = -EINVAL;
2572 break;
2573 }
2574
2575 return ret;
2576}
2577
2578static int fec_enet_set_tunable(struct net_device *netdev,
2579 const struct ethtool_tunable *tuna,
2580 const void *data)
2581{
2582 struct fec_enet_private *fep = netdev_priv(netdev);
2583 int ret = 0;
2584
2585 switch (tuna->id) {
2586 case ETHTOOL_RX_COPYBREAK:
2587 fep->rx_copybreak = *(u32 *)data;
2588 break;
2589 default:
2590 ret = -EINVAL;
2591 break;
2592 }
2593
2594 return ret;
2595}
2596
2597static void
2598fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2599{
2600 struct fec_enet_private *fep = netdev_priv(ndev);
2601
2602 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2603 wol->supported = WAKE_MAGIC;
2604 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2605 } else {
2606 wol->supported = wol->wolopts = 0;
2607 }
2608}
2609
2610static int
2611fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2612{
2613 struct fec_enet_private *fep = netdev_priv(ndev);
2614
2615 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2616 return -EINVAL;
2617
2618 if (wol->wolopts & ~WAKE_MAGIC)
2619 return -EINVAL;
2620
2621 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2622 if (device_may_wakeup(&ndev->dev)) {
2623 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2624 if (fep->irq[0] > 0)
2625 enable_irq_wake(fep->irq[0]);
2626 } else {
2627 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2628 if (fep->irq[0] > 0)
2629 disable_irq_wake(fep->irq[0]);
2630 }
2631
2632 return 0;
2633}
2634
2635static const struct ethtool_ops fec_enet_ethtool_ops = {
2636 .get_drvinfo = fec_enet_get_drvinfo,
2637 .get_regs_len = fec_enet_get_regs_len,
2638 .get_regs = fec_enet_get_regs,
2639 .nway_reset = phy_ethtool_nway_reset,
2640 .get_link = ethtool_op_get_link,
2641 .get_coalesce = fec_enet_get_coalesce,
2642 .set_coalesce = fec_enet_set_coalesce,
2643#ifndef CONFIG_M5272
2644 .get_pauseparam = fec_enet_get_pauseparam,
2645 .set_pauseparam = fec_enet_set_pauseparam,
2646 .get_strings = fec_enet_get_strings,
2647 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2648 .get_sset_count = fec_enet_get_sset_count,
2649#endif
2650 .get_ts_info = fec_enet_get_ts_info,
2651 .get_tunable = fec_enet_get_tunable,
2652 .set_tunable = fec_enet_set_tunable,
2653 .get_wol = fec_enet_get_wol,
2654 .set_wol = fec_enet_set_wol,
2655 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2656 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2657};
2658
2659static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2660{
2661 struct fec_enet_private *fep = netdev_priv(ndev);
2662 struct phy_device *phydev = ndev->phydev;
2663
2664 if (!netif_running(ndev))
2665 return -EINVAL;
2666
2667 if (!phydev)
2668 return -ENODEV;
2669
2670 if (fep->bufdesc_ex) {
2671 if (cmd == SIOCSHWTSTAMP)
2672 return fec_ptp_set(ndev, rq);
2673 if (cmd == SIOCGHWTSTAMP)
2674 return fec_ptp_get(ndev, rq);
2675 }
2676
2677 return phy_mii_ioctl(phydev, rq, cmd);
2678}
2679
2680static void fec_enet_free_buffers(struct net_device *ndev)
2681{
2682 struct fec_enet_private *fep = netdev_priv(ndev);
2683 unsigned int i;
2684 struct sk_buff *skb;
2685 struct bufdesc *bdp;
2686 struct fec_enet_priv_tx_q *txq;
2687 struct fec_enet_priv_rx_q *rxq;
2688 unsigned int q;
2689
2690 for (q = 0; q < fep->num_rx_queues; q++) {
2691 rxq = fep->rx_queue[q];
2692 bdp = rxq->bd.base;
2693 for (i = 0; i < rxq->bd.ring_size; i++) {
2694 skb = rxq->rx_skbuff[i];
2695 rxq->rx_skbuff[i] = NULL;
2696 if (skb) {
2697 dma_unmap_single(&fep->pdev->dev,
2698 fec32_to_cpu(bdp->cbd_bufaddr),
2699 FEC_ENET_RX_FRSIZE - fep->rx_align,
2700 DMA_FROM_DEVICE);
2701 dev_kfree_skb(skb);
2702 }
2703 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2704 }
2705 }
2706
2707 for (q = 0; q < fep->num_tx_queues; q++) {
2708 txq = fep->tx_queue[q];
2709 bdp = txq->bd.base;
2710 for (i = 0; i < txq->bd.ring_size; i++) {
2711 kfree(txq->tx_bounce[i]);
2712 txq->tx_bounce[i] = NULL;
2713 skb = txq->tx_skbuff[i];
2714 txq->tx_skbuff[i] = NULL;
2715 dev_kfree_skb(skb);
2716 }
2717 }
2718}
2719
2720static void fec_enet_free_queue(struct net_device *ndev)
2721{
2722 struct fec_enet_private *fep = netdev_priv(ndev);
2723 int i;
2724 struct fec_enet_priv_tx_q *txq;
2725
2726 for (i = 0; i < fep->num_tx_queues; i++)
2727 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2728 txq = fep->tx_queue[i];
2729 dma_free_coherent(&fep->pdev->dev,
2730 txq->bd.ring_size * TSO_HEADER_SIZE,
2731 txq->tso_hdrs,
2732 txq->tso_hdrs_dma);
2733 }
2734
2735 for (i = 0; i < fep->num_rx_queues; i++)
2736 kfree(fep->rx_queue[i]);
2737 for (i = 0; i < fep->num_tx_queues; i++)
2738 kfree(fep->tx_queue[i]);
2739}
2740
2741static int fec_enet_alloc_queue(struct net_device *ndev)
2742{
2743 struct fec_enet_private *fep = netdev_priv(ndev);
2744 int i;
2745 int ret = 0;
2746 struct fec_enet_priv_tx_q *txq;
2747
2748 for (i = 0; i < fep->num_tx_queues; i++) {
2749 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2750 if (!txq) {
2751 ret = -ENOMEM;
2752 goto alloc_failed;
2753 }
2754
2755 fep->tx_queue[i] = txq;
2756 txq->bd.ring_size = TX_RING_SIZE;
2757 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2758
2759 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2760 txq->tx_wake_threshold =
2761 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2762
2763 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2764 txq->bd.ring_size * TSO_HEADER_SIZE,
2765 &txq->tso_hdrs_dma,
2766 GFP_KERNEL);
2767 if (!txq->tso_hdrs) {
2768 ret = -ENOMEM;
2769 goto alloc_failed;
2770 }
2771 }
2772
2773 for (i = 0; i < fep->num_rx_queues; i++) {
2774 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2775 GFP_KERNEL);
2776 if (!fep->rx_queue[i]) {
2777 ret = -ENOMEM;
2778 goto alloc_failed;
2779 }
2780
2781 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2782 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2783 }
2784 return ret;
2785
2786alloc_failed:
2787 fec_enet_free_queue(ndev);
2788 return ret;
2789}
2790
2791static int
2792fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2793{
2794 struct fec_enet_private *fep = netdev_priv(ndev);
2795 unsigned int i;
2796 struct sk_buff *skb;
2797 struct bufdesc *bdp;
2798 struct fec_enet_priv_rx_q *rxq;
2799
2800 rxq = fep->rx_queue[queue];
2801 bdp = rxq->bd.base;
2802 for (i = 0; i < rxq->bd.ring_size; i++) {
2803 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2804 if (!skb)
2805 goto err_alloc;
2806
2807 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2808 dev_kfree_skb(skb);
2809 goto err_alloc;
2810 }
2811
2812 rxq->rx_skbuff[i] = skb;
2813 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2814
2815 if (fep->bufdesc_ex) {
2816 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2817 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2818 }
2819
2820 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2821 }
2822
2823 /* Set the last buffer to wrap. */
2824 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2825 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2826 return 0;
2827
2828 err_alloc:
2829 fec_enet_free_buffers(ndev);
2830 return -ENOMEM;
2831}
2832
2833static int
2834fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2835{
2836 struct fec_enet_private *fep = netdev_priv(ndev);
2837 unsigned int i;
2838 struct bufdesc *bdp;
2839 struct fec_enet_priv_tx_q *txq;
2840
2841 txq = fep->tx_queue[queue];
2842 bdp = txq->bd.base;
2843 for (i = 0; i < txq->bd.ring_size; i++) {
2844 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2845 if (!txq->tx_bounce[i])
2846 goto err_alloc;
2847
2848 bdp->cbd_sc = cpu_to_fec16(0);
2849 bdp->cbd_bufaddr = cpu_to_fec32(0);
2850
2851 if (fep->bufdesc_ex) {
2852 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2853 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2854 }
2855
2856 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2857 }
2858
2859 /* Set the last buffer to wrap. */
2860 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2861 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2862
2863 return 0;
2864
2865 err_alloc:
2866 fec_enet_free_buffers(ndev);
2867 return -ENOMEM;
2868}
2869
2870static int fec_enet_alloc_buffers(struct net_device *ndev)
2871{
2872 struct fec_enet_private *fep = netdev_priv(ndev);
2873 unsigned int i;
2874
2875 for (i = 0; i < fep->num_rx_queues; i++)
2876 if (fec_enet_alloc_rxq_buffers(ndev, i))
2877 return -ENOMEM;
2878
2879 for (i = 0; i < fep->num_tx_queues; i++)
2880 if (fec_enet_alloc_txq_buffers(ndev, i))
2881 return -ENOMEM;
2882 return 0;
2883}
2884
2885static int
2886fec_enet_open(struct net_device *ndev)
2887{
2888 struct fec_enet_private *fep = netdev_priv(ndev);
2889 int ret;
2890 bool reset_again;
2891
2892 ret = pm_runtime_get_sync(&fep->pdev->dev);
2893 if (ret < 0)
2894 return ret;
2895
2896 pinctrl_pm_select_default_state(&fep->pdev->dev);
2897 ret = fec_enet_clk_enable(ndev, true);
2898 if (ret)
2899 goto clk_enable;
2900
2901 /* During the first fec_enet_open call the PHY isn't probed at this
2902 * point. Therefore the phy_reset_after_clk_enable() call within
2903 * fec_enet_clk_enable() fails. As we need this reset in order to be
2904 * sure the PHY is working correctly we check if we need to reset again
2905 * later when the PHY is probed
2906 */
2907 if (ndev->phydev && ndev->phydev->drv)
2908 reset_again = false;
2909 else
2910 reset_again = true;
2911
2912 /* I should reset the ring buffers here, but I don't yet know
2913 * a simple way to do that.
2914 */
2915
2916 ret = fec_enet_alloc_buffers(ndev);
2917 if (ret)
2918 goto err_enet_alloc;
2919
2920 /* Init MAC prior to mii bus probe */
2921 fec_restart(ndev);
2922
2923 /* Probe and connect to PHY when open the interface */
2924 ret = fec_enet_mii_probe(ndev);
2925 if (ret)
2926 goto err_enet_mii_probe;
2927
2928 /* Call phy_reset_after_clk_enable() again if it failed during
2929 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
2930 */
2931 if (reset_again)
2932 phy_reset_after_clk_enable(ndev->phydev);
2933
2934 if (fep->quirks & FEC_QUIRK_ERR006687)
2935 imx6q_cpuidle_fec_irqs_used();
2936
2937 napi_enable(&fep->napi);
2938 phy_start(ndev->phydev);
2939 netif_tx_start_all_queues(ndev);
2940
2941 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2942 FEC_WOL_FLAG_ENABLE);
2943
2944 return 0;
2945
2946err_enet_mii_probe:
2947 fec_enet_free_buffers(ndev);
2948err_enet_alloc:
2949 fec_enet_clk_enable(ndev, false);
2950clk_enable:
2951 pm_runtime_mark_last_busy(&fep->pdev->dev);
2952 pm_runtime_put_autosuspend(&fep->pdev->dev);
2953 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2954 return ret;
2955}
2956
2957static int
2958fec_enet_close(struct net_device *ndev)
2959{
2960 struct fec_enet_private *fep = netdev_priv(ndev);
2961
2962 phy_stop(ndev->phydev);
2963
2964 if (netif_device_present(ndev)) {
2965 napi_disable(&fep->napi);
2966 netif_tx_disable(ndev);
2967 fec_stop(ndev);
2968 }
2969
2970 phy_disconnect(ndev->phydev);
2971
2972 if (fep->quirks & FEC_QUIRK_ERR006687)
2973 imx6q_cpuidle_fec_irqs_unused();
2974
2975 fec_enet_update_ethtool_stats(ndev);
2976
2977 fec_enet_clk_enable(ndev, false);
2978 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2979 pm_runtime_mark_last_busy(&fep->pdev->dev);
2980 pm_runtime_put_autosuspend(&fep->pdev->dev);
2981
2982 fec_enet_free_buffers(ndev);
2983
2984 return 0;
2985}
2986
2987/* Set or clear the multicast filter for this adaptor.
2988 * Skeleton taken from sunlance driver.
2989 * The CPM Ethernet implementation allows Multicast as well as individual
2990 * MAC address filtering. Some of the drivers check to make sure it is
2991 * a group multicast address, and discard those that are not. I guess I
2992 * will do the same for now, but just remove the test if you want
2993 * individual filtering as well (do the upper net layers want or support
2994 * this kind of feature?).
2995 */
2996
2997#define FEC_HASH_BITS 6 /* #bits in hash */
2998
2999static void set_multicast_list(struct net_device *ndev)
3000{
3001 struct fec_enet_private *fep = netdev_priv(ndev);
3002 struct netdev_hw_addr *ha;
3003 unsigned int crc, tmp;
3004 unsigned char hash;
3005 unsigned int hash_high = 0, hash_low = 0;
3006
3007 if (ndev->flags & IFF_PROMISC) {
3008 tmp = readl(fep->hwp + FEC_R_CNTRL);
3009 tmp |= 0x8;
3010 writel(tmp, fep->hwp + FEC_R_CNTRL);
3011 return;
3012 }
3013
3014 tmp = readl(fep->hwp + FEC_R_CNTRL);
3015 tmp &= ~0x8;
3016 writel(tmp, fep->hwp + FEC_R_CNTRL);
3017
3018 if (ndev->flags & IFF_ALLMULTI) {
3019 /* Catch all multicast addresses, so set the
3020 * filter to all 1's
3021 */
3022 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3023 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3024
3025 return;
3026 }
3027
3028 /* Add the addresses in hash register */
3029 netdev_for_each_mc_addr(ha, ndev) {
3030 /* calculate crc32 value of mac address */
3031 crc = ether_crc_le(ndev->addr_len, ha->addr);
3032
3033 /* only upper 6 bits (FEC_HASH_BITS) are used
3034 * which point to specific bit in the hash registers
3035 */
3036 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3037
3038 if (hash > 31)
3039 hash_high |= 1 << (hash - 32);
3040 else
3041 hash_low |= 1 << hash;
3042 }
3043
3044 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3045 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3046}
3047
3048/* Set a MAC change in hardware. */
3049static int
3050fec_set_mac_address(struct net_device *ndev, void *p)
3051{
3052 struct fec_enet_private *fep = netdev_priv(ndev);
3053 struct sockaddr *addr = p;
3054
3055 if (addr) {
3056 if (!is_valid_ether_addr(addr->sa_data))
3057 return -EADDRNOTAVAIL;
3058 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3059 }
3060
3061 /* Add netif status check here to avoid system hang in below case:
3062 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3063 * After ethx down, fec all clocks are gated off and then register
3064 * access causes system hang.
3065 */
3066 if (!netif_running(ndev))
3067 return 0;
3068
3069 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3070 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3071 fep->hwp + FEC_ADDR_LOW);
3072 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3073 fep->hwp + FEC_ADDR_HIGH);
3074 return 0;
3075}
3076
3077#ifdef CONFIG_NET_POLL_CONTROLLER
3078/**
3079 * fec_poll_controller - FEC Poll controller function
3080 * @dev: The FEC network adapter
3081 *
3082 * Polled functionality used by netconsole and others in non interrupt mode
3083 *
3084 */
3085static void fec_poll_controller(struct net_device *dev)
3086{
3087 int i;
3088 struct fec_enet_private *fep = netdev_priv(dev);
3089
3090 for (i = 0; i < FEC_IRQ_NUM; i++) {
3091 if (fep->irq[i] > 0) {
3092 disable_irq(fep->irq[i]);
3093 fec_enet_interrupt(fep->irq[i], dev);
3094 enable_irq(fep->irq[i]);
3095 }
3096 }
3097}
3098#endif
3099
3100static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3101 netdev_features_t features)
3102{
3103 struct fec_enet_private *fep = netdev_priv(netdev);
3104 netdev_features_t changed = features ^ netdev->features;
3105
3106 netdev->features = features;
3107
3108 /* Receive checksum has been changed */
3109 if (changed & NETIF_F_RXCSUM) {
3110 if (features & NETIF_F_RXCSUM)
3111 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3112 else
3113 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3114 }
3115}
3116
3117static int fec_set_features(struct net_device *netdev,
3118 netdev_features_t features)
3119{
3120 struct fec_enet_private *fep = netdev_priv(netdev);
3121 netdev_features_t changed = features ^ netdev->features;
3122
3123 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3124 napi_disable(&fep->napi);
3125 netif_tx_lock_bh(netdev);
3126 fec_stop(netdev);
3127 fec_enet_set_netdev_features(netdev, features);
3128 fec_restart(netdev);
3129 netif_tx_wake_all_queues(netdev);
3130 netif_tx_unlock_bh(netdev);
3131 napi_enable(&fep->napi);
3132 } else {
3133 fec_enet_set_netdev_features(netdev, features);
3134 }
3135
3136 return 0;
3137}
3138
3139static const struct net_device_ops fec_netdev_ops = {
3140 .ndo_open = fec_enet_open,
3141 .ndo_stop = fec_enet_close,
3142 .ndo_start_xmit = fec_enet_start_xmit,
3143 .ndo_set_rx_mode = set_multicast_list,
3144 .ndo_validate_addr = eth_validate_addr,
3145 .ndo_tx_timeout = fec_timeout,
3146 .ndo_set_mac_address = fec_set_mac_address,
3147 .ndo_do_ioctl = fec_enet_ioctl,
3148#ifdef CONFIG_NET_POLL_CONTROLLER
3149 .ndo_poll_controller = fec_poll_controller,
3150#endif
3151 .ndo_set_features = fec_set_features,
3152};
3153
3154static const unsigned short offset_des_active_rxq[] = {
3155 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3156};
3157
3158static const unsigned short offset_des_active_txq[] = {
3159 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3160};
3161
3162 /*
3163 * XXX: We need to clean up on failure exits here.
3164 *
3165 */
3166static int fec_enet_init(struct net_device *ndev)
3167{
3168 struct fec_enet_private *fep = netdev_priv(ndev);
3169 struct bufdesc *cbd_base;
3170 dma_addr_t bd_dma;
3171 int bd_size;
3172 unsigned int i;
3173 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3174 sizeof(struct bufdesc);
3175 unsigned dsize_log2 = __fls(dsize);
3176 int ret;
3177
3178 WARN_ON(dsize != (1 << dsize_log2));
3179#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3180 fep->rx_align = 0xf;
3181 fep->tx_align = 0xf;
3182#else
3183 fep->rx_align = 0x3;
3184 fep->tx_align = 0x3;
3185#endif
3186
3187 /* Check mask of the streaming and coherent API */
3188 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3189 if (ret < 0) {
3190 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3191 return ret;
3192 }
3193
3194 fec_enet_alloc_queue(ndev);
3195
3196 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3197
3198 /* Allocate memory for buffer descriptors. */
3199 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3200 GFP_KERNEL);
3201 if (!cbd_base) {
3202 return -ENOMEM;
3203 }
3204
3205 /* Get the Ethernet address */
3206 fec_get_mac(ndev);
3207 /* make sure MAC we just acquired is programmed into the hw */
3208 fec_set_mac_address(ndev, NULL);
3209
3210 /* Set receive and transmit descriptor base. */
3211 for (i = 0; i < fep->num_rx_queues; i++) {
3212 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3213 unsigned size = dsize * rxq->bd.ring_size;
3214
3215 rxq->bd.qid = i;
3216 rxq->bd.base = cbd_base;
3217 rxq->bd.cur = cbd_base;
3218 rxq->bd.dma = bd_dma;
3219 rxq->bd.dsize = dsize;
3220 rxq->bd.dsize_log2 = dsize_log2;
3221 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3222 bd_dma += size;
3223 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3224 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3225 }
3226
3227 for (i = 0; i < fep->num_tx_queues; i++) {
3228 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3229 unsigned size = dsize * txq->bd.ring_size;
3230
3231 txq->bd.qid = i;
3232 txq->bd.base = cbd_base;
3233 txq->bd.cur = cbd_base;
3234 txq->bd.dma = bd_dma;
3235 txq->bd.dsize = dsize;
3236 txq->bd.dsize_log2 = dsize_log2;
3237 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3238 bd_dma += size;
3239 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3240 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3241 }
3242
3243
3244 /* The FEC Ethernet specific entries in the device structure */
3245 ndev->watchdog_timeo = TX_TIMEOUT;
3246 ndev->netdev_ops = &fec_netdev_ops;
3247 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3248
3249 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3250 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3251
3252 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3253 /* enable hw VLAN support */
3254 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3255
3256 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3257 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3258
3259 /* enable hw accelerator */
3260 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3261 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3262 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3263 }
3264
3265 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3266 fep->tx_align = 0;
3267 fep->rx_align = 0x3f;
3268 }
3269
3270 ndev->hw_features = ndev->features;
3271
3272 fec_restart(ndev);
3273
3274 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3275 fec_enet_clear_ethtool_stats(ndev);
3276 else
3277 fec_enet_update_ethtool_stats(ndev);
3278
3279 return 0;
3280}
3281
3282#ifdef CONFIG_OF
3283static int fec_reset_phy(struct platform_device *pdev)
3284{
3285 int err, phy_reset;
3286 bool active_high = false;
3287 int msec = 1, phy_post_delay = 0;
3288 struct device_node *np = pdev->dev.of_node;
3289
3290 if (!np)
3291 return 0;
3292
3293 err = of_property_read_u32(np, "phy-reset-duration", &msec);
3294 /* A sane reset duration should not be longer than 1s */
3295 if (!err && msec > 1000)
3296 msec = 1;
3297
3298 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3299 if (phy_reset == -EPROBE_DEFER)
3300 return phy_reset;
3301 else if (!gpio_is_valid(phy_reset))
3302 return 0;
3303
3304 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3305 /* valid reset duration should be less than 1s */
3306 if (!err && phy_post_delay > 1000)
3307 return -EINVAL;
3308
3309 active_high = of_property_read_bool(np, "phy-reset-active-high");
3310
3311 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3312 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3313 "phy-reset");
3314 if (err) {
3315 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3316 return err;
3317 }
3318
3319 if (msec > 20)
3320 msleep(msec);
3321 else
3322 usleep_range(msec * 1000, msec * 1000 + 1000);
3323
3324 gpio_set_value_cansleep(phy_reset, !active_high);
3325
3326 if (!phy_post_delay)
3327 return 0;
3328
3329 if (phy_post_delay > 20)
3330 msleep(phy_post_delay);
3331 else
3332 usleep_range(phy_post_delay * 1000,
3333 phy_post_delay * 1000 + 1000);
3334
3335 return 0;
3336}
3337#else /* CONFIG_OF */
3338static int fec_reset_phy(struct platform_device *pdev)
3339{
3340 /*
3341 * In case of platform probe, the reset has been done
3342 * by machine code.
3343 */
3344 return 0;
3345}
3346#endif /* CONFIG_OF */
3347
3348static void
3349fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3350{
3351 struct device_node *np = pdev->dev.of_node;
3352
3353 *num_tx = *num_rx = 1;
3354
3355 if (!np || !of_device_is_available(np))
3356 return;
3357
3358 /* parse the num of tx and rx queues */
3359 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3360
3361 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3362
3363 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3364 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3365 *num_tx);
3366 *num_tx = 1;
3367 return;
3368 }
3369
3370 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3371 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3372 *num_rx);
3373 *num_rx = 1;
3374 return;
3375 }
3376
3377}
3378
3379static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3380{
3381 int irq_cnt = platform_irq_count(pdev);
3382
3383 if (irq_cnt > FEC_IRQ_NUM)
3384 irq_cnt = FEC_IRQ_NUM; /* last for pps */
3385 else if (irq_cnt == 2)
3386 irq_cnt = 1; /* last for pps */
3387 else if (irq_cnt <= 0)
3388 irq_cnt = 1; /* At least 1 irq is needed */
3389 return irq_cnt;
3390}
3391
3392static int
3393fec_probe(struct platform_device *pdev)
3394{
3395 struct fec_enet_private *fep;
3396 struct fec_platform_data *pdata;
3397 struct net_device *ndev;
3398 int i, irq, ret = 0;
3399 const struct of_device_id *of_id;
3400 static int dev_id;
3401 struct device_node *np = pdev->dev.of_node, *phy_node;
3402 int num_tx_qs;
3403 int num_rx_qs;
3404 char irq_name[8];
3405 int irq_cnt;
3406
3407 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3408
3409 /* Init network device */
3410 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3411 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3412 if (!ndev)
3413 return -ENOMEM;
3414
3415 SET_NETDEV_DEV(ndev, &pdev->dev);
3416
3417 /* setup board info structure */
3418 fep = netdev_priv(ndev);
3419
3420 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3421 if (of_id)
3422 pdev->id_entry = of_id->data;
3423 fep->quirks = pdev->id_entry->driver_data;
3424
3425 fep->netdev = ndev;
3426 fep->num_rx_queues = num_rx_qs;
3427 fep->num_tx_queues = num_tx_qs;
3428
3429#if !defined(CONFIG_M5272)
3430 /* default enable pause frame auto negotiation */
3431 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3432 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3433#endif
3434
3435 /* Select default pin state */
3436 pinctrl_pm_select_default_state(&pdev->dev);
3437
3438 fep->hwp = devm_platform_ioremap_resource(pdev, 0);
3439 if (IS_ERR(fep->hwp)) {
3440 ret = PTR_ERR(fep->hwp);
3441 goto failed_ioremap;
3442 }
3443
3444 fep->pdev = pdev;
3445 fep->dev_id = dev_id++;
3446
3447 platform_set_drvdata(pdev, ndev);
3448
3449 if ((of_machine_is_compatible("fsl,imx6q") ||
3450 of_machine_is_compatible("fsl,imx6dl")) &&
3451 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3452 fep->quirks |= FEC_QUIRK_ERR006687;
3453
3454 if (of_get_property(np, "fsl,magic-packet", NULL))
3455 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3456
3457 phy_node = of_parse_phandle(np, "phy-handle", 0);
3458 if (!phy_node && of_phy_is_fixed_link(np)) {
3459 ret = of_phy_register_fixed_link(np);
3460 if (ret < 0) {
3461 dev_err(&pdev->dev,
3462 "broken fixed-link specification\n");
3463 goto failed_phy;
3464 }
3465 phy_node = of_node_get(np);
3466 }
3467 fep->phy_node = phy_node;
3468
3469 ret = of_get_phy_mode(pdev->dev.of_node);
3470 if (ret < 0) {
3471 pdata = dev_get_platdata(&pdev->dev);
3472 if (pdata)
3473 fep->phy_interface = pdata->phy;
3474 else
3475 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3476 } else {
3477 fep->phy_interface = ret;
3478 }
3479
3480 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3481 if (IS_ERR(fep->clk_ipg)) {
3482 ret = PTR_ERR(fep->clk_ipg);
3483 goto failed_clk;
3484 }
3485
3486 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3487 if (IS_ERR(fep->clk_ahb)) {
3488 ret = PTR_ERR(fep->clk_ahb);
3489 goto failed_clk;
3490 }
3491
3492 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3493
3494 /* enet_out is optional, depends on board */
3495 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3496 if (IS_ERR(fep->clk_enet_out))
3497 fep->clk_enet_out = NULL;
3498
3499 fep->ptp_clk_on = false;
3500 mutex_init(&fep->ptp_clk_mutex);
3501
3502 /* clk_ref is optional, depends on board */
3503 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3504 if (IS_ERR(fep->clk_ref))
3505 fep->clk_ref = NULL;
3506
3507 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3508 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3509 if (IS_ERR(fep->clk_ptp)) {
3510 fep->clk_ptp = NULL;
3511 fep->bufdesc_ex = false;
3512 }
3513
3514 ret = fec_enet_clk_enable(ndev, true);
3515 if (ret)
3516 goto failed_clk;
3517
3518 ret = clk_prepare_enable(fep->clk_ipg);
3519 if (ret)
3520 goto failed_clk_ipg;
3521 ret = clk_prepare_enable(fep->clk_ahb);
3522 if (ret)
3523 goto failed_clk_ahb;
3524
3525 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
3526 if (!IS_ERR(fep->reg_phy)) {
3527 ret = regulator_enable(fep->reg_phy);
3528 if (ret) {
3529 dev_err(&pdev->dev,
3530 "Failed to enable phy regulator: %d\n", ret);
3531 goto failed_regulator;
3532 }
3533 } else {
3534 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3535 ret = -EPROBE_DEFER;
3536 goto failed_regulator;
3537 }
3538 fep->reg_phy = NULL;
3539 }
3540
3541 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3542 pm_runtime_use_autosuspend(&pdev->dev);
3543 pm_runtime_get_noresume(&pdev->dev);
3544 pm_runtime_set_active(&pdev->dev);
3545 pm_runtime_enable(&pdev->dev);
3546
3547 ret = fec_reset_phy(pdev);
3548 if (ret)
3549 goto failed_reset;
3550
3551 irq_cnt = fec_enet_get_irq_cnt(pdev);
3552 if (fep->bufdesc_ex)
3553 fec_ptp_init(pdev, irq_cnt);
3554
3555 ret = fec_enet_init(ndev);
3556 if (ret)
3557 goto failed_init;
3558
3559 for (i = 0; i < irq_cnt; i++) {
3560 snprintf(irq_name, sizeof(irq_name), "int%d", i);
3561 irq = platform_get_irq_byname_optional(pdev, irq_name);
3562 if (irq < 0)
3563 irq = platform_get_irq(pdev, i);
3564 if (irq < 0) {
3565 ret = irq;
3566 goto failed_irq;
3567 }
3568 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3569 0, pdev->name, ndev);
3570 if (ret)
3571 goto failed_irq;
3572
3573 fep->irq[i] = irq;
3574 }
3575
3576 init_completion(&fep->mdio_done);
3577 ret = fec_enet_mii_init(pdev);
3578 if (ret)
3579 goto failed_mii_init;
3580
3581 /* Carrier starts down, phylib will bring it up */
3582 netif_carrier_off(ndev);
3583 fec_enet_clk_enable(ndev, false);
3584 pinctrl_pm_select_sleep_state(&pdev->dev);
3585
3586 ret = register_netdev(ndev);
3587 if (ret)
3588 goto failed_register;
3589
3590 device_init_wakeup(&ndev->dev, fep->wol_flag &
3591 FEC_WOL_HAS_MAGIC_PACKET);
3592
3593 if (fep->bufdesc_ex && fep->ptp_clock)
3594 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3595
3596 fep->rx_copybreak = COPYBREAK_DEFAULT;
3597 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3598
3599 pm_runtime_mark_last_busy(&pdev->dev);
3600 pm_runtime_put_autosuspend(&pdev->dev);
3601
3602 return 0;
3603
3604failed_register:
3605 fec_enet_mii_remove(fep);
3606failed_mii_init:
3607failed_irq:
3608failed_init:
3609 fec_ptp_stop(pdev);
3610 if (fep->reg_phy)
3611 regulator_disable(fep->reg_phy);
3612failed_reset:
3613 pm_runtime_put_noidle(&pdev->dev);
3614 pm_runtime_disable(&pdev->dev);
3615failed_regulator:
3616 clk_disable_unprepare(fep->clk_ahb);
3617failed_clk_ahb:
3618 clk_disable_unprepare(fep->clk_ipg);
3619failed_clk_ipg:
3620 fec_enet_clk_enable(ndev, false);
3621failed_clk:
3622 if (of_phy_is_fixed_link(np))
3623 of_phy_deregister_fixed_link(np);
3624 of_node_put(phy_node);
3625failed_phy:
3626 dev_id--;
3627failed_ioremap:
3628 free_netdev(ndev);
3629
3630 return ret;
3631}
3632
3633static int
3634fec_drv_remove(struct platform_device *pdev)
3635{
3636 struct net_device *ndev = platform_get_drvdata(pdev);
3637 struct fec_enet_private *fep = netdev_priv(ndev);
3638 struct device_node *np = pdev->dev.of_node;
3639 int ret;
3640
3641 ret = pm_runtime_get_sync(&pdev->dev);
3642 if (ret < 0)
3643 return ret;
3644
3645 cancel_work_sync(&fep->tx_timeout_work);
3646 fec_ptp_stop(pdev);
3647 unregister_netdev(ndev);
3648 fec_enet_mii_remove(fep);
3649 if (fep->reg_phy)
3650 regulator_disable(fep->reg_phy);
3651
3652 if (of_phy_is_fixed_link(np))
3653 of_phy_deregister_fixed_link(np);
3654 of_node_put(fep->phy_node);
3655 free_netdev(ndev);
3656
3657 clk_disable_unprepare(fep->clk_ahb);
3658 clk_disable_unprepare(fep->clk_ipg);
3659 pm_runtime_put_noidle(&pdev->dev);
3660 pm_runtime_disable(&pdev->dev);
3661
3662 return 0;
3663}
3664
3665static int __maybe_unused fec_suspend(struct device *dev)
3666{
3667 struct net_device *ndev = dev_get_drvdata(dev);
3668 struct fec_enet_private *fep = netdev_priv(ndev);
3669
3670 rtnl_lock();
3671 if (netif_running(ndev)) {
3672 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3673 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3674 phy_stop(ndev->phydev);
3675 napi_disable(&fep->napi);
3676 netif_tx_lock_bh(ndev);
3677 netif_device_detach(ndev);
3678 netif_tx_unlock_bh(ndev);
3679 fec_stop(ndev);
3680 fec_enet_clk_enable(ndev, false);
3681 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3682 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3683 }
3684 rtnl_unlock();
3685
3686 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3687 regulator_disable(fep->reg_phy);
3688
3689 /* SOC supply clock to phy, when clock is disabled, phy link down
3690 * SOC control phy regulator, when regulator is disabled, phy link down
3691 */
3692 if (fep->clk_enet_out || fep->reg_phy)
3693 fep->link = 0;
3694
3695 return 0;
3696}
3697
3698static int __maybe_unused fec_resume(struct device *dev)
3699{
3700 struct net_device *ndev = dev_get_drvdata(dev);
3701 struct fec_enet_private *fep = netdev_priv(ndev);
3702 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3703 int ret;
3704 int val;
3705
3706 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3707 ret = regulator_enable(fep->reg_phy);
3708 if (ret)
3709 return ret;
3710 }
3711
3712 rtnl_lock();
3713 if (netif_running(ndev)) {
3714 ret = fec_enet_clk_enable(ndev, true);
3715 if (ret) {
3716 rtnl_unlock();
3717 goto failed_clk;
3718 }
3719 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3720 if (pdata && pdata->sleep_mode_enable)
3721 pdata->sleep_mode_enable(false);
3722 val = readl(fep->hwp + FEC_ECNTRL);
3723 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3724 writel(val, fep->hwp + FEC_ECNTRL);
3725 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3726 } else {
3727 pinctrl_pm_select_default_state(&fep->pdev->dev);
3728 }
3729 fec_restart(ndev);
3730 netif_tx_lock_bh(ndev);
3731 netif_device_attach(ndev);
3732 netif_tx_unlock_bh(ndev);
3733 napi_enable(&fep->napi);
3734 phy_start(ndev->phydev);
3735 }
3736 rtnl_unlock();
3737
3738 return 0;
3739
3740failed_clk:
3741 if (fep->reg_phy)
3742 regulator_disable(fep->reg_phy);
3743 return ret;
3744}
3745
3746static int __maybe_unused fec_runtime_suspend(struct device *dev)
3747{
3748 struct net_device *ndev = dev_get_drvdata(dev);
3749 struct fec_enet_private *fep = netdev_priv(ndev);
3750
3751 clk_disable_unprepare(fep->clk_ahb);
3752 clk_disable_unprepare(fep->clk_ipg);
3753
3754 return 0;
3755}
3756
3757static int __maybe_unused fec_runtime_resume(struct device *dev)
3758{
3759 struct net_device *ndev = dev_get_drvdata(dev);
3760 struct fec_enet_private *fep = netdev_priv(ndev);
3761 int ret;
3762
3763 ret = clk_prepare_enable(fep->clk_ahb);
3764 if (ret)
3765 return ret;
3766 ret = clk_prepare_enable(fep->clk_ipg);
3767 if (ret)
3768 goto failed_clk_ipg;
3769
3770 return 0;
3771
3772failed_clk_ipg:
3773 clk_disable_unprepare(fep->clk_ahb);
3774 return ret;
3775}
3776
3777static const struct dev_pm_ops fec_pm_ops = {
3778 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3779 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3780};
3781
3782static struct platform_driver fec_driver = {
3783 .driver = {
3784 .name = DRIVER_NAME,
3785 .pm = &fec_pm_ops,
3786 .of_match_table = fec_dt_ids,
3787 },
3788 .id_table = fec_devtype,
3789 .probe = fec_probe,
3790 .remove = fec_drv_remove,
3791};
3792
3793module_platform_driver(fec_driver);
3794
3795MODULE_ALIAS("platform:"DRIVER_NAME);
3796MODULE_LICENSE("GPL");