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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MUSB OTG driver - support for Mentor's DMA controller
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2007 by Texas Instruments
7 */
8#include <linux/device.h>
9#include <linux/interrupt.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include "musb_core.h"
13#include "musb_dma.h"
14
15#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
16 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
17
18#define musb_read_hsdma_addr(mbase, bchannel) \
19 musb_readl(mbase, \
20 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
21
22#define musb_write_hsdma_addr(mbase, bchannel, addr) \
23 musb_writel(mbase, \
24 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
25 addr)
26
27#define musb_read_hsdma_count(mbase, bchannel) \
28 musb_readl(mbase, \
29 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
30
31#define musb_write_hsdma_count(mbase, bchannel, len) \
32 musb_writel(mbase, \
33 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
34 len)
35/* control register (16-bit): */
36#define MUSB_HSDMA_ENABLE_SHIFT 0
37#define MUSB_HSDMA_TRANSMIT_SHIFT 1
38#define MUSB_HSDMA_MODE1_SHIFT 2
39#define MUSB_HSDMA_IRQENABLE_SHIFT 3
40#define MUSB_HSDMA_ENDPOINT_SHIFT 4
41#define MUSB_HSDMA_BUSERROR_SHIFT 8
42#define MUSB_HSDMA_BURSTMODE_SHIFT 9
43#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
44#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
45#define MUSB_HSDMA_BURSTMODE_INCR4 1
46#define MUSB_HSDMA_BURSTMODE_INCR8 2
47#define MUSB_HSDMA_BURSTMODE_INCR16 3
48
49#define MUSB_HSDMA_CHANNELS 8
50
51struct musb_dma_controller;
52
53struct musb_dma_channel {
54 struct dma_channel channel;
55 struct musb_dma_controller *controller;
56 u32 start_addr;
57 u32 len;
58 u16 max_packet_sz;
59 u8 idx;
60 u8 epnum;
61 u8 transmit;
62};
63
64struct musb_dma_controller {
65 struct dma_controller controller;
66 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
67 void *private_data;
68 void __iomem *base;
69 u8 channel_count;
70 u8 used_channels;
71 int irq;
72};
73
74static void dma_channel_release(struct dma_channel *channel);
75
76static void dma_controller_stop(struct musb_dma_controller *controller)
77{
78 struct musb *musb = controller->private_data;
79 struct dma_channel *channel;
80 u8 bit;
81
82 if (controller->used_channels != 0) {
83 dev_err(musb->controller,
84 "Stopping DMA controller while channel active\n");
85
86 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
87 if (controller->used_channels & (1 << bit)) {
88 channel = &controller->channel[bit].channel;
89 dma_channel_release(channel);
90
91 if (!controller->used_channels)
92 break;
93 }
94 }
95 }
96}
97
98static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
99 struct musb_hw_ep *hw_ep, u8 transmit)
100{
101 struct musb_dma_controller *controller = container_of(c,
102 struct musb_dma_controller, controller);
103 struct musb_dma_channel *musb_channel = NULL;
104 struct dma_channel *channel = NULL;
105 u8 bit;
106
107 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
108 if (!(controller->used_channels & (1 << bit))) {
109 controller->used_channels |= (1 << bit);
110 musb_channel = &(controller->channel[bit]);
111 musb_channel->controller = controller;
112 musb_channel->idx = bit;
113 musb_channel->epnum = hw_ep->epnum;
114 musb_channel->transmit = transmit;
115 channel = &(musb_channel->channel);
116 channel->private_data = musb_channel;
117 channel->status = MUSB_DMA_STATUS_FREE;
118 channel->max_len = 0x100000;
119 /* Tx => mode 1; Rx => mode 0 */
120 channel->desired_mode = transmit;
121 channel->actual_len = 0;
122 break;
123 }
124 }
125
126 return channel;
127}
128
129static void dma_channel_release(struct dma_channel *channel)
130{
131 struct musb_dma_channel *musb_channel = channel->private_data;
132
133 channel->actual_len = 0;
134 musb_channel->start_addr = 0;
135 musb_channel->len = 0;
136
137 musb_channel->controller->used_channels &=
138 ~(1 << musb_channel->idx);
139
140 channel->status = MUSB_DMA_STATUS_UNKNOWN;
141}
142
143static void configure_channel(struct dma_channel *channel,
144 u16 packet_sz, u8 mode,
145 dma_addr_t dma_addr, u32 len)
146{
147 struct musb_dma_channel *musb_channel = channel->private_data;
148 struct musb_dma_controller *controller = musb_channel->controller;
149 struct musb *musb = controller->private_data;
150 void __iomem *mbase = controller->base;
151 u8 bchannel = musb_channel->idx;
152 u16 csr = 0;
153
154 musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
155 channel, packet_sz, &dma_addr, len, mode);
156
157 if (mode) {
158 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
159 BUG_ON(len < packet_sz);
160 }
161 csr |= MUSB_HSDMA_BURSTMODE_INCR16
162 << MUSB_HSDMA_BURSTMODE_SHIFT;
163
164 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
165 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
166 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
167 | (musb_channel->transmit
168 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
169 : 0);
170
171 /* address/count */
172 musb_write_hsdma_addr(mbase, bchannel, dma_addr);
173 musb_write_hsdma_count(mbase, bchannel, len);
174
175 /* control (this should start things) */
176 musb_writew(mbase,
177 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
178 csr);
179}
180
181static int dma_channel_program(struct dma_channel *channel,
182 u16 packet_sz, u8 mode,
183 dma_addr_t dma_addr, u32 len)
184{
185 struct musb_dma_channel *musb_channel = channel->private_data;
186 struct musb_dma_controller *controller = musb_channel->controller;
187 struct musb *musb = controller->private_data;
188
189 musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
190 musb_channel->epnum,
191 musb_channel->transmit ? "Tx" : "Rx",
192 packet_sz, &dma_addr, len, mode);
193
194 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
195 channel->status == MUSB_DMA_STATUS_BUSY);
196
197 /*
198 * The DMA engine in RTL1.8 and above cannot handle
199 * DMA addresses that are not aligned to a 4 byte boundary.
200 * It ends up masking the last two bits of the address
201 * programmed in DMA_ADDR.
202 *
203 * Fail such DMA transfers, so that the backup PIO mode
204 * can carry out the transfer
205 */
206 if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
207 return false;
208
209 channel->actual_len = 0;
210 musb_channel->start_addr = dma_addr;
211 musb_channel->len = len;
212 musb_channel->max_packet_sz = packet_sz;
213 channel->status = MUSB_DMA_STATUS_BUSY;
214
215 configure_channel(channel, packet_sz, mode, dma_addr, len);
216
217 return true;
218}
219
220static int dma_channel_abort(struct dma_channel *channel)
221{
222 struct musb_dma_channel *musb_channel = channel->private_data;
223 void __iomem *mbase = musb_channel->controller->base;
224 struct musb *musb = musb_channel->controller->private_data;
225
226 u8 bchannel = musb_channel->idx;
227 int offset;
228 u16 csr;
229
230 if (channel->status == MUSB_DMA_STATUS_BUSY) {
231 if (musb_channel->transmit) {
232 offset = musb->io.ep_offset(musb_channel->epnum,
233 MUSB_TXCSR);
234
235 /*
236 * The programming guide says that we must clear
237 * the DMAENAB bit before the DMAMODE bit...
238 */
239 csr = musb_readw(mbase, offset);
240 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
241 musb_writew(mbase, offset, csr);
242 csr &= ~MUSB_TXCSR_DMAMODE;
243 musb_writew(mbase, offset, csr);
244 } else {
245 offset = musb->io.ep_offset(musb_channel->epnum,
246 MUSB_RXCSR);
247
248 csr = musb_readw(mbase, offset);
249 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
250 MUSB_RXCSR_DMAENAB |
251 MUSB_RXCSR_DMAMODE);
252 musb_writew(mbase, offset, csr);
253 }
254
255 musb_writew(mbase,
256 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
257 0);
258 musb_write_hsdma_addr(mbase, bchannel, 0);
259 musb_write_hsdma_count(mbase, bchannel, 0);
260 channel->status = MUSB_DMA_STATUS_FREE;
261 }
262
263 return 0;
264}
265
266irqreturn_t dma_controller_irq(int irq, void *private_data)
267{
268 struct musb_dma_controller *controller = private_data;
269 struct musb *musb = controller->private_data;
270 struct musb_dma_channel *musb_channel;
271 struct dma_channel *channel;
272
273 void __iomem *mbase = controller->base;
274
275 irqreturn_t retval = IRQ_NONE;
276
277 unsigned long flags;
278
279 u8 bchannel;
280 u8 int_hsdma;
281
282 u32 addr, count;
283 u16 csr;
284
285 spin_lock_irqsave(&musb->lock, flags);
286
287 int_hsdma = musb_clearb(mbase, MUSB_HSDMA_INTR);
288
289 if (!int_hsdma) {
290 musb_dbg(musb, "spurious DMA irq");
291
292 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
293 musb_channel = (struct musb_dma_channel *)
294 &(controller->channel[bchannel]);
295 channel = &musb_channel->channel;
296 if (channel->status == MUSB_DMA_STATUS_BUSY) {
297 count = musb_read_hsdma_count(mbase, bchannel);
298
299 if (count == 0)
300 int_hsdma |= (1 << bchannel);
301 }
302 }
303
304 musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
305
306 if (!int_hsdma)
307 goto done;
308 }
309
310 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
311 if (int_hsdma & (1 << bchannel)) {
312 musb_channel = (struct musb_dma_channel *)
313 &(controller->channel[bchannel]);
314 channel = &musb_channel->channel;
315
316 csr = musb_readw(mbase,
317 MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
318 MUSB_HSDMA_CONTROL));
319
320 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
321 musb_channel->channel.status =
322 MUSB_DMA_STATUS_BUS_ABORT;
323 } else {
324 addr = musb_read_hsdma_addr(mbase,
325 bchannel);
326 channel->actual_len = addr
327 - musb_channel->start_addr;
328
329 musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
330 channel, musb_channel->start_addr,
331 addr, channel->actual_len,
332 musb_channel->len,
333 (channel->actual_len
334 < musb_channel->len) ?
335 "=> reconfig 0" : "=> complete");
336
337 channel->status = MUSB_DMA_STATUS_FREE;
338
339 /* completed */
340 if (musb_channel->transmit &&
341 (!channel->desired_mode ||
342 (channel->actual_len %
343 musb_channel->max_packet_sz))) {
344 u8 epnum = musb_channel->epnum;
345 int offset = musb->io.ep_offset(epnum,
346 MUSB_TXCSR);
347 u16 txcsr;
348
349 /*
350 * The programming guide says that we
351 * must clear DMAENAB before DMAMODE.
352 */
353 musb_ep_select(mbase, epnum);
354 txcsr = musb_readw(mbase, offset);
355 if (channel->desired_mode == 1) {
356 txcsr &= ~(MUSB_TXCSR_DMAENAB
357 | MUSB_TXCSR_AUTOSET);
358 musb_writew(mbase, offset, txcsr);
359 /* Send out the packet */
360 txcsr &= ~MUSB_TXCSR_DMAMODE;
361 txcsr |= MUSB_TXCSR_DMAENAB;
362 }
363 txcsr |= MUSB_TXCSR_TXPKTRDY;
364 musb_writew(mbase, offset, txcsr);
365 }
366 musb_dma_completion(musb, musb_channel->epnum,
367 musb_channel->transmit);
368 }
369 }
370 }
371
372 retval = IRQ_HANDLED;
373done:
374 spin_unlock_irqrestore(&musb->lock, flags);
375 return retval;
376}
377EXPORT_SYMBOL_GPL(dma_controller_irq);
378
379void musbhs_dma_controller_destroy(struct dma_controller *c)
380{
381 struct musb_dma_controller *controller = container_of(c,
382 struct musb_dma_controller, controller);
383
384 dma_controller_stop(controller);
385
386 if (controller->irq)
387 free_irq(controller->irq, c);
388
389 kfree(controller);
390}
391EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
392
393static struct musb_dma_controller *
394dma_controller_alloc(struct musb *musb, void __iomem *base)
395{
396 struct musb_dma_controller *controller;
397
398 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
399 if (!controller)
400 return NULL;
401
402 controller->channel_count = MUSB_HSDMA_CHANNELS;
403 controller->private_data = musb;
404 controller->base = base;
405
406 controller->controller.channel_alloc = dma_channel_allocate;
407 controller->controller.channel_release = dma_channel_release;
408 controller->controller.channel_program = dma_channel_program;
409 controller->controller.channel_abort = dma_channel_abort;
410 return controller;
411}
412
413struct dma_controller *
414musbhs_dma_controller_create(struct musb *musb, void __iomem *base)
415{
416 struct musb_dma_controller *controller;
417 struct device *dev = musb->controller;
418 struct platform_device *pdev = to_platform_device(dev);
419 int irq = platform_get_irq_byname(pdev, "dma");
420
421 if (irq <= 0) {
422 dev_err(dev, "No DMA interrupt line!\n");
423 return NULL;
424 }
425
426 controller = dma_controller_alloc(musb, base);
427 if (!controller)
428 return NULL;
429
430 if (request_irq(irq, dma_controller_irq, 0,
431 dev_name(musb->controller), controller)) {
432 dev_err(dev, "request_irq %d failed!\n", irq);
433 musb_dma_controller_destroy(&controller->controller);
434
435 return NULL;
436 }
437
438 controller->irq = irq;
439
440 return &controller->controller;
441}
442EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);
443
444struct dma_controller *
445musbhs_dma_controller_create_noirq(struct musb *musb, void __iomem *base)
446{
447 struct musb_dma_controller *controller;
448
449 controller = dma_controller_alloc(musb, base);
450 if (!controller)
451 return NULL;
452
453 return &controller->controller;
454}
455EXPORT_SYMBOL_GPL(musbhs_dma_controller_create_noirq);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MUSB OTG driver - support for Mentor's DMA controller
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2007 by Texas Instruments
7 */
8#include <linux/device.h>
9#include <linux/interrupt.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include "musb_core.h"
13
14#define MUSB_HSDMA_BASE 0x200
15#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
16#define MUSB_HSDMA_CONTROL 0x4
17#define MUSB_HSDMA_ADDRESS 0x8
18#define MUSB_HSDMA_COUNT 0xc
19
20#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
21 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
22
23#define musb_read_hsdma_addr(mbase, bchannel) \
24 musb_readl(mbase, \
25 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
26
27#define musb_write_hsdma_addr(mbase, bchannel, addr) \
28 musb_writel(mbase, \
29 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
30 addr)
31
32#define musb_read_hsdma_count(mbase, bchannel) \
33 musb_readl(mbase, \
34 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
35
36#define musb_write_hsdma_count(mbase, bchannel, len) \
37 musb_writel(mbase, \
38 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
39 len)
40/* control register (16-bit): */
41#define MUSB_HSDMA_ENABLE_SHIFT 0
42#define MUSB_HSDMA_TRANSMIT_SHIFT 1
43#define MUSB_HSDMA_MODE1_SHIFT 2
44#define MUSB_HSDMA_IRQENABLE_SHIFT 3
45#define MUSB_HSDMA_ENDPOINT_SHIFT 4
46#define MUSB_HSDMA_BUSERROR_SHIFT 8
47#define MUSB_HSDMA_BURSTMODE_SHIFT 9
48#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
49#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
50#define MUSB_HSDMA_BURSTMODE_INCR4 1
51#define MUSB_HSDMA_BURSTMODE_INCR8 2
52#define MUSB_HSDMA_BURSTMODE_INCR16 3
53
54#define MUSB_HSDMA_CHANNELS 8
55
56struct musb_dma_controller;
57
58struct musb_dma_channel {
59 struct dma_channel channel;
60 struct musb_dma_controller *controller;
61 u32 start_addr;
62 u32 len;
63 u16 max_packet_sz;
64 u8 idx;
65 u8 epnum;
66 u8 transmit;
67};
68
69struct musb_dma_controller {
70 struct dma_controller controller;
71 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
72 void *private_data;
73 void __iomem *base;
74 u8 channel_count;
75 u8 used_channels;
76 int irq;
77};
78
79static void dma_channel_release(struct dma_channel *channel);
80
81static void dma_controller_stop(struct musb_dma_controller *controller)
82{
83 struct musb *musb = controller->private_data;
84 struct dma_channel *channel;
85 u8 bit;
86
87 if (controller->used_channels != 0) {
88 dev_err(musb->controller,
89 "Stopping DMA controller while channel active\n");
90
91 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
92 if (controller->used_channels & (1 << bit)) {
93 channel = &controller->channel[bit].channel;
94 dma_channel_release(channel);
95
96 if (!controller->used_channels)
97 break;
98 }
99 }
100 }
101}
102
103static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
104 struct musb_hw_ep *hw_ep, u8 transmit)
105{
106 struct musb_dma_controller *controller = container_of(c,
107 struct musb_dma_controller, controller);
108 struct musb_dma_channel *musb_channel = NULL;
109 struct dma_channel *channel = NULL;
110 u8 bit;
111
112 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
113 if (!(controller->used_channels & (1 << bit))) {
114 controller->used_channels |= (1 << bit);
115 musb_channel = &(controller->channel[bit]);
116 musb_channel->controller = controller;
117 musb_channel->idx = bit;
118 musb_channel->epnum = hw_ep->epnum;
119 musb_channel->transmit = transmit;
120 channel = &(musb_channel->channel);
121 channel->private_data = musb_channel;
122 channel->status = MUSB_DMA_STATUS_FREE;
123 channel->max_len = 0x100000;
124 /* Tx => mode 1; Rx => mode 0 */
125 channel->desired_mode = transmit;
126 channel->actual_len = 0;
127 break;
128 }
129 }
130
131 return channel;
132}
133
134static void dma_channel_release(struct dma_channel *channel)
135{
136 struct musb_dma_channel *musb_channel = channel->private_data;
137
138 channel->actual_len = 0;
139 musb_channel->start_addr = 0;
140 musb_channel->len = 0;
141
142 musb_channel->controller->used_channels &=
143 ~(1 << musb_channel->idx);
144
145 channel->status = MUSB_DMA_STATUS_UNKNOWN;
146}
147
148static void configure_channel(struct dma_channel *channel,
149 u16 packet_sz, u8 mode,
150 dma_addr_t dma_addr, u32 len)
151{
152 struct musb_dma_channel *musb_channel = channel->private_data;
153 struct musb_dma_controller *controller = musb_channel->controller;
154 struct musb *musb = controller->private_data;
155 void __iomem *mbase = controller->base;
156 u8 bchannel = musb_channel->idx;
157 u16 csr = 0;
158
159 musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
160 channel, packet_sz, &dma_addr, len, mode);
161
162 if (mode) {
163 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
164 BUG_ON(len < packet_sz);
165 }
166 csr |= MUSB_HSDMA_BURSTMODE_INCR16
167 << MUSB_HSDMA_BURSTMODE_SHIFT;
168
169 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
170 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
171 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
172 | (musb_channel->transmit
173 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
174 : 0);
175
176 /* address/count */
177 musb_write_hsdma_addr(mbase, bchannel, dma_addr);
178 musb_write_hsdma_count(mbase, bchannel, len);
179
180 /* control (this should start things) */
181 musb_writew(mbase,
182 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
183 csr);
184}
185
186static int dma_channel_program(struct dma_channel *channel,
187 u16 packet_sz, u8 mode,
188 dma_addr_t dma_addr, u32 len)
189{
190 struct musb_dma_channel *musb_channel = channel->private_data;
191 struct musb_dma_controller *controller = musb_channel->controller;
192 struct musb *musb = controller->private_data;
193
194 musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
195 musb_channel->epnum,
196 musb_channel->transmit ? "Tx" : "Rx",
197 packet_sz, &dma_addr, len, mode);
198
199 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
200 channel->status == MUSB_DMA_STATUS_BUSY);
201
202 /*
203 * The DMA engine in RTL1.8 and above cannot handle
204 * DMA addresses that are not aligned to a 4 byte boundary.
205 * It ends up masking the last two bits of the address
206 * programmed in DMA_ADDR.
207 *
208 * Fail such DMA transfers, so that the backup PIO mode
209 * can carry out the transfer
210 */
211 if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
212 return false;
213
214 channel->actual_len = 0;
215 musb_channel->start_addr = dma_addr;
216 musb_channel->len = len;
217 musb_channel->max_packet_sz = packet_sz;
218 channel->status = MUSB_DMA_STATUS_BUSY;
219
220 configure_channel(channel, packet_sz, mode, dma_addr, len);
221
222 return true;
223}
224
225static int dma_channel_abort(struct dma_channel *channel)
226{
227 struct musb_dma_channel *musb_channel = channel->private_data;
228 void __iomem *mbase = musb_channel->controller->base;
229 struct musb *musb = musb_channel->controller->private_data;
230
231 u8 bchannel = musb_channel->idx;
232 int offset;
233 u16 csr;
234
235 if (channel->status == MUSB_DMA_STATUS_BUSY) {
236 if (musb_channel->transmit) {
237 offset = musb->io.ep_offset(musb_channel->epnum,
238 MUSB_TXCSR);
239
240 /*
241 * The programming guide says that we must clear
242 * the DMAENAB bit before the DMAMODE bit...
243 */
244 csr = musb_readw(mbase, offset);
245 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
246 musb_writew(mbase, offset, csr);
247 csr &= ~MUSB_TXCSR_DMAMODE;
248 musb_writew(mbase, offset, csr);
249 } else {
250 offset = musb->io.ep_offset(musb_channel->epnum,
251 MUSB_RXCSR);
252
253 csr = musb_readw(mbase, offset);
254 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
255 MUSB_RXCSR_DMAENAB |
256 MUSB_RXCSR_DMAMODE);
257 musb_writew(mbase, offset, csr);
258 }
259
260 musb_writew(mbase,
261 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
262 0);
263 musb_write_hsdma_addr(mbase, bchannel, 0);
264 musb_write_hsdma_count(mbase, bchannel, 0);
265 channel->status = MUSB_DMA_STATUS_FREE;
266 }
267
268 return 0;
269}
270
271static irqreturn_t dma_controller_irq(int irq, void *private_data)
272{
273 struct musb_dma_controller *controller = private_data;
274 struct musb *musb = controller->private_data;
275 struct musb_dma_channel *musb_channel;
276 struct dma_channel *channel;
277
278 void __iomem *mbase = controller->base;
279
280 irqreturn_t retval = IRQ_NONE;
281
282 unsigned long flags;
283
284 u8 bchannel;
285 u8 int_hsdma;
286
287 u32 addr, count;
288 u16 csr;
289
290 spin_lock_irqsave(&musb->lock, flags);
291
292 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
293
294 if (!int_hsdma) {
295 musb_dbg(musb, "spurious DMA irq");
296
297 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
298 musb_channel = (struct musb_dma_channel *)
299 &(controller->channel[bchannel]);
300 channel = &musb_channel->channel;
301 if (channel->status == MUSB_DMA_STATUS_BUSY) {
302 count = musb_read_hsdma_count(mbase, bchannel);
303
304 if (count == 0)
305 int_hsdma |= (1 << bchannel);
306 }
307 }
308
309 musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
310
311 if (!int_hsdma)
312 goto done;
313 }
314
315 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
316 if (int_hsdma & (1 << bchannel)) {
317 musb_channel = (struct musb_dma_channel *)
318 &(controller->channel[bchannel]);
319 channel = &musb_channel->channel;
320
321 csr = musb_readw(mbase,
322 MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
323 MUSB_HSDMA_CONTROL));
324
325 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
326 musb_channel->channel.status =
327 MUSB_DMA_STATUS_BUS_ABORT;
328 } else {
329 u8 devctl;
330
331 addr = musb_read_hsdma_addr(mbase,
332 bchannel);
333 channel->actual_len = addr
334 - musb_channel->start_addr;
335
336 musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
337 channel, musb_channel->start_addr,
338 addr, channel->actual_len,
339 musb_channel->len,
340 (channel->actual_len
341 < musb_channel->len) ?
342 "=> reconfig 0" : "=> complete");
343
344 devctl = musb_readb(mbase, MUSB_DEVCTL);
345
346 channel->status = MUSB_DMA_STATUS_FREE;
347
348 /* completed */
349 if (musb_channel->transmit &&
350 (!channel->desired_mode ||
351 (channel->actual_len %
352 musb_channel->max_packet_sz))) {
353 u8 epnum = musb_channel->epnum;
354 int offset = musb->io.ep_offset(epnum,
355 MUSB_TXCSR);
356 u16 txcsr;
357
358 /*
359 * The programming guide says that we
360 * must clear DMAENAB before DMAMODE.
361 */
362 musb_ep_select(mbase, epnum);
363 txcsr = musb_readw(mbase, offset);
364 if (channel->desired_mode == 1) {
365 txcsr &= ~(MUSB_TXCSR_DMAENAB
366 | MUSB_TXCSR_AUTOSET);
367 musb_writew(mbase, offset, txcsr);
368 /* Send out the packet */
369 txcsr &= ~MUSB_TXCSR_DMAMODE;
370 txcsr |= MUSB_TXCSR_DMAENAB;
371 }
372 txcsr |= MUSB_TXCSR_TXPKTRDY;
373 musb_writew(mbase, offset, txcsr);
374 }
375 musb_dma_completion(musb, musb_channel->epnum,
376 musb_channel->transmit);
377 }
378 }
379 }
380
381 retval = IRQ_HANDLED;
382done:
383 spin_unlock_irqrestore(&musb->lock, flags);
384 return retval;
385}
386
387void musbhs_dma_controller_destroy(struct dma_controller *c)
388{
389 struct musb_dma_controller *controller = container_of(c,
390 struct musb_dma_controller, controller);
391
392 dma_controller_stop(controller);
393
394 if (controller->irq)
395 free_irq(controller->irq, c);
396
397 kfree(controller);
398}
399EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
400
401struct dma_controller *musbhs_dma_controller_create(struct musb *musb,
402 void __iomem *base)
403{
404 struct musb_dma_controller *controller;
405 struct device *dev = musb->controller;
406 struct platform_device *pdev = to_platform_device(dev);
407 int irq = platform_get_irq_byname(pdev, "dma");
408
409 if (irq <= 0) {
410 dev_err(dev, "No DMA interrupt line!\n");
411 return NULL;
412 }
413
414 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
415 if (!controller)
416 return NULL;
417
418 controller->channel_count = MUSB_HSDMA_CHANNELS;
419 controller->private_data = musb;
420 controller->base = base;
421
422 controller->controller.channel_alloc = dma_channel_allocate;
423 controller->controller.channel_release = dma_channel_release;
424 controller->controller.channel_program = dma_channel_program;
425 controller->controller.channel_abort = dma_channel_abort;
426
427 if (request_irq(irq, dma_controller_irq, 0,
428 dev_name(musb->controller), &controller->controller)) {
429 dev_err(dev, "request_irq %d failed!\n", irq);
430 musb_dma_controller_destroy(&controller->controller);
431
432 return NULL;
433 }
434
435 controller->irq = irq;
436
437 return &controller->controller;
438}
439EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);