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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MUSB OTG driver - support for Mentor's DMA controller
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2007 by Texas Instruments
7 */
8#include <linux/device.h>
9#include <linux/interrupt.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include "musb_core.h"
13#include "musb_dma.h"
14
15#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
16 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
17
18#define musb_read_hsdma_addr(mbase, bchannel) \
19 musb_readl(mbase, \
20 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
21
22#define musb_write_hsdma_addr(mbase, bchannel, addr) \
23 musb_writel(mbase, \
24 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
25 addr)
26
27#define musb_read_hsdma_count(mbase, bchannel) \
28 musb_readl(mbase, \
29 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
30
31#define musb_write_hsdma_count(mbase, bchannel, len) \
32 musb_writel(mbase, \
33 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
34 len)
35/* control register (16-bit): */
36#define MUSB_HSDMA_ENABLE_SHIFT 0
37#define MUSB_HSDMA_TRANSMIT_SHIFT 1
38#define MUSB_HSDMA_MODE1_SHIFT 2
39#define MUSB_HSDMA_IRQENABLE_SHIFT 3
40#define MUSB_HSDMA_ENDPOINT_SHIFT 4
41#define MUSB_HSDMA_BUSERROR_SHIFT 8
42#define MUSB_HSDMA_BURSTMODE_SHIFT 9
43#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
44#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
45#define MUSB_HSDMA_BURSTMODE_INCR4 1
46#define MUSB_HSDMA_BURSTMODE_INCR8 2
47#define MUSB_HSDMA_BURSTMODE_INCR16 3
48
49#define MUSB_HSDMA_CHANNELS 8
50
51struct musb_dma_controller;
52
53struct musb_dma_channel {
54 struct dma_channel channel;
55 struct musb_dma_controller *controller;
56 u32 start_addr;
57 u32 len;
58 u16 max_packet_sz;
59 u8 idx;
60 u8 epnum;
61 u8 transmit;
62};
63
64struct musb_dma_controller {
65 struct dma_controller controller;
66 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
67 void *private_data;
68 void __iomem *base;
69 u8 channel_count;
70 u8 used_channels;
71 int irq;
72};
73
74static void dma_channel_release(struct dma_channel *channel);
75
76static void dma_controller_stop(struct musb_dma_controller *controller)
77{
78 struct musb *musb = controller->private_data;
79 struct dma_channel *channel;
80 u8 bit;
81
82 if (controller->used_channels != 0) {
83 dev_err(musb->controller,
84 "Stopping DMA controller while channel active\n");
85
86 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
87 if (controller->used_channels & (1 << bit)) {
88 channel = &controller->channel[bit].channel;
89 dma_channel_release(channel);
90
91 if (!controller->used_channels)
92 break;
93 }
94 }
95 }
96}
97
98static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
99 struct musb_hw_ep *hw_ep, u8 transmit)
100{
101 struct musb_dma_controller *controller = container_of(c,
102 struct musb_dma_controller, controller);
103 struct musb_dma_channel *musb_channel = NULL;
104 struct dma_channel *channel = NULL;
105 u8 bit;
106
107 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
108 if (!(controller->used_channels & (1 << bit))) {
109 controller->used_channels |= (1 << bit);
110 musb_channel = &(controller->channel[bit]);
111 musb_channel->controller = controller;
112 musb_channel->idx = bit;
113 musb_channel->epnum = hw_ep->epnum;
114 musb_channel->transmit = transmit;
115 channel = &(musb_channel->channel);
116 channel->private_data = musb_channel;
117 channel->status = MUSB_DMA_STATUS_FREE;
118 channel->max_len = 0x100000;
119 /* Tx => mode 1; Rx => mode 0 */
120 channel->desired_mode = transmit;
121 channel->actual_len = 0;
122 break;
123 }
124 }
125
126 return channel;
127}
128
129static void dma_channel_release(struct dma_channel *channel)
130{
131 struct musb_dma_channel *musb_channel = channel->private_data;
132
133 channel->actual_len = 0;
134 musb_channel->start_addr = 0;
135 musb_channel->len = 0;
136
137 musb_channel->controller->used_channels &=
138 ~(1 << musb_channel->idx);
139
140 channel->status = MUSB_DMA_STATUS_UNKNOWN;
141}
142
143static void configure_channel(struct dma_channel *channel,
144 u16 packet_sz, u8 mode,
145 dma_addr_t dma_addr, u32 len)
146{
147 struct musb_dma_channel *musb_channel = channel->private_data;
148 struct musb_dma_controller *controller = musb_channel->controller;
149 struct musb *musb = controller->private_data;
150 void __iomem *mbase = controller->base;
151 u8 bchannel = musb_channel->idx;
152 u16 csr = 0;
153
154 musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
155 channel, packet_sz, &dma_addr, len, mode);
156
157 if (mode) {
158 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
159 BUG_ON(len < packet_sz);
160 }
161 csr |= MUSB_HSDMA_BURSTMODE_INCR16
162 << MUSB_HSDMA_BURSTMODE_SHIFT;
163
164 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
165 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
166 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
167 | (musb_channel->transmit
168 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
169 : 0);
170
171 /* address/count */
172 musb_write_hsdma_addr(mbase, bchannel, dma_addr);
173 musb_write_hsdma_count(mbase, bchannel, len);
174
175 /* control (this should start things) */
176 musb_writew(mbase,
177 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
178 csr);
179}
180
181static int dma_channel_program(struct dma_channel *channel,
182 u16 packet_sz, u8 mode,
183 dma_addr_t dma_addr, u32 len)
184{
185 struct musb_dma_channel *musb_channel = channel->private_data;
186 struct musb_dma_controller *controller = musb_channel->controller;
187 struct musb *musb = controller->private_data;
188
189 musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
190 musb_channel->epnum,
191 musb_channel->transmit ? "Tx" : "Rx",
192 packet_sz, &dma_addr, len, mode);
193
194 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
195 channel->status == MUSB_DMA_STATUS_BUSY);
196
197 /*
198 * The DMA engine in RTL1.8 and above cannot handle
199 * DMA addresses that are not aligned to a 4 byte boundary.
200 * It ends up masking the last two bits of the address
201 * programmed in DMA_ADDR.
202 *
203 * Fail such DMA transfers, so that the backup PIO mode
204 * can carry out the transfer
205 */
206 if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
207 return false;
208
209 channel->actual_len = 0;
210 musb_channel->start_addr = dma_addr;
211 musb_channel->len = len;
212 musb_channel->max_packet_sz = packet_sz;
213 channel->status = MUSB_DMA_STATUS_BUSY;
214
215 configure_channel(channel, packet_sz, mode, dma_addr, len);
216
217 return true;
218}
219
220static int dma_channel_abort(struct dma_channel *channel)
221{
222 struct musb_dma_channel *musb_channel = channel->private_data;
223 void __iomem *mbase = musb_channel->controller->base;
224 struct musb *musb = musb_channel->controller->private_data;
225
226 u8 bchannel = musb_channel->idx;
227 int offset;
228 u16 csr;
229
230 if (channel->status == MUSB_DMA_STATUS_BUSY) {
231 if (musb_channel->transmit) {
232 offset = musb->io.ep_offset(musb_channel->epnum,
233 MUSB_TXCSR);
234
235 /*
236 * The programming guide says that we must clear
237 * the DMAENAB bit before the DMAMODE bit...
238 */
239 csr = musb_readw(mbase, offset);
240 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
241 musb_writew(mbase, offset, csr);
242 csr &= ~MUSB_TXCSR_DMAMODE;
243 musb_writew(mbase, offset, csr);
244 } else {
245 offset = musb->io.ep_offset(musb_channel->epnum,
246 MUSB_RXCSR);
247
248 csr = musb_readw(mbase, offset);
249 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
250 MUSB_RXCSR_DMAENAB |
251 MUSB_RXCSR_DMAMODE);
252 musb_writew(mbase, offset, csr);
253 }
254
255 musb_writew(mbase,
256 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
257 0);
258 musb_write_hsdma_addr(mbase, bchannel, 0);
259 musb_write_hsdma_count(mbase, bchannel, 0);
260 channel->status = MUSB_DMA_STATUS_FREE;
261 }
262
263 return 0;
264}
265
266irqreturn_t dma_controller_irq(int irq, void *private_data)
267{
268 struct musb_dma_controller *controller = private_data;
269 struct musb *musb = controller->private_data;
270 struct musb_dma_channel *musb_channel;
271 struct dma_channel *channel;
272
273 void __iomem *mbase = controller->base;
274
275 irqreturn_t retval = IRQ_NONE;
276
277 unsigned long flags;
278
279 u8 bchannel;
280 u8 int_hsdma;
281
282 u32 addr, count;
283 u16 csr;
284
285 spin_lock_irqsave(&musb->lock, flags);
286
287 int_hsdma = musb_clearb(mbase, MUSB_HSDMA_INTR);
288
289 if (!int_hsdma) {
290 musb_dbg(musb, "spurious DMA irq");
291
292 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
293 musb_channel = (struct musb_dma_channel *)
294 &(controller->channel[bchannel]);
295 channel = &musb_channel->channel;
296 if (channel->status == MUSB_DMA_STATUS_BUSY) {
297 count = musb_read_hsdma_count(mbase, bchannel);
298
299 if (count == 0)
300 int_hsdma |= (1 << bchannel);
301 }
302 }
303
304 musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
305
306 if (!int_hsdma)
307 goto done;
308 }
309
310 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
311 if (int_hsdma & (1 << bchannel)) {
312 musb_channel = (struct musb_dma_channel *)
313 &(controller->channel[bchannel]);
314 channel = &musb_channel->channel;
315
316 csr = musb_readw(mbase,
317 MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
318 MUSB_HSDMA_CONTROL));
319
320 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
321 musb_channel->channel.status =
322 MUSB_DMA_STATUS_BUS_ABORT;
323 } else {
324 addr = musb_read_hsdma_addr(mbase,
325 bchannel);
326 channel->actual_len = addr
327 - musb_channel->start_addr;
328
329 musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
330 channel, musb_channel->start_addr,
331 addr, channel->actual_len,
332 musb_channel->len,
333 (channel->actual_len
334 < musb_channel->len) ?
335 "=> reconfig 0" : "=> complete");
336
337 channel->status = MUSB_DMA_STATUS_FREE;
338
339 /* completed */
340 if (musb_channel->transmit &&
341 (!channel->desired_mode ||
342 (channel->actual_len %
343 musb_channel->max_packet_sz))) {
344 u8 epnum = musb_channel->epnum;
345 int offset = musb->io.ep_offset(epnum,
346 MUSB_TXCSR);
347 u16 txcsr;
348
349 /*
350 * The programming guide says that we
351 * must clear DMAENAB before DMAMODE.
352 */
353 musb_ep_select(mbase, epnum);
354 txcsr = musb_readw(mbase, offset);
355 if (channel->desired_mode == 1) {
356 txcsr &= ~(MUSB_TXCSR_DMAENAB
357 | MUSB_TXCSR_AUTOSET);
358 musb_writew(mbase, offset, txcsr);
359 /* Send out the packet */
360 txcsr &= ~MUSB_TXCSR_DMAMODE;
361 txcsr |= MUSB_TXCSR_DMAENAB;
362 }
363 txcsr |= MUSB_TXCSR_TXPKTRDY;
364 musb_writew(mbase, offset, txcsr);
365 }
366 musb_dma_completion(musb, musb_channel->epnum,
367 musb_channel->transmit);
368 }
369 }
370 }
371
372 retval = IRQ_HANDLED;
373done:
374 spin_unlock_irqrestore(&musb->lock, flags);
375 return retval;
376}
377EXPORT_SYMBOL_GPL(dma_controller_irq);
378
379void musbhs_dma_controller_destroy(struct dma_controller *c)
380{
381 struct musb_dma_controller *controller = container_of(c,
382 struct musb_dma_controller, controller);
383
384 dma_controller_stop(controller);
385
386 if (controller->irq)
387 free_irq(controller->irq, c);
388
389 kfree(controller);
390}
391EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
392
393static struct musb_dma_controller *
394dma_controller_alloc(struct musb *musb, void __iomem *base)
395{
396 struct musb_dma_controller *controller;
397
398 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
399 if (!controller)
400 return NULL;
401
402 controller->channel_count = MUSB_HSDMA_CHANNELS;
403 controller->private_data = musb;
404 controller->base = base;
405
406 controller->controller.channel_alloc = dma_channel_allocate;
407 controller->controller.channel_release = dma_channel_release;
408 controller->controller.channel_program = dma_channel_program;
409 controller->controller.channel_abort = dma_channel_abort;
410 return controller;
411}
412
413struct dma_controller *
414musbhs_dma_controller_create(struct musb *musb, void __iomem *base)
415{
416 struct musb_dma_controller *controller;
417 struct device *dev = musb->controller;
418 struct platform_device *pdev = to_platform_device(dev);
419 int irq = platform_get_irq_byname(pdev, "dma");
420
421 if (irq <= 0) {
422 dev_err(dev, "No DMA interrupt line!\n");
423 return NULL;
424 }
425
426 controller = dma_controller_alloc(musb, base);
427 if (!controller)
428 return NULL;
429
430 if (request_irq(irq, dma_controller_irq, 0,
431 dev_name(musb->controller), controller)) {
432 dev_err(dev, "request_irq %d failed!\n", irq);
433 musb_dma_controller_destroy(&controller->controller);
434
435 return NULL;
436 }
437
438 controller->irq = irq;
439
440 return &controller->controller;
441}
442EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);
443
444struct dma_controller *
445musbhs_dma_controller_create_noirq(struct musb *musb, void __iomem *base)
446{
447 struct musb_dma_controller *controller;
448
449 controller = dma_controller_alloc(musb, base);
450 if (!controller)
451 return NULL;
452
453 return &controller->controller;
454}
455EXPORT_SYMBOL_GPL(musbhs_dma_controller_create_noirq);
1/*
2 * MUSB OTG driver - support for Mentor's DMA controller
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2007 by Texas Instruments
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33#include <linux/device.h>
34#include <linux/interrupt.h>
35#include <linux/platform_device.h>
36#include <linux/slab.h>
37#include "musb_core.h"
38#include "musbhsdma.h"
39
40static int dma_controller_start(struct dma_controller *c)
41{
42 /* nothing to do */
43 return 0;
44}
45
46static void dma_channel_release(struct dma_channel *channel);
47
48static int dma_controller_stop(struct dma_controller *c)
49{
50 struct musb_dma_controller *controller = container_of(c,
51 struct musb_dma_controller, controller);
52 struct musb *musb = controller->private_data;
53 struct dma_channel *channel;
54 u8 bit;
55
56 if (controller->used_channels != 0) {
57 dev_err(musb->controller,
58 "Stopping DMA controller while channel active\n");
59
60 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
61 if (controller->used_channels & (1 << bit)) {
62 channel = &controller->channel[bit].channel;
63 dma_channel_release(channel);
64
65 if (!controller->used_channels)
66 break;
67 }
68 }
69 }
70
71 return 0;
72}
73
74static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
75 struct musb_hw_ep *hw_ep, u8 transmit)
76{
77 struct musb_dma_controller *controller = container_of(c,
78 struct musb_dma_controller, controller);
79 struct musb_dma_channel *musb_channel = NULL;
80 struct dma_channel *channel = NULL;
81 u8 bit;
82
83 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
84 if (!(controller->used_channels & (1 << bit))) {
85 controller->used_channels |= (1 << bit);
86 musb_channel = &(controller->channel[bit]);
87 musb_channel->controller = controller;
88 musb_channel->idx = bit;
89 musb_channel->epnum = hw_ep->epnum;
90 musb_channel->transmit = transmit;
91 channel = &(musb_channel->channel);
92 channel->private_data = musb_channel;
93 channel->status = MUSB_DMA_STATUS_FREE;
94 channel->max_len = 0x100000;
95 /* Tx => mode 1; Rx => mode 0 */
96 channel->desired_mode = transmit;
97 channel->actual_len = 0;
98 break;
99 }
100 }
101
102 return channel;
103}
104
105static void dma_channel_release(struct dma_channel *channel)
106{
107 struct musb_dma_channel *musb_channel = channel->private_data;
108
109 channel->actual_len = 0;
110 musb_channel->start_addr = 0;
111 musb_channel->len = 0;
112
113 musb_channel->controller->used_channels &=
114 ~(1 << musb_channel->idx);
115
116 channel->status = MUSB_DMA_STATUS_UNKNOWN;
117}
118
119static void configure_channel(struct dma_channel *channel,
120 u16 packet_sz, u8 mode,
121 dma_addr_t dma_addr, u32 len)
122{
123 struct musb_dma_channel *musb_channel = channel->private_data;
124 struct musb_dma_controller *controller = musb_channel->controller;
125 struct musb *musb = controller->private_data;
126 void __iomem *mbase = controller->base;
127 u8 bchannel = musb_channel->idx;
128 u16 csr = 0;
129
130 dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
131 channel, packet_sz, dma_addr, len, mode);
132
133 if (mode) {
134 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
135 BUG_ON(len < packet_sz);
136 }
137 csr |= MUSB_HSDMA_BURSTMODE_INCR16
138 << MUSB_HSDMA_BURSTMODE_SHIFT;
139
140 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
141 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
142 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
143 | (musb_channel->transmit
144 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
145 : 0);
146
147 /* address/count */
148 musb_write_hsdma_addr(mbase, bchannel, dma_addr);
149 musb_write_hsdma_count(mbase, bchannel, len);
150
151 /* control (this should start things) */
152 musb_writew(mbase,
153 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
154 csr);
155}
156
157static int dma_channel_program(struct dma_channel *channel,
158 u16 packet_sz, u8 mode,
159 dma_addr_t dma_addr, u32 len)
160{
161 struct musb_dma_channel *musb_channel = channel->private_data;
162 struct musb_dma_controller *controller = musb_channel->controller;
163 struct musb *musb = controller->private_data;
164
165 dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
166 musb_channel->epnum,
167 musb_channel->transmit ? "Tx" : "Rx",
168 packet_sz, dma_addr, len, mode);
169
170 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
171 channel->status == MUSB_DMA_STATUS_BUSY);
172
173 /* Let targets check/tweak the arguments */
174 if (musb->ops->adjust_channel_params) {
175 int ret = musb->ops->adjust_channel_params(channel,
176 packet_sz, &mode, &dma_addr, &len);
177 if (ret)
178 return ret;
179 }
180
181 /*
182 * The DMA engine in RTL1.8 and above cannot handle
183 * DMA addresses that are not aligned to a 4 byte boundary.
184 * It ends up masking the last two bits of the address
185 * programmed in DMA_ADDR.
186 *
187 * Fail such DMA transfers, so that the backup PIO mode
188 * can carry out the transfer
189 */
190 if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
191 return false;
192
193 channel->actual_len = 0;
194 musb_channel->start_addr = dma_addr;
195 musb_channel->len = len;
196 musb_channel->max_packet_sz = packet_sz;
197 channel->status = MUSB_DMA_STATUS_BUSY;
198
199 configure_channel(channel, packet_sz, mode, dma_addr, len);
200
201 return true;
202}
203
204static int dma_channel_abort(struct dma_channel *channel)
205{
206 struct musb_dma_channel *musb_channel = channel->private_data;
207 void __iomem *mbase = musb_channel->controller->base;
208
209 u8 bchannel = musb_channel->idx;
210 int offset;
211 u16 csr;
212
213 if (channel->status == MUSB_DMA_STATUS_BUSY) {
214 if (musb_channel->transmit) {
215 offset = MUSB_EP_OFFSET(musb_channel->epnum,
216 MUSB_TXCSR);
217
218 /*
219 * The programming guide says that we must clear
220 * the DMAENAB bit before the DMAMODE bit...
221 */
222 csr = musb_readw(mbase, offset);
223 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
224 musb_writew(mbase, offset, csr);
225 csr &= ~MUSB_TXCSR_DMAMODE;
226 musb_writew(mbase, offset, csr);
227 } else {
228 offset = MUSB_EP_OFFSET(musb_channel->epnum,
229 MUSB_RXCSR);
230
231 csr = musb_readw(mbase, offset);
232 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
233 MUSB_RXCSR_DMAENAB |
234 MUSB_RXCSR_DMAMODE);
235 musb_writew(mbase, offset, csr);
236 }
237
238 musb_writew(mbase,
239 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
240 0);
241 musb_write_hsdma_addr(mbase, bchannel, 0);
242 musb_write_hsdma_count(mbase, bchannel, 0);
243 channel->status = MUSB_DMA_STATUS_FREE;
244 }
245
246 return 0;
247}
248
249static irqreturn_t dma_controller_irq(int irq, void *private_data)
250{
251 struct musb_dma_controller *controller = private_data;
252 struct musb *musb = controller->private_data;
253 struct musb_dma_channel *musb_channel;
254 struct dma_channel *channel;
255
256 void __iomem *mbase = controller->base;
257
258 irqreturn_t retval = IRQ_NONE;
259
260 unsigned long flags;
261
262 u8 bchannel;
263 u8 int_hsdma;
264
265 u32 addr, count;
266 u16 csr;
267
268 spin_lock_irqsave(&musb->lock, flags);
269
270 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
271
272#ifdef CONFIG_BLACKFIN
273 /* Clear DMA interrupt flags */
274 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
275#endif
276
277 if (!int_hsdma) {
278 dev_dbg(musb->controller, "spurious DMA irq\n");
279
280 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
281 musb_channel = (struct musb_dma_channel *)
282 &(controller->channel[bchannel]);
283 channel = &musb_channel->channel;
284 if (channel->status == MUSB_DMA_STATUS_BUSY) {
285 count = musb_read_hsdma_count(mbase, bchannel);
286
287 if (count == 0)
288 int_hsdma |= (1 << bchannel);
289 }
290 }
291
292 dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);
293
294 if (!int_hsdma)
295 goto done;
296 }
297
298 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
299 if (int_hsdma & (1 << bchannel)) {
300 musb_channel = (struct musb_dma_channel *)
301 &(controller->channel[bchannel]);
302 channel = &musb_channel->channel;
303
304 csr = musb_readw(mbase,
305 MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
306 MUSB_HSDMA_CONTROL));
307
308 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
309 musb_channel->channel.status =
310 MUSB_DMA_STATUS_BUS_ABORT;
311 } else {
312 u8 devctl;
313
314 addr = musb_read_hsdma_addr(mbase,
315 bchannel);
316 channel->actual_len = addr
317 - musb_channel->start_addr;
318
319 dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
320 channel, musb_channel->start_addr,
321 addr, channel->actual_len,
322 musb_channel->len,
323 (channel->actual_len
324 < musb_channel->len) ?
325 "=> reconfig 0" : "=> complete");
326
327 devctl = musb_readb(mbase, MUSB_DEVCTL);
328
329 channel->status = MUSB_DMA_STATUS_FREE;
330
331 /* completed */
332 if ((devctl & MUSB_DEVCTL_HM)
333 && (musb_channel->transmit)
334 && ((channel->desired_mode == 0)
335 || (channel->actual_len &
336 (musb_channel->max_packet_sz - 1)))
337 ) {
338 u8 epnum = musb_channel->epnum;
339 int offset = MUSB_EP_OFFSET(epnum,
340 MUSB_TXCSR);
341 u16 txcsr;
342
343 /*
344 * The programming guide says that we
345 * must clear DMAENAB before DMAMODE.
346 */
347 musb_ep_select(mbase, epnum);
348 txcsr = musb_readw(mbase, offset);
349 txcsr &= ~(MUSB_TXCSR_DMAENAB
350 | MUSB_TXCSR_AUTOSET);
351 musb_writew(mbase, offset, txcsr);
352 /* Send out the packet */
353 txcsr &= ~MUSB_TXCSR_DMAMODE;
354 txcsr |= MUSB_TXCSR_TXPKTRDY;
355 musb_writew(mbase, offset, txcsr);
356 }
357 musb_dma_completion(musb, musb_channel->epnum,
358 musb_channel->transmit);
359 }
360 }
361 }
362
363 retval = IRQ_HANDLED;
364done:
365 spin_unlock_irqrestore(&musb->lock, flags);
366 return retval;
367}
368
369void dma_controller_destroy(struct dma_controller *c)
370{
371 struct musb_dma_controller *controller = container_of(c,
372 struct musb_dma_controller, controller);
373
374 if (!controller)
375 return;
376
377 if (controller->irq)
378 free_irq(controller->irq, c);
379
380 kfree(controller);
381}
382
383struct dma_controller *__init
384dma_controller_create(struct musb *musb, void __iomem *base)
385{
386 struct musb_dma_controller *controller;
387 struct device *dev = musb->controller;
388 struct platform_device *pdev = to_platform_device(dev);
389 int irq = platform_get_irq_byname(pdev, "dma");
390
391 if (irq == 0) {
392 dev_err(dev, "No DMA interrupt line!\n");
393 return NULL;
394 }
395
396 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
397 if (!controller)
398 return NULL;
399
400 controller->channel_count = MUSB_HSDMA_CHANNELS;
401 controller->private_data = musb;
402 controller->base = base;
403
404 controller->controller.start = dma_controller_start;
405 controller->controller.stop = dma_controller_stop;
406 controller->controller.channel_alloc = dma_channel_allocate;
407 controller->controller.channel_release = dma_channel_release;
408 controller->controller.channel_program = dma_channel_program;
409 controller->controller.channel_abort = dma_channel_abort;
410
411 if (request_irq(irq, dma_controller_irq, 0,
412 dev_name(musb->controller), &controller->controller)) {
413 dev_err(dev, "request_irq %d failed!\n", irq);
414 dma_controller_destroy(&controller->controller);
415
416 return NULL;
417 }
418
419 controller->irq = irq;
420
421 return &controller->controller;
422}