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1/* SPDX-License-Identifier: GPL-2.0-only */
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
6 */
7
8#ifndef EFX_NIC_H
9#define EFX_NIC_H
10
11#include "nic_common.h"
12#include "efx.h"
13
14enum {
15 PHY_TYPE_NONE = 0,
16 PHY_TYPE_TXC43128 = 1,
17 PHY_TYPE_88E1111 = 2,
18 PHY_TYPE_SFX7101 = 3,
19 PHY_TYPE_QT2022C2 = 4,
20 PHY_TYPE_PM8358 = 6,
21 PHY_TYPE_SFT9001A = 8,
22 PHY_TYPE_QT2025C = 9,
23 PHY_TYPE_SFT9001B = 10,
24};
25
26enum {
27 EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
28 EF10_STAT_port_tx_packets,
29 EF10_STAT_port_tx_pause,
30 EF10_STAT_port_tx_control,
31 EF10_STAT_port_tx_unicast,
32 EF10_STAT_port_tx_multicast,
33 EF10_STAT_port_tx_broadcast,
34 EF10_STAT_port_tx_lt64,
35 EF10_STAT_port_tx_64,
36 EF10_STAT_port_tx_65_to_127,
37 EF10_STAT_port_tx_128_to_255,
38 EF10_STAT_port_tx_256_to_511,
39 EF10_STAT_port_tx_512_to_1023,
40 EF10_STAT_port_tx_1024_to_15xx,
41 EF10_STAT_port_tx_15xx_to_jumbo,
42 EF10_STAT_port_rx_bytes,
43 EF10_STAT_port_rx_bytes_minus_good_bytes,
44 EF10_STAT_port_rx_good_bytes,
45 EF10_STAT_port_rx_bad_bytes,
46 EF10_STAT_port_rx_packets,
47 EF10_STAT_port_rx_good,
48 EF10_STAT_port_rx_bad,
49 EF10_STAT_port_rx_pause,
50 EF10_STAT_port_rx_control,
51 EF10_STAT_port_rx_unicast,
52 EF10_STAT_port_rx_multicast,
53 EF10_STAT_port_rx_broadcast,
54 EF10_STAT_port_rx_lt64,
55 EF10_STAT_port_rx_64,
56 EF10_STAT_port_rx_65_to_127,
57 EF10_STAT_port_rx_128_to_255,
58 EF10_STAT_port_rx_256_to_511,
59 EF10_STAT_port_rx_512_to_1023,
60 EF10_STAT_port_rx_1024_to_15xx,
61 EF10_STAT_port_rx_15xx_to_jumbo,
62 EF10_STAT_port_rx_gtjumbo,
63 EF10_STAT_port_rx_bad_gtjumbo,
64 EF10_STAT_port_rx_overflow,
65 EF10_STAT_port_rx_align_error,
66 EF10_STAT_port_rx_length_error,
67 EF10_STAT_port_rx_nodesc_drops,
68 EF10_STAT_port_rx_pm_trunc_bb_overflow,
69 EF10_STAT_port_rx_pm_discard_bb_overflow,
70 EF10_STAT_port_rx_pm_trunc_vfifo_full,
71 EF10_STAT_port_rx_pm_discard_vfifo_full,
72 EF10_STAT_port_rx_pm_trunc_qbb,
73 EF10_STAT_port_rx_pm_discard_qbb,
74 EF10_STAT_port_rx_pm_discard_mapping,
75 EF10_STAT_port_rx_dp_q_disabled_packets,
76 EF10_STAT_port_rx_dp_di_dropped_packets,
77 EF10_STAT_port_rx_dp_streaming_packets,
78 EF10_STAT_port_rx_dp_hlb_fetch,
79 EF10_STAT_port_rx_dp_hlb_wait,
80 EF10_STAT_rx_unicast,
81 EF10_STAT_rx_unicast_bytes,
82 EF10_STAT_rx_multicast,
83 EF10_STAT_rx_multicast_bytes,
84 EF10_STAT_rx_broadcast,
85 EF10_STAT_rx_broadcast_bytes,
86 EF10_STAT_rx_bad,
87 EF10_STAT_rx_bad_bytes,
88 EF10_STAT_rx_overflow,
89 EF10_STAT_tx_unicast,
90 EF10_STAT_tx_unicast_bytes,
91 EF10_STAT_tx_multicast,
92 EF10_STAT_tx_multicast_bytes,
93 EF10_STAT_tx_broadcast,
94 EF10_STAT_tx_broadcast_bytes,
95 EF10_STAT_tx_bad,
96 EF10_STAT_tx_bad_bytes,
97 EF10_STAT_tx_overflow,
98 EF10_STAT_V1_COUNT,
99 EF10_STAT_fec_uncorrected_errors = EF10_STAT_V1_COUNT,
100 EF10_STAT_fec_corrected_errors,
101 EF10_STAT_fec_corrected_symbols_lane0,
102 EF10_STAT_fec_corrected_symbols_lane1,
103 EF10_STAT_fec_corrected_symbols_lane2,
104 EF10_STAT_fec_corrected_symbols_lane3,
105 EF10_STAT_ctpio_vi_busy_fallback,
106 EF10_STAT_ctpio_long_write_success,
107 EF10_STAT_ctpio_missing_dbell_fail,
108 EF10_STAT_ctpio_overflow_fail,
109 EF10_STAT_ctpio_underflow_fail,
110 EF10_STAT_ctpio_timeout_fail,
111 EF10_STAT_ctpio_noncontig_wr_fail,
112 EF10_STAT_ctpio_frm_clobber_fail,
113 EF10_STAT_ctpio_invalid_wr_fail,
114 EF10_STAT_ctpio_vi_clobber_fallback,
115 EF10_STAT_ctpio_unqualified_fallback,
116 EF10_STAT_ctpio_runt_fallback,
117 EF10_STAT_ctpio_success,
118 EF10_STAT_ctpio_fallback,
119 EF10_STAT_ctpio_poison,
120 EF10_STAT_ctpio_erase,
121 EF10_STAT_COUNT
122};
123
124/* Maximum number of TX PIO buffers we may allocate to a function.
125 * This matches the total number of buffers on each SFC9100-family
126 * controller.
127 */
128#define EF10_TX_PIOBUF_COUNT 16
129
130/**
131 * struct efx_ef10_nic_data - EF10 architecture NIC state
132 * @mcdi_buf: DMA buffer for MCDI
133 * @warm_boot_count: Last seen MC warm boot count
134 * @vi_base: Absolute index of first VI in this function
135 * @n_allocated_vis: Number of VIs allocated to this function
136 * @n_piobufs: Number of PIO buffers allocated to this function
137 * @wc_membase: Base address of write-combining mapping of the memory BAR
138 * @pio_write_base: Base address for writing PIO buffers
139 * @pio_write_vi_base: Relative VI number for @pio_write_base
140 * @piobuf_handle: Handle of each PIO buffer allocated
141 * @piobuf_size: size of a single PIO buffer
142 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
143 * reboot
144 * @mc_stats: Scratch buffer for converting statistics to the kernel's format
145 * @stats: Hardware statistics
146 * @workaround_35388: Flag: firmware supports workaround for bug 35388
147 * @workaround_26807: Flag: firmware supports workaround for bug 26807
148 * @workaround_61265: Flag: firmware supports workaround for bug 61265
149 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
150 * after MC reboot
151 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
152 * %MC_CMD_GET_CAPABILITIES response)
153 * @datapath_caps2: Further Capabilities of datapath firmware (FLAGS2 field of
154 * %MC_CMD_GET_CAPABILITIES response)
155 * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
156 * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
157 * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
158 * @pf_index: The number for this PF, or the parent PF if this is a VF
159#ifdef CONFIG_SFC_SRIOV
160 * @vf: Pointer to VF data structure
161#endif
162 * @vport_mac: The MAC address on the vport, only for PFs; VFs will be zero
163 * @vlan_list: List of VLANs added over the interface. Serialised by vlan_lock.
164 * @vlan_lock: Lock to serialize access to vlan_list.
165 * @udp_tunnels: UDP tunnel port numbers and types.
166 * @udp_tunnels_dirty: flag indicating a reboot occurred while pushing
167 * @udp_tunnels to hardware and thus the push must be re-done.
168 * @udp_tunnels_lock: Serialises writes to @udp_tunnels and @udp_tunnels_dirty.
169 */
170struct efx_ef10_nic_data {
171 struct efx_buffer mcdi_buf;
172 u16 warm_boot_count;
173 unsigned int vi_base;
174 unsigned int n_allocated_vis;
175 unsigned int n_piobufs;
176 void __iomem *wc_membase, *pio_write_base;
177 unsigned int pio_write_vi_base;
178 unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
179 u16 piobuf_size;
180 bool must_restore_piobufs;
181 __le64 *mc_stats;
182 u64 stats[EF10_STAT_COUNT];
183 bool workaround_35388;
184 bool workaround_26807;
185 bool workaround_61265;
186 bool must_check_datapath_caps;
187 u32 datapath_caps;
188 u32 datapath_caps2;
189 unsigned int rx_dpcpu_fw_id;
190 unsigned int tx_dpcpu_fw_id;
191 bool must_probe_vswitching;
192 unsigned int pf_index;
193 u8 port_id[ETH_ALEN];
194#ifdef CONFIG_SFC_SRIOV
195 unsigned int vf_index;
196 struct ef10_vf *vf;
197#endif
198 u8 vport_mac[ETH_ALEN];
199 struct list_head vlan_list;
200 struct mutex vlan_lock;
201 struct efx_udp_tunnel udp_tunnels[16];
202 bool udp_tunnels_dirty;
203 struct mutex udp_tunnels_lock;
204 u64 licensed_features;
205};
206
207/* TSOv2 */
208int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
209 bool *data_mapped);
210
211extern const struct efx_nic_type efx_hunt_a0_nic_type;
212extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
213
214#endif /* EFX_NIC_H */
1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EFX_NIC_H
12#define EFX_NIC_H
13
14#include <linux/net_tstamp.h>
15#include <linux/i2c-algo-bit.h>
16#include "net_driver.h"
17#include "efx.h"
18#include "mcdi.h"
19
20enum {
21 EFX_REV_FALCON_A0 = 0,
22 EFX_REV_FALCON_A1 = 1,
23 EFX_REV_FALCON_B0 = 2,
24 EFX_REV_SIENA_A0 = 3,
25 EFX_REV_HUNT_A0 = 4,
26};
27
28static inline int efx_nic_rev(struct efx_nic *efx)
29{
30 return efx->type->revision;
31}
32
33u32 efx_farch_fpga_ver(struct efx_nic *efx);
34
35/* NIC has two interlinked PCI functions for the same port. */
36static inline bool efx_nic_is_dual_func(struct efx_nic *efx)
37{
38 return efx_nic_rev(efx) < EFX_REV_FALCON_B0;
39}
40
41/* Read the current event from the event queue */
42static inline efx_qword_t *efx_event(struct efx_channel *channel,
43 unsigned int index)
44{
45 return ((efx_qword_t *) (channel->eventq.buf.addr)) +
46 (index & channel->eventq_mask);
47}
48
49/* See if an event is present
50 *
51 * We check both the high and low dword of the event for all ones. We
52 * wrote all ones when we cleared the event, and no valid event can
53 * have all ones in either its high or low dwords. This approach is
54 * robust against reordering.
55 *
56 * Note that using a single 64-bit comparison is incorrect; even
57 * though the CPU read will be atomic, the DMA write may not be.
58 */
59static inline int efx_event_present(efx_qword_t *event)
60{
61 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
62 EFX_DWORD_IS_ALL_ONES(event->dword[1]));
63}
64
65/* Returns a pointer to the specified transmit descriptor in the TX
66 * descriptor queue belonging to the specified channel.
67 */
68static inline efx_qword_t *
69efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
70{
71 return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
72}
73
74/* Get partner of a TX queue, seen as part of the same net core queue */
75static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue)
76{
77 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
78 return tx_queue - EFX_TXQ_TYPE_OFFLOAD;
79 else
80 return tx_queue + EFX_TXQ_TYPE_OFFLOAD;
81}
82
83/* Report whether this TX queue would be empty for the given write_count.
84 * May return false negative.
85 */
86static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue,
87 unsigned int write_count)
88{
89 unsigned int empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
90
91 if (empty_read_count == 0)
92 return false;
93
94 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
95}
96
97/* Decide whether we can use TX PIO, ie. write packet data directly into
98 * a buffer on the device. This can reduce latency at the expense of
99 * throughput, so we only do this if both hardware and software TX rings
100 * are empty. This also ensures that only one packet at a time can be
101 * using the PIO buffer.
102 */
103static inline bool efx_nic_may_tx_pio(struct efx_tx_queue *tx_queue)
104{
105 struct efx_tx_queue *partner = efx_tx_queue_partner(tx_queue);
106 return tx_queue->piobuf &&
107 __efx_nic_tx_is_empty(tx_queue, tx_queue->insert_count) &&
108 __efx_nic_tx_is_empty(partner, partner->insert_count);
109}
110
111/* Decide whether to push a TX descriptor to the NIC vs merely writing
112 * the doorbell. This can reduce latency when we are adding a single
113 * descriptor to an empty queue, but is otherwise pointless. Further,
114 * Falcon and Siena have hardware bugs (SF bug 33851) that may be
115 * triggered if we don't check this.
116 * We use the write_count used for the last doorbell push, to get the
117 * NIC's view of the tx queue.
118 */
119static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
120 unsigned int write_count)
121{
122 bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count);
123
124 tx_queue->empty_read_count = 0;
125 return was_empty && tx_queue->write_count - write_count == 1;
126}
127
128/* Returns a pointer to the specified descriptor in the RX descriptor queue */
129static inline efx_qword_t *
130efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
131{
132 return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
133}
134
135enum {
136 PHY_TYPE_NONE = 0,
137 PHY_TYPE_TXC43128 = 1,
138 PHY_TYPE_88E1111 = 2,
139 PHY_TYPE_SFX7101 = 3,
140 PHY_TYPE_QT2022C2 = 4,
141 PHY_TYPE_PM8358 = 6,
142 PHY_TYPE_SFT9001A = 8,
143 PHY_TYPE_QT2025C = 9,
144 PHY_TYPE_SFT9001B = 10,
145};
146
147#define FALCON_XMAC_LOOPBACKS \
148 ((1 << LOOPBACK_XGMII) | \
149 (1 << LOOPBACK_XGXS) | \
150 (1 << LOOPBACK_XAUI))
151
152/* Alignment of PCIe DMA boundaries (4KB) */
153#define EFX_PAGE_SIZE 4096
154/* Size and alignment of buffer table entries (same) */
155#define EFX_BUF_SIZE EFX_PAGE_SIZE
156
157/* NIC-generic software stats */
158enum {
159 GENERIC_STAT_rx_noskb_drops,
160 GENERIC_STAT_rx_nodesc_trunc,
161 GENERIC_STAT_COUNT
162};
163
164/**
165 * struct falcon_board_type - board operations and type information
166 * @id: Board type id, as found in NVRAM
167 * @init: Allocate resources and initialise peripheral hardware
168 * @init_phy: Do board-specific PHY initialisation
169 * @fini: Shut down hardware and free resources
170 * @set_id_led: Set state of identifying LED or revert to automatic function
171 * @monitor: Board-specific health check function
172 */
173struct falcon_board_type {
174 u8 id;
175 int (*init) (struct efx_nic *nic);
176 void (*init_phy) (struct efx_nic *efx);
177 void (*fini) (struct efx_nic *nic);
178 void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode);
179 int (*monitor) (struct efx_nic *nic);
180};
181
182/**
183 * struct falcon_board - board information
184 * @type: Type of board
185 * @major: Major rev. ('A', 'B' ...)
186 * @minor: Minor rev. (0, 1, ...)
187 * @i2c_adap: I2C adapter for on-board peripherals
188 * @i2c_data: Data for bit-banging algorithm
189 * @hwmon_client: I2C client for hardware monitor
190 * @ioexp_client: I2C client for power/port control
191 */
192struct falcon_board {
193 const struct falcon_board_type *type;
194 int major;
195 int minor;
196 struct i2c_adapter i2c_adap;
197 struct i2c_algo_bit_data i2c_data;
198 struct i2c_client *hwmon_client, *ioexp_client;
199};
200
201/**
202 * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device
203 * @device_id: Controller's id for the device
204 * @size: Size (in bytes)
205 * @addr_len: Number of address bytes in read/write commands
206 * @munge_address: Flag whether addresses should be munged.
207 * Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
208 * use bit 3 of the command byte as address bit A8, rather
209 * than having a two-byte address. If this flag is set, then
210 * commands should be munged in this way.
211 * @erase_command: Erase command (or 0 if sector erase not needed).
212 * @erase_size: Erase sector size (in bytes)
213 * Erase commands affect sectors with this size and alignment.
214 * This must be a power of two.
215 * @block_size: Write block size (in bytes).
216 * Write commands are limited to blocks with this size and alignment.
217 */
218struct falcon_spi_device {
219 int device_id;
220 unsigned int size;
221 unsigned int addr_len;
222 unsigned int munge_address:1;
223 u8 erase_command;
224 unsigned int erase_size;
225 unsigned int block_size;
226};
227
228static inline bool falcon_spi_present(const struct falcon_spi_device *spi)
229{
230 return spi->size != 0;
231}
232
233enum {
234 FALCON_STAT_tx_bytes = GENERIC_STAT_COUNT,
235 FALCON_STAT_tx_packets,
236 FALCON_STAT_tx_pause,
237 FALCON_STAT_tx_control,
238 FALCON_STAT_tx_unicast,
239 FALCON_STAT_tx_multicast,
240 FALCON_STAT_tx_broadcast,
241 FALCON_STAT_tx_lt64,
242 FALCON_STAT_tx_64,
243 FALCON_STAT_tx_65_to_127,
244 FALCON_STAT_tx_128_to_255,
245 FALCON_STAT_tx_256_to_511,
246 FALCON_STAT_tx_512_to_1023,
247 FALCON_STAT_tx_1024_to_15xx,
248 FALCON_STAT_tx_15xx_to_jumbo,
249 FALCON_STAT_tx_gtjumbo,
250 FALCON_STAT_tx_non_tcpudp,
251 FALCON_STAT_tx_mac_src_error,
252 FALCON_STAT_tx_ip_src_error,
253 FALCON_STAT_rx_bytes,
254 FALCON_STAT_rx_good_bytes,
255 FALCON_STAT_rx_bad_bytes,
256 FALCON_STAT_rx_packets,
257 FALCON_STAT_rx_good,
258 FALCON_STAT_rx_bad,
259 FALCON_STAT_rx_pause,
260 FALCON_STAT_rx_control,
261 FALCON_STAT_rx_unicast,
262 FALCON_STAT_rx_multicast,
263 FALCON_STAT_rx_broadcast,
264 FALCON_STAT_rx_lt64,
265 FALCON_STAT_rx_64,
266 FALCON_STAT_rx_65_to_127,
267 FALCON_STAT_rx_128_to_255,
268 FALCON_STAT_rx_256_to_511,
269 FALCON_STAT_rx_512_to_1023,
270 FALCON_STAT_rx_1024_to_15xx,
271 FALCON_STAT_rx_15xx_to_jumbo,
272 FALCON_STAT_rx_gtjumbo,
273 FALCON_STAT_rx_bad_lt64,
274 FALCON_STAT_rx_bad_gtjumbo,
275 FALCON_STAT_rx_overflow,
276 FALCON_STAT_rx_symbol_error,
277 FALCON_STAT_rx_align_error,
278 FALCON_STAT_rx_length_error,
279 FALCON_STAT_rx_internal_error,
280 FALCON_STAT_rx_nodesc_drop_cnt,
281 FALCON_STAT_COUNT
282};
283
284/**
285 * struct falcon_nic_data - Falcon NIC state
286 * @pci_dev2: Secondary function of Falcon A
287 * @board: Board state and functions
288 * @stats: Hardware statistics
289 * @stats_disable_count: Nest count for disabling statistics fetches
290 * @stats_pending: Is there a pending DMA of MAC statistics.
291 * @stats_timer: A timer for regularly fetching MAC statistics.
292 * @spi_flash: SPI flash device
293 * @spi_eeprom: SPI EEPROM device
294 * @spi_lock: SPI bus lock
295 * @mdio_lock: MDIO bus lock
296 * @xmac_poll_required: XMAC link state needs polling
297 */
298struct falcon_nic_data {
299 struct pci_dev *pci_dev2;
300 struct falcon_board board;
301 u64 stats[FALCON_STAT_COUNT];
302 unsigned int stats_disable_count;
303 bool stats_pending;
304 struct timer_list stats_timer;
305 struct falcon_spi_device spi_flash;
306 struct falcon_spi_device spi_eeprom;
307 struct mutex spi_lock;
308 struct mutex mdio_lock;
309 bool xmac_poll_required;
310};
311
312static inline struct falcon_board *falcon_board(struct efx_nic *efx)
313{
314 struct falcon_nic_data *data = efx->nic_data;
315 return &data->board;
316}
317
318enum {
319 SIENA_STAT_tx_bytes = GENERIC_STAT_COUNT,
320 SIENA_STAT_tx_good_bytes,
321 SIENA_STAT_tx_bad_bytes,
322 SIENA_STAT_tx_packets,
323 SIENA_STAT_tx_bad,
324 SIENA_STAT_tx_pause,
325 SIENA_STAT_tx_control,
326 SIENA_STAT_tx_unicast,
327 SIENA_STAT_tx_multicast,
328 SIENA_STAT_tx_broadcast,
329 SIENA_STAT_tx_lt64,
330 SIENA_STAT_tx_64,
331 SIENA_STAT_tx_65_to_127,
332 SIENA_STAT_tx_128_to_255,
333 SIENA_STAT_tx_256_to_511,
334 SIENA_STAT_tx_512_to_1023,
335 SIENA_STAT_tx_1024_to_15xx,
336 SIENA_STAT_tx_15xx_to_jumbo,
337 SIENA_STAT_tx_gtjumbo,
338 SIENA_STAT_tx_collision,
339 SIENA_STAT_tx_single_collision,
340 SIENA_STAT_tx_multiple_collision,
341 SIENA_STAT_tx_excessive_collision,
342 SIENA_STAT_tx_deferred,
343 SIENA_STAT_tx_late_collision,
344 SIENA_STAT_tx_excessive_deferred,
345 SIENA_STAT_tx_non_tcpudp,
346 SIENA_STAT_tx_mac_src_error,
347 SIENA_STAT_tx_ip_src_error,
348 SIENA_STAT_rx_bytes,
349 SIENA_STAT_rx_good_bytes,
350 SIENA_STAT_rx_bad_bytes,
351 SIENA_STAT_rx_packets,
352 SIENA_STAT_rx_good,
353 SIENA_STAT_rx_bad,
354 SIENA_STAT_rx_pause,
355 SIENA_STAT_rx_control,
356 SIENA_STAT_rx_unicast,
357 SIENA_STAT_rx_multicast,
358 SIENA_STAT_rx_broadcast,
359 SIENA_STAT_rx_lt64,
360 SIENA_STAT_rx_64,
361 SIENA_STAT_rx_65_to_127,
362 SIENA_STAT_rx_128_to_255,
363 SIENA_STAT_rx_256_to_511,
364 SIENA_STAT_rx_512_to_1023,
365 SIENA_STAT_rx_1024_to_15xx,
366 SIENA_STAT_rx_15xx_to_jumbo,
367 SIENA_STAT_rx_gtjumbo,
368 SIENA_STAT_rx_bad_gtjumbo,
369 SIENA_STAT_rx_overflow,
370 SIENA_STAT_rx_false_carrier,
371 SIENA_STAT_rx_symbol_error,
372 SIENA_STAT_rx_align_error,
373 SIENA_STAT_rx_length_error,
374 SIENA_STAT_rx_internal_error,
375 SIENA_STAT_rx_nodesc_drop_cnt,
376 SIENA_STAT_COUNT
377};
378
379/**
380 * struct siena_nic_data - Siena NIC state
381 * @efx: Pointer back to main interface structure
382 * @wol_filter_id: Wake-on-LAN packet filter id
383 * @stats: Hardware statistics
384 * @vf: Array of &struct siena_vf objects
385 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
386 * @vfdi_status: Common VFDI status page to be dmad to VF address space.
387 * @local_addr_list: List of local addresses. Protected by %local_lock.
388 * @local_page_list: List of DMA addressable pages used to broadcast
389 * %local_addr_list. Protected by %local_lock.
390 * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
391 * @peer_work: Work item to broadcast peer addresses to VMs.
392 */
393struct siena_nic_data {
394 struct efx_nic *efx;
395 int wol_filter_id;
396 u64 stats[SIENA_STAT_COUNT];
397#ifdef CONFIG_SFC_SRIOV
398 struct siena_vf *vf;
399 struct efx_channel *vfdi_channel;
400 unsigned vf_buftbl_base;
401 struct efx_buffer vfdi_status;
402 struct list_head local_addr_list;
403 struct list_head local_page_list;
404 struct mutex local_lock;
405 struct work_struct peer_work;
406#endif
407};
408
409enum {
410 EF10_STAT_port_tx_bytes = GENERIC_STAT_COUNT,
411 EF10_STAT_port_tx_packets,
412 EF10_STAT_port_tx_pause,
413 EF10_STAT_port_tx_control,
414 EF10_STAT_port_tx_unicast,
415 EF10_STAT_port_tx_multicast,
416 EF10_STAT_port_tx_broadcast,
417 EF10_STAT_port_tx_lt64,
418 EF10_STAT_port_tx_64,
419 EF10_STAT_port_tx_65_to_127,
420 EF10_STAT_port_tx_128_to_255,
421 EF10_STAT_port_tx_256_to_511,
422 EF10_STAT_port_tx_512_to_1023,
423 EF10_STAT_port_tx_1024_to_15xx,
424 EF10_STAT_port_tx_15xx_to_jumbo,
425 EF10_STAT_port_rx_bytes,
426 EF10_STAT_port_rx_bytes_minus_good_bytes,
427 EF10_STAT_port_rx_good_bytes,
428 EF10_STAT_port_rx_bad_bytes,
429 EF10_STAT_port_rx_packets,
430 EF10_STAT_port_rx_good,
431 EF10_STAT_port_rx_bad,
432 EF10_STAT_port_rx_pause,
433 EF10_STAT_port_rx_control,
434 EF10_STAT_port_rx_unicast,
435 EF10_STAT_port_rx_multicast,
436 EF10_STAT_port_rx_broadcast,
437 EF10_STAT_port_rx_lt64,
438 EF10_STAT_port_rx_64,
439 EF10_STAT_port_rx_65_to_127,
440 EF10_STAT_port_rx_128_to_255,
441 EF10_STAT_port_rx_256_to_511,
442 EF10_STAT_port_rx_512_to_1023,
443 EF10_STAT_port_rx_1024_to_15xx,
444 EF10_STAT_port_rx_15xx_to_jumbo,
445 EF10_STAT_port_rx_gtjumbo,
446 EF10_STAT_port_rx_bad_gtjumbo,
447 EF10_STAT_port_rx_overflow,
448 EF10_STAT_port_rx_align_error,
449 EF10_STAT_port_rx_length_error,
450 EF10_STAT_port_rx_nodesc_drops,
451 EF10_STAT_port_rx_pm_trunc_bb_overflow,
452 EF10_STAT_port_rx_pm_discard_bb_overflow,
453 EF10_STAT_port_rx_pm_trunc_vfifo_full,
454 EF10_STAT_port_rx_pm_discard_vfifo_full,
455 EF10_STAT_port_rx_pm_trunc_qbb,
456 EF10_STAT_port_rx_pm_discard_qbb,
457 EF10_STAT_port_rx_pm_discard_mapping,
458 EF10_STAT_port_rx_dp_q_disabled_packets,
459 EF10_STAT_port_rx_dp_di_dropped_packets,
460 EF10_STAT_port_rx_dp_streaming_packets,
461 EF10_STAT_port_rx_dp_hlb_fetch,
462 EF10_STAT_port_rx_dp_hlb_wait,
463 EF10_STAT_rx_unicast,
464 EF10_STAT_rx_unicast_bytes,
465 EF10_STAT_rx_multicast,
466 EF10_STAT_rx_multicast_bytes,
467 EF10_STAT_rx_broadcast,
468 EF10_STAT_rx_broadcast_bytes,
469 EF10_STAT_rx_bad,
470 EF10_STAT_rx_bad_bytes,
471 EF10_STAT_rx_overflow,
472 EF10_STAT_tx_unicast,
473 EF10_STAT_tx_unicast_bytes,
474 EF10_STAT_tx_multicast,
475 EF10_STAT_tx_multicast_bytes,
476 EF10_STAT_tx_broadcast,
477 EF10_STAT_tx_broadcast_bytes,
478 EF10_STAT_tx_bad,
479 EF10_STAT_tx_bad_bytes,
480 EF10_STAT_tx_overflow,
481 EF10_STAT_COUNT
482};
483
484/* Maximum number of TX PIO buffers we may allocate to a function.
485 * This matches the total number of buffers on each SFC9100-family
486 * controller.
487 */
488#define EF10_TX_PIOBUF_COUNT 16
489
490/**
491 * struct efx_ef10_nic_data - EF10 architecture NIC state
492 * @mcdi_buf: DMA buffer for MCDI
493 * @warm_boot_count: Last seen MC warm boot count
494 * @vi_base: Absolute index of first VI in this function
495 * @n_allocated_vis: Number of VIs allocated to this function
496 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
497 * @must_restore_filters: Flag: filters have yet to be restored after MC reboot
498 * @n_piobufs: Number of PIO buffers allocated to this function
499 * @wc_membase: Base address of write-combining mapping of the memory BAR
500 * @pio_write_base: Base address for writing PIO buffers
501 * @pio_write_vi_base: Relative VI number for @pio_write_base
502 * @piobuf_handle: Handle of each PIO buffer allocated
503 * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC
504 * reboot
505 * @rx_rss_context: Firmware handle for our RSS context
506 * @rx_rss_context_exclusive: Whether our RSS context is exclusive or shared
507 * @stats: Hardware statistics
508 * @workaround_35388: Flag: firmware supports workaround for bug 35388
509 * @workaround_26807: Flag: firmware supports workaround for bug 26807
510 * @must_check_datapath_caps: Flag: @datapath_caps needs to be revalidated
511 * after MC reboot
512 * @datapath_caps: Capabilities of datapath firmware (FLAGS1 field of
513 * %MC_CMD_GET_CAPABILITIES response)
514 * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU
515 * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU
516 * @vport_id: The function's vport ID, only relevant for PFs
517 * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot
518 * @pf_index: The number for this PF, or the parent PF if this is a VF
519#ifdef CONFIG_SFC_SRIOV
520 * @vf: Pointer to VF data structure
521#endif
522 */
523struct efx_ef10_nic_data {
524 struct efx_buffer mcdi_buf;
525 u16 warm_boot_count;
526 unsigned int vi_base;
527 unsigned int n_allocated_vis;
528 bool must_realloc_vis;
529 bool must_restore_filters;
530 unsigned int n_piobufs;
531 void __iomem *wc_membase, *pio_write_base;
532 unsigned int pio_write_vi_base;
533 unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT];
534 bool must_restore_piobufs;
535 u32 rx_rss_context;
536 bool rx_rss_context_exclusive;
537 u64 stats[EF10_STAT_COUNT];
538 bool workaround_35388;
539 bool workaround_26807;
540 bool must_check_datapath_caps;
541 u32 datapath_caps;
542 unsigned int rx_dpcpu_fw_id;
543 unsigned int tx_dpcpu_fw_id;
544 unsigned int vport_id;
545 bool must_probe_vswitching;
546 unsigned int pf_index;
547 u8 port_id[ETH_ALEN];
548#ifdef CONFIG_SFC_SRIOV
549 unsigned int vf_index;
550 struct ef10_vf *vf;
551#endif
552 u8 vport_mac[ETH_ALEN];
553};
554
555int efx_init_sriov(void);
556void efx_fini_sriov(void);
557
558struct ethtool_ts_info;
559int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel);
560void efx_ptp_defer_probe_with_channel(struct efx_nic *efx);
561void efx_ptp_remove(struct efx_nic *efx);
562int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr);
563int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr);
564void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info);
565bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
566int efx_ptp_get_mode(struct efx_nic *efx);
567int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted,
568 unsigned int new_mode);
569int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
570void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
571size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings);
572size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats);
573void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev);
574void __efx_rx_skb_attach_timestamp(struct efx_channel *channel,
575 struct sk_buff *skb);
576static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel,
577 struct sk_buff *skb)
578{
579 if (channel->sync_events_state == SYNC_EVENTS_VALID)
580 __efx_rx_skb_attach_timestamp(channel, skb);
581}
582void efx_ptp_start_datapath(struct efx_nic *efx);
583void efx_ptp_stop_datapath(struct efx_nic *efx);
584
585extern const struct efx_nic_type falcon_a1_nic_type;
586extern const struct efx_nic_type falcon_b0_nic_type;
587extern const struct efx_nic_type siena_a0_nic_type;
588extern const struct efx_nic_type efx_hunt_a0_nic_type;
589extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;
590
591/**************************************************************************
592 *
593 * Externs
594 *
595 **************************************************************************
596 */
597
598int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
599
600/* TX data path */
601static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
602{
603 return tx_queue->efx->type->tx_probe(tx_queue);
604}
605static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
606{
607 tx_queue->efx->type->tx_init(tx_queue);
608}
609static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
610{
611 tx_queue->efx->type->tx_remove(tx_queue);
612}
613static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
614{
615 tx_queue->efx->type->tx_write(tx_queue);
616}
617
618/* RX data path */
619static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
620{
621 return rx_queue->efx->type->rx_probe(rx_queue);
622}
623static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
624{
625 rx_queue->efx->type->rx_init(rx_queue);
626}
627static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
628{
629 rx_queue->efx->type->rx_remove(rx_queue);
630}
631static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
632{
633 rx_queue->efx->type->rx_write(rx_queue);
634}
635static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
636{
637 rx_queue->efx->type->rx_defer_refill(rx_queue);
638}
639
640/* Event data path */
641static inline int efx_nic_probe_eventq(struct efx_channel *channel)
642{
643 return channel->efx->type->ev_probe(channel);
644}
645static inline int efx_nic_init_eventq(struct efx_channel *channel)
646{
647 return channel->efx->type->ev_init(channel);
648}
649static inline void efx_nic_fini_eventq(struct efx_channel *channel)
650{
651 channel->efx->type->ev_fini(channel);
652}
653static inline void efx_nic_remove_eventq(struct efx_channel *channel)
654{
655 channel->efx->type->ev_remove(channel);
656}
657static inline int
658efx_nic_process_eventq(struct efx_channel *channel, int quota)
659{
660 return channel->efx->type->ev_process(channel, quota);
661}
662static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
663{
664 channel->efx->type->ev_read_ack(channel);
665}
666void efx_nic_event_test_start(struct efx_channel *channel);
667
668/* Falcon/Siena queue operations */
669int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
670void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
671void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
672void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
673void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
674int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
675void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
676void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
677void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
678void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
679void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
680int efx_farch_ev_probe(struct efx_channel *channel);
681int efx_farch_ev_init(struct efx_channel *channel);
682void efx_farch_ev_fini(struct efx_channel *channel);
683void efx_farch_ev_remove(struct efx_channel *channel);
684int efx_farch_ev_process(struct efx_channel *channel, int quota);
685void efx_farch_ev_read_ack(struct efx_channel *channel);
686void efx_farch_ev_test_generate(struct efx_channel *channel);
687
688/* Falcon/Siena filter operations */
689int efx_farch_filter_table_probe(struct efx_nic *efx);
690void efx_farch_filter_table_restore(struct efx_nic *efx);
691void efx_farch_filter_table_remove(struct efx_nic *efx);
692void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
693s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,
694 bool replace);
695int efx_farch_filter_remove_safe(struct efx_nic *efx,
696 enum efx_filter_priority priority,
697 u32 filter_id);
698int efx_farch_filter_get_safe(struct efx_nic *efx,
699 enum efx_filter_priority priority, u32 filter_id,
700 struct efx_filter_spec *);
701int efx_farch_filter_clear_rx(struct efx_nic *efx,
702 enum efx_filter_priority priority);
703u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
704 enum efx_filter_priority priority);
705u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
706s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
707 enum efx_filter_priority priority, u32 *buf,
708 u32 size);
709#ifdef CONFIG_RFS_ACCEL
710s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
711 struct efx_filter_spec *spec);
712bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
713 unsigned int index);
714#endif
715void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
716
717bool efx_nic_event_present(struct efx_channel *channel);
718
719/* Some statistics are computed as A - B where A and B each increase
720 * linearly with some hardware counter(s) and the counters are read
721 * asynchronously. If the counters contributing to B are always read
722 * after those contributing to A, the computed value may be lower than
723 * the true value by some variable amount, and may decrease between
724 * subsequent computations.
725 *
726 * We should never allow statistics to decrease or to exceed the true
727 * value. Since the computed value will never be greater than the
728 * true value, we can achieve this by only storing the computed value
729 * when it increases.
730 */
731static inline void efx_update_diff_stat(u64 *stat, u64 diff)
732{
733 if ((s64)(diff - *stat) > 0)
734 *stat = diff;
735}
736
737/* Interrupts */
738int efx_nic_init_interrupt(struct efx_nic *efx);
739void efx_nic_irq_test_start(struct efx_nic *efx);
740void efx_nic_fini_interrupt(struct efx_nic *efx);
741
742/* Falcon/Siena interrupts */
743void efx_farch_irq_enable_master(struct efx_nic *efx);
744void efx_farch_irq_test_generate(struct efx_nic *efx);
745void efx_farch_irq_disable_master(struct efx_nic *efx);
746irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
747irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
748irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
749
750static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
751{
752 return ACCESS_ONCE(channel->event_test_cpu);
753}
754static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
755{
756 return ACCESS_ONCE(efx->last_irq_cpu);
757}
758
759/* Global Resources */
760int efx_nic_flush_queues(struct efx_nic *efx);
761void siena_prepare_flush(struct efx_nic *efx);
762int efx_farch_fini_dmaq(struct efx_nic *efx);
763void efx_farch_finish_flr(struct efx_nic *efx);
764void siena_finish_flush(struct efx_nic *efx);
765void falcon_start_nic_stats(struct efx_nic *efx);
766void falcon_stop_nic_stats(struct efx_nic *efx);
767int falcon_reset_xaui(struct efx_nic *efx);
768void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
769void efx_farch_init_common(struct efx_nic *efx);
770void efx_ef10_handle_drain_event(struct efx_nic *efx);
771void efx_farch_rx_push_indir_table(struct efx_nic *efx);
772
773int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
774 unsigned int len, gfp_t gfp_flags);
775void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
776
777/* Tests */
778struct efx_farch_register_test {
779 unsigned address;
780 efx_oword_t mask;
781};
782int efx_farch_test_registers(struct efx_nic *efx,
783 const struct efx_farch_register_test *regs,
784 size_t n_regs);
785
786size_t efx_nic_get_regs_len(struct efx_nic *efx);
787void efx_nic_get_regs(struct efx_nic *efx, void *buf);
788
789size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
790 const unsigned long *mask, u8 *names);
791void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
792 const unsigned long *mask, u64 *stats,
793 const void *dma_buf, bool accumulate);
794void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat);
795
796#define EFX_MAX_FLUSH_TIME 5000
797
798void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
799 efx_qword_t *event);
800
801#endif /* EFX_NIC_H */